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IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09 / 01 / 2011 1 high voltage led lighting driver with switch dimming general description IS31LT3918 led driver ic is a peak current detection buck converter which operates in constant off time mode. it operates over a very wide input voltage supply range of 6vdc to 450vdc or 110vac/220vac. IS31LT3918 incorporates the special feature of switch dimming by detecting off-on cycles of the main power switch. when the switch is cycled within a 2 second period (typical) the device automatically switches the dimming level to the next step. as a result, dimming can be achieved without replacing any wiring in the original system. there are multiple modes of switch dimming that the user may configure 2 steps or 3 steps, as well as different levels of dimming via the external pins dim1 and dim2. IS31LT3918 can also realize led dimming using an external pwm signal. it can accept a pwm signal from 0% to 100% duty cycle. the led current may also be adjusted linearly by applying an analog input voltage in the range of 0.5v to 2.5v. IS31LT3918 adopts a peak current mode control architecture, which eliminates the need for any additional loop compensation while maintaining a good degree of constant output current regulation. features ? user configurable switch dimming levels ? 3% output current accuracy ? over current, voltage and temperature protection ? high efficiency (typical up to 95%) ? wide input voltage range: 6vdc~450vdc or 85vac~ 265vac ? linear and pwm dimming ? very few external components applications ? dc/dc or ac/dc constant current led driver ? signal and decorative lighting ? backlight led driver typical application circuit is3918 gate cs adj toff vin dim1 dim2 gnd fuse 85vac- 265vac led+ led- r3 r4 q1 q2 c4 c6 r2 d6 dz c2 r1 c1 r5 d5 l1 c3 d1 d2 d3 d4 switch k r6 copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances IS31LT3918 october 2011
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 2 pin configuration package pin configurations sop-8 pin description pin name pin number description dim1 1 these two pins configure the dimming levels as follows: dim1=?floating?dim2=?floating?, no dimming (100% only) dim1=?floating?dim2=?gnd? , 100%-30%-100% dim1=?gnd?dim2=?floating?, 100%-50%-100% dim1=?gnd?dim2=?gnd?, 100%-50%-20%-100% dim2 2 adj 3 linear and pwm dimming input pin. linear dimming range: 0.5v to 2.5v. if v adj < 0.5v, gate output is off. if 0.5v v adj 2.5v, v csth = v adj /10. if v adj > 2.5v, v csth = 0.25v. when this pin is floating, there is an internal pull up to 4.5v (typical) and v csth = 0.25v. pwm dimming frequency range: 200hz -1khz. gnd 4 ground pin. all internal currents return through this pin. gate 5 this pin connects to the external nmos?s gate cs 6 current detect pin, uses an external resistor to sense the peak inductor current. to ff 7 this pin sets the off time for the switch by connecting a resistor between this pin and gnd. vin 8 8v ? 450v supply voltage is connected to this pin via an external resistor. it is internally clamped and must be bypassed using a capacitor to gnd. ordering information industrial range: -40c to +85c order part no. package qty/reel IS31LT3918?grls2-tr sop-8, lead-free 2500
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 3 absolute maximum ratings parameter range unit vin pin to gnd -0.3 ? 6.0 v dim1,dim2,cs, adj, gate, toff pin to gnd -0.3 - 6.0 v vin pin input current (note1) 10 ma junction temperature -40 ? 150 device storage temperature -65 - 150 esd human body model 3500 v stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditio ns is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. electrical characteristics (the specifications are at ta=25c and vindc=10v (note 2), rin =10k, unless otherwise noted) symbol parameter conditions min typ max unit v clamp vin pin clamp voltage supply voltage connected to vin via an appropriate resistor 4.3 5 5.5 v uvlo undervoltage lockout vin rising 4.8 v uvlo uvlo hysteresis 400 mv i in quiescent current vin=5v 300 400 ua i in,uv input current in uvlo vin=4v 90 120 ua v csth current sense threshold adj=5v 245 250 255 mv t blank current sense blanking time v cs =v csth +50mv 445 500 650 ns t off off time r ext =250k ? 9.8 10 10.2 us v adj (note 3) pwm input voltage high threshold 2.5 v pwm input voltage low threshold 0.25 0.5 0.75 v linear dimming input voltage range 0.5 2.5 v i source gate source current gate=0 75 90 ma i sink gate sink current gate=5v 75 90 ma t p over temperature protection threshold 150 o c t p over temperature protection hysteresis 20 o c v ocp over current protection cs voltage threshold adj=5v,cs rising 0.35 0.4 0.45 v t off_reset over current protection toff delay time 500 us t max maximum switch off time for switch dimming 2 s notes: 1. beyond the input current range, vin pin may not clamp at 5v. 2. vin is the input voltage. when vin>5v, input voltage connected to vin pin should via a appropriate resistor. 3. when v adj >2.5v, i out is 100% output current. when v adj <0.5v, i out is shutdown. when 0.5v v adj 2.5v, i out is linear dimming .
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 4 application information IS31LT3918 is a peak current control led driver ic. it does not require any high side current sensing or the design of any closed loop control, but provides a very accurate constant led driving current. IS31LT3918 includes an dimming input allowing either a pwm or an analog dimming signal. an external resistor connected to the toff pin determines the internal oscillator?s constant off time. the off time adds to the on time, controlled by the internal switching control logic, to set the oscillation frequency. the inductor current increases when the switch is on. this current also flows through the external current sense resistor r cs , and when the voltage across r cs reaches the current sense threshold, v csth or 1/10 of the adj input voltage, whichever is lower, the switch turns off. the current through the inductor will continue to flow through the leds, but will decrease linearly during the switch off time. after the programmed off-time, the switch will turn on again. a short blanking time of 500ns (typical) is implemented to block the voltage spike encountered across r cs , caused by the parasitic capacitance of the switch discharging. after the blanking time the control logic again compares the cs input voltage to the current sense threshold. choose the acceptable level of ripple current, k then calculate the value of the current sense resistor: led csth cs i k v r ) 2 / 1 ( ? ? v csth : if v adj < 0.5v, gate output is off. if 0.5v v adj 2.5v, v csth = v adj /10. if v adj > 2.5v, v csth = 0.25v. when adj pin is floating, there is an internal pull up to 4.5v (typical) and v csth = 0.25v. k: acceptable current ripple, the recommended value range is 1~1.8. a constant off-time peak current control scheme can easily operate at duty cycles greater than 0.5 and also gives inherent input voltage rejection making the led current almost insensitive to input voltage variations. input voltage regulation the vin pin is internally clamped at 5v (typical). when supplying a voltage larger than 5v, an external resistor must be used between the input voltage and the vin pin. bypass the vin pin using a low esr capacitor to provide a high frequency path to gnd. the current required by the device is 0.3ma plus the switching current of the external switch. the switching frequency of the external nmos affects the amount of current required, as does the nmos?s gate charge requirement (found on the nmos data sheet). s g in f q ma i ? ? ? 3 . 0 in the above equation, f s is the switching frequency, q g is the external nmos gate charge (from the nmos datasheet). current detection the voltage input to the cs pin is provided to two internal comparators. one of the comparators uses a fixed 250mv reference, while the other uses a scaled value of the adj pin voltage as reference. the outputs of the comparators are ored, thus causing the lower of the two thresholds to trigger the switch control logic. at the moment the switch control logic changes the gate signal to low, the toff timer is started. the external switch will remain off for the length of time programmed, and once the toff time is expired, the switch control logic again toggles the gate signal, this time from low to high, and the external switch turns on. as the external switch turns on, the parasitic capacitance on the drain of the switch must discharge through the switch channel causing a spike of current which can be quite large, but only lasts for a very short period of time. to prevent this current from causing a false trip of the current sense comparators, the signal is blocked from the internal comparators for 500ns (typical). in some special cases, the 500ns blanking time may not be sufficient to prevent false triggering of the cs threshold logic. under these circumstances, an additional rc filter may be added to the cs input pin to help filter out the voltage spike. carefully layout of the pcb to minimize parasitic capacitance, trace resistance and inductance greatly aids in the elimination of false triggering.
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 5 oscillator IS31LT3918?s toff pin controls the off time of the internal oscillator. oscillator off time is determined by the following equation: ext r s toff ? ? ? ? 12 10 40 ) ( r ext resistor connected between toff and gnd switch dimming IS31LT3918 detects the external switch action of the main power switch, and can automatically adjust the level of the output current based on the action of the main power switch. the action of the external power switch can be divided into two types. the first is ?normal switch operation? in which the switch is toggled from on to off, remaining off for longer than 2 seconds (typical). the second is ?switch dimming action? in which the switch is toggled from on to off and back on within 2 seconds (typical). when the device is in normal switch operation, it merely powers on in the first state when the power switch is toggled to on, and the device turns off when the external power switch is changed to off. switch dimming output current levels are configured by connecting the dim1 and dim2 pins as indicated in the table below dim1 dim2 dimming levels floating floating no dimming floating gnd 2 levels 100%-30%-100% gnd floating 2 levels 100%-50%-100% gnd gnd 3 levels 100%-50%-20%-100% when operating in switch dimming mode, normally the device will always power up at 100% output current. the operation of the power switch and the configuration of the dim1 and dim2 pins control the dimming process as follows 1. when dim1 and dim2 pins are both floating, there is no switch dimming, and the output current is 100% of the programmed value when the power is on. 2. when dim1 is floating and dim2 is gnd, the output current is a) 100% at power on. b) the first switch dimming action causes the current to change to 30%. c) a second switch dimming action causes the current to return to 100%. d) a third switch dimming action has the same effect as the first switch dimming action. e) subsequent switch dimming actions causes the cycle to continue. 3. when dim1 is gnd and dim2 is floating, the dimming sequence is as described in (2) above, except that the current sequence is 100%-50%-100%. 4. when both dim1 and dim2 are connected to gnd, the dimming sequence is as described in (2) above, except that the current sequence is 100%-50%-20%-100%. if the switch is operated normally, that is, switched on once after being in the off position for a long time, or if both the dim1 and dim2 pins are floating, then the output current always starts up at the initial value of 100%. note: because the main power switch is used to initiate the switch dimming function, the device must have a large enough external capacitor on vin to maintain device operation for 2 seconds. please refer to the applications examples for specific values. linear dimming an external voltage, 0.5v to 2.5v, connected to the adj pin can adjust the led current. two possible situations might be used are if it is not possible to change the value of r cs to obtain the desired value of led current, an external voltage reference can be connected to the adj pin to adjust the voltage sense level across r cs , equivalent to changing the value of r cs . connecting a resistor between the vin and adj pin, then connecting a thermistor from the adj pin to gnd can adjust the led current based on temperature, thus realizing the temperature compensation feature.
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 6 pwm dimming pwm dimming may be realized by applying a low frequency pwm waveform to the adj pin. when the pwm signal is low, less than 0.5v, the IS31LT3918 remains off when the pwm signal is high, greater than 2.5v, the driver is enabled and operates normally. the pwm signal does not shut down the other circuit blocks of the device, thus the response to the pwm signal is relatively fast, and primarily determined by the rise and fall time of the inductor current. to disable pwm dimming, just leave the adj pin not connected.
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 7 application example dc input voltage inac v =220v output vo=40v 12, 1w leds in series, vf=3.3v i led =0.35a 1. vin power supply circuit refer to the typical application circuit. the circuit consists of r1, c2, dz, r5, q1, q2, d6, r2, c4, c6. r1, c2 and dz, provide a steady, approximately 12v to the gate of q2. mos q2 starts in conduction state, and begins to charge c4 via r2 and d6. when vin reaches about 5v, the device starts to operate. component parameters: r1=0.5m ? , c1=22uf, c2=10uf, dz=12v, d6=ss16, r2=3k ? , c4=10uf, c6=10uf, r5=150 ? 2. off time t off off time is given by ext r s toff ? ? ? ? 12 10 40 ) ( to decide the off time, assume the desired switching frequency is 50khz, and the duty cycle is 18.2% (the duty cycle is decided by the ratio of the output voltage and input voltage), then toff is 16.36us, r ext =409k ? ? =r3 to ff = 15 . 6u s . 3. current sense resistor r cs the current sense resistor is given by 4 ) 2 / 1 ( r i k v r led csth cs ? ? ? k is the ripple current coefficient. assuming a typical value for k of 1.8, r cs =0.376 ? , choose r cs =0.38 ? 4. inductor l1 the inductance of inductor l1 is dependent on the led current, in this case 350ma. we have already chosen toff=15.6us, thus: mh i k t v i t v l led off o ripple off o 1 35 . 0 8 . 1 10 6 . 15 40 6 ? ? ? ? ? ? ? ? ? ? ? where, i ripple is the design target for ripple current. 5. freewheeling diode (d5) and nmos (q1, q2) choose q2 to have a voltage rating at least as large as the maximum input voltage with approximately 50% margin. v fet =1.5 v indc the current through the nmos is based on the peak led current, choose fet current rating with 50% margin. i fet = i peak * 150% thus, select 600v, 2a, nmos, such as: 2n60 q1 peak voltage is dependent on the dc input voltage to the device. the recommended nmos is ap2306 (30v, 5a). the diode ratings are equal to that of the nmos, q2. note: the diode must be a superfast recovery diode and the reverse recovery time(t rr ) should be less than 50ns. thus, select 600v, 1a, superfast recovery diode, such as: es1j
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09 / 01 / 2011 8 appendix: typical application circuit of dc vo ltage input using a single external nmos is3918 gate cs adj toff vin dim1 dim2 gnd led+ led- roff rcs q1 cin rin d1 l1 cout vin dc 6-150v cin note: in the above configuration, it is important to pay attention to the vgson value for q1. IS31LT3918 provides a maximum gate d rive of 4.5v (typ), thus requiring that a low threshold voltage nmos be used. IS31LT3918
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09 / 01 / 2011 9 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. classification profile
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09 / 01 / 2011 10 tape and reel information
IS31LT3918 integrated silicon solution, inc. ? www.issi.com rev. a, 09/01/2011 11 package information sop-8 3 d f n d j h 2 x w o l q h ' u d z l q j ' % 6 &

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