View M24LR64-R_4649760.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

april 2010 doc id 15170 rev 9 1/126 1 M24LR64-R 64 kbit eeprom with password protection & dual interface: 400 khz i2c serial bus & iso 1 5693 rf protocol at 13.56 mhz features i2c interface two-wire i 2 c serial interface supports 400 khz protocol single supply voltage: ? 1.8 v to 5.5 v byte and page write (up to 4 bytes) random and sequential read modes self-timed programming cycle automatic address incrementing enhanced esd/latch-up protection contactless interface iso 15693 and iso 18000-3 mode 1 compliant 13.56 mhz 7k hz carrier frequency to tag: 10% or 100% ask modulation using 1/4 (26 kbit/s) or 1/256 (1.6 kbit/s) pulse position coding from tag: load modulation using manchester coding with 423 khz and 484 khz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. supports the 53 kbit/s data rate with fast commands internal tuning capacitance: 27.5 pf 64-bit unique identifier (uid) read block & write (32-bit blocks) memory 64 kbit eeprom organized into: ? 8192 bytes in i2c mode ? 2048 blocks of 32 bits in rf mode write time ? i2c: 5 ms (max.) ? rf: 5.75 ms including the internal verify time more than 1 million write cycles in i 2 c mode more than 100 000 wr ite cycles in rf mode multiple password pr otection in rf mode single password protection in i 2 c mode more than 40-year data retention package ? ecopack2 ? (rohs compliant and halogen-free) so8 (mn) 150 mils width ufdfpn8 (mb) 2 3 mm tssop8 (dw) www.st.com
contents M24LR64-R 2/126 doc id 15170 rev 9 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 chip enable (e0, e1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 antenna coil (ac0, ac1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.1 operating supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.2 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.3 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.4 power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 user memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 system memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 M24LR64-R rf block security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 example of the M24LR64-R security protection . . . . . . . . . . . . . . . . . . . . 24 4.3 i2c_write_lock bit area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5 M24LR64-R i 2 c password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5.1 i 2 c present password command description . . . . . . . . . . . . . . . . . . . . 26 4.5.2 i 2 c write password command description . . . . . . . . . . . . . . . . . . . . . . 27 5i 2 c device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 acknowledge bit (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.4 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.5 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.6 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.7 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M24LR64-R contents doc id 15170 rev 9 3/126 5.8 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.9 minimizing system delays by polling on ack . . . . . . . . . . . . . . . . . . . . . . 33 5.10 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.11 random address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.12 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.13 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.14 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 user memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7 rf device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.1 power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.2 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.2.3 operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 communication signal from vcd to M24LR64-R . . . . . . . . . . . . . . . . . 39 9 data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.2 data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.3 vcd to M24LR64-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.4 start of frame (sof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10 communications signal from M24LR64-R to vcd . . . . . . . . . . . . . . . . 46 10.1 load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.2 subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.3 data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1 bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1.1 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11.1.2 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11.3 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
contents M24LR64-R 4/126 doc id 15170 rev 9 11.4 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 M24LR64-R to vcd frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 sof when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.2 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.3 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.4 sof when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.5 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.6 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.7 eof when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.8 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.9 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.10 eof when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.11 high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.12 low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13 unique identifier (uid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14 application family identifier (a fi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 15 data storage format identifier (dsfid) . . . . . . . . . . . . . . . . . . . . . . . . . 56 15.1 crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 16 M24LR64-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 17 M24LR64-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17.1 power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17.2 ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17.3 quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 17.4 selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 18 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 18.1 addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 18.2 non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 61 18.3 select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
M24LR64-R contents doc id 15170 rev 9 5/126 19 request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 19.1 request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 20 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.1 response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 20.2 response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 21 anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 21.1 request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 22 request processing by the m24lr 64-r . . . . . . . . . . . . . . . . . . . . . . . . 68 23 explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 24 inventory initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 25 timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25.1 t1: M24LR64-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25.2 t2: vcd new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 25.3 t 3 : vcd new request delay in the absence of a response from the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 26 commands codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 26.1 inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 26.2 stay quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 26.3 read single block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 26.4 write single block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 26.5 read multiple block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.6 select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 26.7 reset to ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 26.8 write afi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 26.9 lock afi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 26.10 write dsfid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 26.11 lock dsfid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 26.12 get system info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 26.13 get multiple block security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
contents M24LR64-R 6/126 doc id 15170 rev 9 26.14 write-sector password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 26.15 lock-sector password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 26.16 present-sector password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 26.17 fast read single block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 26.18 fast inventory initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 26.19 fast initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 26.20 fast read multiple block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 26.21 inventory initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 26.22 initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 27 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 28 i 2 c dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 29 rf dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 31 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 appendix a anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 121 a.1 algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 appendix b crc (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 b.1 crc error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 b.2 crc calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 appendix c application family identifier (afi) (informative) . . . . . . . . . . . . . . 124 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
M24LR64-R list of tables doc id 15170 rev 9 7/126 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 3. address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 8. read / write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. M24LR64-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. M24LR64-R sector security protection after a valid presentation of password 1 . . . . . . . . 24 table 13. i2c_write_lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. system parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 16. 10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 17. response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. uid format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. crc transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 20. vcd request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 21. M24LR64-R response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 22. M24LR64-R response depending on request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. general request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24. definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25. request flags 5 to 8 when bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 26. request flags 5 to 8 when bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 27. general response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 28. definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 29. response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 30. inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 31. example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 32. timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 33. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 34. inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 35. inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 36. stay quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 37. read single block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 38. read single block response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . 76 table 39. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 40. read single block response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 76 table 41. write single block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 42. write single block response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . 78 table 43. write single block response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 78 table 44. read multiple block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 45. read multiple block response format when error_flag is not set. . . . . . . . . . . . . . . . . . . 80 table 46. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 47. read multiple block response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 81 table 48. select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
list of tables M24LR64-R 8/126 doc id 15170 rev 9 table 49. select block response format when error_flag is not set. . . . . . . . . . . . . . . . . . . . . . . . . 82 table 50. select response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 51. reset to ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 52. reset to ready response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . 83 table 53. reset to ready response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 54. write afi request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 55. write afi response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 56. write afi response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 57. lock afi request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 58. lock afi response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 59. lock afi response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 60. write dsfid request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 61. write dsfid response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . 88 table 62. write dsfid response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 63. lock dsfid request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 64. lock dsfid response format when error_flag is not set . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 65. lock dsfid response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 66. get system info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 67. get system info response format when error_flag is not set. . . . . . . . . . . . . . . . . . . . . . 92 table 68. get system info response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 69. get multiple block security status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 70. get multiple block security status response format when error_flag is not set . . . . . . . 94 table 71. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 72. get multiple block security status response format when error_flag is set . . . . . . . . . . . . 95 table 73. write-sector password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 74. write-sector password response format when error_flag is not set . . . . . . . . . . . . . . . . 96 table 75. write-sector password response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . 96 table 76. lock-sector password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 77. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 78. lock-sector password response format when error_flag is not set . . . . . . . . . . . . . . . . . 98 table 79. lock-sector password response format when error_flag is set . . . . . . . . . . . . . . . . . . . . . 98 table 80. present-sector password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 81. present-sector password response format when error_flag is not set . . . . . . . . . . . . . 100 table 82. present-sector password response format when error_flag is set . . . . . . . . . . . . . . . . . . 100 table 83. fast read single block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 84. fast read single block response format when error_flag is not set . . . . . . . . . . . . . . . 102 table 85. sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 86. fast read single block response format when error_flag is set . . . . . . . . . . . . . . . . . . . 102 table 87. fast inventory initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 88. fast inventory initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 89. fast initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 90. fast initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 91. fast read multiple block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 92. fast read multiple block response format when error_flag is not set. . . . . . . . . . . . . . 106 table 93. sector security status if option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 06 table 94. fast read multiple block response format when error_flag is set . . . . . . . . . . . . . . . . . . 107 table 95. inventory initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 96. inventory initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 97. initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 98. initiate initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 99. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 100. i 2 c operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
M24LR64-R list of tables doc id 15170 rev 9 9/126 table 101. ac test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 102. input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 103. i 2 c dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 104. i 2 c ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 105. rf ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 106. rf dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 107. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 108. so8n ? 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 117 table 109. ufdfpn8 (mlp8) ? ultra thin fine pitch dual flat package no lead 2 x 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 110. tssop8 ? 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 119 table 111. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 112. crc definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 113. afi coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 114. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
list of figures M24LR64-R 10/126 doc id 15170 rev 9 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) 15 figure 5. i 2 c bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. i 2 c present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. i 2 c write password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10. write mode sequences with i2c_write_lock bit = 1 (data write inhibited). . . . . . . . . . . . . 30 figure 11. write mode sequences with i2c_write_lock bit = 0 (data write enabled) . . . . . . . . . . . . . 32 figure 12. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 13. read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 15. 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 16. 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17. detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 18. 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 19. 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 20. sof to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. sof to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. eof for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 23. logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24. logic 0, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25. logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 26. logic 1, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 27. logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 28. logic 0, low data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 29. logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 30. logic 1, low data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 31. logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 32. logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 33. logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 34. logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 35. start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 36. start of frame, high data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 37. start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 38. start of frame, low data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 39. start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 figure 40. start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 figure 41. end of frame, high data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 42. end of frame, high data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 43. end of frame, low data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 44. end of frame, low data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 45. end of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 46. end of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 47. M24LR64-R decision tree for afi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
M24LR64-R list of figures doc id 15170 rev 9 11/126 figure 48. M24LR64-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 49. M24LR64-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 50. principle of comparison between the mask, the slot number and the uid . . . . . . . . . . . . . 67 figure 51. description of a po ssible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 52. stay quiet frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . 75 figure 53. read single block frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . 77 figure 54. write single block frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . 79 figure 55. read multiple block frame exchange between vcd and M24LR64-R. . . . . . . . . . . . . . . . 81 figure 56. select frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 57. reset to ready frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . 83 figure 58. write afi frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 59. lock afi frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 60. write dsfid frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 89 figure 61. lock dsfid frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . 91 figure 62. get system info frame exchange between vcd and M24LR64-R. . . . . . . . . . . . . . . . . . . 93 figure 63. get multiple block security status frame exchange between vcd and M24LR64-R . . . . 95 figure 64. write-sector password frame exchange betw een vcd and M24LR64-R . . . . . . . . . . . . . 97 figure 65. lock-sector password frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . 99 figure 66. present-sector password frame exchange between vcd and M24LR64-R . . . . . . . . . . 101 figure 67. fast read single block frame exchange be tween vcd and M24LR64-R . . . . . . . . . . . . 103 figure 68. fast initiate frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 105 figure 69. fast read multiple block frame exchange between vcd and M24LR64-R. . . . . . . . . . . 107 figure 70. initiate frame exchange between vcd and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 71. ac test measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 72. i 2 c ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 73. M24LR64-R synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 74. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 117 figure 75. ufdfpn8 (mlp8) ? ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 76. tssop8 ? 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 119
description M24LR64-R 12/126 doc id 15170 rev 9 1 description the M24LR64-R device is a dual-interface, el ectrically erasable programmable memory (eeprom). it features an i 2 c interface and can be operated from a v cc power supply. it is also a contactless memory powered by the received carrier electromagnetic wave. the M24LR64-R is organized as 8192 8 bits in the i 2 c mode and as 2048 32 bits in the iso 15693 and iso 18000-3 mode 1 rf mode. figure 1. logic diagram i 2 c uses a two-wire serial interface, comprising a bidirectional data line and a clock line. the devices carry a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition. the device behaves as a slave in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the start condition is followed by a device select code and read/write bit (rw ) (as described in ta bl e 2 ), terminated by an acknowledge bit. when writing data to the memory, the device inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. in the iso15693/iso18000-3 mode 1 rf mode, the M24LR64-R is accessed via the 13.56 mhz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modu lation (ask: amplitude shift keying). the received ask wave is 10% or 100% modulated with a data rate of 1.6 kbit/s using the 1/256 pulse coding mode or a data rate of 26 kbit/s using the 1/4 pulse coding mode. outgoing data are generated by the M24LR64-R load variation using manchester coding with one or two subcarrier frequencies at 423 khz and 484 khz. data are transferred from the M24LR64-R at 6.6 kbit/s in low data rate mode and 26 kbit/s high data rate mode. the M24LR64-R supports the 53 kbit/s in high data rate mode in one subcarrier frequency at 423 khz. the M24LR64-R follows the iso 15693 and iso 18000-3 mode 1 recommendation for radio-frequency power and signal interface. ai15106b 2 e0-e1 sda v cc M24LR64-R scl v ss ac0 ac1
M24LR64-R description doc id 15170 rev 9 13/126 figure 2. 8-pin package connections 1. see package mechanical data section for package dimensions, and how to identify pin-1. table 1. signal names signal name function direction e0, e1 chip enable input sda serial data i/o scl serial clock input ac0, ac1 antenna coils i/o v cc supply voltage v ss ground sda v ss scl e1 ac0 e0 v cc ac1 ai15107 1 2 3 4 8 7 6 5
signal description M24LR64-R 14/126 doc id 15170 rev 9 2 signal description 2.1 serial clock (scl) this input signal is used to strobe all data in and out of the device. in applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from serial clock (scl) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). in most applications, though, this method of sy nchronization is not employed, and so the pull- up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 serial data (sda) this bidirectional signal is used to transfer data in or out of the device. it is an open drain output that may be wire-or?ed with other open drain or open collector signals on the bus. a pull up resistor must be connected from serial data (sda) to v cc . ( figure 4 indicates how the value of the pull-up resistor can be calculated). 2.3 chip enable (e0, e1) these input signals are used to set the value that is to be looked for on the two least significant bits (b2, b1) of the 7-bit device select code. these inputs must be tied to v cc or v ss , to establish the device select code as shown in figure 3 . when not connected (left floating), these inputs are read as low (0,0). figure 3. device select code 2.4 antenna coil (ac0, ac1) these inputs are used to connect the device to an external coil. when correctly tuned, the coil is used to power and access the device using the iso 15693 and iso 18000-3 mode 1 protocols. 2.5 v ss ground v ss is the reference for the v cc supply voltage. ai12806 v cc m24xxx v ss e i v cc m24xxx v ss e i
M24LR64-R signal description doc id 15170 rev 9 15/126 2.6 supply voltage (v cc ) 2.6.1 operating supply voltage v cc prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see ta b l e 1 0 0 ). in order to secure a stable dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss package pins. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the co mpletion of the internal i2c write cycle (t w ). 2.6.2 power-up conditions when the power supply is turned on, v cc rises from v ss to v cc . the v cc rise time must not vary faster than 1v/s. 2.6.3 device reset in order to prevent inadvertent write operations during power-up, a power-on reset (por) circuit is included. at power-up (continuous rise of v cc ), the device does not respond to any instruction until v cc has reached the power-on reset threshold voltage (this threshold is lower than the minimum v cc operating voltage defined in ta bl e 1 0 0 ). when v cc passes over the por threshold, the device is reset and enters the standby power mode, however, the device must not be accessed until v cc has reached a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range. in a similar way, during power-down (continuous decrease in v cc ), as soon as v cc drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 power-down conditions during power-down (continuous decay of v cc ), the device must be in standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). figure 4. i 2 c fast mode (f c = 400 khz): maximum r bus value versus bus parasitic capacitance (c bus ) 1 10 100 10 100 1000 b us line c a p a citor (pf) b us line p u ll- u p re s i s tor (k ) when t low = 1. 3 s (min v a l u e for f c = 400 khz), the r bus c bus time con s t a nt m us t b e b elow the 400 n s time con s t a nt line repre s ented on the left. i2c bus m as ter m24xxx r bus v cc c bus s cl s da a i14796 b r bus c bus = 400 n s here r bus c bus = 120 n s 4 k 3 0 pf
signal description M24LR64-R 16/126 doc id 15170 rev 9 figure 5. i 2 c bus protocol table 2. device select code device type identifier (1) 1. the most significant bit, b7, is sent first. chip enable address (2) 2. e0 and e1 are compared against the respecti ve external pins on the memory device. rw b7 b6 b5 b4 b3 b2 b1 b0 device select code 1010e2 (3) 3. e2 is not connected to any external pin. it is however used to address the M24LR64-R as described in section 3 and section 4 . e1 e0 rw table 3. address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 table 4. address least significant byte b7 b6 b5 b4 b3 b2 b1 b0 scl sda scl sda sda start condition sda input sda change ai00792b stop condition 1 23 7 89 msb ack start condition scl 1 23 7 89 msb ack stop condition
M24LR64-R user memory organization doc id 15170 rev 9 17/126 3 user memory organization the M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in ta b l e 5 . figure 7 shows the memory sector organization. each sector can be individually read- and/or write-protected using a specific password command. read and write operations are possible if the addressed data are not in a protected sector. the M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (uid). the uid is compliant with the iso 15963 description, and its value is used during the anticollision sequence (inventory). this block is not accessible by the user and its value is written by st on the production line. the M24LR64-R includes an afi register that stores the application family identifier, and a dsfid register that st ores the data storage family iden tifier used in the anticollision algorithm. the M24LR64-R has four additional 32-bit blocks that store an i 2 c password plus three rf password codes. figure 6. block diagram eeprom row decoder latch logic rf i 2 c rf v cc contact v cc scl sda v ss v cc ac0 ac1 power management ai15123
user memory organization M24LR64-R 18/126 doc id 15170 rev 9 figure 7. memory sector organization sector details the M24LR64-R user memory is divided into 64 sectors. each sector contains 1024 bits. the protection scheme is described in section 4: system memory area . in rf mode, a sector provides 32 blocks of 32 bits. each read and write access are done by block. read and write block accesses are controlled by a sector security status byte that defines the access rights to all the 32 blocks contained in the sector. if the sector is not protected, a write command updates the complete 32 bits of the selected block. in i 2 c mode, a sector provides 128 bytes that can be individually accessed in read and write modes. when protected by the corresponding i2c_write_lock bit, the entire sector is write- protected. to access the user memory, the device select code used for any i 2 c command must have the e2 chip enable address at 0. 0 1 kbit eeprom sector 5 bits 1 1 kbit eeprom sector 5 bits 2 1 kbit eeprom sector 5 bits 3 1 kbit eeprom sector 5 bits 60 1 kbit eeprom sector 5 bits 61 1 kbit eeprom sector 5 bits 62 1 kbit eeprom sector 5 bits 63 1 kbit eeprom sector 5 bits i2c password system rf password 1 system rf password 2 system rf password 3 system 8 bit dsfid system 8 bit afi system 64 bit uid system sector area sector security status ai15124
M24LR64-R user memory organization doc id 15170 rev 9 19/126 table 5. sector details sector number rf block address i 2 c byte address bits [31:24] bits [23:16 ] bits [15:8] bits [7:0] 0 0 0 user user user user 1 4 user user user user 2 8 user user user user 3 12 user user user user 4 16 user user user user 5 20 user user user user 6 24 user user user user 7 28 user user user user 8 32 user user user user 9 36 user user user user 10 40 user user user user 11 44 user user user user 12 48 user user user user 13 52 user user user user 14 56 user user user user 15 60 user user user user 16 64 user user user user 17 68 user user user user 18 72 user user user user 19 76 user user user user 20 80 user user user user 21 84 user user user user 22 88 user user user user 23 92 user user user user 24 96 user user user user 25 100 user user user user 26 104 user user user user 27 108 user user user user 28 112 user user user user 29 116 user user user user 30 120 user user user user 31 124 user user user user
user memory organization M24LR64-R 20/126 doc id 15170 rev 9 1 32 128 user user user user 33 132 user user user user 34 136 user user user user 35 140 user user user user 36 144 user user user user 37 148 user user user user 38 152 user user user user 39 156 user user user user ... ... ... ... ... ... ... ... ... ... ... ... ... table 5. sector details (continued) sector number rf block address i 2 c byte address bits [31:24] bits [23:16 ] bits [15:8] bits [7:0]
M24LR64-R user memory organization doc id 15170 rev 9 21/126 63 2016 8064 user user user user 2017 8068 user user user user 2018 8072 user user user user 2019 8076 user user user user 2020 8080 user user user user 2021 8084 user user user user 2022 8088 user user user user 2023 8092 user user user user 2024 8096 user user user user 2025 8100 user user user user 2026 8104 user user user user 2027 8108 user user user user 2028 8112 user user user user 2029 8116 user user user user 2030 8120 user user user user 2031 8124 user user user user 2032 8128 user user user user 2033 8132 user user user user 2034 8136 user user user user 2035 8140 user user user user 2036 8144 user user user user 2037 8148 user user user user 2038 8152 user user user user 2039 8156 user user user user 2040 8160 user user user user 2041 8164 user user user user 2042 8168 user user user user 2043 8172 user user user user 2044 8176 user user user user 2045 8180 user user user user 2046 8184 user user user user 2047 8188 user user user user table 5. sector details (continued) sector number rf block address i 2 c byte address bits [31:24] bits [23:16 ] bits [15:8] bits [7:0]
system memory area M24LR64-R 22/126 doc id 15170 rev 9 4 system memory area 4.1 M24LR64-R rf block security the M24LR64-R provides a special protection mechanism based on passwords. each memory sector of the M24LR64-R can be individually protected by one out of three available passwords, and each sector can also have read/write access conditions set. each memory sector of the M24LR64-R is assigned with a sector security status byte including a sector lock bit, two password control bits and two read/write protection bits as shown in ta bl e 7 . ta bl e 6 describes the organization of the sector security status byte which can be read using the read single block and read multiple block commands with the option_flag set to ?1?. on delivery, the default value of the sss bytes is reset to 00h. when the sector lock bit is set to ?1?, for instance by issuing a lock-sector password command, the 2 read/write protection bits (b 1 , b 2 ) are used to set the read/write access of the sector as described in ta b l e 8 . table 6. sector security status byte area rf address i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] 0 e2 = 1 0 sss 3 sss 2 sss 1 sss 0 128 e2 = 1 4 sss 7 sss 6 sss 5 sss 4 256 e2 = 1 8 sss 11 sss 10 sss 9 sss 8 384 e2 = 1 12 sss 15 sss 14 sss 13 sss 12 512 e2 = 1 16 sss 19 sss 18 sss 17 sss 16 640 e2 = 1 20 sss 23 sss 22 sss 21 sss 20 768 e2 = 1 24 sss 27 sss 26 sss 25 sss 24 896 e2 = 1 28 sss 31 sss 30 sss 29 sss 28 1024 e2 = 1 32 sss 35 sss 34 sss 33 sss 32 1152 e2 = 1 36 sss 39 sss 38 sss 37 sss 36 1280 e2 = 1 40 sss 43 sss 42 sss 41 sss 40 1408 e2 = 1 44 sss 47 sss 46 sss 45 sss 44 1536 e2 = 1 48 sss 51 sss 50 sss 49 sss 48 1664 e2 = 1 52 sss 55 sss 54 sss 53 sss 52 1792 e2 = 1 56 sss 59 sss 58 sss 57 sss 56 1920 e2 = 1 60 sss 63 sss 62 sss 61 sss 60 table 7. sector security status byte organization b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 0 password control bits read / write protection bits sector lock
M24LR64-R system memory area doc id 15170 rev 9 23/126 the next 2 bits of the sector security status byte (b 3 , b 4 ) are the password control bits. the value these two bits is used to link a password to the sector as defined in ta b l e 9 . the M24LR64-R password protection is organized around a dedicated set of commands plus a system area of three password blocks wh ere the password val ues are stored. this system area is described in ta bl e 1 0 . the dedicated password commands are: write-sector password: the write-sector password command is used to write a 32-bit block into the password system area. this command must be used to update password values. after the write cycle, the new password value is automatica lly activated. it is possible to modify a password value after issuing a valid present-sector password command. on delivery, the three default password values are set to 0000 0000h and are activated. lock-sector password: the lock-sector password command is used to set the sector security status byte of the selected sector. bits b 4 to b 1 of the sector security status byte are affected by the lock-sector password command. the sector lock bit, b 0 , is set to ?1? automatically. after issuing a lock-sector password command, the protection settings of the selected sector are activated. the protection of a locked block cannot be changed in rf mode. a lock-sector password command sent to a locked sector returns an error code. table 8. read / write protection bit setting sector lock b 2 , b 1 sector access when password presented sector access when password not presented 0 xx read write read write 1 00 read write read no write 1 01 read write read write 1 10 read write no read no write 1 11 read no write no read no write table 9. password control bits b 4 , b 3 password 00 the sector is not protected by a password 01 the sector is protected by the password 1 10 the sector is protected by the password 2 11 the sector is protected by the password 3 table 10. password system area add 0 7 8 15 16 23 24 31 1 password 1 2 password 2 3 password 3
system memory area M24LR64-R 24/126 doc id 15170 rev 9 present-sector password: the present-sector password command is used to present one of the three passwords to the M24LR64-R in order to modify the access rights of all the memory sectors linked to that password ( ta bl e 8 ) including the password itself. if the presented password is correct, the access rights remain activated until the tag is powered off or until a new present-sector password command is issued. if the presented password value is not correct, all the access rights of all the memory sectors are deactivated. sector security status byte area access conditions in i 2 c mode: in i 2 c mode, read access to the sector security status byte area is always allowed. write access depends on the correct presentation of the i 2 c password (see i 2 c present password command description on page 26 ). to access the sector security status byte area, the device select code used for any i 2 c command must have the e2 chip enable address at 1. an i 2 c write access to a sector security status byte re-initializes the rf access condition to the given memory sector. 4.2 example of the M24LR64-R security protection ta bl e 1 1 and ta bl e 1 2 show the sector security protections before and after a valid present- sector password command. ta b l e 1 1 shows the sector access rights of an M24LR64-R after power-up. after a valid present-sector password command with password 1, the memory sector access is changed as shown in ta b l e 1 2 . table 11. M24LR64-R sector security protection after power-up sector address sector security status byte b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 protection: standard read no write xxx 0 0 0 0 1 1 protection: pswd 1 read no write xxx 01001 2 protection: pswd 1 read write xxx 0 1 0 1 1 3 protection: pswd 1 no read no write xxx 0 1 1 0 1 4 protection: pswd 1 no read no write xxx 0 1 1 1 1 table 12. M24LR64-R sector security protection after a valid presentation of password 1 sector address sector security status byte b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 protection: standard read no write xxx 0 0 0 0 1 1 protection: pswd 1 read write xxx 0 1 0 0 1 2 protection: pswd 1 read write xxx 0 1 0 1 1 3 protection: pswd 1 read write xxx 0 1 1 0 1 4 protection: pswd 1 read no write xxx 0 1 1 1 1
M24LR64-R system memory area doc id 15170 rev 9 25/126 4.3 i2c_write_lock bit area in the i 2 c mode only, it is possible to protect individual sectors against write operations. this feature is controlled by the i2c_write_lock bits stored in the 8 bytes of the i2c_write_lock bit area starting from the location 2048 (see ta bl e 1 3 ). using these 64 bits, it is possible to write-protect all the 64 sectors of the M24LR64-R memory. each bit controls the i 2 c write access to a specific sector as shown in ta b l e 1 3 . it is always possible to unprotect a sector in the i 2 c mode. when an i2c_write_lock bit is reset to 0, the corresponding sector is unprotected. when the bit is set to 1, the corresponding sector is write-protected. in i 2 c mode, read access to the i2c_write_lock bit area is always allowed. write access depends on the correct presentation of the i 2 c password. to access the i2c_write_lock bit area, the device select code used for any i 2 c command must have the e2 chip enable address at 1. on delivery, the default value of the 8 bytes of the i2c_write_lock bit area is reset to 00h. 4.4 system parameters the M24LR64-R provides the system area required by the iso 15693 rf protocol, as shown in ta b l e 1 4 . the first 32-bit block starting from i 2 c address 2304 stores the i 2 c password. this password is used to activate/deactivate the write protection of the protected sector in i 2 c mode. at power-on, all user memory sectors protected by the i2c_write_lock bits can be read but cannot be modified. to remove the write protection, it is necessary to use the i 2 c present password described in figure 8 . when the password is correctly presented ? that is, when all the presented bits correspond to the stored ones ? it is also possible to modify the i 2 c password using the i 2 c write password command described in figure 9 . the next three 32-bit blocks store the three rf passwords. these passwords are neither read- nor write- accessible in the i 2 c mode. the next 2 bytes are used to store the afi, at i 2 c location 2322, and the dsfid, at i 2 c location 2323. these 2 values are used during the rf inventory sequence. they are read- only in the i 2 c mode. the next 8 bytes, starting from location 2324, store the 64-bit uid programmed by st on the production line. bytes at i 2 c locations 2332 to 2335 store the ic ref and the mem_size data used by the rf get_system_info command. the uid, mem_size and ic ref values are read-only data. table 13. i2c_write_lock bit i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] e2 = 1 2048 sectors 31-24 sectors 23-16 sectors 15-8 sectors 7-0 e2 = 1 2052 sectors 63-56 sectors 55-48 sectors 47-40 sectors 39-32
system memory area M24LR64-R 26/126 doc id 15170 rev 9 4.5 M24LR64-R i 2 c password security the M24LR64-R controls i 2 c sector write access using the 32-bit-long i 2 c password and the 64-bit i2c_write_lock bit area. the i 2 c password value is managed using two i 2 c commands: i ? c present password and i 2 c write password. 4.5.1 i 2 c present password command description the i 2 c present password command is used in i 2 c mode to present the password to the M24LR64-R in order to modify the write access rights of all the memory sectors protected by the i2c_write_lock bits, including the password itself. if the presented password is correct, the access rights remain activated until the M24LR64-R is powered off or until a new i 2 c present password command is issued. following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0 and the chip enable bit e2 at 1. the device acknowledges this, as shown in figure 8 , and waits for two i 2 c password address bytes 09h and 00h. the device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 09h, and a resend of the 4 password data bytes. the most significant byte of the password is sent first, followed by the least significant bytes. it is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. if the two 32-bit passwords sent are not exactly the same, the M24LR64-R does not start the internal comparison. when the bus master generates a stop condition immediately after the ack bit (during the ?10 th bit? time slot), an internal delay equivalent to the write cycle time is triggered. a stop condition at any other time does not trigger the internal delay. during that delay, the M24LR64-R compares the 32 received data bits with the 32 bits of the stored i 2 c password. if the values match, the write access rights to all protected sectors are modified after the internal delay. if the values do not match, the protected sectors remains protected. during the internal delay, serial data (sda) is disabled internally, and the device does not respond to any requests. table 14. system parameter sector rf address i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] -e2 = 12304 i 2 c password (1) 1. delivery state: i 2 c password= 0000 0000h, rf password = 0000 0000h, 1 e2 = 1 2308 rf password 1 (1) 2 e2 = 1 2312 rf password 2 (1) 3 e2 = 1 2316 rf password 3 (1) - e2 = 1 2320 dsfid (ffh) afi (00h) st reserved st reserved - e2 = 1 2324 uid uid uid uid - e2 = 1 2328 uid (e0h) uid (02h) uid uid - e2 = 1 2332 mem_size (03 07ffh) ic ref (2ch)
M24LR64-R system memory area doc id 15170 rev 9 27/126 figure 8. i 2 c present password command 4.5.2 i 2 c write password command description the i 2 c write password command is used to write a 32-bit block into the M24LR64-R i 2 c password system area. this command is used in i 2 c mode to update the i 2 c password value. it cannot be used to update any of the rf passwords. after the write cycle, the new i 2 c password value is automatically activated. the i 2 c password value can only be modified after issuing a valid i 2 c present password command. on delivery, the i 2 c default password value is set to 0000 0000h and is activated. following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0 and the chip enable bit e2 at 1. the device acknowledges this, as shown in figure 9 , and waits for the two i 2 c password address bytes, 09h and 00h. the device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 07h, and a resend of the 4 password data bytes. the most significant byte of the password is sent first, followed by the least significant bytes. it is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. if the two 32-bit passwords sent are not exactly the same, the M24LR64-R does not modify the i 2 c password value. when the bus master generates a stop condition immediately after the ack bit (during the 10 th bit time slot), the internal write cycle is triggered. a stop condition at any other time does not trigger the internal write cycle. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. ai15125b start device select code password address 09h password address 00h password [31:24] ack r/w ack ack ack device select code = 1010 1 e1 e0 password [23:16] password [15:8] password [7:0] ack ack ack ack generated during 9 th bit time slot. stop validation code 09h ack password [31:24] ack password [23:16] password [15:8] password [7:0] ack ack ack
system memory area M24LR64-R 28/126 doc id 15170 rev 9 figure 9. i 2 c write password command ai15126 start device select code password address 09h password address 00h new password [31:24] ack r/w ack ack ack device select code = 1010 1 e1 e0 new password [23:16] new password [15:8] new password [7:0] ack ack ack ack generated during 9 th bit time slot. stop validation code 07h ack new password [31:24] ack new password [23:16] new password [15:8] new password [7:0] ack ack ack
M24LR64-R i 2 c device operation doc id 15170 rev 9 29/126 5 i 2 c device operation the device supports the i 2 c protocol. this is summarized in figure 5 . any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. the device that controls the data transfer is known as the bus master, and the other as the slave device. a data transfer can on ly be initiated by the bus master, which will also provide the serial clock for synchronization. the M24LR64-R device is always a slave in all communications. 5.1 start condition start is identified by a falling edge of serial da ta (sda) while serial clock (scl) is stable in the high state. a start condition must precede any data transfer command. the device continuously monitors (except during a write cycle) serial data (sda) and serial clock (scl) for a start condition, and will not respond unless one is given. 5.2 stop condition stop is identified by a rising edge of serial data (sda) while serial clock (scl) is stable and driven high. a stop condition terminates communication between the device and the bus master. a read command that is followed by noack can be followed by a stop condition to force the device into the standby mode. a stop condition at the end of a write command triggers the internal write cycle. 5.3 acknowledge bit (ack) the acknowledge bit is used to indicate a successful byte transfer. the bus transmitter, whether it be bus master or slave device, releases serial data (sda) after sending eight bits of data. during the 9 th clock pulse period, the receiver pulls serial data (sda) low to acknowledge the receipt of the eight data bits. 5.4 data input during data input, the device samples serial data (sda) on the rising edge of serial clock (scl). for correct device operation, serial data (sda) must be stable during the rising edge of serial clock (scl), and the serial data (sda) signal must change only when serial clock (scl) is driven low.
i 2 c device operation M24LR64-R 30/126 doc id 15170 rev 9 5.5 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in ta b l e 2 (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (e2, e1, e0). to address the memory array, the 4-bit device type identifier is 1010b. up to four memory devices can be connected on a single i 2 c bus. each one is given a unique 2-bit code on the chip enable (e0, e1) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (e0, e1) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. figure 10. write mode sequences with i2c_write_lock bit = 1 (data write inhibited) table 15. operating modes mode rw bit bytes initial sequence current address read 1 1 st art, device select, rw = 1 random address read 0 1 start, device select, rw = 0, address 1 restart, device select, rw = 1 sequential read 1 ? 1 similar to current or random address read byte write 0 1 start, device select, rw = 0 page write 0 ?? 4 bytes start, device select, rw = 0 stop start byte write dev select byte address byte address data in start page write dev select byte address byte address data in 1 data in 2 ai15115 page write (cont'd) stop data in n ack ack ack no ack r/w ack ack ack no ack r/w no ack no ack
M24LR64-R i 2 c device operation doc id 15170 rev 9 31/126 5.6 write operations following a start condition the bus master sends a device select code with the read/write bit (rw ) reset to 0. the device acknowledges this, as shown in figure 11 , and waits for two address bytes. the device responds to each address byte with an acknowledge bit, and then waits for the data byte. writing to the memory may be inhibited if th e i2c_write_lock bit = 1. a write instruction issued with the i2c_write_lock bit = 1 and with no i2c_password presented, does not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in figure 10 . each data byte in the memory has a 16-bit (two byte wide) address. the most significant byte ( ta b l e 3 ) is sent first, followed by the least significant byte ( ta bl e 4 ). bits b15 to b0 form the address of the byte in memory. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. after the stop condition, the delay t w , and the successful completion of a write operation, the device?s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. 5.7 byte write after the device select code and the address bytes, the bus master sends one data byte. if the addressed location is write-protected by the i2c_write_lock bit (= 1), the device replies with noack, and the location is not modified. if, instead, the addressed location is not write- protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 11 . 5.8 page write the page write mode allows up to 4 bytes to be written in a single write cycle, provided that they are all located in the same ?row? in the memory: that is, the most significant memory address bits (b12-b2) ar e the same. if more bytes are sent than will fit up to the end of the row, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 4 bytes of data, each of which is acknowledged by the device if the i2c_write_lock bit = 0 or the i2c_password was correctly presented. if the i2c_write_lock_bit = 1 and the i2c_password is not presented, the contents of the addressed memory location are not modified, and each data byte is followed by a noack. after each byte is transferred, the internal byte address counter (inside the page) is incremented. the transfer is terminated by the bus master generating a stop condition.
i 2 c device operation M24LR64-R 32/126 doc id 15170 rev 9 figure 11. write mode sequences with i2c_write_lock bit = 0 (data write enabled) figure 12. write cycle polling flowchart using ack stop start byte write dev select byte address byte address data in start page write dev select byte address byte address data in 1 data in 2 ai15116 stop data in n ack r/w ack ack ack ack ack ack ack r/w ack ack write cycle in progress ai01847d next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
M24LR64-R i 2 c device operation doc id 15170 rev 9 33/126 5.9 minimizing system delays by polling on ack during the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to th e memory cells. the maximum i2c write time (t w ) is shown in ta b l e 1 0 4 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 12 , is: 1. initial condition: a write cycle is in progress. 2. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). 3. step 2: if the device is busy with the in ternal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1).
i 2 c device operation M24LR64-R 34/126 doc id 15170 rev 9 figure 13. read mode sequences 1. the seven most significant bits of the dev ice select code of a random read (in the 1 st and 4 th bytes) must be identical. start dev select * byte address byte address start dev select data out 1 ai01105d data out n stop start current address read dev select data out random address read stop start dev select * data out sequential current read stop data out n start dev select * byte address byte address sequential random read start dev select * data out 1 stop ack r/w no ack ack r/w ack ack ack r/w ack ack ack no ack r/w no ack ack ack ack r/w ack ack r/w ack no ack
M24LR64-R i 2 c device operation doc id 15170 rev 9 35/126 5.10 read operations read operations are performed independently of the state of the i2c_write_lock bit. after the successful completion of a read operation, the device?s internal address counter is incremented by one, to point to the next byte address. 5.11 random address read a dummy write is first performed to load the address into this address counter (as shown in figure 13 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.12 current address read for the current address read operation, following a start condition, the bus master only sends a device select code with the read/write bit (rw ) set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 13 , without acknowledging the byte. 5.13 sequential read this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 13 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.14 acknowledge in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode.
user memory initial state M24LR64-R 36/126 doc id 15170 rev 9 6 user memory initial state the device is delivered with all bits in the user memory array set to 1 (each byte contains ffh). 7 rf device operation the M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in ta b l e 5 . each sector can be individually read- and/or write-protected using a specific lock or password command. read and write operations are possible if the addressed block is not protected. during a write, the 32 bits of the block are replaced by the new 32-bit value. the M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier (uid). the uid is compliant with the iso 15963 description, and its value is used during the anticollision sequence (inventory). this block is not accessible by the user and its value is written by st on the production line. the M24LR64-R also includes an afi register in which the application family identifier is stored, and a dsfid register in which the data storage family identifier used in the anticollision algorithm is stored. the m24lr64- r has three additional 32-bit blocks in which the password codes are stored.
M24LR64-R rf device operation doc id 15170 rev 9 37/126 7.1 commands the M24LR64-R supports the following commands: inventory , used to perform the anticollision sequence. stay quiet , used to put the M24LR64-R in quiet mode, where it does not respond to any inventory command. select , used to select the M24LR64-R. after this command, the M24LR64-R processes all read/write commands with select_flag set. reset to ready , used to put the M24LR64-R in the ready state. read block , used to output the 32 bits of the selected block and its locking status. write block , used to write the 32-bit value in the selected block, provided that it is not locked. read multiple blocks , used to read the selected blocks and send back their value. write afi , used to write the 8-bit value in the afi register. lock afi , used to lock the afi register. write dsfid , used to write the 8-bit value in the dsfid register. lock dsfid , used to lock the dsfid register. get system info , used to provide the system information value get multiple block security status , used to send the security status of the selected block. initiate , used to trigger the tag response to the inventory initiated sequence. inventory initiated , used to perform the anticollision sequence triggered by the initiate command. write-sector password , used to write the 32 bits of the selected password. lock-sector password , used to write the sector security status bits of the selected sector. present-sector password , enables the user to present a password to unprotect the user blocks linked to this password. fast initiate , used to trigger the tag response to the inventory initiated sequence. fast inventory initiated , used to perform the anticollis ion sequence triggered by the initiate command. fast read single block , used to output the 32 bits of the selected block and its locking status. fast read multiple blocks , used to read the selected blocks and send back their value.
rf device operation M24LR64-R 38/126 doc id 15170 rev 9 7.2 initial dialog for vicinity cards the dialog between the vicinity coupling device or vcd (commonly the ?rf reader?) and the vicinity integrated circuit card or vi cc (M24LR64-R) takes place as follows: activation of the M24LR64-R by the rf operating field of the vcd transmission of a command by the vcd transmission of a response by the M24LR64-R these operations use the rf power transfer an d communication signal interface described below (see power transfer , frequency and operating field ). this technique is called rtf (reader talk first). 7.2.1 power transfer power is transferred to the M24LR64-R by radio frequency at 13.56 mhz via coupling antennas in the M24LR64-R and the vcd. the rf operating field of the vcd is transformed on the M24LR64-R antenna to an ac voltage which is rectified, filtered and internally regulated. the amplitude modu lation (ask) on this received signal is demodulated by the ask demodulator. 7.2.2 frequency the iso 15693 standard defines the carrier frequency ( f c ) of the operating field as 13.56 mhz 7 khz. 7.2.3 operating field the M24LR64-R operates continuously betwe en the minimum and maximum values of the electromagnetic field h defined in table 105 . the vcd has to generate a field within these limits.
M24LR64-R communication signal from vcd to M24LR64-R doc id 15170 rev 9 39/126 8 communication signal from vcd to M24LR64-R communications between the vcd and the M24LR64-R takes place using the modulation principle of ask (amplitude sh ift keying). two modulation indexes are used, 10% and 100%. the M24LR64-R decodes both. the vcd determines wh ich index is used. the modulation index is defined as [a ? b]/[a + b] where a is the peak signal amplitude and b, the minimum signal amplitude of the carrier frequency. depending on the choice made by the vcd, a ?pause? will be created as described in figure 14 and figure 15 . the M24LR64-R is operational for any degree of modulation index from between 10% and 30%. figure 14. 100% modulation waveform 105 % a 95 % 5 % 60 % c a rrier amplit u de t t 2 t 1 t 3 t 4 min ( s ) t 1 6,0 t 2 2,1 t 3 0 m a x ( s ) 9,44 t 1 4,5 t 4 0 0, 8 b the clock recovery s h a ll b e oper a tion a l a fter t 4 m a x. a i1579 3
communication signal from vcd to M24LR64-R M24LR64-R 40/126 doc id 15170 rev 9 figure 15. 10% modulation waveform table 16. 10% modulation parameters symbol parameter definition value hr 0.1 x (a ? b) max hf 0.1 x (a ? b) max the vicc s h a ll b e oper a tion a l for a ny v a l u e of mod u l a tion index b etween 10 % a nd 3 0 % . min 6,0 s t2 3 ,0 s t 3 0 m a x 9,44 s t1 4,5 s mod u l a tion index t1 10 % 3 0 % hf, hr 0,1 ( a - b ) m a x y 0,05 ( a - b ) t1 t2 hf y hr t 3 t y a b c a rrier amplit u de min 6,0 s t2 3 ,0 s t 3 0 m a x 9,44 s t1 4,5 s mod u l a tion index t1 10 % 3 0 % min 6,0 s t2 3 ,0 s t 3 0 m a x 9,44 s t1 4,5 s mod u l a tion index t1 10 % 3 0 % hf, hr 0,1 ( a - b ) m a x y 0,05 ( a - b ) hf, hr 0,1 ( a - b ) m a x y 0,05 ( a - b ) t1 t2 hf y hr t 3 t y a b c a rrier amplit u de a i15794
M24LR64-R data rate and data coding doc id 15170 rev 9 41/126 9 data rate and data coding the data coding implemented in the M24LR64-R uses pulse position modulation. both data coding modes that are described in the iso15693 are supported by the M24LR64-R. the selection is made by the vcd and indicated to the M24LR64-R within the start of frame (sof). 9.1 data coding mode: 1 out of 256 the value of one single byte is represented by the position of one pause. the position of the pause on 1 of 256 successive time periods of 18.88 s (256/ f c ), determines the value of the byte. in this case the transmission of one byte takes 4.833 ms and the resulting data rate is 1.65 kbits/s ( f c /8192). figure 16 illustrates this pulse position modulation technique. in this figure, data e1h (225 decimal) is sent by the vcd to the M24LR64-R. the pause occurs during the second half of the position of the time period that determines the value, as shown in figure 17 . a pause during the first period transmits the data value 00h. a pause during the last period transmit the data value ffh (255 decimal). figure 16. 1 out of 256 coding mode ai06656 0 1 2 3 . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . 2 2 2 2 . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . 5 5 5 5 . . . . . . . . . 5 . . . . . . . . . . . . . . . . . . . . . 2 3 4 5 4.833 ms 18.88 s 9.44 s pulse modulated carrier
data rate and data coding M24LR64-R 42/126 doc id 15170 rev 9 figure 17. detail of a time period 9.2 data coding mode: 1 out of 4 the value of 2 bits is represented by the position of one pause. the position of the pause on 1 of 4 successive time periods of 18.88 s (256/ f c ), determines the value of the 2 bits. four successive pairs of bits form a byte, where the least significant pair of bits is transmitted first. in this case the transmission of one byte takes 302.08 s and the resulting data rate is 26.48 kbits/s ( f c /512). figure 18 illustrates the 1 out of 4 puls e position technique and coding. figure 19 shows the transmission of e1h (225d - 1110 0001b) by the vcd. ai06657 2 2 5 18.88 s 9.44 s pulse modulated carrier 2 2 6 2 2 4 . . . . . . . . . . . . . . time period one of 256
M24LR64-R data rate and data coding doc id 15170 rev 9 43/126 figure 18. 1 out of 4 coding mode figure 19. 1 out of 4 coding example ai06658 9.44 s 9.44 s 75.52 s 28.32 s 9.44 s 75.52 s 47.20s 9.44 s 75.52 s 66.08 s 9.44 s 75.52 s pulse position for "00" pulse position for "11" pulse position for "10" (0=lsb) pulse position for "01" (1=lsb) ai06659 75.52s 75.52s 75.52s 75.52s 00 10 01 11
data rate and data coding M24LR64-R 44/126 doc id 15170 rev 9 9.3 vcd to M24LR64-R frames frames are delimited by a start of frame (sof) and an end of frame (eof). they are implemented using code violation. unus ed options are reserved for future use. the M24LR64-R is ready to receive a new command frame from the vcd 311.5 s (t 2 ) after sending a response frame to the vcd. the M24LR64-R takes a power-up time of 0.1 ms after being activated by the powering field. after this delay, the M24LR64-R is ready to receive a command frame from the vcd. 9.4 start of frame (sof) the sof defines the data coding mode the vcd is to use for the following command frame. the sof sequence described in figure 20 selects the 1 out of 256 data coding mode. the sof sequence described in figure 21 selects the 1 out of 4 data coding mode. the eof sequence for either coding mode is described in figure 22 . figure 20. sof to select 1 out of 256 data coding mode figure 21. sof to select 1 out of 4 data coding mode ai06661 37.76s 9.44s 9.44s 37.76s ai06660 37.76s 9.44s 9.44s 37.76s 9.44s
M24LR64-R data rate and data coding doc id 15170 rev 9 45/126 figure 22. eof for either data coding mode ai06662 9.44s 37.76s 9.44s
communications signal from M24LR64-R to vcd M24LR64-R 46/126 doc id 15170 rev 9 10 communications signal from M24LR64-R to vcd the M24LR64-R has several modes defined for some parameters, owing to which it can operate in different noise environments and meet different application requirements. 10.1 load modulation the M24LR64-R is capable of communication to the vcd via an inductive coupling area whereby the carrier is loaded to generate a subcarrier with frequency f s . the subcarrier is generated by switching a load in the M24LR64-R. the load-modulated amplitude received on the vcd antenna must be of at least 10mv when measured as described in the test methods defined in international standard iso10373-7. 10.2 subcarrier the M24LR64-R supports the one-subcarrier and two-subcarrier response formats. these formats are selected by the vcd using the first bit in the protocol header. when one subcarrier is used, the frequency f s1 of the subcarrier load modulation is 423.75 khz ( f c /32). when two subcarriers are used, the frequency f s1 is 423.75 khz ( f c /32), and frequency f s2 is 484.28 khz ( f c /28). when using the two-subcarrier mode, the M24LR64-R generates a continuous phase relationship between f s1 and f s2 . 10.3 data rates the M24LR64-R can respond using the low or the high data rate format. the selection of the data rate is made by the vcd using the second bit in the protocol header. it also supports the x2 mode available on all the fast commands. ta bl e 1 7 shows the different data rates produced by the M24LR64-R using the different response format combinations. table 17. response data rates data rate one subcarrier two subcarriers low standard commands 6.62 kbit/s ( f c /2048) 6.67 kbit/s ( f c /2032) fast commands 13.24 kbit/s ( f c /1024) not applicable high standard commands 26.48 kbit/s ( f c /512) 26.69 kbit/s ( f c /508) fast commands 52.97 kbit/s ( f c /256) not applicable
M24LR64-R bit representation and coding doc id 15170 rev 9 47/126 11 bit representation and coding data bits are encoded using manchester coding, according to the following schemes. for the low data rate, same subcarrier frequency or frequencies is/are used, in this case the number of pulses is multiplied by 4 and all ti mes will increase by this factor. for the fast commands using one subcarrier, all pulse numbers and times are divided by 2. 11.1 bit coding using one subcarrier 11.1.1 high data rate a logic 0 starts with 8 pulses at 423.75 khz (f c /32) followed by an unmodulated time of 18.88 s as shown in figure 23 . figure 23. logic 0, high data rate for the fast commands, a logic 0 starts with 4 pulses at 423.75 khz (f c /32) followed by an unmodulated time of 9.44 s as shown in figure 24 . figure 24. logic 0, high data rate x2 a logic 1 starts with an unmodulated time of 18.88 s followed by 8 pulses at 423.75 khz (f c /32) as shown in figure 25 . figure 25. logic 1, high data rate for the fast commands, a logic 1 starts with an unmodulated time of 9.44 s followed by 4 pulses of 423.75 khz (f c /32) as shown in figure 26 . figure 26. logic 1, high data rate x2 37.76s ai12076 18.88s ai12066 37.76s ai12077 18.88s ai12067
bit representation and coding M24LR64-R 48/126 doc id 15170 rev 9 11.1.2 low data rate a logic 0 starts with 32 pulses at 423.75 khz (f c /32) followed by an unmodulated time of 75.52 s as shown in figure 27 . figure 27. logic 0, low data rate for the fast commands, a logic 0 starts with 16 pulses at 423.75 khz (f c /32) followed by an unmodulated time of 37.76 s as shown in figure 28 . figure 28. logic 0, low data rate x2 a logic 1 starts with an unmodulated time of 75.52 s followed by 32 pulses at 423.75 khz (f c /32) as shown in figure 29 . figure 29. logic 1, low data rate for the fast commands, a logic 1 starts with an unmodulated time of 37.76 s followed by 16 pulses at 423.75 khz (f c /32) as shown in figure 29 . figure 30. logic 1, low data rate x2 151.04s ai12068 75.52s ai12069 151.04s ai12070 75.52s ai12071
M24LR64-R bit representation and coding doc id 15170 rev 9 49/126 11.2 bit coding using two subcarriers 11.3 high data rate a logic 0 starts with 8 pulses at 423.75 khz (f c /32) followed by 9 pulses at 484.28 khz (f c /28) as shown in figure 31 . for the fast commands, the x2 mode is not available. figure 31. logic 0, high data rate a logic 1 starts with 9 pulses at 484.28 khz (f c /28) followed by 8 pulses at 423.75 khz (f c /32) as shown in figure 32 . for the fast commands, the x2 mode is not available. figure 32. logic 1, high data rate 11.4 low data rate a logic 0 starts with 32 pulses at 423.75 khz (f c /32) followed by 36 pulses at 484.28 khz (f c /28) as shown in figure 33 . for the fast commands, the x2 mode is not available. figure 33. logic 0, low data rate a logic 1 starts with 36 pulses at 484.28 khz (f c /28) followed by 32 pulses at 423.75 khz (f c /32) as shown in figure 34 . for the fast commands, the x2 mode is not available. figure 34. logic 1, low data rate 37.46 s ai12074 37.46 s ai12073 149.84s ai12072 149.84s ai12075
M24LR64-R to vcd frames M24LR64-R 50/126 doc id 15170 rev 9 12 M24LR64-R to vcd frames frames are delimited by an sof and an eof. they are implemented using code violation. unused options are reserved for future use. for the low data rate, the same subcarrier frequency or frequencies is/are used. in this case the number of pulses is multiplied by 4. for the fast commands using one subcarrier, all pulse numbers and times are divided by 2. 12.1 sof when using one subcarrier 12.2 high data rate the sof includes an unmodulated time of 56.64 s, followed by 24 pulses at 423.75 khz (f c /32), and a logic 1 that consists of an unmodulated time of 18.88 s followed by 8 pulses at 423.75 khz as shown in figure 35 . figure 35. start of frame, high data rate, one subcarrier for the fast commands, the sof comprises an unmodulated time of 28.32 s, followed by 12 pulses at 423.75 khz (f c /32), and a logic 1 that consists of an unmodulated time of 9.44s followed by 4 pulses at 423.75 khz as shown in figure 36 . figure 36. start of frame, high data rate, one subcarrier x2 12.3 low data rate the sof comprises an unmodulated time of 226.56 s, followed by 96 pulses at 423.75 khz ( f c /32), and a logic 1 that consists of an unmodulated time of 75.52 s followed by 32 pulses at 423.75 khz as shown in figure 37 . figure 37. start of frame, low data rate, one subcarrier 113.28s ai12078 37.76s 56.64s ai12079 18.88s 453.12s ai12080 151.04s
M24LR64-R M24LR64-R to vcd frames doc id 15170 rev 9 51/126 for the fast commands, the sof comprises an unmodulated time of 113.28 s, followed by 48 pulses at 423.75 khz ( f c /32), and a logic 1 that includes an unmodulated time of 37.76 s followed by 16 pulses at 423.75 khz as shown in figure 38 . figure 38. start of frame, low data rate, one subcarrier x2 12.4 sof when using two subcarriers 12.5 high data rate the sof comprises 27 pulses at 484.28 khz ( f c /28), followed by 24 pulses at 423.75 khz ( f c /32), and a logic 1 that includes 9 pulses at 484.28 khz followed by 8 pulses at 423.75 khz as shown in figure 39 . for the fast commands, the x2 mode is not available. figure 39. start of frame, high data rate, two subcarriers 12.6 low data rate the sof comprises 108 pulses at 484.28 khz ( f c /28), followed by 96 pulses at 423.75 khz ( f c /32), and a logic 1 that includes 36 pulses at 484.28 khz followed by 32 pulses at 423.75 khz as shown in figure 40 . for the fast commands, the x2 mode is not available. figure 40. start of frame, low data rate, two subcarriers 226.56s ai12081 75.52s 112.39s ai12082 37.46s 449.56s ai12083 149.84s
M24LR64-R to vcd frames M24LR64-R 52/126 doc id 15170 rev 9 12.7 eof when using one subcarrier 12.8 high data rate the eof comprises a logic 0 that includes 8 pulses at 423.75 khz and an unmodulated time of 18.88 s, followed by 24 pulses at 423.75 khz ( f c /32), and by an unmodulated time of 56.64 s as shown in figure 41 . figure 41. end of frame, high data rate, one subcarriers for the fast commands, the eof comprises a logic 0 that includes 4 pulses at 423.75 khz and an unmodulated time of 9.44 s, followed by 12 pulses at 423.75 khz ( f c /32) and an unmodulated time of 37.76 s as shown in figure 42 . figure 42. end of frame, high data rate, one subcarriers x2 12.9 low data rate the eof comprises a logic 0 that includes 32 pulses at 423.75 khz and an unmodulated time of 75.52 s, followed by 96 pulses at 423.75 khz ( f c /32) and an unmodulated time of 226.56 s as shown in figure 43 . figure 43. end of frame, low data rate, one subcarriers for the fast commands, the eof comprises a logic 0 that includes 16 pulses at 423.75 khz and an unmodulated time of 37.76 s, followed by 48 pulses at 423.75 khz ( f c /32) and an unmodulated time of 113.28 s as shown in figure 44 . figure 44. end of frame, low data rate, one subcarriers x2 113.28s ai12084 37.76s 56.64s ai12085 18.88s 453.12s ai12086 151.04s 226.56s ai12087 75.52s
M24LR64-R M24LR64-R to vcd frames doc id 15170 rev 9 53/126 12.10 eof when using two subcarriers 12.11 high data rate the eof comprises a logic 0 that includes 8 pulses at 423.75 khz and 9 pulses at 484.28 khz, followed by 24 pulses at 423.75 khz ( f c /32) and 27 pulses at 484.28 khz ( f c /28) as shown in figure 45 . for the fast commands, the x2 mode is not available. figure 45. end of frame, high data rate, two subcarriers 12.12 low data rate the eof comprises a logic 0 that includes 32 pulses at 423.75 khz and 36 pulses at 484.28 khz, followed by 96 pulses at 423.75 khz ( f c /32) and 108 pulses at 484.28 khz ( f c /28) as shown in figure 46 . for the fast commands, the x2 mode is not available. figure 46. end of frame, low data rate, two subcarriers 112.39s ai12088 37.46s 449.56s ai12089 149.84s
unique identifier (uid) M24LR64-R 54/126 doc id 15170 rev 9 13 unique identifier (uid) the M24LR64-R is uniquely identified by a 64-b it unique identifier (u id). this uid complies with iso/iec 15963 and iso/iec 7816-6. the uid is a read-only code and comprises: 8 msbs with a value of e0h the ic manufacturer code of st 02h, on 8 bits (iso/iec 7816-6/am1) a unique serial number on 48 bits with the uid each M24LR64-R can be addressed uniquely and individually during the anticollision loop and for one-to-one exchange s between a vcd an d an M24LR64-R. table 18. uid format msb lsb 63 56 55 48 47 0 0xe0 0x02 unique serial number
M24LR64-R application family identifier (afi) doc id 15170 rev 9 55/126 14 application family identifier (afi) the afi (application family identifier) represent s the type of application targeted by the vcd and is used to identify, among all the M24LR64-Rs present, only the M24LR64-Rs that meet the required application criteria. figure 47. M24LR64-R decision tree for afi the afi is programmed by the M24LR64-R issuer (or purchaser) in the afi register. once programmed and locked, it can no longer be modified. the most significant nibble of th e afi is used to code one spec ific or all application families. the least significant nibble of the afi is us ed to code one specific or all application subfamilies. subfamily codes diff erent from 0 are proprietary. (see iso 15693-3 documentation) ai15130 inventory request received no no answer yes no afi value = 0 ? yes no afi flag set ? yes answer given by the m24rf64 to the inventory request afi value = internal value ?
data storage format identifier (dsfid) M24LR64-R 56/126 doc id 15170 rev 9 15 data storage format identifier (dsfid) the data storage format identifier indicates how the data is structured in the M24LR64-R memory. the logical organization of data can be known instantly using the dsfid. it can be programmed and locked using the write dsfid and lock dsfid commands. 15.1 crc the crc used in the M24LR64-R is calculated as per the definition in iso/iec 13239. the initial register contents are all ones: ?ffff?. the two-byte crc are appended to each request and response, within each frame, before the eof. the crc is calculated on all the bytes after the sof up to the crc field. upon reception of a request from the vcd, the M24LR64-R verifies that the crc value is valid. if it is invalid, the M24LR64-R discards the frame and does not answer to the vcd. upon reception of a response from the M24LR64-R, it is recommended that the vcd verifies whether the crc value is valid. if it is invalid, actions to be performed are left to the discretion of the vcd designer. the crc is transmitted least significant byte firs t. each byte is transm itted least significant bit first. table 19. crc transmission rules lsbyte msbyte lsbit msbit lsbit msbit crc 16 (8 bits) crc 16 (8 bits)
M24LR64-R M24LR64-R protocol description doc id 15170 rev 9 57/126 16 M24LR64-R protocol description the transmission protocol (or simply protoc ol) defines the mechanism used to exchange instructions and data between the vcd and the M24LR64-R, in both directions. it is based on the concept of ?vcd talks first?. this means that an M24LR64-R will not start transmitting unless it has received and properly decoded an instruction sent by the vcd. the protocol is based on an exchange of: a request from the vcd to the M24LR64-R a response from the M24LR64-R to the vcd each request and each response are contained in a frame. the frame delimiters (sof, eof) are described in section 12: M24LR64-R to vcd frames . each request consists of: a request sof (see figure 20 and figure 21 ) flags a command code parameters, depending on the command application data a 2-byte crc a request eof (see figure 22 ) each response consists of: an answer sof (see figure 35 to figure 40 ) flags parameters, depending on the command application data a 2-byte crc an answer eof (see figure 41 to figure 46 ) the protocol is bit-oriented. the number of bits transmitted in a frame is a multiple of eight (8), that is an integer number of bytes. a single-byte field is transmitted least signific ant bit (lsbit) first. a multiple-byte field is transmitted least significant byte (lsbyte) first, each byte is transmitted least significant bit (lsbit) first. the setting of the flags indicates the presence of the optional fields. when the flag is set (to one), the field is present. when the flag is reset (to zero), the field is absent. table 20. vcd request frame format request sof request_flags command code parameters data 2-byte crc request eof table 21. M24LR64-R response frame format response sof response_flags parameters data 2-byte crc response eof
M24LR64-R protocol description M24LR64-R 58/126 doc id 15170 rev 9 figure 48. M24LR64-R protocol timing vcd request frame ( ta b l e 2 0 ) request frame ( ta b l e 2 0 ) m24lr64 -r response frame ( ta b l e 2 1 ) response frame ( ta b l e 2 1 ) timing <-t 1 -> <-t 2 -> <-t 1 -> <-t 2 ->
M24LR64-R M24LR64-R states doc id 15170 rev 9 59/126 17 M24LR64-R states an M24LR64-R can be in one of 4 states: power-off ready quiet selected transitions between these states are specified in figure 49: M24LR64-R state transition diagram and table 22: M24LR64-R response depending on request_flags . 17.1 power-off state the M24LR64-R is in the power-off state when it does not receive enough energy from the vcd. 17.2 ready state the M24LR64-R is in the ready state when it receives enough energy from the vcd. when in the ready state, the M24LR64-R answers any request where the select_flag is not set. 17.3 quiet state when in the quiet state, the M24LR64-R answers any request except for inventory requests with the address_flag set. 17.4 selected state in the selected state, the M24LR64-R answers any request in all modes (see section 18: modes ): request in select mode with the select_flag set request in addressed mode if the uid matches request in non-addressed mode as it is the mode for general requests
M24LR64-R states M24LR64-R 60/126 doc id 15170 rev 9 figure 49. M24LR64-R state transition diagram 1. the M24LR64-R returns to the ?power off? state only when both conditions are met: the v cc pin is not supplied (0 v or hiz) and the tag is out of the rf fi eld. please refer to application note an3057 for more information. 2. the intention of the state transition method is that only one M24LR64-R should be in the selected state at a time. table 22. M24LR64-R response depending on request_flags flags address_flag select_flag 1 addressed 0 non addressed 1 selected 0 non selected M24LR64-R in ready or selected state (devices in quiet state do not answer) xx M24LR64-R in selected state x x M24LR64-R in ready, quiet or selected state (the device which matches the uid) xx error (03h) x x !)b 0ower/ff )nfield /utoffield 2eady 1uiet 3elected !nyother#ommand where3elect?&lag isnotset /utof2&field and no$# powersupply 3tayquiet5)$ 3elect5)$ !nyothercommand !nyothercommandwherethe !ddress?&lagisset!.$ where)nventory?&lagisnotset 3tayquiet5)$ 3elect5)$ 2esettoreadywhere 3elect?&lagis setor 3electdifferent 5)$ 2esettoready /utof2&field and no$# powersupply
M24LR64-R modes doc id 15170 rev 9 61/126 18 modes the term ?mode? refers to the mechanism used in a request to specify the set of m24lr64- rs that will answer the request. 18.1 addressed mode when the address_flag is set to 1 (addressed mode), the request contains the unique id (uid) of the addressed M24LR64-R. any M24LR64-R that receives a request with the address_flag set to 1 compares the received unique id to its own. if it matches, then the M24LR64-R executes the request (if possible) and returns a response to the vcd as specified in the command description. if the uid does not match, then it remains silent. 18.2 non-addressed mode (general request) when the address_flag is cleared to 0 (non-a ddressed mode), the request does not contain a unique id. any M24LR64-R receiving a request with the address_flag cleared to 0 executes it and returns a response to the vcd as specified in the command description. 18.3 select mode when the select_flag is set to 1 (select mode ), the request does not contain an m24lr64- r unique id. the M24LR64-R in the selected state that receives a request with the select_flag set to 1 executes it and returns a response to the vcd as specified in the command description. only M24LR64-Rs in the selected state answer a request where the select_flag set to 1. the system design ensures in theory that only one M24LR64-R can be in the select state at a time.
request format M24LR64-R 62/126 doc id 15170 rev 9 19 request format the request consists of: an sof flags a command code parameters and data a crc an eof 19.1 request flags in a request, the ?flags? field specifies the actions to be performed by the M24LR64-R and whether corresponding fields are present or not. the flags field consists of eight bits. the bit 3 (inventory_flag) of the request flag defines the contents of the 4 msbs (bits 5 to 8). when bit 3 is reset (0), bits 5 to 8 define the m24lr64- r selection criteria. when bit 3 is set (1), bits 5 to 8 define the M24LR64-R inventory parameters. table 23. general request format s o f request_flags command code parameters data crc e o f table 24. definition of request flags 1 to 4 bit no flag level description bit 1 subcarrier_flag (1) 1. subcarrier_flag refers to the M24LR64-R-to-vcd communication. 0 a single subcarrier frequency is used by the M24LR64-R 1 two subcarrier are used by the M24LR64-R bit 2 data_rate_flag (2) 2. data_rate_flag refers to the M24LR64-R-to-vcd communication 0 low data rate is used 1 high data rate is used bit 3 inventory_flag 0 the meaning of flags 5 to 8 is described in ta bl e 2 5 1 the meaning of flags 5 to 8 is described in ta bl e 2 6 bit 4 protocol_extension_flag 0 no protocol format extension 1 protocol format extension
M24LR64-R request format doc id 15170 rev 9 63/126 . table 25. request flags 5 to 8 when bit 3 = 0 bit no flag level description bit 5 select flag (1) 1. if the select_flag is set to 1, the address_flag is set to 0 and the uid field is not present in the request. 0 request is executed by any M24LR64-R according to the setting of address_flag 1 request is executed only by the M24LR64-R in selected state bit 6 address flag (1) 0 request is not addressed. uid field is not present. the request is executed by all M24LR64-Rs. 1 request is addressed. uid field is present. the request is executed only by the M24LR64-R whose uid matches the uid specified in the request. bit 7 option flag 0 option not activated. 1 option activated. bit 8 rfu 0 table 26. request flags 5 to 8 when bit 3 = 1 bit no flag level description bit 5 afi flag 0 afi field is not present 1 afi field is present bit 6 nb_slots flag 0 16 slots 11 slot bit 7 option flag 0 bit 8 rfu 0
response format M24LR64-R 64/126 doc id 15170 rev 9 20 response format the response consists of: an sof flags parameters and data a crc an eof 20.1 response flags in a response, the flags indicate how actions have been performed by the M24LR64-R and whether corresponding fields are present or not. the response flags consist of eight bits. table 27. general response format s o f response_flags parameters data crc e o f table 28. definitions of response flags 1 to 8 bit no flag level description bit 1 error_flag 0 no error 1 error detected. e rror code is in the "error" field. bit 2 rfu 0 bit 3 rfu 0 bit 4 extension flag 0 no extension bit 5 rfu 0 bit 6 rfu 0 bit 7 rfu 0 bit 8 rfu 0
M24LR64-R response format doc id 15170 rev 9 65/126 20.2 response error code if the error_flag is set by the M24LR64-R in the response, the error code field is present and provides information about the error that occurred. error codes not specified in ta bl e 2 9 are reserved for future use. table 29. response error code definition error code meaning 02h the command is not recognized, for example a format error occurred 03h the option is not supported 0fh error with no information given 10h the specified block is not available 11h the specified block is already locked and thus cannot be locked again 12h the specified block is locked an d its contents cannot be changed. 13h the specified block was not successfully programmed 14h the specified block was not successfully locked 15h the specified block is read-protected
anticollision M24LR64-R 66/126 doc id 15170 rev 9 21 anticollision the purpose of th e anticollision sequence is to invent ory the M24LR64-Rs present in the vcd field using their unique id (uid). the vcd is the master of communications with one or several M24LR64-Rs. it initiates M24LR64-R communication by issuing the inventory request. the M24LR64-R sends its response in the determined slot or does not respond. 21.1 request parameters when issuing the inventory command, the vcd: sets the nb_slots_flag as desired adds the mask length and the mask value after the command field the mask length is the number of significant bits of the mask value. the mask value is contained in an integer number of bytes. the mask length indicates the number of significant bits. lsb is transmitted first if the mask length is not a mu ltiple of 8 (bits), as many 0-bits as required will be added to the mask value msb so that the mask value is contained in an integer number of bytes the next field starts at the next byte boundary. in the example of the ta bl e 3 1 and figure 50 , the mask length is 11 bits. five 0-bits are added to the mask value msb. the 11-bit mask and the current slot number are compared to the uid. table 30. inventory request format msb lsb sof request_ flags command optional afi mask length mask value crc eof 8 bits 8 bits 8 bits 8 bits 0 to 8 bytes 16 bits table 31. example of the addition of 0-bits to an 11-bit mask value (b 15 ) msb lsb (b 0 ) 0000 0 100 1100 1111 0-bits added 11-bit mask value
M24LR64-R anticollision doc id 15170 rev 9 67/126 figure 50. principle of comparison between the mask, the slot number and the uid the afi field is present if the afi_flag is set. the pulse is generated according to the definition of the eof in iso/iec 15693-2. the first slot starts immediately after the reception of the request eof. to switch to the next slot, the vcd sends an eof. the following rules and restrictions apply: if no M24LR64-R answer is detected, the vcd may switch to the next slot by sending an eof, if one or more M24LR64-R answers are detected, the vcd waits until the complete frame has been received before sending an eof for switching to the next slot. ai06682 mask value received in the inventory command 0000 0100 1100 1111 b 16 bits the mask value less the padding 0s is loaded into the tag comparator 100 1100 1111 b 11 bits the slot counter is calculated xxxx nb_slots_flags = 0 (16 slots), slot counter is 4 bits the slot counter is concatened to the mask value xxxx 100 1100 1111 b nb_slots_flags = 0 15 bits the concatenated result is compared with the least significant bits of the tag uid. xxxx xxxx ..... xxxx xxxx x xxx xxxx xxxx xxxx 64 bits lsb msb b lsb msb lsb msb lsb msb b0 b63 compare bits ignored uid 4 bits
request processing by the M24LR64-R M24LR64-R 68/126 doc id 15170 rev 9 22 request processing by the M24LR64-R upon reception of a valid request, the M24LR64-R performs the following algorithm: nbs is the total number of slots (1 or 16) sn is the current slot number (0 to 15) lsb (value, n) function returns the n less significant bits of value msb (value, n) function returns the n most significant bits of value ?&? is the concatenation operator slot_frame is either an sof or an eof sn = 0 if (nb_slots_flag) then nbs = 1 sn_length = 0 endif else nbs = 16 sn_length = 4 endif label1: if lsb(uid, sn_length + mask_length) = lsb(sn,sn_length)&lsb(mask,mask_length) then answer to inventory request endif wait (slot_frame) if slot_frame = sof then stop anticollision decode/process request exit endif if slot_frame = eof if sn < nbs-1 then sn = sn + 1 goto label1 exit endif endif
M24LR64-R explanation of the possible cases doc id 15170 rev 9 69/126 23 explanation of the possible cases figure 51 summarizes the main poss ible cases that can occu r during an anticollision sequence when the slot number is 16. the different steps are: the vcd sends an inventory request, in a frame terminated by an eof. the number of slots is 16. M24LR64-R_1 transmits its response in slot 0. it is the only one to do so, therefore no collision occurs and its uid is rece ived and registered by the vcd; the vcd sends an eof in order to switch to the next slot. in slot 1, two M24LR64-Rs, M24LR64-R _2 and M24LR64-R_3 transmit a response, thus generating a collision. the vcd records the event and remember s that a collision was detected in slot 1. the vcd sends an eof in order to switch to the next slot. in slot 2, no M24LR64-R transmits a respon se. therefore the vcd does not detect any M24LR64-R sof and decides to switch to the next slot by sending an eof. in slot 3, there is anot her collision caused by respon ses from M24LR64-R_4 and M24LR64-R_5 the vcd then decides to send a request (for instance a read block) to M24LR64-R_1 whose uid has already been correctly received. all M24LR64-Rs detect an so f and exit the anticollision s equence. they process this request and since the request is addres sed to M24LR64-R_1, only M24LR64-R_1 transmits a response. all M24LR64-Rs are ready to receive another request. if it is an inventory command, the slot numbering sequence restarts from 0. note: the decision to interrupt the anticollision sequenc e is made by the vcd. it could have continued to send eofs until slot 16 and only then sent the request to M24LR64-R_1.
explanation of the possible cases M24LR64-R 70/126 doc id 15170 rev 9 figure 51. description of a possible anticollision sequence ai15117 slot 0 slot 1 slot 2 slot 3 vcd sof inventory request eof eof eof eof sof request to m24rf64_1 eof response 2 response 4 m24rf64 s response from m24rf64_1 response 1 response 3 response 5 timing t1 t2 t1 t2 t3 t1 t2 t1 comment no collision collision no response collision time
M24LR64-R inventory initiated command doc id 15170 rev 9 71/126 24 inventory initiated command the M24LR64-R provides a special feature to improve the inventory time response of moving tags using the initiate_flag value. this flag, controlled by the initiate command, allows tags to answer to inventory initiated commands. for applications in which multiple tags are moving in front of a reader, it is possible to miss tags using the standard inventory command. the reason is that the inventory sequence has to be performed on a global tree search. for example, a tag with a particular uid value may have to wait the run of a long tree search before being inventoried. if the delay is too long, the tag may be out of the field before it has been detected. using the initiate command, the inventory sequence is optimized. when multiple tags are moving in front of a re ader, the ones which are within th e reader field will be initiated by the initiate command. in th is case, a small batch of tags will answer to the inventory initiated command which will optimize the time necessary to identify all the ta gs. when finished, the reader has to issue a new initia te command in order to initia te a new small batch of tags which are new inside the reader field. it is also possible to reduce the inventory sequence time using the fast initiate and fast inventory initiated commands. these commands allow the M24LR64-Rs to increase their response data rate by a factor of 2, up to 53 kbit/s.
timing definition M24LR64-R 72/126 doc id 15170 rev 9 25 timing definition 25.1 t 1 : M24LR64-R response delay upon detection of the rising edge of the eof received from the vcd, the M24LR64-R waits for a time t 1nom before transmitting its response to a vcd request or before switching to the next slot during an inventory process. values of t 1 are given in ta b l e 3 2 . the eof is defined in figure 22 on page 45 . 25.2 t 2 : vcd new request delay t 2 is the time after which the vcd may send an eof to switch to the next slot when one or more M24LR64-R responses have been received during an inventory command. it starts from the reception of the eof from the M24LR64-Rs. the eof sent by the vcd may be either 10% or 100% modulated regardless of the modulation index used for transmitting the vcd request to the M24LR64-R. t 2 is also the time after which the vcd may send a new request to the M24LR64-R as described in table 48: M24LR64-R protocol timing . values of t 2 are given in ta b l e 3 2 . 25.3 t 3 : vcd new request delay in th e absence of a response from the M24LR64-R t 3 is the time after which the vcd may send an eof to switch to the next slot when no M24LR64-R response has been received. the eof sent by the vcd may be either 10% or 100% modulated regardless of the modulation index used for transmitting the vcd request to the M24LR64-R. from the time the vcd has generated the rising edge of an eof: if this eof is 100% modulated, the vcd waits a time at least equal to t 3min before sending a new eof. if this eof is 10% modulated, the vcd waits a time at least equal to the sum of t 3min + the M24LR64-R nominal response time (which depends on the M24LR64-R data rate and subcarrier modulation mode) before sending a new eof. table 32. timing values (1) 1. the tolerance of specific timings is 32/f c . minimum (min) values nominal (n om) values maximum (max) values t 1 318.6 s 320.9 s 323.3 s t 2 309.2 s no t nom no t max t 3 t 1max (2) + t sof (3) 2. t 1max does not apply for write alike requests. timing condi tions for write alike requests are defined in the command description. 3. t sof is the time taken by the M24LR64-R to transmit an sof to the vcd. t sof depends on the current data rate: high data rate or low data rate. no t nom no t max
M24LR64-R commands codes doc id 15170 rev 9 73/126 26 commands codes the M24LR64-R supports the commands described in this section. their codes are given in ta bl e 3 3 . table 33. command codes command code standard function command code custom function 01h inventory 2ch get multiple block security status 02h stay quiet b1h write-sector password 20h read single block b2h lock-sector password 21h write single block b3h present-sector password 23h read multiple block c0h fast read single block 25h select c1h fast inventory initiated 26h reset to ready c2h fast initiate 27h write afi c3h fast read multiple block 28h lock afi d1h inventory initiated 29h write dsfid d2h initiate 2ah lock dsfid 2bh get system info
commands codes M24LR64-R 74/126 doc id 15170 rev 9 26.1 inventory when receiving the inve ntory request, the M24LR64-R runs the anticollision sequence. the inventory_flag is set to 1. the meaning of flags 5 to 8 is shown in table 26: request flags 5 to 8 when bit 3 = 1 . the request contains: the flags, the inventory command code (see table 33: command codes ) the afi if the afi flag is set the mask length the mask value the crc the M24LR64-R does not generate any answer in case of error. the response contains: the flags the unique id during an inventory process, if the vcd does not receive an rf M24LR64-R response, it waits a time t 3 before sending an eof to switch to the next slot. t 3 starts from the rising edge of the request eof sent by the vcd. if the vcd sends a 100% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t sof if the vcd sends a 10% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t nrt where: t sof is the time required by the M24LR64-R to transmit an sof to the vcd t nrt is the nominal response time of the M24LR64-R t nrt and t sof are dependent on the M24LR64-R-to-vcd data rate and subcarrier modulation mode. table 34. inventory request format request sof request_flags inventory optional afi mask length mask value crc16 request eof 8 bits 01h 8 bits 8 bits 0 - 64 bits 16 bits table 35. inventory response format response sof response_ flags dsfid uid crc16 response eof 8 bits 8 bits 64 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 75/126 26.2 stay quiet command code = 0x02 on receiving the stay quiet command, the M24LR64-R enters the quiet state if no error occurs, and does not send back a response. there is no response to the stay quiet command even if an error occurs. when in the quiet state: the M24LR64-R does not process any request if the inventory_flag is set, the M24LR64-R processes any addressed request the M24LR64-R exits the quiet state when: it is reset (power off), receiving a select request. it then goes to the selected state, receiving a reset to ready request. it then goes to the ready state. the stay quiet command must always be executed in addressed mode (select_flag is reset to 0 and address_flag is set to 1). table 36. stay quiet request format request sof request flags stay quiet uid crc16 request eof 8 bits 02h 64 bits 16 bits figure 52. stay quiet frame exchange between vcd and M24LR64-R vcd sof stay quiet request eof M24LR64-R timing
commands codes M24LR64-R 76/126 doc id 15170 rev 9 26.3 read single block on receiving the read single block command, the M24LR64-R reads the requested block and sends back its 32-bit value in the response. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. the option_flag is supported. request parameters: option_flag uid (optional) block number response parameters: sector security status if option_flag is set (see table 39: sector security status ) 4 bytes of block data table 37. read single block request format request sof request_ flags read single block uid (1) 1. gray means that t he field is optional. block number crc16 request eof 8 bits 20h 64 bits 16 bits 16 bits table 38. read single block response format when error_flag is not set response sof response_flags sector security status (1) 1. gray means that t he field is optional. data crc16 response eof 8 bits 8 bits 32 bits 16 bits table 39. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use. all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 40. read single block response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 77/126 response parameter: error code as error_flag is set ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available ? 15h: the specified block is read-protected figure 53. read single block frame exchange between vcd and M24LR64-R vcd sof read single block request eof m24lr64- r <-t 1 -> sof read single block response eof
commands codes M24LR64-R 78/126 doc id 15170 rev 9 26.4 write single block on receiving the write single block command, the M24LR64-R writes the data contained in the request to the requested block and reports whether the write operation was successful in the response. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%). otherwise, the M24LR64-R may not program correctly the data into the memory. the w t time is equal to t 1nom + 18 302 s. request parameters: uid (optional) block number data response parameter: no parameter. the response is send back after the writing cycle. response parameter: error code as error_flag is set: ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available ? 12h: the specified block is locked and its contents cannot be changed. ? 13h: the specified block was not successfully programmed table 41. write single block request format request sof request_ flags write single block uid (1) 1. gray means that t he field is optional. block number data crc16 request eof 8 bits 21h 64 bits 16 bits 32 bits 16 bits table 42. write single block response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 43. write single block response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 79/126 figure 54. write single block frame exchange between vcd and M24LR64-R vcd sof write single block request eof M24LR64-R <-t 1 -> sof write single block response eof write sequence when error M24LR64-R <------------------- w t ---------------> sof write single block response eof
commands codes M24LR64-R 80/126 doc id 15170 rev 9 26.5 read multiple block when receiving the read multiple block command, the M24LR64-R reads the selected blocks and sends back their value in multiples of 32 bits in the response. the blocks are numbered from '00h to '7ffh' in the request and the value is minus one (?1) in the field. for example, if the ?number of blocks? field contains the value 06h, 7 blocks are read. the maximum number of blocks is fixed at 32 assuming that they are all located in the same sector. if the number of blocks overlaps sectors, the M24LR64-R returns an error code. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. the option_flag is supported. request parameters: option_flag uid (optional) first block number number of blocks response parameters: sector security status if option_flag is set (see table 46: sector security status ) n blocks of data table 44. read multiple block request format request sof request_ flags read multiple block uid (1) 1. gray means that t he field is optional. first block number number of blocks crc16 request eof 8 bits 23h 64 bits 16 bits 8 bits 16 bits table 45. read multiple block response format when error_flag is not set response sof response_ flags sector security status (1) 1. gray means that t he field is optional. data crc16 response eof 8 bits 8 bits (2) 2. repeated as needed. 32 bits (2) 16 bits table 46. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use. all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked
M24LR64-R commands codes doc id 15170 rev 9 81/126 response parameter: error code as error_flag is set: ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available ? 15h: the specified block is read-protected table 47. read multiple block response format when error_flag is set response sof response_flags error code crc16 response eof 8 bits 8 bits 16 bits figure 55. read multiple block frame exchange between vcd and M24LR64-R vcd sof read multiple block request eof M24LR64-R <-t 1 -> sof read multiple block response eof
commands codes M24LR64-R 82/126 doc id 15170 rev 9 26.6 select when receiving the select command: if the uid is equal to its own uid, the M24LR64-R enters or stays in the selected state and sends a response. if the uid does not match its own, the selected M24LR64-R returns to the ready state and does not send a response. the M24LR64-R answers an error code only if the uid is equal to its own uid. if not, no response is generated. if an error occurs, the M24LR64-R remains in its current state. request parameter: uid response parameter: no parameter. response parameter: error code as error_flag is set: ? 03h: the option is not supported ? 0fh: error with no information given table 48. select request format request sof request_ flags select uid crc16 request eof 8 bits 25h 64 bits 16 bits table 49. select block response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 50. select response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits figure 56. select frame exchange between vcd and M24LR64-R vcd sof select request eof m24lr64 -r <-t 1 -> sof select response eof
M24LR64-R commands codes doc id 15170 rev 9 83/126 26.7 reset to ready on receiving a reset to ready command, the M24LR64-R returns to the ready state if no error occurs. in the addressed mode, the M24LR64-R answers an error code only if the uid is equal to its own uid. if not, no response is generated. request parameter: uid (optional) response parameter: no parameter response parameter: error code as error_flag is set: ? 03h: the option is not supported ? 0fh: error with no information given table 51. reset to ready request format request sof request_ flags reset to ready uid (1) 1. gray means that t he field is optional. crc16 request eof 8 bits 26h 64 bits 16 bits table 52. reset to ready response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 53. reset to ready response format when error_flag is set response sof response_flags error code crc16 response eof 8 bits 8 bits 16 bits figure 57. reset to ready frame exchange between vcd and M24LR64-R vcd sof reset to ready request eof m24lr64- r <-t 1 -> sof reset to ready response eof
commands codes M24LR64-R 84/126 doc id 15170 rev 9 26.8 write afi on receiving the write afi request, the M24LR64-R programs the 8-bit afi value to its memory. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%). otherwise, the M24LR64-R may not write correctly the afi value into the memory. the w t time is equal to t 1nom + 18 302 s. request parameter: uid (optional) afi response parameter: no parameter. response parameter: error code as error_flag is set ? 03h: the option is not supported ? 0fh: error with no information given ? 12h: the specified block is locked and its contents cannot be changed. ? 13h: the specified block was not successfully programmed table 54. write afi request format request sof request _flags write afi uid (1) 1. gray means that t he field is optional. afi crc16 request eof 8 bits 27h 64 bits 8 bits 16 bits table 55. write afi response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 56. write afi response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 85/126 figure 58. write afi frame exchange between vcd and M24LR64-R vcd sof write afi request eof M24LR64-R <-t 1 -> sof write afi response eof write sequence when error M24LR64-R <------------------ w t --------------> sof write afi response eof
commands codes M24LR64-R 86/126 doc id 15170 rev 9 26.9 lock afi on receiving the lock afi request, the M24LR64-R locks the afi value permanently. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%). otherwise, the M24LR64-R may not lock correctly the afi value in memory. the w t time is equal to t 1nom + 18 302 s. request parameter: uid (optional) response parameter: no parameter response parameter: error code as error_flag is set ? 03h: the option is not supported ? 0fh: error with no information given ? 11h: the specified block is already locked and thus cannot be locked again ? 14h: the specified block was not successfully locked table 57. lock afi request format request sof request_ flags lock afi uid (1) 1. gray means that t he field is optional. crc16 request eof 8 bits 28h 64 bits 16 bits table 58. lock afi response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 59. lock afi response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 87/126 figure 59. lock afi frame exchange between vcd and M24LR64-R vcd sof lock afi request eof M24LR64-R <-t 1 -> sof lock afi response eof lock sequence when error M24LR64-R <----------------- w t -------------> sof lock afi response eof
commands codes M24LR64-R 88/126 doc id 15170 rev 9 26.10 write dsfid on receiving the write dsfid request, the M24LR64-R programs the 8-bit dsfid value to its memory. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%). otherwise, the M24LR64-R may not write correctly the dsfid value in memory. the w t time is equal to t 1nom + 18 302 s. request parameter: uid (optional) dsfid response parameter: no parameter response parameter: error code as error_flag is set ? 03h: the option is not supported ? 0fh: error with no information given ? 12h: the specified block is locked and its contents cannot be changed. ? 13h: the specified block was not successfully programmed table 60. write dsfid request format request sof request_ flags write dsfid uid (1) 1. gray means that t he field is optional. dsfid crc16 request eof 8 bits 29h 64 bits 8 bits 16 bits table 61. write dsfid response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 62. write dsfid response format when error_flag is set response sof response_flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 89/126 figure 60. write dsfid frame exchange between vcd and M24LR64-R vcd sof write dsfid request eof M24LR64-R <-t 1 -> sof write dsfid response eof write sequence when error M24LR64-R <---------------- w t ------------> sof write dsfid response eof
commands codes M24LR64-R 90/126 doc id 15170 rev 9 26.11 lock dsfid on receiving the lock dsfid request, the M24LR64-R locks the dsfid value permanently. the option_flag is supported. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%). otherwise, the M24LR64-R may not lock correctly the dsfid value in memory. the w t time is equal to t 1nom + 18 302 s. request parameter: uid (optional) response parameter: no parameter. response parameter: error code as error_flag is set: ? 03h: the option is not supported ? 0fh: error with no information given ? 11h: the specified block is already locked and thus cannot be locked again ? 14h: the specified block was not successfully locked table 63. lock dsfid request format request sof request_ flags lock dsfid uid (1) 1. gray means that t he field is optional. crc16 request eof 8 bits 2ah 64 bits 16 bits table 64. lock dsfid response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 65. lock dsfid response format when error_flag is set response sof response_flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 91/126 figure 61. lock dsfid frame exchange between vcd and M24LR64-R vcd sof lock dsfid request eof M24LR64-R <-t 1 -> sof lock dsfid response eof lock sequence when error M24LR64-R <----------------- w t -------------> sof lock dsfid response eof
commands codes M24LR64-R 92/126 doc id 15170 rev 9 26.12 get system info when receiving the get system info command, the M24LR64-R sends back its information data in the response.the option_flag is supported and must be reset to 0. the get system info can be issued in both addressed and non addressed modes. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. request parameter: uid (optional) response parameters: information flags set to 0fh. dsfid, afi, memory size and ic reference fields are present uid code on 64 bits dsfid value afi value memory size. the M24LR64-R provides 2048 blocks (07ffh) of 4 byte (03h) ic reference. only the 6 msb are significant. response parameter: error code as error_flag is set: ? 03h: option not supported ? 0fh: other error table 66. get system info request format request sof request _flags get system info uid (1) 1. gray means that t he field is optional. crc16 request eof 8 bits 2bh 64 bits 16 bits table 67. get system info response format when error_flag is not set response sof response _flags information flags uid dsfid afi memory size ic reference crc16 response eof 00h 0fh 64 bits 8 bits 8 bits 0307ffh 2ch 16 bits table 68. get system info response format when error_flag is set response sof response_flags error code crc16 response eof 01h 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 93/126 figure 62. get system info frame exchange between vcd and M24LR64-R vcd sof get system info request eof m24lr64 -r <-t 1 -> sof get system info response eof
commands codes M24LR64-R 94/126 doc id 15170 rev 9 26.13 get multiple bl ock security status when receiving the get multiple block security status command, the M24LR64-R sends back the sector security status. the blocks are numbered from '00h to '07ffh' in the request and the value is minus one (?1) in the field. for example, a value of '06' in the ?number of blocks? field requests to return the security status of 7 blocks. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. during the M24LR64-R response, if the internal block address counter reaches 07ffh, it rolls over to 0000h and the sector security status bytes for that location are sent back to the reader. request parameter: uid (optional) first block number number of blocks response parameters: sector security status (see table 71: sector security status ) table 69. get multiple block security status request format request sof request _flags get multiple block security status uid (1) 1. gray means that t he field is optional. first block number number of blocks crc16 request eof 8 bits 2ch 64 bits 16 bits 16 bits 16 bits table 70. get multiple block security status response format when error_flag is not set response sof response_ flags sector security status crc16 response eof 8 bits 8 bits (1) 1. repeated as needed. 16 bits table 71. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use. all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked
M24LR64-R commands codes doc id 15170 rev 9 95/126 response parameter: error code as error_flag is set: ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available table 72. get multiple block security status response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits figure 63. get multiple block security status frame exchange between vcd and M24LR64-R vcd sof get multiple block security status eof m24lr64 -r <-t 1 -> sof get multiple block security status eof
commands codes M24LR64-R 96/126 doc id 15170 rev 9 26.14 write-sector password on receiving the write-sector password command, the M24LR64-R uses the data contained in the request to write the password and reports whether the operation was successful in the response. t he option_flag is supported. during the rf write cycle time, w t , there must be no modulation at all (neither 100% nor 10%). otherwise, the M24LR64-R may not correctly program the data into the memory. the w t time is equal to t 1nom + 18 302 s. after a successful write, the new value of the selected password is automatically activated. it is not required to present the new password value until M24LR64-R power-down. request parameter: uid (optional) password number (01h = pswd1, 02h = pswd2, 03h = pswd3, other = error) data response parameter: 32-bit password value. the response is sent back after the write cycle. response parameter: error code as error_flag is set: ? 02h: the command is not recognized, for example: a format error occurred ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available ? 12h: the specified block is locked and its contents cannot be changed. ? 13h: the specified block was not successfully programmed table 73. write-sector pa ssword request format request sof request _flags write- sector password ic mfg code uid (1) 1. gray means that t he field is optional. password number data crc16 request eof 8 bits b1h 02h 64 bits 8 bits 32 bits 16 bits table 74. write-sector password response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 75. write-sector password response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 97/126 figure 64. write-sector password frame exchange between vcd and M24LR64-R vcd sof write- sector password request eof M24LR64-R <-t 1 -> sof write-sector password response eof write sequence when error M24LR64-R <----------------- w t -------------> sof write- sector password response eof
commands codes M24LR64-R 98/126 doc id 15170 rev 9 26.15 lock-sector password on receiving the lock-sector password command, the M24LR64-R sets the access rights and permanently locks the selected sector. the option_flag is supported. a sector is selected by giving the address of one of its blocks in the lock-sector password request (sector number field). for example, addresses 0 to 31 are used to select sector 0 and addresses 32 to 63 are used to select sector 1. care must be taken when issuing the lock-sector password command as all the blocks belonging to the same sector are automatically locked by a single command. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. during the rf write cycle w t , there should be no modulation (neither 100% nor 10%) otherwise, the M24LR64-R may not correctly lock the memory block. the w t time is equal to t 1nom + 18 302 s. request parameters: (optional) uid sector number sector security status (refer to ta bl e 7 7 ) response parameter: no parameter. table 76. lock-sector password request format request sof request _flags lock- sector password ic mfg code uid (1) 1. gray means that t he field is optional. sector number sector security status crc16 request eof 8 bits b2h 02h 64 bits 16 bits 8 bits 16 bits table 77. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 0 password control bits read / write protection bits 1 table 78. lock-sector password response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 79. lock-sector password response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 99/126 response parameter: error code as error_flag is set: ? 02h: the command is not recognized, for example: a format error occurred ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available ? 11h: the specified block is already locked and thus cannot be locked again ? 14h: the specified block was not successfully locked figure 65. lock-sector password frame exchange between vcd and M24LR64-R vcd sof lock-sector password request eof M24LR64-R <-t 1 -> sof lock-sector password response eof lock sequence when error M24LR64-R <---------------- w t ------------> sof lock-sector password response eof
commands codes M24LR64-R 100/126 doc id 15170 rev 9 26.16 present-sector password on receiving the present-sector password command, the M24LR64-R compares the requested password with the data contained in the request and reports whether the operation has been successful in the response. the option_flag is supported. during the comparison cycle equal to w t , there should be no modulation (neither 100% nor 10%) otherwise, the M24LR64-R the password value may not be correctly compared. the w t time is equal to t 1nom + 18 302 s. after a successful command, the access to all the memory blocks linked to the password is changed as described in section 4.1: m24lr64- r rf block security . request parameter: uid (optional) password number (0x01 = pswd1, 0x02 = pswd2, 0x03 = pswd3, other = error) data response parameter: no parameter. the response is send back after the write cycle. response parameter: error code as error_flag is set: ? 02h: the command is not recognized, for example: a format error occurred ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available table 80. present-sector password request format request sof request _flags present- sector password ic mfg code uid (1) 1. gray means that t he field is optional. password number data crc16 request eof 8 bits b3h 02h 64 bits 8 bits 32 bits 16 bits table 81. present-sector password response format when error_flag is not set response sof response_flags crc16 response eof 8 bits 16 bits table 82. present-sector password response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 101/126 figure 66. present-sector password frame exchange between vcd and M24LR64-R vcd sof present- sector password request eof M24LR64-R <-t 1 -> sof present- sector password response eof sequence when error M24LR64-R <---------------- w t ------------> sof present- sector password response eof
commands codes M24LR64-R 102/126 doc id 15170 rev 9 26.17 fast read single block on receiving the fast read single block command, the M24LR64-R reads the requested block and sends back its 32-bit value in the response. the option_flag is supported. the data rate of the response is multiplied by 2. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. request parameters: option_flag uid (optional) block number response parameters: sector security status if option_flag is set (see ta b l e 8 5 ) 4 bytes of block data table 83. fast read single block request format request sof request_ flags fast read single block ic mfg code uid (1) 1. gray means that t he field is optional. block number crc16 request eof 8 bits c0h 02h 64 bits 16 bits 16 bits table 84. fast read single block response format when error_flag is not set response sof response _flags sector security status (1) 1. gray means that t he field is optional. data crc16 response eof 8 bits 8 bits 32 bits 16 bits table 85. sector security status b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future used. all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked table 86. fast read single block response format when error_flag is set response sof response_ flags error code crc16 response eof 8 bits 8 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 103/126 response parameter: error code as error_flag is set: ? 02h: the command is not recognized, for example: a format error occurred ? 03h: the option is not supported ? 0fh: error with no information given ? 10h: the specified block is not available ? 15h: the specified block is read protected figure 67. fast read single block frame exchange between vcd and M24LR64-R vcd sof fast read single block request eof m24lr64 -r <-t 1 -> sof fast read single block response eof
commands codes M24LR64-R 104/126 doc id 15170 rev 9 26.18 fast inventory initiated before receiving the fast inventory initiated command, the M24LR64-R must have received an initiate or a fast initiate command in order to set the initiate_ flag. if not, the M24LR64-R does not answer to the fast inventory initiated command. on receiving the fast inventory initiated request, the M24LR64-R runs the anticollision sequence. the inventory_flag must be set to 1. the meaning of flags 5 to 8 is shown in table 26: request flags 5 to 8 when bit 3 = 1 . the data rate of the re sponse is multiplied by 2. the request contains: the flags, the inventory command code the afi if the afi flag is set the mask length the mask value the crc the M24LR64-R does not generate any answer in case of error. the response contains: the flags the unique id during an inventory process, if the vcd does not receive an rf M24LR64-R response, it waits a time t 3 before sending an eof to switch to the next slot. t 3 starts from the rising edge of the request eof sent by the vcd. if the vcd sends a 100% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t sof if the vcd sends a 10% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t nrt where: t sof is the time required by the M24LR64-R to transmit an sof to the vcd t nrt is the nominal response time of the M24LR64-R table 87. fast inventory initiated request format request sof request _flags fast inventory initiated ic mfg code optional afi mask length mask value crc16 request eof 8 bits c1h 02h 8 bits 8 bits 0 - 64 bits 16 bits table 88. fast inventory initiated response format response sof response _flags dsfid uid crc16 response eof 8 bits 8 bits 64 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 105/126 t nrt and t sof are dependent on the M24LR64-R-to-vcd data rate and subcarrier modulation mode. 26.19 fast initiate on receiving the fast initiate command, the M24LR64-R will set the in ternal initiate_flag and send back a response only if it is in the ready state. the command has to be issued in the non addressed mode only (select_flag is reset to 0 and address_flag is reset to 0). if an error occurs, the M24LR64-R does not generate any answer. the initiate_flag is reset after a power off of the M24LR64-R. the data rate of the response is multiplied by 2. the request contains: no data the response contains: the flags the unique id table 89. fast initiate request format request sof request_flags fast initiate ic mfg code crc16 request eof 8 bits c2h 02h 16 bits table 90. fast initiate response format response sof response _flags dsfid uid crc16 response eof 8 bits 8 bits 64 bits 16 bits figure 68. fast initiate frame exchange between vcd and M24LR64-R vcd sof fast initiate request eof m24lr64- r <-t 1 -> sof fast initiate response eof
commands codes M24LR64-R 106/126 doc id 15170 rev 9 26.20 fast read multiple block on receiving the fast read multiple block command, the M24LR64-R reads the selected blocks and sends back their value in multiples of 32 bits in the response. the blocks are numbered from '00h to '7ffh' in the request and the value is minus one (?1) in the field. for example, if the ?number of blocks? field contains the value 06h, 7 blocks are read. the maximum number of blocks is fixed to 32 assuming that they are all located in the same sector. if the number of blocks overlaps sectors, the M24LR64-R returns an error code. the protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. if the protocol_extention_flag is at 0, the M24LR64-R answers with an error code. the option_flag is supported. the data rate of the response is multiplied by 2. request parameters: option_flag uid (optional) first block number number of blocks response parameters: sector security status if option_flag is set (see table 93: sector security status if option_flag is set ) n block of data table 91. fast read multiple block request format request sof request_ flags fast read multiple block ic mfg code uid (1) 1. gray means that t he field is optional. first block number number of blocks crc16 request eof 8 bits c3h 02h 64 bits 16 bits 8 bits 16 bits table 92. fast read multiple block response format when error_flag is not set response sof response_ flags sector security status (1) 1. gray means that t he field is optional. data crc16 response eof 8 bits 8 bits (2) 2. repeated as needed. 32 bits (2) 16 bits table 93. sector security status if option_flag is set b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 reserved for future use. all at 0 password control bits read / write protection bits 0: current sector not locked 1: current sector locked
M24LR64-R commands codes doc id 15170 rev 9 107/126 response parameter: error code as error_flag is set: ? 0fh: other error ? 10h: block address not available table 94. fast read multiple block response format when error_flag is set response sof response_flags err or code crc16 response eof 8 bits 8 bits 16 bits figure 69. fast read multiple block frame exchange between vcd and M24LR64-R vcd sof fast read multiple block request eof M24LR64-R <-t 1 -> sof fast read multiple block response eof
commands codes M24LR64-R 108/126 doc id 15170 rev 9 26.21 inventory initiated before receiving the inventory initiated command, the M24LR64-R must have received an initiate or a fast initiate command in order to set the initiate_ flag. if not, the M24LR64-R does not answer to the inventory initiated command. on receiving the inventory initiated req uest, the M24LR64-R runs the anticollision sequence. the inventory_flag must be set to 1. the meaning of flags 5 to 8 is given in table 26: request flags 5 to 8 when bit 3 = 1 . the request contains: the flags, the inventory command code the afi if the afi flag is set the mask length the mask value the crc the M24LR64-R does not generate any answer in case of error. the response contains: the flags the unique id during an inventory process, if the vcd does not receive an rf M24LR64-R response, it waits a time t 3 before sending an eof to switch to the next slot. t 3 starts from the rising edge of the request eof sent by the vcd. if the vcd sends a 100% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t sof if the vcd sends a 10% modulated eof, the minimum value of t 3 is: t 3 min = 4384/f c (323.3s) + t nrt where: t sof is the time required by the M24LR64-R to transmit an sof to the vcd t nrt is the nominal response time of the M24LR64-R t nrt and t sof are dependent on the M24LR64-R-to-vcd data rate and subcarrier modulation mode. table 95. inventory initiated request format request sof request _flags inventory initiated ic mfg code optional afi mask length mask value crc16 request eof 8 bits d1h 02h 8 bits 8 bits 0 - 64 bits 16 bits table 96. inventory initiated response format response sof response _flags dsfid uid crc16 response eof 8 bits 8 bits 64 bits 16 bits
M24LR64-R commands codes doc id 15170 rev 9 109/126 26.22 initiate on receiving the initiate co mmand, the M24LR64-R will set the internal initiate_flag and send back a response only if it is in the ready state. the command has to be issued in the non addressed mode only (select_flag is reset to 0 and address_flag is reset to 0). if an error occurs, the M24LR64-R does not generate any answer. the initiate_flag is reset after a power off of the M24LR64-R. the request contains: no data the response contains: the flags the unique id table 97. initiate request format request sof request_flags initiate ic mfg code crc16 request eof 8 bits d2h 02h 16 bits table 98. initiate initiated response format response sof response _flags dsfid uid crc16 response eof 8 bits 8 bits 64 bits 16 bits figure 70. initiate frame exchange between vcd and M24LR64-R vcd sof initiate request eof m24lr64 -r <-t 1 -> sof initiate response eof
maximum rating M24LR64-R 110/126 doc id 15170 rev 9 27 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 99. absolute maximum ratings symbol parameter min. max. unit t a ambient operating temperature ?40 85 c t stg , h stg , t stg storage conditions wafer 15 25 c 23 months kept in its antistatic bag t stg storage temperature ufdfpn8 (mlp8), so8, tssop8 ?65 150 c t lead lead temperature during soldering ufdfpn8 (mlp8), so8, tssop8 see note (1) 1. compliant with jedec std j-std-020c (for smal l body, sn-pb or pb assembly), the st ecopack ? 7191395 specification, and the european directive on re strictions on hazardous substances (rohs) 2002/95/eu. c v io i 2 c input or output range ?0.50 6.0 v v cc i 2 c supply voltage ?0.50 6.0 v i cc rf supply current on ac0 / ac1 ?20 20 ma v max rf input voltage on ac0 / ac1 ?7 7 v v esd electrostatic discharge voltage (human body model) (2) 2. aec-q100-002 (compliant with jedec std jesd22-a114a, c1 = 100 pf, r1 = 1500 ? , r2 = 500 ? ) ac0, ac1 ?800 800 v other pads ?3000 3000 electrostatic discharge voltage (machine model) ?100 100
M24LR64-R i 2 c dc and ac parameters doc id 15170 rev 9 111/126 28 i 2 c dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device in i 2 c mode. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 71. ac test measurement i/o waveform table 100. i 2 c operating conditions symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 101. ac test measurement conditions symbol parameter min. max. unit c l load capacitance 100 pf input rise and fall times 50 ns input levels 0.2v cc to 0.8v cc v input and output timing reference levels 0.3v cc to 0.7v cc v table 102. input parameters symbol parameter min. max. unit c in input capacitance (sda) - 8 pf c in input capacitance (other pins) - 6 pf t ns (1) 1. characterized only. pulse width ignored (input filter on scl and sda) - 80 ns ai00825b 0.8v cc 0.2v cc 0.7v cc 0.3v cc input and output timing reference levels input levels
i 2 c dc and ac parameters M24LR64-R 112/126 doc id 15170 rev 9 table 103. i 2 c dc characteristics symbol parameter test condition min. max. unit i li input leakage current (scl, sda, e1, e0) v in = v ss or v cc device in standby mode 2 a i lo output leakage current sda in hi-z, external voltage applied on sda: v ss or v cc 2 a i cc supply current (read) (1) 1. scl, sda according to ac input waveform figure 71 . e0, e1 connected to ground or v cc v cc = 1.8 v, f c = 400 khz (rise/fall time < 50 ns) 100 a v cc = 2.5 v, f c = 400 khz (rise/fall time < 50 ns) 200 v cc = 5.5 v, f c = 400 khz (rise/fall time < 50 ns) 500 i cc0 supply current (write) (1) during t w , v cc = 1.8 v 300 (2) 2. characterized value, not tested in production. a during t w , v cc = 2.5 v 400 (2) during t w , v cc = 5.5 v 700 (2) i cc1 standby supply current v in = v ss or v cc v cc = 1.8 v 30 a v in = v ss or v cc v cc = 2.5 v 30 v in = v ss or v cc v cc = 5.5 v 40 v il input low voltage (sda, scl) v cc = 1.8 v ?0.45 0.25v cc v v cc = 2.5 v ?0.45 0.25v cc v cc = 5.5 v ?0.45 0.3v cc v ih input high voltage (sda, scl) v cc = 1.8 v 0.75v cc v cc +1 v v cc = 2.5 v 0.75v cc v cc +1 v cc = 5.5 v 0.7v cc v cc +1 v ol output low voltage i ol = 2.1 ma, v cc = 1.8 v or i ol = 3 ma, v cc = 5.5 v 0.4 v
M24LR64-R i 2 c dc and ac parameters doc id 15170 rev 9 113/126 table 104. i 2 c ac characteristics test conditions specified in table 100 symbol alt. parameter min. max. unit f c f scl clock frequency 400 khz t chcl t high clock pulse width high 600 ns t clch t low clock pulse width low 1300 ns t xh1xh2 (1) 1. values recommended by the i2 c-bus fast-mode specification. t r input signal rise time 20 300 ns t xl1xl2 (1) t f input signal fall time 20 300 ns t dl1dl2 t f sda (out) fall time 20 100 ns t dxcx t su:dat data in set up time 100 ns t cldx t hd:dat data in hold time 0 ns t clqx t dh data out hold time 100 ns t clqv (2)(3) 2. to avoid spurious start and st op conditions, a minimum delay is pl aced between scl=1 and the falling or rising edge of sda. 3. t clqv is the time (from the falling edge of scl) required by the sda bus line to reach 0.8v cc in a compatible way with the i 2 c specification (which specifies t su:dat (min) = 100 ns), assuming that the r bus c bus time constant is less than 500 ns (as specified in figure 4 ). t aa clock low to next data valid (access time) 100 900 ns t chdx (4) 4. for a restart condition, or following a write cycle. t su:sta start condition set up time 600 ns t dlcl t hd:sta start condition hold time 600 ns t chdh t su:sto stop condition set up time 600 ns t dhdl t buf time between stop condition and next start condition 1300 ns t w i2c write time 5 ms
i 2 c dc and ac parameters M24LR64-R 114/126 doc id 15170 rev 9 figure 72. i 2 c ac waveforms scl sda in scl sda out scl sda in tchcl tdlcl tchdx start condition tclch tdxcx tcldx sda input sda change tchdh tdhdl stop condition data valid tclqv tclqx tchdh stop condition tchdx start condition write cycle tw ai00795e start condition tchcl txh1xh2 txh1xh2 txl1xl2 txl1xl2 data valid tdl1dl2
M24LR64-R rf dc and ac parameters doc id 15170 rev 9 115/126 29 rf dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device in rf mode. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 105. rf ac characteristics (1) (2) symbol parameter condition min typ max unit f cc external rf signal frequency 13.553 13.56 13.567 mhz h_iso operating field according to iso t a = 0 c to 50 c 150 5000 ma/ m h_extended operating field in extended temperature range t a = ?40 c to 85 c 150 3500 ma/ m mi carrier 10% carrier modulation index (3) (4) mi=(a-b)/(a+b) 150 ma/m > h_iso > 1000 ma/m 15 30 % h_iso > 1000 ma/m 10 30 t rfr ,t rff 10% rise and fall time 0.5 3.0 s t rfsbl 10% minimum pulse width for bit 7.1 9.44 s mi carrier 100% carrier modulation index mi=(a-b)/(a+b) 95 100 % t rfr ,t rff 100% rise and fall time 0.5 3.5 s t rfsbl 100% minimum pulse width for bit 7.1 9.44 s t jit bit pulse jitter -2 +2 s t min cd minimum time from carrier generation to first data from h-field min 0.1 1 ms f sh subcarrier frequency high f cc /32 423.75 khz f sl subcarrier frequency low f cc /28 484.28 khz t 1 time for M24LR64-R response 4224/f s 318.6 320.9 323.3 s t 2 time between commands 4224/f s 309 311.5 314 s w t rf write time (including internal verify) 5.75 ms 1. t a = ?40 to 85 c. 2. all timing measurements were performed between 0 c and 50 c on a reference antenna with the following characteristics: external size: 75 mm x 48 mm number of turns: 5 width of conductor: 5 mm space between 2 conductors: 0.3 mm value of the tuning capacitor in so8: 27.5 pf (M24LR64-R) value of the coil: 5 h tuning frequency: 13.56 mhz. 3. characterized only, not 100% tested 4. 15% (or more) carrier modulation index offers a better signal/ noise ratio and therefore a wider operating range with a better noise immunity
rf dc and ac parameters M24LR64-R 116/126 doc id 15170 rev 9 figure 73 shows an ask modulated signal, from the vcd to the m2 4lr64-r. the test condition for the ac/dc parameters are: close coupling condition with tester antenna (1 mm) M24LR64-R performance measured at the tag antenna figure 73. M24LR64-R synchronous timing, transmit and receive table 106. rf dc characteristics (1) 1. t a = ?40 to 85 c. symbol parameter test conditions min. typ. max. unit v cc limited voltage 2.0 v v back backscattered level as defined by iso test iso10373-7 10 mv i cc supply current read v cc = 2.0 v 50 a write v cc = 2.0 v 150 a c tun internal tuning capacitor in so8 (2) 2. characterised only, at room temperature only, measured at v ac0-ac1 = 0.5 v peak. f = 13.56 mhz 24.8 27.5 30.2 pf table 107. operating conditions symbol parameter min. max. unit t a ambient operating temperature ?40 85 c ai06680 ab t rff t rfr t rfsbl t max t min cd f cc
M24LR64-R package mechanical data doc id 15170 rev 9 117/126 30 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 74. so8n ? 8-lead plastic small outlin e, 150 mils body width, package outline 1. drawing is not to scale. table 108. so8n ? 8-lead plastic small outline, 150 mils body width, package data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.75 0.0689 a1 0.10 0.25 0.0039 0.0098 a2 1.25 0.0492 b 0.28 0.48 0.0110 0.0189 c 0.17 0.23 0.0067 0.0091 ccc 0.10 0.0039 d 4.90 4.80 5.00 0.1929 0.1890 0.1969 e 6.00 5.80 6.20 0.2362 0.2283 0.2441 e1 3.90 3.80 4.00 0.1535 0.1496 0.1575 e1.27? ?0.0500? ? h 0.25 0.50 k 08 08 l 0.40 1.27 0.0157 0.0500 l1 1.04 0.0410 so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane
package mechanical data M24LR64-R 118/126 doc id 15170 rev 9 figure 75. ufdfpn8 (mlp8) ? ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline 1. drawing is not to scale. table 109. ufdfpn8 (mlp8) ? ultra thin fine pitch dual flat package no lead 2 x 3 mm, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 0.55 0.45 0.6 0.0217 0.0177 0.0236 a1 0.02 0 0.05 0.0008 0 0.002 b 0.25 0.2 0.3 0.0098 0.0079 0.0118 d 2 1.9 2.1 0.0787 0.0748 0.0827 d2 1.6 1.5 1.7 0.063 0.0591 0.0669 e 3 2.9 3.1 0.1181 0.1142 0.122 e2 0.2 0.1 0.3 0.0079 0.0039 0.0118 e 0.5 - - 0.0197 - - l 0.45 0.4 0.5 0.0177 0.0157 0.0197 l1 0.15 0.0059 l3 0.3 0.0118 ddd (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. 0.08 0.0031 d e ufdfpn-01 a a1 ddd l1 e b d2 l e2 l3
M24LR64-R package mechanical data doc id 15170 rev 9 119/126 figure 76. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 110. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. typ min max typ min max a 1.2 0.0472 a1 0.05 0.15 0.002 0.0059 a2 1 0.8 1.05 0.0394 0.0315 0.0413 b 0.19 0.3 0.0075 0.0118 c 0.09 0.2 0.0035 0.0079 cp 0.1 0.0039 d 3 2.9 3.1 0.1181 0.1142 0.122 e 0.65 - - 0.0256 - - e 6.4 6.2 6.6 0.252 0.2441 0.2598 e1 4.4 4.3 4.5 0.1732 0.1693 0.1772 l 0.6 0.45 0.75 0.0236 0.0177 0.0295 l1 1 0.0394 a 08 08 n8 8 tssop8am 1 8 cp c l e e1 d a2 a e b 4 5 a1 l1
part numbering M24LR64-R 120/126 doc id 15170 rev 9 31 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 111. ordering information scheme example: M24LR64-R - mn 6 t /2 device type m24lr64 = dual-access eerpom operating voltage r = v cc = 1.8 v to 5.5 v package mn = so8n (150 mils width) mb = ufdfpn8 (mlp8) dw = tssop8 device grade 6 = industrial: device tested with standard test flow over ?40 to 85 c option t = tape and reel packing capacitance /2 = 27.5 pf
M24LR64-R anticollision algorithm (informative) doc id 15170 rev 9 121/126 appendix a anticollision algorithm (informative) the following pseudocode describes how anti collision could be implemented on the vcd, using recursivity. a.1 algorithm for pulsed slots function push (mask, address); pushes on private stack function pop (mask, address); pops from private stack function pulse_next_pause; generates a power pulse function store(M24LR64-R_uid); stores M24LR64-R_uid function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask ; send the request mode = anticollision send_request (request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR64-R is inventoried then store (M24LR64-R_uid) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle
crc (informative) M24LR64-R 122/126 doc id 15170 rev 9 appendix b crc (informative) b.1 crc error detection method the cyclic redundancy check (crc) is calculated on all data contained in a message, from the start of the flags through to the end of data. the crc is used from vcd to M24LR64-R and from M24LR64-R to vcd. to add extra protection against shifting errors, a further transformation on the calculated crc is made. the one?s complement of the calculated crc is the value attached to the message for transmission. to check received messages the 2 crc bytes are often also included in the re-calculation, for ease of use. in this case, the expected value for the generated crc is the residue f0b8h. b.2 crc calculation example this example in c language illustrates one met hod of calculating the crc on a given set of bytes comprising a message. c-example to calculate or check the crc16 according to iso/iec 13239 #define polynomial0x8408// x^16 + x^12 + x^5 + 1 #define preset_value0xffff #define check_value0xf0b8 #define number_of_bytes4// example: 4 data bytes #define calc_crc1 #define check_crc0 void main() { unsigned int current_crc_value; unsigned char array_of_databytes[number_of_bytes + 2] = {1, 2, 3, 4, 0x91, 0x39}; int number_of_databytes = number_of_bytes; int calculate_or_check_crc; int i, j; calculate_or_check_crc = calc_crc; // calculate_or_check_crc = check_crc;// this could be an other example if (calculate_or_check_crc == calc_crc) { table 112. crc definition crc definition crc type length polynomial direction preset residue iso/iec 13239 16 bits x 16 + x 12 + x 5 + 1 = 8408h backward ffffh f0b8h
M24LR64-R crc (informative) doc id 15170 rev 9 123/126 number_of_databytes = number_of_bytes; } else // check crc { number_of_databytes = number_of_bytes + 2; } current_crc_value = preset_value; for (i = 0; i < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for (j = 0; j < 8; j++) { if (current_crc_value & 0x0001) { current_crc_value = (current_crc_value >> 1) ^ polynomial; } else { current_crc_value = (current_crc_value >> 1); } } } if (calculate_or_check_crc == calc_crc) { current_crc_value = ~current_crc_value; printf ("generated crc is 0x%04x\n", current_crc_value); // current_crc_value is now ready to be appended to the data stream // (first lsbyte, then msbyte) } else // check crc { if (current_crc_value == check_value) { printf ("checked crc is ok (0x%04x)\n", current_crc_value); } else { printf ("checked crc is not ok (0x%04x)\n", current_crc_value); } } }
application family identifier (afi) (informative) M24LR64-R 124/126 doc id 15170 rev 9 appendix c application family identifier (af i) (informative) the afi (application family identifier) represents the type of application targeted by the vcd and is used to extract from all the M24LR64-R present only the M24LR64-R meeting the required application criteria. it is programmed by the M24LR64-R issuer (the purchaser of the M24LR64-R). once locked, it cannot be modified. the most significant nibble of the afi is used to code one specific or all application families, as defined in ta b l e 1 1 3 . the least significant nibble of the afi is us ed to code one specific or all application subfamilies. subfamily codes diff erent from 0 are proprietary. table 113. afi coding (1) 1. x = '1' to 'f', y = '1' to 'f' afi most significant nibble afi least significant nibble meaning viccs respond from examples / note ?0? ?0? all families and subfamilies no applicative preselection ?x? '0 'all subfamilies of family x wide applicative preselection 'x '?y? only the yth subfamily of family x ?0? ?y? proprietary subfamily y only ?1 '?0?, ?y? transport mass transit, bus, airline,... '2 '?0?, ?y? financial iep, banking, retail,... '3 '?0?, ?y? identification access control,... '4 '?0?, ?y? telecommunication public telephony, gsm,... ?5? ?0?, ?y? medical '6 '?0?, ?y? multimedia internet services.... '7 '?0?, ?y? gaming 8 '?0?, ?y? data storage portable files,... '9 '?0?, ?y? item management 'a '?0?, ?y? express parcels 'b '?0?, ?y? postal services 'c '?0?, ?y? airline bags 'd '?0?, ?y? rfu 'e '?0?, ?y? rfu ?f? ?0?, ?y? rfu
M24LR64-R revision history doc id 15170 rev 9 125/126 revision history table 114. document revision history date revision changes 26-feb-2010 8 previous revisions: design and engineering phase. initial public release. 06-apr-2010 9 updated section 28 and section 29 following product characterisation
M24LR64-R 126/126 doc id 15170 rev 9 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of M24LR64-R

	To Download M24LR64-R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .