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d a t a sh eet product speci?cation supersedes data of 1998 jul 29 2003 may 19 integrated circuits 74lvc373a octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state
2003 may 19 2 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a features 5 v tolerant inputs/outputs for interfacing with 5 v logic wide supply voltage range from 1.2 to 3.6 v cmos low power consumption direct interface with ttl levels inputs accept voltages up to 5.5 v high-impedance outputs when v cc =0v complies with jedec standard no. 8-1a esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v specified from - 40 to +85 c and - 40 to +125 c. description the 74lvc373a is a high-performance, low-power, low-voltage, si-gate cmos device, superior to most advanced cmos compatible ttl families. inputs can be driven from either 3.3 or 5 v devices. in 3-state operation, outputs can handle 5 v. this feature allows the use of these devices as translators in a mixed 3.3 and 5 v environment. the 74lvc373a is an octal d-type transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus-oriented applications. a latch enable input (pin le) and an output enable input (pin oe) are common to all internal latches. the 74lvc373a consists of eight d-type transparent latches with 3-state true outputs. when pin le is high, data at the d-inputs (pins d0 to d7) enters the latches. in this condition, the latches are transparent, i.e. a latch output will change each time its corresponding d-input changes. when pin le is low, the latches store the information that was present at the d-inputs one set-up time preceding the high-to-low transition of pin le. when pin oe is low, the contents of the eight latches are available at the q-outputs (pins q0 to q7). when pin oe is high, the outputs go to the high-impedance off-state. operation of input pin oe does not affect the state of the latches. the 74lvc373a is functionally identical to the 74lvc573a, but the 74lvc573a has a different pin arrangement. quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc . symbol parameter conditions typical unit t phl /t plh propagation delay c l = 50 pf; v cc = 3.3 v dn to qn 3.0 ns le to qn 3.1 ns c i input capacitance 5.0 pf c pd power dissipation capacitance per latch v cc = 3.3 v; notes 1 and 2 14 pf
2003 may 19 3 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a function table see note 1. note 1. h = high voltage level; h = high voltage level one setup time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one setup time prior to the high-to-low le transition; x = dont care; z = high-impedance off-state. ordering information operating modes input internal latches output oe le dn qn enable and read register (transparent mode) lhlll lhhhh latch and read register l l l l l llhhh latch register and disable outputs h x x x z type number package temperature range pins package material code 74lvc373ad - 40 to +125 c 20 so20 plastic sot163-1 74lvc373adb - 40 to +125 c 20 ssop20 plastic sot339-1 74lvc373apw - 40 to +125 c 20 tssop20 plastic sot360-1 74LVC373ABQ - 40 to +125 c 20 dhvqfn20 plastic sot764-1 pinning pin symbol description 1 oe output enable input (active low) 2 q0 latch output 3 d0 data input 4 d1 data input 5 q1 latch output 6 q2 latch output 7 d2 data input 8 d3 data input 9 q3 latch output 10 gnd ground (0 v) 11 le latch enable input (active high) 12 q4 latch output 13 d4 data input 14 d5 data input 15 q5 latch output 16 q6 latch output 17 d6 data input 18 d7 data input 19 q7 latch output 20 v cc supply voltage pin symbol description
2003 may 19 4 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a handbook, halfpage 1 2 3 4 5 6 7 8 9 q0 d0 d1 q1 q2 d2 d3 q3 19 18 17 16 15 14 13 12 q7 d7 d6 q6 q5 d5 d4 q4 20 1oe v cc 10 11 gnd top view le gnd (1) mdb199 fig.1 pin configuration dhvqfn20. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. handbook, halfpage oe q0 d0 d1 q1 q2 d2 d3 q3 gnd v cc q7 d7 d6 q5 d5 q6 d4 q4 le 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 mna879 373a fig.2 pin configuration so20 and (t)ssop20. handbook, halfpage mna881 d0 d1 d2 d3 d4 d5 d6 d7 q0 q1 q2 q3 q4 q5 q6 q7 le 11 1 18 17 14 13 8 7 4 3 19 16 15 12 9 6 5 2 oe fig.3 logic symbol. a ndbook, halfpage mna880 19 16 15 12 9 6 5 1 en 11 c1 1d 2 18 17 14 13 8 7 4 3 fig.4 logic symbol (ieee/iec).
2003 may 19 5 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a handbook, halfpage mna882 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 19 16 15 12 9 6 5 2 d0 d1 d2 d3 d4 d5 d6 d7 le oe 18 11 1 17 14 13 8 7 4 3 fig.5 functional diagram. handbook, halfpage q le d le le le mna189 fig.6 logic diagram (one latch). handbook, full pagewidth mna883 q4 d4 d le q q3 d3 d le q q2 d2 d le q q1 d1 d le le le q q0 d0 dq le oe le le le le q5 d5 d le q le q6 d6 d le q le q7 d7 d le q le fig.7 logic diagram.
2003 may 19 6 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so20 packages: above 70 c derate linearly with 8 mw/k. for ssop20 and tssop20 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn20 packages: above 60 c derate linearly with 4.5 mw/k. symbol parameter conditions min. max. unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low-voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage high or low state 0 v cc v 3-state 0 5.5 v t amb operating ambient temperature in free air - 40 +125 c t r , t f input rise and fall times v cc = 1.2 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +6.5 v i ik input diode current v i <0 -- 50 ma v i input voltage note 1 - 0.5 +6.5 v i ok output diode current v o >v cc or v o <0 - 50 ma v o output voltage high or low state; note 1 - 0.5 v cc + 0.5 v 3-state; note 1 - 0.5 +6.5 v i o output source or sink current v o = 0 to v cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation t amb = - 40 to +125 c; note 2 - 500 mw
2003 may 19 7 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a dc characteristics at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb = - 40 to +85 c ; note 1 v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 2.7 to 3.6 v cc - 0.2 -- v i o = - 12 ma 2.7 v cc - 0.5 -- v i o = - 18 ma 3.0 v cc - 0.6 -- v i o = - 24 ma 3.0 v cc - 0.8 -- v v ol low-level output voltage v i =v ih or v il i o = 100 m a 2.7 to 3.6 -- 0.2 v i o =12ma 2.7 -- 0.4 v i o =24ma 3.0 -- 0.55 v i li input leakage current v i = 5.5 v or gnd 3.6 - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd 3.6 - 0.1 5 m a i off power-off leakage current v i or v o = 5.5 v 0.0 - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 - 0.1 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0 2.7 to 3.6 - 5 500 m a
2003 may 19 8 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a note 1. all typical values are measured at v cc = 3.3 v and t amb =25 c. t amb = - 40 to +125 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 2.7 to 3.6 v cc - 0.3 -- v i o = - 12 ma 2.7 v cc - 0.65 -- v i o = - 18 ma 3.0 v cc - 0.75 -- v i o = - 24 ma 3.0 v cc - 1.0 -- v v ol low-level output voltage v i =v ih or v il i o = 100 m a 2.7 to 3.6 -- 0.3 v i o =12ma 2.7 -- 0.6 v i o =24ma 3.0 -- 0.8 v i li input leakage current v i = 5.5 v or gnd 3.6 -- 20 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 5.5 v or gnd 3.6 -- 20 m a i off power-off leakage current v i or v o = 5.5 v 0.0 -- 20 m a i cc quiescent supply current v i =v cc or gnd; i o =0 3.6 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o =0 2.7 to 3.6 -- 5000 m a symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 may 19 9 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a ac characteristics gnd = 0 v; t r =t f 2.5 ns; c l = 50 pf; r l = 500 w . symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c t phl /t plh propagation delay dn to qn see figs 8 and 12 1.2 - 14 - ns 2.7 1.5 3.5 7.8 ns 3.0 to 3.6 1.5 3.0 (1) 6.8 ns propagation delay le to qn see figs 9 and 12 1.2 - 16 - ns 2.7 1.5 3.4 8.2 ns 3.0 to 3.6 1.5 3.1 (1) 7.2 ns t pzh /t pzl 3-state output enable time oe to qn see figs 10 and 12 1.2 - 17 - ns 2.7 1.5 4.2 8.7 ns 3.0 to 3.6 1.5 3.4 (1) 7.7 ns t phz /t plz 3-state output disable time oe to qn see figs 10 and 12 1.2 - 8.0 - ns 2.7 1.5 3.3 7.1 ns 3.0 to 3.6 1.5 2.9 (1) 6.1 ns t w le pulse width high see fig.9 2.7 3.0 -- ns 3.0 to 3.6 3.0 1.5 (1) - ns t su set-up time dn to le see fig.11 2.7 2.0 -- ns 3.0 to 3.6 2.0 0 (1) - ns t h hold time dn to le see fig.11 2.7 1.5 -- ns 3.0 to 3.6 1.5 0.3 (1) - ns t sk(0) skew note 2 --- 1.0 ns
2003 may 19 10 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a notes 1. typical values are measured at v cc = 3.3 v and t amb =25 c. 2. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. t amb = - 40 to +125 c t phl /t plh propagation delay dn to qn see figs 8 and 12 2.7 1.5 - 10.0 ns 3.0 to 3.6 1.5 - 8.5 ns propagation delay le to qn see figs 9 and 12 2.7 1.5 - 10.5 ns 3.0 to 3.6 1.5 - 9.0 ns t pzh /t pzl 3-state output enable time oe to qn see figs 10 and 12 2.7 1.5 - 11.0 ns 3.0 to 3.6 1.5 - 10.0 ns t phz /t plz 3-state output disable time oe to qn see figs 10 and 12 2.7 1.5 - 9.0 ns 3.0 to 3.6 1.5 - 8.0 ns t w le pulse width high see fig.9 2.7 4.5 -- ns 3.0 to 3.6 4.5 -- ns t su set-up time dn to le see fig.11 2.7 2.0 -- ns 3.0 to 3.6 2.0 -- ns t h hold time dn to le see fig.11 2.7 1.5 -- ns 3.0 to 3.6 1.5 -- ns t sk(0) skew note 2 --- 1.5 ns symbol parameter test conditions min. typ. max. unit waveforms v cc (v) ac waveforms handbook, halfpage mna884 dn input qn output t phl t plh gnd v i v m v m v oh v ol fig.8 input (dn) to output (qn) propagation delays. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5 v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load.
2003 may 19 11 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a handbook, full pagewidth mna885 le input qn output t phl t plh t w v m v oh v i gnd v ol v m fig.9 latch enable input (le) pulse width, the latch enable input to output (qn) propagation delays. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load. handbook, full pagewidth mna886 t plz t phz output disabled output enabled v y v x output enabled qn output low-to-off off-to-low qn output high-to-off off-to-high oe input v ol v oh v cc v i v m gnd gnd t pzl t pzh v m v m fig.10 3-state enable and disable times. v m = 0.5v cc at v cc < 2.7 v; v m = 1.5 v at v cc 3 2.7 v; v x =v ol + 0.1v cc at v cc < 2.7 v; v x =v ol + 0.3 v at v cc 3 2.7 v; v y =v oh - 0.1v cc at v cc < 2.7 v; v y =v oh - 0.3 v at v cc 3 2.7 v. v ol and v oh are the typical output voltage drop that occur with the output load.
2003 may 19 12 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a handbook, full pagewidth mna887 t h t su t h t su v m v m v i gnd v i gnd le input dn input fig.11 data set-up and hold times for the dn input to the le input. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5 v cc at v cc < 2.7 v. the shaded areas indicate when the input is permitted to change for predictable output performance. handbook, full pagewidth open gnd 2 v cc v cc v i v o mna888 d.u.t. c l = 50 pf r t r l = 500 w r l = 500 w pulse generator s 1 fig.12 load circuitry for switching times. test s 1 t plh /t phl open t plz /t pzl 2 v cc t phz /t pzh gnd v cc v i <2.7 v v cc 2.7 to 3.6 v 2.7 v definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator.
2003 may 19 13 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
2003 may 19 14 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p q (1) z y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 0.9 0.7 0.9 0.5 8 0 o o 0.13 1.25 0.2 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.2 mm maximum per side are not included. 1.03 0.63 sot339-1 mo-150 99-12-27 03-02-19 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 110 20 11 y 0.25 pin 1 index 0 2.5 5 mm scale ssop20: plastic shrink small outline package; 20 leads; body width 5.3 mm sot339-1 a max. 2
2003 may 19 15 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
2003 may 19 16 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 4.6 4.4 d h 3.15 2.85 y 1 2.6 2.4 1.15 0.85 e 1 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot764-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot764-1 dhvqfn20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 29 19 12 11 10 1 20 x d e c b a terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
2003 may 19 17 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 220 c (snpb process) or below 245 c (pb-free process) C for all the bga packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 may 19 18 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso, vssop not recommended (6) suitable
2003 may 19 19 philips semiconductors product speci?cation octal d-type transparent latch with 5 v tolerant inputs/outputs; 3-state 74lvc373a data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/02/pp 20 date of release: 2003 may 19 document order number: 9397 750 10551

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