single output clock generator idt5v926a data sheet idt5v926a revision a june 11, 2009 1 ? 2009 integrated device technology, inc. description: the idt5v926a is a low-cost, low skew, low jitter, and high-performance clock multiplier with a reference clock from either a lower frequency crystal or clock input. it has been specially designed to interface with gigabit ethernet and fast ethernet applications by providing a 125mhz clock from 25mhz input. it can be programmed to provide output frequencies ranging from 48mhz to 160mhz, with input frequencies ranging from 6mhz to 80mhz. the idt5v926a includes an internal rc filter that pro- vides excellent jitter characteristics and eliminates the need for external components. when using the optional crystal input, the device accepts a 10 - 40mhz fundamental mode crystal with a maximum equivalent series resistance of 50 . features: ? 3v to 3.6v operating voltage ? 48mhz to 160mhz output frequency range ? input from fundamental crystal oscillator or external source ? internal pll feedback (loading the feedback output relative to the other outputs, will adjust the propagation delay between ref inputs and outputs) ? select inputs (s [1:0] ) for fb divide selection (multiply ratio of 2, 3, 4, 4.25, 5, 6, 6.25, and 8) ? low jitter ? pll bypass for testing and power-down control (s1 = h, s0 = h, powers part down <500a) ? available in tssop package ? pin and function compatible to idt5v926 applications: ? gigabit ethernet ? router ? network switches ? san ? instrumentation ? fibre channel functional block diagram x1/ref x2 crystal oscillator phase detector charge pump loop filter vco select mode q out q ref s1 s0 oe vco divide 1/n refe 0 1
dt5v926a revision a june 11, 2009 2 ? 2009 integrated device technology, inc. idt5v926a data sheet single output clock generator 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 refe x 1 /ref x 2 v dd v ddq q ref v ddq s 1 oe gnd v ddq gnd q out v ddq s 0 gnd pin configuration tssop top view crystal specification the crystal oscillators should be fundamental mode quartz crystals: overtone crystals are not suitable. crystal frequency should be specified for parallel resonance with 50 maximum equivalent series resonance. crystal tuning capacitors should be connected from x1/ref to gnd and from x2 to gnd. notes: 1. h = high, m = mid, l = low 2. test mode for low frequency testing. in this mode, ref clock bypasses the vco (vco powered down) and the crystal oscillator is powered down. symbol parameter max. unit v dd/ v ddq supply voltage to ground -0.5 to +4.6 v v i input voltage -0.5 to +4.6 v i o output current 50 ma t stg storage temperature -65 to +150 c t j junction temperature 150 c absolute maximum ratings (1) divide selection table (1) s1 s0 divide-by-n value mode ll2pll lm3pll lh4pll m l 4.25 pll mm5pll mh6pll h l 6.25 pll hm8pll h h test test (2) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. pin description pin name type description s[1:0] i three level divider/mode select pins. float to mid. oe i output enable bar. outputs qout and qref are in a high-impedance state when high. set oe low for normal operation (has internal pull-down). refe i qref enable input. qref stopped low when high. when set refe low, the qref is enabled (has internal pull-down). x1/ref i crystal oscillator input or clock input. x2 i crystal oscillator output. leave unconnected for clock input. qout o output at n*ref frequency. qref o output at ref frequency. vddq pwr power supply for the device outputs. connect to vdd on pcb. vdd pwr power supply for the device core and inputs. connect to vdd on pcb. gnd pwr ground supply.
dt5v926a revision a june 11, 2009 3 ? 2009 integrated device technology, inc. idt5v926a data sheet single output clock generator common output frequency examples (mhz) dc electrical characteristics over operating range following conditions apply unless otherwise specified: industrial: t a = ?40c to +85c, v dd /v ddq = 3.3v 0.3v symbol parameter test conditions min. typ. max unit v il input low voltage ? ? 0.8 v v ih input high voltage 2 ? ? v v ihh input high voltage 3-level input only v dd - 0.6 ? ? v v imm input mid voltage 3-level input only v dd /2 - 0.3 ? v dd /2 + 0.3 v v ill input low voltage 3-level input only ? ? 0.6 v v in = v dd high level ? ? +200 i 3 3-level input dc current, s [1:0] v in = v dd /2 mid level - 50 ? +50 a v in = gnd low level - 200 ? ? i ih input high current v in = v dd oe , refe ? ? 100 a v in = v dd , s [1:0] = hh x 1 /ref ? 2 4 ma v ol output low voltage i ol = 12ma ? ? 0.4 v v oh output high voltage i oh = -12ma 2.4 ? ? v output 48 60 64 72 75 80 90 100 input 2410161225101520 fb divide selection s[1:0] ll mh lh mh lm hm mh mm output 106.25 106.25 120 125 125 125 150 155.52 input 17 25 15 20 25 62.5 25 19.44 fb divide selection s[1:0] hl ml hm hl mm ll mh hm symbol parameter min. typ. max. unit v dd /v ddq power supply voltage 3 3.3 3.6 v t a operating temperature - 40 25 +85 c c in input capacitance, oe, f = 1mhz, v in = 0v, t a = 25c ? 5 pf operating conditions
dt5v926a revision a june 11, 2009 4 ? 2009 integrated device technology, inc. idt5v926a data sheet single output clock generator power supply characteristics symbol parameter test conditions (1) min. typ. max unit i dd_pd power down current v dd = max. ? ? 500 a s [1:0] = hh oe = l ; x 1 /ref = l all outputs unloaded i dd supply current per input v dd = max., v in = 3v ? ? 30 a i dd dynamic supply current v dd = 3.6v ? ? 50 ma s [1:0] = ll oe = l f out = 160mhz all outputs unloaded ac electrical characteristics over operating range symbol parameter t est conditions min. typ. max. unit t r, t f rise time, fall time 0.8v to 2v q out 0.7 1.5 ns q ref 0.7 2.0 d t output/duty cycle v t = v ddq /2 q out < 125mhz 45 55 % q out > 125mhz 44 56 q ref 40 60 f out = 106.25mhz 100 t j cycle - cycle jitter f out = 125mhz 90 ps f out = 155.52mhz 125 f out output frequency 48 160 mhz note: 1. for conditions shown as min. or max., use the appropriate values specified under dc electrical characteristics. symbol description (1) min. max. unit t r, t f maximum input rise and fall time, 0.8v to 2v (2) ? 10 ns/v t pwc input clock pulse, high or low (2) 2?ns d h input duty cycle (2) 10 90 % f osc xtal oscillator frequency 10 40 mhz f in input frequency (2) 48/n 160/n mhz notes: 1. where pulse width implied by d h is less than the t pwc limit, t pwc limit applies. 2. when using a clock input. input timing requirements
dt5v926a revision a june 11, 2009 5 ? 2009 integrated device technology, inc. idt5v926a data sheet single output clock generator p arameter m easurement i nformation c ycle - to -c ycle j itter 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx lvcmos gnd 1.65v0.15v -1.65v0.15v v dd , v ddq o utput r ise /f all t ime o utput d uty c ycle /p ulse w idth /p eriod t period t pw t period odc = v dd 2 x 100% t pw qref, qout ? ? ? ? t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles qout 0.8v 2v 2v 0.8v t r t f qref, qout
idt5v926a single output clock generator preliminary innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt for tech support netcom@idt.com +480-763-2056 corporate headquarters integrated device t echnology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other br ands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ordering information idt xxxx x package thin shrink small outline package tssop - green pg pgg device type 5v926a single output clock generator x process -40c to +85c (industrial) i
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