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rev. 1.0 7/04 copyright ? 2004 by silicon laboratories aero i + aero i + a ero ? i + t ransceiver for gsm and gprs w ireless c ommunications features ? single 8 x 8 mm package ? cmos process technology ? integrated gsm/gprs transceiver including: z low-if receiver z universal baseband interface z offset-pll transmitter z dual rf synthesizer z digitally-controlled crystal oscillator (dcxo) ? integrated vcos, frequency synthesizers, and tuning inductors ? quad-band support: z gsm 850 class 4, small ms z e-gsm 900 class 4, small ms z dcs 1800 class 1 z pcs 1900 class 1 ? gprs class 12 compliant ? 3-wire serial interface ? 2.7 v to 3.0 v operation applications ? multi-band gsm/gprs di gital cellular handsets ? multi-band gsm/gprs wireless data modems description the aero i + transceiver is a complete rf front end for multi-band gsm and gprs wireless communications. the transmit section interfaces between the baseband processor and the power amplifier. the receive section interfaces between the rf band-select saw filters and the baseband processor. all sensitive components, such as rf/if vcos, loop filters, and tuning inductors, are completely integrated into a single compact package. the aero i + includes a digitally-controlled crystal oscillator (dcxo) function and comp letely integrates the reference oscillator and varactor. functional block diagram adc adc pga pga lna lna lna rf pll gsm dcs pcs gsm dcs pcs 0 / 90 antenna switch i det baseband xafc pga pga channel filter 100 khz si4206 if pll pa xout dcxo i q analog interface pin assignments (top view) SI4206-BM (pin description, see page 35) 1 2 3 22 23 24 25 26 27 28 bqp bqn xout bip rfipn rfidp gnd rfipp rfidn rfigp rfign 15 16 17 18 19 20 21 8 9 10 11 12 13 14 4 5 6 7 xtal1 xafc xdrven xtalen sdi sdo xtal2 sen sclk diag2 diag1 rfod rfog pdn xen bin v dd gnd gnd gnd gnd 32 31 30 29 ordering information: see page 36. patents pending
aero i + 2 rev. 1.0
aero i + rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.1. receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2. transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.3. frequency synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4. dcxo overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4.5. serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4.6. xout buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6. pin descriptions: SI4206-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8. package outline: si 4206-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
aero i + 4 rev. 1.0 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient temperature t a ?20 25 85 c dc supply voltage v dd 2.7 2.85 3.0 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at 2.85 v and an operating temperature of 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit dc supply voltage v dd ?0.5 to 3.3 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v dd + 0.3) v operating temperature t op ?40 to 95 c storage temperature t stg ?55 to 150 c rf input level 4 10 dbm notes: 1. permanent device damage may occur if the above absolu te maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. the si4206 device is a high-performance rf integrated circuit with an esd rating of < 2 kv. handling and assembly of this device should only be done at esd-protected workstations. 3. for signals sclk, sdi, sen , pdn , xin, xen, xtalen, and xdrven. 4. at saw filter output for all bands.
table 3. dc characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit supply current 1 i rx receive mode ? 83 115 ma i tx transmit mode ? 85 109 ma i xtal13 pdn = 0, xen = 1, f xtal = 13 mhz ? 4.0 6.0 ma i xtal26 pdn = 0, xen = 1, f xtal = 26 mhz ? 5.0 7.0 ma i pdn pdn = 0, xen = 0, xbuf = 0, xpd1 = 1 ? 5 80 a high level input voltage 2 v ih 0.7 v dd ? ? v low level input voltage 2 v il ? ? 0.3 v dd v high level input current 2 i ih v ih = v dd = 3.0 v ?10 ? 10 a low level input current 2 i il v il = 0 v, v dd = 3.0 v ?10 ? 10 a high level output voltage 3 v oh i oh = ?500 a v dd ?0.4 ? ? v low level output voltage 3 v ol i ol = 500 a ? ? 0.4 v high level output voltage 4 v oh i oh = ?10 ma v dd ?0.4 ? ? v low level output voltage 4 v ol i ol = 10 ma ? ? 0.4 v notes: 1. measured with load on xout pin of 10 pf and f xtal = 13 mhz. limits with xen = 1 guaranteed by characterization. measured with xen, xdrven, and xtalen tied together and controlled simultaneously. 2. for pins sclk, sdi, sen , xen, pdn , xdrven, and xtalen. 3. for pins sdo, xout. 4. for pins diag1, diag2. aero i + rev. 1.0 5
table 4. ac characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk cycle time t clk figures 1, 3 35 ? ? ns sclk rise time t r figures 1, 3 ? ? 50 ns sclk fall time t f figures 1, 3 ? ? 50 ns sclk high time t hi figures 1, 3 10 ? ? ns sclk low time t lo figures 1, 3 10 ? ? ns pdn rise time t pr figure 2 ? ? 10 ns pdn fall time t pf figure 2 ? ? 10 ns sdi setup time to sclk t su figure 3 15 ? ? ns sdi hold time from sclk t hold figure 3 10 ? ? ns sen to sclk delay time t en1 figure 3 10 ? ? ns sclk to sen delay time t en2 figures 3, 4 12 ? ? ns sen to sclk delay time t en3 figures 3, 4 12 ? ? ns sen pulse width t w figures 3, 4 10 ? ? ns sclk to sdo time t ca figure 4 ? ? 27 ns digital input pin capacitance * ? ? 5 pf *note: for pins sclk, sdi, sen , xen, pdn , xdrven, and xtalen. sclk 80% 20% 50% t r t f t lo t clk t hi aero i + 6 rev. 1.0 figure 1. sclk timing diagram pdn 80% 20% t pr t pf figure 2. pdn timing diagram
t en1 80% 50% 20% 80% 50% 20% 80% 50% 20% d17 d16 a0 t r t w t en2 t f t lo t hi t clk t hold t su sdi sclk sen t en3 aero i + rev. 1.0 7 figure 3. serial interface write timing diagram 80% 50% 20% 80% 50% 20% 80% 50% 20% a0 80% 50% 20% sdi sclk sen sdo od17 od0 od16 t ca t en2 t en3 t w figure 4. serial interface read timing diagram
aero i + 8 rev. 1.0 table 5. receiver characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit gsm input frequency 1 f in gsm 850 band 869 ? 894 mhz e-gsm 900 band 925 ? 960 mhz dcs or pcs input frequency 1 dcs 1800 band 1805 ? 1880 mhz pcs 1900 band 1930 ? 1990 mhz noise figure at 25 c 2,3 nf 25 gsm 850 band ? 2.9 3.8 db e-gsm 900 band ? 3.0 3.9 db dcs 1800 band ? 3.3 4.1 db pcs 1900 band ? 3.7 4.5 db noise figure at 75 c 2,3 nf 75 gsm 850 band ? 3.6 4.5 db e-gsm 900 band ? 3.7 4.6 db dcs 1800 band ? 4.2 5.0 db pcs 1900 band ? 4.9 5.7 db noise figure at 85 c 2,3 nf 85 gsm 850 band ? 3.7 4.6 db e-gsm 900 band ? 3.8 4.7 db dcs 1800 band ? 4.6 5.4 db pcs 1900 band ? 5.2 6.0 db 3 mhz input desensitization 2,3,4 des 3 gsm input ?25 ?21 ? dbm dcs/pcs inputs ?28 ?25 ? dbm 20 mhz input desensitization 2,3,4 des 20 gsm input ?20 ?16 ? dbm dcs/pcs inputs ?19 ?15 ? dbm input ip2 2 ip2 |f 1,2 ? f 0 | t 6 mhz, |f 2 ? f 1 | 100 khz 29 40 ? dbm input ip3 2 ip3 |f 2 ? f 1 | t 800 khz, f 0 = 2f 1 ? f 2 ?18 ?12 ? dbm image rejection 2,4 ir gsm input 28 35 ? db dcs/pcs inputs 28 40 ? db 1 db input compression 2,5 cp max gsm input ?28 ?23 ? dbm dcs/pcs inputs ?27 ?22 ? dbm 1 db input compression 2,6 cp min gsm input ?23 ?18 ? dbm dcs/pcs inputs ?23 ?18 ? dbm minimum voltage gain 2,6,7 g min gsm input 3.0 8.5 12.5 db dcs/pcs inputs 10.0 15.5 19.5 db maximum voltage gain 2,7 g max gsm input 100 104 109 db dcs/pcs inputs 96 102 107 db lna voltage gain 3,8 g lna gsm input ? 17 ? db dcs/pcs inputs ? 15 ? db lna gain control range ' g lna gsm input 13 17 21 db dcs/pcs inputs 4 8 12 db
aero i + rev. 1.0 9 analog pga control range ? g apga 13 16 19 db analog pga step size 3.2 4.0 4.8 db digital pga control range ? g dpga ? 63 ? db digital pga step size ? 1 ? db maximum differentia l output voltage 9 dacfs[1:0] = 00 0.7 1.0 1.3 v ppd dacfs[1:0] = 01 1.5 2.0 2.5 v ppd dacfs[1:0] = 10 2.6 3.5 4.4 v ppd output common mode voltage 9 daccm[1:0] = 00 0.8 1.0 1.2 v daccm[1:0] = 01 1.05 1.25 1.45 v daccm[1:0] = 10 1.15 1.35 1.55 v differential output offset voltage 9,10,11 ? ? 16 mv differential output offset voltage drift 9,10,11 ? ? 5 mv baseband gain error 9,11 ? ? 1 % baseband phase error 9,11 ? ? 1 deg output load resistance 9 r l single-ended 10 ? ? k ? output load capacitance 9 c l single-ended ? ? 10 pf group delay 12 csel = 0 ? ? 22 s csel = 1 ? ? 16 s differential group delay 12 csel = 0 ? ? 1.5 s csel = 1 ? ? 1 s powerup settling time 3,13 from powerdown ? 200 220 s notes: 1. gsm input pins rfigp and rfign. dcs input pins rf idp and rfidn. pcs input pins rfipp and rfipn. 2. measurement is performed with a 2:1 balun (50 ? input, 200 ? balanced output) and includes matching network and pcb losses. measured at max gain (again[2:0] =100 b , lnag[1:0] = 01 b , lnac[1:0] = 01 b ) unless otherwise noted. noise figure measurements are referred to 290 k. insertion loss of the balun is removed. 3. specifications guaranteed by characterization using lqw15an series matching inductors. 4. input signal at balun is ?102 dbm. snr at baseband output is 9 db. 5. again[2:0]=min=000 b , lnag[1:0] = max=01 b , lnac[1:0] =max= 01 b . 6. again[2:0]=min=000 b , lnag[1:0] = min=00 b , lnac[1:0] = min=00 b . 7. voltage gain is defined as the differential rms voltage at th e bip/bin pins or bqp/bqn pins divided by the rms voltage at the balun input with dacfs[1:0] = 01 and csel = 1. gain is 1.5 db higher with csel = 0. minimum and maximum values do not include the variation in the dac full scal e voltage (also see maximum differential output voltage specification). 8. voltage gain is defined as the differential rms voltage at the lna output divided by the rms voltage at the balun output. 9. output pins bip, bin, bqp, bqn. 10. specified as root sum square: rxip rxin ? () 2 rxqp rxqn ? () 2 + . drift specification applies to dc offset calibration and is guaranteed by characterization. see zerodel[2:0] in the register description. 11. the baseband signal path is entirely digital. gain, phase, and offset errors at the baseband outputs are because of the d/a converters. offsets can be measur ed and calibrated out. see zerodel[2: 0] in the register description. 12. group delay is measured from antenna input to baseba nd outputs. differential group delay is measured in-band. 13. includes settling time of the frequency synthesizer. settling to 5 degrees phase error measur ed at bip, bin, bqp, and bqn pins. table 5. receiver characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
0 50 100 150 200 250 300 350 400 ?120 ?100 ?80 ?60 ?40 ?20 0 receive path magnitude response (csel = 0) magnitude (db) frequency (khz) aero i + 10 rev. 1.0 figure 5. receive path magnitude response (csel = 0) 0 10 20 30 40 50 60 70 80 90 10 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 receive path passband magnitude response (csel = 0) magnitude (db) frequency (khz) figure 6. receive path passband magnitude response (csel = 0) 0 10 20 30 40 50 60 70 80 90 10 0 15 16 17 18 19 20 21 22 23 24 25 receive path passband group delay (csel = 0) group delay (usec) frequency (khz) figure 7. receive path passband group delay (csel = 0) 0 50 100 150 200 250 300 350 400 ?80 ?60 ?40 ?20 0 receive path magnitude response (csel = 1) magnitude (db) frequency (khz) figure 8. receive path magnitude response (csel = 1) 0 10 20 30 40 50 60 70 80 90 10 0 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 receive path passband magnitude response (csel = 1) magnitude (db) frequency (khz) figure 9. receive path passband magnitude response (csel = 1) 0 10 20 30 40 50 60 70 80 90 10 0 10 11 12 13 14 15 16 17 18 19 20 receive path passband group delay (csel = 1) group delay (usec) frequency (khz) figure 10. receive path passband group delay (csel = 1)
aero i + rev. 1.0 11 table 6. transmitter characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit rfog output frequency 1 gsm 850 band 824 ? 849 mhz e-gsm 900 band 880 ? 915 mhz rfod output frequency 2 dcs 1800 band 1710 ? 1785 mhz pcs 1900 band 1850 ? 1910 mhz i/q differential input swing 3,4 0.88 ? 2.2 v ppd i/q input common mode 3 1.1 ? 1.4 v i/q differential input resistance 3,4 bbg[1:0] = 11 b 16 19 22 k : bbg[1:0] = 00 b 14 17 20 k : bbg[1:0] = 01 b 12 15 18 k : powered down ? hi-z ? k : i/q input capacitance 3,5 ? ? 5 pf i/q input bias current 3 13 16 19 p a sideband suppression 67.7 khz sinusoid ? ?46 ?34 dbc carrier suppression 67.7 khz sinusoid ? ?48 ?33 dbc im3 suppression 67.7 khz sinusoid ? ?57 ?50 dbc phase error 5 ? 1.9 3.0 o rms ? 5 10 o peak txvco pushing 1,2 open loop ? 100 ? khz/v txvco pulling 1,2 vswr 2:1, all phases, open loop ? 200 ? khz pp rfog output modulation spectrum 1,6 400 khz offset ? ?65 ?63 dbc 1.8 mhz offset ? ?70 ?68 dbc rfod output modulation spectrum 2,6 400 khz offset ? ?65 ?63 dbc 1.8 mhz offset ? ?70 ?65 dbc rfog output phase noise 1,5,7 10 mhz offset ? ?160 ?155 dbc/hz 20 mhz offset ? ?166 ?164 dbc/hz rfod output phase noise 2,5,7 20 mhz offset ? ?163 ?157 dbc/hz rfog output power level 1 z l = 50 : 7 9 11 dbm rfod output power level 2 z l = 50 : 6 8 10 dbm
aero i + 12 rev. 1.0 rf output harmonic suppression 1,2 2nd harmonic ? ? ?20 dbc 3rd harmonic ? ? ?10 dbc powerup settling time 5,8 from powerdown ? ? 150 p s notes: 1. measured at rfog pin. 2. measured at rfod pin. 3. input pins bip, bi n, bqp, and bqn. 4. differential input swing is programmable with the bbg[1:0] bi ts in register 04h. program these bits to the closest appropriate value. the i/q input resistance scales inversely with the bbg[1:0] setting. 5. specifications guaranteed by characterization. 6. measured with pseudo-random pattern. carrier power and noise power < 1.8 mhz measured with 30 khz rbw. noise power t 1.8 mhz measured with 100 khz rbw. 7. measured with all 1s pattern. 8. including settling time of the frequency synthesizer. settlin g time measured at the rfod and rfog pins to 0.1 ppm frequency error. table 6. transmitter characteristics (continued) (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit
table 7. frequency synthesizer characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit rf1 vco frequency 1 f rf1 gsm 850 band 1737.8 ? 1787.8 mhz e-gsm 900 band 1849.8 ? 1919.8 mhz dcs 1800 band 1804.9 ? 1879.9 mhz pcs 1900 band 1929.9 ? 1989.9 mhz rf2 vco frequency 1 f rf2 gsm 850 band 1272 ? 1297 mhz e-gsm 900 1279 ? 1314 mhz dcs 1800 band 1327 ? 1402 mhz pcs 1900 band 1423 ? 1483 mhz if vco frequency 1 f if gsm 850 band ? 896 ? mhz e-gsm 900 band 880?895 mhz 900?915 mhz ? 798 ? mhz e-gsm 900 band 895?900 mhz ? 790 ? mhz dcs 1800 band ? 766 ? mhz pcs 1900 band ? 854 ? mhz rf1 pll phase detector update frequency f gsm input, rfup = 0 ? 200 ? khz dcs/pcs inputs, rfup = 1 ? 100 ? khz if and rf2 pll phase detector update frequency f ? 200 ? khz rf1 vco pushing 2 open loop ? 500 ? khz/v rf2 vco pushing 2 ? 400 ? khz/v if vco pushing 2 ? 300 ? khz/v rf1 vco pulling 2 vswr = 2:1, all phases, open loop ? 400 ? khz pp rf2 vco pulling 2 ? 100 ? khz pp if vco pulling 2 ? 100 ? khz pp rf1 pll phase noise 2 3 mhz offset ? ?144 ?138 dbc/hz rf2 pll phase noise 2 400 khz offset ? ?126 ?121 dbc/hz if pll phase noise 2 400 khz offset ? ?128 ?123 dbc/hz rf1 pll spurious 2 3 mhz offset ? ?95 ?83 dbc rf2 pll spurious 2 400 khz offset ? ?80 ?75 dbc if pll spurious 2 400 khz offset ? ?80 ?70 dbc notes: 1. for the gsm input, the rf1 vco is divided by two. during transmit, the if vco is divided by two. 2. specifications are guaran teed by characterization. aero i + rev. 1.0 13
table 8. reference oscillator characteristics (v dd = 2.7 to 3.0 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit crystal oscillation frequency f xtal xsel = 0, div2 = 0 ? 13 ? mhz xsel = 1, div2 = 1 ? 26 ? mhz afc input voltage v afc 0 ? 2.5 v afc capacitance range * c var f xtal = 13 mhz ? 1.7 ? pf f xtal = 26 mhz ? 1.4 ? pf dac capacitance range * c dac f xtal = 13 mhz ? 3.0 ? pf f xtal = 26 mhz ? 2.9 ? pf fixed capacitance * c fix f xtal = 13 mhz ? 4.4 ? pf f xtal = 26 mhz ? 4.3 ? pf powerup settling time t dcxo v ctl = 0 to 1.25 v ? 1.0 ? ms *note: parameters relate to reference oscillator frequency tuning range depending on the crystal characteristics. see ?an83: selecting a crystal for aero?+/ i + designs? for detailed instru ctions on crystal selection. aero i + 14 rev. 1.0
aero i + rev. 1.0 15 2. typical application schematic vdd gnd gnd vdd diag1 diag2 pdnb xen bqp bqn bip bin xafc xtalen xdrven sdo senb sclk sdi xout rfog rfod pcs 1900 in dcs 1800 in gsm900 in u1 si4206 xtal2 6 bqp 1 bqn 2 xafc 7 bip 3 rfidp 18 rfipp 16 rfipn 17 rfidn 19 rfigp 20 rfign 21 diag1 24 rfog 23 rfod 22 diag2 25 pdnb 26 xen 27 xout 28 bin 4 xtal1 5 xtalen 8 xdrven 9 sdo 10 senb 11 sclk 12 sdi 13 vdd 14 gnd 15 vdd 32 gnd 31 vdd 30 gnd 29 z3 out+ out- in gnd z1 out+ out- in gnd c8 c3 l2 l1 c7 c4 l3 c6 c1 x1 13/26mhz c5 c2 z2 out+ out- in gnd notes: 1. connect pads on bottom of u1 to gnd. 2. see ?an92: aero? i/aero? i+ transceiver pcb layout guidelines? for details on the following: z lna matching network (c1?c6, l1?l3). values should be custom tuned for a specific pcb layout and saw filter to optimize performance. z differential traces between the saw filters (z1?z3) and transceiver (u1) pins 16?21. z detailed saw filter requirements. z crystal connection to u1 pins 5?6. 3. xen, xdrven, and xtalen are recommended to be tied together and controlled simultaneously.
aero i + 16 rev. 1.0 3. bill of materials component value/description supplier(s) c1?c2 1.2 pf, 0.1 pf, c0g (gsm 850 and e-gsm 900) murata grm36c0g series venkel c0402c0g500 series c3?c4 1.2 pf, 0.1 pf, c0g (dcs 1800) murata grm36c0g series venkel c0402c0g500 series c5?c6 1.5 pf, 0.1 pf, c0g (pcs 1900) murata grm36c0g series venkel c0402c0g500 series c7 22 nf, 20%, z5u/x7r c8 10 pf, 5%, c0g l1 24 nh, 2% murata lqg15hn series (0402 size) murata lqw15an series (0402 size) l2 6.8 nh, 0.2 nh murata lqg15hn series (0402 size) murata lqw15an series (0402 size) l3 5.6 nh, 0.2 nh murata lqg15hn series (0402 size) murata lqw15an series (0402 size) u1 gsm/gprs transceiver silicon laboratories si4206 x1 13 or 26 mhz crystal kds 1br13000aa0f kss cx96fffbqaj13 ndk w-168-237 toyocom tn4-25999-r0-2 z1 gsm 850 rx saw filter (150 ? balanced output) epcos b39881-b9001-c710 (5-pin, 1.4 x 2.0 mm) epcos b39881-b9004-e710 (6-pin, 1.6 x 2.0 mm) murata safek881mfl0t00r00 (6-pin, 1.6 x 2.0 mm) e-gsm 900 rx saw filter (150 ? balanced output) epcos b39941-b7820-c710 (5-pin, 1.4 x 2.0 mm) murata safek942mfm0t00r00 (6-pin, 1.6 x 2.0 mm) z2 dcs 1800 rx saw filter (150 ? balanced output) epcos b39182-b7821-c710 (5-pin, 1.4 x 2.0 mm) epcos b39182-b9013-k310 (6-pin, 1.6 x 2.0 mm) murata safek1g84fa0t00r00 (6-pin, 1.6 x 2.0 mm) z3 pcs 1900 rx saw filter (150 ? balanced output) epcos b39202-b7825-c710 (5-pin, 1.4 x 2.0 mm) murata safek1g96fa0t00r00 (6-pin, 1.6 x 2.0 mm)
aero i + rev. 1.0 17 4. functional description adc adc pga pga lna lna lna rf pll gsm dcs pcs gsm dcs pcs 0 / 90 antenna switch i det baseband xafc pga pga channel filter 100 khz si4206 if pll pa xout dcxo i q analog interface figure 11. aero i + transceiver block diagram the aero i + transceiver is the industry?s most integrated rf front end for multi-band gsm/gprs digital cellular handsets and wireless data modems. the highly integrated solution eliminates the if saw filter, external low noise amplifiers (lnas) for three bands, transmit and rf voltage-controlled oscillator (vco) modules, and more than 70 other discrete components found in conventional designs. the high level of integration obtained through high- performance packaging and fine line cmos process technology results in a solution with 50% less area and 80% fewer components than competing solutions. a triple-band gsm transceiver using the aero i + transceiver can be implemented with 15 components in less than 1.2 cm 2 of board area. this level of integration is an enabling force in lowering the cost, simplifying the design and manufacturing, and shrinking the form factor in next-generation gsm/gprs voice and data terminals. the receive section uses a digital low-if architecture that avoids the difficulti es associated with direct conversion while deliveri ng lower solution cost and reduced complexity. the baseband interface is compatible with any supplier?s baseband subsystem. the transmit section is a complete up-conversion path from the baseband subsystem to the power amplifier, and uses an offset phase-locked loop (pll) with a fully integrated transmit vco. the frequency synthesizer uses silicon laboratories? proven technology that includes integrated rf and if vcos, varactors, and loop filters. the unique integer-n pll architecture produces a transient response superior in speed to fractional-n architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. this fast transient response makes the aero i + transceiver well suited to gprs multi-slot applications where channel switching and settling times are critical. while conventional solutions use bicmos or other bipolar process technologies, the aero i + transceiver employs 100% cmos process. this brings the dramatic cost savings and extensive manufacturing capacity of cmos to the gsm market.
aero i + 18 rev. 1.0 4.1. receiver baseband dac dac pga pga channel filter 100 khz adc adc pga pga lna lna lna si4206 0/90 i q n rf1 [15:0] rfup rxband[1:0] lnac[1:0] lnag[1:0] again[2:0] csel dgain[5:0] daccm[1:0] dacfs[1:0] zerodel[2:0] rf pll gsm dcs pcs dcxo cdac[5:0] xout figure 12. receiver block diagram the aero i + transceiver uses a low-if receiver architecture that allows fo r on-chip integration of the channel selection filters, e liminating the external rf image reject filters and the if saw filter required in conventional superheterodyne architectures. compared to a direct-conversion architecture, the low-if architecture has a much greater degree of immunity to dc offsets that can arise from rf local oscillator (rflo) self-mixing, 2nd-order distortion of blockers, and device 1/f noise. this relaxes the common mode balance requirements on the input saw filters and simplifies pc board design and manufacturing. three differential-input lnas are integrated. the gsm input supports the gsm 850 (869?894 mhz) or e- gsm 900 (925?960 mhz) bands. the dcs input supports the dcs 1800 (1805?1880 mhz) band. the pcs input supports the pcs 1900 (1930?1990 mhz) band. the lna inputs are matched to the 200 ? balanced- output saw filters throug h external lc matching networks. the lna gain is controlled with the lnag[1:0] and lnac[1:0] bits in register 05h. a quadrature image-reject mixer downconverts the rf signal to a 100 khz intermediate frequency (if) with the rflo from the frequency synthesizer. the rflo frequency is between 1737.8 and 1989.9 mhz, and is divided by two for gsm 850 and e-gsm 900 modes. the mixer output is amplified with an analog programmable gain amplifier (pga), which is controlled with the again[2:0] bits in register 05h. the quadrature if signal is digitized with high resolution a/d converters (adcs). the adc output is downconverted to baseband with a digital 100 khz quadrature lo signal. digital decimation and iir filters perform channel selection to remove blocking and reference interference signals. the response of the iir filter is programmable to a high selectivity setting (csel = 0) or a low selectivity setting (csel = 1). the low selectivity f ilter has a flatter group delay response that may be desirable where the final channelization filter is in the baseband chip. after channel selection, the digital output is scaled with a digital pga, which is controlle d with the dgain[5:0] bits in register 05h. the lnag[1:0], lnac[1:0], ag ain[2:0] and dgain[5:0] bits must be set to provide a constant amplitude signal to the baseband receive inputs. see ?an51: aero transceiver agc strategy? for more details. dacs drive a differential an alog signal onto the bip, bin, bqp, and bqn pins to interface to standard analog-input baseband ics. no special processing is required in the baseband for offset compensation or extended dynamic range. the receive and transmit baseband i/q pins are multiplexed together through the bip, bin, bqp, and bqn pins. the common mode output level is programmabl e with the daccm[1:0] bits, and the full scale level is programmable with the dacfs[1:0] bits in register 12h.
aero i + rev. 1.0 19 4.2. transmitter i det pa pa i q gsm dcs/pcs if pll rf pll y 2 fif[3:0] n rf2 [15:0] pdrb n if [15:0] pdib y 1, 2 txband[1:0] si4206 reg reg bbg[1:0] swap rfog rfod baseband figure 13. transmitter block diagram the transmit (tx) section consists of an i/q baseband upconverter, an offset phase-locked loop (opll), and two 50 ? output buffers that can drive external power amplifiers (pa), one for the gsm 850 (824?849 mhz) and e-gsm 900 (880?915 mhz) bands and one for the dcs 1800 (1710?1785 mhz) and pcs 1900 (1850? 1910 mhz) bands. the opll requires no external duplexer to attenuate tran smitter noise and spurious signals in the receive band, saving both cost and power. additionally, the output of the transmit vco (txvco) is a constant-envelope signal that reduces the problem of spectral spreading caused by non-linearity in the pa. a quadrature mixer upconverts the differential in-phase (bip, bin) and quadrature (bqp, bqn) signals with the iflo to generate a ssb if signal that is filtered and used as the reference input to the opll. the iflo frequency is generated between 766 and 896 mhz. the iflo is divided by two to generate the quadrature lo signals for the quadrature modulator, resulting in an if between 383 and 448 mhz. for the e-gsm 900 band, two different iflo frequencies are required for spur management. therefore, the if pll must be programmed per channel in the e-gsm 900 band. the iflo frequencies are defined in ta b l e 6 on page 11 . the opll consists of a feedback mixer, a phase detector, a loop filter, and a fully integrated txvco. the txvco is centered between the dcs 1800 and pcs 1900 bands, and its output is divided by two for the gsm 850 and e-gsm 900 bands. the si4133t generates the rflo frequency between 1272 and 1483 mhz. to allow a single vco to be used for the rflo, high-side injection is used for the gsm 850 and e-gsm 900 bands, and low-side injection is used for the dcs 1800 and pcs 1900 bands. the i and q signals are automatically swapped when switching bands. therefore, there is no need for the customer to externally swap the i and o signals. however, for additional layout flexibility, the swap bit in register 03h can be used to manually exchange the i and q signals. low-pass filters before the opll phase detector reduce the harmonic content of the quadrature modulator and feedback mixer outputs. the cutoff frequency of the filters is programmable with the fif[3:0] bits in register 04h and should be set to the recommended settings detailed in the register description.
aero i + 20 rev. 1.0 4.3. frequency synthesizer self tune i det rf1 rf2 y n [15:0] [15:0] y 65, y 130 y 1, 2 power control serial i/o y n i det n if [15:0] rfpwr[1:0] rfup div2 pdib pdrb sdosel[3:0] if pll rf pll self tune sen sclk sdo sdi pdn xtal1 to rx/tx dcxo xtal2 xout xen cdac[5:0] xafc xtalen si4206 to tx n rf1 n rf2 figure 14. frequency synthesizer block diagram the aero i + transceiver integrates two complete plls including vcos, varactors, resonators, loop filters, reference and vco dividers, and phase detectors. the rf pll uses two multiplexed vcos. the rf1 vco is used for receive mode, and the rf2 vco is used for transmit mode. the if pll is used only during transmit mode. all vco tuning inductors are also integrated. the if and rf output frequencies are set by programming the n-divider registers, n rf1 , n rf2 , and n if . programming the n-divider register for either rf1 or rf2 automatically selects the proper vco. the output frequency of each pll is as follows: f out nf = a programmable divider in the input stage allows either a 13 or 26 mhz reference frequency depending on the choice of crystal. a 26 mhz reference clock can be divided by 2 using the div2 bi t in register 31h. the rf pll phase detector update rate (f ) can be programmed with the rfup bit in register 31h to either f = 100 khz or f = 200 khz. the if pll always uses f = 200 khz. receive mode should use f = 100 khz in dcs 1800 and pcs 1900 bands, and f = 200 khz in the gsm 850 and e-gsm 900 bands. transmit modes should always use f = 200 khz.
aero i + rev. 1.0 21 4.4. dcxo overview the aero i + transceiver integrates the dcxo circuitry required to generate a precise system reference clock using only an external crystal resonator. (see figure 15 .) an internal digitally programmable capacitor array (cdac) provides a coarse method of adjusting the reference frequency in discrete steps. an integrated analog varactor (cvar) allows for a fine and continuous adjustment of the reference frequency by an external control voltage (xafc). this control voltage is supplied by the afc dac on the baseband ic. the complete dcxo solution effectively replaces tcvcxo modules typically required to provide a 13 or 26 mhz reference clock for the system. 4.4.1. dcxo tuning the dcxo uses the cdac and the cvar to correct for both static and dynamic frequency errors, respectively. to compensate for crystal offset error, the cdac ensures a minimum of 10 ppm frequency adjustment capability. the cdac is programmed using register 28h. the cdac register (register 28) may be programmed during powerup or after an initial calibration. periodic adjustments to compensate for aging may also be performed over time to ensure accuracy. the baseband determines the appropriate frequency adjustment based on the receipt of the fcch burst. the baseband then adjusts the xafc voltage using the baseband afc dac (12 or 13-bit). the baseband afc dac can ad just cvar to correct for frequency variations caused by temperature drift. the step size per bit depends on the resolution of the afc dac and its output voltage range. 4.4.2. dcxo crystal selection the tuning range specifications listed in table 8 on page 14 for cdac and cvar assume that aero i + is used with a crystal that conforms to the crystal parameters listed in the same table. other crystals may be used with aero i + for cost and/or performance reasons. for example, using a higher sensitivity crystal extends the cvar and the cdac frequency compensation range. however, care must be taken when using a more sensitive crystal because other system parameters are affected. contact silicon laboratories? application support for assistance in selecting other crystals. < ;7$/ ;7$/ 6l ;287 %$6(%$1' ;$)& $)& '$& 72 3//v &'$&>@ &9$5 ;(1 figure 15. dcxo system signal routing diagram
aero i + 22 rev. 1.0 4.5. serial interface a three-wire serial interfac e is provided to allow an external system controller to write the control registers for dividers, receive path gain, power down settings, and other controls. the serial control word is 24 bits in length, comprised of an 18-b it data field and a 6-bit address field as shown in figure 16 . d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 5 a 4 a 3 a 2 a 1 a 0 data field address field last bit clocked in d 16 d 17 figure 16. serial interface format all registers must be written when the pdn pin is asserted (low), except for register 22h. all serial interface pins should be held at a constant level during receive and transmit bursts to minimize spurious emissions. this includes stopping the sclk clock. a timing diagram for the serial interface is shown in figure 3 on page 7 . when the serial interface is enabled (i.e., when sen is low), data and address bits on the sdi pin are clocked into an internal shift register on the rising edge of sclk. data in the shift register is then transferred on the rising edge of sen into the internal data register addressed in the address field. the internal shift register ignores any leading bits before the 24 required bits. the serial interface is disabled when sen is high. optionally, registers can be read as illustrated in figure 4 on page 7 . the serial output data appears on the sdo pin after writing the revision register with the address to be read. writing to any of the registers causes the function of sdo to revert to its previously programmed function. 4.6. xout buffer the aero i + transceiver contains a reference clock buffer to drive the baseba nd input. the xsel control has no effect on the buffered clock signal. the xout buffer is a cmos driver stage with approximately 250 ? of series resistance. this buffer is enabled when the xen pin is set high, independent of the pdn pin. the xtalen signal controls the powerup state of the dcxo and must be enabled (xtalen = 1) before the xout signal can be source d. to achieve complete powerdown during sleep, the xen pin must be set low, the xbuf bit in register 12 must be set to zero, and the xpd1 bit in register 11 must be set to one. during normal operation, these bits should be set to their default values.
aero i + rev. 1.0 23 5. control registers table 9. register summary reg name bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 01h reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 02h mode 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 auto mode[1:0] 03h config 0 0 0 0 diag[1:0] swap 0 0 0 txband[1:0] rxband[1:0] 0 0 1 0 04h transmit 0 0 0 0 0 0 0 1 bbg[1:0] fif[3:0] 0 0 0 0 05h receive 0 0 0 0 dgain[5:0] 0 again[2:0] lnac[1:0] lnag[1:0] 11h config 0 0 0 0 dpds[2:0] xpd1 1 xsel 0 1 0 1 0 0 0 csel 12h dac config 0 0 0 0 0 0 0 1 xbuf 0 zdbs zerodel[2:0] daccm[1:0] dacfs[1:0] 19h reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 master registers 20h rx master #1 rxband[1:0] n rf1 [15:0] 21h rx master #2 0 dpds[2:0] lnac[1:0] lnag[1:0] again[2:0] 0 dgain[5:0] 22h rx master #3 0 0 0 0 0 0 0 0 0 0 0 0 dgain[5:0] 23h tx master #1 txband[1:0] n rf2 [15:0] 24h tx master #2 fif[3:0] n if [13:0] 28h cdac 0 0 0 0 0 0 0 0 0 0 0 0 cdac[5:0] 31h config 0 0 0 sdosel[3:0] 0 0 0 0 0 0 rfup div2 0 0 0 32h powerdown 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pdib pdrb 33h rf1 n divider 0 0 n rf1 [15:0] 34h rf2 n divider 0 0 n rf2 [15:0] 35h if n divider 0 0 n if [15:0] notes: 1. any register not listed here is reserved and should not be written. writing to reserved register s may result in unpredictable behavior. 2. master registers 20h to 24h simplify programming the aero i + to support initiation of receive (rx) and transmit (tx) operations with only two register writes. 3. see ?an50: aero transceiver programming guide? for detailed instructions on register programming.
register 01h. reset bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset bit name function 17:1 reserved program to zero. 0 reset chip reset. 0 = normal operation (default). 1 = reset all registers to default values. note: this register must be written to 0 t wice after a reset operation. this bit does not reset registers 31h to 35h. register 02h. mode control bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 auto mode[1:0] bit name function 17:3 reserved program to zero. 2 auto automatic mode select. 0 = manual. mode is controlled by mode[1:0] bits (default). 1 = automatic. last register write to n rf1 implies rx mode; last register write to n rf2 implies tx mode. mode[1:0] bits are ignored. 1:0 mode[1:0] transmit/receive/cal mode select. 00 = receive mode (default). 01 = transmit mode. 10 = calibration mode. 11 = reserved. note: these bits are valid only when auto = 0. aero i + 24 rev. 1.0 note: calibration must be performed each time the power suppl y is applied. to initiate the calibration mode, set mode[1:0] = 10 and pulse the pdn pin high for at least 150 s.
register 03h. configuration bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 diag[1:0] swap 0 0 0 txband[1:0] rxband[1:0] 0 0 1 0 bit name function 17:14 reserved program to zero. 13:12 diag[1:0] diag1/diag2 ou tput select. diag1 diag2 00 = low low (default) 01 = low high 10 = high low 11 = high high note: these pins can be used to control antenna switch functions. these bits must be programmed with the pdn pin is zero. the diag1/diag2 pins will be held at the desired value regardless of the state of the pdn pin. 11 swap transmit i/q swap. 0 = normal (default). 1 = swap i and q for txip, txin, txqp, and txqn pins. 10:8 reserved program to zero. 7:6 txband[1:0] transmit band select. 00 = gsm 850 or e-gsm 900 (default). 01 = dcs 1800. 10 = pcs 1900. 11 = reserved. 5:4 rxband[1:0] receive band select. 00 = gsm input (default). 01 = dcs input. 10 = pcs input. 11 = reserved. 3:2 reserved program to zero. 1 reserved program to one. 0 reserved program to zero. aero i + rev. 1.0 25
register 04h. transmit control bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 1 bbg[1:0] fif[3:0] 0 0 0 0 bit name function 17:11 reserved program to zero. 10 reserved program to one. 9:8 bbg[1:0] tx baseband input full scale differential input voltage. 10 = reserved. 11 = 2.0 v ppd 00 = 1.6 v ppd (default). 01 = 1.2 v ppd note: refer to ta b l e 6 on page 11 for minimum and maximum values. set this register to the nearest value. 7:4 fif[3:0] tx if filter cutoff frequency. 0111 = use for gsm 850, e-gsm 900 and pcs 1900 bands. 0110 = use for dcs 1800 band. note: use the recommended setting for each band. other settings reserved. 3:0 reserved program to zero. aero i + 26 rev. 1.0
register 05h. receive gain bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 dgain[5:0] 0 again[2:0] lnac[1:0] lnag[1:0] bit name function 17:14 reserved program to zero. 13:8 dgain[5:0] digital pga gain control. 00h = 0 db (default). 01h = 1 db. ... 3fh = 63 db. note: see ?an51: aero transceiver agc strategy? for details on setting the gain registers. 7 reserved program to zero. 6:4 again[2:0] analog pga gain control. 000 = 0 db (default). 001 = 4 db. 010 = 8 db. 011 = 12 db. 100 = 16 db. 101 = reserved. 110 = reserved. 111 = reserved. note: see ?an51: aero transceiver agc strategy? for details on setting the gain registers. 3:2 lnac[1:0] lna bias current control. 00 = minimum current (default). 01 = maximum current. 10 = reserved. 11 = reserved. note: program these bits to the same value as same as lnag[1:0]. 1:0 lnag[1:0] lna gain control. 00 = minimum gain (default). 01 = maximum gain. 10 = reserved. 11 = reserved. notes: 1. program these bits to the same value as lnac[1:0]. 2. see ?an51: aero transceiver agc strategy? for details on setting the gain registers. aero i + rev. 1.0 27
register 11h. configuration bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 dpds[2:0] xpd1 1 xsel 0 1 0 1 0 0 0 csel bit name function 17:14 reserved program to zero. 13:11 dpds[2:0] data path delayed start. 111= use for gsm 850 and gsm 900 bands. 011= use for dcs 1800 and pcs 1900 bands (default). note: use the recommended setting for each band. other settings reserved. 10 xpd1 reference buffer powerdown. 0 = reference buffer always powered up (default). 1 = reference buffer powered down when not in use. note: this bit should be set to 0 during normal operation. to achieve lowest si4206 powerdown current (i pdn1 ), this bit should be set to 1. 9 reserved program to one. 8 xsel reference frequency select. 0 = no divider. xin = 13 mhz (default). 1 = divide xin by 2. xin = 26 mhz. note: the internal clock should always be 13 mhz. 7 reserved program to zero. 6 reserved program to one. 5 reserved program to zero. 4 reserved program to one. 3:1 reserved program to zero. 0 csel digital iir coefficient select. 0 = high selectivity filter (default). 1 = low selectivity filter. aero i + 28 rev. 1.0
register 12h. dac configuration bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 1 xb uf 0 zdbs zerodel[2:0] daccm[1:0] dacfs[1:0] bit name function 17:11 reserved program to zero. 10 reserved program to one. 9 xbuf reference buffer power control. 0 = reference buffer powered down when not in use. 1 = reference buffer always powered up (default). note: this bit should be set to 1 during normal operation. to achieve the lowest aero i + powerdown current (i pdn1 ), this bit should be set to 0. 8 reserved program to zero. 7 zdbs zerodel band select. 0 = use zerodel[2:0] settings co rresponding to dcs/pcs column (default). 1 = use rxband[1:0] to determine zerodel[2:0] dela y setting (gsm or dcs/pcs). 6:4 zerodel[2:0] rx output zero delay. code gsm dcs/pcs 000: 90 s 130 s (default) 001: 110 s150 s 010: 130 s170 s 011: 140 s180 s 100: 150 s190 s 101: 160 s200 s 110: 180 s220 s 111: reserved note: dac input is forced to zero after pdn is deasserted. this feature can be used by the baseband processor to cancel the si4206 dac dc offset. offsets induced on channels due to 13 mhz harmonics will not be included in the calibrated value. 3:2 daccm[1:0] rx output common mode voltage. 00 = 1.0 v. 01 = 1.25 v (default). 10 = 1.35 v. 11 = reserved. 1:0 dacfs[1:0] rx output differential full scale voltage. 00 = 1.0 v ppd . 01 = 2.0 v ppd (default). 10 = 3.5 v ppd . 11 = reserved. aero i + rev. 1.0 29
register 19h. reserved bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name function 17:0 reserved program to zero. register 20h. rx master #1 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name rxband[1:0] n rf1 [15:0] aero i + 30 rev. 1.0 notes: 1. see registers 03h and 33h for bit definitions. 2. when this register is written, the pdib bit is automatically set to 0, the pdrb bit is set to 1 and the rfup bit is set as a function of rxband[1:0]. register 21h. rx master #2 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 dpds[2:0] lnac[1:0] lnag[1:0] again[2:0] 0 dgain[5:0] note: see registers 05h and 11h for bit definitions. register 22h. rx master #3 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 0 0 0 0 0 dgain[5:0] notes: 1. see register 05h for bit definitions. 2. the dgain[5:0] in register 22h c an be changed without powering down.
register 23h. tx master #1 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name txband[1:0] n rf2 [15:0] aero i + rev. 1.0 31 notes: 1. see registers 03h and 34h for bit definitions. 2. when this register is written, the pdib bit is auto matically set to 1, and the pdrb bit is set to 1. register 24h. tx master #2 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name fif[3:0] n if [13:0] note: see registers 04h and 35h for bit definitions.
register 28h. cdac (si4134t) bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 0 0 0 0 0 cdac[5:0] bit name function 17:6 reserved read as zero. 5:0 cdac[5:0] dcxo coarse frequency dac adjustment. 64 steps. 1.0 ppm typical per step. an increase in cdac results in a lower oscillating frequency. likewise, a decrease in cdac results in a higher oscillating frequency. 000000 = highest frequency ... 111111 = lowest frequency register 31h. main configuration bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 sdosel[3:0] 0 0 0 0 0 0 rfup div2 0 0 0 bit name function 17:15 reserved program to zero. 14:11 sdosel[3:0] sdo output control register. the mux_output table is as follows: 0000 connected to the output shift register (default). 0001 force the output to low. 0010 reference clock. 0011 lock detect (ldetb) signal from phase detectors. 1111 high impedance. notes: 1. sdo is high-impedance when pdn = 0. 2. sdo is serial data output when in register read mode. 10:5 reserved program to zero. 4 rfup rf pll update rate (rf1 vco only). 0 = 200 khz update rate (receive gsm modes). 1 = 100 khz update rate (receive dcs and pcs modes). notes: 1. this bit is set to 1 when register 20 h d[17:16] = 01b or 10b (dcs 1800 or pcs 1900 receive modes) and is set to 0 when d[17:16] = 00b or 11b (gsm 850 or gsm 900 modes). 2. this bit is set to 0 when register 23h is written (transmit mode) 3 div2 input clock frequency. 0 = no divider. xin = 13 mhz. 1 = divide xin by 2. xin = 26 mhz. 2:0 reserved program to zero. aero i + 32 rev. 1.0
register 32h. powerdown bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pdib pdrb bit name function 17:2 reserved program to zero. 1 pdib powerdown if pll. 0 = if synthesizer powered down. 1 = if synthesizer powered up when the pdn pin is high. notes: 1. the if pll is only used in transm it mode. powerdown for receive mode. 2. this bit is set to 0 when register 20h is written (receive mode). 3. this bit is set to 1 when register 23h is written (transmit mode). 0 pdrb powerdown rf pll. 0 = rf synthesizer powered down. 1 = rf synthesizer powered up when the pdn pin is high. notes: 1. this bit is set to 1 when register 20h is written (receive mode). 2. this bit is set to 1 when register 23h is written (transmit mode). register 33h. rf1 n divider bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 n rf1 [15:0] bit name function 17:16 reserved program to zero. 15:0 n rf1 [15:0] n divider for rf pll (rf1 vco). used for receive mode. register 34h. rf2 n divider bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 n rf2 [15:0] bit name function 17:16 reserved program to zero. 15:0 n rf2 [15:0] n divider for rf pll (rf2 vco). used for transmit mode. aero i + rev. 1.0 33
register 35h. if n divider bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0 0 n if [15:0] bit name function 17:16 reserved program to zero. 15:0 n if [15:0] n divider for if pll. used for transmit mode. aero i + 34 rev. 1.0
aero i + rev. 1.0 35 6. pin descriptions: SI4206-BM 1 2 3 22 23 24 25 26 27 28 bqp bqn xout bip rfipn rfidp gnd rfipp rfidn rfigp rfign 15 16 17 18 19 20 21 8 9 10 11 12 13 14 4 5 6 7 xtal1 xafc xdrven xtalen sdi sdo xtal2 sen sclk diag2 diag1 rfod rfog pdn xen bin v dd gnd gnd gnd gnd 32 31 30 29 pin number(s) name description 1, 2 bqp, bqn transmit/receive q signal (differential). 3, 4 bip, bin transmit/receive i signal (differential). 5 xtal1 crystal input. 6 xtal2 crystal output. 7 xafc baseband afc signal input. 8 xtalen crystal enable. 9 xdrven xdrv enable. 10 sdo serial data output. 11 sen serial enable input (active low). 12 sclk serial clock input. 13 sdi serial data input. 14, 30, 32 v dd supply voltage. 15, 29, 31 gnd ground. connect to ground plane on pcb. 16, 17 rfipp, rfipn pcs lna input (differential). use for pcs 1900 band. 18, 19 rfidp, rfidn dcs lna input (differential). use for dcs 1800 band. 20, 21 rfigp, rfign gsm lna input (differential). use for gsm 850 or e-gsm 900 bands. 22 rfod dcs and pcs transmit output to power amplifier. use for dcs 1800 and pcs 1900 bands. 23 rfog gsm transmit output to power amplifier. use for gsm 850 and e-gsm 900 bands. 24, 25 diag1, diag2 diagnostic output. can be used as digital outputs to control antenna switch functions. 26 pdn powerdown input (active low). 27 xen xout pin enable. 28 xout clock output to baseband.
aero i + 36 rev. 1.0 7. ordering guide part number description operating temperature SI4206-BM tri-band transceiver with dcxo gsm 850 or e-gsm 900, dcs 1800, pcs 1900 ?20 to 85 c note: add an ?r? at the end of the pa rt number to denote tape and reel option; 2500 quantity per reel. the si4206 is a lead-free device.
aero i + rev. 1.0 37 8. package ou tline: SI4206-BM 8.00 8.00 pin 1 indicator 1.350.07 0.10 c (4x) 0.10 2x 1.75 2x 3.80 0.10 c m a b 4x 1.20 x 1.20 0.10 c m a b 28x 0.50 x 0.30 2x 1.75 2x 3.80 top view side view bottom view 4x 1.25 6x 0.80 (=4.80) 4x 7.30 4x 4x 0.35 pin 1 4x 0.35 a c b 4x 0.50 x 0.50 0.10 c m a b figure 17. 32-pin land grid array (lga) notes: 1. dimensions in mm. 2. approximate device weight is 184 mg.
aero i + rev. 1.0 38 d ocument c hange l ist revision 0.81 to revision 1.0 ? ta b l e 8 on page 14 updated. z cvar range, cdac range, and cfix updated. ? functional description text on page 19 updated. ? figure 15, ?dcxo system signal routing diagram,? on page 21 updated. ? "ordering guide" on page 36 updated.
aero i + rev. 1.0 39 n otes :
aero i + 40 rev. 1.0 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, texas 78735 tel:1+ (512) 416-8500 fax:1+ (512) 416-9669 toll free:1+ (877) 444-3032 email: aeroinfo@silabs.com internet: www.silabs.com the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon labo ratories assumes no responsib ility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further not ice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of t he application or use of any produc t or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental da mages. silicon laboratories products are not designed, intended, or authorized for use in applica- tions intended to support or sustain life, or for any other appl ication in which the failure of the silicon laboratories produc t could create a situation where personal injury or death may occur. should bu yer purchase or use silicon laboratories products for any such uni ntended or unauthorized application, buye r shall indemnify and hold sili con laboratories harmless against all claims and damages. silicon laboratories, silicon labs, and aero are trademarks of silicon laboratories inc. other products or brand names mentioned herein are tradema rks or registered trademarks of their respective holder.

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