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11409hkim 20081021-s00001 no.a1354-1/19 specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LC75412WS overview the LC75412WS are electronic volume controllers that enable control of volume, balance, fader, bass/treble, loudness, input switching, and input gain using only a small number of external components. functions ? volume : 0db to -79db in 1db steps, and - (81 positions) balance function with separate l/r control ? fader : rear output or front output can be attenuated across 16 positions (in 1db steps from 0db to -2db, 2db steps from -2db to -20db, 10db steps from -20db to -30db, and -45db, -60db, - ) ? bass/treble : each band can be controlled in 2db steps from 0db to 18db. ? input gain : 0db to +18.75db (1.25db steps) amplification is possible for the input signal. ? input switching : six input signals can be selected for left and for right (five are singleended inputs and one is a differential input.) ? loudness : a tap is output from the -32db position of a volume control resistor ladder. a loudness function can be implemented by connecting an external rc circuit. specifications absolute maximum ratings at ta = 25 c, v ss = 0v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd 11 v maximum input voltage v in max all input pins v ss -0.3 to v dd +0.3 v operating temperature topr -40 to +85 c ordering number : ena1354 cmos ic electronic volume controller for car audio systems ? ccb is a registered trademark of sanyo electric co., ltd. ? ccb is sanyo semiconductor's original bus format. all bus addresses are managed by sanyo semiconductor for this format.
LC75412WS no.a1354-2/19 allowable operating ranges at ta = 25 c, v ss = 0v ratings parameter symbol conditions min typ max unit supply voltage v dd v dd 6.0 10 v input high-level voltage v ih cl, di, ce 4.0 10 v input low-level voltage v il cl, di, ce v ss 1.0 v input amplitude voltage v in v ss v dd vp-p input pulse width t w cl 1 s setup time tsetup cl, di, ce 1 s hold time thold cl, di, ce 1 s operating frequency fopg cl 500 khz electrical characteristics at ta = 25 c, v dd = 9v, v ss = 0v ratings parameter symbol pin name conditions min typ max unit [input block] input resistance rin l1 to l4, l6, r1 to r4, r6 30 50 70 k minimum input gain ginmin l1 to l4, l6, r1 to r4, r6 -1 0 +1 db maximum input gain ginmax +16.5 +18.75 +21 db step setting error aterr 0.6 db l/r balance bal 0.5 db [volume block] input resistance rvr lvrin, rvrin loudness off 25 50 100 k step setting error aterr 0db to -40db 0.5 db l/r balance bal 0db to -40db 0.5 db [tone block] step setting error aterr -8db to +8db 1.0 db bass control range gbass max. boost/cut 15 18 21 db treble control range gt re max. boost/cut 15 18 21 db l/r balance bal 0.5 db [fader block] input resistance rf ed lfin, rfin 25 50 100 k 0db to -2db 0.5 db -2db to -20db 1db -20db to -30db 2db step setting error aterr -30db to -60db 3db l/r balance bal 0db to -60db 0.5 db [general] thd (1) v in = 0dbv, f = 1khz 0.004 0.01 % total harmonic distortion thd (2) v in = -10dbv, f = 10khz 0.006 0.01 % input crosstalk ct v in = 1vrms, f = 1khz 80 88 db l/r crosstalk ct v in = 1vrms, f = 1khz 80 88 db vomin (1) v in = 1vrms, f = 1khz 80 88 db maximum attenuated output vomin (2) v in = 1vrms, f = 1khz inmute, fader 90 95 db vn (1) flat overall, ihf-a filter 5 10 v output noise voltage vn (2) flat overall, 20 to 20khzbpf 7 15 v current drain i dd 55 60 ma input high-level current i ih cl, di, ce, v in = 9v 10 a input low-level current i il cl, di, ce, v in = 0v -10 a maximum input voltage vcl thd = 1%, r l = 10k flat overall, f in = 1khz 2.3 2.5 vrms common-mode rejection ratio cmrr v in = 0db, f = 1khz 70 db
LC75412WS no.a1354-3/19 package dimensions unit : mm (typ) 3190a pin assignment 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (1.25) 116 17 32 33 48 49 64 sanyo : sqfp64(10x10) top view LC75412WS 61 62 63 l5m l4 l3 l2 l1 l6 l5p rfin rfout rrout tim nc rav ss mute ce di cl dv ss test lav ss lrout lfout lfin vref r6 r1 r3 r2 r4 r5m r5p v dd 64 58 59 60 55 56 57 52 53 54 49 50 51 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 15 16 33 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 13 14 11 12 9 10 7 8 5 6 3 4 lselo rselo 1 lvrin rvrin lct rct nc nc nc nc nc nc lf1c1 rf1c1 lf1c2 rf1c2 lf1c3 rf1c3 nc nc nc nc nc nc lf3c1 rf3c1 lf3c2 rf3c2 lf3c3 rf3c3 rtout ltout 2
LC75412WS no.a1354-4/19 equivalent circuit block diagra m/sample application circuit di ce cl pa l5p l5m l4 lfin com rfin rfout rrout tim rav ss mute ce di cl lav ss lrout lfout 31 35 34 33 32 logic circuit zero crossdet multiplexer zero crossdet ccb interface 30 29 28 27 26 25 24 23 22 21 20 19 18 17 dv ss 36 37 38 39 40 41 42 43 44 45 46 47 48 14 15 16 13 12 11 10 9 8 7 6 5 4 3 2 1 50 49 51 52 53 54 55 56 57 58 59 60 61 62 63 64 l3 l2 l1 l6 v dd vref r6 r1 r2 r3 r4 r5m r5p lf3c2 ltout lf1c2 lf1c1 lvref lvref lselo lvrin lct control circuit no signal timmer rf3c1 rf3c2 rtout rf1c2 rf1c1 rvref rvref rselo rvrin rct rvref lvref rvref lvref test nc 1 f 10 f 10 f 0.001 10k 22 f 0.001 10khz] 1000pf 10k 1k 0.033 f 1m rf1c3 rf3c3 nc nc nc nc nc nc lvref rvref nc lf1c3 lf3c1 lf3c3 nc nc nc nc nc 10 f 10 f 10 f 10 f [bass f0 100hz] 0.33 f 0.001 10khz] [bass f0 100hz] 0.1 f 7 1 f 7 pa pa pa multiplexer
LC75412WS no.a1354-5/19 control timing and data format to control the LC75412WS input specified serial data to the di, ce, and cl pins. the data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits. 1) address code (b0 to a3) the LC75412WS use 8-bit address code and can be used in common with ics that support sanyo?s ccb serial bus. address code b0 b1 b2 b3 a0 a1 a2 a3 (lsb) 1 0 0 0 0 0 0 1 (81hex) 2) control code allocation input switching control d0 d1 d2 setting 0 0 0 l1 (r1) 1 0 0 l2 (r2) 0 1 0 l3 (r3) 1 1 0 l4 (r4) 0 0 1 l5 (r5) 1 0 1 l6 (r6) d3 bit for ic testing: normally set to 0 input gain control d4 d5 d6 d7 operation 0 0 0 0 0db 1 0 0 0 +1.25db 0 1 0 0 +2.50db 1 1 0 0 +3.75db 0 0 1 0 +5.00db 1 0 1 0 +6.25db 0 1 1 0 +7.50db 1 1 1 0 +8.75db 0 0 0 1 +10.00db 1 0 0 1 +11.25db 0 1 0 1 +12.50db 1 1 0 1 +13.75db 0 0 1 1 +15.00db 1 0 1 1 +16.25db 0 1 1 1 +17.50db 1 1 1 1 +18.75db 1 t dest ce di d43 d42 d41 d40 d39 d38 d5 d4 d3 d2 d0 d1 a3 a2 a1 a0 b3 b2 b1 b0 cl 1
LC75412WS no.a1354-6/19 volume control (0 to -50db) d8 d9 d10 d11 d12 d13 d14 d15 operation 0 0 0 0 0 0 0 0 0db 1 0 0 0 0 0 0 0 -1db 0 1 0 0 0 0 0 0 -2db 1 1 0 0 0 0 0 0 -3db 0 0 1 0 0 0 0 0 -4db 1 0 1 0 0 0 0 0 -5db 0 1 1 0 0 0 0 0 -6db 1 1 1 0 0 0 0 0 -7db 0 0 0 1 0 0 0 0 -8db 1 0 0 1 0 0 0 0 -9db 0 1 0 1 0 0 0 0 -10db 1 1 0 1 0 0 0 0 -11db 0 0 1 1 0 0 0 0 -12db 1 0 1 1 0 0 0 0 -13db 0 1 1 1 0 0 0 0 -14db 1 1 1 1 0 0 0 0 -15db 0 0 0 0 1 0 0 0 -16db 1 0 0 0 1 0 0 0 -17db 0 1 0 0 1 0 0 0 -18db 1 1 0 0 1 0 0 0 -19db 0 0 1 0 1 0 0 0 -20db 1 0 1 0 1 0 0 0 -21db 0 1 1 0 1 0 0 0 -22db 1 1 1 0 1 0 0 0 -23db 0 0 0 1 1 0 0 0 -24db 1 0 0 1 1 0 0 0 -25db 0 1 0 1 1 0 0 0 -26db 1 1 0 1 1 0 0 0 -27db 0 0 1 1 1 0 0 0 -28db 1 0 1 1 1 0 0 0 -29db 0 1 1 1 1 0 0 0 -30db 1 1 1 1 1 0 0 0 -31db 0 0 0 0 0 1 0 0 -32db 1 0 0 0 0 1 0 0 -33db 0 1 0 0 0 1 0 0 -34db 1 1 0 0 0 1 0 0 -35db 0 0 1 0 0 1 0 0 -36db 1 0 1 0 0 1 0 0 -37db 0 1 1 0 0 1 0 0 -38db 1 1 1 0 0 1 0 0 -39db 0 0 0 1 0 1 0 0 -40db 1 0 0 1 0 1 0 0 -41db 0 1 0 1 0 1 0 0 -42db 1 1 0 1 0 1 0 0 -43db 0 0 1 1 0 1 0 0 -44db 1 0 1 1 0 1 0 0 -45db 0 1 1 1 0 1 0 0 -46db 1 1 1 1 0 1 0 0 -47db 0 0 0 0 1 1 0 0 -48db 1 0 0 0 1 1 0 0 -49db 0 1 0 0 1 1 0 0 -50db continued on next page.
LC75412WS no.a1354-7/19 continued from preceding page. volume control (-51 to - db) d8 d9 d10 d11 d12 d13 d14 d15 operation 1 1 0 0 1 1 0 0 -51db 0 0 1 0 1 1 0 0 -52db 1 0 1 0 1 1 0 0 -53db 0 1 1 0 1 1 0 0 -54db 1 1 1 0 1 1 0 0 -55db 0 0 0 1 1 1 0 0 -56db 1 0 0 1 1 1 0 0 -57db 0 1 0 1 1 1 0 0 -58db 1 1 0 1 1 1 0 0 -59db 0 0 1 1 1 1 0 0 -60db 1 0 1 1 1 1 0 0 -61db 0 1 1 1 1 1 0 0 -62db 1 1 1 1 1 1 0 0 -63db 0 0 0 0 0 0 1 0 -64db 1 0 0 0 0 0 1 0 -65db 0 1 0 0 0 0 1 0 -66db 1 1 0 0 0 0 1 0 -67db 0 0 1 0 0 0 1 0 -68db 1 0 1 0 0 0 1 0 -69db 0 1 1 0 0 0 1 0 -70db 1 1 1 0 0 0 1 0 -71db 0 0 0 1 0 0 1 0 -72db 1 0 0 1 0 0 1 0 -73db 0 1 0 1 0 0 1 0 -74db 1 1 0 1 0 0 1 0 -75db 0 0 1 1 0 0 1 0 -76db 1 0 1 1 0 0 1 0 -77db 0 1 1 1 0 0 1 0 -78db 1 1 1 1 0 0 1 0 -79db *1 1 1 1 1 1 1 0 - *1: ?0? or ?1?
LC75412WS no.a1354-8/19 tone control d16 d17 d18 d19 d40 bass d24 d25 d26 d27 d41 treble 1 1 0 0 1 +18db 0 1 0 0 1 +16db 1 0 0 0 1 +14db 0 1 1 0 0 +12db 1 0 1 0 0 +10db 0 0 1 0 0 +8db 1 1 0 0 0 +6db 0 1 0 0 0 +4db 1 0 0 0 0 +2db 0 0 0 0 0 0db 1 0 0 1 0 -2db 0 1 0 1 0 -4db 1 1 0 1 0 -6db 0 0 1 1 0 -8db 1 0 1 1 0 -10db 0 1 1 1 0 -12db 1 0 0 1 1 -14db 0 1 0 1 1 -16db 1 1 0 1 1 -18db d20 d21 d22 d23 setting 0 0 0 0 set to 0 fader volume control d28 d29 d30 d31 operation 0 0 0 0 0db 1 0 0 0 -1db 0 1 0 0 -2db 1 1 0 0 -4db 0 0 1 0 -6db 1 0 1 0 -8db 0 1 1 0 -10db 1 1 1 0 -12db 0 0 0 1 -14db 1 0 0 1 -16db 0 1 0 1 -18db 1 1 0 1 -20db 0 0 1 1 -30db 1 0 1 1 -45db 0 1 1 1 -60db 1 1 1 1 -
LC75412WS no.a1354-9/19 channel selection control d32 d33 setting 1 0 rch 0 1 lch 1 1 l/r simultaneously fader rear/front control d34 setting 0 rear 1 front loudness control d35 setting 0 off 1 on zero-cross control d36 d37 setting 0 0 data write through zero-cross detection 1 1 zero-cross detection stopped (d ata write at falling edge of ce) zero-cross signal detection block control d38 d39 setting 0 0 selector 1 0 volume 0 1 tone 1 1 fader test mode control d42 d43 setting 0 0 for ic testing. always set to 0.
LC75412WS no.a1354-10/19 pin functions pin pin no. function equivalent circuit l1 l2 l3 l4 l6 r1 r2 r3 r4 r6 54 53 52 51 55 59 60 61 62 58 ? single-end input pins. l5m l5p r5m r5p 50 49 63 64 ? differential input pins. lselo rselo 48 1 ? input selector output pins. lct rct 46 3 ? loudness pins. connect high-pass compensation cr between lct (rct) and lvrin (rvrin), and connect low-pass compensation cr between lct (rct) and gnd. lvrin rvrin 47 2 ? volume and equalizer input pins. lf1c1 lf1c2 lf1c3 rf1c1 rf1c2 rf1c3 42 41 40 7 8 9 ? equalizer f1 band filter configuration capacitor connection pins. connect capacitor between lf1c1 (rf1c1) and lf1c2 (rf1c2) lf1c2 (rf1c2) and lf1c3 (rf1c3) lf3c1 lf3c2 lf3c3 rf3c1 rf3c2 rf3c3 36 35 34 13 14 15 ? equalizer f3 band filter configuration capacitor connection pins. connect capacitor between lf3c1 (rf3c1) and lf3c2 (rf3c2) lf3c2 (rf3c2) and lf3c3 (rf3c3) continued on next page. v dd lvref rvref v dd m v dd p lvref rvref v dd v dd v dd v dd fnc1 v dd v dd fnc3 v dd fnc2
LC75412WS no.a1354-11/19 continued from preceding page. pin pin no. function equivalent circuit nc nc nc nc nc nc nc nc nc nc nc nc nc 45 44 43 39 38 37 21 12 11 10 6 5 4 ? no connect pin. test 28 ? dedicated ic test pin. ? normally this pin is used connected to gnd. ltout rtout 33 16 ? equalizer output pins. lfin rfin 32 17 ? fader block input pins. ? drive at low impedance. lfout lrout rfout rrout 31 30 18 19 ? fader output pins. attenuation is possible separately for the front end and rear end. the attenuation amount is the same for l and r. vref 57 ? connect a capacitor of a few tens of f between vref and av ss (v ss ) as a v dd /2 voltage generator, current ripple countermeasure. v dd 56 ? power supply pin. dv ss 27 ? logic system ground pin. lav ss rav ss 29 22 ? analog system ground pins. mute 23 ? external muting control pin. ? setting this pin to v ss level sets forcibly fader volume block to - level. continued on next page. v dd v dd v dd v dd v dd lvref rvref v dd
LC75412WS no.a1354-12/19 continued from preceding page. pin pin no. function equivalent circuit tim 20 ? timer pin when there is no signal in the zero-cross circuit. forcibly set data when there is no zero-cross signal, from the time the data is set until the timer ends. cl di 26 25 ? input pin for serial data and clock used for control. ce 24 ? chip enable pin. data is written to the internal latch and the analog switches are operated when the level changes from high to low. data transfer is enabled when the level is high. internal equivalent circuit block diagram selector block equivalent circuit block diagram v dd v dd total resistance: 50k same for right channel 1.25db 2.50db 3.75db 5.00db 6.25db 7.50db 8.75db l5p l5m lselo 0db r3=22.65k r4=25k r2=25k r1=22.65k 50k 50k 50k 50k lvref lvref lvref 6.702k 5.804k 5.026k 4.352k 3.769k 3.264k 2.826k 2.447k 2.119k 1.835k 1.589k 1.376k 1.192k 1.032k 0.894k 5.774k lvref 10.00db 11.25db 12.50db 13.75db 15.00db 16.25db 17.50db 18.75db l3 l2 lvref lvref inmute sw lvref l1 l6 50k lvref l4
LC75412WS no.a1354-13/19 volume block equivalent circuit block diagram same for right channel lvrin lvref to tone block -1db 0db r55=133 r28=243 r56=119 r57=106 r1=5434 r29=216 r30=193 r2=4845 r3=4319 r4=3850 r5=3431 r6=3058 r7=2726 -3db -4db -9db -10db -2db -5db -6db -8db -7db -11db -13db -14db -12db -19db -20db -21db -15db -16db -18db -17db -26db -27db -22db -23db -25db -24db -37db -38db -40db -41db -39db -46db -47db -48db -42db -43db -45db -44db -53db -54db -49db -50db -52db -51db -64db -65db -67db -68db -66db -73db -74db -75db -69db -70db -72db -71db - -76db -77db -79db -78db -28db -29db -31db -32db -30db -33db -34db -35db -36db -55db -56db -58db -59db -57db -60db -61db -63db -62db 1500 1227 1230 1236 1233 r85 r84 r83 r82 r81 lct r8=2429 r9=2165 r10=1930 r11=1720 r12=1533 r13=1366 r14=1218 r15=1085 r16=967 r17=862 r18=768 r19=685 r20=610 r21=544 r22=485 r23=432 r24=385 r25=343 r26=306 r27=273 r31=172 r32=153 r33=839 r34=748 r35=667 r36=594 r37=530 r38=472 r39=421 r40=375 r41=334 r42=298 r43=266 r44=237 r45=211 r46=188 r47=168 r48=149 r49=133 r50=119 r51=106 r52=94 r53=84 r54=75 r58=94 r59=84 r60=75 r61=134 r62=119 r63=106 r64=95 r65=84 r66=75 r67=134 r68=119 r69=106 r70=95 r71=85 r72=75 r73=134 r74=120 r75=107 r76=95 r77=85 r78=76 r79=67 r80=552 r86 1m total resistance of 48.746k over tap total resistance of 1.256k under tap (loud off) total resistance of 7.662k under tap (loud on) 0db& - asw=1k others asw=3k
LC75412WS no.a1354-14/19 tone control block equivalent circuit diagram during boost, sw1 and sw3 are on, during cut sw2 and sw4 are on, and when 0db, 0db sw and sw2 and sw3 are on. ltout total resistance: 59.359k same for right channel from volume block 18db 16db 14db 12db 10db lf1c1 lf1c3 8db 6db 4db 2db 0db sw1 sw2 sw3 sw4 2.189k 2.756k 3.470k 4.368k 5.498k 6.923k 8.715k 10.972k 13.813k 0.655k lf1c2 3.90k 18db 16db 14db 12db 10db lf3c1 lf3c3 8db 6db 4db 2db 0db sw1 sw2 sw3 sw4 0.655k 2.189k 2.756k 3.470k 4.368k 5.498k 6.923k 8.715k 10.972k 13.813k lf3c2 3.90k
LC75412WS no.a1354-15/19 f1/f3 band circuit the equivalent circuit and the formula for calculating the ex ternal cr with a mean frequency of 1khz are shown below. ? f1/f3 band equivalent circuit block diagram ? calculation example specification mean frequency : f0 = 1khz gain during maximum boost : g +18db = 18db let us use r1 = 0.665k , r2 = 58.704k , and c1 = c2 = c. 1) calculate r3 with g +18db = 18db: 2) calculate c with the cen ter frequency f0 = 1khz 3) calculate q: r1 r3 c2 c1 r2 3900 ? 2 r1 1 10 r2 r3 g/20 = ? = ? ? ? ? ? ? ? r2)r3c1c2 (r1 2 1 f0 + = () () 1.789 r1 2r3 r2 r1 r3 r2)r3 (r1 1 q ? + + + = ( ) r1 2r3 r2 1 log 20 g 10 18db + + = + f 0.01 10 0.010 3900 39359 1000 2 1 r2)r3 (r1 f0 2 1 c 6 ? = = + = ?
LC75412WS no.a1354-16/19 fader volume block equivalent circuit block diagram when - data is sent to the main volume, s1 and s2 be come open, and s3 and s4 simultaneously become on. lfin 5.437k when fader = "1", s2 and s3 are on. when fader = "0", s1 and s4 are on. total resistance: 50k same for right channel 4.846k 8.169k 4.094k lfout lvref -1db -2db 0db s1 s2 s3 s4 6.489k 5.154k -6db -8db -4db 3.252k 2.583k 2.052k 3.419k -12db -14db -10db 1.630k 1.295k -18db -20db -16db 1.300k 0.231k -45db -60db - db -30db 0.050k lrout
LC75412WS no.a1354-17/19 usage cautions (1) data transmission at power on the status of internal analog switches is unstable at power on. therefore, perform muting or some other countermeasure until the data has been set. (2) description of zero-cross switching circuit operation the LC75412WS have a function to switch zero-cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated. basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zero-cross comparator, so it is necessary to switch the detection location every time. LC75412WS zero-cross detection circuit (3) zero-cross switching control method the zero-cross switching control method consists of settin g the zero-cross control bits to the zero-cross detection mode (d36, d37 = 0), and specifying the detection blocks (d38, d39) before transmitting the data. these control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of ce, so when updating data of volumes, etc., it is possible to perform mode setting and zero-cross switching with one data transfer. an example of control when updating the data of the volume block is shown below. d36 d37 d38 d39 0 0 1 0 (4) zero-cross timer setting if the input signal becomes lower than the zero-cross co mparator detection sensitivity, or if only low-frequency signals are input, zero-cross detection continues to be impossible, and data is not latched during this time. the zero-cross timer can set a time for forcible latch during such a status when zero-cro ss detection is not possible. for example, to set 25ms, using t = 0.69cr and c = 0.033 f, we obtain r= 1.1m normally, a value between 10ms and 50ms is set. volume tone switch fader zero-cross comparator selector volume block setting zero-cross detection mode setting 2510 - 3 0.690.03310 -6
LC75412WS no.a1354-18/19 (5) cautions related to serial data transfer 1) to ensure that the high-frequency digital signals transferred to the cl, di, and ce pins do not spill over to the analog signal block, either guard these signal lines with a ground pattern, or perform transmission using shielded wires. 2) the data format of the LC75412WS uses 8-bit addresses and 44-bit data. when sending data using multiples of 8 (when sending 48 bits), use the method described in figure 1. method for receiving data using multiple of 8 of LC75412WS figure 1 (6) note on usage of external muting see figure 2, to control muting with an external switch. if a microcontroller is used for the control, it is likely that an overvoltage is applied to the microcon troller via the mute pin because the mute pin is connected internally to v dd . to avoid such problems, add the resister r2 as shown in figure 3 to resistor-divide the voltage at the mute pin. figure 2 figure 3 as an example, the relationship between the voltage s at the mute pin and the values of r2 when v dd is 9 volts is shown below. the characteristic curve sh own in the figure is a standard one. *v ih (high detection voltage) at the mute pin must always be 4v or higher regardless of the supply voltage to be used. d43 d42 d41 d40 d39 d38 d37 d36 ????? d3 d2 d1 d0 x x x x test mode control input switching control dummy data x: don?t care switch mute v dd r1 mute microcontroller r2 v dd r1 50 0 100 150 200 2 0 4 6 8 10 mute pin voltage - v r2 - k ta=25 c relationship between r2 values and mute pin voltages when v dd is 9 volt
LC75412WS no.a1354-19/19 ps this catalog provides information as of january, 2009. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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