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pxd20 microcontroller reference manual devices supported: pxd2020 PXD20RM rev. 1 09/2011
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com document number: PXD20RM rev. 1 09/2011 information in this document is provided solely to enable system and software implementers to use freescale semicond uctor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the ri ght to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of an y product or circuit, and specifically disclaims any and all liability, includ ing without limitati on consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical expe rts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semico nductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2011. all rights reserved.
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor iii table of contents chapter 1 introduction 1.1 the pxd20 microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 pxd20 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.4 feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5.1 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.5.2 e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5.3 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.5.4 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.5.5 interrupt controller (intc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.5.6 quadspi serial flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5.7 system integration unit lite (siul) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5.8 on-chip flash memory with ecc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5.9 static random-access memory (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.5.10 on-chip graphics sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.5.11 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.5.12 2d graphics accelerator (gfx2d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.5.13 display control unit (dcu3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.5.14 display control unit lite (dculite) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.5.15 timing controller (tcon) and rsds interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.5.16 rle decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.5.17 dram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.5.18 video input unit (viu2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.5.19 boot assist module (bam) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.5.20 enhanced modular input/output system (emios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.5.21 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.5.22 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.5.23 controller area network (can) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.5.24 serial communication interface module (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.5.25 inter-integrated circuit (i2c) controller modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.5.26 system clocks and clock generat ion modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.5.27 periodic interrupt timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.5.28 real time counter (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.5.29 system timer module (stm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.5.30 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.5.31 stepper motor controller (smc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.5.32 stepper stall detect (ssd) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.5.33 sound generator module (sgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.5.34 ieee 1149.1 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.5.35 nexus development interface (ndi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.6 how to use the pxd20 documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.6.1 the pxd20 document set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.6.2 reference manual content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.7 using the pxd20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.7.1 hardware design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.7.2 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.7.3 software design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.7.4 other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor iv chapter 2 memory map chapter 3 signal description 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.1 pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.2 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.3.3 pad types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.4 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.3.5 nexus pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.3.6 dram interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.3.7 viu muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.8 sgm muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.3.9 rsds special function muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.3.10 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 chapter 4 safety 4.1 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1.3 modes of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.3.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.1.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.1.4.2 change lock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.1.4.3 access errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.1.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.4 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.6 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.6.1 swt control register (swt_cr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.6.2 swt interrupt register (swt_ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.2.6.3 swt time-out register (swt_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.2.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 chapter 5 analog-to-digital converter (adc) 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 device-specific features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 device-specific implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.2 control logic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor v 5.3.2.1 main configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.2.2 main status register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.3.1 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.3.2 channel pending registers (ceocfr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.3.3 interrupt mask register (imr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.3.4 channel interrupt mask register (cimr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 5.3.3.5 watchdog threshold interrupt status register (wtisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.3.3.6 watchdog threshold interrupt mask register (wtimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 5.3.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.4.1 dma enable register (dmae) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.4.2 dma channel select register (dmar[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.3.5 threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16 5.3.5.2 threshold control register (trcx, x = [0..3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.5.3 threshold register (thrhlr[0:3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17 5.3.6 conversion timing registers ctr[1..2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.3.7 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.7.2 normal conversion mask registers (ncmr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.3.7.3 injected conversion mask registers (jcmr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.3.8 delay registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.3.8.1 decode signals delay register (dsdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.3.8.2 power-down exit delay register (pdedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22 5.3.9 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.3.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.3.9.2 channel data register (cdr n ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.4.1 analog channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.4.1.1 normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.4.1.2 start of normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25 5.4.1.3 normal conversion operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.4.1.4 injected channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.1.5 abort conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.2 analog clock generator and conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.3 adc sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.4 programmable analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.4.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.4.5 dma functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.4.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.4.7 external decode signals delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.4.8 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.4.9 auto-clock-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 chapter 6 boot assist module (bam) 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3 boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.5.1 entering boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.5.2 reset configuration half word source (rchw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.5.3 single chip boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.3.1 boot and alternate boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.4 boot through bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.4.1 executing bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.4.2 bam software flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.4.3 bam resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5.4.4 download and execute the new code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5.4.5 download 64-bit password and password check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.5.4.6 download start address, vle bit and code size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor vi 6.5.4.7 download data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.4.8 execute code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.5 boot from uart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.5.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.5.2 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.6 bootstrap with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.6.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.6.2 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.5.7 flash memory password swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.5.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 chapter 7 can sampler 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3.1 can sampler control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3.2 can sampler sample registers 0?11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4.1 enabling/disabling the can sampler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.2 selecting the rx port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.3 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 chapter 8 clock description 8.1 clock architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 auxiliary clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3 clock generation module (mc_cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.3.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.3.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 8.3.4.1 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 8.3.4.2 dividers functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.3.4.3 dram controller clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 8.3.4.4 output clock multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 8.3.4.5 output clock division selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 8.4 oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1 pierce oscillator (fxosc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.4.1.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 8.4.1.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 8.4.1.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 8.4.2 external crystal oscillator (sxosc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.4.2.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.4.2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.4.2.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 8.4.3 sirc digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 8.4.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 8.4.3.2 slow internal rc oscillator (128 khz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 8.4.3.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35 8.4.4 firc digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.4.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.4.4.2 functional description (16 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor vii 8.4.4.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8.5 frequency-modulated phase-locked l oop (fmpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8.5.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38 8.5.3 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38 8.5.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 8.5.5 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 8.5.5.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 8.5.5.2 modulation register (mr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42 8.5.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 8.5.6.1 normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 8.5.6.2 progressive clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 8.5.6.3 normal mode with frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 8.5.6.4 powerdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.5.6.5 1:1 mode (fmpll0 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.5.7 recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.6 clock monitor unit (cmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47 8.6.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48 8.6.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48 8.6.4.1 control status register (cmu_csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-49 8.6.4.2 frequency display register (cmu_fdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-50 8.6.4.3 high frequency reference register fmpll0 (cmu_hfrefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-50 8.6.4.4 low frequency reference register fmpll0 (cmu_lfrefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-51 8.6.4.5 interrupt status register (cmu_isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-51 8.6.4.6 measurement duration register (cmu_mdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52 8.6.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-52 8.6.5.1 crystal clock monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53 8.6.5.2 pll clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53 8.6.5.3 frequency meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-53 8.7 clock monitor unit (cmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-54 8.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-54 8.7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-55 8.7.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-56 8.7.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-56 8.7.4.1 control status register (cmu_csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-57 8.7.4.2 frequency display register (cmu_fdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-58 8.7.4.3 high frequency reference register fmpll0 (cmu_hfrefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-58 8.7.4.4 low frequency reference register fmpll0 (cmu_lfrefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-59 8.7.4.5 interrupt status register (cmu_isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-59 8.7.4.6 measurement duration register (cmu_mdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-60 8.7.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-60 8.7.5.1 crystal clock monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-61 8.7.5.2 pll clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-61 8.7.5.3 frequency meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-61 chapter 9 crossbar switch (xbar) 9.1 information specific to this device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.1 device-specific block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.2 xbar master id numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.3 unsupported features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.2.3 limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.2.4 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.3 xbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.3.2 xbar register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.3.2.1 master priority register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor viii 9.3.2.2 slave general purpose control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.3.2.3 master general purpose control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.3.3 coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.1 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.1.1 arbitration during undefined length bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.1.2 fixed priority operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.1.3 round-robin priority operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.4.2 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.4.2.1 context switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.4.2.2 priority elevation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.3 master port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.4.3.2 master port decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.3.3 master port capture unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.3.4 master port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.3.5 master port state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.4 slave port functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.4.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.4.4.2 slave port muxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-19 9.4.4.3 slave port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.4.4.4 slave port state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 9.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 9.6 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 9.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.6.2 master ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.6.2.1 ignored accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.6.2.2 terminated accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.6.2.3 taken accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.6.2.4 stalled accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 9.6.2.5 error response terminated accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.6.3 slave ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 chapter 10 deserial serial peripheral interface (dspi) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.3 module disable mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.5.4 external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.5.5 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.6 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.7 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.7.1 signal overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.7.2 signal names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.7.2.1peripheral chip select / slave select (cs_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.7.2.2peripheral chip selects 1?2 (cs1:2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.7.2.3serial input (sin_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.7.2.4serial output (sout_x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.7.2.5serial clock (sck_ x ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.8 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.8.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.8.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.8.2.1dspi module configuration register (dspix_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.8.2.2dspi transfer count register (dspix_tcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.8.2.3dspi clock and transfer attributes registers 0?7 (dspix_ctarn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.8.2.4dspi status register (dspix_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-16 10.8.2.5dspi dma / interrupt request select and enable register (dspix_rser). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor ix 10.8.2.6dspi push tx fifo register (dspix_pushr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.8.2.7dspi pop rx fifo register (dspix_popr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22 10.8.2.8dspi transmit fifo registers 0?4 (dspix_txfrn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.8.2.9dspi receive fifo registers 0?4 (dspix_rxfrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23 10.9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.9.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.9.1.1master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25 10.9.1.2slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.9.1.3module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.9.1.4external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.9.1.5debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.9.2 start and stop of dspi transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-26 10.9.3 serial peripheral interface (spi) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.9.3.1spi master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.9.3.2spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.9.3.3fifo disable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.9.3.4transmit first in first out (tx fifo) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.9.3.5receive first in first out (rx fifo ) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29 10.9.4 dspi baud rate and clock delay generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.9.4.1baud rate generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.9.4.2cs to sck delay (tcsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.9.4.3after sck delay (tasc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.9.4.4delay after transfer (tdt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32 10.9.5 transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33 10.9.5.1classic spi transfer format (cpha = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34 10.9.5.2classic spi transfer format (cpha = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35 10.9.5.3modified spi transfer format (mtfe = 1, cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36 10.9.5.4modified spi transfer format (mtfe = 1, cpha = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10.9.5.5continuous selection format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38 10.9.5.6clock polarity switching between dspi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39 10.9.6 continuous serial communications clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40 10.9.7 interrupts/dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41 10.9.7.1end of queue interrupt request (eoqf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42 10.9.7.2transmit fifo fill interrupt or dma request (tfff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42 10.9.7.3transfer complete interrupt request (tcf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42 10.9.7.4transmit fifo underflow interrupt request (tfuf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.9.7.5receive fifo drain interrupt or dma request (rfdf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.9.7.6receive fifo overflow interrupt request (rfof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.9.7.7fifo overrun request (tfuf) or (rfof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.9.8 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.9.8.1external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 10.9.8.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.9.8.3slave interface signal gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.10 initialization and application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.10.1how to change queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-44 10.10.2baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-45 10.10.3delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46 10.10.4calculation of fifo pointer addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-46 10.10.4.1address calculation for the first-in entry and last-in entry in the tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47 10.10.4.2address calculation for the first-in entry and last-in entry in the rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-47 chapter 11 display control unit (dcu3) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.2.2 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor x 11.3.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.3.3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11.3.4.1control descriptor l0_1 register (ctrldescl0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.3.4.2control descriptor l0_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.3.4.3control descriptor l0_3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.3.4.4control descriptor l0_4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.3.4.5control descriptor l0_5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.3.4.6control descriptor l0_6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.3.4.7control descriptor l0_7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.3.4.8control descriptor cursor 1 register (ctrldesccursor_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.3.4.9control descriptor cursor 2 register (ctrldesccursor_2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.3.4.10control descriptor cursor 3 register (ctrldesccursor_3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.3.4.11control descriptor cursor 4 register (ctrldesccursor_4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.3.4.12dcu3 mode register (dcu_mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-34 11.3.4.13bgnd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 11.3.4.14disp_size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11.3.4.15hsyn_para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11.3.4.16vsyn_para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.3.4.17syn_pol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11.3.4.18threshold register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 11.3.4.19interrupt status register (int_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11.3.4.20interrupt mask register (int_mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-42 11.3.4.21colbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.3.4.22divide ratio register (div_ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.3.4.23sign_calc_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-49 11.3.4.24sign_calc_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 11.3.4.25crc_val register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-50 11.3.4.26pdi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51 11.3.4.27pdi status mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-52 11.3.4.28parr_err_status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-53 11.3.4.29mask parr_err status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-56 11.3.4.30threshold_inp_buf_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-58 11.3.4.31threshold_inp_buf_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-59 11.3.4.32luma component register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-59 11.3.4.33red chroma components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-60 11.3.4.34green chroma component register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-60 11.3.4.35blue chroma component register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-61 11.3.4.36crc_pos register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-62 11.3.4.37fg0_fcolor register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-62 11.3.4.38fg0_bcolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-63 11.3.4.39lyr_intpol_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65 11.3.4.40lyr_luma_component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-65 11.3.4.41lyr_chroma_red . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-66 11.3.4.42lyr_chroma_green . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-66 11.3.4.43lyr_chroma_blue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67 11.3.4.44comp_imsize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68 11.3.4.45global protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68 11.3.4.46soft lock bit register l0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-69 11.3.4.47soft lock bit register l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-71 11.3.4.48soft lock disp_size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-72 11.3.4.49soft lock hsync/vsync para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-73 11.3.4.50soft lock pol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-74 11.3.4.51soft lock l0_transp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-74 11.3.4.52soft lock l1_transp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-76 11.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-76 11.4.1 graphic sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-77 11.4.2 tft lcd panel configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-77 11.4.3 dcu3 mode selection and background color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-79 11.4.4 layer configuration and blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-80 11.4.4.1blending priority of layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-81 11.4.4.2control descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-83 11.4.4.3layer size and positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-83
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xi 11.4.4.4graphics and data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-84 11.4.4.5alpha and chroma-key blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-88 11.4.4.6transparency mode and blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-94 11.4.4.7luminance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-97 11.4.4.8tile mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-98 11.4.5 hardware cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-99 11.4.6 clut/tile ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-100 11.4.7 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-101 11.4.8 temporal dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-102 11.4.9 special ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-103 11.4.10run length encoding (rle) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-103 11.4.10.1rle decoding scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-104 11.5 timing, error and interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-104 11.5.1 synchronizing to panel frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-105 11.5.2 managing the dcu3 fifos and dma activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-105 11.5.3 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-107 11.5.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-107 11.6 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-108 11.6.1 operation of scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-108 11.6.2 list of protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109 11.7 safety mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-109 11.7.1 crc area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-111 11.7.1.1configuring the crc calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-111 11.7.2 summary of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-112 11.8 parallel data interface (camera interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113 11.8.1 pdi interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113 11.8.1.1introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113 11.8.1.2pdi interaction with other modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-113 11.8.1.3features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-115 11.8.1.4itu-r bt.656 sync information extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-115 11.8.1.5normal and narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-117 11.8.1.6modes of operation based on sync extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-119 11.8.1.7mode of operation depending on pdi[17:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-123 11.8.1.8pdi-related interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-124 11.9 switch between dcu mode and pdi mode (top-level description). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-125 11.9.1 changes in the configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-126 11.9.1.1pdi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-126 11.9.1.2pdi sync detection/validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-126 11.9.1.3other assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-127 11.10 dcu3 initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-127 11.11 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-128 chapter 12 display control unit lite (dculite) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.1 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.3 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 12.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.3.4.1control descriptor l0_1 register (ctrldescl0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.3.4.2control descriptor l0_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20 12.3.4.3control descriptor l0_3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 12.3.4.4control descriptor l0_4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.3.4.5control descriptor l0_5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 12.3.4.6control descriptor l0_6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 12.3.4.7control descriptor l0_7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xii 12.3.4.8control descriptor cursor 1 register (ctrldesccursor_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 12.3.4.9control descriptor cursor 2 register (ctrldesccursor_2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26 12.3.4.10control descriptor cursor 3 register (ctrldesccursor_3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.3.4.11control descriptor cursor_4 register (ctrldesccursor_4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.4.12dculite mode register (dcu_mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.4.13bgnd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.3.4.14disp_size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31 12.3.4.15hsyn_para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.4.16vsyn_para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.4.17syn_pol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33 12.3.4.18threshold register (threshold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-34 12.3.4.19interrupt status register (int_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 12.3.4.20interrupt mask register (int_mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12.3.4.21colbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12.3.4.22clock divider ratio (div_ratio) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-41 12.3.4.23sign_calc_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12.3.4.24sign_calc_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 12.3.4.25crc_val register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43 12.3.4.26pdi status register (pdi_status). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44 12.3.4.27pdi status mask register (mask_pdi_status). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-45 12.3.4.28parr_err status register (parr_err_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46 12.3.4.29mask_parr_err_status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48 12.3.4.30threshold_input buf_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49 12.3.4.31luma component register (luma). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12.3.4.32red chroma components (red) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12.3.4.33green chroma component register (green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.3.4.34blue chroma component register (blue) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.3.4.35crc_pos register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52 12.3.4.36fg0_fcolor register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.3.4.37fg0_bcolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-53 12.3.4.38lyr_intpol_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 12.3.4.39lyr_luma_component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 12.3.4.40lyr_chroma_red . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-55 12.3.4.41lyr_chroma_green . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56 12.3.4.42lyr_chroma_blue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56 12.3.4.43comp_imsize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57 12.3.4.44global protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-57 12.3.4.45soft lock bit register l0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-58 12.3.4.46soft lock bit register l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59 12.3.4.47soft lock disp_size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61 12.3.4.48soft lock hsync/vsync para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62 12.3.4.49soft lock pol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 12.3.4.50soft lock l0_transp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 12.3.4.51soft lock l1_transp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 12.4.1 graphic sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-66 12.4.2 tft lcd panel configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-66 12.4.3 dculite mode selection and background color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-68 12.4.4 layer configuration and blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-69 12.4.4.1blending priority of layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-70 12.4.4.2control descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-72 12.4.4.3layer size and positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-72 12.4.4.4graphics and data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-73 12.4.4.5alpha and chroma-key blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-76 12.4.4.6transparency mode and blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-83 12.4.4.7luminance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-86 12.4.4.8tile mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-87 12.4.5 hardware cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-88 12.4.6 clut ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-89 12.4.7 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-90 12.4.8 temporal dithering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-91 12.4.9 special ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-92 12.4.10run length encoding (rle) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-92
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xiii 12.4.10.1rle decoding scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-93 12.5 timing, error and interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-93 12.5.1 synchronizing to panel frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-94 12.5.2 managing the dculite fifos and dma activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-94 12.5.3 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-96 12.5.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-96 12.6 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-97 12.6.1 operation of scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-97 12.6.2 list of protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98 12.7 safety mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98 12.7.1 crc area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-100 12.7.1.1configuring the crc calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-100 12.7.2 summary of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-101 12.8 parallel data interface (camera interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-102 12.8.1 pdi interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-102 12.8.1.1introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-102 12.8.1.2pdi interaction with other modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-102 12.8.1.3features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-104 12.8.1.4itu-r bt.656 sync information extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-104 12.8.1.5normal and narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-106 12.8.1.6modes of operation based on sync extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-108 12.8.1.7mode of operation depending on pdi[17:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-112 12.8.1.8pdi-related interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-113 12.9 switch between dcu mode and pdi mode (top-level description). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-114 12.9.1 changes in the configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-115 12.9.1.1pdi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-115 12.9.1.2pdi sync detection/validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-115 12.9.1.3other assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-116 12.10 dculite initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-116 12.11 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-116 chapter 13 dram controller (dramc) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.2.1dramc system configuration register (dramc_scr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.2.2timing configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.3.2.3dramc command register (dramc_cmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.3.2.4dramc compact command register (dramc_ccmd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.3.2.5dqs config offset count register (dramc_dqs_oc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.3.2.6dqs config offset time register (dramc_dqs_ot). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.3.2.7dqs delay status (dramc_dqs_ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16 13.3.2.8dramc extra attributes (dramc_extra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.4.1 interfacing with the dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.4.1.1connecting the dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.4.2 programming dram device internal configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.4.3 dram command engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.4.4 write buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.4.5 timing manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.4.6 dram read block and dram write block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 13.4.7 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 chapter 14 dramc priority manager 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xiv 14.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.3 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.4.2.1prioman_config1, prioman_config2 (cfg1, cfg2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.4.2.2hpcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.4.2.3lookup table main upper registers (mlutu0?mlutu4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.4.2.4lookup table main lower registers (mlutl0?mlutl4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.4.2.5lookup table alternate upper registers (alutu0?alutu4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.4.2.6lookup table alternate lower registers (alutl0?alutl4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.4.2.7performance monitor config register (pmcfg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.4.2.8event time timer (evtmr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.4.2.9event time preset (evprst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.4.2.10performance monitor address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 14.4.2.11counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-14 14.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.5.1 description of operation ? overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.5.2 description of operation ? block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.5.3 congestion detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 chapter 15 e200z4d core 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2.1 execution unit features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2.1.1instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.2.1.2integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.1.3load/store unit features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 l1 cache features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.3 memory management unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.4 system bus (core complex interface) features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.2.5 nexus 3+ features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 15.3 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.1 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.3.2 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.3.3 interrupts and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.4 microarchitecture summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.5 availability of detailed documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 chapter 16 enhanced direct me mory access (edma) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 memory map/register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.2.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.1.1dma control register (dmacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.2.1.2dma error status (dmaes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.2.1.3dma enable request (dmaerqh, dmaerql). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.2.1.4dma enable error interrupt (dmaeeih, dmaeeil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.2.1.5dma set enable request (dmaserq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.2.1.6dma clear enable request (dmacerq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.2.1.7dma set enable error interrupt (dmaseei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.2.1.8dma clear enable error interrupt (dmaceei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.2.1.9dma clear interrupt request (dmacint). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.2.1.10dma clear error (dmacerr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.2.1.11dma set start bit (dmassrt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.2.1.12dma clear done status (dmacdne) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.2.1.13dma interrupt request (dmainth, dmaintl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xv 16.2.1.14dma error (dmaerrh, dmaerrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.2.1.15dma hardware request status (dmahrsh, dmahrsl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 16.2.1.16dma channel n priority (dchprin), n = 0,..., {15} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 16.2.1.17transfer control descriptor (tcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.3.1 dma microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.3.2 dma basic data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33 16.3.3 dma performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-36 16.4 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 16.4.1 dma initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-39 16.4.2 dma programming errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40 16.4.3 dma arbitration mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41 16.4.3.1fixed group arbitration, fixed channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41 16.4.3.2round-robin group arbitration, fixed channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41 16.4.3.3round-robin group arbitrati on, round-robin channel arbitratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41 16.4.3.4fixed group arbitration, round-robin channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42 16.4.4 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42 16.4.4.1single request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42 16.4.4.2multiple requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-43 16.4.5 tcd status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45 16.4.5.1minor loop complete. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45 16.4.5.2active channel tcd reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46 16.4.5.3preemption status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46 16.4.6 channel linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46 16.4.7 dynamic programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47 16.4.7.1dynamic priority changing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47 16.4.7.2dynamic channel linking and dynamic scatter/gather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47 16.4.8 hardware request release timi ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48 chapter 17 edma channel mux (dmachmux) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3.1.1channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.4.1 dma channels with periodic triggering capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6 17.4.2 dma channels with no triggering capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.4.3 "always enabled" dma sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.5 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.5.2 low power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.5.3 enabling and configuring sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 chapter 18 enhanced modular io subsystem (emios) 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.4 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.4.1 unsupported features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.4.2 device-specific configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.4.3 emios clocking configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.4.4 channel types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.4.5 unified channel block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xvi 18.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.5.2 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.5.2.1emiosi[n] - emios200 channel input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.5.2.2emioso[n] - emios200 channel output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.5.2.3emios_flag_out[n] - emios200 channel flag signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.6 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.6.1.1unified channel memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.6.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.6.2.1emios200 module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.6.2.2emios200 global flag register (gfr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 18.6.2.3emios200 output update disable (oudr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 18.6.2.4emios200 disable channel (ucdis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 18.6.2.5emios200 uc a register (cadr[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 18.6.2.6emios200 uc b register (cbdr[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14 18.6.2.7emios200 uc counter register (ccntr[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 18.6.2.8emios200 uc control register (ccr[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 18.6.2.9emios200 uc status register (csr[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.6.2.10emios200 uc alternate a register (altcadr[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 18.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 18.7.1 unified channel (uc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-24 18.7.1.1uc modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 18.7.1.2input programmable filter (ipf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 18.7.1.3clock prescaler (cp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 18.7.1.4effect of freeze on the unified channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 18.7.2 global clock prescaler submodule (gcp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 18.7.2.1effect of freeze on the gcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.8 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.8.1 considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.8.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.8.2.1time base generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 18.8.2.2coherent accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46 18.8.2.3channel/modes initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-46 chapter 19 error correction status module (ecsm) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.4.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.4.2.1miscellaneous user-defined control register (mudcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.4.2.2ecc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.4.2.3ecc configuration register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.4.2.4ecc status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.4.2.5ecc error generation register (eegr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.4.2.6flash ecc address register (fear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.4.2.7flash ecc master number register (femr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.4.2.8flash ecc attributes (feat) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.4.2.9flash ecc data register (fedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.4.2.10ram ecc address register (rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.4.2.11ram ecc syndrome register (resr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.4.2.12ram ecc master number register (remr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.4.2.13ram ecc attributes (reat) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 19.4.2.14ram ecc data register (redr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.4.3 high priority enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 19.4.4 supervisor mode access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xvii chapter 20 flexcan 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.2 flexcan module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.2 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.2.1can rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.3.2.2can tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.4.1 flexcan memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.4.2 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.4.3 rx fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.4.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.4.4.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.4.4.2control register (ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 20.4.4.3free running timer (timer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.4.4.4rx global mask (rxgmask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.4.4.5rx 14 mask (rx14mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.4.4.6rx 15 mask (rx15mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.4.4.7error counter register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.4.4.8error and status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-23 20.4.4.9interrupt mask register high (imrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-25 20.4.4.10interrupt mask register low (imrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-26 20.4.4.11interrupt flag register high (ifrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-27 20.4.4.12interrupt flag register low (ifrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-28 20.4.4.13rx individual mask registers (rximr0?rximr63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-29 20.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-30 20.5.2 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31 20.5.3 arbitration process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-31 20.5.4 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-32 20.5.5 matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-33 20.5.6 data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-34 20.5.6.1message buffer deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-35 20.5.6.2message buffer lock mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-35 20.5.7 rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-36 20.5.8 can protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37 20.5.8.1remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37 20.5.8.2overload frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-37 20.5.8.3time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-38 20.5.8.4protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-38 20.5.8.5arbitration and matching timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-40 20.5.9 modes of operation: details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-41 20.5.9.1freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-41 20.5.9.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42 20.5.10interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-42 20.5.11bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-43 20.6 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-43 20.6.1 flexcan initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-43 20.6.2 flexcan addressing and ram size configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-44 chapter 21 flash memory 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.2 flash memory block segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xviii 21.1.3 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.1.4.1flash user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.1.4.2low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.1.4.3power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.1.4.4user test mode (utest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.3.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.3.2.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.3.2.2low/mid address space block locking register (lml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 21.3.2.3high address space block locking register (hbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 21.3.2.4secondary low/mid address space block locking register (sll). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 21.3.2.5low/mid address space block select register (lms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 21.3.2.6high address space block select register (hbs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 21.3.2.7address register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.3.2.8platform flash configuration registers (pfcrp0 and pfcrp1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.3.2.9platform flash access protection register (pfapr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-20 21.3.2.10pflash supervisor access control register (pfsacc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.3.2.11pflash data access control register (pfdacc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.3.2.12user test register 0 (ut0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.3.2.13user test register 1 (ut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 21.3.2.14user test register 2 (ut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 21.3.2.15user multiple input signature register [0:4] (um n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 21.3.2.16nonvolatile private censorship password 0 register (nvpwd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 21.3.2.17nonvolatile private censorship password 1 register (nvpwd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 21.3.2.18nonvolatile system censoring information 0 register (n vscc0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 21.3.2.19nonvolatile system censoring information 1 register (n vscc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 21.3.2.20nonvolatile user options register (nvusro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.4.1 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.4.1.1read and write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.4.1.2flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.4.1.3flash erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-37 21.4.2 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-40 21.4.3 power down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41 21.4.4 utest mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41 21.4.4.1array integrity self check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41 21.4.4.2factory margin read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-42 21.4.4.3ecc logic check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 21.4.5 pflash2p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 21.4.5.1line read buffers and prefetch operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 21.4.5.2instruction / data prefetch triggering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-45 21.4.5.3per-master prefetch triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-45 21.4.5.4buffer allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-45 21.4.5.5buffer invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.6.1 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.6.2 flash memory setting recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 chapter 22 graphics accelerator gasket (gxg) 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3.2 registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.3.2.1window configuration (gxgcnfg0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xix 22.3.2.2window destination base address (gxgbase0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.3.2.3window first address (gxgfrst0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.3.2.4window last address (gxglast0-3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.3.2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gfx2d stride setting (gxgstride)22-7 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.1 ips to ahb bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.2 axi to ahb bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.3 1x2 axi bus matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4.4 address filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.5 byte swapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.6 frame buffer color depth converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.7 alpha buffer write suppressor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 22.4.8 serial flash exclusive access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 chapter 23 graphics static ram (gsram) 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.2.2.1pram2p control register (pram2p_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.2.2.2pram2p status register (pram2p_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.2.2.3pram2p fill region begin address register (pram2p_beg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.2.2.4pram2p fill region end address register (pram2p_end) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.2.2.5pram2p fill register (pram2p_fil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.4 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 chapter 24 ieee 1149.1 test access port controller (jtagc) 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.5.2 ieee 1149.1-2001 defined test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.5.2.1bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.5.2.2tap sharing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.6 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.7 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.7.1 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.7.2 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.7.3 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.7.4 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.8.1 jtagc reset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.8.2 ieee 1149.1-2001 (jtag) test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.8.3 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.8.3.1selecting an ieee 1149.1-2001 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.8.4 jtagc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.8.4.1bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.8.4.2access_aux_tap_ x instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.8.4.3extest ? external test instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.8.4.4idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 24.8.4.5sample instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xx 24.8.4.6sample/preload instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 24.8.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10 24.9 e200z0 once controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.9.1 e200z0 once controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.9.2 e200z0 once controller functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.9.2.1enabling the tap controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.9.3 e200z0 once controller register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.9.3.1once command register (ocmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.10 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 chapter 25 inter-integrated circuit bus controller module (i 2 c) 25.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3.2 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3.2.1scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3.2.2sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.4.2 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.4.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.4.3.1i 2 c bus address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.4.3.2i 2 c bus frequency divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.4.3.3i 2 c bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.4.3.4i 2 c bus status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.4.3.5i 2 c bus data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16 25.4.3.6i 2 c bus interrupt configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16 25.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5.2 i-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5.2.1start signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5.2.2slave address transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 25.5.2.3data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 25.5.2.4stop signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.5.2.5repeated start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.5.2.6arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.5.2.7clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.5.2.8handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.5.2.9clock stretching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.5.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.5.3.1general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.5.3.2interrupt description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.6 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.6.1 i 2 c programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.6.1.1initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.6.1.2generation of start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.6.1.3post-transfer software response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.6.1.4generation of stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.6.1.5generation of repeated start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.6.1.6slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.6.1.7arbitration lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24 25.6.2 dma application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxi chapter 26 interrupt controller (intc) 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4.1.1software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4.1.2hardware vector mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.4.1.3debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.4.1.4stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.5.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.5.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.5.2.1intc module configuration register (intc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.5.2.2intc current priority register for processor (intc_cpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.5.2.3intc interrupt acknowledge register (intc_iackr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.5.2.4intc end-of-interrupt register (intc_eoir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.5.2.5intc software set/clear interrupt registers (intc_sscir0_3?intc_sscir4_7). . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.5.2.6intc priority select registers (intc_psr0_3?intc_psr206_238) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-9 26.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11 26.6.1 interrupt request sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-22 26.6.1.1peripheral interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-22 26.6.1.2software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-22 26.6.1.3unique vector for each interrupt request source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 26.6.2 priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 26.6.2.1current priority and preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-23 26.6.2.2last-in first-out (lifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24 26.6.3 handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24 26.6.3.1software vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24 26.6.3.2hardware vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26 26.7 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26 26.7.1 initialization flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26 26.7.2 interrupt exception handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.7.2.1software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.7.2.2hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 26.7.3 isr, rtos, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 26.7.4 order of execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-29 26.7.5 priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30 26.7.5.1elevating priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30 26.7.5.2ensuring coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-30 26.7.6 selecting priorities according to request rates and deadli nes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-31 26.7.7 software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-31 26.7.7.1scheduling a lower priority portion of an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-31 26.7.7.2scheduling an isr on another processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32 26.7.8 lowering priority within an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-32 26.7.9 negating an interrupt request outside of its isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-33 26.7.9.1negating an interrupt request as a side effect of an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-33 26.7.9.2negating multiple interrupt requests in one isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-33 26.7.9.3proper setting of interrupt request priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-33 26.7.10examining lifo contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-33 chapter 27 lin controller (linflexd) 27.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2.1 lin mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.2.2 uart mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.3 the lin protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.1 dominant and recessive logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxii 27.3.2 lin frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.3 lin header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.3.1break field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.3.2sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.4.1data field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.4.2identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.4.3checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.4 linflexd and software intervention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.5 summary of operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6 controller-level operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.6.1 initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.6.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.6.3 sleep (low-power) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.7 lin modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.7.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.7.1.1lin header transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.7.1.2data transmission (transceiver as publisher) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.1.3data reception (transceiver as subscriber) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.1.4error detection and handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.7.2.1data transmission (transceiver as publisher) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7.2.2data reception (transceiver as subscriber) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7.2.3data discard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 27.7.2.4error detection and handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-11 27.7.2.5valid header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.7.2.6valid message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.7.2.7overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.7.3 slave mode with identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.7.3.1filter submodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-12 27.7.3.2identifier filter submode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-13 27.7.4 slave mode with automatic resynchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15 27.7.4.1automatic resynchronization method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-15 27.7.4.2deviation error on the sync field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 27.8 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 27.8.1 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-16 27.8.2 self test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 27.9 uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 27.9.1 data frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 27.9.1.18-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-17 27.9.1.29-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18 27.9.1.316-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18 27.9.1.417-bit data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-18 27.9.2 buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19 27.9.3 uart transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-19 27.9.4 uart receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-20 27.10 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-22 27.10.1lin control register 1 (lincr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-24 27.10.2lin interrupt enable register (linier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-27 27.10.3lin status register (linsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-29 27.10.4lin error status register (linesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-32 27.10.5uart mode control register (uartcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-33 27.10.6uart mode status register (uartsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-36 27.10.7lin timeout control status register (lintcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-38 27.10.8lin output compare register (linocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-39 27.10.9lin timeout control register (lintocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-40 27.10.10lin fractional baud rate register (linfbrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-41 27.10.11lin integer baud rate register (linibrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-41 27.10.12lin checksum field register (lincfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-42 27.10.13lin control register 2 (lincr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-43 27.10.14buffer identifier register (bidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-44 27.10.15buffer data register least significant (bdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-45 27.10.16buffer data register most significant (bdrm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-46
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxiii 27.10.17identifier filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-47 27.10.18identifier filter match index (ifmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-47 27.10.19identifier filter mode register (ifmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-48 27.10.20identifier filter control registers (ifcr0?ifcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-49 27.10.21global control register (gcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-50 27.10.22uart preset timeout register (uartpto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-51 27.10.23uart current timeout register (uartcto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-52 27.10.24dma tx enable register (dmatxe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-53 27.10.25dma rx enable register (dmarxe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-53 27.11 dma interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-54 27.11.1master node, tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-54 27.11.2master node, rx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-58 27.11.3slave node, tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-61 27.11.4slave node, rx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-64 27.11.5uart node, tx mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-67 27.11.6uart node, rx mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-70 27.11.7use cases and limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-73 27.12 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-74 27.12.18-bit timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-74 27.12.1.1lin timeout mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-74 27.12.1.2output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-74 27.12.2interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-74 27.12.3fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-76 27.13 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-76 27.13.1master node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-77 27.13.2slave node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-78 27.13.3extended frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-81 27.13.4timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-81 27.13.5uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-82 chapter 28 memory protection unit (mpu) 28.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.1.4 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.2.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.2.2.1mpu control/error status register (mpu_cesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.2.2.2mpu error address register, slave port n (mpu_earn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.2.2.3mpu error detail register, slave port n (mpu_edrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-7 28.2.2.4mpu region descriptor n (mpu_rgdn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.2.2.5mpu region descriptor alternate access control n (mpu_rgdaacn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-13 28.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15 28.3.1 access evaluation macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-15 28.3.1.1access evaluation ? hit determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16 28.3.1.2access evaluation ? privilege violation determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-16 28.3.2 putting it all together and ahb error terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.4 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18 28.5 opcode pre-fetch cycles and the execute permission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18 28.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-18 chapter 29 mode entry module (mc_me) 29.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxiv 29.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 29.3.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-14 29.3.2.1global status register (me_gs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-15 29.3.2.2mode control register (me_mctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-17 29.3.2.3mode enable register (me_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-18 29.3.2.4interrupt status register (me_is) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-19 29.3.2.5interrupt mask register (me_im). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-20 29.3.2.6invalid mode transition status regi ster (me_imts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-21 29.3.2.7debug mode transition status register (me_dmts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-22 29.3.2.8reset mode configuration register (me_reset_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-25 29.3.2.9test mode configuration register (me_test_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-25 29.3.2.10safe mode configuration register (me_safe_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-26 29.3.2.11drun mode configuration register (me_drun_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-26 29.3.2.12run0?3 mode configuration registers (me_run0?3_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-27 29.3.2.13halt mode configuration register (me_halt_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-27 29.3.2.14stop mode configuration register (me_stop_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-28 29.3.2.15standby mode configuration register (me_standby_mc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-28 29.3.2.16peripheral status register 0 (me_ps0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30 29.3.2.17peripheral status register 1 (me_ps1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-30 29.3.2.18peripheral status register 2 (me_ps2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-31 29.3.2.19peripheral status register 3 (me_ps3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-31 29.3.2.20run peripheral configuration registers (me_run_pc0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-32 29.3.2.21low-power peripheral configuration registers (me_lp_pc0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33 29.3.2.22peripheral control registers (me_pctl0?143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-33 29.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-34 29.4.1 mode transition request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-34 29.4.2 modes details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35 29.4.2.1reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-35 29.4.2.2drun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36 29.4.2.3safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-36 29.4.2.4test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-37 29.4.2.5run0?3 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38 29.4.2.6halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-38 29.4.2.7stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-39 29.4.2.8standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40 29.4.3 mode transition process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40 29.4.3.1target mode request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-40 29.4.3.2target mode configuration loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-41 29.4.3.3peripheral clocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-42 29.4.3.4processor low-power mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-42 29.4.3.5processor and system memory clock disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-42 29.4.3.6clock sources (main voltage regulator independent) switch-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43 29.4.3.7main voltage regulator switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43 29.4.3.8flash module switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-43 29.4.3.9clock sources (main voltage regulator dependent) switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44 29.4.3.10power domain #2 switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44 29.4.3.11pad outputs-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44 29.4.3.12peripheral clocks enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44 29.4.3.13processor and memory clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-44 29.4.3.14processor low-power mode exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45 29.4.3.15system clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-45 29.4.3.16power domain #2 switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46 29.4.3.17pad switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46 29.4.3.18clock sources switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46 29.4.3.19flash switch-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-46 29.4.3.20main voltage regulator switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-47 29.4.3.21current mode update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-47 29.4.4 protection of mode configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-49 29.4.5 mode transition interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-49 29.4.5.1invalid mode configuration interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-49 29.4.5.2invalid mode transition interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-49
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxv 29.4.5.3safe mode transition interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-51 29.4.5.4mode transition complete interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-51 29.4.6 peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-51 29.4.7 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-52 chapter 30 nexus development interface (ndi) 30.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.4.1 nexus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.4.2 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4.2.1disabled-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4.2.2censored mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4.2.3stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.5.1 nexus signal reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.6 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.6.1 nexus debug interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.6.2.1nexus device id register (did) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.6.2.2port configuration register (pcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.6.2.3development control register 1, 2 (dc1, dc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.6.2.4development status register (ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10 30.6.2.5read/write access control/status (rwcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.6.2.6read/write access address (rwa). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13 30.6.2.7read/write access data (rwd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-13 30.6.2.8watchpoint trigger register (wt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14 30.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.7.1 npc_hndshk module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.7.2 enabling nexus clients for tap access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.7.3 configuring the ndi for nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.7.4 programmable mcko frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-17 30.7.5 nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.7.6 evto sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.7.7 debug mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.7.7.1evti generated break request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.7.8 nexus reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.8 initialization / application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.8.1 relationship between tck and system clock frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 chapter 31 openvg graphics accelerator (gfx2d) 31.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1.2.1frame buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.1.2.22d bitmap graphics (separate 2d unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.1.2.3vector graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.1 g12_commandstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.3.2 g12_mmucommandstream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.3.3 g12_revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.3.4 g12_sysstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.3.5 g12_irqstatus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.3.6 g12_irqenable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.3.7 g12_irq_active_cnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.3.8 g12_clocken . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxvi 31.3.9 mmu_read_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.3.10mmu_read_data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.3.11g12_fifofree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.4 command stream registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.4.1 g2d_base0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14 31.4.2 g2d_cfg0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-14 31.4.3 g2d_scissorx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.4.4 g2d_scissory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-15 31.4.5 g2d_foreground, g2d_background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.4.6 g2d_alphablend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.4.7 g2d_rop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-16 31.4.8 g2d_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-17 31.4.9 g2d_input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.4.10g2d_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.4.11g2d_blendercfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.4.12g2d_blend_a0-3, gd2_blend_c0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-18 31.4.13vgv1_vtx0-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-20 31.4.14vgv1_tileofs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-20 31.4.15vgv1_fill . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.4.16vgv1_scissorx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.4.17vgv1_scissory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.4.18vgv1_cfg1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.4.19vgv1_cfg2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-21 31.4.20vgv1_dirtybase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-22 31.4.21vgv1_cbase1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-22 31.4.22vgv1_ubase2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-22 31.4.23vgv2_c1x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-22 31.4.24vgv2_c1y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-22 31.4.25vgv2_c2x, vgv2_c2y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-23 31.4.26vgv2_c3x, vgv2_c3y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-23 31.4.27vgv2_c4x, vgv2_c4y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-23 31.4.28vgv2_c(1-4)xrel, vgv2_c(1-4)yrel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-23 31.4.29vgv2_xfxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-24 31.4.30vgv2_xfyx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-24 31.4.31vgv2_xfxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-24 31.4.32vgv2_xfyy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-24 31.4.33vgv2_xfxa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.4.34vgv2_xfya . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.4.35vgv2_xfstxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.4.36vgv2_xfstyx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.4.37vgv2_xfstxy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-25 31.4.38vgv2_xfstyy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.4.39vgv2_bboxminx, vgv2_bboxminy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.4.40vgv2_bboxmaxx, vgv2_bboxmaxy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.4.41vgv2_scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.4.42vgv2_bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-26 31.4.43vgv2_accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.4.44vgv2_thinradius. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.4.45vgv2_arccos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.4.46vgv2_arcsin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.4.47vgv2_arctan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-27 31.4.48vgv2_radius . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.4.49vgv2_miter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.4.50vgv2_clip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.4.51vgv2_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-28 31.4.52vgv2_action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-29 31.4.53vgv3_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-30 31.4.54vgv3_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-30 31.4.55vgv3_writeaddr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-30 31.4.56vgv3_write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31 31.4.57vgv3_writeifpaused . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31 31.4.58vgv3_nextaddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31 31.4.59vgv3_nextcmd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-31
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxvii 31.4.60vgv3_vgbypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-32 31.4.61vgv3_writes8, vgv3_writes16, vgv3_writes32, vgv3_write f32, vgv3_writeraw . . . . . . . . . . . . . . . . . 31-32 31.4.62vgv3_writedmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-32 31.4.63vgv3_last . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-32 31.4.64fbc_base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-33 31.4.65fbc_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-33 31.4.66fbc_width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-33 31.4.67fbc_height . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-33 31.4.68fbc_stride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-33 31.4.69fbc_start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-34 31.4.70g2d_const0-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-34 31.4.71gradw_const0-b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-34 31.4.72g2d_gradient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-35 31.4.73gradw_texcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-35 31.4.74gradw_texsize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-36 31.4.75gradw_texbase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-36 31.4.76gradw_bordercolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-36 31.4.77gradw_inst0-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-37 31.4.78g2d_xy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-37 31.4.79g2d_widthheight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-37 31.4.80g2d_sxy, g2d_sxy2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.4.81g2d_vgspan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.4.82g2d_idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.4.83g2d_color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-38 31.5 mmu command stream registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-39 31.5.1 mh_mmu_config. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.5.2 mh_mmu_va_range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.5.3 mh_mmu_pt_base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-40 31.5.4 mh_mmu_page_fault. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.5.5 mh_mmu_tran_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.5.6 mh_mmu_invalidate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-41 31.5.7 mh_mmu_mpu_base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.5.8 mh_mmu_mpu_end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.5.9 mh_arbiter_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-42 31.5.10mh_clnt_axi_id_reuse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-43 31.5.11mh_interrupt_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.5.12mh_interrupt_status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.5.13mh_interrupt_clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.5.14mh_axi_error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-44 31.5.15mh_perfcounter0_select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-45 31.5.16mh_perfcounter0_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-45 31.5.17mh_perfcounter0_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-45 31.5.18mh_perfcounter0_hi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.5.19mh_perfcounter1_select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.5.20mh_perfcounter1_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.5.21mh_perfcounter1_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.5.22mh_perfcounter1_hi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.5.23mh_debug_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-46 31.5.24mh_debug_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.5.25mh_axi_halt_control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-47 31.5.26performance counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-48 31.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.1 bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.2 input unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.3 arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.4 burst cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.5 2d+vg unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.6 2d+vg unit level architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-51 31.6.6.1command handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-52 31.6.6.2geometry engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-52 31.6.6.3rasterizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-53 31.6.6.42d unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-53 31.6.6.5gradient and texturing unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-53
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxviii chapter 32 periodic interrupt timer (pit) 32.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.3.2.1pit module control register (pitmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.3.2.2timer load value register (ldval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.3.2.3current timer value register (cval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3.2.4timer control register (tctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-5 32.3.2.5timer flag register (tflg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.4.1.1timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.4.1.2debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8 32.4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8 32.5 initialization and application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 32.5.1 example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 chapter 33 peripheral bridge (pbridge) 33.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2.1 access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2.1.1peripheral write buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2.1.2read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.2.1.3write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.2.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 chapter 34 power control unit (mc_pcu) 34.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 34.3.2.1power domain #0 configuration register (pcu_pconf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-5 34.3.2.2power domain #1 configuration register (pcu_pconf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-6 34.3.2.3power domain #2 configuration register (pcu_pconf2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7 34.3.2.4power domain status register (pcu_pstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-7 34.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.4.2 reset / power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.4.3 mc_pcu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.4.4 mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.4.4.1drun, safe, test, run0?3, halt, and stop mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-8 34.4.4.2standby mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-9 34.4.4.3power saving for memories during standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-10 34.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11 34.6.1 standby mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-11
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxix chapter 35 quad serial peripheral interface (quadspi) 35.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.1.3 quadspi modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.1.3.1normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.1.3.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.1.3.3stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2.1pcsfa - peripheral chip select flash a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2.2pcsfb - peripheral chip select flash b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2.3sckfa ? serial clock flash a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2.4sckfb ? serial clock flash b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2.5iofa[3:0] - data io flash a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2.6iofa[3:0] - data io flash b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.2.3 driving of external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.3 interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7 35.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8 35.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8 35.4.2 serial flash address assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-9 35.4.3 amba bus register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10 35.4.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10 35.4.4.1register write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10 35.4.4.2module configuration register (qspi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-11 35.4.4.3latency configuration register (qspi_lcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-12 35.4.4.4serial flash address register (qspi_sfar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-13 35.4.4.5instruction code register (qspi_icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-14 35.4.4.6sampling register (qspi_smpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-15 35.4.4.7rx buffer status register (qspi_rbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-16 35.4.4.8rx buffer control register (qspi_rbct). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-17 35.4.4.9tx buffer status register (qspi_tbsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-17 35.4.4.10tx buffer data register (qspi_tbdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-18 35.4.4.11amba control register (qspi_acr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-19 35.4.4.12status register (qspi_sfmsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-20 35.4.4.13flag register (qspi_sfmfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-21 35.4.4.14interrupt and dma request select and enable register (qspi_sfmrser) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-23 35.4.4.15rx buffer data registers 0?31 (qspi_rbdr0?qspi_rbdr31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-25 35.4.5 ahb bus register memory map descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-26 35.4.5.1ahb bus access considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-26 35.4.5.2memory mapped serial flash data - i ndividual flash mode on flash a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-26 35.4.5.3memory mapped serial flash data - i ndividual flash mode on flash b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-26 35.4.5.4memory mapped serial flash data - parallel flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-27 35.4.5.5ahb rx data buffer (qspi_ardb0 to qspi_ardb31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-28 35.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-29 35.5.1 serial flash access schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-29 35.5.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-30 35.5.3 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-30 35.5.3.1issuing sfm commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-30 35.5.3.2flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-31 35.5.3.3flash read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-32 35.5.3.4byte ordering of serial flash read data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-34 35.5.3.5normal mode interrupt and dma requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-36 35.5.3.6tx buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-38 35.5.4 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-39 35.5.4.1stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-39 35.5.4.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-40 35.5.4.3leaving power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-41 35.5.4.4slave bus signal gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-41 35.6 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-41
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxx 35.6.1 power up and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-41 35.6.2 available status/flag information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-41 35.6.2.1ip commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-41 35.6.2.2ahb commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-42 35.6.2.3overview of error flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-42 35.6.2.4ip bus and ahb access command collisions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-43 35.6.3 exclusive access to serial flash for ahb commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-43 35.6.3.1rx buffer read via qspi_ardb registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-44 35.6.3.2rx buffer read via qspi_rdbr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-44 35.6.4 command arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-44 35.6.5 flash device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-45 35.6.6 continuous mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-45 35.6.7 dma usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-45 35.6.7.1dma usage in normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-45 35.7 byte ordering - endianess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-47 35.7.1 programming flash data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-47 35.7.2 reading flash data into the rx buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-47 35.7.2.1readout of the rx buffer via qspi_rbdrn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-48 35.7.2.2readout of the rx buffer via ardbn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-48 35.7.3 reading flash data into the ahb buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-48 35.7.3.1readout of the ahb buffer via memory mapped read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-48 35.8 serial flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-49 35.8.1 supported instruction codes in winbond devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-49 35.8.2 instruction codes in spansion devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-52 35.8.3 instruction codes in macronix devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-56 35.8.4 instruction codes in numonyx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-59 35.8.5 serial flash clock frequency limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-62 35.9 internal sampling of serial flash input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-63 chapter 36 real-time clock (rtc/api) 36.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.3 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.4.1 functional mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.4.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.5 memory map and register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.5.1 rtc supervisor control register (rtcsupv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.5.2 rtc control register (rtcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.5.3 rtc status register (rtcs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 36.5.4 rtc counter register (rtccnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7 36.6 rtc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8 36.7 api functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9 chapter 37 reset generation module (mc_rgm) 37.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-11 37.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-11 37.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-12 37.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-13 37.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-14 37.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-14 37.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-16 37.3.1.1functional event status register (rgm_fes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-17 37.3.1.2destructive event status register (rgm_des) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-18 37.3.1.3functional event reset disable register (rgm_ferd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-19 37.3.1.4destructive event reset disable register (rgm_derd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-21 37.3.1.5functional event alternate request register (rgm_fear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-22 37.3.1.6destructive event alternate request register (rgm_dear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-23
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxi 37.3.1.7functional event short sequence register (rgm_fess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-24 37.3.1.8standby reset sequence register (rgm_stdby). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-25 37.3.1.9functional bidirectional reset enable register (rgm_fbre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-26 37.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-27 37.4.1 reset state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-27 37.4.1.1phase0 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-28 37.4.1.2phase1 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-29 37.4.1.3 phase2 ph ase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-29 37.4.1.4phase3 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-29 37.4.1.5idle phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-29 37.4.2 destructive resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-30 37.4.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-30 37.4.4 functional resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 37.4.5 standby entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 37.4.6 alternate event generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-31 37.4.7 boot mode capturing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-32 chapter 38 run-length encoding decoder (rle_dec) 38.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.1.3 rle_dec modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.1.3.1normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.1.3.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.1.3.3stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.3 interrupt and dma request signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.4.2 amba bus register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.4.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.4.3.1module configuration register (rle_dec_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.4.3.2image configuration register (rle_dec_icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5 38.4.3.3compressed image size register (rle_dec_cisr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6 38.4.3.4decompressed image coordinates register (rle_dec_dicr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6 38.4.3.5status register (rle_dec_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7 38.4.3.6interrupt request status register (rle_dec_isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-7 38.4.3.7interrupt request enable register (rle_dec_rier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8 38.4.3.8start pixel coordinate register of image (rle_dec_spcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-9 38.4.3.9end pixel coordinate register of image (rle_dec_epcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-10 38.4.4 crossbar switch memory map descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.4.4.1rx fifo address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.4.4.2tx fifo address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.4.4.3memory mapped rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.4.4.4memory mapped tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-11 38.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12 38.5.1 rle encoding format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12 38.5.2 rle decoding process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-12 38.5.3 image coordinates? example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-13 38.5.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-13 38.5.5 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.5.6 power-saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 38.5.6.1module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-14 chapter 39 sound generator module (sgm) 39.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.3 device-specific configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxii 39.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3 39.5 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.6 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.6.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6 39.6.2.1sgm control register (sgmctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6 39.6.2.2sgm configuration register (sgmcfg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-8 39.6.2.3clock configuration register for resampler (clkrsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-11 39.6.2.4clock configuration register for channel 3 (clkch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-12 39.6.2.5dds configuration register for channel 3 (ddsch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-12 39.6.2.6envelope configuration register of attack phase for channel 3 (ecrach3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-13 39.6.2.7envelope configuration register of release phase for channel 3 (ecrrch3). . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-14 39.6.2.8envelope configuration register of sustain timing for c hannel 3 (ecrsch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-15 39.6.2.9inter-note no-output phase timing for channel 3 (ntch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-16 39.6.2.10target note pulse count for channel 3 (tpcch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-16 39.6.2.11playback timing configuration register for channel 3(ptcch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-17 39.6.2.12dead time configuration register for channel 3(dtcch3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-18 39.6.2.13repeat number configuration register for channel 3(rncch3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-18 39.6.2.14volume control register for wave mode (vcrwav) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-19 39.6.2.15sgm timeout count register (sgmtocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-20 39.6.2.16mixer configuration register (mixcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-20 39.6.2.17clock configuration register for pwm (clkpwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-21 39.6.2.18pwm configuration register (pwmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22 39.6.2.19data fifo register 1(dfifo1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-22 39.6.2.20data fifo register 2(dfifo2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-23 39.6.2.21fifo watermark (fifowm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-24 39.6.2.22fifo read pointer (fiforp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-24 39.6.2.23fifo write pointer (fifowp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-25 39.6.2.24sgm status register (sgmst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-25 39.6.2.25sgm interrupt control register for fifo and dma (sgmicfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-27 39.6.2.26sgm interrupt control register (sgmic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-29 39.6.2.27sgm interrupt status register for fifo and dma (sgmisfd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-31 39.6.2.28sgm interrupt status register (sgmis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-32 39.6.2.29i2s enable register (i2sen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-34 39.6.2.30i2s control register (i2sctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-35 39.6.2.31i2s output data format control register (i2sdfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-36 39.6.2.32i2s clock prescaler register (i2sprs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-38 39.6.2.33i2s interrupt control register (i2sintc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-38 39.6.2.34i2s status register (i2sst). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-39 39.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-40 39.7.1 wave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-40 39.7.1.1state machine of sgm channel in wave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-42 39.7.2 dds mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-43 39.7.2.1dds concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-43 39.7.2.2wavetable initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-44 39.7.2.3generating the tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-44 39.7.2.4updating the configuration buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-46 39.7.2.5state machine of sgm channel in dds mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-47 39.7.3 sgm architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-48 39.7.4 sgm clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-48 39.7.5 channel controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-49 39.7.5.1dds controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-49 39.7.5.2asr envelope controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-50 39.7.5.3sample format converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-50 39.7.5.4volume control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-50 39.7.6 re-sampling block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-51 39.7.7 mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-51 39.7.8 i2s interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-52 39.7.8.1features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-52 39.7.8.2clock choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-53 39.7.8.3i2s block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-53 39.7.8.4supported protocol modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-53 39.7.9 pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-60
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxiii 39.8 interrupts and dma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-61 39.9 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-62 39.9.1 wave mode use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-62 39.9.1.1speech. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-62 39.9.1.2alarm sound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-63 39.9.2 dds mode use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-64 39.9.2.1polyphonic sound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-65 39.9.2.2polyphonic alarm sound. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-68 chapter 40 static ram (sram) 40.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.1.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.1.1.1normal (functional) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.1.1.2standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.3 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.5 sram ecc mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.5.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.5.2 reset effects on sram accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.6 dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.7 interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.8 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5 40.8.1 example code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5 chapter 41 stepper motor controller (smc) 41.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.2.1functional modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.2.2pwm channel configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.1.2.3pwm alignment modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 41.1.2.4low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 41.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.2.1 m0c0m/m0c0p/m0c1m/m0c1p ? pwm output pins for motor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.2.2 m1c0m/m1c0p/m1c1m/m1c1p ? pwm output pins for motor 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.2.3 m2c0m/m2c0p/m2c1m/m2c1p ? pwm output pins for motor 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.2.4 m3c0m/m3c0p/m3c1m/m3c1p ? pwm output pins for motor 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.2.5 m4c0m/m4c0p/m4c1m/m4c1p ? pwm output pins for motor 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.2.6 m5c0m/m5c0p/m5c1m/m5c1p ? pwm output pins for motor 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.3.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.3.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 41.3.2.1motor controller control register 0 (mcctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-8 41.3.2.2motor controller control register 1 (mcctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.3.2.3motor controller period register (mcper) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10 41.3.2.4motor controller channel control register (mccc0..11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10 41.3.2.5motor controller duty cycle register (mcdc0..11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-11 41.3.2.6short-circuit detector time-out register (mcsdto). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-13 41.3.2.7short-circuit detector enable register 0 (mcsde0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-13 41.3.2.8short-circuit detector enable register 1 (mcsde1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-14 41.3.2.9short-circuit detector enable register 2 (mcsde2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-14 41.3.2.10short-circuit detector interrupt enable register 0 (mcsdien0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15 41.3.2.11short-circuit detector interrupt enable register 1 (mcsdien1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-15 41.3.2.12short-circuit detector interrupt enable register 2 (mcsdien2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-16 41.3.2.13short-circuit detector interrupt register 0 (mcsdi0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-16 41.3.2.14short-circuit detector interrupt register 1 (mcsdi1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-17
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxiv 41.3.2.15short-circuit detector interrupt register 2 (mcsdi2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-17 41.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18 41.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18 41.4.1.1pwm output modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-18 41.4.1.2relationship between pwm mode and pwm channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-21 41.4.1.3relationship between sign, duty, dither, recirc, period, and pwm mode functions41-21 41.4.2 pwm duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-31 41.4.3 motor controller counter clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-31 41.4.4 output switching delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-32 41.4.5 operation in smc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-32 41.4.6 short-circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-32 41.5 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-37 41.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-37 chapter 42 stepper stall detect (ssd) 42.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1 42.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-1 42.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 42.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 42.1.3.1disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 42.1.3.2normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-3 42.1.3.3power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-4 42.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5 42.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5 42.3.3.1ssd control and status register (control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-5 42.3.3.2interrupt enable and flag register (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-7 42.3.3.3integration accumulator register (itgacc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8 42.3.3.4down counter register (dcnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-8 42.3.3.5blanking counter load register (blncntld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9 42.3.3.6integration counter load register (itgcntld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-9 42.3.3.7ssd prescale and divider register (prescale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-10 42.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-11 42.4.1 main building blocks of the ssd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-11 42.4.1.1analog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-11 42.4.1.2analog wrapper + port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-13 42.4.1.3register interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-15 42.4.1.4bis control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-16 42.4.2 stepper stall detection measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-19 42.4.2.1overview of the ssd measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-19 42.4.2.2details of the ssd measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-20 42.4.3 additional modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.4.3.1blanking with no drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.4.3.2integration with no drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.5.1 analog block startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.5.2 analog block polarity switching time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-22 42.5.3 ssd startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-23 42.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-23 42.6.1 current flow examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-23 42.6.2 setting of the prescale register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-25 42.6.2.1timing resolution considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-25 42.6.2.2offset cancellation consi derations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-26 42.6.3 watching internal states of the ssd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-26 42.6.4 stepper motor transition considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-27 42.6.4.1ssd phase-in and phase-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-27 42.6.4.2changing of ssd internal states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-27 42.6.5 legacy modes - separate blanking and integr ation phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42-28
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxv chapter 43 system integration unit lite (siul) 43.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 43.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-1 43.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-2 43.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.4.1 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.4.1.1general-purpose i/o pins (gpio[0:184]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.4.1.2external interrupt request input pins (eirq[0:23]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-3 43.4.1.3special function output pins confi guration (pcr[185:281]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4 43.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-4 43.5.1 siu memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-5 43.5.2 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-6 43.5.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-6 43.5.3.1mcu id register #1 (midr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-7 43.5.3.2mcu id register #2 (midr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8 43.5.3.3interrupt status flag register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-8 43.5.3.4interrupt request enable register (irer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-9 43.5.3.5interrupt rising-edge event enable register (ireer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-9 43.5.3.6interrupt falling-edge event enable register (ifeer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-10 43.5.3.7interrupt filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-11 43.5.3.8pad configuration registers (pcr0?pcr184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-11 43.5.3.9pad configuration registers (pcr185?pcr281) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-13 43.5.3.10pad selection for multiplexed inputs registers (psmi0_3?psmi50_53). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-15 43.5.3.11gpio pad data output registers (gpdo0_3 - gpdo184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-19 43.5.3.12gpio pad data input registers (g pdi0_3?gpdi184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-20 43.5.3.13parallel gpio pad data out registers (pgpdo0?pgpdo5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-21 43.5.3.14parallel gpio pad data in register (pgpdi0?pgpdi5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-22 43.5.3.15masked parallel gpio pad data out register (mpgpdo0?mpgpdo11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-23 43.5.3.16interrupt filter maximum counter registers (ifmc0?ifmc23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-24 43.5.3.17interrupt filter clock prescaler register (ifcpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-25 43.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-26 43.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-26 43.6.2 pad control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-26 43.6.3 general purpose input and output pads (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-26 43.6.4 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-27 43.6.4.1external interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-28 43.7 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43-28 chapter 44 system status and conf iguration module (sscm) 44.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-1 44.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2.2.1system status register (status). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-2 44.2.2.2system memory configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-3 44.2.2.3error configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-4 44.2.2.4debug status port register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-5 44.2.2.5password comparison registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-6 44.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-8 44.4 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-8 44.4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44-8
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxvi chapter 45 system timer module (stm) 45.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-1 45.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-2 45.3.2.1stm control register (stm_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-2 45.3.2.2stm count register (stm_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-3 45.3.2.3stm channel control register (stm_ccr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-4 45.3.2.4stm channel interrupt register (stm_cir n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-4 45.3.2.5stm channel compare register (stm_cmp n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-5 45.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45-5 chapter 46 timing controller (tcon) 46.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-1 46.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-1 46.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-2 46.2 external signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-2 46.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-2 46.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-2 46.3.2 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-3 46.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-5 46.3.3.1control register 1 (tcon_ctrl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-6 46.3.3.2bit mapping control (tcon_bmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-8 46.3.3.3tcon_comp0 - tcon_comp3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-8 46.3.3.4tcon_comp0_msk - tcon_comp3_msk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-10 46.3.3.5tcon_pulse0 - tcon_pulse5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-11 46.3.3.6tcon_pulse0_msk - tcon_pulse5_msk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-12 46.3.3.7tcon_smx0 - tcon_smx13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-13 46.3.3.8tcon_omux_low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-15 46.3.3.9tcon_omux_high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-16 46.3.3.10 tcon_lut0 - tcon_lut13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-18 46.3.3.11tcon_data0_dly - tcon_data12_dly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-19 46.3.3.12tcon_ctrl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-21 46.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-22 46.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-22 46.4.1.1rsds mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-22 46.4.1.2ttl mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-22 46.4.1.3bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-23 46.4.2 timing signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-23 46.4.2.1comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-23 46.4.2.2pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-24 46.4.2.3toggle generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-24 46.4.2.4 signal mixer (smx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-26 46.4.2.5output crossbar mux. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-27 46.4.3 data inversion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-27 46.4.4 bit mapping control (bmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-27 46.4.4.1bit mapping in ttl mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-28 46.4.4.2bit mapping in rsds mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-28 46.4.4.3bit mapping examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-30 46.4.4.4clock mapping in rsds mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-31 46.4.4.5clock mapping in ttl mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-32 46.4.5 clock/data skew adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-34 46.5 rsds interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-34 46.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-34
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxvii 46.5.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-35 46.5.3 data path signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-35 46.5.3.1pad_p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-35 46.5.3.2pad_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-36 46.5.4 cell description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-36 46.5.4.1rsds_ref - rsds reference cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-36 46.5.4.2rsds_tx - rsds transmitter cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-36 46.5.5 functionality and modes of operation:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-37 46.5.6 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-38 46.5.7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-38 46.6 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-40 46.6.1 tcon initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46-40 chapter 47 video input unit (viu2) 47.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-1 47.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-1 47.2 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-1 47.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-1 47.2.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-2 47.2.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-5 47.2.3.1scr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-5 47.2.3.2luma_comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-7 47.2.3.3chroma_red . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-8 47.2.3.4chroma_green . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-9 47.2.3.5chroma_blue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-9 47.2.3.6dma_addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-10 47.2.3.7dma_inc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-10 47.2.3.8invsz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-11 47.2.3.9hpalrm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-12 47.2.3.10alpha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-12 47.2.3.11hfactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-13 47.2.3.12vfactor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-13 47.2.3.13vid_size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-14 47.2.3.14lut_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-14 47.2.3.15lut_data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-15 47.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-15 47.3.1 itu656 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-15 47.3.2 input synchronizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-17 47.3.3 itu decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-17 47.3.4 down scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-17 47.3.5 brightness and contrast adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-18 47.3.6 yuv to rgb conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-19 47.3.7 round and dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-19 47.3.7.1round . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-20 47.3.7.2dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-20 47.3.8 output formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-20 47.3.9 dma and de-interlace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-21 47.3.10error case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-22 47.4 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-23 47.4.1 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-23 47.4.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-24 47.4.2.1register configuration timing window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47-24 chapter 48 voltage regulators and power supplies 48.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-1 48.2 power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-1 48.3 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-1 48.3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-3
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxviii 48.3.2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-3 48.3.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-4 48.3.3.1vddr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-4 48.3.3.2vrc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-4 48.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-4 48.4.1 voltage regulator control register (vreg_ctl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-4 48.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-5 48.5.1 high power or main regulator (hpreg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-5 48.5.2 low power regulator (lpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-5 48.5.3 ultra low power regulator (ulpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-5 48.5.4 low voltage detectors (lvd) and power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-5 48.5.5 vreg digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-6 48.6 gpio power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-6 48.7 power domain organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-8 chapter 49 wakeup unit (wkpu) 49.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-1 49.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-2 49.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-3 49.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-3 49.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-3 49.4.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-4 49.4.2.1nmi status flag register (nsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-5 49.4.2.2nmi configuration register (ncr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-5 49.4.2.3wakeup/interrupt status flag register (wisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-7 49.4.2.4interrupt request enable register (irer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-7 49.4.2.5wakeup request enable register (wrer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-8 49.4.2.6wakeup/interrupt rising-edge event enable register (wireer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-8 49.4.2.7wakeup/interrupt falling-edge event enable register (wifeer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-9 49.4.2.8wakeup/interrupt filter enable register (wifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-9 49.4.2.9wakeup/interrupt pullup enable register (wipuer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-10 49.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-10 49.5.1 wkpu behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-10 49.5.2 non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-11 49.5.2.1nmi management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-12 49.5.3 external wakeups and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-13 49.5.3.1external interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-14 49.5.3.2on-chip wakeup management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49-14 chapter 50 device performance optimization 50.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-1 50.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-1 50.3 configuring hardware features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 50.3.1 branch target buffer (btb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 50.3.1.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 50.3.1.2recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-2 50.3.2 frequency-modulated pll0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-3 50.3.2.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-3 50.3.2.2recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-3 50.3.3 flash bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-4 50.3.3.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-4 50.3.3.2recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-4 50.3.4 crossbar switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-4 50.3.4.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-4 50.3.4.2recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-5 50.3.5 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-5 50.3.5.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-5 50.3.5.2recommended configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-5
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xxxix 50.3.6 memory management unit (mmu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-7 50.3.6.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-7 50.3.7 dramc priority manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-8 50.3.7.1description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-8 50.4 application software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-8 50.4.1 compiler optimizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-8 50.4.2 signal processing extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-9 50.4.3 hardware single precision fl oating point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-10 50.4.4 variable length encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-10 50.5 peripherals and general application guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-11 50.6 performance optimization checklist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50-11 appendix a registers under protection appendix b revision history
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor xl
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor xli preliminary?subject to change without notice preface overview the primary objective of th is document is to define the functionali ty of the pxd20 microcontroller for use by software and hardware developers. th e pxd20 is built on power architecture ? technology and integrates technologies that are important for today?s inst rument cluster applications. the information in this document is subject to change without notice, as descri bed in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibility to be sure he or she is using the most recent vers ion of the documentation. to locate any published errata or updates for th is document, visit the freescale web site at www.freescale.com. audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the pxd20 device. it is assumed that the re ader understands operating systems, microprocessor syst em design, basic principles of software and hardware, and basic details of the power architecture. organization this document includes chapters that describe: ? the microcontroller as a whole ? the functionality of the indivi dual modules on the microcontroller when the microcontroller is specified as ?pxd20,? the reader is instructed to apply this information to all of the microcontrollers specified on the front cover of this manual, unl ess individual devi ce-specific details are provided in that chapter. the following summary provides a brief description of the majo r sections of this manual: ? chapter 1, introduction, includes general descrip tions of the modules and fe atures incorporated in the device while focusing on new features. ? chapter 2, memory map, provides a high-level listi ng of the pxd20 memory map. ? chapter 3, signal description , summarizes the external signal functions, their static electrical characteristics, and pad confi guration settings for the pxd20. ? chapter 4, safety, describes a set of features to support using the pxd20 fo r applications that need to fulfill functional safety requirements. ? chapter 5, analog-to-digital converter (adc), describes the adc module implemented on the pxd20.
pxd20 microcontroller reference manual, rev. 1 xlii freescale semiconductor preliminary?subject to change without notice ? chapter 6, boot assist module (bam) , describes the bam, whic h contains the mcu boot program code supporting the differ ent booting modes for this device. ? chapter 7, can sampler, describes detecting a can message while no precise clock is running. ? chapter 8, clock description, describes the various clock sources that are availa ble on the pxd20. ? chapter 9, crossbar switch (xbar), describes the multi-port axbs cr ossbar switch that supports simultaneous connections be tween the master ports and slave ports on the pxd20. ? chapter 10, deserial serial peripheral interface (dspi), describes the serial peripheral interface (spi) block, which provides a s ynchronous serial interface for communication between the pxd20 and external devices. ? chapter 11, display control unit (dcu3), describes the module that displays to a tft lcd panel. ? chapter 12, display control unit lite (dculite), describes the module that displays to a tft lcd panel. ? chapter 13, dram controller (dramc), describes the dram controller on the pxd20. ? chapter 14, dramc priority manager, describes the submodule of the dramc that services prioritized requests from different buses on the pxd20. ? chapter 15, e200z4d core, describes the organization of the e200z4 power processor cores and an overview of the programming models as they are implemented on the device. ? chapter 16, enhanced direct memory access (edma), describes the enhanced dma controller implemented on the pxd20. ? chapter 17, edma channel mux (dmachmux), describes the dma multiplexer block implemented on the pxd20. ? chapter 18, enhanced modular io subsystem (emios), describes the emios module, which provides timed i/o channels for comm unications with off-chip devices. ? chapter 19, error correction status module (ecsm), describes the ecsm block, which provides monitoring and control functions to report memory errors and apply error-correcting code (ecc) implementations. ? chapter 20, flexcan, describes the can module, a communi cation controller implementing the can protocol according to bosch specifica tion version 2.0b and iso standard 11898. ? chapter 21, flash memory, describes the flash memory block and the flash memory controller. ? chapter 22, graphics accel erator gasket (gxg), describes a graphics acc elerator (gfx2d) with a 32-bit ips-to-ahb bridge to the slave port an d a 64-bit axi-to-ahb bridge to the master port. ? chapter 23, graphics static ram (gsram), describes a block of ram with an array controller and dual ahb input ports. ? chapter 24, ieee 1149.1 test access port controller (jtagc), describes configuration and operation of the joint test action group (jtag) controller implementati on. it describes those items required by the ieee ? 1149.1 standard and provides additi onal information specific to the device. for internal details and sample applications, see the ieee 1149.1 document. ? chapter 25, inter-integrated circ uit bus controller module (i2c), describes the i 2 c module, including i 2 c protocol, clock synchronization, and i 2 c programming model registers. ? chapter 26, interrupt controller (intc), summarizes the software a nd hardware interrupts for the pxd20 device.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor xliii preliminary?subject to change without notice ? chapter 27, lin controller (linflexd), describes the linflex (l ocal interconnect network flexible) controller, which provides uart capabiliti es as well as an interface to a lin network. ? chapter 28, memory protection unit (mpu), describes the block that provides hardware access control for all memory references generated in the pxd20. ? chapter 29, mode entry module (mc_me), describes the module that controls the pxd20 mode and mode transition sequences in all functional states. ? chapter 30, nexus development interface (ndi), describes the nexus development interface (ndi) block, which provides real-time devel opment support capabilities for the pxd20 in compliance with the ieee-isto 5001-2003 standard. ? chapter 31, openvg graphi cs accelerator (gfx2d), describes a graphics accelerator module. ? chapter 32, periodic interrupt timer (pit), describes an array of timers that can be used to initiate interrupts and trigger dma channels. ? chapter 33, peripheral bridge (pbridge), describes the interface between the system bus and lower bandwidth peripherals via the aips bridge. ? chapter 34, power control unit (mc_pcu), describes the controls for the bridge that maps the pmc peripheral to the mc_pcu address space. ? chapter 35, quad serial peripheral interface (quadspi), describes a module that provides a synchronous serial bus for communication with an external peripheral device. ? chapter 36, real-time clock (rtc/api), describes a free running count er used for time keeping applications that may be configured to gene rate an interrupt at a predefined interval. ? chapter 37, reset generation module (mc_rgm), describes the module that centralizes the different reset sources and manages the reset sequence of the device. ? chapter 38, run-length encoding decoder (rle_dec), describes the module that is used to decode data that has been compressed using a run length encoding (rle) scheme. ? chapter 39, sound generator module (sgm), describes the module is a 4-channel sound generator supporting autonomous audio not e generation, mono linear pcm data playback, mixing, and amplitude control. ? chapter 40, static ram (sram), describes the on-chip static ram (sram) implementation, and covers general operations, conf iguration, and initialization. ? chapter 41, stepper motor controller (smc), describes the smc, a pwm motor controller suitable for driving small stepper and air core motors used in instru mentation applications. ? chapter 42, stepper stall detect (ssd), describes a block that conn ects to a stepper motor (sm) with two coils and monitors the movement of the sm. ? chapter 43, system integration unit lite (siul), describes the siu modul e, which controls mcu reset configuration, pad configur ation, external interrupt, genera l-purpose i/o (gpio), internal peripheral multiplexing, and th e system reset operation. ? chapter 44, system status and configuration module (sscm), describes the module that provides information about the current state and configur ation of the system, which may be useful for configuring application softwa re and for debugging the system. ? chapter 45, system timer module (stm), describes the timer control module.
pxd20 microcontroller reference manual, rev. 1 xliv freescale semiconductor preliminary?subject to change without notice ? chapter 46, timing controller (tcon), describes an alternative interface for the dcu3 that provides rgb data and timi ng signals for tft panels. ? chapter 47, video input unit (viu2), describes a video input module. ? chapter 48, voltage regulators and power supplies, describes the three on- chip voltage regulators for power management and distribution, allowing low-power operation and optimization of power consumption. ? chapter 49, wakeup unit (wkpu), describes the module that supports an external source that can cause non-maskable interrupt requests or wakeup events. ? chapter 50, device perf ormance optimization, describes methods to e nhance performance of the pxd20. ? appendix a, registers under protection, lists the registers under protection on the pxd20. ? appendix b, revision history, provides the revision history of this document.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor xlv preliminary?subject to change without notice document conventions this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e 0, it is said to be cleared; when it takes a value of 1, it is said to be set. reserved when a bit or address is reserved, it should not be writ ten. if read, its value is not guaranteed. reading or wr iting to reserved bits or addresses may cause unexpected results. mnemonics in text, instruction mn emonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x prefix to denote hexadecimal number 0b prefix to denote binary number reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, rambar [ba] identifies the base address field in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit halfword a 16-bit data unit 1 word a 32-bit data unit doubleword a 64-bit data unit x in some contexts, such as signal encodi ngs, x (without italics) indicates a ?don?t care? condition. x with italics, used to express an undefi ned alphanumeric value (e.g., a variable in an equation); or a variable alphabetic character in a bit, register, or module name (e.g., dspi_ x could refer to dspi_a or dspi_b). n used to express an undefined numerical valu e; or a variable numeric character in a bit, register, or module name (e.g., eif n could refer to eif1 or eif0). ~ not logical operator & and logical operator | or logical operator || field concatenation operator overbar an overbar indicates that a signal is active-low. register figure conventions 1. the only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. to simplify the discussion these un its are referred to as words regardless of length.
pxd20 microcontroller reference manual, rev. 1 xlvi freescale semiconductor preliminary?subject to change without notice this document uses the following conventions for the register rese t values in register figures: ? bit value is undefined at reset. u bit value is unchanged by reset. pr evious value preserved during reset. [ signal_name ] reset value is determined by th e polarity of the indicated signal. the following descriptions are used in register bit field description tables: acronyms and abbreviated terms the following table lists some acronyms a nd abbreviations used in this document. r 0 indicates a reserved bit field in a memory-mapped register. these bits are always read as 0. w r 1 indicates a reserved bit field in a memory-mapped register. these bits are always read as 1. w r fieldname indicates a read/write bit in a memory-mapped register. w r fieldname indicates a read-only bit field in a memory-mapped register. w r indicates a write-only bit field in a memory-mapped register. w fieldname r fieldname write 1 to clear: indicates that writing a 1 to this bit field clears it. ww1c r 0 indicates a self-clearing bit. w fieldname term meaning gpio general-purpose i/o ieee institute for electric al and electronics engineers jedec joint electron device engineering council jtag joint test action group mux multiplex rx receive rtl register transfer language
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor xlvii preliminary?subject to change without notice references in addition to this reference manual, the followi ng documents provide additi onal information on the operation of the pxd20: ? ieee-isto 5001-2003 standard for a global embedded processor interface (nexus) ? ieee 1149.1-2001 standard - ieee standard test access port and boundary-scan architecture ? power architecture book e v1.0 (http://www.freescale.com/files/ 32bit/doc/user_guide/book_eum.pdf) tx transmit uart universal asynchronous/synch ronous receiver transmitter term meaning
pxd20 microcontroller reference manual, rev. 1 xlviii freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-1 preliminary?subject to change without notice chapter 1 introduction 1.1 the pxd20 microcontroller the pxd20 represents a new generation of 32-bit microcontrollers targeting single-chip automotive instrument cluster app lications. pxd20 devices are part of the family of power architecture ? -based devices. this family has been designed with an emphasis on providing cost-effective and high quality graphics capabilities in order to satisfy the increasi ng market demand for color thin film transistor (tft) displays within the vehicle cockpit. traditional cluster functions, such as gauge drive, real time counter, and sound generation are also integrated on each device. the pxd20: ? includes 2 mb internal flash memory, 1 mb inte rnal graphics sram and 64 kb system sram ? offers high processing performanc e operating at speeds up to 125 mhz ? is optimized for low power consumption the pxd20 is designed to reduce development and production costs of tft-based instrument cluster displays by providing a single-chip so lution with the processing and stor age capacity to host and execute real-time application software a nd drive tft displays directly. the pxd20 features a 2d openvg and raster graphics acce lerator, video input unit (viu2) and two on-chip display control units (dcu3 and dculite) designed to drive two color tft displays simultaneously. the pxd20 includes a enhanced quadspi serial flash controller and an optional dram controller allowing graphics ram expansion externally. the pxd20 is compatible with the existing development infrastructure of current power architecture devices and are supported with softwa re drivers, operating systems and c onfiguration code to assist with application development. 1.2 pxd20 device summary table 1-1 summarizes the pxd20 device. table 1-1. pxd20 family feature set feature pxd20 package 176 lqfp 208 lqfp 416 mapbga cpu e200z4d 4 kb instruction-cache 16-entry memory management unit (mmu) floating point unit (fpu) signal processing extension (spe) execution speed static?125 mhz flash memory (ecc) 2 mb ram (ecc) 64 kb
pxd20 microcontroller reference manual, rev. 1 1-2 freescale semiconductor preliminary?subject to change without notice on-chip graphics ram (no ecc) 1 mb mpu 16 entry edma 16 channels dram controller no yes openvg graphics accelerator (gfx2d) yes (openvg 1.1) display control unit (dcu3) yes display control unit lite (dculite) no yes timing controller (tcon) and rsds interface no yes video input unit (viu2) yes quadspi serial flash interface yes stepper motor controller (smc) 4 motors 6 motors stepper stall detect (ssd) yes sound generator module (sgm) yes 32 khz external crystal oscillator yes real time counter and autonomous periodic interrupt (rtc/api) ye s periodic interrupt timer (pit) 8 ch, 32-bit software watchdog timer (swt) yes system timer module (stm) 4 ch, 32-bit timed i/o 20 ch, 16-bit: ic / oc / opwm 8 ch, 16-bit: ic / oc 4 ch, 16-bit: ic / oc / opwm / qdec analog-to-digital converter (adc) 16 channels, 10-bit 20 channels, 10-bit can (64 mailboxes) 3 can can sampler yes serial communication interface 3 lin 4 lin spi 2 spi 3 spi i 2 c 4 gpio 128 150 177 debug nexus class 3 (4 ? mdo) nexus class 3 (12 ? mdo) table 1-1. pxd20 family feature set (continued) feature pxd20 package 176 lqfp 208 lqfp 416 mapbga
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-3 preliminary?subject to change without notice 1.3 device block diagram figure 1-1 shows a top-level block diagram of the pxd20. figure 1-1. pxd20 block diagram rsds tcon smd 6x ssd crossbar switch (xbar) pxd20 block diagram vreg oscillator interrupt system fmpll x 2 debug jtag controller e200z4d core mmu z160 rsds rtc/32 khz 2d gfx tcon oscillator viu2 dcu lite dcu nexus class 3+ (4 kb i-cache) 16-ch dma crossbar masters memory protection unit (mpu) pit swt stm 2 mb flash ecc 64 kb sram 1 mb graphics sram rle decode quad spi v02 dram interface communications i/o system crossbar slaves boot assist module (bam) emios a 16-ch emios b 16-ch 3x can 4x uart/lin 3x spi 4x i 2 c sgm 20-ch adc 10-bit pbridge adc ? analog-to-digital converter can ? controller area network controller dcu ? display control unit dma ? direct memory access controller dram ? dynamic random-access memory ecc ? error correction code emios ? timed input/output fmpll ? frequency-modulated phase-locked loop gfx ? openvg graphics accelerator i 2 c ? inter-integrated circuit controller jtag ? joint test action group interface mmu ? memory management unit pbridge ? peripheral i/o bridge pit ? periodic interrupt timer rle ? run length encoding rtc ? real time clock rsds ? reduced-swing differ ential sgnal interface sgm ? sound generator module smd ssd ? stepper motor driver/stepper stall detect spi ? serial peripheral interface controller sram ? sraric random-access memory stm ? system timer module swt ? software watchdog timer tcon ? timing controller uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network viu2 ? video input unit vle ? variable-length execution set vreg ? voltage regulator
pxd20 microcontroller reference manual, rev. 1 1-4 freescale semiconductor preliminary?subject to change without notice 1.4 feature summary ? dual-issue, 32-bit power architecture book e compliant cpu core complex (e200z4d) ? memory management unit (mmu) ? 4 kb, 2/4-way instruction cache ? 2 mb on-chip ecc flash memory with: ? flash memory controller ? prefetch buffers ? 64 kb on-chip ecc sram ? 1 mb on-chip non-ecc graphics sram wi th two-port graphics sram controller ? memory protection unit (mpu) wi th up to 16 region descriptors a nd 32-byte region granularity to provide basic memory access permission and ensure separation between different codes and data ? interrupt controller (intc) wi th 181 peripheral interrupt source s and eight software interrupts ? two frequency-modulated ph ase-locked loops (fmplls) ? primary fmpll (fmpll0) provides a system clock up to 125 mhz ? auxiliary fmpll (fmpll1) is available for use as an alternate, modul ated or non-modulated clock source to emios modules, quadspi and as alternate clock to the dcu and dcu-lite for pixel clock generation ? crossbar switch architecture enables concurrent access of peripherals, flash memory or ram from multiple bus masters ? 16-channel enhanced direct memory access cont roller (edma) with multiple transfer request sources using a dma channel multiplexer ? boot assist module (bam) with 8 kb dedicate d rom for embedded boot code supports boot options including download of boot c ode via a serial link (can or sci) ? two display control units (dcu3 and dculite) fo r direct drive of up to two tft lcd displays up to xga resolution ? timing controller (tcon) and rs ds interface for the dcu3 module ? 2d openvg 1.1 and raster gr aphics accelerator (gfx2d) ? video input unit (viu2) supporting 8/10-bit it u656 video input, yuv to rgb conversion, video down-scaling, de-interlacing, contrast ad justment and brightness adjustment. ? dram controller supporting ddr 1, ddr2, lpddr1 and sdr drams ? stepper motor controller (smc) ? high-current drivers for as many as six ste pper motors driven in full dual h-bridge configuration ? stepper motor return-to-zero and stall detection module ? stepper motor short circuit detection ? sound generator module (sgm) ? 4-channel mixer ? supports pcm wave playback and synthesized tones ? optional pwm or i 2 s outputs
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-5 preliminary?subject to change without notice ? two 16-channel enhanced modular i nput output system (emios) modules ? support a range of 16-bit input capture, ou tput compare, pulse width modulation and quadrature decode functions ? 10-bit analog-to-digital converter (adc ) with a maximum conversion time of 1 ? s ? up to 20 internal channels ? up to 8 external channels ? three deserial serial peripheral interfac e (dspi) modules for full-duplex, synchronous, communications with external devices ? quadspi serial flash memory controller ? supports single, dual and quad io serial flash memory ? interfaces to external, memory -mapped serial flash memories ? supports simultaneous addressing of 2 external serial flashes to achieve up 80 mb/s read bandwidth ? rle decoder supporting memory to memory dec oding of rle data in conjunction with edma ? four local interconnect networ k (linflex) controller modules ? capable of autonomous mess age handling (master), autonom ous header handling (slave mode), and uart support ? compliant with lin protocol rev 2.1 ? three controller-area network (flexcan) modules ? compliant with the can protocol version 2.0 c ? 64 configurable buffers ? programmable bit rate of up to 1 mb/s ? four inter-integrated circuit (i 2 c) internal bus controllers wi th master/slave bus interface ? low-power loop controlled pier ce crystal oscillator supporting 4?16mhz external crystal or resonator ? real time counter (rtc) with clock source from internal 128 khz or 16 mhz oscillator supporting autonomous wake-up with 1 ms resolution with maximum timeout of 2 seconds ? support for real time c ounter (rtc) with clock source from external 32 khz crystal oscillator, supporting wake-up with 1 s resolu tion and maximum timeout of one hour ? rtc optionally clocked by fast 4?16 mhz external oscillator ? system timers: ? four-channel 32-bit system timer module (stm) ? eight-channel 32-bit periodic interrupt ti mer (pit) module (including adc trigger) ? software watchdog timer (swt) ? system integration unit lite (s iul) module to manage external interrupts, gpio and pad control ? system status and configuration module (sscm) ? provides information for identification of the device, last boot mode, or debug status ? provides an entry point for the censorship password mechanism
pxd20 microcontroller reference manual, rev. 1 1-6 freescale semiconductor preliminary?subject to change without notice ? clock generation module (mc_cgm) to generate system clock sources and provide a unified register interface, enabling access to all clock sources ? clock monitor unit (cmu) ? monitors the integrity of the fast (4?16 mhz) external crystal oscillator and the primary fmpll (fmpll0) ? acts as a frequency meter, measuring the freque ncy of one clock source and comparing it to a reference clock ? mode entry module (mc_me) ? controls the device power mode, i.e., run, halt, stop, or standby ? controls mode transition sequences ? manages the power control, voltage regulator, clock gene ration and clock management modules ? power control unit (mc_pcu) to implement standby mode entry/ex it and control connections to power domains ? reset generation module (mc_rgm) to manage rese t assertion and release to the device at initial power-up ? nexus development interface (n di) per ieee-isto 5001-2008 class 3 standard with additional class 4 features: ? watchpoint triggering ? processor overrun control ? device/board boundary-sca n testing supported per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator controller for re gulating the 3.3?5 v supply voltage down to 1.2 v for core logic (requires exte rnal ballast transistor) ? package: 1 ? 176 lqfp, 0.5 mm pitch, 24 mm ? 24 mm outline ? 208 lqfp, 0.5 mm pitch, 28 mm ? 28 mm outline ? 416 tepbga, 1mm ball pitch, 27 mm ? 27 mm outline 1.5 feature details 1.5.1 low-power operation the pxd20 is designed for optim ized low-power operation and dynami c power management of the cpu and peripherals. power management features include software-controlled clock gating of peripherals and multiple power domains to mini mize leakage in low-power modes. there are three low-power modes: 1. see the device comparison table for package offerings for each device in the family.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-7 preliminary?subject to change without notice ?standby ?stop ? halt and five dynamic power modes ? r un[0..3] and drun. all low-power m odes use clock gating to halt the clock for all or part of the device. standby mode turns off the power to the majority of the chip to offer the lowest power consumption mode. the device can be awakened from standby mode via from any of up to 23 i/o pins, a reset or from a periodic wake-up using a lo w power oscillator. if re quired, it is possible to en able the internal 16 mhz oscillator, the external 4?16 mhz oscilla tor and the external 32 khz oscillator. in standby mode the contents of the cpu, on-chip peripheral registers and potentially some of the volatile memory are lost. the two possibl e configurations in standby mode are: ? the device retains 64 kb of the on-chip sram, but the content of the graphics sram is lost. ? the device retains 8 kb of the on-chip sram, but the content of the graphics sram is lost. stop mode maintains power to the entire device al lowing the retention of al l on-chip registers and memory, and providing a faster rec overy low power mode than the lo west-power standby mode. there is no need to reconfigure the device before executi ng code. the clocks to the cpu and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense of a slow er start-up time. stop is entered from run mode onl y. wake-up from stop mode is tr iggered by an external event or by the internal periodic wake-up, if enabled. run modes are the main operating m odes where the entire device can be powered and clocked and from which most processing activity is done. four dynamic run modes are s upported?run0 - run3. the ability to configure and se lect different run modes en ables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. the necessary peripherals, clock sources , clock speed and system clock prescalers can be independently configured for each of the f our run modes of the device. halt mode is a reduced activity, low power mode intended for modera te periods of lower processing activity. in this mode the cpu system clocks are st opped but user-selected periph eral tasks can continue to run. it can be configured to provide more effici ent power management featur es (switch-off pll, flash memory, main regulator, etc.) at the cost of longer wake up latency. the system returns to run mode as soon as an event or interrupt is pending. table 1-2 summarizes the operating modes of the pxd20.
pxd20 microcontroller reference manual, rev. 1 1-8 freescale semiconductor preliminary?subject to change without notice additional notes on low power operation: ? fast wake-up using the on-chip 16 mhz internal rc oscillator allows rapid execution from ram on exit from low power modes table 1-2. operating mode summary 1 1 table key: on?powered and clocked op?optionally configurable to be enabled or disabled (clock gated) cg?clock gated, powered but clock stopped off-?powered off and clock gated fp?vreg full performance mode lp?vreg low power mode, reduced output capab ility of vreg but lower power consumption var?variable duration, based on the required reconfiguration and execution clock speed bam?boot assist module software and hardware used for device start-up and configuration operating mode soc features clock sources periodic wake-up wake-up input vreg mode wake-up time 2 2 a high level summary of some key durations that need to be considered when recovering from low power modes. this does not account for all durations at wake up. other delays will be necessary to consider including, but not limited to the external supply start-up time. irc wake-up time must not be added to the overall wake-up time as it starts in parallel with the vreg. all other wake-up times must be added to determine the total start-up time. cpu gfx accelerator dram controller peripherals flash ram graphics ram primary pll auxiliary pll 16 mhz irc 4?16 mhz osc 128 khz irc 32 khz x osc vreg start-up irc wake-up flash recovery osc stabilization pll lock s/w reconfig mode switch over run on op op op 3 3 either 64 kb or 8 kb available. on op op on op on op ? ? fp ? ? ? ? ? ? ? halt cg op op op 3 on op op on op on op op op fp ? ? ? ? ? ? tbd stop cg cg cg op 3 on cg cg op op on op op op lp 350 s 4 s 20 s 1 m s 200 s ?24 s standb y off off off 64 kb 4 4 64 kb of the ram contents is retained, but not accessible in standby mode. off off off op op op op op op lp 350 s 8 s 100 s 1m s 200 s va r 28 s off off off 8 kb 5 5 8 kb of the ram contents is retained , but not accessible in standby mode. off off off op op op op op op lp 200 s 8 s 100 s 1m s 200 s va r 28 s por 500 s 8 s 100 s 1m s 200 s bam 6 6 dependent on boot option after reset.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-9 preliminary?subject to change without notice ? the 16 mhz internal rc oscillat or supports low speed code execut ion and clocking of peripherals when it is selected as the system clock and can also be used as the pll input clock source to provide fast start-up without th e external oscillator delay ? the device includes an internal voltage re gulator that includes the following features: ? regulates input to genera te all internal supplies ? manages power gating ? external ballast transistor for high power regulator ? low-power and ultra-low-power regulators support operation when in stop and standby modes, respectively, to mi nimize power consumption ? startup on-chip regulators in <350 s for rapid exit of stop and standby modes ? low voltage detection on main s upply and 1.2 v regulated supplies. 1.5.2 e200z4d core the e200z4d power architecture core provides the following features: ? dual issue, 32-bit power architecture book e compliant cpu ? implements the vle apu fo r reduced code footprint ? in-order execution and retirement ? precise exception handling ? branch processing unit ? dedicated branch address calculation adder ? branch target prefetch ing using 8-entry btb ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory via indepe ndent instruction and data bius. ? load/store unit ? 2 cycle load latency ? fully pipelined ? big and little endian support ? misaligned access support ? 64-bit general purpose register file ? dual ahb 2.v6 64-bit system buses ? memory management unit (mmu) with 16-entry fully-associative tlb and multiple page size support ? 4 kb, 2/4-way set associative instruction cache ? signal processing extension (spe1.1) apu suppor ting simd fixed-point operations using the 64-bit general purpose register file. ? embedded floating-point (efp2) apu supporting scalar and vector si md single-precision floating-point operations, using the 64- bit general purpose register file. ? nexus class 3 real-time development unit
pxd20 microcontroller reference manual, rev. 1 1-10 freescale semiconductor preliminary?subject to change without notice ? dynamic power management of execution units, cache and mmu 1.5.3 crossbar switch (xbar) the xbar multi-port crossbar switc h supports simultaneous connections between seven master ports and eight slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows concur rent transactions to occu r from any master port to any slave port but one of those transfers must be an instruction fetch from inte rnal flash. if a slave port is simultaneously requested by more than one master port, arbitr ation logic selects the higher priority master and gran ts it ownership of the slave port. all other masters requesting that slave port are stalle d until the higher priority master completes its transactions. requesti ng masters having equal priority are granted access to a slave port in round-robin fashion, based upon the id of th e last master to be granted access. the crossbar provides the following features: ? seven master ports: ? e200z4d core instruction port ? e200z4d core complex load/store data port ? edma controller ?dcu ?dcu-lite ?viu ? 2d graphics accelerator (gfx2d) ? seven slave ports: ? platform flash cont roller (2 ports) ? platform sram controller ? graphics sram controller (2 ports) ? quadspi serial flash controller and rle decoder ? peripheral bridge ? 32-bit internal address bus , 64-bit internal data bus ? programmable arbitration priority ? requesting masters can be treate d with equal priority and will be granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access or a priority order can be assigned by softwa re at application run time ? temporary dynamic priority elevation of masters 1.5.4 enhanced direct memory access (edma) the edma module is a controller capable of performing complex da ta movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations , and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-11 preliminary?subject to change without notice channels. this implementation is utilized to minimize the overall bl ock size. the edma module provides the following features: ? 16 channels support independent 8-, 16- or 32-bit single value or block transfers ? supports variable sized que ues and circular queues ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by a peripheral, cpu, periodic timer in terrupt or edma channel request ? each dma channel can optionally send an interrupt request to th e cpu on completion of a single value or block transfer ? dma transfers possible between system me mories, quadspi, rle decoder, spis, i 2 c, adc, emios and general purpose i/os (gpios) ? programmable dma channel mux allows assignm ent of any dma source to any available dma channel with up to a total of 64 potential request sources. 1.5.5 interrupt controller (intc) the intc (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically schedul ed hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executi ng the interrupt service routine (i sr) has been minimized. the intc provides a unique vector for each inte rrupt request source for quick dete rmination of which isr needs to be executed. it also provides an ample number of prior ities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropria te priorities for each s ource of interrupt request, the priority of each interrupt re quest is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the re source can not preempt each other. multiple processors can assert interru pt requests to each other through soft ware settable interrupt requests. these same software settable interr upt requests also can be used to break the work involved in servicing an interrupt request into a high pr iority portion and a low priority portion. the high priority portion is initiated by a peripheral interrupt request, but then the isr asserts a software settable interrupt request to finish the servicing in a lower priority isr. therefore these software settable inte rrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. the intc provides the following features: ? unique 9-bit vector for each of the po ssible 128 separate interrupt sources ? eight software trigge rable interrupt sources ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority. ? modifying the priority can be used to implem ent the priority ceiling protocol for accessing shared resources. ? external non maskable interrupt directly accessi ng the main cpu critical interrupt mechanism
pxd20 microcontroller reference manual, rev. 1 1-12 freescale semiconductor preliminary?subject to change without notice ? 32 external interrupts 1.5.6 quadspi serial flash memory controller the quadspi module enables use of external seri al flash memories supporting single, dual and quad modes of operation. it features the following: ? maximum serial clock frequency 80 mhz ? memory mapped read access for ahb crossbar switch masters ? automatic serial flash read co mmand generation by cpu, edma, dcu, or dcu- lite read access on ahb bus ? supports single, dual and quad serial flash read commands ? simultaneous mode: ? supports concurrent read of two external serial flashes ? the quad data streams from the two flashes ca n be recombined in the quadspi to achieve up to 80 mb/s read bandwidth with 80 mhz serial flash ?16 ? 64-bit buffer with speculative fe tch and buffer flush mechanisms to maximize read bandwidth of serial flash ? dma support ? all serial flash program, erase, read and configuration commands available via ip bus interface. 1.5.7 system integration unit lite (siul) the siul controls mcu re set configuration, pad configuration, ex ternal interrupt, general purpose i/o (gpio), internal peripheral multiple xing, and the system reset operation. the gpio features the following: ? up to four levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control ? all gpio pins can be independently conf igured to support pul l-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alte rnatively configured as both gene ral purpose input or output pins except adc channels which support alternative configurat ion as general purpose inputs ? direct readback of the pin value supported on all digita l output pins through the siu ? configurable digital input filter that can be appl ied to up to 24 general pur pose input pins for noise elimination on external interrupts ? register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset. 1.5.8 on-chip flash memory with ecc the pxd20 microcontroller has the fo llowing flash memory features:
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-13 preliminary?subject to change without notice ? 2 mb of flash memory ? typical flash memory access time: 0 wait-state for buffer hits, 3 wait-states for page buffer miss at 125 mhz ? two 4 128-bit page buffers with programmable prefetch control ? one set of page buffers can be allocated for c ode-only, fixed partitions of code and data, all available for any access ? one set of page buffers allocat ed to display controller units, graphics accelerator and the edma ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? small block flash arrangement to support feat ures such as boot block, eeprom emulation, operating system block. ?8 ? 16 kb ?2 ? 64 kb ?2 ? 128 kb ?6 ? 256 kb ? hardware managed flash writes, erase and verify sequence ? censorship protection scheme to prevent flash content visibility 1.5.9 static random-access memory (sram) the pxd20 microcontroller has 64 kb general-purpose on-chip sram with the following features: ? typical sram access tim e: 1 wait-state for r eads and 32-bit writes ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), word (32-bit) and double-word (64-bi t) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses ? separate internal power domains applied to 56 kb and 8 kb sram blocks during standby modes to retain contents during low power mode. 1.5.10 on-chip graphics sram the pxd20 microcontroller has 1 mb on-chip gra phics sram with the following features: ? two crossbar slave ports: ? one dedicated to the 2d gra phics accelerator (gfx2d) access ? one dedicated to all other crossbar masters ? usable as general purpose sram ? supports byte (8-bit), half word (16-bit), word (32-bit) and double-word (64-bi t) writes for optimal use of memory ? ram controller with hardware ram fill f unction supporting all-zero es or all-ones sram initialization
pxd20 microcontroller reference manual, rev. 1 1-14 freescale semiconductor preliminary?subject to change without notice ? independent data buffers (one per ahb port) for maximum system performance ? optimized for burst transfers (read + write) ? programmable read prefetch capabilities 1.5.11 memory protection unit (mpu) the mpu features the following: ? sixteen region descriptors for per master protection ? start and end address defi ned with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for 4 concurrent read ports ? read and write attri butes for all masters ? execute and supervisor/user mode attributes for processor masters 1.5.12 2d graphics accelerator (gfx2d) ? native vector gr aphics rendering ? compatible with openvg1.1 ? complete hardware openvg 1.1 rendering pipeline ? both geometry and pixel processing ? adaptive processing of b ezier curves and strokes ? 16-sample edge anti-aliasing ? high image quality, font scalability, etc. ?4 ? rotated grid supersampl ing (rgss) aa for flash ? 3d perspective texturing, reflections, and shadowing ? shading (linear or radial gradient) ? separate 2d engine for bitb lt, fill and rop operations ? significant performance improvement when compared to so ftware or 3d gpu-based openvg implementations 1.5.13 display control unit (dcu3) the dcu3 is a display controller designed to drive tft lcd displays up to wv ga resolution using direct blit graphics and video. the dcu3 generates all the necessary signals requir ed to drive the tft lcd displays: up to 24-bit rgb data bus, pixel clock, data enable, horizontal-sync and vertical-sync. the flexible architecture of the dcu3 enables th e display of openvg-rendere d frame buffer content and direct blit rendered graphics simultaneously.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-15 preliminary?subject to change without notice an optional timing controller (tc on) and rsds interface is availabl e to directly drive the row and column drivers of a display panel. internal memory resource of the de vice allows to easily handle complex graphics contents (pictures, icons, languages, fonts). the dcu3 supports 4-plane blending and 16 graphics la yers. control descriptors (cds) associated with each of the 16 layers enable effective merging of di fferent resolutions into one plane to optimize use of internal memory buffers. a layer ma y be constructed from graphic content of vari ous resolutions including indexed colors of 1, 2, 4 and 8 bpp, direct colors of 16, 24 and 32 bpp, and a yuv 4:2:2 color space. the ability of the dcu3 to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the pxd20. a special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizing graphic memory usage. a hardware cursor can be managed independently of the layers at bl ending level increasing the efficient use of the internal dcu3 resources. to secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the tft pads. the dcu3 features the following: ? display color depth: up to 24 bpp ? generation of all rgb and control signals for tft ? four-plane blending ? maximum number of input layers: 16 (fixed priority) ? dynamic look-up-table (color and gamma look-up) ? ?? blending range: up to 256 levels ? transparency mode ? gamma correction ? tiled mode on all the layers ? hardware cursor ? supports ycrcb 4:2:2 input data format ? rle decode inline supporting di rect read of rle compressed images from system memory ? critical display content integrity m onitoring for functional safety support ? internal direct memory access (d ma) module to transfer data from internal and / or external memory. the dcu3 also features a parallel data interface (pdi ) to receive external digita l video or graphic content into the dcu3. the pdi input is di rectly injected into the dcu3 background plane fifo . when the pdi is activated, all the dcu3 synchroni zation is extracted from the extern al video stream to guarantee the synchronization of the two video sources. the pdi can be used to: ? connect a video camera output directly to the pdi ? connect a secondary display driver as slave with a minimum of extra cost
pxd20 microcontroller reference manual, rev. 1 1-16 freescale semiconductor preliminary?subject to change without notice ? connect a device gathering various video sources ? provide flexibility to allow the dcu to be used in slave mode (e xternal synchronization) the pdi features the following: ? supported color modes: ? 8-bit mono ? 8-bit color multiplexed ? rgb565 ? 16-bit/18-bit raw color ? supported synchronization modes: ? embedded itu-r bt.656-4 (rgb565 mode 2) ? hsync, vsync ? data enable ? direct interface with dcu3 background plane fifo ? synchronization generation for the dcu3 1.5.14 display control unit lite (dculite) the dculite is a display controller designed to enable the pxd 20 to drive a second tft lcd display up to xga resolution using direct blit graphics and vi deo. the dculite includes all features of the dcu3, including the pdi with th e following exceptions: ? reduced from 4-plane to 2-plane blending ? reduced from 16 layers to 4 layers ? reduced clut size 1.5.15 timing controller (tcon) and rsds interface the tcon enables direct drive of the row and column drivers of display panels enabling emulation of tcon ics used in display panels. ? programmable timing generation un it featuring 12 waveform genera tors allowing high degree of flexibility in panel waveform generation ? reduced swing differential signaling (rsd s) interface for rgb da ta and pixel clock ? conforms to ?rsds ?int ra panel? interface sp ecification? rev. 1.0 (n ational semiconductor) 1.5.16 rle decoder the rle decoder is a crossbar slave sharing a slav e port with the quadspi m odule. the platform edma is used to stream compressed image data into and extract decompressed data out of the rle decoder. ? lossless decompression ? pixel formats supported: 8bpp, 16bpp, 24bpp and 32bpp ? ahb mapped read and write registers in rle_dec to achieve higher throughput
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-17 preliminary?subject to change without notice ? programmable fill levels of read and write buffers fo r initiating burst transfers ? crop feature: support for selectively reading out a part of decompre ssed image data taking complete compressed data fo r the full image as input. 1.5.17 dram controller the dram controller is a multi-port dram controller suppor ting sdr, lpddr1, ddr-1, and ddr-2 memories. the dram controller listens to the incoming requests to the seven buses in parallel and then sends commands to the dram from the highe st priority bus at the current time the seven incoming 64-bit buses are: ?dcu3 ?dculite ? e200z4d core - instruction bus ? e200z4d core - data bus ?viu2 ?gfx2d ?edma the dram controller f eatures the following: ? supports cas latency of 2, 3, and 4 clock cycles. ? master buses ? 7 incoming master buses ? supports 16-byte and 32-byte bursts ? supports byte enables ? supports 4-bit priority signal for each bus ? write buffer contains five 32-byte entries ? supports 16-wide and 32-wide sdr, dd r1, ddr2 and lpddr1 dram devices ? controller supports one chip select, 8-bank dram system ? supports dynamic on-die termination in the host device and in the dram. ? supports memory sizes as small as 64mbit 1.5.18 video input unit (viu2) the viu2 is a crossbar master module accepting an itu656 compatible video input stream on a parallel interface, converting the pixel data to rgb or yuv format and transf erring the video image to internal frame buffer memory or exte rnal dram if available. ? supports 8-bit/10-bit itu656 video input ? output formats: ? rgb888 ? rgb565
pxd20 microcontroller reference manual, rev. 1 1-18 freescale semiconductor preliminary?subject to change without notice ? 8-bit monochrome ? ycrcb 4:2:2 ? video downscaling ? contrast and brightness adjustment ? de-interlace for inte rlaced video image ? internal dma engine for data transfer to memory 1.5.19 boot assist module (bam) the bam is a block of read-only memory that is programmed once by freescale. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam s upports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (a program is downloaded into ram via can or lin and then executed) ? booting from external memory additionally the bam: ? enables and manages the transition of the mcu from reset to user code execution ? configures device for serial bootload ? enables multiple bootcode starting locations out of reset through implem entation of search for valid reset configuration halfword ? enables or disables software watchdog time r out of reset through bam read of reset configuration halfword option bit 1.5.20 enhanced modular inpu t/output system (emios) this device has two emios modules, each with 16 cha nnels supporting a range of 16-bit input capture, output compare, pulse width modulati on, and quadrature decode functions. ? selectable clock source from primary fmpll, secondary fmpll, external 4?16 mhz oscillator or 16 mhz internal rc oscill ator on a per module basis ? timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges ? edge aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? programmable phase sh ift between channels ? 4 channels of quadrature decode ? dma transfer support
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-19 preliminary?subject to change without notice 1.5.21 analog-to-digital converter (adc) the adc features the following: ? 10-bit a/d resolution ? 0?5 v or 0?3.3 v common mode conversion range ? supports conversions speeds of up to 1 ? s ? 20 internal and 8 external channels support ? up to 20 single-ended inputs channels ? 10 channels configured as input only pins ? 10-bit 2 counts accuracy (tue) ? 10 channels configured to have alternate function as general pur pose input/output pins ? 10-bit 3 counts accuracy (tue) ? external multiplexer support to increase up to 27 channels ? automatic 1 8 multiplexer control ? external multiplexer connected to a dedicated input channel ? shared register between the 8 external channels ? result register available fo r every non-multiplexed channel ? configurable left or right aligned result format ? supports for one-shot, scan and injection conversion modes ? injection mode status bit implemented on ad jacent 16-bit register for each result ? supports access to result and injec tion status with single 32-bit read ? independently enabling of function for channels: ? pre-sampling ? offset error cancellation ?offset refresh ? conversion triggering support ? internal conversion triggering from periodic interrupt timer (pit) ? four configurable analog comparator channels offering range comparison with triggered alarm ? greater than ?less than ? out of range ? all unused analog pins availabl e as general purpose input pins ? selected unused analog pins avai lable as general purpose pins ? power down mode ? optional support for dma transfer of results
pxd20 microcontroller reference manual, rev. 1 1-20 freescale semiconductor preliminary?subject to change without notice 1.5.22 serial peripheral interface (spi) the spi modules provide a synchronous serial in terface for communication between the mcu and external devices. the spi features: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data fram es from 4 to 16 bits ? up to 3 chip select lines avai lable, depending on package and pi n multiplexing, enab le 8 external devices to be selected using ex ternal muxing from a single spi ? eight clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for de-glitching ? fifos for buffering up to 4 transfer s on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma 1.5.23 controller area network (can) module the pxd20 includes up to three controller ar ea network (can) modules. the can module is a communication controll er implementing the can pr otocol according to bosch specification version 2.0b. the can protocol was designed to be used primarily as a vehicle seri al data bus, meeting the specific requirements of this field: real-t ime processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. each can module offers the following: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? mailboxes configurable while modul e remains synchronized to can bus ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or out er priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-21 preliminary?subject to change without notice ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities ?can sampler ? can catch the 1st message sent on the c an network while the mcu is stopped. this guarantees a clean startup of the system without missing message s on the can network. ? the can sampler is connected to one of the can rx pins. 1.5.24 serial communication interface module (uart) the pxd20 devices include up to four uart modules and support fo r uart master mode, uart slave mode and uart mode. the modules are uart state machine compliant to the lin 1.3 and 2.0 and 2.1 specifications and handle uart frame transmission and recept ion without cpu intervention. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? 2 receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to store identi fier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back
pxd20 microcontroller reference manual, rev. 1 1-22 freescale semiconductor preliminary?subject to change without notice ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 1.5.25 inter-integrated circuit (i 2 c) controller modules the pxd20 includes four i 2 c modules. each module features the following: ? two-wire bi-directional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multi-master operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection 1.5.26 system clocks and clock generation modules the system clock on the pxd20 can be derived from an external oscillator, an on-chip fmpll, or the internal 16 mhz oscillator. the source system clock frequency can be cha nged via an on-chip progr ammable clock divider ( ? 1 to ?? 2). an additional programmable peri pheral bus clock divider (ratios ? 1 to ??? ) is also available. the pxd20 has two on-chip fmplls (primary a nd secondary). each feat ures the following: ? input clock frequency from 4 mhz to 16 mhz ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) de tection for reference and feedback clocks ? on-chip loop filter (for impr oved electromagnetic interferen ce performance and reduction of number of external components required) ? support for frequency ramping from pll
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-23 preliminary?subject to change without notice the primary fmpll module is for use as a system cl ock source. the secondary fmpll is available for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation. the main oscillator provides the following features: ? input frequency range 4?16 mhz ? square-wave input mode ? oscillator input mode 3.3 v (5.0 v) ? automatic level control ? low power consumption ? pll reference the pxd20 also includes the following oscillators: ? 32 khz low power external oscillator for slow execution, low power, and rtc ? dedicated internal 128 khz rc oscillator fo r low power mode operation and self wake-up ? 10% accuracy across vol tage and temperature (a fter factory trimming) ? trimming registers to suppor t improved accuracy with in-application calibration ? dedicated 16 mhz inte rnal rc oscillator ? used as default clock source out of reset ? provides a clock for rapid st art-up from low power modes ? provides a back-up clock in the event of pll or external oscillator clock failure ? offers an independent cl ock source for the swt ? 5% accuracy across voltage and te mperature (after factory trimming) ? trimming registers to support frequency ad justment with in-appl ication calibration 1.5.27 periodic interrupt timer (pit) the pit features the following: ? eight general purpose interrupt timers ? two dedicated interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency 1.5.28 real time counter (rtc) the real timer counter supports wake-up from lo w power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 s resolution for >1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources from external 32 khz crystal, extern al 4?16 mhz crystal, internal 128 khz rc oscillator or divide d internal 16 mhz rc oscillator
pxd20 microcontroller reference manual, rev. 1 1-24 freescale semiconductor preliminary?subject to change without notice 1.5.29 system timer module (stm) the stm is a 32-bit timer designed to support commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.5.30 software watchdog timer (swt) the swt features the following: ? watchdog supporting software acti vation or enabled out of reset ? supports normal or windowed mode ? watchdog timer value wr itable once after reset ? watchdog supports optional halting during low power modes ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset ? clock source: 128 khz rc oscillator 1.5.31 stepper motor controller (smc) the smc module is a pwm motor controller suitable to drive instruments in a clus ter configuration or any other loads requiring a pwm signal. the motor controlle r has twelve pwm channels associated with two pins each (24 pins in total) driving up to 6 stepper motors. the smc module includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with select able pwm dithering function ? left, right, or center aligned pwm ? output slew rate control ? output short circuit detection this module is suited for, but not limited to, dr iving small stepper and ai r core motors used in instrumentation applications . this module can be used for other motor control or pwm applications that match the frequency, resolution, and out put drive capabilitie s of the module. 1.5.32 stepper stall de tect (ssd) module the ssd module provides a circuit to measure and inte grate the induced voltage on the non-driven coil of a stepper motor using full steps when the gauge pointer is returning to zero (rtz). the ssd module features the following:
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-25 preliminary?subject to change without notice ? programmable full step state ? programmable integration polarity ? blanking (recirculation) state ? 16-bit integration accumulator register ? 16-bit modulus down counter with interrupt 1.5.33 sound generator module (sgm) the sgm features the following: ? 4-channel audio mixer ? each channel capable of independent tone generation or wave playback ? individual channel volume control (8-bit resolution) ? tone mode: ? programmable tone frequency ? programmable amplitude enve lope: attack, duration and decay ? programmable number of tone pulses and inter-tone duration ? wave mode: ? one fifo per channel worki ng in conjunction with edma ? supports standard audio sampling rates (4 khz, 8 khz, 11.025 khz, 16 khz, 22.050 khz, 32 khz, 44.100 khz, 48 khz) ? same sample rate applies to all channels ? 8-bit, 12-bit, 16-bit input data formats ? programmable wave durati on and inter-wave duration ? repeat mode with programma ble number of wave playbacks ? sgm output: ? 16-bit pwm channel ? integrated i 2 s master interface for connect ion to external audio dac 1.5.34 ieee 1149.1 jtag controller (jtagc) jtagc features the following: ? backward compatible to standard jtag ieee 1149.1-2001 test access port (tap) interface ? support for boundary scan testing 1.5.35 nexus development interface (ndi) the nexus 3 module is compliant with class 3 of the ieee-isto 5001-2008 standard, with additional class 4 features available. the fo llowing features are implemented:
pxd20 microcontroller reference manual, rev. 1 1-26 freescale semiconductor preliminary?subject to change without notice ? program trace via branch trace messaging (btm ). branch trace messaging displays program flow discontinuities (direct and i ndirect branches, exceptions, etc.), allowing the de velopment tool to interpolate what transpires between the discontinuities. thus static code may be traced. ? data trace via data write me ssaging (dwm) and data read messaging (drm). this provides the capability for the development t ool to trace reads and/or writes to selected internal memory resources. ? ownership trace via ownership trace messagi ng (otm). otm facilitates ownership trace by providing visibility of which process id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. ? run-time access to embedded processor memory ma p via the jtag port. this allows for enhanced download/upload capabilities. ? watchpoint messaging vi a the auxiliary pins ? watchpoint trigger enable of pr ogram and/or data trace messaging ? data acquisition messaging (dqm ) allows code to be instru mented to export customized information to the nexus auxiliary output port. ? address translation messaging via program correl ation messages displays updates to the tlb for use by the debugger in correlating virtua l and physical address information ? auxiliary interface for higher data input/output ? registers for program trace, data trace, ownership trace and watchpoint trigger. ? all features controllable and configurable via the jtag port 1.6 how to use the pxd20 documents this section: ? describes how the pxd20 documents pr ovide information on the microcontroller ? makes recommendations on how to us e the documents in a system design 1.6.1 the pxd20 document set the pxd20 document set comprises: ? this reference manual (provides in formation on the features of the logical blocks on the device and how they are integrated with each other) ? the device data sheet (specifies the el ectrical characteristics of the device) ? the device product brief the following reference documents (available online at www.freescale.com) are also available to support the cpu on this device: ? programmer?s reference manual for freescale embedded processors ? e200z4 power architectur e core reference manual ? variable-length encoding (vle) programming environments manual
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-27 preliminary?subject to change without notice the aforementioned documents describe all of the f unctional and electrical char acteristics of the pxd20 microcontroller. depending on your task, you may need to refer to multiple documents to make design decisions. however, in general the use of the documents can be divided up as follows: ? use the reference manual (this document) dur ing software development and when allocating functions during system design. ? use the data sheet when designing hard ware and optimizing power consumption. ? use the cpu reference documents when: ? configuring cpu memory, bran ch and cache optimizations ? doing detailed software development in assembly language ? debugging complex software interactions 1.6.2 reference manual content the content in this document focuses on the functi onality of the microcontroller rather than its performance. most chapters describe the functionality of a particular on-chip module, such as a can controller or timer. the remaining chapters describe how these modules are integrated into the memory map, how they are powered and clocked, and the pin-out of the device. in general, when an individual modul e is enabled for use all of the detail required to configure and operate it is contained in the dedicated chap ter. in some cases ther e are multiple implementa tions of this module, however, there is only one chapter for each type of mo dule in use. for this reas on, the address of registers in each module is normally provide d as an offset from a base address which can be found in chapter 2, memory map . the benefit of this approach is that software developed for a pa rticular module can be easily reused on this device and on other rela ted devices that use the same modules. the steps to enable a module for use varies but typi cally these require configur ation of the integration features of the microcontroller. the module will normally have to be power ed and enabled at system level, then a clock may have to be explicitly chosen and finally if required the input and output connections to the external system must be configured. the primary integration chapters of the reference manual contain most of the information required to enable the modules. there are specia l cases where a chapter may describe module functionality and some integration features for convenience ? for example, the microcontroller input /output (siul) module. integration and functional content is provided in the manual as shown in table 1-3 .
pxd20 microcontroller reference manual, rev. 1 1-28 freescale semiconductor preliminary?subject to change without notice 1.7 using the pxd20 there are many different approaches to designing a system using the pxd20 so the guidance in this section is provided as an example of how the doc uments can be applied in this task. familiarity with the pxd20 m odules can help ensure that its features are being optimally used in a system design. therefore, the current chapte r is a good starting point. further info rmation on the detailed features of a module are provided within the module chapters. these, combined wi th the current chapter, should provide a good introduction to the functions available on the mcu. table 1-3. reference manual integration and functional content chapter integration content functional content overview ? the main features on chip ? a summary of the functions provided by each module ? memory map how the memo ry map is allocated, including: ? internal ram ? flash memory ? external memory-mapped resources and the location of the registers used by the peripherals 1 1 to find the address of a register in a particular module ta ke the start address of the module given in the memory map and add the offset for the register given in the module chapter. ? signal description how the signals from each of the modules are combined and brought to a particular pin on a package ? boot assist module cpu boot sequence from re set implementation of the boot options if internal flash memory is not used clock architecture clocking archit ecture of the device (which clock is available for the system and each peripheral) ? edma channel mux source values for module edma channels how to connect a module edma channel to the edma module interrupt controller interrupt vector table operation of the module mode entry module module numbering for cont rol and status operation of operating modes system integration unit lite how input signals are mapped to individual modules including external interrupt pins operation of gpio voltage regulators and power supplies power distribution to the mcu and in particular to different i/o banks ? wakeup unit allocation of inputs to the wakeup unit operation of the wakeup feature
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-29 preliminary?subject to change without notice 1.7.1 hardware design the pxd20 requires that certain pi ns are connected to particular pow er supplies, system functions and other voltage leve ls for operation. the pxd20 internal logic operates from 1.2 v (nom inal) supplies that are normally supplied by the on-chip voltage regulator from a 5 v or 3.3 v supply. the 5 v and 3.3 v supplies are also used to supply the input/output pins on the mcu. this means that di fferent input/output ports can operate at different voltages simultaneously. chapter 3, signal description, describes the power supply pin names, numbers and their purpose. for more detail on the voltage supply of each pin, see chapter 48, voltage regulators and power supplies ; that chapter also describes the use of th e required external ballast transistor to generate the 1.2 v. for specifications of the voltage ranges and limits and decoupling of the power supplies see the pxd20 data sheet. certain pins have dedicated functions that affect the behavior of the mc u after reset. these include pins to force test or alternate boot conditions and debug features. these are described in chapter 3, signal description, and a hardware designer should take care that these pins are connected to allow correct operation. beyond power supply and pins that have special functions there are also pins that have special system purposes such as oscillat or and reset pins. these are also described in chapter 3, signal description . the reset pin is bidirectional and its function is closely tied to the reset generation module (see chapter 37, reset generation module (mc_rgm) ). the crystal oscillator pins are dedicated to this function but the oscillator is not star ted automatically after reset. the oscillator module is described in section 8.4.1, pierce oscillator (fxosc), along with the internal clock architecture and the other oscillator sources on chip. 1.7.2 input/output pins the majority of the pins on the mcu are input/output pins which may either operate as general purpose pins or be connected to a particul ar on-chip module. the arrangement al lows a function to be available on several pins. the system designer s hould allocate the function for the pi n before connecting to external hardware. the software should then choose the co rrect function to match the hardware. the pad characteristics can vary dependi ng on the functions on the pad. chapter 3, signal description, describes each pad type (for example, slow, medium, or smd) . two pads may be able to carry the same function but have different pad types. the el ectrical specification of the pads is described in the data sheet dependent on the function enabled and the pad type. in addition to general purpose input/output pins the px d20 also includes dedicated pins that have a single function and connect to an external dram device. there are five modules that confi gure the various functions available: ? system integration unit lite (siul) ? wakeup unit (wkpu) ? timing controller (tcon) ? 32 khz oscillator (sxosc) ? dram controller
pxd20 microcontroller reference manual, rev. 1 1-30 freescale semiconductor preliminary?subject to change without notice the siul configures the di gital pin functions. each pin has a regi ster (pcr) in the module that allows selection of the output func tions that is connected to the pin. th e available settings for the pcr are described in section 3.3.10, functional ports. inputs are selected using th e psmi registers; these are described in chapter 43, system integration unit lite (siul) . (psmi registers connect a module to one of several pins, whereas the pcr registers c onnect a pin to one of several modules). the dram controller pins have a single function and use the related pc rs to configure the correct slew rate control for a connected memory. the wkpu provides the ability to cause interr upts and wake the mcu from low power modes and operates independently from the siul. in addition to digital i/o functions there are ?special functions? that provide analog functionality. these are listed in section 3.3.10, functional ports . the special functions are enabled independently from the digital i/o which means that the digi tal function on the pin must be disa bled when the special function is active. the tcon module and the sxos c oscillator are enabled in th e modules. the adc functions are enabled using the pcrs. the rsds function of the tcon module has a separate set of pcrs for configuration of the pin when th at special function is enabled. 1.7.3 software design certain modules provide system in tegration functions, and other m odules (such as timers and can modules) provide sp ecific functions. from reset, the modules involved in configur ing the system for application software are: ? boot assist module (bam) ? determines the selected boot source ? reset generation module (mc_rgm) ? determines the behavior of the mcu when various reset sources are triggered and reports the source of the reset ? mode entry module (mc_me) ? controls which op erating mode the mcu is in and configures the peripherals and clocks and power supplies for each of the modes ? power control unit (mc_pcu) ? de termines which power domains (see chapter 48, voltage regulators and power supplies ) are active ? clock generation module (mc_cgm) ? chooses the clock source for the system and many peripherals after reset, the mcu will automatical ly select the appropriate reset so urce and begin to execute code. at this point the system clock is the 16 mhz firc oscill ator, the cpu is in supervisor mode and the memory management unit (mmu) makes available a small area of memory at the selected reset vector. initialization is required before most memory and pe ripherals may be used and before the sram can be read (since it is protected by ecc the syndrome will generall y be uninitialized afte r reset and reads would fail the check). accessing disabled featur es causes error conditions or interrupts. a typical startup routine would i nvolve initializing the software en vironment starting with the mmu configuration and including stacks, heaps, variable initialization and so on and configuring the mcu for the application.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 1-31 preliminary?subject to change without notice the mmu translates physical memory addresses for use by the cpu and it must be configured before any peripherals or memories are avai lable for use by the cpu. see the e200z4 power architecture core reference manual for details on how to configure the mmu. the mc_me module enables the modules and other features like clocks. it is therefore an essential part of the initialization and operation so ftware. in general, the software will configure an mc_me mode to make certain peripherals, clocks, and memory active and then switch to that mode. chapter 8, clock description, includes a graphic of the clock archit ecture of the mcu. this can be used to determine how to configure the mc_cgm module. in general software will configure the module to enable the required clocks and plls and route these to the active modules. after these steps are complete it is possible to c onfigure the input/output pins and the modules for the application. 1.7.4 other features the mc_me module manages low power m odes and so it is likely that it will be used to switch into different configurations (module sets, cloc ks) depending on the application requirements. the mcu includes two other f eatures (both described in chapter 4, safety ) to improve the integrity of the application: ? it is possible to enable a software watchdog (swt ) immediately at reset or afterwards to help detect code runaway. ? individual register settings can be protected fr om unintended writes using the features of the register protection module. the pr otected registers are shown in appendix a, registers under protection . other integration f unctionality is provided by the system status and configur ation module (sscm).
pxd20 microcontroller reference manual, rev. 1 1-32 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 2-1 preliminary?subject to change without notice chapter 2 memory map table 2-1 shows the system memory map for the pxd 20. all addresses on the pxd20, including those that are reserved, are identified in the table. the addresses represent the physi cal addresses assigned to each ip block. table 2-1. pxd20 system memory map start address end address size (kb) region on-chip flash memories (code flash) code flash 0: fl-2048_4_0 (8 ? 16k, 2 ? 64k, 2 ? 128k, 6 ? 256k) 0x00000000 0x00003fff 16 code flash array 0 0x00004000 0x00007fff 16 code flash array 0 0x00008000 0x0000bfff 16 code flash array 0 0x000c000 0x0000ffff 16 code flash array 0 0x00010000 0x00013fff 16 code flash array 0 0x00014000 0x00017fff 16 code flash array 0 0x00018000 0x0001bfff 16 code flash array 0 0x001c000 0x0001ffff 16 code flash array 0 0x00020000 0x0002ffff 64 code flash array 0 0x00030000 0x0003ffff 64 code flash array 0 0x00040000 0x0005ffff 128 code flash array 0 0x00060000 0x0007ffff 128 code flash array 0 0x00080000 0x000bffff 256 code flash array 0 0x000c0000 0x000fffff 256 code flash array 0 0x00100000 0x0013ffff 256 code flash array 0 0x00140000 0x0017ffff 256 code flash array 0 0x00180000 0x001bffff 256 code flash array 0 0x001c0000 0x001fffff 256 code flash array 0 0x00200000 0x007fffff reserved on-chip flash memories (shadow for code flash) 0x00f00000 0x00ffbfff reserved 0x00ffc000 0x00ffffff 16 code flash array 0 shadow sector emulation mapping 0x01000000 0x1fffffff 507904 flash memory emulation mapping 0x20000000 0x3fffffff 524288 dram (lower 512 mb) sram
pxd20 microcontroller reference manual, rev. 1 2-2 freescale semiconductor preliminary?subject to change without notice 0x40000000 0x40001fff 8 sram (power domain pd0 ? always on) 0x40002000 0x4000ffff 56 sram (ram domain pd2) 0x40010000 0x5fffffff reserved 0x60000000 0x600fffff 1024 1 mb graphics sram 0x60100000 0x6fffffff reserved external, memory mapped serial flash for quadspi 0x70000000 0x77ffffff 131072 external serial flash memory a 0x78000000 0x7fffffff 131072 external serial flash memory b 0x80000000 0x8fffffff 262144 external serial flash memory a // b 0x90000000 0x900001ff 0.5 quadspi rx buffer 0x90000200 0x90003fff reserved 0x90004000 0x900041ff 0.5 rle decoder 0x90004200 0x9fffffff reserved 0xa0000000 0xbfffffff 524288 dram (upper 512 mb) pbridge(1) - off platform peripher als (mirrored to pbridge(0) memo ry range 0xffe80000-0xffefffff) 0xc0000000 0xc3f87fff reserved 0xc3f88000 0xc3f8bfff 16 code flash 0 configuration (cflash0) 0xc3f8c000 0xc3f8ffff reserved 0xc3f90000 0xc3f93fff 16 system integration unit lite (siul) 0xc3f94000 0xc3f97fff 16 wakeup unit (wkpu) 0xc3f98000 0xc3f9bfff reserved 0xc3f9c000 0xc3f9ffff reserved 0xc3fa0000 0xc3fa3fff 16 enhanced modular i/o subsystem 0 (emios0) 0xc3fa4000 0xc3fa7fff 16 enhanced modular i/o subsystem 1 (emios1) 0xc3fa8000 0xc3fd7fff reserved 0xc3fd8000 0xc3fdbfff 16 system status and configuration module (sscm) 0xc3fdc000 0xc3fdffff 16 mode entry module (mc_me) 0xc3fe0000 0xc3fe3fff 16 clock generation module (mc_cgm) 0xc3fe4000 0xc3fe7fff 16 reset generation module (mc_rgm) 0xc3fe8000 0xc3febfff 16 power control unit (mc_pcu) 0xc3fec000 0xc3feffff 16 real time counter & correction timer 0xc3ff0000 0xc3ff3fff 16 periodic interrupt timer (pit/rti) 0xc3ff4000 0xc3ffffff reserved table 2-1. pxd20 system memory map (continued) start address end address size (kb) region
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 2-3 preliminary?subject to change without notice pbridge(0) - off platform peripherals (new range) 0xffe00000 0xffe03fff 16 analog-to-digital converter 0 (adc0) 0xffe04000 0xffe13fff reserved 0xffe14000 0xffe17fff 16 rle decoder 0xffe18000 0xffe23fff reserved 0xffe24000 0xffe27fff 16 video input unit (viu2) 0xffe28000 0xffe2bfff 16 dram controller (dramc) 0xffe2c000 0xffe2ffff reserved 0xffe30000 0xffe33fff 16 inter-ic bus interface controller 0 (i2c0) 0xffe34000 0xffe37fff 16 inter-ic bus interface controller 1 (i2c1) 0xffe38000 0xffe3bfff 16 inter-ic bu s interface controller 2 (i2c2) 0xffe3c000 0xffe3ffff 16 inter-ic bus interface controller 3 (i2c3) 0xffe40000 0xffe43fff 16 linflex 0 0xffe44000 0xffe47fff 16 linflex 1 0xffe48000 0xffe4bfff 16 linflex 2 0xffe4c000 0xffe4ffff 16 linflex 3 0xffe50000 0xffe53fff 16 openvg graphics accelerator (gfx2d) 0xffe54000 0xffe57fff 16 graphics accelerator gasket (gxg) 0xffe58000 0xffe5bfff 16 display control unit lite (dculite) 0xffe5c000 0xffe5ffff 16 display control unit (dcu3) 0xffe60000 0xffe60fff 4 stepper motor controller (smc) 0xffe61000 0xffe617ff 2 stepper stall detect 0 (ssd0) 0xffe61800 0xffe61fff 2 stepper stall detect 1 (ssd1) 0xffe62000 0xffe627ff 2 stepper stall detect 2 (ssd2) 0xffe62800 0xffe62fff 2 stepper stall detect 3 (ssd3) 0xffe63000 0xffe637ff 2 stepper stall detect 4 (ssd4) 0xffe63800 0xffe63fff 2 stepper stall detect 5 (ssd5) 0xffe64000 0xffe6ffff reserved 0xffe70000 0xffe73fff 16 can sampler 0xffe74000 0xffe77fff reserved 0xffe78000 0xffe7bfff 16 sound generator module (sgm) 0xffe7c000 0xffe7ffff 16 timing controller (tcon) 0xffe80000 0xffefffff reserved table 2-1. pxd20 system memory map (continued) start address end address size (kb) region
pxd20 microcontroller reference manual, rev. 1 2-4 freescale semiconductor preliminary?subject to change without notice pbridge(0) - on platform peripherals 0xfff00000 0xfff03fff 16 pbridge0 0xfff04000 0xfff07fff 16 xbar 0xfff08000 0xfff0bfff reserved 0xfff0c000 0xfff0ffff 16 graphics ram controller 0xfff10000 0xfff13fff 16 memory protection unit (mpu) 0xfff14000 0xfff37fff reserved 0xfff38000 0xfff3bfff 16 software watchdog timer 0 (swt0) 0xfff3c000 0xfff3ffff 16 system timer module 0 (stm0) 0xfff40000 0xfff43fff 16 error correction status module (ecsm) 0xfff44000 0xfff47fff 16 1st direct memory access controller (edma) 0xfff48000 0xfff4bfff 16 inte rrupt controller (intc) 0xfff4c000 0xfff7ffff reserved pbridge(0) - off platform peripherals 0xfff80000 0xfff8ffff reserved 0xfff90000 0xfff93fff 16 dspi 0 0xfff94000 0xfff97fff 16 dspi 1 0xfff98000 0xfff9bfff 16 dspi 2 0xfff9c000 0xfff9ffff reserved 0xfffa0000 0xfffa3fff 16 quadspi0 0xfffa4000 0xfffbffff reserved 0xfffc0000 0xfffc3fff 16 flexcan 0 (can0) 0xfffc4000 0xfffc7fff 16 flexcan 1 (can1) 0xfffc8000 0xfffcbfff 16 flexcan 2 (can2) 0xfffcc000 0xfffdbfff reserved 0xfffdc000 0xfffdffff 16 dm a channel mux (dma_mux) 0xfffe0000 0xffffbfff reserved 0xffffc000 0xffffffff 16 b oot assist module (bam) table 2-1. pxd20 system memory map (continued) start address end address size (kb) region
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-1 preliminary?subject to change without notice chapter 3 signal description 3.1 introduction the following sections provide signa l descriptions and related inform ation about the f unctionality and configuration. 3.2 package pinouts the 176- and 208-pin lqfp pinouts a nd the 416 tepbga ballmap are provided in the following figures.
pxd20 microcontroller reference manual, rev. 1 3-2 freescale semiconductor preliminary?subject to change without notice figure 3-1. 176-pin lqfp pinout pxd20 176 lqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 vss vdd12 pf15 / qspi_clk_0 / clkout / mck0 pf14 / qspi_io1_0 / mdo3 pf13 / qspi_io0_0 / mdo2 pf12 / qspi_io3_0 / mdo1 pf11 / qspi_io2_0 / mdo0 pf10 / qspi_pcs_0 / evti pg12 / cs0_1 / pdi_de vss vdde_b pf9 / scl_0 / cs1_1 / txd_1 pf8 / sda_0 / cs2_1 / rxd_1 pf7 / emios1[15] / scl_1 pf6 / qspi_io0_1 / emios1[16] / pdi17_viu9 pf5 / qspi_io1_1 / emios1[15] / pdi16_viu8 pf4 / emios1[14] / sda_1 pf3 / emios1[21] / mseo2 pf1 / emios1[20] / mseo pf0 / emios1[19] / evto pk1 / qspi_io2_1 / emios1[14] / pdi15_viu7 pk0 / emios1[18] vss pb2 / txd_0 pb3 / rxd_0 pj15 / qspi_io3_1 / emios1[9] / pdi14_viu6 pj14 / qspi_clk_1 / emios1[17] / pdi_pclk pj13 / qspi_pcs_1 / emios1[8] / pdi13_viu5 pj12 / dcu_tag pg11 / dcu_pclk pg7 / dcu_b7 pg6 / dcu_b6 pg5 / dcu_b5 pg4 / dcu_b4 pg3 / dcu_b3 pg2 / dcu_b2 vdde_b vss vdd12 pg1 / dcu_b1 / sda_3 / emios0[22] pg0 / dcu_b0 / scl_3 / emios0[21] pa15 / dcu_g7 pa14 / dcu_g6 vss nmi/pf2 cs2_0 / emios1[10] / rxd_1 / pb12 cs1_0 / emios1[11] / txd_1 / pb13 vdde_b vss vdd12 emios1[12] / sda_1 / pk10 dcu_tag / emios1[13] / scl_1 / pk11 i2s_fs / emios1[18] / sck_0 / pb9 i2s_do / emios1[19] / sout_0 / pb8 i2s_sck / emios1[20] / sin_0 / pb7 emios0[23] / emios0[21] / pdi0_viu2 / pj4 emios0[16] / emios0[20] / pdi1_viu3 / pj5 emios0[15] / emios0[19] / pdi2_viu4 / pj6 emios0[14] / emios0[18] / pdi3_viu5 / pj7 pdi_de / emios0[22] / viu_pclk / pj3 emios1[21] / cs0_0 / ph4 ma0 / sck_1 / pb4 fabm / ma1 / sout_1 / pb5 abs[0] / ma2 / sin_1 / pb6 vdde_b vss vdd12 vss xtal32 / an15 / pc15 extal32 / an14 / pc14 cs0_1 / ma2 / an13 / pc13 cs1_1 / ma1 / an12 / pc12 cs2_1/ma0/an11/pc11 i2s_do / an10_mux / pc10 an9 / pc9 an8 / pc8 vdde_a vsse_a vdda vssa an7 / pc7 an6 / pc6 an5 / pc5 an4 / pc4 an3 / pc3 an2 / pc2 an1 / pc1 an0 / pc0 vdde_b pa13 / dcu_g5 pa12 / dcu_g4 pa11 / dcu_g3 pa10 / dcu_g2 pa9 / dcu_g1 / sda_2 / emios0[19] pa8 / dcu_g0 / scl_2 / emios0[20] pa7 / dcu_r7 pa6 / dcu_r6 vss vdde_b pa5 / dcu_r5 pa4 / dcu_r4 pa3 / dcu_r3 pa2 / dcu_r2 pa1 / dcu_r1 / scl_1 / emios0[17] pa0 / dcu_r0 / sda_1 / emios0[18] pm11 / txd_2 / cntx_2 / emios0[23] pm10 / rxd_2 / cnrx_2 / emios0[16] pm9/ pdi_pclk/ sgm_mclk/ emios0[8] vdde_b vss vdd12 pd15 / m3c1p / ssd3_3 / emios0[15] pd14 / m3c1m / ssd3_2 / emios0[14] pd13 / m3c0p / ssd3_1 / emios0[13] pd12 / m3c0m / ssd3_0 / emios0[12] vssm vddm pd11 / m2c1p / ssd2_3 / emios0[11] pd10 / m2c1m / ssd2_3 / emios0[10] pd9 / m2c0p / ssd2_1 / emios0[9] pd8 / m2c0m / ssd2_0 pd7 / m1c1p / ssd1_3 pd6 / m1c1m / ssd1_2 / emios0[23] pd5 / m1c0p / ssd1_1 / emios0[16] pd4 / m1c0m / ssd1_0 / emios0[8] vssm vddm pd3 / m0c1p / ssd0_3 / emios0[9] pd2 / m0c1m / ssd0_2 / emios1[23] pd1 / m0c0p / ssd0_1 / emios1[16] pd0 / m0c0m / ssd0_0 / emios1[8] vdde_b dcu_vsync / pg8 dcu_hsync / pg9 dcu_de / pg10 emios0[8] / emios1[9] / pdi_hsync_viu1 / pj1 emios0[9] / emios1[14] / pdi_vsync_viu0 / pj2 vdde_b vss emios0[13] / emios0[17] / pdi4_viu6 / pj8 emios0[12] / emios1[22] / pdi5_viu7 / pj9 emios0[11] / emios1[17] / pdi6_viu8 / pj10 emios0[10] / emios1[15] / pdi7_viu9 / pj11 rxd_0 / cnrx_0 / pb1 txd_0 / cntx_0 / pb0 i2s_do / cnrx_1 / pb10 sgm_mclk / cntx_1 / pb11 dcu_tag / emios1[22] / pdi13_viu5 / pm5 emios1[23] / pdi14_viu6 / pm6 vss vdde_b vddr vssr vsup_test vdd12 vss vddpll vreg_bypass extal xtal vrc_ctrl reset emios1[10] / pdi8_viu0 / pk2 emios1[11] / pdi9_viu1 / pk3 emios1[12] / pdi10_viu2 / pk4 emios1[13] / pdi11_viu3 / pk5 emios1[9] / pdi12_viu4 / pk6 vss vdde_b emios1[8] / i2s_fs / pdi15_viu7 / ph5 emios1[16] / i2s_do / pdi16_viu8 / pm7 emios1[23] / i2s_sck / pdi17_viu9 / pm8 tck / ph0 tdi/ph1 tdo/ph2 tms / ph3 note: functions in bold are available only on this package.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-3 preliminary?subject to change without notice figure 3-2. 208-pin lqfp pinout pxd20 208 lqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 dcu_vsync_tcon2 / pg8 dcu_hsync_tcon1 / pg9 dcu_de_tcon3 / pg10 emios0[8] / emios1[9] / pdi_hsync_viu1 / pj1 emios0[9] / emios1[14] / pdi_vsync_viu0 / pj2 vdde_b vss emios0[13] / emios0[17] / pdi4_viu6 / pj8 emios0[12] / emios1[22] / pdi5_viu7 / pj9 emios0[11] / emios1[17] / pdi6_viu8 / pj10 emios0[10] / emios1[15] / pdi7_viu9 / pj11 rxd_0 / cnrx_0 / pb1 txd_0 / cntx_0 / pb0 i2s_do / cnrx_1 / pb10 sgm_mclk / cntx_1 / pb11 tcon4 / rxd_3 / cnrx_2 / pm3 tcon5 / txd_3 / cntx_2 / pm4 vss vdde_b vddr vssr vsup_test vdd12 vss vddpll vreg_bypass extal xtal vrc_ctrl reset tcon6 / pdi13_viu5 / cs2_2 / pl4 tcon7 / pdi14_viu6 / cs1_2 / pl5 emios1[18] / pdi15_viu7 / cs0_2 / pl6 emios1[19] / pdi16_viu8 / sin_2 / pl7 emios1[20] / pdi17_viu9 / sout_2 / pl8 emios1[21] / pdi_pclk / sck_2 / pl9 vdde_b vss dculite_tag / emios1[10] / pdi8_viu0 / pk2 dculite_de / emios1[11] / pdi9_viu1 / pk3 dculite_hsync / emios1[12] / pdi10_viu2 / pk4 dculite_vsync / emios1[13] / pdi11_viu3 / pk5 dculite_pclk / emios1[9] / pdi12_viu4 / pk6 tcon8 / dculite_r2 / rxd_2 / pk7 tcon9 / dculite_r3 / txd_2 / pk8 tcon10 / dculite_r4 / i2s_do / pk9 vss vdde_b tck / ph0 tdi / ph1 tdo / ph2 tms / ph3 vdde_b pa13 / dcu_g5 / rsds6m pa12 / dcu_g4 / rsds6p pa11 / dcu_g3 / rsds5m pa10 / dcu_g2 / rsds5p pa9/dcu_g1/sda_2/emios0[19]/rsds4m pa8 / dcu_g0 / scl_2 / emios0[20] / rsds4p pa7 / dcu_r7 / rsds3m pa6 / dcu_r6 / rsds3p vss vdde_b vref_rsds pa5 / dcu_r5 / rsds2m pa4 / dcu_r4 / rsds2p pa3 / dcu_r3 / rsrs1m pa2 / dcu_r2 / rsds1p pa1 / dcu_r1 / scl_1 / emios0[17] / rsds0m pa0 / dcu_r0 / sda_1 / emios0[18] / rsds0p vdde_b vss vdd12 pe7 / m5c1p / ssd5_3 pe6 / m5c1m / ssd5_2 pe5 / m5c0p / ssd5_1 pe4 / m5c0m / ssd5_0 vssm vddm pe3 / m4c1p / ssd4_3 pe2 / m4c1m / ssd4_2 pe1 / m4c0p / ssd4_1 pe0 / m4c0m / ssd4_0 pd15 / m3c1p / ssd3_3 / emios0[15] pd14 / m3c1m / ssd3_2 / emios0[14] pd13 / m3c0p / ssd3_1 / emios0[13] pd12 / m3c0m / ssd3_0 / emios0[12] vssm vddm pd11 / m2c1p / ssd2_3 / emios0[11] pd10 / m2c1m / ssd2_2 / emios0[10] pd9 / m2c0p / ssd2_1 / emios0[9] pd8 / m2c0m / ssd2_0 pd7 / m1c1p / ssd1_3 pd6 / m1c1m / ssd1_2 / emios0[23] pd5 / m1c0p / ssd1_1 / emios0[16] pd4 / m1c0m / ssd1_0 / emios0[8] vssm vddm pd3 / m0c1p / ssd0_3 / emios0[9] pd2 / m0c1m / ssd0_2 / emios1[23] pd1 / m0c0p / ssd0_1 / emios1[16] pd0 / m0c0m / ssd0_0 / emios1[8] vdde_b nmi / pf2 cs2_0 / emios1[10] / rxd_1 / pb12 cs1_0 / emios1[11] / txd_1 / pb13 vdde_b vss vdd12 dcu_tag / emios1[12] / sda_1 / pk10 dculite_tag / emios1[13] / scl_1 / pk11 tcon11 / dculite_r5 / i2s_sck/ pm0 dculite_r6 / i2s_fs / pm1 vdde_b vss i2s_fs / emios1[18] / sck_0 / pb9 i2s_do / emios1[19] / sout_0 / pb8 i2s_sck / emios1[20] / sin_0 / pb7 emios0[23] / emios0[21] / pdi0_viu2 / pj4 emios0[16] / emios0[20] / pdi1_viu3 / pj5 emios0[15] / emios0[19] / pdi2_viu4 / pj6 emios0[14] / emios0[18] / pdi3_viu5 / pj7 pdi_de / emios0[22] / viu_pclk / pj3 dculite_g6/emios1[21]/cs0_0/ph4 ma0/sck_1/pb4 fabm / ma1 / sout_1 / pb5 abs[0] / ma2 / sin_1 / pb6 vdde_b vss vdd12 vss cnrx_1 / an19 / pl0 cntx_1 / an18 / pl1 emios1[22] / cnrx_0 / an17 / pl2 emios1[23] / cntx_0 / an16 / pl3 xtal32 / an15 / pc15 extal32 / an14 / pc14 cs0_1/ma2/an13/pc13 cs1_1/ma1/an12/pc12 cs2_1/ma0/an11/pc11 i2s_do / an10_mux / pc10 an9 / pc9 an8 / pc8 vdde_a vsse_a vdda vssa an7 / pc7 an6 / pc6 an5 / pc5 an4 / pc4 an3 / pc3 an2 / pc2 an1 / pc1 an0 / pc0 vss vdd12 pf15 / qspi_clk_0 / clkout / mcko pf14 / qspi_io1_0 / mdo3 pf13 / qspi_io0_0 / mdo2 pf12 / qspi_io3_0 / mdo1 pf11 / qspi_io2_0 / mdo0 pf10 / qspi_pcs_0 / evti pg12 / cs0_1 / pdi_de / dculite_b7 vss vdde_b pf9 / scl_0 / cs1_1 / txd_1 pf8 / sda_0 / cs2_1 / rxd_1 pf7 / emios1[15] / scl_1 / dculite_b6 pf6 / qspi_io0_1 / emios1[16] / pdi17_viu9 pf5 / qspi_io1_1 / emios1[15] / pdi16_viu8 pf4 / emios1[14] / sda_b / dculite_b5 pf3 / emios1[21] / mseo2 / dculite_b4 pf1 / emios1[20] / mseo / dculite_b3 pf0 / emios1[19] / evto / dculite_b2 pk1 / qspi_io2_1 / emios1[14] / pdi15_viu7 pk0 / emios1[18] / dculite_g7 vdd12 vss vdde_b pb2 / txd_0 pb3 / rxd_0 pj15 / qspi_io3_1 / emios1[9] / pdi14_viu6 pj14 / qspi_clk_1 / emios1[17] / pdi_pclk pj13 / qspi_pcs_1 / emios1[8] / pdi13_viu5 pj12 / dcu_tag_tcon0 / dculite_g6 pl13 / emios1[13] / dculite_g5 pl12 / emios1[12] / dculite_g4 pl11 / emios1[11] / dculite_g3 pl10 / emios1[10] / dculite_g2 pm2 / emios1[17] / dculite_r7/dculite_de/rsdslckm pg11 / dcu_pclk / rsdslckp pg7/ dcu_b7 / rsds11m pg6 / dcu_b6 / rsds11p pg5 / dcu_b5 / rsds10m pg4 / dcu_b4 / rsds10p pg3 / dcu_b3 / rsds9m pg2 / dcu_b2 / rsds9p vref_rsds vdde_b vss vdd12 pg1 / dcu_b1 / sda_3 / emios0[22] / rsds8m pg0 / dcu_b0 / scl_3 / emios0[21] / rsds8p pa15 / dcu_g7 / rsds7m pa14 / dcu_g6 / rsds7p vss
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-4 figure 3-3. 416-pin tepbga ballmap 1234567891011121314151617181920212223242526 a ddr_dq[2 6] ddr_dq[2 7] ddr_dq[2 8] ddr_dq[2 9] 30] 31] ddr_ba[0] ddr_ba[1] ddr_ba[2] ddr_addr ess[0] ddr_addr ess[4] ddr_addr ess[6] ddr_addr ess[8] ddr_addr ess[12] pg12 pf14 pf10 pf8 pf5 pf3 pk0 pb3 pj12 pl11 pg7 pg6 a b ddr_dq[2 5] vss ddr_dqs[ 3] ddr_dm[3 ] vss ddr_cas ddr_ras vss ddr_web ddr_addr ess[1] vss ddr_addr ess[7] ddr_addr ess[9] vss ddr_addr ess[15] pf13 vdde pf15 vss pf1 vdde pj15 pl13 vdde vss pg5 b c ddr_dq[2 3]] vdde_dd r vss ddr_dq[2 4] vdde_dd r vss ddr_dram _clk vdde_dd dr vss ddr_addr ess[2] vdde_dd r vss ddr_addr ess[10] vdde_dd r vss pf12 vss pf7 vdde pf0 vss pj14 pl12 pl10 pg3 pg4 c d ddr_dq[1 9] ddr_dq[2 0] ddr_dq[2 1] ddr_dq[2 2] ddr_odt vdd33_d dr ddr_dram _clkb ddr_cke ddr_cs ddr_addr ess[3] ddr_addr ess[5] vdd33_d dr ddr_addr ess[11] ddr_addr ess[13] ddr_addr ess[14] pf11 pf9 pf6 pf4 pk1 pb2 pj13 pm2 vref_rs ds2 pg2 pg1 d e ddr_dq[1 7] vss vdde_dd r ddr_dq[1 8] pg11 vss vdde pg0 e f ddr_dq[1 6] mvtt3 vss vdd33_d dr pa15 pa14 pa13 pa12 f g ddr_dq[1 5] ddr_dqs[ 2] ddr_dm[2 ] ddr_dq[1 4] pa11 pa9 pa8 pa7 g h ddr_dq[1 3] vss vdde_dd r ddr_dq[1 2] pa10 vdde vss va6 h j ddr_dq[1 1] mvtt2 vss mvref pa3 vref_rs ds1 pa5 pa4 j k ddr_dq[9] ddr_dqs[ 1] ddr_dm[1 ] ddr_dq[1 0] vdd12 vss vdd12 vss vdd12 vss vdd12 vss pa2 vss pa1 pa0 k l ddr_dq[8] vss vdde_dd r ddr_dq[7] vss vdd12 vss vdd12 vss vdd12 vss vdd12 pm13 pm12 vdde pj0 l m ddr_dq[5] mvtt1 vss ddr_dq[6] vdd12 vss vss vss vss vss vdd12 vss po7 po6 po5 po4 m n ddr_dq[3] ddr_dqs[ 0] vdde_dd r ddr_dq[4] vss vdd12 vss vss vss vss vss vdd12 po3 vdde po2 po1 n p ddr_dq[1] vss ddr_dm[0 ] ddr_dq[2] vdd12 vss vss vss vss vss vdd12 vss po0 pn15 p25 pn14 p r ddr_dq[0] mvtt0 vss vdd33_d dr vss vdd12 vss vss vss vss vss vdd12 pe7 pe6 pn13 pn12 r t pg10 pg9 vdde_dd r pg8 vdd12 vss vdd12 vss vdd12 vss vdd12 vss pe5 pe4 pe3 pe2 t u pj9 pj8 pj2 pj1 vss vdd12 vss vdd12 vs s vdd12 vss vdd12 pe1 vssm vddm pe0 u v pb1 vss pj11 pj10 pd15 pd14 pd13 pd12 v w reset pb10 vdde pb0 pd11 vddm vssm pd10 w y vss pm4 pm3 pb11 pd9 pd8 pd7 pd6 y aa xtal vreg_by pass vrc_ctr l vddreg pd5 vssm vddm pd4 aa ab extal pl4 vss vddpll pd3 pd2 pd1 pd0 ab ac vsup_te st pl5 pn0 pk4 pk6 ph0 pf2 pb13 pk11 pn2 pn4 pn8 pb9 pb7 pj7 pb5 mcko mdo6 mdo10 mvo0 pc0 vdda vsseh_a dc pc3 pc1 pc2 ac ad pl6 vdde pn1 vss pk7 ph1 vdde evti mseo vss pn5 pn9 vdde pj4 pj3 vss mseo2 mdo7 vdde mdo1 pc6 vssa vddeh_a dc pc4 pc7 pc5 ad ae pl7 vss pk2 vdde pk8 ph2 vss evto pm0 vdde pn6 pn10 vss pj5 ph4 vdde mdo4 mdo8 vss mdo2 pl1 pl0 pc10 pc11 pc9 pc8 ae af pl8 pl9 pk3 pk5 pk9 ph3 pb12 pk10 pm1 pn3 pn7 pn11 pb8 pj6 pb4 pb6 mdo5 mdo9 mdo11 mdo3 pl3 pl2 pc15 pc14 pc13 pc12 af 1234567891011121314151617181920212223242526
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-5 preliminary?subject to change without notice 3.3 signal descriptions the following sections provi de signal descriptions a nd related information about the signals? functionality and configuration. 3.3.1 pad configuratio n during reset phases all pads have a fixed c onfiguration under reset. during the power-up phase, all pa ds are forced to tristate. after power-up phase, all pads are fl oating with the following exceptions: ? pb[5] (fab) is pull-down. without external str ong pull-up the device starts fetching from flash memory. ? reset pad is driven low. this is re leased only after phase2 reset completion. ?fast (4 - 16 mhz) external oscillator pads (extal, xtal) are tristate. ? the following pads are pull-up: ?pb[6] ?ph[0] ?ph[1] ?ph[3] 3.3.2 voltage supply pins voltage supply pins are used to provide power to the device. two dedicated pins are used for 1.2 v regulator stabilization. table 3-1. voltage supply pin descriptions supply pin function pin number 176 lqfp 208 lqfp 416 tepbga v dd12 1 1.2 v core supply (1.08 v - 1.32 v) 23, 50, 67, 110, 138, 175 23, 58, 79, 136, 162, 186, 207 k10,k12,k14,k16, l11,l13,l15,l17,m 10,m16,n11,n17,p 10,p16,r11,r17,t 10,t12,t14,t16,u1 1,u13,u15,u17
pxd20 microcontroller reference manual, rev. 1 3-6 freescale semiconductor preliminary?subject to change without notice v ss 1.2 v ground 7, 18, 36, 49, 66, 68, 111, 123, 133, 139, 154, 167, 176 7, 18, 38, 47, 57, 64, 78, 80, 137, 147, 157, 163, 185, 199, 208 ab3,ad10,ad16,a d4,ae13,ae19,ae 2,ae7,b11,b14,b1 9,b2,b25,b5,b8,c1 2,c15,c17,c21,c3 ,c6,c9,e2,e24,f3, h2,h25,j3,k11,k1 3,k15,k17,k24,l10 ,l12,l14,l16,l2,m 11,m12,m13,m14, m15,m17,m3,n10, n12,n13,n14,n15, n16,p11,p12,p13, p14,p15,p17,p2,p 25,r10,r12,r13,r 14,r15,r16,r3,t1 1,t13,t15,t17,u10 ,u12,u14,u16,v2, y1 vdd12 ground and vddpll ground (vsspll) 24 24 ? v dde_b 3.3 v i/o supply. this supply is shared with internal flash, 16 mhz irc oscillator and 4?16mhz crystal oscillator. 6, 19, 37, 48, 65, 89, 112, 122, 132, 140, 166 6, 19, 37, 48, 56, 63, 77, 105, 138, 146, 156, 164, 184, 198 ad13,ad19,ad2,a d7,ae10,ae16,ae 4,b17,b21,b24,c1 9,e25,h24,l25,n2 4,w3 v dda 2 3.3 v/5 v reference voltage and analog supply for a/d converter. this supply is shared with the sxosc. 79 95 ac22 v ssa reference ground and analog ground for a/d converter 80 96 ad22 v ddr voltage regulator vreg supply 20 20 aa4 v ssr voltage regulator ground 21 21 ? v dde_a 2 3.3 v/5 v i/o supply. this supply is shared with the sxosc. 77 93 ad23 v sse_a 3.3 v/5 v i/o supply ground 78 94 ac23 v ddm stepper motor 3.3 v/5 v pad supply. ssd shares this supply. 94, 104 110, 120, 130 u25,w24,aa25 v ssm stepper motor ground 95, 105 111, 121, 131 u24,w24,aa24 v ddpll 1.2 v pll supply 25 25 ab4 v sup_test 3 9 v - 12 v flash test analog write signal 22 22 ac1 v dd_dr 1.8v, 2.5v, and 3.3v ddr sdram supply ? ? c2,c5,c8,c11,c14 ,e3,h3,l3,n3,t3 table 3-1. voltage supply pin descriptions (continued) supply pin function pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-7 preliminary?subject to change without notice 3.3.3 pad types the pads available for system pins a nd functional port pins are described in: ? the port pin summary in table 1 ; ? the pad type descriptions in table 3-6 ; ? section 43.5.3.8, ?pad configurat ion registers (pcr0?pcr184) and section 43.5.3.9, ?pad configuration registers (pcr185?pcr281) ; ? the device data sheet. 3.3.4 system pins the system pins are listed in table 3-2 . v dd33_dr functional supply for sdram pads (where available must be >= vdd_dr) ? ? d6, d12, f4, r4 1 decoupling capacitors must be connect ed between these pins and the nearest v ss pin. 2 vdda must be at the same voltage as vdde_a. 3 this signal needs to be connected to ground during normal operation. table 3-2. system pin descriptions system pin function i/o direction pad type reset configuration 1 pin number 176 lqfp 208 lqfp 416 tepbga reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull up 30 30 w1 extal analog input to the oscillator amplifier circuit. input for the clock generator in bypass mode. i x ? 27 27 ab1 xtal analog output of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. o x ? 28 28 aa1 extal32 analog input of the 32khz oscillator amplifier circuit. os ? 70 86 af24 table 3-1. voltage supply pin descriptions (continued) supply pin function pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 3-8 freescale semiconductor preliminary?subject to change without notice 3.3.5 nexus pins on the 176 lqfp and the 208 lqfp package options a re duced set of nexus pins are optionally available, multiplexed with gpio pins. on the 416 tepbga package option all nexus pins are dedicated to nexus only. xtal32 analog output of the 32 khz oscillator amplifier circuit. input for the clock generator in bypass mode. is ? 69 85 af23 nmi non-maskable interrupt i/o s input, none 45 53 ac7 vrc_ctrl voltage regulator external npn ballast base control pin analo g ? 29 29 aa3 vref_ rsds 2 rsds interface reference voltage analo g ? ? 145, 165 j24,d24 vreg_ bypass 3 pin used for factory testing i ? ? 26 26 aa2 1 reset configuration is given as i/o direction an d pull direction (for example, ?input, pullup?). 2 although this signal is not a supply for rsds pads, it needs to be terminated in an external capacitor with a value of 47 pf. 3 vreg_bypass should be pulled down externally. table 3-3. nexus pins system pin function pad type pcr pin number 1 176 lqfp 208 lqfp 416 tepbga evti nexus event in m pcr[80] 169 201 a17 evto nexus event out m pcr[70] 157 189 c20 mcko nexus msg clock out f pcr[85] 174 206 b18 mseo[0] nexus msg start/end out m pcr[71] 158 190 b20 mseo[2] nexus msg start/end out m pcr[73] 159 191 a20 mdo[0] nexus msg data out m pcr[81] 170 202 d16 mdo[1] nexus msg data out m pcr[82] 171 203 c16 mdo[2] nexus msg data out m pcr[83] 172 204 b16 mdo[3] nexus msg data out m pcr[84] 173 205 a16 evti nexus event in m pcr[197] n/a n/a ad8 table 3-2. system pin descriptions (continued) system pin function i/o direction pad type reset configuration 1 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-9 preliminary?subject to change without notice 3.3.6 dram interface the dram interface pins are listed in table 3-4 . evto nexus event out m pcr[198] n/a n/a ae8 mcko nexus msg clock out f pcr[200] n/a n/a ac17 mseo[0] nexus msg start/end out m pcr[199] n/a n/a ad9 mseo[2] nexus msg start/end out m pcr[201] n/a n/a ad17 mdo[0] nexus msg data out m pcr[185] n/a n/a ac20 mdo[1] nexus msg data out m pcr[186] n/a n/a ad20 mdo[2] nexus msg data out m pcr[187] n/a n/a ae20 mdo[3] nexus msg data out m pcr[188] n/a n/a af20 mdo[4] nexus msg data out m pcr[189] n/a n/a ae17 mdo[5] nexus msg data out m pcr[190] n/a n/a af17 mdo[6] nexus msg data out m pcr[191] n/a n/a ac18 mdo[7] nexus msg data out m pcr[192] n/a n/a ad18 mdo[8] nexus msg data out m pcr[193] n/a n/a ae18 mdo[9] nexus msg data out m pcr[194] n/a n/a af18 mdo[10] nexus msg data out m pcr[195] n/a n/a ac19 mdo[11] nexus msg data out m pcr[196] n/a n/a af19 1 on the 176 lqfp and 208 lqfp package options the nexus pi ns are multiplexed with other gpio. on the 416 tepbga package, there are additional dedicated nexus pins. table 3-4. dram interface pin summary port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga dram data bus ddr_dq[31] dram data bus [31] i/o ddr pcr[237] none, none a6 ddr_dq[30] dram data bus [30] i/o ddr pcr[238] none, none a5 ddr_dq[29] dram data bus [29] i/o ddr pcr[239] none, none a4 ddr_dq[28] dram data bus [28] i/o ddr pcr[240] none, none a3 ddr_dq[27] dram data bus [27] i/o ddr pcr[241] none, none a2 ddr_dq[26] dram data bus [26] i/o ddr pcr[242] none, none a1 table 3-3. nexus pins (continued) system pin function pad type pcr pin number 1 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 3-10 freescale semiconductor preliminary?subject to change without notice ddr_dq[25] dram data bus [25] i/o ddr pcr[243] none, none b1 ddr_dq[24] dram data bus [24] i/o ddr pcr[244] none, none c4 ddr_dq[23] dram data bus [23] i/o ddr pcr[245] none, none c1 ddr_dq[22] dram data bus [22] i/o ddr pcr[246] none, none d4 ddr_dq[21] dram data bus [21] i/o ddr pcr[247] none, none d3 ddr_dq[20] dram data bus [20] i/o ddr pcr[248] none, none d2 ddr_dq[19] dram data bus [19] i/o ddr pcr[249] none, none d1 ddr_dq[18] dram data bus [18] i/o ddr pcr[250] none, none e4 ddr_dq[17] dram data bus [17] i/o ddr pcr[251] none, none e1 ddr_dq[16] dram data bus [16] i/o ddr pcr[252] none, none f1 ddr_dq[15] dram data bus [15] i/o ddr pcr[253] none, none g1 ddr_dq[14] dram data bus [14] i/o ddr pcr[254] none, none g4 ddr_dq[13] dram data bus [13] i/o ddr pcr[255] none, none h1 ddr_dq[12] dram data bus [12] i/o ddr pcr[256] none, none h4 ddr_dq[11] dram data bus [11] i/o ddr pcr[257] none, none j1 ddr_dq[10] dram data bus [10] i/o ddr pcr[258] none, none k4 ddr_dq[9] dram data bus [9] i/o ddr pcr[259] none, none k1 ddr_dq[8] dram data bus [8] i/o ddr pcr[260] none, none l1 ddr_dq[7] dram data bus [7] i/o ddr pcr[261] none, none l4 ddr_dq[6] dram data bus [6] i/o ddr pcr[262] none, none m4 ddr_dq[5] dram data bus [5] i/o ddr pcr[263] none, none m1 ddr_dq[4] dram data bus [4] i/o ddr pcr[264] none, none n4 ddr_dq[3] dram data bus [3] i/o ddr pcr[265] none, none n1 ddr_dq[2] dram data bus [2] i/o ddr pcr[266] none, none p4 ddr_dq[1] dram data bus [1] i/o ddr pcr[267] none, none p1 ddr_dq[0] dram data bus [0] i/o ddr pcr[268] none, none r1 dram data strobes ddr_dqs[3] dram data strobe [3] i/o ddr pcr[232] none, none b3 ddr_dqs[2] dram data strobe [2] i/o ddr pcr[231] none, none g2 ddr_dqs[1] dram data strobe [1] i/o ddr pcr[230] none, none k2 ddr_dqs[0] dram data strobe [0] i/o ddr pcr[229] none, none n2 table 3-4. dram interface pin summary (continued) port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-11 preliminary?subject to change without notice dram data enables ddr_dm[3] dram data enable [3] output ddr pcr[236] output, none b4 ddr_dm[2] dram data enable [2] output ddr pcr[235] output, none g3 ddr_dm[1] dram data enable [1] output ddr pcr[234] output, none k3 ddr_dm[0] dram data enable [0] output ddr pcr[233] output, none p3 dram address ddr_a[15] dram address [15] output ddr pcr[217] output, none b15 ddr_a[14] dram address [14] output ddr pcr[216] output, none d15 ddr_a[13] dram address [13] output ddr pcr[215] output, none d14 ddr_a[12] dram address [12] output ddr pcr[214] output, none a14 ddr_a[11] dram address [11] output ddr pcr[213] output, none d13 ddr_a[10] dram address [10] output ddr pcr[212] output, none c13 ddr_a[9] dram address [9] output ddr pcr[211] output, none b13 ddr_a[8] dram address [8] output ddr pcr[210] output, none a13 ddr_a[7] dram address [7] output ddr pcr[209] output, none b12 ddr_a[6] dram address [6] output ddr pcr[208] output, none a12 ddr_a[5] dram address [5] output ddr pcr[207] output, none d11 ddr_a[4] dram address [4] output ddr pcr[206] output, none a11 ddr_a[3] dram address [3] output ddr pcr[205] output, none d10 ddr_a[2] dram address [2] output ddr pcr[204] output, none c10 table 3-4. dram interface pin summary (continued) port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga
pxd20 microcontroller reference manual, rev. 1 3-12 freescale semiconductor preliminary?subject to change without notice 3.3.7 viu muxing the dcu3, dculite and viu2 modules share the same pins for input video. it is, however, possibile to feed independent video streams to viu2 and dcu3 (operating in narrow mode). figure 3-4 explains the pin sharing arrangement. ddr_a[1] dram address [1] output ddr pcr[203] output, none b10 ddr_a[0] dram address [0] output ddr pcr[202] output, none a10 dram bank address ddr_ba[2] dram bank address[2] output ddr pcr[220] output, none a9 ddr_ba[1] dram bank address[1] output ddr pcr[219] output, none a8 ddr_ba[0] dram bank address[0] output ddr pcr[218] output, none a7 dram control ddr_cas column address strobe output ddr pcr[221] output, none b6 ddr_ras row address strobe output ddr pcr[227] output, none b7 ddr_web write enable output ddr pcr[228] output, none b9 ddr_odt dram on-die termination output ddr pcr[226] output, pull down d5 ddr_clk dram clock output ddr pcr[225] output, none c7 ddr_clkb dram clock bar output ddr na output, none d7 ddr_ck dram clock enable output ddr pcr[222] output, pull down d8 ddr_cs dram chip select output ddr pcr[223] output, none d9 mvref ddr reference voltage input ? na ? j4 mvtt dram termination voltage input ? na ? f2,j2,m2,r2 1 these port pins are disabled and unpowered on packages where the dram interface is not bonded out. 2 reset configuration is given as i/o direction an d pull direction (for example, ?input, pullup?). table 3-4. dram interface pin summary (continued) port pin 1 function i/o direction pad type pcr reset config 2 pin number 416 tepbga
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 3-13 preliminary?subject to change without notice figure 3-4. viu2, dcu3, and dculite pin sharing viu input data selection is done based on select bit (bit 0) of miscella neous control register (0xc3fe0340). ? viu pix data: viu[9:0] ? select bit 1?b0: pdi[7:0],hsync,vsync ? select bit 1?b1: pdi[17:8] 3.3.8 sgm muxing the sgm shares pins between the pwm output signals and the i2s bus signals as shown in the ?port pin summary? table. when the pwm function is enable d in the sgm (sgmctl[pw me]) the pwm (pwmo, pwmoa) signals are available. when the pwm func tion is disabled the i2s bus signals (i2s_do, i2s_sck) are available. 3.3.9 rsds special function muxing ports pa[0:15], pg[0:7], pg[11] and pm[2] have th e rsds signalling option as a special function. the siul allocates pad control register s to these functions (pcr[270:282]), but because these pads share a common pin with the normal gpio pins they do not operate in the same way as the normal gpio ports. pg[11] in particular has a special conf iguration separate from the other pads. the special-function pads are output-only, and the associated pcr[obe] bit is controlled by the tcon_ctrl1 register (tcon_bypass and rsds_m ode bits). however, the alternate function selection is taken from the associ ated normal gpio pad. this allows selection of the dcu3 function as the alternate function of the pad a nd then the tcon module to select if the output style is tcon/rsds or digital rgb format. viu2 dcu3 dculite pdi pdi viu[9:0] de pdi_pclk vsync hsync data[17:0] viu_pclk data[17:8] data[7:0] xbar direct feed of pdi interface to dcu3 or dculite rgb565 rgb888 8-bit mono yuv422
pxd20 microcontroller reference manual, rev. 1 3-14 freescale semiconductor preliminary?subject to change without notice therefore, when the tcon bypass is active (bypass disabled with or wi thout rsds active), it is important not to configure the norma l gpio ports for output operation with a non-dcu3 alternate function on ports pa[0:15] and pg[0:7]. for pg[11], the pcr[282] obe bit is fully controll ed by the tcon module and will become an output whenever the dcu3 alternate option is selected. th erefore, only select the dcu3 function on this pin when ready to configure it as a clock for a tft panel.
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-1 3.3.10 functional ports the functional port pins are listed in table 5 . note that most port pins have options to independently c onfigure slew rate control and after reset this will be set to the slowest option. in addition different pad types have diff erent slew rate performance and this may mean that the default slew rate needs to be changed to match the performance requir ed for each signal. refer to column ?pad type? when selecting and configuring port pins to determin e if slew rate adjustment may be required. table 5. port pin summary port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga port a pa[0] pcr[0] option 0 option 1 option 2 option 3 gpio[0] dcu_r0 sda_1 emios0[18] rsds0p siul dcu3 i 2 c_1 pwm/timer i/o m / rsds none, none 116 139 k26 pa[1] pcr[1] option 0 option 1 option 2 option 3 gpio[1] dcu_r1 scl_1 emios0[17] rsds0m siul dcu3 i 2 c_1 pwm/timer i/o m / rsds none, none 117 140 k25 pa[2] pcr[2] option 0 option 1 option 2 option 3 gpio[2] dcu_r2 ? ? rsds1p siul dcu3 ? ? i/o m / rsds none, none 118 141 k23 pa[3] pcr[3] option 0 option 1 option 2 option 3 gpio[3] dcu_r3 ? ? rsds1m siul dcu3 ? ? i/o m / rsds none, none 119 142 j23 pa[4] pcr[4] option 0 option 1 option 2 option 3 gpio[4] dcu_r4 ? ? rsds2p siul dcu3 ? ? i/o m / rsds none, none 120 143 j26 pa[5] pcr[5] option 0 option 1 option 2 option 3 gpio[5] dcu_r5 ? ? rsds2m siul dcu3 ? ? i/o m / rsds none, none 121 144 j25 pa[6] pcr[6] option 0 option 1 option 2 option 3 gpio[6] dcu_r6 ? ? rsds3p siul dcu3 ? ? i/o m / rsds none, none 124 148 h26
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-1 pa[7] pcr[7] option 0 option 1 option 2 option 3 gpio[7] dcu_r7 ? ? rsds3m siul dcu3 ? ? i/o m / rsds none, none 125 149 g26 pa[8] pcr[8] option 0 option 1 option 2 option 3 gpio[8] dcu_g0 scl_2 emios0[20] rsds4p siul dcu3 i 2 c_2 pwm/timer i/o m / rsds none, none 126 150 g25 pa[9] pcr[9] option 0 option 1 option 2 option 3 gpio[9] dcu_g1 sda_2 emios0[19] rsds4m siul dcu3 i 2 c_2 pwm/timer i/o m / rsds none, none 127 151 g24 pa[10] pcr[10] option 0 option 1 option 2 option 3 gpio[10] dcu_g2 ? ? rsds5p siul dcu3 ? ? i/o m / rsds none, none 128 152 h23 pa[11] pcr[11] option 0 option 1 option 2 option 3 gpio[11] dcu_g3 ? ? rsds5m siul dcu3 ? ? i/o m / rsds none, none 129 153 g23 pa[12] pcr[12] option 0 option 1 option 2 option 3 gpio[12] dcu_g4 ? ? rsds6p siul dcu3 ? ? i/o m / rsds none, none 130 154 f26 pa[13] pcr[13] option 0 option 1 option 2 option 3 gpio[13] dcu_g5 ? ? rsds6m siul dcu3 ? ? i/o m / rsds none, none 131 155 f25 pa[14] pcr[14] option 0 option 1 option 2 option 3 gpio[14] dcu_g6 ? ? rsds7p siul dcu3 ? ? i/o m / rsds none, none 134 158 f24 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-1 pa[15] pcr[15] option 0 option 1 option 2 option 3 gpio[15] dcu_g7 ? ? rsds7m siul dcu3 ? ? i/o m / rsds none, none 135 159 f23 port b pb[0] pcr[16] option 0 option 1 option 2 option 3 gpio[16] cantx_0 txd_0 ? ?siul flexcan_0 linflex_0 ? i/o s none, none 13 13 w4 pb[1] pcr[17] option 0 option 1 option 2 option 3 gpio[17] canrx_0 rxd_0 ? ?siul flexcan_0 linflex_0 ? i/o s none, none 12 12 v1 pb[2] pcr[18] option 0 option 1 option 2 option 3 gpio[18] txd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 153 183 d21 pb[3] pcr[19] option 0 option 1 option 2 option 3 gpio[19] rxd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 152 182 a22 pb[4] pcr[20] option 0 option 1 option 2 option 3 gpio[20] sck_1 ma0 ? ?siul dspi_1 adc ? i/o s none, none 62 74 af15 pb[5] pcr[21] option 0 option 1 option 2 option 3 gpio[21] sout_1 ma1 fabm ?siul dspi_1 adc control i/o s input, pull- down 63 75 ac16 pb[6] pcr[22] option 0 option 1 option 2 option 3 gpio[22] sin_1 ma2 abs[0] ?siul dspi_1 adc control i/o s input, pull- up 64 76 af16 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-1 pb[7] pcr[23] option 0 option 1 option 2 option 3 gpio[23] sin_0 emios1[20] i2s_sck/pwmoa ?siul dspi_0 pwm/timer sgm i/o s none, none 55 67 ac14 pb[8] pcr[24] option 0 option 1 option 2 option 3 gpio[24] sout_0 emios1[19] i2s_do/pwmo ?siul dspi_0 pwm/timer sgm i/o s none, none 54 66 af13 pb[9] pcr[25] option 0 option 1 option 2 option 3 gpio[25] sck_0 emios1[18] i2s_fs ?siul dspi_0 pwm/timer sgm i/o m none, none 53 65 ac13 pb[10] pcr[26] option 0 option 1 option 2 option 3 gpio[26] canrx_1 i2s_do/pwmo ? ?siul flexcan_1 sgm ? i/o s none, none 14 14 w2 pb[11] pcr[27] option 0 option 1 option 2 option 3 gpio[27] cantx_1 sgm_mclk ? ?siul flexcan_1 sgm ? i/o s none, none 15 15 y4 pb[12] pcr[28] option 0 option 1 option 2 option 3 gpio[28] rxd_1 emios1[10] cs2_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 46 54 af7 pb[13] pcr[29] option 0 option 1 option 2 option 3 gpio[29] txd_1 emios1[11] cs1_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 47 55 ac8 pb[14] ? ? reserved ? ? ? ? ? ? ? ? pb[15] ? ? reserved ? ? ? ? ? ? ? ? port c table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-1 pc[0] pcr[30] option 0 option 1 option 2 option 3 gpio[30] ? ? ? ans[0] siul ? ? ? i/o j none, none 88 104 ac21 pc[1] pcr[31] option 0 option 1 option 2 option 3 gpio[31] ? ? ? ans[1] siul ? ? ? i/o j none, none 87 103 ac25 pc[2] pcr[32] option 0 option 1 option 2 option 3 gpio[32] ? ? ? ans[2] siul ? ? ? i/o j none, none 86 102 ac26 pc[3] pcr[33] option 0 option 1 option 2 option 3 gpio[33] ? ? ? ans[3] siul ? ? ? i/o j none, none 85 101 ac24 pc[4] pcr[34] option 0 option 1 option 2 option 3 gpio[34] ? ? ? ans[4] siul ? ? ? i/o j none, none 84 100 ad24 pc[5] pcr[35] option 0 option 1 option 2 option 3 gpio[35] ? ? ? ans[5] siul ? ? ? i/o j none, none 83 99 ad26 pc[6] pcr[36] option 0 option 1 option 2 option 3 gpio[36] ? ? ? ans[6] siul ? ? ? i/o j none, none 82 98 ad21 pc[7] pcr[37] option 0 option 1 option 2 option 3 gpio[37] ? ? ? ans[7] siul ? ? ? i/o j none, none 81 97 ad25 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pc[8] pcr[38] option 0 option 1 option 2 option 3 gpio[38] ? ? ? ans[8] siul ? ? ? i/o j none, none 76 92 ae26 pc[9] pcr[39] option 0 option 1 option 2 option 3 gpio[39] ? ? ? ans[9] siul ? ? ? i/o j none, none 75 91 ae25 pc[10] pcr[40] option 0 option 1 option 2 option 3 gpio[40] ? i2s_do/pwmo ? ans[10] siul ? sgm ? i/o j none, none 74 90 ae23 pc[11] pcr[41] option 0 option 1 option 2 option 3 gpio[41] ? ma0 cs2_1 ans[11] siul ? adc dspi_1 i/o j none, none 73 89 ae24 pc[12] pcr[42] option 0 option 1 option 2 option 3 gpio[42] ? ma1 cs1_1 ans[12] siul ? adc dspi_1 i/o j none, none 72 88 af26 pc[13] pcr[43] option 0 option 1 option 2 option 3 gpio[43] ? ma2 cs0_1 ans[13] siul ? adc dspi_1 i/o j none, none 71 87 af25 pc[14] pcr[44] option 0 option 1 option 2 option 3 gpio[44] ? ? ? ans[14] extal32 siul ? ? ? i/o j none, none 70 86 af24 pc[15] pcr[45] option 0 option 1 option 2 option 3 gpio[45] ? ? ? ans[15] xtal32 siul ? ? ? i/o j none, none 69 85 af23 port d table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pd[0] pcr[46] option 0 option 1 option 2 option 3 gpio[46] m0c0m ssd0_0 emios1[8] ?siul smd ssd pwm/timer i/o smd none, none 90 106 ab26 pd[1] pcr[47] option 0 option 1 option 2 option 3 gpio[47] m0c0p ssd0_1 emios1[16] ?siul smd ssd pwm/timer i/o smd none, none 91 107 ab25 pd[2] pcr[48] option 0 option 1 option 2 option 3 gpio[48] m0c1m ssd0_2 emios1[23] ?siul smd ssd pwm/timer i/o smd none, none 92 108 ab24 pd[3] pcr[49] option 0 option 1 option 2 option 3 gpio[49] m0c1p ssd0_3 emios0[9] ?siul smd ssd pwm/timer i/o smd none, none 93 109 ab23 pd[4] pcr[50] option 0 option 1 option 2 option 3 gpio[50] m1c0m ssd1_0 emios0[8] ?siul smd ssd pwm/timer i/o smd none, none 96 112 aa26 pd[5] pcr[51] option 0 option 1 option 2 option 3 gpio[51] m1c0p ssd1_1 emios0[16] ?siul smd ssd pwm/timer i/o smd none, none 97 113 aa23 pd[6] pcr[52] option 0 option 1 option 2 option 3 gpio[52] m1c1m ssd1_2 emios0[23] ?siul smd ssd pwm/timer i/o smd none, none 98 114 y26 pd[7] pcr[53] option 0 option 1 option 2 option 3 gpio[53] m1c1p ssd1_3 ? ?siul smd ssd ? i/o smd none, none 99 115 y25 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pd[8] pcr[54] option 0 option 1 option 2 option 3 gpio[54] m2c0m ssd2_0 ? ?siul smd ssd ? i/o smd none, none 100 116 y24 pd[9] pcr[55] option 0 option 1 option 2 option 3 gpio[55] m2c0p ssd2_1 emios0[9] ?siul smd ssd pwm/timer i/o smd none, none 101 117 y23 pd[10] pcr[56] option 0 option 1 option 2 option 3 gpio[56] m2c1m ssd2_2 emios0[10] ?siul smd ssd pwm/timer i/o smd none, none 102 118 w26 pd[11] pcr[57] option 0 option 1 option 2 option 3 gpio[57] m2c1p ssd2_3 emios0[11] ?siul smd ssd pwm/timer i/o smd none, none 103 119 w23 pd[12] pcr[58] option 0 option 1 option 2 option 3 gpio[58] m3c0m ssd3_0 emios0[12] ?siul smd ssd pwm/timer i/o smd none, none 106 122 v26 pd[13] pcr[59] option 0 option 1 option 2 option 3 gpio[59] m3c0p ssd3_1 emios0[13] ?siul smd ssd pwm/timer i/o smd none, none 107 123 v25 pd[14] pcr[60] option 0 option 1 option 2 option 3 gpio[60] m3c1m ssd3_2 emios0[14] ?siul smd ssd pwm/timer i/o smd none, none 108 124 v24 pd[15] pcr[61] option 0 option 1 option 2 option 3 gpio[61] m3c1p ssd3_3 emios0[15] ?siul smd ssd pwm/timer i/o smd none, none 109 125 v23 port e table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pe[0] pcr[62] option 0 option 1 option 2 option 3 gpio[62] m4c0m ssd4_0 ? ?siul smd ssd ? i/o smd none, none ? 126 u26 pe[1] pcr[63] option 0 option 1 option 2 option 3 gpio[63] m4c0p ssd4_1 ? ?siul smd ssd ? i/o smd none, none ? 127 u23 pe[2] pcr[64] option 0 option 1 option 2 option 3 gpio[64] m4c1m ssd4_2 ? ?siul smd ssd ? i/o smd none, none ? 128 t26 pe[3] pcr[65] option 0 option 1 option 2 option 3 gpio[65] m4c1p ssd4_3 ? ?siul smd ssd ? i/o smd none, none ? 129 t25 pe[4] pcr[66] option 0 option 1 option 2 option 3 gpio[66] m5c0m ssd5_0 ? ?siul smd ssd ? i/o smd none, none ? 132 t24 pe[5] pcr[67] option 0 option 1 option 2 option 3 gpio[67] m5c0p ssd5_1 ? ?siul smd ssd ? i/o smd none, none ? 133 t23 pe[6] pcr[68] option 0 option 1 option 2 option 3 gpio[68] m5c1m ssd5_2 ? ?siul smd ssd ? i/o smd none, none ? 134 r24 pe[7] pcr[69] option 0 option 1 option 2 option 3 gpio[69] m5c1p ssd5_3 ? ?siul smd ssd ? i/o smd none, none ? 135 r23 port f table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pf[0] pcr[70] option 0 option 1 option 2 option 3 gpio[70] emios1[19] evto dculite_b2 ?siul pwm/timer nexus dculite i/o m none, none 157 189 c20 pf[1] pcr[71] option 0 option 1 option 2 option 3 gpio[71] emios1[20] mseo dculite_b3 ?siul pwm/timer nexus dculite i/o m none, none 158 190 b20 pf[2] pcr[72] option 0 option 1 option 2 option 3 gpio[72] nmi ? ? ?siul nmi ? ? i/o s none, none 45 53 ac7 pf[3] pcr[73] option 0 option 1 option 2 option 3 gpio[73] emios1[21] mseo dculite_b4 ?siul pwm/timer nexus dculite i/o m none, none 159 191 a20 pf[4] pcr[74] option 0 option 1 option 2 option 3 gpio[74] emios1[14] sda_1 dculite_b5 ?siul pwm/timer i 2 c_1 dculite i/o m none, none 160 192 d19 pf[5] pcr[75] option 0 option 1 option 2 option 3 gpio[75] quadspi_io1_b emios1[15] viu8_pdi16 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 161 193 a19 pf[6] pcr[76] option 0 option 1 option 2 option 3 gpio[76] quadspi_io0_b emios1[16] viu9_pdi17 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 162 194 d18 pf[7] pcr[77] option 0 option 1 option 2 option 3 gpio[77] emios1[15] scl_1 dculite_b6 ?siul pwm/timer i 2 c_1 dculite i/o m none, none 163 195 c18 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pf[8] pcr[78] option 0 option 1 option 2 option 3 gpio[78] sda_0 cs2_1 rxd_1 ?siul i 2 c_0 dspi_1 linflex_1 i/o s none, none 164 196 a18 pf[9] pcr[79] option 0 option 1 option 2 option 3 gpio[79] scl_0 cs1_1 txd_1 ?siul i 2 c_0 dspi_1 linflex_1 i/o s none, none 165 197 d17 pf[10] pcr[80] option 0 option 1 option 2 option 3 gpio[80] quadspi_pcs_a ? evti ?siul quadspi ? nexus i/o m none, none 169 201 a17 pf[11] pcr[81] option 0 option 1 option 2 option 3 gpio[81] quadspi_io2_a ? mdo0 ?siul quadspi ? nexus i/o m none, none 170 202 d16 pf[12] pcr[82] option 0 option 1 option 2 option 3 gpio[82] quadspi_io3_a ? mdo1 ?siul quadspi ? nexus i/o m none, none 171 203 c16 pf[13] pcr[83] option 0 option 1 option 2 option 3 gpio[83] quadspi_io0_a ? mdo2 ?siul quadspi ? nexus i/o m none, none 172 204 b16 pf[14] pcr[84] option 0 option 1 option 2 option 3 gpio[84] quadspi_io1_a ? mdo3 ?siul quadspi ? nexus i/o m none, none 173 205 a16 pf[15] pcr[85] option 0 option 1 option 2 option 3 gpio[85] quadspi_clk_a clkout mcko ?siul quadspi control nexus i/o f none, none 174 206 b18 port g table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pg[0] pcr[86] option 0 option 1 option 2 option 3 gpio[86] dcu_b0 scl_3 emios0[21] rsds8p siul dcu3 i 2 c_3 pwm/timer i/o m none, none 136 160 e26 pg[1] pcr[87] option 0 option 1 option 2 option 3 gpio[87] dcu_b1 sda_3 emios0[22] rsds8m siul dcu3 i 2 c_3 pwm/timer i/o m none, none 137 161 d26 pg[2] pcr[88] option 0 option 1 option 2 option 3 gpio[88] dcu_b2 ? ? rsds9p siul dcu3 ? ? i/o m none, none 141 166 d25 pg[3] pcr[89] option 0 option 1 option 2 option 3 gpio[89] dcu_b3 ? ? rsds9m siul dcu3 ? ? i/o m none, none 142 167 c25 pg[4] pcr[90] option 0 option 1 option 2 option 3 gpio[90] dcu_b4 ? ? rsds10p siul dcu3 ? ? i/o m none, none 143 168 c26 pg[5] pcr[91] option 0 option 1 option 2 option 3 gpio[91] dcu_b5 ? ? rsds10m siul dcu3 ? ? i/o m none, none 144 169 b26 pg[6] pcr[92] option 0 option 1 option 2 option 3 gpio[92] dcu_b6 ? ? rsds11p siul dcu3 ? ? i/o m none, none 145 170 a26 pg[7] pcr[93] option 0 option 1 option 2 option 3 gpio[93] dcu_b7 ? ? rsds11m siul dcu3 ? ? i/o m none, none 146 171 a25 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pg[8] pcr[94] option 0 option 1 option 2 option 3 gpio[94] dcu_vsync ? ? ?siul dcu3 ? ? i/o m none, none 11 t4 pg[9] pcr[95] option 0 option 1 option 2 option 3 gpio[95] dcu_hsync ? ? ?siul dcu3 ? ? i/o m none, none 22 t2 pg[10] pcr[96] option 0 option 1 option 2 option 3 gpio[96] dcu_de ? ? ?siul dcu3 ? ? i/o m none, none 33 t1 pg[11] pcr[97] option 0 option 1 option 2 option 3 gpio[97] dcu_pclk ? ? rsdsclkp siul dcu3 ? ? i/o f none, none 147 172 e23 pg[12] pcr[98] option 0 option 1 option 2 option 3 gpio[98] cs0_1 pdi_de dculite_b7 ?siul dspi_1 pdi dculite i/o m none, none 168 200 a15 pg[13] ? ? reserved ? ? ? ? ? ? ? ? pg[14] ? ? reserved ? ? ? ? ? ? ? ? pg[15] ? ? reserved ? ? ? ? ? ? ? ? port h ph[0] 6 pcr[99] option 0 option 1 option 2 option 3 gpio[99] tck ? ? ?siul jtag ? ? i/o s input, pull up 41 49 ac6 ph[1] 6 pcr[100] option 0 option 1 option 2 option 3 gpio[100] tdi ? ? ?siul jtag ? ? i/o s input, pull up 42 50 ad6 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 ph[2] 6 pcr[101] option 0 option 1 option 2 option 3 gpio[101] tdo ? ? ?siul jtag ? ? i/o m output, none 43 51 ae6 ph[3] 6 pcr[102] option 0 option 1 option 2 option 3 gpio[102] tms ? ? ?siul jtag ? ? i/o s input, pull up 44 52 af6 ph[4] pcr[103] option 0 option 1 option 2 option 3 gpio[103] cs0_0 emios1[21] dculite_g6 ?siul dspi_0 pwm/timer dculite i/o m none, none 61 73 ae15 ph[5] pcr[104] option 0 option 1 option 2 option 3 gpio[104] viu7_pdi15 i2s_fs emios1[8] ?siul viu2/pdi sgm pwm/timer i/o s none, none 38 ? ? ph[6] ? ? reserved ? ? ? ? ? ? ? ? ph[7] ? ? reserved ? ? ? ? ? ? ? ? ph[8] ? ? reserved ? ? ? ? ? ? ? ? ph[9] ? ? reserved ? ? ? ? ? ? ? ? ph[10] ? ? reserved ? ? ? ? ? ? ? ? ph[11] ? ? reserved ? ? ? ? ? ? ? ? ph[12] ? ? reserved ? ? ? ? ? ? ? ? ph[13] ? ? reserved ? ? ? ? ? ? ? ? ph[14] ? ? reserved ? ? ? ? ? ? ? ? ph[15] ? ? reserved ? ? ? ? ? ? ? ? port j pj[0] pcr[105] option 0 option 1 option 2 option 3 gpio[105] dculite_b6 ? i2s_do / pwmo ?siul dculite ? sgm i/o m none, none ? ? l26 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-2 pj[1] pcr[106] option 0 option 1 option 2 option 3 gpio[106] viu1_pdi_hsync emios1[9] emios0[8] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 44 u4 pj[2] pcr[107] option 0 option 1 option 2 option 3 gpio[107] viu0_pdi_vsync emios1[14] emios0[9] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 55 u3 pj[3] pcr[108] option 0 option 1 option 2 option 3 gpio[108] viu_pclk emios0[22] pdi_de ?siul viu2 pwm/timer pdi i/o s none, none 60 72 ad15 pj[4] pcr[109] option 0 option 1 option 2 option 3 gpio[109] viu2_pdi0 emios0[21] emios0[23] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 56 68 ad14 pj[5] pcr[110] option 0 option 1 option 2 option 3 gpio[110] viu3_pdi1 emios0[20] emios0[16] ?siul viu2/pdi pwm/timer pwm/timer i/o m none, none 57 69 ae14 pj[6] pcr[111] option 0 option 1 option 2 option 3 gpio[111] viu4_pdi2 emios0[19] emios0[15] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 58 70 af14 pj[7] pcr[112] option 0 option 1 option 2 option 3 gpio[112] viu5_pdi3 emios0[18] emios0[14] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 59 71 ac15 pj[8] pcr[113] option 0 option 1 option 2 option 3 gpio[113] viu6_pdi4 emios0[17] emios0[13] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 88 u2 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pj[9] pcr[114] option 0 option 1 option 2 option 3 gpio[114] viu7_pdi5 emios1[22] emios0[12] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 99 u1 pj[10] pcr[115] option 0 option 1 option 2 option 3 gpio[115] viu8_pdi6 emios1[17] emios0[11] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 10 10 v4 pj[11] pcr[116] option 0 option 1 option 2 option 3 gpio[116] viu9_pdi7 emios1[15] emios0[10] ?siul viu2/pdi pwm/timer pwm/timer i/o s none, none 11 11 v3 pj[12] pcr[117] option 0 option 1 option 2 option 3 gpio[117] dcu_tag ? dculite_g6 ?siul dcu3 ? dculite i/o m none, none 148 178 a23 pj[13] pcr[118] option 0 option 1 option 2 option 3 gpio[118] quadspi_pcs_b emios1[8] viu5_pdi13 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 149 179 d22 pj[14] pcr[119] option 0 option 1 option 2 option 3 gpio[119] quadspi_clk_b emios1[17] pdi_pclk ?siul quadspi pwm/timer pdi i/o f none, none 150 180 c22 pj[15] pcr[120] option 0 option 1 option 2 option 3 gpio[120] quadspi_io3_b emios1[9] viu6_pdi14 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 151 181 b22 port k pk[0] pcr[121] option 0 option 1 option 2 option 3 gpio[121] emios1[18]] ? ? ?siul pwm/timer ? ? i/o m none, none 155 187 a21 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pk[1] pcr[122] option 0 option 1 option 2 option 3 gpio[122] quadspi_io2_b emios1[14] viu7_pdi15 ?siul quadspi pwm/timer viu2/pdi i/o m none, none 156 188 d20 pk[2] pcr[123] option 0 option 1 option 2 option 3 gpio[123] viu0_pdi8 emios1[10] dculite_tag ?siul viu2/pdi pwm/timer dculite i/o m none, none 31 39 ae3 pk[3] pcr[124] option 0 option 1 option 2 option 3 gpio[124] viu1_pdi9 emios1[11] dculite_de ?siul viu2/pdi pwm/timer dculite i/o m none, none 32 40 af3 pk[4] pcr[125] option 0 option 1 option 2 option 3 gpio[125] viu2_pdi10 emios1[12] dculite_hsync ?siul viu2/pdi pwm/timer dculite i/o m none, none 33 41 ac4 pk[5] pcr[126] option 0 option 1 option 2 option 3 gpio[126] viu3_pdi11 emios1[13] dculite_vsync ?siul viu2/pdi pwm/timer dculite i/o m none, none 34 42 af4 pk[6] pcr[127] option 0 option 1 option 2 option 3 gpio[127] viu4_pdi12 emios1[9] dculite_pclk ?siul viu2/pdi pwm/timer dculite i/o f none, none 35 43 ac5 pk[7] pcr[128] option 0 option 1 option 2 option 3 gpio[128] rxd_2 dculite_r2 tcon[8] ?siul linflex_2 dculite tcon i/o m none, none ?44 ad5 pk[8] pcr[129] option 0 option 1 option 2 option 3 gpio[129] txd_2 dculite_r3 tcon[9] ?siul linflex_2 dculite tcon i/o m none, none ? 45 ae5 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pk[9] pcr[130] option 0 option 1 option 2 option 3 gpio[130] i2s_do / pwmo dculite_r4 tcon[10] ?siul sgm dculite tcon i/o m none, none ?46 af5 pk[10] pcr[131] option 0 option 1 option 2 option 3 gpio[131] sda_1 emios1[12] dculite_tag ?siul i 2 c_1 pwm/timer dculite i/o s none, none 51 59 af8 pk[11] pcr[132] option 0 option 1 option 2 option 3 gpio[132] scl_1 emios1[13] dcu_tag / tcon[3] ?siul i 2 c_1 pwm/timer dcu3 / tcon i/o s none, none 52 60 ac9 pk[12] ? ? reserved ? ? ? ? ? ? ? ? pk[13] ? ? reserved ? ? ? ? ? ? ? ? pk[14] ? ? reserved ? ? ? ? ? ? ? ? pk[15] ? ? reserved ? ? ? ? ? ? ? ? port l pl[0] pcr[133] option 0 option 1 option 2 option 3 gpio[133] ? canrx_1 ? ans[19] siul ? flexcan_1 ? i/o m / analo g none, none ? 81 ae22 pl[1] pcr[134] option 0 option 1 option 2 option 3 gpio[134] ? cantx_1 ? ans[18] siul ? flexcan_1 ? i/o m / analo g none, none ? 82 ae21 pl[2] pcr[135] option 0 option 1 option 2 option 3 gpio[135] ? canrx_0 emios1[22] ans[17] siul ? flexcan_0 pwm/timer i/o s / analo g none, none ?83 af22 pl[3] pcr[136] option 0 option 1 option 2 option 3 gpio[136] ? cantx_0 emios1[23] ans[16] siul ? flexcan_0 pwm/timer i/o s / analo g none, none ?84 af21 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pl[4] pcr[137] option 0 option 1 option 2 option 3 gpio[137] cs2_2 viu5_pdi13 tcon[6] ?siul dspi_2 viu2/pdi tcon i/o m none, none ? 31 ab2 pl[5] pcr[138] option 0 option 1 option 2 option 3 gpio[138] cs1_2 viu6_pdi14 tcon[7] ?siul dspi_2 viu2/pdi tcon i/o m none, none ?32 ac2 pl[6] pcr[139] option 0 option 1 option 2 option 3 gpio[139] cs0_2 viu7_pdi15 emios1[18] ?siul dspi_2 viu2/pdi pwm/timer i/o s none, none ?33 ad1 pl[7] pcr[140] option 0 option 1 option 2 option 3 gpio[140] sin_2 viu8_pdi16 emios1[19] ?siul dspi_2 viu2/pdi pwm/timer i/o s none, none ? 34 ae1 pl[8] pcr[141] option 0 option 1 option 2 option 3 gpio[141] sout_2 viu9_pdi17 emios1[20] ?siul dspi_2 viu2/pdi pwm/timer i/o s none, none ?35 af1 pl[9] pcr[142] option 0 option 1 option 2 option 3 gpio[142] sck_2 pdi_pclk emios1[21] ?siul dspi_2 pdi pwm/timer i/o s none, none ?36 af2 pl[10] pcr[143] option 0 option 1 option 2 option 3 gpio[143] emios1[10] dculite_g2 ? ?siul pwm/timer dculite ? i/o m none, none ? 174 c24 pl[11] pcr[144] option 0 option 1 option 2 option 3 gpio[144] emios1[11] dculite_g3 ? ?siul pwm/timer dculite ? i/o m none, none ? 175 a24 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pl[12] pcr[145] option 0 option 1 option 2 option 3 gpio[145] emios1[12] dculite_g4 ? ?siul pwm/timer dculite ? i/o m none, none ? 176 c23 pl[13] pcr[146] option 0 option 1 option 2 option 3 gpio[146] emios1[13] dculite_g5 ? ?siul pwm/timer dculite ? i/o m none, none ? 177 b23 pl[14] ? ? reserved ? ? ? ? ? ? ? ? pl[15] ? ? reserved ? ? ? ? ? ? ? ? port m pm[0] pcr[147] option 0 option 1 option 2 option 3 gpio[147] i2s_sck / pwmoa dculite_r5 tcon[11] ?siul sgm dculite tcon i/o m none, none ? 61 ae9 pm[1] pcr[148] option 0 option 1 option 2 option 3 gpio[148] i2s_fs dculite_r6 ? ?siul sgm dculite ? i/o m none, none ?62 af9 pm[2] pcr[149] option 0 option 1 option 2 option 3 gpio[149] emios1[17] dculite_r7 dculite_de rsdsclkm siul pwm/timer dculite dculite i/o m none, none ? 173 d23 pm[3] pcr[150] option 0 option 1 option 2 option 3 gpio[150] canrx_2 rxd_3 tcon[4] ?siul flexcan_2 linflex_3 tcon i/o m none, none ?16 y3 pm[4] pcr[151] option 0 option 1 option 2 option 3 gpio[151] cantx_2 txd_3 tcon[5] ?siul flexcan_2 linflex_3 tcon i/o m none, none ?17 y2 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pm[5] pcr[152] option 0 option 1 option 2 option 3 gpio[152] viu5_pdi13 emios1[22] dcu_tag ?siul viu2/pdi pwm/timer dcu3 i/o m none, none 16 ? ? pm[6] pcr[153] option 0 option 1 option 2 option 3 gpio[153] viu6_pdi14 emios1[23] dculite_tag ?siul viu2/pdi pwm/timer dculite i/o m none, none 17 ? ? pm[7] pcr[154] option 0 option 1 option 2 option 3 gpio[154] viu8_pdi16 i2s_do / pwmo emios1[16] ?siul viu2/pdi sgm pwm/timer i/o s none, none 39 ? ? pm[8] pcr[155] option 0 option 1 option 2 option 3 gpio[155] viu9_pdi17 i2s_sck / pwmoa emios1[23] ?siul viu2/pdi sgm pwm/timer i/o s none, none 40 ? ? pm[9] pcr[156] option 0 option 1 option 2 option 3 gpio[156] pdi_pclk sgm_mclk emios0[8] ?siul pdi sgm pwm/timer i/o m none, none 113 ? ? pm[10] pcr[157] option 0 option 1 option 2 option 3 gpio[157] rxd_2 canrx_2 emios0[16] ?siul linflex_2 flexcan_2 pwm/timer i/o s none, none 114 ? ? pm[11] pcr[158] option 0 option 1 option 2 option 3 gpio[158] txd_2 cantx_2 emios0[23] ?siul linflex_2 flexcan_2 pwm/timer i/o s none, none 115 ? ? pm[12] pcr[159] option 0 option 1 option 2 option 3 gpio[159] dculite_b7 ? i2s_sck / pwmoa ?siul dculite ? sgm i/o m none, none ? ? l24 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pm[13] pcr[160] option 0 option 1 option 2 option 3 gpio[160] dculite_pclk ? sgm_mclk ?siul dculite ? sgm i/o f none, none ? ? l23 pm[14] ? ? reserved ? ? ? ? ? ? ? ? pm[15] ? ? reserved ? ? ? ? ? ? ? ? port n pn[0] pcr[161] option 0 option 1 option 2 option 3 gpio[161] dculite_hsync ? tcon[4] ?siul dculite ? tcon i/o m none, none ?? ac3 pn[1] pcr[162] option 0 option 1 option 2 option 3 gpio[162] dculite_vsync ? tcon[5] ?siul dculite ? tcon i/o m none, none ?? ad3 pn[2] pcr[163] option 0 option 1 option 2 option 3 gpio[163] dculite_r0 rxd_2 viu0_pdi8 ?siul dculite linflex_2 viu2/pdi i/o m none, none ?? ac10 pn[3] pcr[164] option 0 option 1 option 2 option 3 gpio[164] dculite_r1 txd_2 viu1_pdi9 ?siul dculite linflex_2 viu2/pdi i/o m none, none ?? af10 pn[4] pcr[165] option 0 option 1 option 2 option 3 gpio[165] dculite_r2 ? tcon[6] ?siul dculite ? tcon i/o m none, none ?? ac11 pn[5] pcr[166] option 0 option 1 option 2 option 3 gpio[166] dculite_r3 ? tcon[7] ?siul dculite ? tcon i/o m none, none ?? ad11 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pn[6] pcr[167] option 0 option 1 option 2 option 3 gpio[167] dculite_r4 ? tcon[8] ?siul dculite ? tcon i/o m none, none ? ? ae11 pn[7] pcr[168] option 0 option 1 option 2 option 3 gpio[168] dcu_lite_r5 ? tcon[9] ?siul dculite ? tcon i/o m none, none ?? af11 pn[8] pcr[169] option 0 option 1 option 2 option 3 gpio[169] dculite_r6 ? tcon[10] ?siul dculite ? tcon i/o m none, none ?? ac12 pn[9] pcr[170] option 0 option 1 option 2 option 3 gpio[170] dculite_r7 ? tcon[11] ?siul dculite ? tcon i/o m none, none ?? ad12 pn[10] pcr[171] option 0 option 1 option 2 option 3 gpio[171] dculite_g0 rxd_3 viu2_pdi10 ?siul dculite linflex_3 viu2/pdi i/o m none, none ? ? ae12 pn[11] pcr[172] option 0 option 1 option 2 option 3 gpio[172] dculite_g1 txd_3 viu3_pdi11 ?siul dculite linflex_3 viu2/pdi i/o m none, none ?? af12 pn[12] pcr[173] option 0 option 1 option 2 option 3 gpio[173] dculite_g2 ? emios0[17] ?siul dculite ? pwm/timer i/o m none, none ?? r26 pn[13] pcr[174] option 0 option 1 option 2 option 3 gpio[174] dculite_g3 ? emios0[18] ?siul dculite ? pwm/timer i/o m none, none ?? r25 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pn[14] pcr[175] option 0 option 1 option 2 option 3 gpio[175] dculite_g4 ? emios0[19] ?siul dculite ? pwm/timer i/o m none, none ?? p26 pn[15] pcr[176] option 0 option 1 option 2 option 3 gpio[176] dculite_g5 ? emios0[20] ?siul dculite ? pwm/timer i/o m none, none ?? p24 port p pp[0] pcr[177] option 0 option 1 option 2 option 3 gpio[177] dculite_g6 ? emios0[21] ?siul dculite ? pwm/timer i/o m none, none ?? p23 pp[1] pcr[178] option 0 option 1 option 2 option 3 gpio[178] dculite_g7 ? emios0[22] ?siul dculite ? pwm/timer i/o m none, none ?? n26 pp[2] pcr[179] option 0 option 1 option 2 option 3 gpio[179] dculite_b0 canrx_2 viu4_pdi12 ?siul dculite flexcan_2 viu2/pdi i/o m none, none ?? n25 pp[3] pcr[180] option 0 option 1 option 2 option 3 gpio[180] dculite_b1 cantx_2 pdi_de ?siul dculite flexcan_2 pdi i/o m none, none ?? n23 pp[4] pcr[181] option 0 option 1 option 2 option 3 gpio[181] dculite_b2 ? emios0[11] ?siul dculite ? pwm/timer i/o m none, none ?? m26 pp[5] pcr[182] option 0 option 1 option 2 option 3 gpio[182] dculite_b3 ? emios0[13] ?siul dculite ? pwm/timer i/o m none, none ?? m25 table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-3 pp[6] pcr[183] option 0 option 1 option 2 option 3 gpio[183] dculite_b4 ? emios0[15] ?siul dculite ? pwm/timer i/o m none, none ?? m24 pp[7] pcr[184] option 0 option 1 option 2 option 3 gpio[184] dculite_b5 ? i2s_fs ?siul dculite ? sgm i/o m none, none ?? m23 pp[8] ? ? reserved ? ? ? ? ? ? ? ? pp[9] ? ? reserved ? ? ? ? ? ? ? ? pp[10] ? ? reserved ? ? ? ? ? ? ? ? pp[11] ? ? reserved ? ? ? ? ? ? ? ? pp[12] ? ? reserved ? ? ? ? ? ? ? ? pp[13] ? ? reserved ? ? ? ? ? ? ? ? pp[14] ? ? reserved ? ? ? ? ? ? ? ? pp[15] ? ? reserved ? ? ? ? ? ? ? ? 1 alternate functions are chosen by setting the values of the pcr[pa] bitfields inside the siul module. pcr[pa] = 00 selects option 0 pcr[pa] = 01 selects option 1 pcr[pa] = 10 selects option 2 pcr[pa] = 11 selects option 3 this is intended to select the output functions. to use one of the input functions, the pcr[ibe] bit must be written to ?1?, re gardless of the values selected in the pcr[pa] bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 special functions are enabled independently from the standard di gital pin functions. enabling standard i/o functions in the pcr registers may interfere with their functionality. adc functions are enabled using the pcr[apc] bit; other functions are enabled by enabling the respective m odule. 3 using the psmi registers in the system integr ation unit lite (siul), different pads can be multiplexed to the same peripheral i nput. please see the siul chapter of the pxd20 microcontroller reference manual for details. 4 see the ?pad types? section for an explanation of the letters in this column. 5 reset configuration is given as i/o direction and pull, e.g., ?input, pullup?. 6 out of reset pins ph[0:3] are available as jtag pins (tck, tdi, td o and tms respectively). it is up to the user to configure pi ns ph[0:3] when needed. table 5. port pin summary (continued) port pin pcr alternate function 1 function special function 2 peripheral 3 i/o direction pad type 4 reset config 5 pin number 176 lqfp 208 lqfp 416 tepbga
pxd20 microcontroller reference manual, rev. 1 3-40 freescale semiconductor preliminary?subject to change without notice table 3-6. pad type descriptions 1 1 the pad descriptions refer to the different pad configuratio n register (pcr) types. refer to the siul chapter in the device reference manual for the features available for each pad type. abbreviation description f fast (pad with slew rate) j fast / medium / slow / i/o pad with analog feature (gpio and analog functionality) m medium (pad with slew rate control) m / rsds medium (pad with slew rate cont rol) shared with rsds alternate function s slow (pad with slew rate control) smd stepper motor driver (pad with reduced slew rate control) x oscillator
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-1 preliminary?subject to change without notice chapter 4 safety 4.1 register protection 4.1.1 introduction 4.1.1.1 overview the register protection m odule offers a mechanism to protect de fined memory-mapped address locations in a module under protectio n from being written. the address locations that can be protected are module-specific. the protection module is located be tween the module under protection and the pbridge. this is shown in figure 4-1 . figure 4-1. register protection block diagram 4.1.1.2 features the register protection include s these distinctive features: ? restrict write accesses for the module under protection to supervisor mode only ? lock registers for first 6 kb of memory-mapped address space ? address mirror automatically sets corresponding lock bit pbridge supervisor access / lock registers module under protection protection module write data address / access size uaa hlb gcr access allowed? peripheral enable other control signals peripheral enable
pxd20 microcontroller reference manual, rev. 1 4-2 freescale semiconductor preliminary?subject to change without notice ? once configured lock bits can be protected from changes 4.1.1.3 modes of operation the register protection module is operable when the mo dule under protection is operable. for further details about the availabili ty please see the module?s chapter in this document. 4.1.2 external signal description there are no external signals. 4.1.3 memory map and register description this section provides a detailed de scription of the memory map of a module usi ng the register protection. the original 16 kb module memory space is divided into five areas as shown in figure 4-2 . figure 4-2. register protection memory diagram area 1 is 6 kb large and hol ds the normal functional m odule registers and is transp arent for all read/write operations. area 2 is 2 kb starting at address 0x1800 is a reserved area, which shall not be accessed. area 3 is 6 kb large, starting at address 0x2000 and is a mirror of area 1. a r ead/write access to these 0x2000+x addresses will read/write the register at address x. as a side effect, a write access to address 0x2000+x will set the optional soft lock bits for this address x in the same cycle as th e register at address x is written. not all registers in ar ea 1 need to have protection defined by associated soft lock bits. for module register space base + 0x0000 6kb 2 kb reserved mirror module register space 6kb 1.5 kb lock bits with user defined base + 0x1800 base + 0x2000 base + 0x3800 soft locking function 512 bytes configuration base + 0x3e00 base + 0x3fff area 1 area 2 area 3 area 4 area 5
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-3 preliminary?subject to change without notice unprotected registers at address y, accesses to address 0x2000+y will be identical to accesses at address y. only for registers implemented in area 1 and defined as protectable soft lock bits will be available in area 4. area 4 is 1.5 kb large and holds the soft lock bits, one bit per byte in area 1. th e four soft lock bits associated with one module regist er word are arranged at byte boundaries in the memory map. the soft lock bit registers can be dir ectly written using a bit mask. area 5 is 512 bytes large and holds the configurat ion bits of the protection mode. there is one configuration hard lock bit per module that prevents all furthe r modifications to the so ft lock bits and can only be cleared by a system reset once set. the other bi ts, if set, will allow us er access to the protected module. if any locked byte is accessed with a write transaction, a transf er error will be issued to the system and the write transaction will not be ex ecuted. this is true even if not all accessed bytes are locked. accessing unimplemented 32-bit regi sters in areas 4 and 5 will re sult in a transfer error. 4.1.3.1 memory map table 4-1 gives an overview on the register protection registers implemented. note reserved registers in area #2 will be handled according to the protected ip (module under protection). table 4-1. register protection memory map address offset register name location 0x0000 module register 0 (mr0) on page 4-4 0x0001 module register 1 (mr1) on page 4-4 0x0002 module register 2 (mr2) on page 4-4 0x0003 - 0x17ff module register 3 (mr3) - module register 6143(mr6143) on page 4-4 0x1800 - 0x1fff reserved 0x2000 module register 0 (mr0) + set soft lock bit 0 (lmr0) on page 4-4 0x2001 module register 1 (mr1) + set soft lock bit 1 (lmr1) on page 4-4 0x2002 - 0x37ff module register 2 (mr2) + set soft lock bit 2 (lmr2) - module register 6143 (mr6143) + set soft lock bit 6143 (lmr6143) on page 4-4 0x3800 soft lock bit register 0 (slbr0): soft lock bits 0-3 on page 4-4 0x3801 soft lock bit register 1 (slbr1): soft lock bits 4-7 on page 4-4 0x3802 - 0x3dff soft lock bit register 2 (slbr2): soft lock bits 8-11 - soft lock bit register 1535 (slbr1535): soft lock bits 6140-6143 on page 4-4 0x3e00 - 0x3ffb reserved 0x3ffc global configur ation register (gcr) on page 4-5
pxd20 microcontroller reference manual, rev. 1 4-4 freescale semiconductor preliminary?subject to change without notice 4.1.3.2 register description this section describes in address order all the regist er protection registers. each description includes a standard register diagram with an associated figure num ber. details of register bi t and field function follow the register diagrams, in bit order. 4.1.3.2.1 module re gisters (mr0-6143) this is the lower 6k module memory space which hold s all the functional registers of the module that is protected by the regist er protection module. 4.1.3.2.2 module regi ster and set soft lock bit (lmr0-6143) this is memory area #3 that provides mirrored acce ss to the mr0-6143 registers with the side effect of setting soft lock bits in case of a write access to a mr that is defined as protectable by the locking mechanism. each mr is protectable by one associated bit in a slbr n .slb m , according to the mapping described in table 4-2 . 4.1.3.2.3 soft lock bit register (slbr0-1535) these registers hold the soft lock bits fo r the protected registers in memory area #1. figure 4-3. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit address 0x3800-0x3dff access: read always supervisor write 0 1 2 3 4 5 6 7 r 0 0 0 0 slb0 slb1 slb2 slb3 w we0 we1 we2 we3 reset 0 0 0 0 0 0 0 0 figure 4-4. soft lock bit register (slbr n )
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-5 preliminary?subject to change without notice table 4-3 gives some examples of how slbr n .slb and mr n go together: 4.1.3.2.4 global configur ation register (gcr) this register is used to make global confi gurations related with the register protection. table 4-2. slbr n field descriptions field description we0 we1 we2 we3 write enable bits for soft lock bits (slb): we0 enables writing to slb0 we1 enables writing to slb1 we2 enables writing to slb2 we3 enables writing to slb3 1 value is written to slb 0 slb is not modified slb0 slb1 slb2 slb3 soft lock bits for one mr n register: slb0 can block accesses to mr[ n *4 + 0] slb1 can block accesses to mr[ n *4 + 1] slb2 can block accesses to mr[ n *4 + 2] slb3 can block accesses to mr[ n *4 + 3] 1 associated mr n byte is locked against write accesses 0 associated mr n byte is unprotected and writable table 4-3. soft lock bits vs. protected address soft lock bit protected address slbr0.slb0 mr0 slbr0.slb1 mr1 slbr0.slb2 mr2 slbr0.slb3 mr3 slbr1.slb0 mr4 slbr1.slb1 mr5 slbr1.slb2 mr6 slbr1.slb3 mr7 slbr2.slb0 mr8 ... ...
pxd20 microcontroller reference manual, rev. 1 4-6 freescale semiconductor preliminary?subject to change without notice note the gcr.uaa bit has no effect on the allowed access modes for the registers in the register protection module. 4.1.4 functional description 4.1.4.1 general this module provides a generic regist er (address) write-prot ection mechanism. the protection size can be: ? 32-bit (address == multiples of 4) ? 16-bit (address == multiples of 2) ? 8-bit (address == multiples of 1) ? unprotected (address == multiples of 1) which addresses are protected and the protection size depend on the soc and/or module. therefore this section can just give examples fo r various protecti on configurations. for all addresses that are protected there are slbr n .slb m bits that specify whether the address is locked. when an address is locked it can only be read but not written in any mode (s upervisor/normal). if an address is unprotected the corresponding slbr n .slb m bit is always 0b0 no matt er what software is writing to. address: 0x3ffc access: re ad always supervisor write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hl b 0 0 0 0 0 0 0 u a a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 4-5. global configuration register (gcr) table 4-4. gcr field descriptions field description hlb hard lock bit. this register can not be cleared once it is set by software. it can only be cleared by a system reset. 1 all slb bits are write prot ected and can not be modified 0 all slb bits are accessible and can be modified. uaa user access allowed. 1 the registers in the module under protection can be accessed in the user mode without any additional restrictions. 0 the registers in the module under protection can only be written in supervisor mode. all write accesses in non-supervisor mode are not execut ed and a transfer error is issued. this access restriction is in addition to any access restrictions imposed by the protected ip module.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-7 preliminary?subject to change without notice 4.1.4.2 change lock settings to change the setting whether an address is locked or unlocked the corresponding slbr n .slb m bit needs to be changed. this can be done using the following methods: ? modify the slbr n .slb m directly by writing to area #4 ? set the slbr n .slb m bit(s) by writing to the mirror module space (area #3) both methods are explained in the following sections. 4.1.4.2.1 change lock sett ings directly via area #4 in memory area #4 the lock bits are located. they can be modified by wr iting to them. each slbr n .slb m bit has a mask bit slbr n .we m which protects it from being modified. this masking makes clear-modify-write op erations unnecessary. figure 4-6 shows two modification examples . in the left example there is a write access to the slbr n register specifying a mask value wh ich allows modifi cation of all slbr n .slb m bits. the example on the right specifies a mask which only al lows modification of the bits slbr n .slb[3:1]. figure 4-6. change lock settings directly via area #4 figure 4-6 showed four registers that ca n be protected 8-bit wise. in figure 4-7 registers with 16-bit protection and in figure 4-8 registers with 32-bit protection are shown: figure 4-7. change lock settings for 16-bit protected addresses on the right side of figure 4-7 it is shown that the data written to slbr n .slb[0] is automatically written to slbr n .slb[1] also. this is done as the address reflected by slbr n .slb[0] is protected 16-bit wise. 1 slb3 slb2 slb1 slb0 slbr n .we[3:0] slbr n .slb[3:0] slb3 slb2 slb1 slb0 slbr n .slb[3:0] change allowed to slb3 write data to slb2 to slb1 to slb0 1 1 1 1slbr n .we[3:0] to slb3 write data to slb2 to slb1 to slb0 1 1 0 change allowed slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x1x slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x00
pxd20 microcontroller reference manual, rev. 1 4-8 freescale semiconductor preliminary?subject to change without notice note that in this case the write enable slbr n .we[0] must be set while slbr n .we[1] does not matter. as the enable bits slbr n .we[3:2] are cleared the lock bits slbr n .slb[3:2] remain unchanged. in the example on the left side of figure 4-7 the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] and the data written to slbr n .slb[2] is mirrored to slbr n .slb[3] as for both registers the write enables are set. in figure 4-8 a 32-bit wise protected re gister is shown. when slbr n .we[0] is set the data written to slbr n .slb[0] is automatically written to slbr n .slb[3:1] also. otherwise slbr n .slb[3:0] remains unchanged. figure 4-8. change lock settings for 32-bit protected addresses in figure 4-9 an example is shown which has a mixed protection si ze configuration: figure 4-9. change lock settings for mixed protection the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] as the corresponding register is 16-bit protected. the data written to slbr n .slb[2] is blocked as the corresponding regist er is unprotected. the data written to slbr n .slb[3] is written to slbr n .slb[3]. 4.1.4.2.2 enable locking via mir ror module space (area #3) it is possible to enable locking for a register after writing to it. to do so the mirrored module address space must be used. figure 4-10 shows one example: 1 slb0 slb1 slb2 slb3 slbr n .we[3:0] slbr.slb[3:0] update lock bits to slb0 write data to slb1 to slb2 to slb3 xxx slb0 slb1 0 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 xx1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-9 preliminary?subject to change without notice figure 4-10. enable locking via mirror module space (area #3) when writing to address 0x0008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits rema in unchanged (left part of figure 4-7 ). when writing to address 0x2008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits slbr2.slb[1 :0] are set while the lock bits slbr2.slb[3:2] remain unchanged (right part of figure 4-7 ). figure 4-11 shows an example where some addres ses are protected and some are not: figure 4-11. enable locking for protected and unprotected addresses in the example in figure 4-11 addresses 0x0c and 0x0d are unprotect ed. therefore their corresponding lock bits slbr3.slb[1:0] are always 0b0 (shown in bold). when doing a 32-bit write access to address 0x200c only lock bits slbr3.slb[3:2] are set while bits slbr3.slb[1:0] stay 0b0. note lock bits can only be set via writes to the mirror module space. reads from the mirror module space will not change the lock bits. 4.1.4.2.3 write protect ion for locking bits changing the locking bits through any of the procedures mentioned in section 4.1.4.2.1, change lock settings directly via area #4 , and section 4.1.4.2.2, enable locking via mirror module space (area #3) , is only possible as long as the bit gcr.hlb is cleared. once this bit is set the locking bits can no longer be modified until ther e was a system reset. 4.1.4.3 access errors the protection module generates tran sfer errors under several circumst ances. for the area definition refer to figure 4-2 . 1. if accessing area #1 or area #3, the protection m odule will pass on any access error from the underlying module under protection. slbr 2 we[3:0] 00000000 slb[3:0] 16-bit write to address 0x0008 no change write to mr[9:8] slbr 2 we[3:0] 00001100 slb[3:0] 16-bit write to address 0x2008 set lock bits write to mr[9:8] slbr 3 we[3:0] 0000 00 00 slb[3:0] before write access slbr 3 we[3:0] 0000 00 11 slb[3:0] 32-bit write to address 0x200c set lock bits write to mr[15:12] after write access
pxd20 microcontroller reference manual, rev. 1 4-10 freescale semiconductor preliminary?subject to change without notice 2. if user mode is not allowed, user writes to all ar eas will assert a transfer error and the writes will be blocked. 3. if accessing the reserved area #2, a transfer error will be asserted. 4. if accessing unimplemented 32-bit registers in area #4 and area #5 a transfer error will be asserted. 5. if writing to a register in area #1 and area #3 with soft lock bit set for any of the affected bytes a transfer error is asserted and the write will be blocked. also the comp lete write operation to non-protected bytes in th is word is ignored. 6. if writing to a soft lock register in area #4 with the hard lock bit being set a transfer error is asserted. 7. any write operation in any access mode to area #3 wh ile hard lock bit gcr.hl b is set will result in a transfer error. 4.1.5 reset the reset state of each individu al bit is shown within the regi ster descripti on section (see section 4.1.3.2, register description ). in summary, after reset, locking for all mr n registers is disabled. the registers can be accessed in supervisor mode only. 4.2 software watchdog timer (swt) 4.2.1 overview the software watchdog timer (swt) is a peripheral module that can prev ent system lockup in situations such as software getting trapped in a loop or if a bus transa ction fails to terminate. when enabled, the swt requires periodic execution of a watchdog servicing sequ ence. writing the sequence resets the timer to a specified time-out period. if this servicing action does not occur be fore the timer expires the swt generates an interrupt or ha rdware reset. the swt can be configured to generate a reset or interrupt on an initial time-out, a reset is always ge nerated on a second consecutive time-out. the swt provides a window functionality. when this functionality is program med, the servicing action should take place within the defined window. when oc curring outside the defined period, the swt will generate a reset. 4.2.2 features the swt has the following features: ? 32-bit time-out register to set the time-out period ? the unique swt counter clock is the undivided low power internal oscillator (irc 128 khz), no other clock source can be selected ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out ? master access protection ? hard and soft configuration lock bits
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-11 preliminary?subject to change without notice ? the swt is started on phase1 exit and counts unconditionally dur ing phase2 to monitor flash boot sequence. swt is held in re set during phase3 but can start again at phase3 exit depending on the value of the shadow flash c onfiguration bit nvusr0[watchdog_en]. 4.2.3 modes of operation when enabled, the swt is always active in all modes except standby when it is always disabled and stop when it may be disabled by the swt_cr[stp] bi t. if the stp bit is set, the counter is stopped in stop mode, otherwise it continues to run. on exit from stop mode, th e swt will continue from the state it was before entering stop mode. to simplify software development it is possible to temporarily suspend the swt counter while the mcu is stopped by a debugger. while the mcu is running th e swt counter runs normally. this feature is enabled by setting the swt_cr[frz] bit and is only available when the cpu ha s debug mode active (see the cpu reference manual for more in formation on debug mode and support). software watchdog is not availabl e in standby mode. as soon as out of standby mode, the swt behaves as in a usual ?out of reset? situation. figure 4-12 shows the operation timing diagram of the swt. table 4-5 describes the swt operation after reset. figure 4-12. swt operation timing diagram table 4-5. swt operation after reset swt_cr [wen] mcu mode cpu debug active swt_cr [frz] swt_cr [stp] swt operation 0 ? no 0 or 1 0 or 1 off mc_me mode reset phases swt status swt_cr[wen] reset drun drun idle phase0 phase1 phase2 phase3 disabled enabled disabled enabled if wen = 1 (see note 1) see note 2 notes: 1) the swt is started on phase1 exit and counts unconditionally during phase2 to monitor the flash memory boot sequence. 2) value copied from configuration bit nvusr0[watchdog_en] in the shadow flash memory (software can modify it later)
pxd20 microcontroller reference manual, rev. 1 4-12 freescale semiconductor preliminary?subject to change without notice 4.2.4 external signal description the swt module does not have a ny external interface signals. 4.2.5 memory map and register description the swt programming model has six 32-bit register s. the programming model can only be accessed using 32-bit (word) accesses. references using a differ ent size are invalid. other types of invalid accesses include: writes to read only regist ers, incorrect values written to the service register when enabled, accesses to reserved addr esses and accesses by master s without permission. if th e ria bit in the swt_cr is set then the swt generates a system reset on an invalid access otherwise a bus error is generated. if either the hlk or slk bits in the swt_cr are set then the swt_ cr, swt_to and swt_wn registers are read only. 4.2.5.1 memory map the swt memory map is shown in table 4-6 . 1 normal (mc_me modes drun, run0:3, halt, safe) no 0 or 1 0 or 1 running debug 1 (mc_me modes drun, run0:3, halt, safe) yes 0 0 or 1 running yes 1 0 or 1 halted stop (mc_me mode stop) no 0 or 1 0 running no 0 or 1 1 halted 0 or 1 standby no no no off 1 swt debug mode occurs when the processor is stopped due to user specified debug criteria such as breakpoint. table 4-6. swt memory map address offset register name location 0x0000 swt control register (swt_cr) on page 4-13 0x0004 swt interrupt register (swt_ir) on page 4-14 0x0008 swt time-out register (swt_to) on page 4-15 0x000c swt window register (swt_wn) on page 4-15 0x0010 swt service register (swt_sr) on page 4-16 0x0014 swt counter outp ut register (swt_co) on page 4-16 0x0018? 0x3fff reserved table 4-5. swt operation after reset (continued) swt_cr [wen] mcu mode cpu debug active swt_cr [frz] swt_cr [stp] swt operation
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-13 preliminary?subject to change without notice 4.2.6 register summary the following sections detail the individua l registers within the swt programming model. 4.2.6.1 swt control register (swt_cr) the swt_cr contains fields for configuring and controlli ng the swt. this register is read only if either the swt_cr.hlk or swt_cr.slk bits are set. the swt_cr reset value is 0x8000_011a or 0x800 0_011b, corresponding to map0 = 1 (only cpu access allowed), ria = 1 (reset on invalid swt access) , slk = 1 (soft lock), csl = 1 (irc clock source for counter), frz = 1 (freeze available while debuggi ng), wen = 0 or 1 (copied from configuration bit nvusr0[watchdog_en]). offset 0x0000 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r map 0 map 1 map 2 map 3 000000000 0 00 w reset 1000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 ria wnd itr hlk slk csl stp frz wen w reset 0000000100011 0 1see note note: swt_cr[wen] value is copied from configur ation bit nvusr0[watchdog_en] during reset figure 4-13. swt control register (swt_cr) table 4-7. swt_cr field descriptions field description mapn master access protection for ma ster n. the platform bus master assignments are device specific. 0 = access for the master is not enabled 1 = access for the master is enabled ria reset on invalid access. 0 = invalid access to the swt generates a bus error 1 = invalid access to the swt causes a system reset if wen=1 wnd window mode. 0 = regular mode, service sequence can be done at any time 1 = windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. itr interrupt then reset. 0 = generate a reset on a time-out 1 = generate an interrupt on an initial time-out, reset on a second consecutive time-out
pxd20 microcontroller reference manual, rev. 1 4-14 freescale semiconductor preliminary?subject to change without notice 4.2.6.2 swt interrupt register (swt_ir) the swt_ir contains the time-out interrupt flag. hlk hard lock. this bit is only cleared at reset. 0 = swt_cr, swt_to and swt_wn are read/write registers if slk=0 1 = swt_cr, swt_to and swt_wn are read only registers slk soft lock. this bit is cleared by writing the unlock sequence to the service register. 0 = swt_cr, swt_to and swt_wn are read/write registers if hlk=0 1 = swt_cr, swt_to and swt_wn are read only registers csl clock selection. selects the lp irc 128 khz oscillator clock that drives the internal timer. csl bit can be written.the status of the bit has no effect on counter clock selection on this device. 0 = system clock. (not applicable on this device) 1 = oscillator clock. stp stop mode control. allows the watchdog timer to be stopped when the device enters stop mode. 0 = swt counter continues to run in stop mode 1 = swt counter is stopped in stop mode frz freeze available during debug. this function is only operational when the cpu is in an active debug mode. 0 = swt counter continues to run independent of the cpu status 1 = swt counter is stopped when the cpu is stopped by a debugger wen watchdog enabled. 0 = swt is disabled 1 = swt is enabled offset 0x0004 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000 0 00 w reset 0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 00 00000 tif w reset 0000000000000 0 00 figure 4-14. swt interrupt register (swt_ir) table 4-7. swt_cr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-15 preliminary?subject to change without notice 4.2.6.3 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32-bi t time-out period. this re gister is read-only if either the swt_cr.hlk or swt_cr.slk bits are set. figure 4-15. swt time-out register (swt_to) the default counter value (swt_to_rst) is 1920 (0x0000_0780 hexadecimal) which corresponds to 15 ms with a 128 khz clock. 4.2.6.3.1 swt window register (swt_wn) the swt window (swt_wn) register c ontains the 32-bit window start valu e. this register is cleared on reset. this register is read only if either the swt_cr.hlk or swt_cr.slk bits are set. table 4-8. swt_ir field descriptions field description tif time-out interrupt flag. the flag and interrupt are cleared by writing a 1 to this bit. writing a 0 has no effect. 0 = no interrupt request. 1 = interrupt request due to an initial time-out. offset 0x008 access: read/write 012345678910111213141516171819202122232425262728293031 r wto w reset 00000000000000000000011110000000 table 4-9. swt_to register field descriptions field description wto watchdog time-out period in clock cycles. an internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service sequ ence is written or when the swt is enabled. offset 0x00c access: read/write 012345678910111213141516171 8 19 20 21 22 23 24 25 26 27 28 29 30 31 r wst w reset 00000000000000000000000000000000 figure 4-16. swt window register (swt_wn)
pxd20 microcontroller reference manual, rev. 1 4-16 freescale semiconductor preliminary?subject to change without notice 4.2.6.3.2 swt servi ce register (swt_sr) the swt time-out (swt_sr) service register is the target for servic e sequence writes used to reset the watchdog timer. 4.2.6.3.3 swt counter ou tput register (swt_co) the swt counter output (swt_co) regi ster is a read only register that shows the value of the internal down counter when the swt is disabled. table 4-10. swt_wn regi ster field descriptions field description wst window start value. when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. offset 0x010 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w wsc reset 00000000000000000000000000000000 figure 4-17. swt service register (swt_sr) table 4-11. swt_sr field descriptions field description wsc watchdog service code.this field is used to service the watchdog and to clear the soft lock bit (swt_cr.slk). to service the watchdog, the value 0xa602 followed by 0xb480 is written to the wsc field. to clear the soft lock bit (swt_cr.slkswt_cr.), the value 0xc520 followed by 0xd928 is written to the wsc field. offset 0x014 access: read only 012345678910111213141516171 8 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt w reset 00000000000000000000000000000000 figure 4-18. swt counter output register (swt_co)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 4-17 preliminary?subject to change without notice 4.2.7 functional description the swt is a 32-bit timer desi gned to enable the system to recover in situations such as software getting trapped in a loop or if a bus transact ion fails to terminate. it includes a a control register (swt_cr), an interrupt register (swt_ir), time -out register (swt_to), a window register (swt_wn), a service register (swt_sr) and a counter output regist er (swt_co). the swt_cr includes bits to enable the timer, set c onfiguration options and lo ck configuration of the module. the watchdog is enabled by setting th e swt_cr.wen bit. the reset value of the swt_cr.wen bit is 0 when exiting reset mode if the flash user option bit 31 (watchdog_en) is ?0?. if the reset value of watchdog_en is 1, th e swt_cr.wen bit is se t and the watchdog starts operation automatically after reset is released. the swt_to register holds the watc hdog time-out period in clock cycles unless the value is less than 0x100 in which case the time-out period is set to 0x100. th is time-out period is loaded into an internal 32-bit down counter when the swt is enabled and e ach time a valid service sequence is written. the swt_cr.csl bit selects which clock (system or os cillator) is used to drive the down counter. the configuration of the swt can be lo cked through use of either a soft lock or a hard lock. in either case, when locked the swt_cr, swt_to and swt_wn regist ers are read only. the hard lock is enabled by setting the swt_cr.hlk bit which can only be cleared by a reset. th e soft lock is enabled by setting the swt_cr.slk bit and is cleared by writing the unloc k sequence to the service register. the unlock sequence is a write of 0xc520 followed by a write of 0xd928 to the swt_sr.wsc field. there is no timing requirement between the two writes. the unlock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 seque nce regardless of previous writ es. the unlock sequence can be written at any time and does not requi re the swt_cr.wen bit to be set. when enabled, the swt requires periodic execution of the watchdog servicing sequence. the service sequence is a write of 0xa602 followed by a write of 0xb480 to the swt_sr.wsc field. writing the service sequence loads the internal down counter with the time-out pe riod. there is no timing requirement between the two writes. the servic e sequence logic ignores unlock se quence writes and recognizes the 0xa602, 0xb480 sequence regardless of previous writ es. accesses to swt registers occur with no peripheral bus wait states. (the peri pheral bus bridge may add one or more system wait states.) however, due to synchronization logic in the swt design, rec ognition of the service se quence or configuration changes may require up to three system plus seven counter clock cycles. if window mode is enabled (swt_cr. wnd bit is set), the se rvice sequence must be performed in the last part of the time-out period define d by the window register. the window is open when the down counter is less than the value in the swt_wn register. outside of this window, service se quence writes are invalid table 4-12. swt_co register field descriptions field description cnt watchdog count. when the watchdog is disabled (s wt_cr.wenswt_cr.=0) this field shows the value of the internal down counter. when the watchdog is enabled the value of this field is 0x0000_0000. values in this field can lag behind the inte rnal counter value for up to six s ystem plus eight counter clock cycles. therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter.
pxd20 microcontroller reference manual, rev. 1 4-18 freescale semiconductor preliminary?subject to change without notice accesses and generate a bus error or reset depending on the value of the swt_cr.ria bit. for example, if the swt_to register is set to 5000 and swt_wn register is set to 1000 then th e service sequence must be performed in the last 20% of the time-out period. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay c ould be up to three system plus four counter clock cycles. the interrupt then reset bit (swt_cr.itr) controls the action taken when a time-out occurs. if the swt_cr.itr bit is not set, a reset is generated immediately on a time-out. if the sw t_cr.itr bit is set, an initial time-out causes the swt to generate an interrupt a nd load the down counter with the time-out period. if the service sequen ce is not written before the second c onsecutive time-out, the swt generates a system reset. the interrupt is indicated by the time-out interrupt flag (s wt_ir.tif). the interrupt request is cleared by writing a one to the swt_ir.tif bit. the swt_co register shows the va lue of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter for up to six syst em plus eight counter clock cycles. the swt_co can be used during a so ftware self test of the swt. fo r example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_cr.wen cleared) and the value of the swt_co re ad to determine if the internal down counter is working properly.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-1 preliminary?subject to change without notice chapter 5 analog-to-digital converter (adc) 5.1 overview 5.1.1 device-specific features ? 10-bit resolution ? 20 channels, expandable to 27 cha nnels via external multiplexing ? minimum conversion time of 1 s ? conversion triggering sources: ?software ? pit channel 2 (used to trigger normal conversion) ? pit channel 3 (used to trigger injection conversion) ? two different sampling and conversion time regi sters ctr[1:2] (extended internal channels, external channels) ? as many as 23 data registers for storing converted data. conversion information, such as mode of operation (normal, injected), is associated to data value. ? conversions on external channels managed in th e same way as internal channels, making it transparent to the application ? external decode signals (3 bits) to co ntrol the external analog multiplexers ? one shot/scan modes ? chain injection mode ? hardware-triggered dma transfer requests ? power-down mode ? 2 different abort functions allow to abort eith er single-channel convers ion or chain conversion ? 4 programmable analog watchdogs with interrupt capability ? allows continuous hardware monitoring of as many as 4 analog input channels ? alternate analog thresholds ? auto-clock-off
pxd20 microcontroller reference manual, rev. 1 5-2 freescale semiconductor preliminary?subject to change without notice 5.1.2 device-specific implementation figure 5-1. adc implementation 5.2 introduction the analog-to-digital converter (adc ) block provides accurate and fast conversions for a wide range of applications. an adc analog part has it s corresponding digital interface (adcdig). the adc digital interface c ontains advanced features for normal or injected conversion. an injected conversion can be triggered by soft ware or hardware (pit3). a norma l conversion can be triggered by software or hardware (pit2). there are two types of input channels: ? internal extended, ans (internally mult iplexed standard accuracy channels) ? external, anx (externally multipl exed standard accuracy channels) the mask registers present within the adcdig can be programmed to co nfigure which channel has to be converted. three external decode signals ma[2 :0] (multiplexer addre ss) are provided for exte rnal channel selection and are available as alternate functions on gpio. a conversion timing register for configuring different sampling and c onversion times is as sociated to each channel type. analog watchdogs allow conti nuous hardware monitoring. 16 channels up to 8 extended channels through external mux ch 47 (ans15) ch 42 (ans10) ch 32 (ans0) pit3 ma [2:0] 3 single-ended interrupts eoc, watchdog, ech mux 8 3 digital interface analog switch pit intc d a mux 16 adc system . . . . . . injected trigger /2 adclksel acko system clock pit2 normal trigger
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-3 preliminary?subject to change without notice 5.3 register descriptions 5.3.1 introduction table 5-1 lists the adc registers with thei r address offsets and reset values. table 5-1. adc digital registers address offset (hex) register name location 000 main configuration register (mcr) on page 5-5 004 main status register (msr) on page 5-7 008 .. 00c reserved ? 010 interrupt status register (isr) on page 5-9 014 reserved ? 018 channel pending register (ceocfr1) on page 5-10 01c channel pending register (ceocfr2) on page 5-10 020 interrupt mask register (imr) on page 5-11 024 reserved ? 028 channel interrupt mask register (cimr1) on page 5-12 02c channel interrupt mask register (cimr2) on page 5-12 030 watchdog threshold interrupt status register (wtisr) on page 5-13 034 watchdog threshold interrupt mask register (wtimr) on page 5-14 038 .. 03c reserved ? 040 dma enable register (dmae) on page 5-15 044 reserved ? 048 dma channel select register 1 (dmar1) on page 5-15 04c dma channel select register 2 (dmar2) on page 5-15 050 threshold control register 0 (trc0) on page 5-17 054 threshold control register 1 (trc1) on page 5-17 058 threshold control register 2 (trc2) on page 5-17 05c threshold control register 3 (trc3) on page 5-17 060 threshold register 0 (thrhlr0) on page 5-17 064 threshold register 1 (thrhlr1) on page 5-17 068 threshold register 2 (thrhlr2) on page 5-17 06c threshold register 3 (thrhlr3) on page 5-17 070 .. 094 reserved ? 098 conversion timing register 1 (ctr1) on page 5-18
pxd20 microcontroller reference manual, rev. 1 5-4 freescale semiconductor preliminary?subject to change without notice 09c conversion timing register 2 (ctr2) on page 5-18 0a0 .. 0a4 reserved ? 0a8 normal conversion mask register 1 (ncmr1) on page 5-20 0ac normal conversion mask register 2 (ncmr2) on page 5-20 0b0 .. 0b4 reserved ? 0b8 injected conversion mask register 1 (jcmr1) on page 5-21 0bc injected conversion mask register 2 (jcmr2) on page 5-21 0c0 reserved ? 0c4 decode signals delay register (dsdr) on page 5-22 0c8 power-down exit delay register (pdedr) on page 5-22 0cc .. 17c reserved ? 180 channel 32 data register (cdr32) on page 5-24 184 channel 33 data register (cdr33) on page 5-24 188 channel 34 data register (cdr34) on page 5-24 18c channel 35 data register (cdr35) on page 5-24 190 channel 36 data register (cdr36) on page 5-24 194 channel 37 data register (cdr37) on page 5-24 198 channel 38 data register (cdr38) on page 5-24 19c channel 39 data register (cdr39) on page 5-24 1a0 channel 40 data register (cdr40) on page 5-24 1a4 channel 41 data register (cdr41) on page 5-24 1a8 channel 42 data register (cdr42) on page 5-24 1ac channel 43 data register (cdr43) on page 5-24 1b0 channel 44 data register (cdr44) on page 5-24 1b4 channel 45 data register (cdr45) on page 5-24 1b8 channel 46 data register (cdr46) on page 5-24 1bc channel 47 data register (cdr47) on page 5-24 1c0 channel 48 data register (cdr48) on page 5-24 1c4 channel 49 data register (cdr49) on page 5-24 1c8 channel 50 data register (cdr50) on page 5-24 1cc .. 1fc reserved ? 200 channel 64 data register (cdr64) on page 5-24 204 channel 65 data register (cdr65) on page 5-24 table 5-1. adc digital registers (continued) address offset (hex) register name location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-5 preliminary?subject to change without notice 5.3.2 control logic registers 5.3.2.1 main configuration register (mcr) the main configuration register (mcr) pr ovides configuration settings for the adc. 208 channel 66 data register (cdr66) on page 5-24 20c channel 67 data register (cdr67) on page 5-24 210 channel 68 data register (cdr68) on page 5-24 214 channel 69 data register (cdr69) on page 5-24 218 channel 70 data register (cdr70) on page 5-24 21c channel 71 data register (cdr71) on page 5-24 220 .. 2fc reserved ? table 5-2. bit access descriptions access type description read/write (rw) software can read and write to these bits. read-only (r) software can only read these bits. write-only (w) software can only write to these bits. write 1 to clear (w1c) software can clear bits by writing ?1?. address: base + 0x0000 access: user read/write 0123456789101112131415 r owren wlside mode edglev trgen edge 0 nstart 0 jtrgen jedge jstart 0000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 adclk sel abort chain abort acko 0000 pwdn w reset00000000 00000001 figure 5-2. main configuration register (mcr) table 5-1. adc digital registers (continued) address offset (hex) register name location
pxd20 microcontroller reference manual, rev. 1 5-6 freescale semiconductor preliminary?subject to change without notice table 5-3. main configuration register (mcr) field descriptions bit description 0 owren: overwrite enable this bit enables or disables the functionality to overwrite unread converted data. 0 prevents overwrite of unread converted data; new result is discarded. 1 enables converted data to be overwritten by a new conversion. 1 wlside: write left/right-aligned 0 the conversion data is written right-aligned. 1 data is left-aligned (from 15 to (15 ? resolution + 1)). 2 mode: one shot/scan 0 one shot mode?configures the normal conversion of one chain. 1 scan mode?configures continuous chain conversion mode; when the programmed chain conversion is finished it restarts immediately. 3 edglev: edge or level selection for external start trigger 0 edge configuration for external trigger usage. 1 level configuration for external trigger usage. 4 trgen: external trigger enable. this bit must be set to use external triggering to start a conversion. 0 an external trigger cannot be used to start a conversion. 1 an external trigger can start a conversion. 5 start trigger edge/ level detection. the following table shows the interaction between the edge bit and the trgen and edglev bits. 6reserved must be kept at 0. 7 nstart: normal start conversion setting this bit starts the chain or scan conversion. resetting this bit during scan mode causes the current chain conversion to finish, then stops the operation. this bit stays high while the conversion is ongoing (or pending during injection mode). 0 causes the current chain conversion to finish and stops the operation. 1 starts the chain or scan conversion. 8reserved write of any value has no effect, read value is always 0. 9 jtrgen: injection external trigger enable 0 external trigger disabled for channel injection (injected conversion cannot be started using an external signal). 1 external trigger enabled for channel injection. table 0-1 trgen edglev edge trigger detection 0 n n external triggering disabled 1 0 0 external trigger on falling edge of trigger 1 0 1 external trigger on rising edge of trigger 1 1 0 external trigger on low edge of trigger
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-7 preliminary?subject to change without notice 5.3.2.2 main status register (msr) the main status register (msr) pr ovides status bits for the adc. 10 jedge: injection trigger edge selection edge selection for external trigger, if jtrgen = 1. 0 selects falling edge for the external trigger. 1 selects rising edge for the external trigger. 11 jstart: injection start setting this bit will start the configured injected ana log channels to be converted by software. resetting this bit has no effect, as the injected chain conversion cannot be interrupted. 12:13 reserved write of any value has no effect, read value is always 0. 14 reserved must be kept at 0. 15:22 reserved write of any value has no effect, read value is always 0. 23 adclksel: analog cloc k frequency selector if this bit is set the ad_clk frequency is equal to ipg_clk frequency. otherwise, it is half of ipg_clk frequency. this bit can be written in power-down only. 24 abortchain: abort chain when this bit is set, the ongoing chain conversion is aborted. this bit is reset by hardware as soon as a new conversion is requested. 0 conversion is not affected. 1 aborts the ongoing chain conversion. 25 abort: abort conversion when this bit is set, the ongoing conversion is aborted and a new conversion is invoked. this bit is reset by hardware as soon as a new conversion is invoked. 0 conversion is not affected. 1 aborts the ongoing conversion. 26 acko: auto-clock-off enable if set, this bit enables the auto clock off feature. 0 auto clock off is disabled. 1 auto clock off is enabled. 27:28 reserved must be kept at 0. 29:30 reserved write of any value has no effect, read value is always 0. 31 pwdn: power-down enable when this bit is set, the analog module is requeste d to enter power down mode. when adc status is pwdn, resetting this bit starts adc transition to idle mode. 0 adc is in normal mode. 1 adc has been requested to power down. table 5-3. main configuration register (mcr) field descriptions (continued) bit description
pxd20 microcontroller reference manual, rev. 1 5-8 freescale semiconductor preliminary?subject to change without notice address: base + 0x0004 access: user read-only 0123456789101112131415 r 0000000 n start j abort 00 j start 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chaddr[0:6] 0 00 ack0 0 0 adcstatus[0:2] w reset00000000 00000001 figure 5-3. main status register (msr) table 5-4. main status register (msr) field descriptions field description 0:6 reserved write of any value has no effect, read value is always 0. 7 nstart this status bit is used to signal that a normal conversion is ongoing. 8 jabort this status bit is used to signal that an injected conversion has been aborted. this bit is reset when a new injected conversion starts. 9:10 reserved write of any value has no effect, read value is always 0. 11 jstart this status bit is used to signal that an injected conversion is ongoing. 12:14 reserved write of any value has no effect, read value is always 0. 15 reserved write of any value has no effect, read value is always 0. 16:22 chaddr[0:6]: channel under measure address this status bit is used to signal which channel is under measure. 23:25 reserved write of any value has no effect, read value is always 0. 26 acko: auto-clock-off enable this status bit is used to signal if the auto-clock-off feature is on.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-9 preliminary?subject to change without notice 5.3.3 interrupt registers 5.3.3.1 interrupt status register (isr) the interrupt status register (isr) cont ains interrupt status bits for the adc. 27:28 reserved write of any value has no effect, read value is always 0. 29:31 adcstatus[0:2] the value of this parameter depends on adc status: 000 idle 001 power-down 010 wait state 011 ? 100 sample 101 ? 110 conversion 111 ? address: base + 0x0010 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0000 jeoc jech eoc ech w w1c w1c w1c w1c reset00000000 00000000 figure 5-4. interrupt status register (isr) table 5-5. interrupt status register (isr) field descriptions field description 0:24 reserved write of any value has no effect, read value is always 0. 25:26 reserved write of any value has no effect, read value is always 0. 27 reserved write of any value has no effect, read value is always 0 28 end of injected channel conversion interrupt (jeoc) flag. it is the interrupt of the digital end of conversion for the injected channel; active when set. when this bit is set, a jeoc interrupt has occurred. table 5-4. main status register (m sr) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 5-10 freescale semiconductor preliminary?subject to change without notice 5.3.3.2 channel pending registers (ceocfr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . ceocfr1 = end of conversion pending interrupt for channel 32 to 63 (extended internal channels) ceocfr2 = end of conversion pending interrupt for channel 64 to 95 (external channels) 29 end of injected chain conversion interrupt (jech) fl ag. it is the interrupt of the digital end of chain conversion for the injected channel; active when set. when this bit is set, a jech interrupt has occurred. 30 end of channel conversion interrupt (eoc) flag. it is the interrupt of the digital end of conversion. when this bit is set, an eoc interrupt has occurred. 31 end of chain conversion interrupt (ech) flag. it is the interrupt of the digital end of chain conversion. when this bit is set, an ech interrupt has occurred. address: base + 0x0018 access: user read/write 0123456789101112131415 r eoc_ ch63 eoc_ ch62 eoc_ ch61 eoc_ ch60 eoc_ ch59 eoc_ ch58 eoc_ ch57 eoc_ ch56 eoc_ ch55 eoc_ ch54 eoc_ ch53 eoc_ ch52 eoc_ ch51 eoc_ ch50 eoc_ ch49 eoc_ ch48 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ ch47 eoc_ ch46 eoc_ ch43 eoc_ ch44 eoc_ ch43 eoc_ ch42 eoc_ ch41 eoc_ ch40 eoc_ ch39 eoc_ ch38 eoc_ ch37 eoc_ ch36 eoc_ ch35 eoc_ ch34 eoc_ ch33 eoc_ ch32 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 5-5. channel pending register 1 (ceocfr1) table 5-5. interrupt status register (isr) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-11 preliminary?subject to change without notice 5.3.3.3 interrupt mask register (imr) the interrupt mask register (imr) contains the interrupt enable bits for the adc. address: base + 0x001c access: user read/write 0123456789101112131415 r eoc_ ch95 eoc_ ch94 eoc_ ch93 eoc_ ch92 eoc_ ch91 eoc_ ch90 eoc_ ch89 eoc_ ch88 eoc_ ch87 eoc_ ch86 eoc_ ch85 eoc_ ch84 eoc_ ch83 eoc_ ch82 eoc_ ch81 eoc_ ch80 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ ch79 eoc_ ch78 eoc_ ch77 eoc_ ch76 eoc_ ch75 eoc_ ch74 eoc_ ch73 eoc_ ch72 eoc_ ch71 eoc_ ch70 eoc_ ch69 eoc_ ch68 eoc_ ch67 eoc_ ch66 eoc_ ch65 eoc_ ch64 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000 000000 figure 5-6. channel pending register 2 (ceocfr2) table 5-6. channel pending registers (ceocfr[1..2]) field descriptions field description 31 eoc_ch0 when set, the measure of channel 0 is completed. n eoc_chn when set, the measure of channel n is completed. address: base + 0x0020 acc ess: user read/write 0123456789101112131415 r0000000 0 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0000 msk jeoc msk jech msk eoc msk ech w reset00000000 00000000 figure 5-7. interrupt mask register (imr)
pxd20 microcontroller reference manual, rev. 1 5-12 freescale semiconductor preliminary?subject to change without notice 5.3.3.4 channel interrupt mask register (cimr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . cimr1 = enable bits for channels 32 to 63 (extended internal channels) cimr2 = enable bits for channe ls 64 to 95 (external channels) table 5-7. interrupt mask register (imr) field descriptions field description 0:24 reserved write of any value has no effect, read value is always 0. 25:26 reserved must be kept at 0. 27 reserved must be kept at 0. 28 mskjeoc: mask bit for jeoc when set, the jeoc interrupt is enabled. 29 mskjech: mask bit for jech when set, the jech interrupt is enabled. 30 mskeoc: mask bit for eoc when set, the eoc interrupt is enabled. 31 mskech: mask bit for ech when set, the ech interrupt is enabled. address: base + 0x0028 access: user read/write 0123456789101112131415 r cim 63 cim 62 cim 61 cim 60 cim 59 cim 58 cim 57 cim 56 cim 55 cim 54 cim 53 cim 52 cim 51 cim 50 cim 49 cim 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 47 cim 46 cim 43 cim 44 cim 43 cim 42 cim 41 cim 40 cim 39 cim 38 cim 37 cim 36 cim 35 cim 34 cim 33 cim 32 w reset00000000 00000000 figure 5-8. channel interrupt mask register 1 (cimr1)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-13 preliminary?subject to change without notice 5.3.3.5 watchdog threshold interr upt status register (wtisr) address: base + 0x002c acc ess: user read/write 0123456789101112131415 r cim 95 cim 94 cim 93 cim 92 cim 91 cim 90 cim 89 cim 88 cim 87 cim 86 cim 85 cim 84 cim 83 cim 82 cim 81 cim 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 79 cim 78 cim 77 cim 76 cim 75 cim 74 cim 73 cim 72 cim 71 cim 70 cim 69 cim 68 cim 67 cim 66 cim 65 cim 64 w reset00000000 00000000 figure 5-9. channel interrupt mask register 2 (cimr2) table 5-8. channel interrupt mask register (cimr[1..2]) field descriptions field description 31 cim0: interrupt enable when set (cim0 = 1), interrupt for channel 0 is enabled. n cimn: interrupt enable when set (cimn = 1), interrupt for channel n is enabled. address: base + 0x0030 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 wdg 3h wdg 2h wdg 1h wdg 0h wdg 3l wdg 2l wdg 1l wdg 0l w w1c w1c w1c w1c w1c w1c w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-10. watchdog threshold interrupt status register (wtisr)
pxd20 microcontroller reference manual, rev. 1 5-14 freescale semiconductor preliminary?subject to change without notice 5.3.3.6 watchdog threshold inte rrupt mask register (wtimr) reset value: 0x0000_0000 table 5-9. watchdog threshold interrupt stat us register (wtisr ) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:27 wdgxh [x = 0..3] this corresponds to the status flag generated on the converted value being higher than the programmed higher threshold. 28:31 wdgxl [x = 0..3] this corresponds to the status flag generated on the converted value being lower than the programmed lower threshold. address: base + 0x0034 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 msk wdg 3h msk wdg 2h msk wdg 1h msk wdg 0h msk wdg 3l msk wdg 2l msk wdg 1l msk wdg 0l w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-11. watchdog threshold interrupt mask register (wtimr) table 5-10. watchdog threshold interrupt m ask register (wtimr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:27 mskwdgxh [x = 0..3] this corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold. when set the interrupt is enabled. 28:31 mskwdgxl [x = 0..3] this corresponds to the mask bit for the interrupt gene rated on the converted value being lower than the programmed lower threshold. when set the interrupt is enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-15 preliminary?subject to change without notice 5.3.4 dma registers 5.3.4.1 dma enable register (dmae) the dma enable (dmae) register sets up the dma for use with the adc. 5.3.4.2 dma channel select register (dmar[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . dmar1 = enable bits for channels 32 to 63 (extended internal channels) dmar2 = enable bits for channels 64 to 95 (external channels) reset value: 0x0000_0000 address: base + 0x0040 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 000000 dcl r dma en w reset00000000 00000000 figure 5-12. dma enable register (dmae) table 5-11. dma enable register (dmae) field descriptions field description 0:29 reserved write of any value has no effect, read value is always 0. 30 dclr: dma clear sequence enable 0 dma request cleared by acknowledge from dma controller 1 dma request cleared on read of data registers 31 dmaen: dma global enable 0 dma feature is disabled. 1 dma feature is enabled.
pxd20 microcontroller reference manual, rev. 1 5-16 freescale semiconductor preliminary?subject to change without notice 5.3.5 threshold registers 5.3.5.1 introduction these four registers are used to store the user programmable lower and upper thresholds? values. the inverter bit and the mask bit for mask the interrupt are stored in the trc registers. address: base + 0x0048 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dma 63 dma 62 dma 61 dma 60 dma 59 dma 58 dma 57 dma 56 dma 55 dma 54 dma 53 dma 52 dma 51 dma 50 dma 49 dma 48 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 47 dma 46 dma 43 dma 44 dma 43 dma 42 dma 41 dma 40 dma 39 dma 38 dma 37 dma 36 dma 35 dma 34 dma 33 dma 32 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-13. dma channel select register 1 (dmar1) address: base + 0x004c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dma 95 dma 94 dma 93 dma 92 dma 91 dma 90 dma 89 dma 88 dma 87 dma 86 dma 85 dma 84 dma 83 dma 82 dma 81 dma 80 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 79 dma 78 dma 77 dma 76 dma 75 dma 74 dma 73 dma 72 dma 71 dma 70 dma 69 dma 68 dma 67 dma 66 dma 65 dma 64 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-14. dma channel select register 2 (dmar2) table 5-12. dma channel select register (dmar[1..2]) field descriptions field description 31 dma0: dma enable when set (dma0 = 1), channel 0 is enabled to transfer data in dma mode. n dman: dma enable when set (dman = 1), channel n is enabled to transfer data in dma mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-17 preliminary?subject to change without notice 5.3.5.2 threshold control register (trcx, x = [0..3]) reset value: 0x0000_0000 5.3.5.3 threshold register (thrhlr[0:3]) the four thrhlr n registers are used to store the user-p rogrammable thresholds? 10-bit values. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 reserved ? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 thr en thr inv res. reserved thrch rw rw ? ? rw figure 5-15. threshold control register (trcx, x = [0..3]) table 5-13. threshold control register (trcx, x = [0..3]) field descriptions field description 0:15 reserved write of any value has no effect, read value is always 0. 16 thren: threshold enable when set, this bit enables the threshold detection feature for the selected channel. 17 thrinv: invert the output pin setting this bit inverts the behavior of the threshold output pin. 18 reserved must be kept at 0. 19:24 reserved write of any value has no effect, read value is always 0. 25:31 thrch: choose the channel for threshold comparison.
pxd20 microcontroller reference manual, rev. 1 5-18 freescale semiconductor preliminary?subject to change without notice 5.3.6 conversion timing registers ctr[1..2] the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . ctr1 = associated to extended inte rnal channels (from 32 to 63) ctr2 = associated to external channels (from 64 to 95) address: base + 0x0060 (thrhlr0) base + 0x0064 (thrhlr1) base + 0x0068 (thrhlr2) base + 0x006c (thrhlr3) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 thrh w reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 thrl w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-16. threshold register (thrhlr[0:3]) table 5-14. threshold register (t hrhlr[0:3]) field descriptions field description 0:5 reserved write of any value has no effect, read value is always 0. 6:15 thrh: high threshold value for channel n . 16:21 reserved write of any value has no effect, read value is always 0. 22:31 thrl: low threshold value for channel n .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-19 preliminary?subject to change without notice address: base + 0x0098 (ctr1) base + 0x009c (ctr2) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp latch 0 offshift [0:1] 0 inpcmp [0:1] 0 inpsamp[0:7] w reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 figure 5-17. conversion ti ming registers ctr[1..2] table 5-15. conversion timing registers ctr[1..2] field descriptions field description 0:15 reserved write of any value has no effect, read value is always 0. 16 inplatch configuration bit for latching phase duration 17 reserved write of any value has no effect, read value is always 0. 18:19 offshift[0:1] configuration for offset shift characteristic 00 no shift (that is the transition between codes 000h and 001h) is reached when the a vin (analog input voltage) is equal to 1 lsb. 01 transition between code 000h and 001h is reached when the a vin is equal to1/2 lsb 10 transition between code 00h and 001h is reached when the a vin is equal to 0 11 not used 20 reserved write of any value has no effect, read value is always 0. 21:22 inpcmp[0:1] configuration bits for comparison phase duration 23 reserved write of any value has no effect, read value is always 0. 24:31 inpsamp[0:7] configuration bits for sampling phase duration
pxd20 microcontroller reference manual, rev. 1 5-20 freescale semiconductor preliminary?subject to change without notice 5.3.7 mask registers 5.3.7.1 introduction these registers are used to program which of the 96 input channels must be converted during normal and injected conversion. 5.3.7.2 normal conversion mask registers (ncmr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . ncmr1 = enable bits of normal sampling for ch annel 32 to 63 (extended internal channels) reset value: 0x0000_0000 address: base + 0x00a8 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ch63 ch62 ch61 ch60 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-18. normal conversion mask register 1 (ncmr1) address: base + 0x00ac a ccess: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-19. normal conversion mask register 2 (ncmr2)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-21 preliminary?subject to change without notice 5.3.7.3 injected conversion mask registers (jcmr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . jcmr1 = enable bits of inject ed sampling for channel 32 to 63 (extended internal channels) jcmr2 = enable bits of inj ected sampling for channel 64 to 95 (external channels) reset value: 0x0000_0000 table 5-16. normal conversion mask registers (ncmr[1..2]) field descriptions field description 31 ch0: sampling enable when set sampling is enabled for channel 0. n chn: sampling enable when set sampling is enabled for channel n. address: base + 0x00b8 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ch63 ch62 ch61 ch60 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-20. injected conversion mask register 1 (jcmr1) address: base + 0x00bc access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-21. injected conversion mask register 2 (jcmr2)
pxd20 microcontroller reference manual, rev. 1 5-22 freescale semiconductor preliminary?subject to change without notice 5.3.8 delay registers 5.3.8.1 decode signals delay register (dsdr) reset value: 0x0000_0000 5.3.8.2 power-down exit delay register (pdedr) reset value: 0x0000_0000 table 5-17. injected conversion mask registers (jcmr[1..2]) field descriptions field description 31 ch0: sampling enable when set, sampling is enabled for channel 0. n chn: sampling enable when set, sampling is enabled for channel n. address: base + 0x00c4 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 dsd[0:7] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-22. decode signals delay register (dsdr) table 5-18. decode signals delay register (dsdr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:31 dsd[0:7]: the delay between the external decode signals and the start of the sampling phase. it is used to take into account the settling time of the external multiplexer. the decode signal delay is calculated as: dsd 1/frequency of adc clock. note: when adc clock = peripheral clock/2, the dsd should be incremented by 2, to see an additional adc clock cycle delay on the decode signal. for example: dsd = 0; 0 adc clock cycle delay dsd = 2; 1 adc clock cycle delay dsd = 4; 2 adc clock cycles delay
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-23 preliminary?subject to change without notice 5.3.9 data registers 5.3.9.1 introduction adc conversion results are stored in data regi sters. there is one re gister per channel. the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-1 . cdr[32..63] = extended internal channels cdr[64..95] = external channels each data register also gives information rega rding the corresponding result as described below. address: base + 0x00c8 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 pded[0:7] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-23. power-down exit delay register (pdedr) table 5-19. power-down exit delay re gister (pdedr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:31 pded[0:7]: the delay between the power-down bit reset and the start of conversion the power down delay is calculated as: pded x 1/frequency of adc clock
pxd20 microcontroller reference manual, rev. 1 5-24 freescale semiconductor preliminary?subject to change without notice 5.3.9.2 channel data register (cdr n ) address: see ta b l e 5 - 1 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 va lid over w result [0:1] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 cdata[0:9] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 5-24. channel data register (cdr n ) table 5-20. cdr n field descriptions field description 0:11 reserved write of any value has no effect, read value is always 0. 12 valid used to notify when the data is valid (a new value has been written). it is automatically cleared when data is read. 13 overw: overwrite data this bit signals that the previous converted dat a has been overwritten by a new conversion. this functionality depends on the value of mcr[owren]: ? when owren = 0, then overw is frozen to 0 and cdat a field is protected aga inst being overwritten until being read. ? when owren = 1, then overw flags the cdata field overwrite status. 0 converted data has not been overwritten 1 previous converted data has been overwritten before having been read 14:15 result[0:1] this bit reflects the mode of conversion for the corresponding channel. 00 data is a result of normal conversion mode. 01 data is a result of injected conversion mode. 10 reserved. 11 reserved. 16:21 reserved write of any value has no effect, read value is always 0 22:31 cdata[0:9]: channel 0-95 converted data
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-25 preliminary?subject to change without notice 5.4 functional description 5.4.1 analog channel conversion two conversion modes are available within the adcdig: ? normal conversion ? injected conversion 5.4.1.1 normal conversion this is the normal conversion that the user program s by configuring the normal conversion mask registers (ncmr). each channel can be individually enabled by setting ?1? in the corresponding field of ncmr registers. mask registers must be programmed before starting the conve rsion and cannot be changed until the conversion of all the sel ected channels ends (nstart bit in the main status register (msr) is reset). 5.4.1.2 start of normal conversion by programming the configuration bits in the main configuration register (m cr), the normal conversion can be started in two ways: ? by software (trgen reset)?if the external trigger enable bit is reset, the c onversion chain starts when the nstart bit in the mcr is set. ? by trigger (trgen set)?an on-chip internal signal triggers an adc conversion. the settings in the mcr select how conversions are tri ggered based on these internal signals: ? if the edglev (edge/level selection) bit in the mcr is cleared, then a rising/falling edge (depending on the edge bit in m cr) detected in the signal sets the nstart bit in the msr and starts the programmed conversion. edge = 0 selects a falling edge. edge = 1 selects a rising edge. ? if the edglev bit in the mcr is set, the conversion is started if and only if the nstart bit in the mcr is set and the programmed level on th e trigger signal is detected. the level is selected using the edge bit in the mcr. ed ge = 0 means that the start of conversion is enabled if the signal is low. if edge = 1, the start of conversion is enabled when the signal is high. table 5-21. configurations for starting normal conversion type of conversion start mcr msr result trgen nstar t edgle v edge nstar t software 0 1 ? ? 1 conversion chain starts
pxd20 microcontroller reference manual, rev. 1 5-26 freescale semiconductor preliminary?subject to change without notice the nstart status bit in the msr is automatically set when the normal conversion starts. at the same time the nstart bit in the mcr is reset, allowing the software to pr ogram a new start of conversion. in that case the new requested conversion star ts after the running conversion is completed. if the content of all the normal conversion mask regi sters is zero (that is, no channel is selected) the conversion operation is considered completed and the interrupt ech (see further) is immediately issued after the start of conversion. 5.4.1.3 normal conversion operating modes two operating modes are available for the normal conversion: ? one shot ?scan to enter one of these modes, it is necessary to program the mode bit in the mcr. the first phase of the conversion process involves sampling the analog channel and the next phase involves the conversion phase when the sampled analog value is c onverted to digital as shown in figure 5-25 . figure 5-25. normal conversion flow in one shot mode (mode = 0) a sequential conversion specified in the ncmr registers is performed only once. at the end of ea ch conversion, the digital re sult of the conversion is stored in the corresponding data register. trigger 1 ? 0 0 1 a falling edge detected in a trigger signal sets the nstart bit in the msr and starts the programmed conversion. 1 a rising edge detected in a trigger signal sets the nstart bit in the msr and starts the programmed conversion. trigger 1 1 1 0 1 the conversion is started if the programmed level on the trigger signal is detected: the start of conversion is enabled if the external pin is low. 1 1 the conversion is started if the programmed level on the trigger signal is detected: the start of conversion is enabled if the external pin is high. table 5-21. configurations for starting normal conversion (continued) type of conversion start mcr msr result trgen nstar t edgle v edge nstar t sample b convert b sample c sample d convert d sample e convert e convert c
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-27 preliminary?subject to change without notice example 5-1. one shot mode (mode = 0) channels a-b-c-d-e-f-g-h are present in the device where channels b-d-e are to be converted in the one shot mode. mode = 0 is set for one shot mode. conversion starts from the channel b followed by conversion of channels d-e. at the end of conversion of channel e the scanning of channels stops. the nstart status bit in the msr is automatically set when the normal convers ion starts. at the same time the nstart bit in the mcr is reset, allowing the software to pr ogram a new start of conversion. in that case the new requested conversion star ts after the running conversion is completed. in scan mode (mode = 1), a sequential conversion of n cha nnels specified in the ncmr registers is continuously performed. as in the pr evious case, at the end of each c onversion the digital result of the conversion is stored into th e corresponding data register. the nstart status bit in the msr is automatically set when the normal conve rsion starts. unlike one shot mode, the nstart bit in the mcr is not reset. it can be reset by software when the user needs to stop scan mode. in that case, the adc completes the current scan conversion and, after the last conversion, also resets the nstart bit in the msr. example 5-2. scan mode (mode = 1) channels a-b-c-d-e-f-g-h are present in the device where channels b-d-e are to be converted in the scan mode. mode = 1 is set for scan mode. conversion starts from the channel b followed by conversion of the channels d-e. at the end of conversion of channel e the scanning of channel b starts followed by conversion of the channels d-e. this sequence repeats itself till the nstart bit in the mcr is reset by software. if the conversion is started by an ex ternal trigger and edglev is ?0?, the nstart bit in the mcr is not set. as a consequence, once started the only way to st op scan mode conversion is to set the mode bit to ?0?. at the end of each conversion an end of conversion interr upt is issued (if enab led by the corresponding mask bit) and at the end of the co nversion sequence an end of chain inte rrupt is issued (if enabled by the corresponding mask bit). 5.4.1.4 injected channel conversion a conversion chain can be injected into the ongoi ng normal conversion by configuring the injected conversion mask registers (jcmr). as normal conversion, each channe l can be individually selected. this injected conversion can only occur in one shot mode and interrupts the normal conversion. when an injected conversion is inserted, ongoi ng channel conversion is aborted and the injected channel request is processed. after the last channel in the injected ch ain is converted, normal conversion resumes from the channel at which the normal co nversion was stopped as shown in figure 5-26 .
pxd20 microcontroller reference manual, rev. 1 5-28 freescale semiconductor preliminary?subject to change without notice figure 5-26. injected sample/conversion sequence the injected conversion can be star ted by software setting the jsta rt bit in the mcr; the current conversion is suspended and th e injected chain is convert ed. at the end of the chain, the jstart bit in the msr is reset and the normal chain conversion is resumed. the jstart status bit in the msr is automatically se t when the injected conversion starts. at the same time the jstart bit in the mcr is reset, allowing th e software to program a new start of conversion. in that case the new requested conversion starts af ter the running injected conversion is completed. at the end of each injected conversion, an end of in jected conversion (jeoc) interrupt is issued (if enabled by the corresponding mask bit) and at the end of the sequence an end of injected chain (jech) interrupt is issued (if enabled by the corresponding mask bit). if the content of all the injected conversion mask registers is zero (t hat is, no channel is selected) the interrupt jech is immediately issu ed after the start of conversion. once started, injected chain conversion cannot be interrupted by any other conversion type (it can, however, be aborted; see section 5.4.1.5, abort conversion ). 5.4.1.5 abort conversion two different abort functions are provided. ? the user can abort the ongoing conversion by setting the abort bit in the mcr. the current conversion is aborted and the conve rsion of the next channel of th e chain is immediately started (generating a new start pulse to the analog adc). in the case of an abort operation, the nstart/jstart bit remains set and the abort bi t is reset after the conversion of the next channel starts. the eoc corresponding to the aborte d channel is not generated. this behavior is true for normal or triggered/inject ed conversion modes. if the last channel of a chai n is aborted, the end of chain is reported generating an ech interrupt. ? it is also possible to abort the current chain conversion by setting the abortchain bit in the mcr. in that case the behavior of the adc depends on the mode bit. in fact, if scan mode is disabled, the nstart bit is automatically reset together with the abor tchain bit. otherwise, if the mode bit is set to ?1?, a new chain conve rsion is started. the eoc of the current aborted conversion is not generated but an ech interrupt is generated to signal the end of the chain. the ongoing channel conversion is interrupted and the injected conversion chain is processed first, after the injected chain is converted the normal chain conversion resumes from the channel at which normal conversion was aborted. injected conversion of channels i and j normal conversion resumes from the last aborted channel. sample b convert b sample c sample d convert d sample e convert e convert c sample c abort c sample i sample j convert j sample c convert c convert i
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-29 preliminary?subject to change without notice when a chain conversion abort is requested (a bortchain bit is set) while an injected conversion is running over a suspended normal conversion, both injected chain and normal conversion chain are aborted (both the nsta rt and jstart bits are also reset). 5.4.2 analog clock generator and conversion timings the clock frequency can be select ed by programming the adclksel bit in the mcr. when this bit is set to ?1? the adc clock has the same frequency as the system clock. othe rwise, the adc clock is half of the system clock frequency. the adclksel bi t can be written only in power-down mode. when the internal divider is not enabled (adcclksel = 1), it is important th at the associated clock divider in the clock generation module is ?1?. th is is needed to ensure 50% clock duty cycle. the direct clock should basically be used only in low power mode when the device is using only the 16 mhz fast internal rc oscillator, but the conversi on still requires a 16 mhz clock (an 8 mhz clock is not fast enough). in all other cases, the adc should us e the clock divided by two internally. 5.4.3 adc sampling and conversion timing in order to support different loading and switching times, several different conversion timing registers (ctr) are present. there is one register per cha nnel type. inplatch and in pcmp configurations are limited when the system clock fr equency is greater than 20 mhz. when a conversion is started, the adc connects the in ternal sampling capacitor to the respective analog input pin, allowing the capac itance to charge up to the input voltage value. the time to load the capacitor is referred to as sampling time. after completion of the sampling phase, the evalua tion phase starts and all the bits corresponding to the resolution of the adc are estimated to provide the conversion result. the conversion times are pr ogrammed via the bit fields of the ct r. bit fields inplatch, inpcmp and inpsample are used to define the total conversion duration (t conv ) and in particular the partition between sampling phase duration (t sample ) and total evaluation phase duration (t eval ). the sampling phase duration is: where ndelay is equal to 0.5 if inpsample is less th an or equal to 06h, othe rwise it is 1. inpsample must be greater than or equal to 3 (hardware requirement). the total evaluation phase duration is: t sample inpsample ndelay ? ?? t ck ? = inpsample 3 ? ? 10 inpcmp t ck ? ?? ? == inpcmp 1 ? ?? and inplatch inpcmp ? ??
pxd20 microcontroller reference manual, rev. 1 5-30 freescale semiconductor preliminary?subject to change without notice inpcmp must be greater than or equal to 1 and inplatch must be less than incmp (hardware requirements). the total conversion duration is (not including external multiplexing): the timings refer to the unit t ck , where f ck = (1/2 x adc peripheral se t clock). the maximum clock frequency is specified in table 5-22 . table 5-23 lists the possible combinations by configuring the ad_clk at 60 mhz. table 5-22. max ad_clk frequency and related configuration settings inplatch inpcmp inpsample ad_clk f max (mhz) t sample min. (ns) 01h3h20125 0 1h 4h 20 + 4% 168 1 2h 4h 20 + 4% 168 1 2h 5h 20 + 4% 135 1 3h 6h 32 + 4% 132 1 3h 7h 40 + 4% 128 1 3h 8h 50 + 4% 134 1 3h 9h 60 + 4% 128 table 5-23. adc sampling and conversion timing inplatch inpcmp inpsamp t sample 1 1 represents the number of clock cycl es that this operation will last t eval ndelay t conv 1 11 0000 1001 8 * tck 30 * tck 1 * tck 39 * tck 2 2 the adc minimum conversion time at 60 mhz frequency is 39 * tck; that corresponds to 650 ns. 1 11 0000 1010 9 * tck 30 * tck 1 * tck 40 * tck 1 11 0000 1011 10 * tck 30 * tck 1 * tck 41 * tck 1 11 0000 1100 11 * tck 30 * tck 1 * tck 42 * tck 1 11 0000 1101 12 * tck 30 * tck 1 * tck 43 * tck 1 11 0000 1110 13 * tck 30 * tck 1 * tck 44 * tck 1 11 0000 1111 14 * tck 30 * tck 1 * tck 45 * tck ... ... ... ... ... ... ... 1 11 1111 1100 251 * tck 30 * tck 1 * tck 282 * tck 1 11 1111 1101 252 * tck 30 * tck 1 * tck 283 * tck 1 11 1111 1110 253 * tck 30 * tck 1 * tck 284 * tck 1 11 1111 1111 254 * tck 30 * tck 1 * tck 285 * tck t conv t sample t eval ndelay t ck ? ?? ++ =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-31 preliminary?subject to change without notice 5.4.4 programmable analog watchdog 5.4.4.1 introduction the analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in figure 5-27 ) specified by an upper and a lower threshold value named thrh and thrl respectively. figure 5-27. guarded area after the conversion of the selected channel, a comparison is perfor med between the converted value and the threshold values. if the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated. the comparison resu lt is stored as wdgxh and wdgxl bits in the wtisr as explained in table 5-24 . depending on the mask bits ms kwdgxl and mskwdgxh in the wtimr, an interrupt is gene rated on threshold violation. the channel on which the analog watchdog is to be a pplied is selected by the thrch field in the trc registers. the analog watchdog is enabled by setting the corresponding thren bit in the same register. the lower and higher threshold values for the analog watchdog are programme d using the registers thrhlr. for example, if channel num ber 3 is to be monitored with threshold values in thrhlr1, then the thrch field is programmed in the trc1 re gister to select channel number 3. a set of threshold register s (thrhlrx and trcx) can be linked only to a single channel for a particular thrch value. if another channel is to be monitore d with same threshold values, then the thrch field in the trcx register ha s to be programmed again. table 5-24. values of wdgxh and wdgxl fields wdgxh wdgxl converted data 1 0 converted data > thrh 0 1 converted data < thrl 0 0 thrl <= converted data <= thrh thrh thrl analog voltage upper threshold lower threshold guarded area
pxd20 microcontroller reference manual, rev. 1 5-32 freescale semiconductor preliminary?subject to change without notice note if the higher threshold for the anal og watchdog is programmed lower than the lower threshold and the converted value is less than the lower threshold, then the wdgxl interrupt for the low thre shold violation is set, else if the converted value is greater than the lower threshold (consequently also greater than the higher threshold) then the interrupt wdgxh for high threshold violation is set. thus, the us er should avoid that situation as it could lead to misinterpretati on of the watchdog interrupts. 5.4.5 dma functionality a dma request can be programmed after the convers ion of every channel by setting the respective masking bit in the dmar register s. the dmar masking registers mu st be programmed before starting any conversion. there is one dmar per channel type. the dma transfers can be enabled using the dmaen bit of dmae register. when the dclr bit of dmae register is set then the dma request is clea red on the reading of the register for which dma transfer has been enabled. 5.4.6 interrupts the adc generates the followi ng maskable interrupt signals: ? adc_eoc interrupt requests ? eoc (end of conversion) ? ech (end of chain) ? jeoc (end of injected conversion) ? jech (end of injected chain) ? wdgxl and wdgxh (watchdog threshold) interrupt requests interrupts are generated during the conversion process to signal events such as end of conversion as explained in register descript ion for ceocfr. two 7-bit regist ers named ceocfr (channel pending registers) and imr (interrupt mask register) are provided in order to check and enable the interrupt request to eic module. interrupts can be individually en abled on a channel by channel base by programming the cimr (channel interrupt mask register). several channel interrupt pending registers are also provided in or der to signal which of the channels? measurement has been completed. the analog watchdog interrupts are ha ndled by two 8-bit registers wtis r (watchdog threshold interrupt status register) and wtimr (watchdog threshold interrupt mask registe r) in order to check and enable the interrupt request to the eic module. the watchdog inte rrupt source sets two pending bits wdgxh and wdgxl in the wtisr for each of th e four channels being monitored.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 5-33 preliminary?subject to change without notice the ceocfr contains the in terrupt pending request status . if the user wants to cl ear a particular interrupt event status, then writing a ?1? to th e corresponding status bit clears the pending interrupt flag (at this write operation all the other bits of the ce ocfr must be maintained at ?0?). 5.4.7 external decode signals delay the adc provides several external decode signals to select which external channel has to be converted. in order to take into account the control switchi ng time of the external an alog multiplexer, a decode signals delay register (dsd r) is provided. the delay between the decoding signal selection and the actual start of conversion can be program med by writing the field dsd[0:7]. 5.4.8 power-down mode the analog part of the adc can be put in low power mode by setting the pwdn bit in the mcr. after releasing the reset signal the adc an alog module is kept in power-down mode by default, so this state must be exited before starti ng any operation by resetting th e appropriate bit in the mcr. the power-down mode can be requested at any time by setti ng the pwdn bit in the mcr. if a conversion is ongoing, the adc hard macrocell cannot immediatel y enter the power-down mode. in fact, the adc enters power-down mode only afte r completing the ongoing conversion. otherwise, the ongoing operation should be aborted manually by resetting the nstart bit and using the abortchain bit. bit adcstatus[0] in the msr is set on ly when adc enters power-down mode. after the power-down phase is completed the proc ess ongoing before the power-down phase must be restarted manually (by setting the appropriate start bit). resetting pwdn bit and setting nstart or jsta rt bit during the same cycle is forbidden. 5.4.9 auto-clock-off mode to reduce power consumption during the idle mode of operation (without going into power-down mode), an ?auto-clock-off? feature can be enabled by setti ng the acko bit in the mcr. when enabled, the analog clock is automatically switched off when no opera tion is ongoing, that is, no conversion is programmed by the user.
pxd20 microcontroller reference manual, rev. 1 5-34 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-1 preliminary?subject to change without notice chapter 6 boot assist module (bam) this chapter describes the boot assist module (bam). 6.1 overview the boot assist module is a bl ock of read-only memory containing vle code which is executed according to the boot mode of the device. the bam allows to download code in to internal sram through the follo wing serial protocol and execute it afterwards: ? flexcan (without autobaud) ? linflex (without autobaud) 6.2 features the bam provides the following features: ? locate serial communication interface for downloading application boot code ? detect application boot code ? pxd20 in static mode if internal flash is not initialized or invalid ? system can recover from static mode only by reset ? configures single mmu tbl entry to enable access to startup code ? programmable 64-bit password pr otection for serial boot mode ? serial boot loads the application boot code from a flexcan or linflex bus into internal sram ? censorship protection fo r internal flash module 6.3 boot modes the pxd20 supports the following boot modes: ? single chip (sc) - the device boot s from the first bootable section 1 of the flash memory main array. ? serial boot (sbl) - the device downloads boot c ode from either linflex or flexcan interface and then executes it. if booting is not possible with the se lected configuration (e.g., if no boot id is found in the selected boot location) then the device enters the static mode. 6.4 memory map the bam code resides in a reserved 8 kb rom mapped from address 0xffff_c000. 1. section with valid boot id
pxd20 microcontroller reference manual, rev. 1 6-2 freescale semiconductor preliminary?subject to change without notice the ram location where to download the code can be any 4 byte aligned location starting from the address 0x4000_0100. 6.5 functional description 6.5.1 entering boot modes the pxd20 detects the boot mode based on external pins and device status (see figure 6-1 ). to boot either from flexcan or linflex, the device must be forced into an alternate boot loader mode via the fab (force alternate boot m ode) pin which must be asserted be fore initiating the reset sequence. the type of alternate boot mode is selected according to the abs (alternate boot selector) pin (see table 6-1 ). note the watchdog (swt) is disabl ed at the start of ba m execution. in the case of an unexpected issue during bam execution the cpu may be stalled and it will be necessary to generate an external reset to recover. figure 6-1. boot mode selection the grey blocks represent action done by hardware; the white ones action done by software (bam).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-3 preliminary?subject to change without notice 6.5.2 reset configuration half word source (rchw) pxd20 flash memory is partitione d into boot sectors shown in table 6-3 . each boot sector contains the reset conf iguration half-word (rchw) at offset 0x00. table 6-1. hardware configuration to select boot mode fab abs standby-ram boot flag boot id boot mode 1 0 0 ? linflex 1 1 0 ? flexcan 0 - 0 valid sc (single chip) 0 - 0 not found static mode - - 1 - from backup ram (0x40000000) 1 1 after the device exits standby, it boots fr om backup ram if the standby-ram boot flag is set. if this flag is not set, the devi ce boots internally (sc) or using the bam depending on the state of the fabm and abs pins. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0000000vle boot_id w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 6-2. reset configuration half word (rchw) table 6-2. rchw field descriptions field description vle selects the vle or book e instruct ion set at application start address. 0 selects the classic powerpc instruction set 1 selects the vle instruction set boot_id is valid if its value is 0x5a, th en the sector is considered bootable
pxd20 microcontroller reference manual, rev. 1 6-4 freescale semiconductor preliminary?subject to change without notice figure 6-3. pxd20 flash memory partitioning and rchw search table 6-3. flash boot sector block address 0 0x0000_0000 1 0x0000_4000 2 0x0000_8000 3 0x0000_c000 4 0x0001_0000 5 0x0001_4000 6 0x0001_8000 7 0x0001_c000 16 kb boot information 16 kb 16 kb 16 kb 0x0000_0000 0x0000_8000 0x0000_c000 0x0001_0000 0x0002_0000 internal flash 0x0000_0000 0x0000_0004 0x0000_0008 0x0000_000c 16 kb 0x0001_8000 boot information 128 kb boot information boot information boot information application start address application application 0x0001_4000 boot information 0x0001_c000 boot information rchw 16 kb 16 kb 0x0000_4000 boot information 16 kb
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-5 preliminary?subject to change without notice 6.5.3 single chip boot mode in single chip mode the hardware se arches flash boot sector for a valid boot id. as soon the device detects the first bootable sector, it jumps within this sector and reads the 32-bit word at offset 0x4. this word is the address where the startup code is located (reset boot vector). the hardware then sets up a 4 kb mmu entry at this address. the instruct ion set for this entry is selected by the vle bit in the rchw. then the device executes this startup code. a user application should have a valid instruction at the reset boot vector address. the user applicat ion should set up the mmu to allow access to peripherals and memory as required. if a valid rchw is not found, the bam code is execut ed. in this case bam move s the pxd20 into static mode. 6.5.3.1 boot and alternate boot some applications require an altern ate boot sector so that the main boot can be erased and reprogrammed in the field. when an alternate boot is needed, user can create two bootable sectors; the lowest sector shall be the main boot sector and the highest shall be the alternate boot sector. the alternat e boot sector does not need to be consecutive to the main boot sector. this scheme allows to ensure that there is always one active boot sect or by erasing one of the boot sectors only: ? sector shall be activated (that is, program a valid boot_id instead of 0xff as initially programmed). ? sector shall be deactivated writing to 0 some of the bits boot-i d bit field (bit1 and/or bit3, and/or bit4, and/or bit6). 6.5.4 boot through bam 6.5.4.1 executing bam single chip mode is managed by ha rdware and bam does not participate. bam is executed only in the following two cases: ? serial boot mode has been selected by fab pin ? hardware has not found a valid boot -id in any flash boot locations if one of these conditions is true , the device fetches code at locat ion 0xffff_c000 and bam application starts. 6.5.4.2 bam software flow with reference to figure 6-4 a description of bam logic flow is done.
pxd20 microcontroller reference manual, rev. 1 6-6 freescale semiconductor preliminary?subject to change without notice figure 6-4. bam logic flow the first action is to save the ini tial device configuration. in this way is possible to restore the initial configuration after downloading the new code but before executing it. this allows the new code being executed as the device was just coming out of reset. the bmode field of the sscm status register (see section 44.2.2.1, system status register (status) ) indicates which boot has to be executed (see table 6-4 ). if bmode field shows either a single-chip value (0 11) or the reserved values, the boot mode is not considered valid and the bam pushe s the device into static mode. in all other cases the code of the relative boot is called. data is downloaded and saved into proper sram location. table 6-4. fields of sscm status register used by bam field description bmode bmode device boot mode. 000 flexray boot serial boot loader (future use) 001 can serial boot loader 010 sci serial boot loader 011 single chip other values are reserved bam entry 0xffff_c000 save default configuration check boot mode boot mode valid? download new code and save into sram which boot mode is selected is verified by reading the sscm_status register (bmode) restore default configuration restore default configuration static mode execute new code no ye s
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-7 preliminary?subject to change without notice then, the initial device configurati on is restored and the code jumps to the address of downloaded code. at this point bam ha s finished its task. if there is any error (that is, communication error, wrong boot selected, etc.), bam restores the default configuration and puts the device into static mode. st atic mode means the devi ce enters the low power mode safe and the processor executes a wait instruct ion. it is needed if the device cannot boot in the mode which was selected. during bam executi on and after, the mode reported by the field s_current_mode of the register me_gs in the module mc_me module is "drun". 6.5.4.3 bam resources bam uses/initializes the following mcu resources: ? mc_me and mc_cgm to initia lize mode and clock sources ? flexcan 0, linflex 0 and their pads when performing serial boot mode ? sscm to check the boot mode and during password check (see table 6-4 and figure 6-5 ) ? external oscillator ? swt (the bam disables it) as already mentioned, the initial configuration is restored befo re executing the downloaded code. 6.5.4.4 download and execute the new code from high level perspective, the download protocol follows steps: 1. send 64 bit password 2. send start address, size of down loaded code in bytes and vle bit 3. download data 4. execute code from start address. each step must be complete before the next step starts. the communication is done in half duplex manner, any transmission from host is foll owed by the mcu transmission: ? host sends data to mcu and start waiting ? mcu echoes to host the data received ? mcu verifies if echoes is correct ? if data is correct host can continue to send data ? if data is not correct host stops to transmit and mcu need to be reset. all multi-byte data structures are sent with msb first. a more detailed descripti on of these steps follows.
pxd20 microcontroller reference manual, rev. 1 6-8 freescale semiconductor preliminary?subject to change without notice 6.5.4.5 download 64-bit password and password check the first 64 bits received represen t the password. this password is sent to the password check procedure which verifies if it is correct. the password check data flow is shown in figure 6-5 where: ? sscm_status.sec = 1 means flash secured ? sscm_status.pub = 1 means flash with public access. in case of flash with public access, the received password is compared with the public password 0xfeed_face_cafe_beef. if public access is not allowed but the flash is not secured, the receiv ed password is compared with the value saved on nvpwd0 and nvpwd1 registers. in both of the previous cases, th e comparison is done by the bam c ode. the bam code does not enforce any compliance checks on the password itself. if co mparison fails the bam forces the mcu into static mode. in the case of public access not allowed and flash secured, the password is written into sscm.pwcmph-l registers. after a fixed time waiting, comparison is done by hardware. then bam verifies again sscm_status?s sec flag: ? sec = 0, flash is now unsecured and bam continues its task ? sec = 1, flash is still secured because pass word was wrong; bam puts mcu to static mode. this fixed time depends on the external crystal os cillator frequency (fxosc). with fxosc of 12 mhz, the fixed time is 350 ms.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-9 preliminary?subject to change without notice figure 6-5. password check flow 6.5.4.6 download start addre ss, vle bit and code size the next 8 bytes received by the mcu contain a 32-bit start address, th e vle mode bit and a 31-bit code length as shown in figure 6-6 . the vle bit (variable length instruction) is used to indicate for which instruction set the code has been compiled. the vle bit should be set to 1 for vle instruction set or 0 for booke. the start address defines wh ere the received data will be stored and where the mcu will branch after the download is finished. the two lsb bits of the star t address are ignored by th e bam program, such that the loaded code should be 32-bit word aligned. the length defines how many data bytes have to be loaded.
pxd20 microcontroller reference manual, rev. 1 6-10 freescale semiconductor preliminary?subject to change without notice figure 6-6. start address, vle bit and download size in bytes 6.5.4.7 download data each byte of data received is stored into device? s sram, starting from the address specified in the previous protocol step. the address increments until the num ber of bytes of data received matches the numbe r of bytes specified in the previous protocol step. since the sram is protected by 32-bi t wide error correction code (ecc), bam always writes bytes into sram grouped into 32-bit words. if the last byte received does not fa ll onto a 32-bit boundary, bam fills it with 0 bytes. then a ?dummy? word (0x0000_0000) is written to avoid ecc error during core prefetch. 6.5.4.8 execute code the bam program waits for the last ech o message transmission being completed. then it restores the initial mcu c onfiguration and jumps to the loaded code at start address which was received in step 2 of the protocol. at this point bam has finished its tasks and mcu is controlled by new code executing from sram. 6.5.5 boot from uart 6.5.5.1 configuration boot from uart protocol is implemented by the linflex 0 module. the pins used are: ? linflex_tx corresponds to pin pb[2] ? linflex_rx corresponds to pin pb[3]. the system clock is driven by an external oscillator. start_address[31:16] start_address[15:0] vle code_length[30:16] code_length[15:0]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-11 preliminary?subject to change without notice the linflex controller is configured to operate at a baud ra te = system clock freq uency/833, using an 8-bit data frame without parity bit and 1 stop bit. figure 6-7. linflex bit timing in uart mode 6.5.5.2 protocol table 6-5 summarizes the protocol and bam action during this boot mode. see also section 6.5.7, flash memory password swapping, for information on password swapping. 6.5.6 bootstrap with can 6.5.6.1 configuration boot from flexcan protocol is implemented by the flexcan_0 module. the pins used are: ? can_tx corresponds to pin pb[0] ? can_rx corresponds to pin pb[1]. boot from flexcan uses the system cloc k driven by an external oscillator. the flexcan controller is configured to opera te at a baud rate = sy stem clock frequency/40. it uses the standard 11-bit identifier fo rmat detailed in flex can 2.0a specification. flexcan controller bit timing is pr ogrammed with 10 time quanta, and th e sample point is 2 time quanta before the end, as shown in figure 6-8 . table 6-5. uart boot mode download protocol (autobaud disabled) protocol step host sent message bam response message action 1 64-bit password (msb first) 64-bit password password checked for validity and compared against stored password. 2 32-bit store address 32-bit store address load address is stored for future use. 3 vle bit + 31-bit number of bytes (msb first) vle bit + 31-bit number of bytes (msb first) size of download is stored for future use. verify if vle bit is set to 1 4 8 bits of raw binarydata 8 bits of raw binary data 8-bit data are packed into 32-bit words. this word is saved in sram starting from the ?load address.? ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to dowloaded code
pxd20 microcontroller reference manual, rev. 1 6-12 freescale semiconductor preliminary?subject to change without notice figure 6-8. flexcan bit timing 6.5.6.2 protocol table 6-6 summarizes the protocol and bam action during this boot mode. all data are transmitted byte wise. see also section 6.5.7, flash memory password swapping, for information on password swapping. table 6-6. flexcan boot mode download protocol (autobaud disabled) protocol step host sent message bam response message action 1 can id 0x011+ 64-bit password can id 0x001+ 64-bit password password checked for validity and compared against stored password. 2 can id 0x012+ 32-bit store address+ vle bit+ 31-bit number of bytes can id 0x002+ 32-bit store address+ vle bit+ 31-bit number of bytes load address is stored for future use. size of download is stored for future use. verify if vle bit is set to 1 3 can id 0x013+ 8 to 64 bits of raw binary data can id 0x003+ 8 to 64 bits of raw binary data 8-bit data are packed into 32-bit words. these words are saved in sram starting from the ?load address.? ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to dowloaded code table 6-7. system clock frequency related to external clock frequency f osc [mhz] f rc /f osc 1 f sys [mhz] 4 - 8 4 - 2 16 - 32 8 - 12 2 - 4/3 32 - 48 sync_seg time segment 1 time segment 2 sample point nrz signal transmit point 1 time quantum time quanta time quanta 7 2 1 bit time 1 time quantum = 4 sy stem clock periods
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 6-13 preliminary?subject to change without notice 6.5.7 flash memory password swapping when the chip uses the bam to boot using can or uart, the required flash memory password is different depending on whether the flas h memory is secured or unsecured. this difference affects how you must program the nvpwd0, nvpwd 1, nvsci0, and nvsci1 registers. when the flash memory is secured: ? the registers are pr ogrammed as follows: ? nvpwd0 = 0x87654321 ? nvpwd1 = 0x12345678 ? nvsci0 = 0x55aa1111 ? nvsci1 = 0x55aa1111 ? to download the code via serial boot, the provided password is 0x1234_5678_8765_4321 (nvpwd1 followed by nvpwd0). when the flash memory is unsecured: ? the registers are pr ogrammed as follows: ? nvpwd0 = 0x87654321 ? nvpwd1 = 0x12345678 ? nvsci0 = 0x55aa55aa ? nvsci1 = 0x55aa55aa ? to download the code via serial boot, the provided password is 0x8765_4321_1234_5678 (nvpwd0 followed by nvpwd1). 6.5.8 interrupts no interrupts are generated by or are enabled by the bam. 12 - 16 4/3 - 1 36 - 48 16 - 24 1 - 2/3 32 - 48 > 24 < 2/3 > 24 1 these values and consequently the f sys suffer from the precision of the rc internal oscillator used to measure f osc through the cmu module. table 6-7. system clock frequency related to external clock frequency f osc [mhz] f rc /f osc 1 f sys [mhz]
pxd20 microcontroller reference manual, rev. 1 6-14 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 7-1 preliminary?subject to change without notice chapter 7 can sampler 7.1 introduction the can sampler peripheral has been designed to store the fi rst identifier of can message "detected" on the can bus while no precise clock (crystal) is running at that time on the device, typically in low power modes (stop, halt or standby) or in run mode with crystal switched off. depending on both can baudrate and low power mode used, it is possible to catch either the first or the second can frame by sampling one of two can rx ports and storing all samples in internal registers. after selection of the mode (first or second frame), the can sampler stores samples of the 48 bits or skips the first frame and stores samples of the 48 bits of second frame using the 16-mhz irc oscillator and the 5-bit clock prescaler. after completion, software has to process the sample d data in order to rebuild the 48 minimal bits. figure 7-1. extended can data frame 7.2 main features ? store 384 samples, equivalent to 48 can bit @8 samples/bit ? sample frequency from 500 khz up to 16 mhz, equivalent at 8 samp les/bit to can baud rates of 62.5 kbps to 2 mbps ? user selectable can rx sample port, can0rx, can1rx, or can2rx ? 16 mhz irc clock ? 5-bit clock prescaler base identifier (11 bit) sof spr extended identifier (18 bit) ide-bit rtr-bit r1 r0 data length code
pxd20 microcontroller reference manual, rev. 1 7-2 freescale semiconductor preliminary?subject to change without notice ? configurable trigger mode (immediate, next frame) ? flexible samples processing by software ? very low power consumption 7.3 register description the can sampler registers are listed in table 7-1 . 7.3.1 can sampler control register (cr) table 7-1. can sampler registers register name address offset reset value location control register (cr) 00h 0000 0000h on page 7-2 sample registers 0 04h xxxx xxxxh 1 1 the initialization data is unknown. they wil l be filled only after first can sampling. on page 7-3 sample register 1 08h xxxx xxxxh 1 on page 7-3 ....... .... .... sample register 11 30h xxxx xxxxh 1 on page 7-3 address offset: 0x00 reset value: 0000 0000h 0123 4567 89101112131415 r 0000000000000000 w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_c ompl ete busy active _ck 0 0 0 mode can_rx_sel brp can_ smpl r_en w figure 7-2. control register (cr) table 7-2. cr field descriptions 0-15 reserved 16 rx_complete 1: can frame is stored in the sample registers 0: can frame has not been stor ed in the sample registers 17 busy this bit indicates the status of sampling 1: sampling is ongoing 0: sampling is complete or has not started 18 active_ck this bit indicates which is the cu rrent clock for sample registers. 1: firc is the curr ently selected clock 0: the peripheral set clock is the currently selected clock
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 7-3 preliminary?subject to change without notice 7.3.2 can sampler sample registers 0?11 the can sampler sample registers 0?11 have the same structure; figure 7-3 and figure 7-4 show this structure for registers 0 and 11, respectively. 19-21 reserved these are reserved bits. these bits are always read as ?0?. 22 mode 0:skip the first frame and sample and store the second frame (sf_mode) 1:sample and store the first frame (ff_mode) 23-25 can_rx_sel these bits determine which rx bit is sampled. 000: rx0 is selected 001: rx1 is selected 010: rx2 is selected 011: reserved 100: reserved 101: reserved 110: reserved 111: reserved 26-30 brp baud rate prescaler these bits are used to set the baud rate before going into standby mode 00000: prescaler has 1 11111: presacler has 32 31 can_smplr_e n can sampler enable this bit enables the can sampler before going into standby or stop mode. 0 can sampler is disabled 1 can sampler is enabled address offset: 0x04 reset value: xxxx xxxxh 0123 4567 89101112131415 r sr[0:15] w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr[16:31] w figure 7-3. sample register 0 table 7-2. cr field descriptions (continued)
pxd20 microcontroller reference manual, rev. 1 7-4 freescale semiconductor preliminary?subject to change without notice 7.4 functional description as the can sampler is driven by the 16 mhz irc to sample properly the can identifier, two modes are possible depending on both can baudr ate and low power mode used: ? immediate sampling on falling edge detection (first can frame): this mode is used when the irc 16 mhz is available in lp mode, e.g. stop or halt. ? sampling on next frame (second can frame): this mode is used wh en the irc 16 mhz is switched off in lp mode, e.g. standby. du e to the start-up times of both th e voltage regulat or and the irc 16 mhz (~10 ? s), the can sampler would miss the first bi ts of a can identifi er sent at 500kbps. therefore the first identifier is ignored and the sa mpling is performed on the first falling edge of after interframe space. the can sampler performs sampling on a user selected can rx port, normally wh en the device is in standby or stop mode storing the sample s in internal registers. the user is required to configure the baud rate to achieve 8 samples per can nominal bit.it does not perform a ny sort of filteri ng on input samples. thereafter the software must enable the sampler by setting can_smplr_en bit in cr register.it then becomes the master controller for accessing the in ternal registers implemen ted for storing samples. the can sampler, when enabled, waits for a low pulse on the selected rx line, ta king it as a valid bit of the first can frame and generates the rc wakeup request which can be used to start the rc oscillator. depending upon the mode, it stores the first 8 samples of the 48 bits on sele cted rx line or skips the first frame and stores 8 bits for first 48 bits of second frame. in ff_mode, it sample s the can rx line on rc clock and stores the 8 samples of first 48 bits (384 samples). in sf_mode, it samples the rx and waits for 11 consecutive dominant bits (11 * 8 samples), taking it as the end of first frame. it then waits for first low pulse on the rx, taking it as a valid start of frame (sof) of the second frame. the sampler takes 384 samples (48 bytes * 8) using the rc clock (configuring 8 samples per nom inal bit) of the second frame, including the sof bit. these samples ar e stored in consecutive addresses of the (12 x 32) internal registers. rx_complete bit is set to ?1?, indi cating that sampling is complete. software should now process the sampled data by fi rst becoming master for accessing samples internal registers by resetting can_smplr_en bit.the sampler will need to be enabled again to start waiting for a new sampling routine. address offset: 0x30 reset value: xxxx xxxxh 0123 4567 89101112131415 r sr[0:15] w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr[16:31] w figure 7-4. sample register 11
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 7-5 preliminary?subject to change without notice 7.4.1 enabling/disabling the can sampler the can sampler is disabled on reset and the cpu is able to access the 12 registers used for storing samples. the can sampler must be enabled be fore entering standby or stop mode by setting cr[can_smplr_en]. when the can sampler is enabled, the a, d, wen, cs n and ck to the (12 x 32) block of registers are switched to those generated by the kernel of the sampler. you can m onitor cr[active_ck] to check which is the active clock to the registers. any activity on selected rx line, the sampler enab les the 16 mhz rc oscillator. when can_smplr_en is reset to 0, the sampler should at least receive 3 rc clock pulses to reset itself, after which the rc can be switched off. when the software wishes to access the sample regist ers contents it must first reset the can_smplr_en bit by writing a ?0?. before accessing the register conten ts it must monitor active_ck bit for ?0?.when this bit is reset it can safely access th e (12 x 32) sample regist ers. while shifting from normal to sample mode and vice versa, the sample register signals must be static and inactive to ensure the data is not corrupt. 7.4.2 selecting the rx port one rx port can be selected per sampling routine; the port to be sampled is selected by can_rx_sel. 7.4.3 baud rate generation sampling is performed at a ba ud rate that is set by the software as a multiple of rc osci llator frequency of 62.5 ns (assuming rc is configured for high frequenc y mode i.e. 16 mhz). user must set the baud rate prescaler (brp) such that 8 samples per bit are achieved. baud rate setting must be made by software before going into standby or stop mode. this is done by setting brp bits 5:1 in control register. the reset value of brp is 00000 and can be set to max. 11111 which gives a prescale value of brp+1 thus providing a brp range of 1 to 32. ? maximum bitrate supported for sa mpling is 2mbps using brp as 1 ? minimum bitrate supported for sampling is 62.5kbps using brp as 32 table 7-3. internal multiplexer correspondence can_rx_sel rx selected 000 canrx_0 pb[1] 001 canrx_1 pb[10] 010 canrx_2 pm[3] 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved
pxd20 microcontroller reference manual, rev. 1 7-6 freescale semiconductor preliminary?subject to change without notice for example, suppose system is transmitting at 125kbps. in this case, nominal bit period: t=1/(125*10 3 )s =8*10 -3 *10 -3 s = 8 s eqn. 7-1 to achieve 8 samples per bit sample period= 8/8 s =1 s brp = 1 s/62.5ns = 16. thus, in this case brp = 01111. ? ? ? ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-1 preliminary?subject to change without notice chapter 8 clock description 8.1 clock architecture figure 8-1 shows the how the system clocks on pxd20 are generated. the peripheral groupings mentioned in the figure are listed in table 8-1 . peripherals not explicitly listed in a peripheral set or using an auxiliary clock use the system clock (or where available an alternative chosen within the peripheral) as their reference. note the system clock and modules may not select the fmpll0 clock directly. the option available is fmpll0 divi ded by 2. therefore, to select a 125 mhz clock, the fmpll0 must be configured to produce 250 mhz. the dram controller requi res fmpll0 to be opera tional and selected as the system clock for correct operation. table 8-1. pxd20 peripheral sets peripheral set 1 peripheral set 2 peripheral set 3 peripheral set 4 all linflex modules all flexcan modules adc sound generation module all i2c modules c an sampler ? ? stepper motor controller all dspi modules ? ?
pxd20 microcontroller reference manual, rev. 1 8-2 freescale semiconductor preliminary?subject to change without notice figure 8-1. pxd20 system clock generation ? 1 to ? 32 osca (xosc) primary irc fast clock monitor unit irc slow reset / int system clock selector fmpll0 fxosc_clk_divided firc_divided pll0_clk (e.g. 16 mhz) system_clk cpu peripheral set 1 watchdog rtc/api oscb (xosc) sxosc_clk (32 khz) ? 1 to ? 16 sxosc_clk_divided sirc_divided sirc_clk firc_clk fxosc_clk (via mc_rgm) clkout ? 1, ? 2, ? 4, ? 8 fmpll0_clk/2 firc_clk fxosc_clk clkout selector peripheral set 2 ? 1 to ? 16 ? 1 to ? 32 ? 1 to ? 32 irc_fast_divided fxosc_clk_divided emios1 (16ch) emios0 (16ch) ? 1 to ? 16 ? 1 to ? 16 clock selector clock selector secondary fmpll1 pll1_clk pll0_clk ? 2 firc_divided fxosc_divided firc_divided fxosc_divided dcu3 clock selector dcu3 clock ? 1 to ? 32 sxosc_clk_divided sirc_divided irc_slow_undivided platform clock selector quadspi serial interface clock ? 1 to ? 16 adc ? 1 to ? 16 system_clk rtc/api clock source (rtc_clk) flexcan part of peripheral set 2 option to clock from xosc or from system clk dculite clock selector dculite clock dcu3 dculite gpu memories dram controller tcon/ (e.g. 125 mhz) sgm ? 2 peripheral peripheral set 3 set 4 viu_in_clk viu_in_clk (e.g. 4 mhz) (e.g. 250 mhz) (128 khz) rsds fmpll1_clk (undivided) sirc_clk (128 khz undivided) sxosc_clk (32 khz undivided) ? 2
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-3 preliminary?subject to change without notice 8.2 auxiliary clocks this device has five auxiliary cloc ks configurable using the mc_cgm registers. these auxiliary clocks allow the associated peripherals to operate at clock speeds independent of the system clock (sys_clk). the peripherals also use the undivided syst em clock to synchronously interface with the rest of the device. the auxiliary clock c onfiguration is: ? auxiliary clock 0: dcu3 ? auxiliary clock 1: emios0 ? auxiliary clock 2: emios1 ? auxiliary clock 3: quadspi ? auxiliary clock 4: dculite 8.3 clock generation module (mc_cgm) 8.3.1 introduction this document describes the clock generation module (mc_cgm) which in cludes, but is not limited to, the functionality, pin description, and registers of the mc_cgm module. 8.3.1.1 overview the clock generation module (mc_cg m) generates reference clocks for all the soc blocks. the mc_cgm selects one of the system clock sources to supply the system clock. the mc_me controls the system clock selection (see the mc_me documentation for more deta ils). a set of mc_cgm registers controls the clock dividers which are used for di vided system and peripher al clock generation. the mc_cgm memory space also includes the control registers of the cloc k sources themselves, for example plls, ircs, and oscillators. the mc_cgm also selects and generates an output clock. figure 8-2 depicts the mc_cgm block diagram.
pxd20 microcontroller reference manual, rev. 1 8-4 freescale semiconductor preliminary?subject to change without notice figure 8-2. mc_cgm block diagram 8.3.1.2 features the mc_cgm includes th e following features: ? generates system and peripheral clocks ? selects and enables/disables the system clock supply from sy stem clock sources according to mc_me control ? contains a set of registers to control cl ock dividers for divided clock generation output clock selector/divider registers platform interface cpu mc_cgm mc_me auxiliary clock selector/divider system clock multiplexer/divider fxosc fmpll0 fmpll1 firc mapped modules interface mapped peripherals peripherals pf[15] mc_rgm
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-5 preliminary?subject to change without notice ? supports multiple clock sources and maps their address spaces to its memory map ? generates an output clock ? guarantees glitch-less clock transitions when changing the system clock selection ? supports 8, 16 and 32-bit wide read/write accesses 8.3.2 external signal description the mc_cgm delivers an output clock to the pf[ 15] pin for off-chip use and/or observation. 8.3.3 memory map and register definition table 8-2. mc_cgm register description address name description size access location user supervisor test 0xc3fe- 0340 cgm_viu_mux viu2 multiplex select word read read/write read/write on page 8-11 0xc3fe _0370 cgm_oc_en output clock enable word read read/write read/write on page 8-12 0xc3fe _0374 cgm_ocds_sc output clock division select byte read read/write read/write on page 8-13 0xc3fe _0378 cgm_sc_ss system clock select status byte read read read on page 8-14 0xc3fe _037c cgm_sc_dc0 system clock divider configuration 0 byte read read/write read/write on page 8-15 0xc3fe _037d cgm_sc_dc1 system clock divider configuration 1 byte read read/write read/write on page 8-15 0xc3fe _037e cgm_sc_dc2 system clock divider configuration 2 byte read read/write read/write on page 8-15 0xc3fe _037f cgm_sc_dc3 system clock divider configuration 3 byte read read/write read/write on page 8-15 0xc3fe _0380 cgm_ac0_sc aux clock 0 select control word read read/write read/write on page 8-16 0xc3fe _0384 cgm_ac0_dc aux clock 0 divider configuration byte read read/write read/write on page 8-17 0xc3fe _0388 cgm_ac1_sc aux clock 1 select control word read read/write read/write on page 8-17 0xc3fe _038c cgm_ac1_dc aux clock 1 divider configuration byte read read/write read/write on page 8-18 0xc3fe _0390 cgm_ac2_sc aux clock 2 select control word read read/write read/write on page 8-19 0xc3fe _0394 cgm_ac2_dc aux clock 2 divider configuration byte read read/write read/write on page 8-20
pxd20 microcontroller reference manual, rev. 1 8-6 freescale semiconductor preliminary?subject to change without notice note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error 0xc3fe _0398 cgm_ac3_sc aux clock 3 select control word read read/write read/write on page 8-20 0xc3fe _039c cgm_ac3_dc aux clock 3 divider configuration byte read read/write read/write on page 8-21 0xc3fe _03a0 cgm_ac4_sc aux clock 4 select control word read read/write read/write on page 8-22 0xc3fe _03a4 cgm_ac4_dc aux clock 4 divider configuration byte read read/write read/write on page 8-23 table 8-3. mc_cgm memory map address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe _0000 ? 0xc3fe _003c reserved 0xc3fe _0040 ? 0xc3fe _005c sxosc registers (see section 8.4, oscillators ) 0xc3fe _0060 ? 0xc3fe _007c firc registers (see section 8.4, oscillators ) 0xc3fe _0080 ? 0xc3fe _009c sirc registers (see section 8.4, oscillators ) table 8-2. mc_cgm register description (continued) address name description size access location user supervisor test
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-7 preliminary?subject to change without notice 0xc3fe _00a0 ? 0xc3fe _00bc fmpll0 registers 0xc3fe _00c0 ? 0xc3fe _00dc fmpll1 registers 0xc3fe _00e0 ? 0xc3fe _00fc reserved 0xc3fe _0100 ? 0xc3fe _011c cmu registers (see section 8.6, clock monitor unit (cmu) ) 0xc3fe _0120 ? 0xc3fe _013c reserved 0xc3fe _0140 ? 0xc3fe _015c reserved 0xc3fe _0160 ? 0xc3fe _017c reserved 0xc3fe _0180 ? 0xc3fe _019c reserved 0xc3fe _01a0 ? 0xc3fe _01bc reserved table 8-3. mc_cgm memory map (continued) address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 8-8 freescale semiconductor preliminary?subject to change without notice 0xc3fe _01c0 ? 0xc3fe _01dc reserved 0xc3fe _01e0 ? 0xc3fe _01fc reserved 0xc3fe _0200 ? 0xc3fe _021c reserved 0xc3fe _0220 ? 0xc3fe _023c reserved 0xc3fe _0240 ? 0xc3fe _025c reserved 0xc3fe _0260 ? 0xc3fd _c27c reserved 0xc3fe _0280 ? 0xc3fe _029c reserved 0xc3fe _02a0 ? 0xc3fe _02bc reserved 0xc3fe _02c0 ? 0xc3fe _02dc reserved table 8-3. mc_cgm memory map (continued) address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-9 preliminary?subject to change without notice 0xc3fe _02e0 ? 0xc3fe _02fc reserved 0xc3fe _0300 ? 0xc3fe _031c reserved 0xc3fe _0320 ? 0xc3fe _033c reserved 0xc3fe _0340 cgm_viu_ mux r viusel 000000000000000 w r0000000000000000 w 0xc3fe _0344 ? 0xc3fe _036c reserved 0xc3fe _0370 cgm_oc_enr0000000000000000 w r000000000000000 en w 0xc3fe _0374 cgm_ocds_ sc r0 0 seldiv selctl 00000000 w r0000000000000000 w 0xc3fe _0378 cgm_sc_ssr0000 selstat 00000000 w r0000000000000000 w table 8-3. mc_cgm memory map (continued) address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 8-10 freescale semiconductor preliminary?subject to change without notice 0xc3fe _037c cgm_sc_dc 0?3 r de0 000 div0 de1 000 div1 w r de2 000 div2 de3 000 div3 w 0xc3fe _0380 cgm_ac0_s c r0000 selctl 00000000 w r0000000000000000 w 0xc3fe _0384 cgm_ac0_d c0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe _0388 cgm_ac1_s c r0000 selctl 00000000 w r0000000000000000 w 0xc3fe _038c cgm_ac1_d c0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe _0390 cgm_ac2_s c r0000 selctl 00000000 w r0000000000000000 w 0xc3fe _0394 cgm_ac2_d c0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe _0398 cgm_ac3_s c r0000 selctl 00000000 w r0000000000000000 w table 8-3. mc_cgm memory map (continued) address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-11 preliminary?subject to change without notice 8.3.3.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the cgm_oc_en register may be accessed as a word at address 0xc3fe_0370, as a half-word at address 0xc3fe_0372, or as a byte at address 0xc3fe_0373. 8.3.3.1.1 viu2 multiplex select register (cgm_viu_mux) 0xc3fe _039c cgm_ac3_d c0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe _03a0 cgm_ac4_s c r0000 selctl 00000000 w r0000000000000000 w 0xc3fe _03a4 cgm_ac4_d c0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe _03a8 ? 0xc3fe _3ffc reserved address: 0xc3fe_0340 access: user read, supervisor read/write, test read/write 0123456789101112131415 r viu sel 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000 auto_div2 0 w reset0000000000000000 figure 8-3. viu2 multiplex select register (cgm_viu_mux) table 8-3. mc_cgm memory map (continued) address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 8-12 freescale semiconductor preliminary?subject to change without notice this register is used to select which pi ns to use for viu2 input. for details, see section 3.3.6, dram interface . 8.3.3.1.2 output clock enab le register (cgm_oc_en) this register is used to enab le and disable the output clock. table 8-4. cgm_viu_mux field descriptions field description viusel selects which pins to use for viu2 input. 0 pdi[7:0], hsync, vsync 1pdi[17:8] auto_div2 00 system clock automatically set to half the sdram clock frequency 01 reserved - do not select 10 reserved - do not select 11 reserved - do not select address 0xc3fe_0370 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 en w reset0000000000000000 figure 8-4. output clock enable register (cgm_oc_en) table 8-5. output clock enable register (cgm_oc_en) field descriptions field description en output clock enable control 0 output clock is disabled 1 output clock is enabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-13 preliminary?subject to change without notice 8.3.3.1.3 output clock division se lect register (cgm_ocds_sc) this register is used to select th e current output clock source and by which factor it is divi ded before being delivered at the output clock. address 0xc3fe_0374 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0 0 seldiv selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-5. output clock division select register (cgm_ocds_sc) table 8-6. output clock division select register (cgm_ocds_sc) field descriptions field description seldiv output clock division select 00 output selected output clock without division 01 output selected output clock divided by 2 10 output selected output clock divided by 4 11 output selected output clock divided by 8 selctl output clock source selection control ? this value selects the current source for the output clock. 0000 16 mhz int. rc osc. 0001 4-16 mhz ext. xtal osc. 0010 primary pll/2 0011 secondary pll 0100 128 khz int. rc osc. 0101 32 khz ext. xtal osc. 0110 reserved 0111 rtc clock 1000 system clock 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
pxd20 microcontroller reference manual, rev. 1 8-14 freescale semiconductor preliminary?subject to change without notice 8.3.3.1.4 system clock select status register (cgm_sc_ss) this register provides the curren t system clock source selection. address 0xc3fe_0378 access: user read, supervisor read, test read 0123456789101112131415 r0000 selstat 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-6. system clock select status register (cgm_sc_ss) table 8-7. system clock select status register (cgm_sc_ss) field descriptions field description selstat system clock source selection status ? this value indicates the curr ent source for the system clock. 0000 16 mhz int. rc osc. 0001 reserved 0010 reserved 0011 div. 4-16 mhz ext. xtal osc. 0100 primary pll/2 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-15 preliminary?subject to change without notice 8.3.3.1.5 system clock divider conf iguration registers (cgm_sc_dc0 ? 3) these registers control the system clock dividers. the divided clock is the reference for the associated peripheral set. address 0xc3fe_037c access: user read, supervisor read/write, test read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0123456789101112131415 r de0 000 div0 de1 000 div1 w reset1000000010000000 1514131211109876543210 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r de2 000 div2 de3 000 div3 w reset1000000010000000 figure 8-7. system clock divider configuration registers (cgm_sc_dc0?3) table 8-8. system clock divider configurati on registers (cgm_sc_dc0 ?3) field descriptions field description de0 divider 0 enable 0 disable system clock divider 0 1 enable system clock divider 0 div0 divider 0 division value ? the resultant peripheral set 1 clock will have a period div0 + 1 times that of the system clock. if the de0 is set to ?0? (divider 0 is disabled), any write access to the div0 field is ignored and the peripheral set 1 clock remains disabled. de1 divider 1 enable 0 disable system clock divider 1 1 enable system clock divider 1 div1 divider 1 division value ? the resultant peripheral set 2 clock will have a period div1 + 1 times that of the system clock. if the de1 is set to ?0? (divider 1 is disabled), any write access to the div1 field is ignored and the peripheral set 2 clock remains disabled. de2 divider 2 enable 0 disable system clock divider 2 1 enable system clock divider 2 div2 divider 2 division value ? the resultant peripheral set 3 clock will have a period div2 + 1 times that of the system clock. if the de2 is set to ?0? (divider 2 is disabled), any write access to the div2 field is ignored and the peripheral set 4 clock remains disabled. de3 divider 3 enable 0 disable system clock divider 3 1 enable system clock divider 3 div3 divider 3 division value ? the clock for peripheral clock 4 (sgm) is fixed at divide by 2. this field is not writable and always reads as 0.
pxd20 microcontroller reference manual, rev. 1 8-16 freescale semiconductor preliminary?subject to change without notice 8.3.3.1.6 auxiliary clock 0 select control register (cgm_ac0_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: unused ? divided by auxiliary clock 0 divider 0: dcu3 clock address 0xc3fe_0380 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-8. auxiliary clock 0 select control register (cgm_ac0_sc) table 8-9. cgm_ac0_sc field descriptions field description selctl auxiliary clock 0 source selection control ? this value selects the curre nt source for auxiliary clock 0. 0000 div. 16 mhz int. rc osc. 0001 div. 4-16 mhz ext. xtal osc. 0010 secondary pll 0011 primary pll/2 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-17 preliminary?subject to change without notice 8.3.3.1.7 auxiliary clock 0 divider c onfiguration register (cgm_ac0_dc) this register controls th e auxiliary clock 0 divider. 8.3.3.1.8 auxiliary clock 1 select control register (cgm_ac1_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: unused ? divided by auxiliary clock 1 divider 0: emios0 clock address 0xc3fe_0384 access: user read, supervisor read/write, test read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-9. auxiliary clock 0 divider configuration register (cgm_ac0_dc) table 8-10. cgm_ac0_dc field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 0 divider 0 1 enable auxiliary clock 0 divider 0 div0 divider 0 division value ? the resultant dcu3 clock will have a pe riod div0 + 1 times that of auxiliary clock 0. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the dcu3 clock remains disabled. address 0xc3fe_0388 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-10. auxiliary clock 1 select control register (cgm_ac1_sc)
pxd20 microcontroller reference manual, rev. 1 8-18 freescale semiconductor preliminary?subject to change without notice 8.3.3.1.9 auxiliary clock 1 divider c onfiguration register (cgm_ac1_dc) this register controls th e auxiliary clock 1 divider. table 8-11. auxiliary clock 1 select control register (cgm_ac1_sc) field descriptions field description selctl auxiliary clock 1 source selection control ? this value selects the curre nt source for auxiliary clock 1. 0000 div. 16 mhz int. rc osc. 0001 div. 4-16 mhz ext. xtal osc. 0010 secondary pll 0011 primary pll/2 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_038c access: user read, supervisor read/write, test read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-11. auxiliary clock 1 divider configuration register (cgm_ac1_dc) table 8-12. cgm_ac1_dc field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 1 divider 0 1 enable auxiliary clock 1 divider 0 div0 divider 0 division value ? the resultant emios0 clock will have a period div0 + 1 times that of auxiliary clock 1. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the emios0 clock remains disabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-19 preliminary?subject to change without notice 8.3.3.1.10 auxiliary clock 2 select control register (cgm_ac2_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: unused ? divided by auxiliary clock 2 divider 0: emios1 clock address 0xc3fe_0390 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-12. auxiliary clock 2 select control register (cgm_ac2_sc) table 8-13. auxiliary clock 2 select control register (cgm_ac2_sc) field descriptions field description selctl auxiliary clock 2 source selection control ? this value selects the curre nt source for auxiliary clock 2. 0000 div. 16 mhz int. rc osc. 0001 div. 4-16 mhz ext. xtal osc. 0010 secondary pll 0011 primary pll/2 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
pxd20 microcontroller reference manual, rev. 1 8-20 freescale semiconductor preliminary?subject to change without notice 8.3.3.1.11 auxiliary clock 2 divider configuration register (cgm_ac2_dc) this register controls th e auxiliary clock 2 divider. 8.3.3.1.12 auxiliary clock 3 select control register (cgm_ac3_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: unused ? divided by auxiliary clock 3 divider 0: quadspi clock see figure 8-23 for details. address 0xc3fe_0394 access: user read, supervisor read/write, test read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-13. auxiliary clock 2 divider configuration register (cgm_ac2_dc) table 8-14. cgm_ac2_dc field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 2 divider 0 1 enable auxiliary clock 2 divider 0 div0 divider 0 division value ? the resultant emios1 clock will have a period div0 + 1 times that of auxiliary clock 2. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the emios1 clock remains disabled. address 0xc3fe_0398 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-14. auxiliary clock 3 select control register (cgm_ac3_sc)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-21 preliminary?subject to change without notice 8.3.3.1.13 auxiliary clock 3 divider configuration register (cgm_ac3_dc) this register controls th e auxiliary clock 3 divider. table 8-15. auxiliary clock 3 select control register (cgm_ac3_sc) field descriptions field description selctl auxiliary clock 3 source selection control ? this value selects the curre nt source for auxiliary clock 3. 0000 system clock 0001 primary pll 0010 secondary pll 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_039c access: user read, supervisor read/write, test read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-15. auxiliary clock 3 divider configuration register (cgm_ac3_dc) table 8-16. cgm_ac3_dc field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 3 divider 0 1 enable auxiliary clock 3 divider 0 div0 divider 0 division value ? the resultant quadspi clock will have a period div0 + 1 times that of auxiliary clock 3. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the quadspi clock remains disabled.
pxd20 microcontroller reference manual, rev. 1 8-22 freescale semiconductor preliminary?subject to change without notice 8.3.3.1.14 auxiliary clock 4 select control register (cgm_ac4_sc) this register is used to select the cu rrent clock source for the following clocks: ? undivided: unused ? divided by auxiliary clock 4 divider 0: dculite clock address 0xc3fe_03a0 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-16. auxiliary clock 4 select control register (cgm_ac4_sc) table 8-17. cgm_ac4_sc field descriptions field description selctl auxiliary clock 4 source selection control ? this value selects the curre nt source for auxiliary clock 4. 0000 div. 16 mhz int. rc osc. 0001 div. 4-16 mhz ext. xtal osc. 0010 secondary pll 0011 primary pll/2 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-23 preliminary?subject to change without notice 8.3.3.1.15 auxiliary clock 4 divider configuration register (cgm_ac4_dc) this register controls th e auxiliary clock 4 divider. 8.3.4 functional description 8.3.4.1 system clock generation figure 8-19 shows the block diagram of the system cl ock generation logic. the mc_me provides the system clock select and switch mask (see mc_me documentation for more de tails), and the mc_rgm provides the safe clock request (s ee mc_rgm documentation for more details). the safe clock request forces the selector to select the 16 mhz int. rc osc. as the system clock and to ignore the system clock select. address 0xc3fe_03a4 access: user read, supervisor read/write, test read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-17. auxiliary clock 4 divider configuration register (cgm_ac4_dc) table 8-18. cgm_ac4_dc field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 4 divider 0 1 enable auxiliary clock 4 divider 0 div0 divider 0 division value ? the resultant dculite clock will have a period div0 + 1 times that of auxiliary clock 4. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the dculite clock remains disabled.
pxd20 microcontroller reference manual, rev. 1 8-24 freescale semiconductor preliminary?subject to change without notice figure 8-19. mc_cgm system clock generation overview 8.3.4.1.1 system clock source selection during normal operation, the system clock selection is controlled ? on a safe mode or reset event, by the mc_rgm ? otherwise, by the mc_me figure 8-18. div. 4-16 mhz ext. xtal osc. 3 primary pll/2 4 system clock ?0? cgm_sc_ss register mc_rgm safe mode request me_ _mc.sysclk cgm_sc_dc0 register clock divider peripheral set 1 clock ?? peripheral set 4 clock cgm_sc_dc1 register clock divider peripheral set 2 clock cgm_sc_dc2 register clock divider peripheral set 3 clock system clock is disabled if me__mc.sysclk = ?1111? ?0000? 1 0 16 mhz int. rc osc. 0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-25 preliminary?subject to change without notice 8.3.4.1.2 system clock disable during the stop and test modes, the syst em clock can be disabled by the mc_me. 8.3.4.1.3 system clock dividers the mc_cgm generates the following de rived clocks from the system cloc k that are used as the reference clocks for their associated peripherals: ? peripheral set 1 clock - contro lled by the cgm_sc_dc0 register ? peripheral set 2 clock - contro lled by the cgm_sc_dc1 register ? peripheral set 3 clock - contro lled by the cgm_sc_dc2 register ? peripheral set 4 clock - fixed at ? 2 8.3.4.1.4 auxiliary clock generation figure 8-20 (and those following) shows the block diagram of the auxiliary clock generation logic. see: ? section 8.3.3.1.6, auxiliary clock 0 select control register (cgm_ac0_sc) ? section 8.3.3.1.8, auxiliary clock 1 select control register (cgm_ac1_sc) ? section 8.3.3.1.12, auxiliary clock 3 select control register (cgm_ac3_sc) ? section 8.3.3.1.14, auxiliary clock 4 select control register (cgm_ac4_sc) 8.3.4.1.5 auxiliary clock dividers figure 8-20. mc_cgm auxiliary clock 0 generation overview cgm_ac0_dc register clock divider dcu3 clock unused secondary pll 2 primary pll/2 3 div. 4-16 mhz ext. xtal osc. 1 cgm_ac0_sc register div. 16 mhz int. rc osc. 0
pxd20 microcontroller reference manual, rev. 1 8-26 freescale semiconductor preliminary?subject to change without notice figure 8-22. mc_cgm auxiliary clock 2 generation overview figure 8-21. mc_cgm auxiliary clock 1 generation overview cgm_ac1_dc register clock divider emios0 clock unused secondary pll 2 primary pll/2 3 div. 4-16 mhz ext. xtal osc. 1 cgm_ac1_sc register div. 16 mhz int. rc osc. 0 cgm_ac2_dc register clock divider emios1 clock unused secondary pll 2 primary pll/2 3 div. 4-16 mhz ext. xtal osc. 1 cgm_ac2_sc register div. 16 mhz int. rc osc. 0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-27 preliminary?subject to change without notice figure 8-23. mc_cgm auxiliary clock 3 generation overview figure 8-24. mc_cgm auxiliary clock 4 generation overview 8.3.4.2 dividers functional description dividers are used for the generation of divided system and peripheral clocks. the mc_cgm has the following control register s for built-in dividers: cgm_ac3_dc register clock divider quadspi clock unused secondary pll 2 primary pll 1 cgm_ac3_sc register system clock 0 secondary pll 2 primary pll/2 3 div. 4-16 mhz ext. xtal osc. 1 cgm_ac4_sc register div. 16 mhz int. rc osc. 0 cgm_ac4_dc register clock divider dculite clock unused
pxd20 microcontroller reference manual, rev. 1 8-28 freescale semiconductor preliminary?subject to change without notice ? section 8.3.3.1.5, system clock divider conf iguration register s (cgm_sc_dc0?3) ? section 8.3.3.1.7, auxiliary clock 0 divider configuration register (cgm_ac0_dc) ? section 8.3.3.1.9, auxiliary clock 1 divider configuration register (cgm_ac1_dc) ? section 8.3.3.1.11, auxiliary cloc k 2 divider configurati on register (cgm_ac2_dc) ? section 8.3.3.1.13, auxiliary clock 3 divider configuration register (cgm_ac3_dc) ? section 8.3.3.1.15, auxiliary clock 4 divider configuration register (cgm_ac4_dc) the reset value of all counters is ?1?. if a divider has its de bit in the respective configuration register set to ?0? (the divider is disabled), a ny value in its divn field is ignored. 8.3.4.3 dram controller clock for correct operation, the dram cont roller requires two clocks: the sy stem clock and 2x system clock. since the only clock source available on the device that can provide this is the fmpll0, the dram controller can only operate when fmp ll0 is selected as the system cloc k. this is not a limitation because in practice fmpll0 is the only clock that can pr ovide operating frequencie s high enough for the dram controller. 8.3.4.4 output clock multiplexing the mc_cgm contains a mu ltiplexing function for a num ber of clock sources whic h can then be used as output clock sources. the selection is done via the cgm_ocds_sc register. 8.3.4.5 output clock division selection figure 8-25. mc_cgm output clock multiplexer and pa[0] generation the mc_cgm provides the following output signals for the output clock generation: ? pa [ 0 ] (see figure 8-25 ). this signal is generated by using one of the 3-stage ripple counter outputs or the selected signal without division. the non-divided signal is not guaranteed to be 50% duty cycle by the mc_cgm. cgm_ocds_sc.selctl cgm_ocds_sc.seldiv 0 1 2 3 register register 16 mhz int. rc osc. 0 4-16 mhz ext. xtal osc. 1 primary pll/2 2 secondary pll 3 128 khz int. rc osc. 4 32 khz ext. xtal osc. 5 reserved 6 rtc clock 7 system clock 8 pa [ 0 ] ?0? cgm_oc_en register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-29 preliminary?subject to change without notice the mc_cgm also has an output clock enable register (see section 8.3.3.1.2, output clock enable register (cgm_oc_en) ) which contains the output cloc k enable/disable control bit. 8.4 oscillators 8.4.1 pierce oscillator (fxosc) 8.4.1.1 introduction the pierce oscillator (fxosc) m odule provides a robust, low-noise and low-power clock source. the module is operated from the internally generated v dde_b supply rail (3.3 v) a nd require the minimum number of external components. it is designed for optimal start-up margin with typical crystal oscillators. 8.4.1.2 features the fxosc contains circuitry to dyna mically control current gain in the output amplitude. this ensures a signal with low harmonic distortion, low power and good noise immunity. ? high noise immunity due to input hysteresis ? low rf emissions with peak-t o-peak swing limited dynamically ? transconductance (gm) sized for optimum start-up margin for typical oscillators ? dynamic gain control eliminates the need for external curr ent limiting resistor ? integrated resistor eliminates th e need for external bias resistor in loop controlled pierce mode. ? low power consumption: ? operates from externally provided power v dde_b (3.3 v) ? amplitude control limits power ? clock monitor 8.4.1.3 modes of operation two modes of operation exist: 1. loop controlled pierce (lcp) oscillator 2. external square wave mode 8.4.1.4 block diagram figure 8-26 shows a block diagram of the fxosc.
pxd20 microcontroller reference manual, rev. 1 8-30 freescale semiconductor preliminary?subject to change without notice figure 8-26. fxosc block diagram 8.4.1.5 external signal description this section lists and describes the signals that connect off chip 8.4.1.5.1 v dde_b and v ss ? operating and ground voltage pins theses pins provide s operating voltage (v dde_b ) and ground (v ss ) for the fxosc circuitry. this allows the supply voltage to the fxosc to use an independent bypass capacitor. 8.4.1.5.2 extal and xtal ? input and output pins these pins provide the interface fo r either a crystal or a 3.3 v cmos compatible clock to control the internal clock generator circuitry. extal is the extern al clock input or the input to the crystal oscillator amplifier. xtal is the output of the crystal oscillator amplifier. the mc u internal system clock is derived from the extal input frequency. in full stop m ode (pstp = 0), the extal pin is pulled down by an internal resistor of typical 200 k ? . extal xtal gain control v dde_b = 3.3 v rf oscclk monitor_failure clock monitor peak detector
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-31 preliminary?subject to change without notice note this low-power loop-controlled circuit is not suited for overtone resonators and crystals. freescale recommends an evaluation of the layout and performance of the application board a nd chosen resonator or crysta l by the resonator or crystal supplier. the low-power nature of the circuit should be noted when performing this evaluation since the impact of stray capacitance and external disturbances can be larger th an seen with highe r power oscillators. figure 8-27. loop controlled pierce oscillat or connections (lcp mode selected) figure 8-28. external clock connections 8.4.1.6 memory map and register definition the fxosc does not contain any confi guration registers. the oscillator is enabled and disabled using the mode entry module. 8.4.1.7 functional description the fxosc module has control circuitr y to maintain the crystal oscillat or circuit voltage level to an optimal level which is determined by the amount of hysteresis being used and the maximum oscillation range. the oscillator block has two external pins, exta l and xtal. the oscillator input pin, extal, is intended to be connected to either a crystal or an external clock source . the xtal pin is an output signal that provides crysta l circuit feedback. mcu extal xtal v sspll crystal or ceramic resonator c2 c1 mcu extal xtal not connected cmos compatible external oscillator (v ddpll level)
pxd20 microcontroller reference manual, rev. 1 8-32 freescale semiconductor preliminary?subject to change without notice a buffered extal signal becomes the internal cloc k. to improve noise immunity, the oscillator is powered by the vddpll and vsspll power supply pins. 8.4.1.7.1 gain control a closed loop control system is util ized whereby the amplifier is modul ated to keep the output waveform sinusoidal and to limit the os cillation amplitude. the out put peak to peak voltage will be kept above twice the maximum hysteresis le vel of the input buffer. 8.4.1.7.2 clock monitor the clock monitor circuit is based on an internal rc time delay so that it ca n operate without any mcu clocks. if no oscclk edges are detected within this rc time dela y, the clock monitor indicates failure which asserts self-clock mode or generates a system reset depending on the state of scme bit. if the clock monitor is disabled or the presence of clocks is detected no failure is indicated.the clock monitor function is enabled/disabled by the cme control bit, described in the mc_cgm chapter. 8.4.2 external crystal oscillator (sxosc) 8.4.2.1 features ? external crystal oscillator (sxosc) digital interface ? oscillator powerdown control and status ? oscillator clock available interrupt ? oscillator bypass mode ? output clock division factors ranging from 1,2,3....32 8.4.2.2 functional description the crystal oscillator circui t includes an internal oscillator driver a nd an external crysta l circuitry. it can be used as a reference clock to spec ific modules depending on system needs. the crystal oscillator is contro lled by the osc_ctl register. the oscon bit controls the powerdown while s_osc bit provides the osci llator clock available status. after system reset, the oscillator is put to power down state and soft ware has to switch on when required. whenever the crystal oscillat or is switched on from of f state, osccnt counter st arts and when it reaches the value eocv[7:0]*512, oscillator cl ock is made available to the syst em. also an interrupt pending bit i_osc of osc_ctl register is set. an interrupt will be generated if the interrupt mask bit m_osc is set. the oscillator circuit can be bypasse d by writing oscbyp bit to osc_ctl register to ?1?. this bit can only be set by the software. system re set is needed to reset this bit. in this bypass mode , the output clock has the same polarity as external cl ock applied on extal32 pin and the osci llator status is forced to ?1?. the bypass configuration is independent of the powerdow n mode of the oscillator. the table below shows the truth table of different configurations of oscillator.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-33 preliminary?subject to change without notice the crystal oscillator clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. this di vision factor is specified by the oscdiv[4:0] bits of osc_ctl register. 8.4.2.3 register description note: osc32 is by default always on, but can be conf igured off in standby by writing oscon bit. table 8-19. truth table of crystal oscillator enable byp xtal32 extal32 ck_oscm osc mode 0 0 no crystal, high z no crystal, high z 0 power down, iddq x 1 ext clock x extal32 bypass, osc disabled 1 0 crystal crystal extal32 normal, osc enabled gnd ext clock extal32 normal, osc enabled address offset: 0x0000 base address: 0xc3fe0040 reset value: 0b00000000_10000000_00000000_00000000 0123456789101112131415 oscb yp reserved eocv rs r rw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 m_os c reserved oscdiv i_osc reserved s_osc osco n rw r rw rc r r rw table 8-20. sxosc crystal oscillator control register (osc_ctl) table 8-21. osc_ctl field descriptions field description bit 0 oscbyp : crystal oscillator bypass this bit specifies whether the oscillator should be bypassed or not. software can only set this bit. system reset is needed to reset this bit. 0: oscillator output is used as root clock. 1: extal32 is used as root clock. bits 1-7 reserved bits 8-15 eocv[7:0] : end of count value these bits specify the end of count value to be used for comparison by the oscillator stabilization counter osccnt after reset or whenever it is swit ched on from the off stat e. this counting period ensures that external oscillator clock signal is stab le before it can be selected by the system. when oscillator counter reaches the value eocv[7:0]*512 , oscillator available interrupt request is generated. the reset value of this field depends on the device specificat ion. the osccnt counter will be kept under reset if oscillator bypass mode is selected.
pxd20 microcontroller reference manual, rev. 1 8-34 freescale semiconductor preliminary?subject to change without notice note: osc_ctl register is writable only in supervisor mode. 8.4.3 sirc digital interface 8.4.3.1 introduction the sirc digital interface controls the internal low power 128 khz rc oscillator (sirc). it holds control and status registers ac cessible for application. 8.4.3.2 slow internal rc oscillator (128 khz) the sirc provides a low frequency (f sirc ) clock in the range of tens of khz requiring less current consumption. this clock can be used as reference clock when a fixed base time is required for specific modules. the sirc is always on in all device modes. the sirc clock can be further divide d by a configurable divi sion factor in the range 1 to 32 to generate the divided clock to match system requirements. th is division factor is sp ecified by the lprcdiv[4:0] bits of sirc_ctl register. after a power-on reset, the sirc is trimmed using a factory test valu e stored in test flash memory. however, after a power-on reset the test flash memory value is not visible at sirc_c tl[lprctrim] and this field shows a value of zero. therefore, one should be aware that the sirc_ctl[lprctrim] does not reflect the current trim value until someone has written to this field. particular atte ntionshould be paid to this feature when a read-modify-write operation is initiated on sirc_ctl, because a sirctrim value bit 16 m_osc : crystal oscillator clock interrupt mask 0: crystal oscillator clock interrupt is masked. 1: crystal oscillator clock interrupt is enabled. bits 17-18 reserved bits 19-23 oscdiv[4:0] : crystal oscillator clock division factor these bits specify the crystal osci llator output clock division factor. the output clock is divided by the factor oscdiv+1. bit 24 i_osc : crystal oscillator clock interrupt this bit is set by hardware when osccnt counter reaches the count value eocv[7:0]*512. it is cleared by software by writing ?1?. 0: no oscillator clock interrupt occurred. 1: oscillator clock interrupt pending. bits 25-29 reserved bit 30 s_osc : crystal oscillator statusl 0: crystal oscillator output clock is not stable. 1: crystal oscillator is providing a stable clock. bit 31 oscon : crystal oscillator powerdown control 0: crystal oscillator is switched off. 1: crystal oscillator is switched on. table 8-21. osc_ctl field descriptions
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-35 preliminary?subject to change without notice of zero may be unintentiona lly written back and this may alter the sirc frequency. in this case, the sirc should be calibrated using the cmu or it should be made sure that you only write to the upper 16 bits of this sirc_ctl. in this oscillator, two's complement trimming met hod is implemented. thus, th e trimming code increases from -16 to 15. as the trimming code increases, the in ternal time constant incr eases and frequency reduces. please refer to device datasheet for averag e frequency variation of the trimming step. 8.4.3.3 register description note: sirc_ctl register is writable only in supervisor mode. address offset: 0x0000 base address: 0xc3fe_0080 reset value: 0b00000000_00000000_00000011_00000000 0123456789101112131415 reserved lprctrim rrw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved lprcdiv reserved s_lpr c reserved rrwrrr figure 8-29. slow internal rc control register (sirc_ctl) table 8-22. slow internal rc control register (sirc_ctl) field descriptions field description bits 0-10 reserved bits 11-15 lprctrim[4:0] : low power rc trimming bits note: all configurations cannot be used. plea se refer to the device data sheet. bits 16-18 reserved bits 19-23 lprcdiv[4:0] : low power rc clock division factor these bits specify the low power rc oscillator outpu t clock division factor. the output clock is divided by the factor lprcdiv+1. bits 24-26 reserved bits 27 s_lprc : low power rc clock status 0: lprc is not providing a stable clock. 1: lprc is providing a stable clock. bits 28-31 reserved
pxd20 microcontroller reference manual, rev. 1 8-36 freescale semiconductor preliminary?subject to change without notice 8.4.4 firc digital interface 8.4.4.1 introduction the firc digital interface controls the fast internal 16 mhz rc oscillator (firc). it holds control and status registers accessi ble for application. 8.4.4.2 functional description (16 mhz) the main rc oscillator provides a high-frequency (f firc ) clock. this clock can be used to accelerate the exit from reset and wakeup sequence fr om low power modes of the system. it is controlled by the mc_me module based on the current device mode. the clock source status is updated in s_rc bit of me_gs register. please refer to mc_me specification for further details. the firc clock can be further divide d by a configurable divi sion factor in the range 1 to 32 to generate the divided clock to match system re quirements. this division factor is specified by the rcdiv[4:0] bits of the firc_ctl register. after a power-on reset, the firc is trimmed using a factory test valu e stored in test flash memory. however, after a power-on reset the test flash memo ry value is not visible at firc_ctl[rctrim] and this field shows a value of zero. therefore, be aw are that the firc_ctl[rct rim] does not reflect the current trim value until you have wr itten to this field. pay particular attention to this feature when you initiate a read-modify-write operation on firc_c tl, because a rctrim value of zero may be unintentionally written back and this may alter the firc frequency. in this case, you should calibrate the firc using the cmu or be sure that you only wr ite to the upper 16 bits of this firc_ctl. in this oscillator, two's comple ment trimming method is implemente d. so the trimming code increases from -32 to 31. as the trimming code increases, th e internal time constant increases and frequency reduces. please refer to device datasheet for average frequency variation of the trimming step. during the standby mode entry process, the rc osci llator is controlled base d on the rcon bit of the me_standby_mc register. the is th e last step in the standby entry sequence. on any system wake-up event, the device exits standby mode and switches on the rc oscillator . the actual powerdown status of the rc oscillator when the device is in standby is provided by the s_rc_stdby bit of the firc_ctl register.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-37 preliminary?subject to change without notice 8.4.4.3 register description note: firc_ctl register is writable only in supervisor mode. 8.5 frequency-modulated ph ase-locked loop (fmpll) 8.5.1 introduction this section describes the featur es and functions of the two inde pendent fmpll modules (fmpll_0 and fmpll_1) implemented in pxd20. address offset: 0x0000 base address: 0xc3fe_0060 reset value: 0b00000000_00000000_00000000_00000000 0123456789101112131415 reserved rctrim r rw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rcdiv reserved s_rc_ stdby reserved rrw rwr table 8-23. firc oscillator control register (firc_ctl) table 8-24. firc oscillator control register (firc_ctl) field descriptions field description bits 0-9 reserved bits 10-15 rctrim[5:0] : low power rc trimming bits note: not all configurations can be used. pl ease refer to the device data sheet. bits 16-18 reserved bits 19-23 rcdiv[4:0] : low power rc clock division factor these bits specify the low power rc oscillator outpu t clock division factor. the output clock is divided by the factor lprcdiv+1. bits 24-25 reserved bits 26 s_rc_stdby : mrc oscillator powerdown status in standby mode this bit specifies whether mrc oscillator is powered down or not during standby mode entry. this bit can be cleared by writing ? 1?. 0: mrc is not switched off during standby. 1: mrc is switched off during standby. bits 28-31 reserved
pxd20 microcontroller reference manual, rev. 1 8-38 freescale semiconductor preliminary?subject to change without notice 8.5.2 overview the fmplls enable the user to generate high speed system clocks from a common 4 mhz to 120 mhz input clock. further, the fmplls support programmabl e frequency modulation of the system clock. the pll multiplication factor, out put clock divider ratio are all software configurable. note the user must take care not to program device with frequency higher than allowed (no hardware check). the fmpll?s block di agram is shown in figure 8-30 . figure 8-30. fmpll block diagram 8.5.3 features each fmpll has the foll owing major features: ? input clock frequency from 4 mhz to 120 mhz ? voltage controlled oscillator (vco) range from 256 mhz to 512 mhz ? frequency modulated pll ? modulation enabled/disabled through software ? triangle wave modulation ? programmable modulation depth ? 0.25% to 4% deviation fr om center spread frequency ? ?0.5% to ?8% deviation fr om down spread frequency ? programmable modulation frequency dependent on reference frequency ? self-clocked mode (scm) operation ? five available modes ? normal mode ? progressive clock switching ? normal mode with sscg ? powerdown mode ? 1:1 mode (fmpll0 only) buffer charge pump low pass filter vco idf div2 ndiv loop frequency divider fxosc mode odf div4 mode phi
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-39 preliminary?subject to change without notice 8.5.4 memory map 1 table 8-25 shows the memory map locations. addresses are given as offsets of the module base address. 8.5.5 register description the pll operation is controlled by two registers. thos e registers can only be writ ten in supervisor mode. 8.5.5.1 control register (cr) 1.fmpll_x are mapped through the me_cgm register slot table 8-25. fmpll memory map address register access location base: 0xc3fe00a0 (fmpll0) 0xc3fe00c0 (fmpll1) 0x0000 control register (cr) r/w on page 8-39 0x0004 modulation register (mr) special on page 8-42 offset 0x0000 access: user read/write 0123456789101112131415 r 0 0 idf odf 0 ndiv w reset 0000000101000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 en_pll _sw mode unlock _once 0 i_lock s_lock pll_fail _mask pll_fail _flag 0 w w1c w1c reset 0000000000000000 table 8-26. control register (cr) table 8-27. cr field descriptions field description idf the value of this field sets the pll input division factor as described in ta bl e 8 - 2 8 . the reset value is set during integration. odf the value of this field sets the pll output division factor as described in ta b l e 8 - 2 9 . the reset value is set during integration. ndiv the value of this field sets the p ll loop division factor as described in ta bl e 8 - 3 0 . the reset value is set during integration.
pxd20 microcontroller reference manual, rev. 1 8-40 freescale semiconductor preliminary?subject to change without notice en_pll_sw this bit is used to enable progressive clock switch ing. after the pll locks, t he pll output initially is divided by 8 then progressively divides down until divide by 1. 0 => progressive clock switching disabled 1 => progressive clock switching enabled note: the pll output should not be used if a non-c hanging clock is needed (such as for serial communications) until the division has finished mode this bit is used to activate the 1:1 mode. unlock_once this bit is a sticky indication of pll loss of lock condition. unlock_once is set when the pll loses lock. whenever the pll reacquires lock, unlock_once remains set. only a power-on reset can clear this bit. i_lock this bit is set by hardware whenever there is a lock/unlock event.it is cleared by software, writing 1. s_lock this bit is an indication of whether the pll has acquired lock. 0 => pll unlocked 1 => pll locked pll_fail_mask this bit is used to mask the pll_fail output. 0 => pll_fail not masked 1 => pll_fail masked pll_fail_flag this bit is asynchronously set by hardware whenever a loss of lock event occurs while pll is switched on. it is cleared by software, writing 1. table 8-28. input divide ratios idf input divide ratio (r inp ) 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12 1100 divide by 13 1101 divide by 14 table 8-27. cr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-41 preliminary?subject to change without notice 1110 divide by 15 1111 clock inhibit table 8-29. output divide ratios odf output divide ratio (r out ) 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 table 8-30. loop divide ratios ndiv loop divide ratio (r loop ) 0000000-0011111 na 0100000 divide by 32 0100001 divide by 33 0100010 divide by 34 ... ... 1011111 divide by 95 1100000 divide by 96 1100001-1111111 na table 8-28. input divide ratios (continued) idf input divide ratio (r inp )
pxd20 microcontroller reference manual, rev. 1 8-42 freescale semiconductor preliminary?subject to change without notice 8.5.5.2 modulation register (mr) offset 0x0004 access: user read/write 01234567 8 9101112131415 rstr b_b ypa ss 0 spr d_s el mod_period w reset00000000 0 00 0 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fm_ en inc_step w reset00000000 0 0? 1 0 0000 table 8-31. modulation register (mr) table 8-32. mr field descriptions field description 0 strb_bypass strobe bypass the strb_bypass signal is used to bypass the strb signal used inside pll to latch the correct values for control bits (inc_step, mod_period and sprd_sel). 0 = strb is used to latch pll modulation control bits 1 = strb is bypassed. in this case control bits need to be static. the control bits must be changed only when pll is in power down mode. 2 sprd_sel spread type selection the sprd_sel control the spread type in frequency modulation mode. 0 = center spread 1 = down spread 3-15 mod_period modulation period the mod_period field is the binary equivalent of the value modperiod derived from following formula: where: fref: represents the frequency of the feedback divider fmod : represents the modulation frequency modperiod f ref 4f mod ? -------------------- =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-43 preliminary?subject to change without notice 8.5.6 functional description 8.5.6.1 normal mode in normal mode the pll inputs are driven by the cr (see section 8.5.5.1, control register (cr) ). this means that, when the pll is in lock state, the p ll output clock (phi) is derived by the reference clock (clkin) through equation 8-1 : eqn. 8-1 where the value of r loop , r inp , and r out are set in the cr and can be derived from table 8-28 , table 8-29 , and table 8-30 . some examples are given in table 8-33 . 16 fm_en frequency modulation enable the fm_en enables the frequency modulation. 0 = frequency modulation disabled 1= frequency modulation enabled 17-31 inc_step increment step the inc_step field is the binary equivalent of the value incstep derived from following formula: where: md : represents the peak modulation depth in percentage (center spread -- pk-pk=+/-md, downspread -- pk-pk=-2*md) mdf : represents the nominal value of loop di vider (ndiv in pll control register) table 8-33. examples of typical pll settings crystal frequency (mhz) pll output frequency (mhz) dram clock frequency (mhz) register values vco frequency (mhz) idf odf ndiv 8 32 64 0 1 32 256 64 128 0 1 64 512 80 160 0 0 40 320 124 248 0 0 62 496 16 32 64 0 1 32 256 64 128 0 1 64 512 80 160 0 0 40 320 124 248 0 0 62 496 table 8-32. mr field descriptions (continued) field description incstep round 2 15 1 ? ?? md ? mdf ? 100 5 ? modperiod ? -------------------------------------------------------------- - ?? ?? = phi clkin r loop ? r inp r out ? ---------------------------------- - =
pxd20 microcontroller reference manual, rev. 1 8-44 freescale semiconductor preliminary?subject to change without notice 8.5.6.2 progressive clock switching progressive clock switching allows to switch system clock to pll output clock stepping through different division factors. this means that th e current consumption gradually incr eases and so the voltage regulator has a better response. this feature can be enabled by pr ogramming the en_pll_sw bit in cr. th en, when the input pin pll_select goes high, the output cloc k ck_pll_div will progres sively increase its freque ncy as described in table 8-34 and figure 8-31 . figure 8-31. diagram of progressive clock switching 8.5.6.3 normal mode with frequency modulation the fmpll default mode is wit hout frequency modulation enabled. when frequency modulation is enabled, however, two parameters must be set to ge nerate the desired level of modulation: the period, and the step. the modulation waveform is always a triangle wave and its sh ape is not programmable. fm modulation shall be activated in two steps: 10 30 60 0 2 48 480 60 120 0 1 48 480 80 160 1 0 64 320 125 250 0 0 50 500 table 8-34. progressive clock switching on pll_select rising edge number of pll output clock cycles ck_pll_frequency (pll output clock frequency) 8 (ck_pll_out frequency)/8 16 (ck_pll_out frequency)/4 32 (ck_pll_out frequency)/2 onward (ck_pll_out frequency) table 8-33. examples of typical pll settings crystal frequency (mhz) pll output frequency (mhz) dram clock frequency (mhz) register values vco frequency (mhz) idf odf ndiv ck_pll_out ck_pll_div ?? ?? ?? ??
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-45 preliminary?subject to change without notice ? first: configure the fm modulation char acteristics: mod_period, inc_step. ? second: enable the fm modulation by setting the mr [fm_en] bit. fm modulated mode can be enabled only when pll is in lock state. to latch these values inside the pll, two ways are usable depending on the value of strb_bypass register bit in mr. if strb_bypass is low, the modulat ion [parameters are latched in the pll only when the strb signal goes high for at least 2 cycles of infin clock. the st rb signal is automatically generated in the plld when the modulation is enabled (fm_en goes high) if the pll is locked (s_lock=1) or when the modulation has been enabled (fm_en=1) and p ll enters in lock state (s_lock goes high). if strb_bypass is high, the strb signal is bypassed. in this case, control bits (m od_period[12:0], inc_step[14:0], spread_cont rol) need to be static or hardwi red to constant values. the control bits must be changed only when the pll is in power down mode. the modulation depth in % is note the user must ensure that the produc t of inctep and modperiod is less than (2 15 -1). figure 8-32. pll frequency modulation modes modulationdepth 100 5 ? incstepxmodperiod ? 2 15 1 ? ?? mdf ? -------------------------------------------------------------------------------------------- - ?? ?? =
pxd20 microcontroller reference manual, rev. 1 8-46 freescale semiconductor preliminary?subject to change without notice 8.5.6.4 powerdown mode the pll can be switched off when not required to achieve lower consumption by programming the registers me_x_mc register on mc_me module. 8.5.6.5 1:1 mode (fmpll0 only) 1:1 mode is set by assertin g the mode bit in cr (see section 8.5.5.1, contro l register (cr) ). an external input signal (mode_en) has been provided to disable this feature. if mode_en is ti ed to 0, the mode bit in cr is disabled and there is no way to activate 1:1 mode. in 1:1 mode the inputs of the pll are driven by cr and mr, but the division factors and the modulation parameters have no influe nce on the output clock. in fact the divi ders and the sscg control are bypassed inside the pll. the pll output clock (phi) fre quency is determined by the following relation: 8.5.7 recommendations to avoid any unpredictable behavior of the pll cl ock, it is recommended to respect the following guidelines: ? the pll vco frequency should re side in the range 256 mhz to 512 mhz. care is required when programming the multiplication and division factors to respect this requirement. ? the user must change the mult iplication, division factors only wh en the pll output clock is not selected as system clock. mod_period, inc_ step, spread_sel bits should be modified before activating the fm modulated mode. then st robe has to be generated to enable the new settings. if strb_byp is set to 1 then mod_period, inc_step and spread_sel can be modified only when pll is in power down mode. ? use progressive clock switching 8.6 clock monito r unit (cmu) 8.6.1 introduction the clock monitor unit (cmu), also referred to as clock quality checker or cl ock fault detector, serves two purposes. the main task is to permanently supervise the integrity of the device?s syst em clock sources, i.e., crystal oscillator fxosc, firc, and fmpll 0. if fmpll0 leaves an upper or lower frequency boundary or the crystal oscillator fails it can detect and forward this kind of event towards the mode and clock management unit. the clock management unit in turn can then switch to a safe mode where it uses a safe fallback clock source such as an on-chip rc os cillator, reset the device or generate the interrupt according to the system needs. phi clkin 2 ------------ - =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-47 preliminary?subject to change without notice it can also monitor external crysta l oscillator clock which must be gr eater than the internal rc clock divided by a division factor given by rcdiv[1:0] of cmu_csr regist er and generates a system clock transition request or an interrupt when enabled. the second task of the cmu is to provide a frequenc y meter, which allows to measure the frequency of one clock source vs. a reference clock. this is us eful to allow the calibration of the on-chip rc oscillator(s), as well as being able to correct/calcula te the time deviation of a counter which is clocked by the rc oscillator. note the cmu does not monitor sxosc, sirc, or fmpll_1. figure 8-33. cmu component interaction 8.6.2 main features ? rc oscillator frequency measurement ? external oscillator clock monitori ng with respect to ck_firc/n clock ? pll clock frequency monitoring wi th respect to ck_firc/4 clock ? event generation for various failur es detected insi de monitoring unit cmu ck 0 (reference) ck fxosc ck pll olr fll ircosc_clk 16 mhz fxosc_clk 4??16 m fmpll_0 64 mhz fxosc valid (on and stable)/off fmpll_0 valid (on and locked)/off mc_cgm fcu loss of crystal fmpll_0 freq. out of range
pxd20 microcontroller reference manual, rev. 1 8-48 freescale semiconductor preliminary?subject to change without notice 8.6.3 block diagram figure 8-34. clock monitor unit diagram 8.6.4 memory map and register description the memory map of the cmu is shown in the following table. table 8-35. rc digital interface register set - base address 0xc3fe_0100 address offset register name location 0x00 control status register (cmu_csr) on page 8-49 0x04 frequency display register (cmu_fdr) on page 8-50 0x08 high frequency reference register fmpll0(cmu_hfrefr_a) on page 8-50 0x0c low frequency reference register fmpll0(cmu_lfrefr_a) on page 8-51 0x10 interrupt status register (cmu_isr) on page 8-51 0x14 reserved ? 0x18 measurement duration register (cmu_mdr) on page 8-52 cmu_mdr register fxosc supervisor fosc < frc fast / n cmu_href register fixed prescaler /4 fpll > href or fpll < frc fast / 4 fpll < lfref cmu_lfref register frequency meter cmu_fdr register pll supervisor olr_evt flc_evt_a fhh_evt_a fll_evt_a fxosc on/off from mc_me pll on/off from mc_me mux 1 clksel1[1:0] 00 01 10 11 ck_firc ck_firc ck_sirc ck_sxosc ck_fxosc ckpll_a
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-49 preliminary?subject to change without notice 8.6.4.1 control status register (cmu_csr) address offset: 0x00 reset value: 0x00000006 0123456789101112131415 reserved sfm reserved rrsr 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved clksel1 reserved rcdiv cme_ a r rw r rw rw table 8-36. control status register (cmu_csr) table 8-37. control status register (cmu_csr) field descriptions field description 8 sfm start frequency measure the software can only set this bit to start a clock frequency measure. it is reset by hardware when the measure is ready in the cmu_fdr register. 0: frequency measurement is completed or not yet started. 1: frequency measurement is not completed. 22-23 clksel1 rc oscillator(s) selection bit clksel1 selects the clock to be measured by the frequency meter. 00: ck_firc is selected. 01: ck_sirc is selected. 10: ck_sxosc crystal oscillator clock is selected. 11: ck_firc is selected. 29-30 rcdiv[1:0 ] rc clock division factor these bits specify the rc clock divisi on factor. the output clock is ck_irc fast divided by the factor 2 rcdiv . this output clock is used to compare with ck_fxosc for crystal clock monitor feature.the clock division coding is as follows. 00: clock divided by 1 (no division) 01: clock divided by 2 10: clock divided by 4 11: clock divided by 8 31 cme_a fmpll0 clock monitor enable 0: fmpll0 monitor is disabled. 1: fmpll0 monitor is enabled.
pxd20 microcontroller reference manual, rev. 1 8-50 freescale semiconductor preliminary?subject to change without notice 8.6.4.2 frequency display register (cmu_fdr) . 8.6.4.3 high frequency reference register fmpll0 (cmu_hfrefr) address offset: 0x04 reset value: 0x00000000 0123456789101112131415 reserved fd[19:16] rr 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fd[15:0] r table 8-38. frequency display register (cmu_fdr) table 8-39. frequency display register (cmu_fdr) field descriptions field description 12-31 fd measured frequency bits this register displays the measured frequency frc with respect to fosc. the measured value is given by the following formula: frc = (fosc * md) / n, where n is the value in cmu_fdr register address offset: 0x08 reset value: 0x00000fff 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved hfref[11:0] rrw table 8-40. high frequency reference register fmpll0 table 8-41. high frequency reference register fmpll0 field descriptions field description 20-31 hfref high frequency reference value these bits determine the high reference valu e for the fmpll0 clock. the reference value is given by: (hfref [11:0]/16) * (frc fast /4).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-51 preliminary?subject to change without notice 8.6.4.4 low frequency reference register fmpll0 (cmu_lfrefr) 8.6.4.5 interrupt status register (cmu_isr) address offset: 0x0c reset value: 0x00000000 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved lfref[11:0] rrw table 8-42. low frequency reference register fmpll0 table 8-43. low frequency reference register fmpll0 field descriptions field description 20-31 lfref low frequency reference value these bits determine the low reference value for the fmpll0. the reference value is given by: (lfref[11:0]/16) * (frc fast /4). address offset: 0x10 reset value: 0x00000000 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved fhhi flli olri r rcrcrc table 8-44. interrupt status register (cmu_isr) table 8-45. interrupt status regi ster (cmu_isr) field descriptions field description 29 fhhi fmpll0 clock frequency higher than high reference interrupt this bit is set by hardware when ck_fmpll frequency becomes higher than hfref value and ck_fmpll is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0: no fhh event. 1: fhh event is pending.
pxd20 microcontroller reference manual, rev. 1 8-52 freescale semiconductor preliminary?subject to change without notice 8.6.4.6 measurement duration register (cmu_mdr) 8.6.5 functional description the names of the clocks involved in th is block have the following meaning: ? ck_fxosc: clock coming from th e external crystal oscillator. ? ck_sirc: clock coming from the low frequency internal rc oscillator. ? ck_firc: clock coming from the high frequency internal rc oscillator. ? ck_pll: clock coming from the pll. ? fosc: frequency of external crystal oscillator clock. ? frcslow: frequency of low fre quency internal rc oscillator. 30 flli fmpll0 clock frequency less than low reference event this bit is set by hardware when ck_fmpll frequency becomes lower than lfref value and ck_fmpll is ?on? as signalled by the mc_m e. it can be cleared by software by writing ?1?. 0: no fll event. 1: fll event is pending. 31 olri oscillator frequency less than rc frequency event this bit is set by hardware when the frequency of ck_fxosc is less than ck_firc/2 rcdiv frequency and ck_fxosc is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0: no olr event. 1: olr event is pending. address offset: 0x18 reset value: 0x00000000 0123456789101112131415 reserved md[19:16] rrw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 md[15:0] rw table 8-46. measurement duration register (cmu_mdr) table 8-47. measurement duration register (cmu_mdr) field descriptions field description 12-31 md measurement duration bits this register displays the measured duration in term of irc clock cycles. this value is loaded in the frequency meter downcounter. wh en sfm bit is set to ?1?, downcounter starts counting. table 8-45. interrupt status register (c mu_isr) field descriptions (continued)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-53 preliminary?subject to change without notice ? frcfast: frequency of high fr equency internal rc oscillator. ? fpll: frequency of fmpll clock. 8.6.5.1 crystal clock monitor if fosc is smaller than frcfast divided by 2 rcdiv . bits of cmu_csr and th e ck_fxosc is ?on? as signalled by the mc_me then: ? an event pending bit olri in cmu_isr is set. ? a failure event olr is signalled to the mc_rgm which in turn can automatically switch to a safe fallback clock and generate an interrupt or a reset. note f_xosc must be grea ter than f_firc / 2^rcdiv by at least 0.5 mh z in order to gua rantee correct xosc monitoring. 8.6.5.2 pll clock monitor the pll clock ck_pll frequency can be monitored by programming cme bit of cmu_csr register to ?1?. ck_pll monitor starts as soon as cme bit is set. this monitor can be disabled at any time by writing cme bit to ?0?. if ck_pll frequency (fpll) is grea ter than a reference value determin ed by the hfref[11:0] bits of cmu_hfrefr and the ck _pll is ?on? as signalled by the mc_me then ? an event pending bit fhhi in cmu_isr is set, ? a failure event is signalled to the mc_rgm and fault co llection unit which in turn can generate an interrupt or a reset. if fpll is less than a reference clock frequency (f rc/4) and the ck_pll is ?on? as signalled by the mc_me then an event pending bit flci in cmu_isr will be set. if fpll is less than a reference value determined by the lfref[11:0] bits of cmu_lfrefr and the ck_pll is ?on? as signalled by the mc_me then ? an event pending bit flli in cmu_isr is set, ? a failure event fll is signalled to the mc_rgm which can generate an interrupt or a reset. note f_pll must be greater than f_firc / 4 by at least 0.5 mhz in order to guarantee correct pll monitoring. 8.6.5.3 frequency meter the purpose of frequency meter is to calibrate th e internal rc oscillator (ck_irc) using a known frequency. hint: this value can then be stored into the flash so that application software can reuse it later on.
pxd20 microcontroller reference manual, rev. 1 8-54 freescale semiconductor preliminary?subject to change without notice the reference clock will be always the fxosc. the frequency meter returns a precise value of ck_32k, ck_firc or ck_sirc according to the clksel1 bit va lue. the measure starts when the sfm (start frequency measure) bit in the cmu_csr is set to ?1?. the measurement duration is given by the cmu_mdr register in numbers of cloc k cycles of the selected clock s ource with a widt h of 20 bits. the sfm bit is reset to ?0? by the hardware once the fre quency measurement is done and the count is loaded in the cmu_fdr. the frequency frc can be derived from the value loaded in the cmu_fdr register as follows: frc = (fosc * md) / n, eqn. 8-2 where n is the value in the cmu_fdr regist er and md is the value in the cmu_mdr. frequency meter by default evaluate s ck_firc, but the software can swap to ck_sirc or ck_sxosc by programming the clksel bits in the cmu_csr register.the ckon bits indicate which is the actual clock at the output of the multiplexer mux1. 8.7 clock monito r unit (cmu) 8.7.1 introduction the clock monitor unit (cmu), also referred to as clock quality checker or cl ock fault detector, serves two purposes. the main task is to permanently supervise the integrity of the device?s syst em clock sources, i.e., crystal oscillator fxosc, firc, and fmpll 0. if fmpll0 leaves an upper or lower frequency boundary or the crystal oscillator fails it can detect and forward this kind of event towards the mode and clock management unit. the clock management unit in turn can then switch to a safe mode where it uses a safe fallback clock source such as an on-chip rc os cillator, reset the device or generate the interrupt according to the system needs. it can also monitor external crysta l oscillator clock which must be gr eater than the internal rc clock divided by a division factor given by rcdiv[1:0] of cmu_csr regist er and generates a system clock transition request or an interrupt when enabled. the second task of the cmu is to provide a frequenc y meter, which allows to measure the frequency of one clock source vs. a reference clock. this is us eful to allow the calibration of the on-chip rc oscillator(s), as well as being able to correct/calcula te the time deviation of a counter which is clocked by the rc oscillator. note the cmu does not monitor sxosc, sirc, or fmpll_1.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-55 preliminary?subject to change without notice figure 8-35. cmu component interaction 8.7.2 main features ? rc oscillator frequency measurement ? external oscillator clock monitori ng with respect to ck_firc/n clock ? pll clock frequency monitoring wi th respect to ck_firc/4 clock ? event generation for various failur es detected insi de monitoring unit cmu ck 0 (reference) ck fxosc ck pll olr fll ircosc_clk 16 mhz fxosc_clk 4??16 m fmpll_0 64 mhz fxosc valid (on and stable)/off fmpll_0 valid (on and locked)/off mc_cgm fcu loss of crystal fmpll_0 freq. out of range
pxd20 microcontroller reference manual, rev. 1 8-56 freescale semiconductor preliminary?subject to change without notice 8.7.3 block diagram figure 8-36. clock monitor unit diagram 8.7.4 memory map and register description the memory map of the cmu is shown in the following table. table 8-48. rc digital interface register set - base address 0xc3fe_0100 address offset register name location 0x00 control status register (cmu_csr) on page 8-49 0x04 frequency display register (cmu_fdr) on page 8-50 0x08 high frequency reference register fmpll0(cmu_hfrefr_a) on page 8-50 0x0c low frequency reference register fmpll0(cmu_lfrefr_a) on page 8-51 0x10 interrupt status register (cmu_isr) on page 8-51 0x14 reserved ? 0x18 measurement duration register (cmu_mdr) on page 8-52 cmu_mdr register fxosc supervisor fosc < frc fast / n cmu_href register fixed prescaler /4 fpll > href or fpll < frc fast / 4 fpll < lfref cmu_lfref register frequency meter cmu_fdr register pll supervisor olr_evt flc_evt_a fhh_evt_a fll_evt_a fxosc on/off from mc_me pll on/off from mc_me mux 1 clksel1[1:0] 00 01 10 11 ck_firc ck_firc ck_sirc ck_sxosc ck_fxosc ckpll_a
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-57 preliminary?subject to change without notice 8.7.4.1 control status register (cmu_csr) address offset: 0x00 reset value: 0x00000006 0123456789101112131415 reserved sfm reserved rrsr 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved clksel1 reserved rcdiv cme_ a r rw r rw rw table 8-49. control status register (cmu_csr) table 8-50. control status register (cmu_csr) field descriptions field description 8 sfm start frequency measure the software can only set this bit to start a clock frequency measure. it is reset by hardware when the measure is ready in the cmu_fdr register. 0: frequency measurement is completed or not yet started. 1: frequency measurement is not completed. 22-23 clksel1 rc oscillator(s) selection bit clksel1 selects the clock to be measured by the frequency meter. 00: ck_firc is selected. 01: ck_sirc is selected. 10: ck_sxosc crystal oscillator clock is selected. 11: ck_firc is selected. 29-30 rcdiv[1:0 ] rc clock division factor these bits specify the rc clock divisi on factor. the output clock is ck_irc fast divided by the factor 2 rcdiv . this output clock is used to compare with ck_fxosc for crystal clock monitor feature.the clock division coding is as follows. 00: clock divided by 1 (no division) 01: clock divided by 2 10: clock divided by 4 11: clock divided by 8 31 cme_a fmpll0 clock monitor enable 0: fmpll0 monitor is disabled. 1: fmpll0 monitor is enabled.
pxd20 microcontroller reference manual, rev. 1 8-58 freescale semiconductor preliminary?subject to change without notice 8.7.4.2 frequency display register (cmu_fdr) . 8.7.4.3 high frequency reference register fmpll0 (cmu_hfrefr) address offset: 0x04 reset value: 0x00000000 0123456789101112131415 reserved fd[19:16] rr 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fd[15:0] r table 8-51. frequency display register (cmu_fdr) table 8-52. frequency display register (cmu_fdr) field descriptions field description 12-31 fd measured frequency bits this register displays the measured frequency frc with respect to fosc. the measured value is given by the following formula: frc = (fosc * md) / n, where n is the value in cmu_fdr register address offset: 0x08 reset value: 0x00000fff 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved hfref[11:0] rrw table 8-53. high frequency reference register fmpll0 table 8-54. high frequency reference register fmpll0 field descriptions field description 20-31 hfref high frequency reference value these bits determine the high reference valu e for the fmpll0 clock. the reference value is given by: (hfref [11:0]/16) * (frc fast /4).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-59 preliminary?subject to change without notice 8.7.4.4 low frequency reference register fmpll0 (cmu_lfrefr) 8.7.4.5 interrupt status register (cmu_isr) address offset: 0x0c reset value: 0x00000000 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved lfref[11:0] rrw table 8-55. low frequency reference register fmpll0 table 8-56. low frequency reference register fmpll0 field descriptions field description 20-31 lfref low frequency reference value these bits determine the low reference value for the fmpll0. the reference value is given by: (lfref[11:0]/16) * (frc fast /4). address offset: 0x10 reset value: 0x00000000 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved fhhi flli olri r rcrcrc table 8-57. interrupt status register (cmu_isr) table 8-58. interrupt status regi ster (cmu_isr) field descriptions field description 29 fhhi fmpll0 clock frequency higher than high reference interrupt this bit is set by hardware when ck_fmpll frequency becomes higher than hfref value and ck_fmpll is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0: no fhh event. 1: fhh event is pending.
pxd20 microcontroller reference manual, rev. 1 8-60 freescale semiconductor preliminary?subject to change without notice 8.7.4.6 measurement duration register (cmu_mdr) 8.7.5 functional description the names of the clocks involved in th is block have the following meaning: ? ck_fxosc: clock coming from th e external crystal oscillator. ? ck_sirc: clock coming from the low frequency internal rc oscillator. ? ck_firc: clock coming from the high frequency internal rc oscillator. ? ck_pll: clock coming from the pll. ? fosc: frequency of external crystal oscillator clock. ? frcslow: frequency of low fre quency internal rc oscillator. 30 flli fmpll0 clock frequency less than low reference event this bit is set by hardware when ck_fmpll frequency becomes lower than lfref value and ck_fmpll is ?on? as signalled by the mc_m e. it can be cleared by software by writing ?1?. 0: no fll event. 1: fll event is pending. 31 olri oscillator frequency less than rc frequency event this bit is set by hardware when the frequency of ck_fxosc is less than ck_firc/2 rcdiv frequency and ck_fxosc is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0: no olr event. 1: olr event is pending. address offset: 0x18 reset value: 0x00000000 0123456789101112131415 reserved md[19:16] rrw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 md[15:0] rw table 8-59. measurement duration register (cmu_mdr) table 8-60. measurement duration register (cmu_mdr) field descriptions field description 12-31 md measurement duration bits this register displays the measured duration in term of irc clock cycles. this value is loaded in the frequency meter downcounter. wh en sfm bit is set to ?1?, downcounter starts counting. table 8-58. interrupt status register (c mu_isr) field descriptions (continued)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 8-61 preliminary?subject to change without notice ? frcfast: frequency of high fr equency internal rc oscillator. ? fpll: frequency of fmpll clock. 8.7.5.1 crystal clock monitor if fosc is smaller than frcfast divided by 2 rcdiv . bits of cmu_csr and th e ck_fxosc is ?on? as signalled by the mc_me then: ? an event pending bit olri in cmu_isr is set. ? a failure event olr is signalled to the mc_rgm which in turn can automatically switch to a safe fallback clock and generate an interrupt or a reset. note f_xosc must be grea ter than f_firc / 2^rcdiv by at least 0.5 mh z in order to gua rantee correct xosc monitoring. 8.7.5.2 pll clock monitor the pll clock ck_pll frequency can be monitored by programming cme bit of cmu_csr register to ?1?. ck_pll monitor starts as soon as cme bit is set. this monitor can be disabled at any time by writing cme bit to ?0?. if ck_pll frequency (fpll) is grea ter than a reference value determin ed by the hfref[11:0] bits of cmu_hfrefr and the ck _pll is ?on? as signalled by the mc_me then ? an event pending bit fhhi in cmu_isr is set, ? a failure event is signalled to the mc_rgm and fault co llection unit which in turn can generate an interrupt or a reset. if fpll is less than a reference clock frequency (f rc/4) and the ck_pll is ?on? as signalled by the mc_me then an event pending bit flci in cmu_isr will be set. if fpll is less than a reference value determined by the lfref[11:0] bits of cmu_lfrefr and the ck_pll is ?on? as signalled by the mc_me then ? an event pending bit flli in cmu_isr is set, ? a failure event fll is signalled to the mc_rgm which can generate an interrupt or a reset. note f_pll must be greater than f_firc / 4 by at least 0.5 mhz in order to guarantee correct pll monitoring. 8.7.5.3 frequency meter the purpose of frequency meter is to calibrate th e internal rc oscillator (ck_irc) using a known frequency. hint: this value can then be stored into the flash so that application software can reuse it later on.
pxd20 microcontroller reference manual, rev. 1 8-62 freescale semiconductor preliminary?subject to change without notice the reference clock will be always the fxosc. the frequency meter returns a precise value of ck_32k, ck_firc or ck_sirc according to the clksel1 bit va lue. the measure starts when the sfm (start frequency measure) bit in the cmu_csr is set to ?1?. the measurement duration is given by the cmu_mdr register in numbers of cloc k cycles of the selected clock s ource with a widt h of 20 bits. the sfm bit is reset to ?0? by the hardware once the fre quency measurement is done and the count is loaded in the cmu_fdr. the frequency frc can be derived from the value loaded in the cmu_fdr register as follows: frc = (fosc * md) / n, eqn. 8-3 where n is the value in the cmu_fdr regist er and md is the value in the cmu_mdr. frequency meter by default evaluate s ck_firc, but the software can swap to ck_sirc or ck_sxosc by programming the clksel bits in the cmu_csr register.the ckon bits indicate which is the actual clock at the output of the multiplexer mux1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-1 preliminary?subject to change without notice chapter 9 crossbar switch (xbar) 9.1 information specific to this device this section presents device-specifi c parameterization, customization, and feature availability information not specifically referenced in the remainder of this chapter. 9.1.1 device-specific block diagram figure 9-1 shows the simplified block diagram for the pxd20. figure 9-1. device-specific block diagram 9.1.2 xbar master id numbers the xbar module refers to indivi dual masters by their physical master port number. other modules such as mpu and swt use the master ids. this is differ ent from the physical master port numbers which are in figure 9-1 above. table 9-1. xbar master id numbers master master id number xbar port id cpu (instruction) 0 0 cpu (data) 0 1 edma 2 2 gfx2d 3 3 dculite 4 4 crossbar switch master modules slave modules z4d core (instruction) m0 z4d core (data) m1 edma m2 gfx2d m3 viu2 m4 dculite m5 dcu3 m6 flash memory (instruction) s0 flash memory s1 sram s2 graphics ram (gfx2d) s3 graphics ram s4 unused* s5 quadspi rle s6 pbridge s7 unused* s5 * dram accesses do not go through the xbar.
pxd20 microcontroller reference manual, rev. 1 9-2 freescale semiconductor preliminary?subject to change without notice 9.1.3 unsupported features ? the max_halt_request input ? the use of the alternate master priority registers ? the use of the alternate gene ral purpose control registers ? registers for slave 5 ? registers for master 7 9.2 introduction 9.2.1 overview this section provides an overview of the generic multi-layer ahb cr ossbar switch (xbar). the purpose of the xbar is to concurrently support up to ei ght simultaneous connections between master ports and slave ports. the xbar supports a 64 -bit address bus width and almost any data bus width at all master and slave ports. 9.2.2 features the xbar has the ability to gain control of all the slave ports a nd prevent any masters from making accesses to the slave ports. this featur e is useful when the user wishes to turn off the clocks to the system and needs to ensure that no bus activity will be interrupted. the xbar can put each slave port in to a low power park mode so that slave port will not dissipate any power transitioning address, control or data signal s when not being actively accessed by a master port. each slave port can also support multiple master prio rity schemes. each slave port has a hardware input which selects the master priority scheme so the user can dynamically change master priority levels on a slave port by slave port basis. the xbar will allow for concurrent transactions to occur from any mast er port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a result of independent master requests. if a slave port is simultan eously requested by more than one ma ster port, arbitration logic will select the higher priority master and grant it ownershi p of the slave port. all other masters requesting that slave port will stalled until the higher prio rity master completes its transactions. viu2 5 5 dcu3 6 6 nexus id 8 1 table 9-1. xbar master id numbers (continued) master master id number xbar port id
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-3 preliminary?subject to change without notice 9.2.3 limitations the xbar routes bus transactions initiated on the mast er ports to the appropriate slave ports. there is no provision included to route tr ansactions initiated on the slave ports to other slave ports or to master ports. simply put, the slave ports do not support the bus request/bus grant prot ocol, the xbar assumes it is the sole master of each slave port. since the xbar does not s upport the bus request/bus grant protocol , if multiple masters are to be connected to a single master port an external arbiter w ill need to be used. in th e case of a single master connecting to a master port the single master?s bus gr ant signal must be tied off in the asserted state. each master and slave port is full y ahb-lite + amba v6 extensions co mpliant. the ports are not fully ahb compliant because the xbar does not support splits or retrys. 9.2.4 general operation when a master makes an access to the xbar the ac cess will be immediately ta ken by the xbar. if the targeted slave port of the access is available then the access will be immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses thr ough the xbar. if the targeted slave port of the access is busy or parked on a different master port the reques ting master will simply see wait states inserted ( hready held negated) until the targeted slave port can service the ma ster?s request. the latency in servicing the request wi ll depend on each master?s priority level and th e responding peripheral?s access time. since the xbar appears to be just another slave to the master device, the master device will have no knowledge of whether or not it actual ly owns the slave port it is target ing. while the master does not have control of the slave port it is target ing it will simply be wait stated. a master will be given control of the targeted slav e port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has an out standing request to one slave port that has a long response time, has a pending access to a different slave port, and a lower prio rity master is also making a request to the same slave port as the pending access of the higher priority master. once the master has control of the slave port it is target ing the master will remain in control of that slave port until it gives up the slave port by running an idle cycle or by leaving that slave port for its next access. the master could also lose control of the slave port if another higher priority master makes a request to the slave port; however, if the master is ru nning a locked or fixed length burst transfer it will retain control of the slave port unt il that transfer is completed. ba sed on the aulb bit in the mgpcr (master general purpose control regi ster) the master will either reta in control of the slave port when doing undefined length incrementing burst transfers or will lose the bus to a higher priority master. the xbar will terminate al l master idle transfers (as opposed to al lowing the termination to come from one of the slave busses). additionally, when no master is requesting access to a slave port the xbar will drive idle transfers onto the slave bus, even though a default master ma y be granted access to the slave port. when the xbar is controlling the slave bus (that is, during low power park or halt mode) the hmaster field will indicate 4?b0000.
pxd20 microcontroller reference manual, rev. 1 9-4 freescale semiconductor preliminary?subject to change without notice when a slave bus is being idled by the xbar it can park the slave port on the master port indicated by the park bits in the sgpcr (slave general purpose control register). th is can be done in an attempt to save the initial clock of arbitration de lay that would otherwise be seen if the master had to arbitrate to gain control of the slave port. the slave por t can also be put into low power pa rk mode in attempt to save power. 9.3 xbar registers this section provides info rmation on xbar registers. 9.3.1 register summary there are four registers that reside in each slave port of the xbar and one regist er that resides in each master port of the xbar. these regi sters are ip bus compliant register s. read and write transfers both require two ip bus clock cycles. the registers can only be read from a nd written to in supervisor mode. additionally, these registers can only be r ead from or written to by 32-bit accesses. the registers are fully decoded and an error response is returned if an unimplemented location is accessed within the xbar. the slave registers also feature a bit, which when wr itten with a 1, will preven t the registers from being written to again. the registers will st ill be readable, but future write at tempts will have no effect on the registers and will be termin ated with an error response. the memory map for the xbar program -visible registers is shown in table 9-2 . table 9-3 shows the xbar register summary. table 9-2. xbar registers address offset use location 0x000 master priority register for slave port 0 (mpr0) on page 9-6 0x004 reserved ? 0x010 general purpose control register for slave port 0 (sgpcr0) on page 9-9 0x014 reserved ? 0x100 master priority register for slave port 1 (mpr1) on page 9-6 0x104 reserved ? 0x110 general purpose control register for slave port 1 (sgpcr1) on page 9-9 0x114 reserved ? 0x200 master priority register for slave port 2 (mpr2) on page 9-6 0x204 reserved ? 0x210 general purpose control register for slave port 2 (sgpcr2) on page 9-9 0x214 reserved ? 0x300 master priority register for slave port 3 (mpr3) on page 9-6 0x304 reserved ? 0x310 general purpose control register for slave port 3 (sgpcr3) on page 9-9 0x314 reserved ? 0x400 master priority register for slave port 4 (mpr4) on page 9-6 0x404 reserved ? 0x410 general purpose control register for slave port 4 (sgpcr4) on page 9-9
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-5 preliminary?subject to change without notice 0x414 reserved ? 0x500 master priority register for slave port 5 (mpr5) on page 9-6 0x504 reserved ? 0x510 general purpose control register for slave port 5 (sgpcr5) on page 9-9 0x514 reserved ? 0x600 master priority register for slave port 6 (mpr6) on page 9-6 0x604 reserved ? 0x610 general purpose control register for slave port 6 (sgpcr6) on page 9-9 0x614 reserved ? 0x700 master priority register for slave port 7 (mpr7) on page 9-6 0x704 reserved ? 0x710 general purpose control register for slave port 7 (sgpcr7) on page 9-9 0x714 reserved ? 0x800 general purpose control register for master port 0 (mgpcr0) on page 9-11 0x900 general purpose control register for master port 1 (mgpcr1) on page 9-11 0xa00 general purpose control register for master port 2 (mgpcr2) on page 9-11 0xb00 general purpose control register for master port 3 (mgpcr3) on page 9-11 0xc00 general purpose control register for master port 4 (mgpcr4) on page 9-11 0xd00 general purpose control register for master port 5 (mgpcr5) on page 9-11 0xe00 general purpose control register for master port 6 (mgpcr6) on page 9-11 0xf00 general purpose control register for master port 7 (mgpcr7) on page 9-11 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a ? bit w1c bit figure 9-2. key to register fields table 9-3. xbar register summary name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mprn ($base + 0x000 + n*0x100) r0mstr_70mstr_60mstr_50mstr_4 w r0mstr_30mstr_20mstr_10mstr_0 w sgpcrn ($base + 0x010 + n*0x100) r0000000000000000 wro hlp hpe7hpe6hpe5hpe4hpe3hpe2hpe1hpe0 r0000000000000000 w arb pctl pa r k mgpcrn ($base + 0x800 + n*0x100 r0000000000000000 w table 9-2. xbar registers (continued) address offset use location
pxd20 microcontroller reference manual, rev. 1 9-6 freescale semiconductor preliminary?subject to change without notice note: for n = 0 to 7 9.3.2 xbar register descriptions the following paragraphs provide detailed de scriptions of the various xbar registers. table 9-4 provides a key to the terms found in xbar registers. 9.3.2.1 master priority register the master priority register (mpr) sets the priori ty of each master port on a per slave port basis and resides in each slave port. r0000000000000000 w aulb table 9-4. register terms term description gray bit unimplemented bit; always reads as zero;writing has no effect access s supervisor mode only ? supervisor or user mode type r read only; writing to this bit has no effect w write only rw standard read/write bit. only software can change a bit?s value (other than a hardware reset). rwm a read/write bit that may be modified by hardware in some fashion other than reset. w1c a status bit that can be read and cleared by writing a logic 1 slfclr self-clearing bit. writing a 1 has some effect on module, but it always reads as a 0. reset 0 resets to a logic 0 1 resets to a logic 1 u unaffected by reset ? reset state is unknown. table 9-3. xbar register summary (continued) name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-7 preliminary?subject to change without notice note: for n = 0 to 7 figure 9-3. master priority register n mprn master priority register n addr $base + 0x000 + n*100 wait state: 0 access: s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mstr_7 mstr_6 mstr_5 mstr_4 type: r rw rw rw r rw rw rw r rw rw rw r rw rw rw reset: 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mstr_3 mstr_2 mstr_1 mstr_0 type: r rw rw rw r rw rw rw r rw rw rw r rw rw rw reset: 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 table 9-5. master priority register descriptions name description settings bit 0 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_7 master 7 priority - these bits set the arbitration priority for master port 7 on the associated slave port. these bits are initialized by hardware reset. the reset value is 111 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 4 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_6 master 6 priority - these bits set the arbitration priority for master port 6 on the associated slave port. these bits are initialized by hardware reset. the reset value is 110 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 8 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_5 master 5 priority - these bits set the arbitration priority for master port 5 on the associated slave port. these bits are initialized by hardware reset. the reset value is 101 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 12 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na
pxd20 microcontroller reference manual, rev. 1 9-8 freescale semiconductor preliminary?subject to change without notice the master priority register can onl y be accessed in supervisor mode with 32-bit accesses. once the ro (read only) bit has been set in the slave general pur pose control register the ma ster priority register can only be read from, attempts to write to it will have no effect on the mpr and resu lt in an error response. note no two available master ports may be programmed with the same priority level. attempts to program two or mo re available masters with the same priority level will result in an er ror response and the mpr will not be updated. mstr_4 master 4 priority - these bits set the arbitration priority for master port 4 on the associated slave port. these bits are initialized by hardware reset. the reset value is 100 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 16 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_3 master 3 priority - these bits set the arbitration priority for master port 3 on the associated slave port. these bits are initialized by hardware reset. the reset value is 011 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 20 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_2 master 2 priority - these bits set the arbitration priority for master port 2 on the associated slave port. these bits are initialized by hardware reset. the reset value is 010 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 24 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_1 master 1 priority - these bits set the arbitration priority for master port 1 on the associated slave port. these bits are initialized by hardware reset. the reset value is 001 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. bit 28 master priority register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na mstr_0 master 0 priority - these bits set the arbitration priority for master port 0 on the associated slave port. these bits are initialized by hardware reset. the reset value is 000 000this master has the highest priority when accessing the slave port. 111this master has the lowest priority when accessing the slave port. table 9-5. master priority register descriptions (continued) name description settings
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-9 preliminary?subject to change without notice 9.3.2.2 slave general purpose control register the slave general purpose control register (sgpcr) controls several features of each slave port. the read only (ro) bit will prevent any registers a ssociated with this slave port from being written to once set. this bit may be written with 0 as many times as the user desire s, but once it is wr itten to a 1 only a reset condition will allow it to be written again. the halt low priority (hlp) bit will set the priority of the max_halt_request input to the lowest possible priority for initial arbitration of the slave ports. by default it is the highest priority. se tting this bit will not effect the max_halt_request from attaining highest priority on ce it has control of the slave ports. the pctl bits determine how the slave port will park when no master is actively making a request. the available options are to park on the master defined by the park bits, park on the last master to use the slave port, or go into a low power pa rk mode which will force all the ou tputs of the slave port to inactive states when no master is requesting an access. the lo w power park feature can re sult in an overall power savings if a the slave port is not saturated; however, it will force an extra clock of latency whenever any master tries to access it when it is not in us e because it will not be parked on any master. the park bits determine which master the slave will park on when no master is making an active request and the max_halt_request input is negated. please use caution to onl y select master ports that are actually present in the design. if the user programs the park bits to a master not present in the current design implementation undefined behavior will result. note: for n = 0 to 7 figure 9-4. slave general purpose control register n sgpcrn slave general purpose control register n addr $base + 0x010 + n*100 wait state: 0 access: s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ro hlp hpe 7 hpe 6 hpe 5 hpe 4 hpe 3 hpe 2 hpe 1 hpe 0 type: rw rw r r r r r r rw rw rw rw rw rw rw rw reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: once the ro bit is written to a 1, only hardware reset will return it to a 0. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 arb pctl pa r k type: r r r r r r rw rw r r rw rw r rw rw rw reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: - - - - - - - - - - - - - - - -
pxd20 microcontroller reference manual, rev. 1 9-10 freescale semiconductor preliminary?subject to change without notice table 9-6. slave general purpose control register descriptions name description setting ro read only - this bit is used to force all of a slave port?s registers to be read only. once written to 1 it can only be cleared by hardware reset. this bit is initialized by hardware reset. the reset value is 0 0 all this slave port?s registers can be written. 1 all this slave port?s registers are read only and cannot be written (attempted writes have no effect and result in an error response). hlp halt low priority - this bit is used to set the initial arbitration priority of the max_halt_request input. this bit is initialized by hardware reset. the reset value is 0 0 the max_halt_request input has the highest priority for arbitration on this slave port 1 the max_halt_request input has the lowest initial priority for arbitration on this slave port. bits 2?7 slave general purpose control register reserved - these bits are reserved for future expansion. they read as zero and should be written with zero for upward compatibility. na hpex high priority enable - these bits are used to enable the mx_high_priority inputs for the respective master. these bits are initialized by hardware reset. the reset value is 0 0 the mx_high_priority input is disabled on this slave port 1 the mx_high_priority input is enabled on this slave port. bits 16?21 slave general purpose control register reserved - these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. na arb arbitration mode - these bits are used to select the arbitration policy for the slave port. these bits are initialized by hardware reset. the reset value is 00 00 fixed priority. 01 round robin (rotating) priority. 10 reserved 11 reserved bits 24?25 slave general purpose control register reserved - these bits are reserved for future expansion. they are read as zero and should be written with zero for upward compatibility. na pctl parking control - these bits determine the parking control used by this slave port. these bits are initialized by hardware reset. the reset value is 00. 00 when no master is making a request the arbiter will park the slave port on the master port defined by the park bit field. 01 when no master is making a request the arbiter will park the slave port on the last master to be in control of the slave port. 10 when no master is making a request the arbiter will park the slave port on no master and will drive all outputs to a constant safe state. 11 reserved bit 28 slave general purpose control register reserved - this bit is reserved for future expansion. it is read as zero and should be written with zero for upward compatibility. na
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-11 preliminary?subject to change without notice the sgpcr can only be accessed in supervisor mode with 32-bit acce sses. once the ro (read only) bit has been set in the sgpcr the sgpcr can only be read, attempts to write to it will have no effect on the sgpcr and result in an error response. 9.3.2.3 master general purpose control register the master general purpose contro l register (mgpcr) presently c ontrols only whether or not the master?s undefined length burst accesses will be allowed to complete uninterrupted or whether they can be broken by requests from hi gher priority masters. the aulb (arbitrate on undefined le ngth bursts) bit field determines whether (and when) or not the xbar will arbitrate away the slav e port the master owns when the ma ster is performing undefined length burst accesses. if the user has configured the xbar to have less than eight master port s only the registers associated with the remaining master ports will be present, all other registers will become reserved locations in memory. note: for n = 0 to 7 figure 9-5. master general purpose control register n pa r k park - these bits are used to determine which master port this slave port parks on when no masters are actively making requests and the pctl bits are set to 00. these bits are initialized by hardware reset. the reset value is 000 000park on master port 0 001park on master port 1 010park on master port 2 011park on master port 3 100park on master port 4 101park on master port 5 110park on master port 6 111park on master port 7 mgpcrn master general purpose control register n addr $base + 0x800 + n*100 wait state: 0 access: s 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 type: r r r r r r r r r r r r r r r r reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 aulb type: r r r r r r r r r r r r r rw rw rw reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: - - - - - - - - - - - - - - - - table 9-6. slave general purpose control register descriptions (continued) name description setting
pxd20 microcontroller reference manual, rev. 1 9-12 freescale semiconductor preliminary?subject to change without notice the mgpcr can only be accessed in supervisor mode with 32-bit accesses. 9.3.3 coherency since the content of the regi sters has a real time effect on the operation of the xbar it is important for the user to understand that any register m odifications take effect as soon as the register is wr itten. the values of the registers do not track with slave port related ahb accesses but instead track only with ip bus accesses. the exception to this rule are the aulb bits in the mgpcr. these update of these bits is only recognized when the master on that master port runs an idle cycle, even though the ip bus cycle to write them will have long since terminated successful ly. if the aulb bits in the mgp cr are written in between two burst accesses the new aulb encodings will not take effect until an idle cycle has been initiated by the master on that master port. 9.4 function this section describes in more deta il the functionality of the xbar. 9.4.1 arbitration the xbar supports two arbi tration schemes; a simple fixed-priori ty comparison algorithm, and a simple round-robin fairness algorithm. the arbitration scheme is independe ntly programmable for each slave port. table 9-7. master general purpose control register descriptions name description setting bits 0?28 master general purpose control register reserved - these bits are reserved for future expansion. they read as zero and should be written with zero for upwa rd compatibility. na aulb arbitrate on undefined length bursts - these bits are used to select the arbitration policy during undefined length bursts by this master. these bits are initialized by hardware reset. the reset value is 000 000no arbitration will be allowed during an undefined length burst. 001arbitration will be allowed at any time during an undefined length burst. 010arbitration will be allowed after four beats of an undefined length burst. 011arbitration will be allowed after eight beats of an undefined length burst. 100arbitration will be allowed after 16 beats of an undefined length burst. 101reserved 110reserved 111reserved
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-13 preliminary?subject to change without notice 9.4.1.1 arbitration during undefined length bursts arbitration points during an undefined length burst are defined by the current master?s mgpcr aulb field setting. when a defi ned length is imposed on th e burst via the aulb bits the undefined length burst will be treated as a single or series of si ngle back to back fixed length burst accesses. example: a master runs an undefine d length burst and the aulb bits in the mgpcr indicate arbitration will occur after the fourth beat of the burst. the master runs two sequential beats and then starts what will be an 12 beat undefined length burst access to a new address within the same slave port region as the previous access. the xbar will not allow an arbitration point until the fourth ove rall access (second beat of the second burst). at that point all remaining accesse s will be open for arbitration until the master loses control of the slave port. assume the master loses control of the slave port after the fifth beat of the second burst. once the master regains control of the slave port no ar bitration point will be available unt il after the master has run four more beats of its burst. after the fourth beat of the (now continued) burst (ninth beat of the second burst from the master?s perspective) is taken all beats of the burst will once again be open for arbitration until the master loses control of the slave port. assume the master again loses control of the slave port on the fifth beat of the th ird (now continued) burst (10th beat of the second bur st from the master?s perspective). once the master regains control of the slave port it will be allowed to complete its final two beats of its burst wi thout facing arbitration. note that fixed length bur st accesses are not affected by the aulb bits. all fixed length burst accesses lock out arbitration until the last beat of the fixed length burst. 9.4.1.2 fixed priority operation when operating in fixed-priority mode , each master is assi gned a unique priority le vel in the mpr (master priority register). if two masters both request access to a slave port th e master with the highest priority in the selected priority register will gain control over the slave port. any time a master makes a re quest to a slave port the sl ave port checks to see if the new requesting master?s priority level is higher than that of the master that currently has contro l over the slave port (unless the slave port is in a parked state). the slave port does an arbitr ation check at every clock edge to ensure that the proper master (if any) has control of the slave port. if the new requesting master?s priority level is higher than th at of the master that currently has control of the slave port the new requesting master will be granted cont rol over the slave port at the next clock edge. the exception to this rule is if the master that cu rrently has control over the slave port is running a fixed length burst transfer or a locked transfer. in this case the new re questing master will ha ve to wait until the end of the burst transfer or locked transfer before it will be gr anted control of the slave port. if the master is running an undefined length burst tr ansfer the new requesti ng master must wait unt il an arbitration point for the undefined length burst transfer before it will be granted control of the sl ave port. arbitration points for an undefined length burst are defi ned in the mgpcr for each master. if the new requesting master?s priority level is lower than that of the ma ster that currently has control of the slave port the new requesting master will be forced to wait until th e master that currently has control
pxd20 microcontroller reference manual, rev. 1 9-14 freescale semiconductor preliminary?subject to change without notice of the slave port either runs an idle cycle or runs a non idle cycle to a location other than the current slave port. 9.4.1.3 round-robin priority operation when operating in round-robin mode, each master is assigned a relative priority based on the master number.this relative priority is compared to the id of the last master to perform a transfer on the slave bus. the highest priority requesting mast er will become owner of the slav e bus as the next transfer boundary (accounting for locked and fi xed-length burst transfers). priority is based on how far ahead the id of the requesting master is to the id of the last mast er (id is defined by master port number, not the hmaster field). once granted access to a slave port, a master may perf orm as many transfers as de sired to that port until another master makes a request to the same slave port. the next master in line wi ll be granted access to the slave port at the next assertion of sx_hready , or possibly on the next clock cycle if the current master has no pending access request. as an example of arbitration in round-robin mode, assume the xbar is implemented with master ports 0, 1, 4 and 5. if the last master of the slave port was master 1, and ma ster 0, 4 and 5 make simultaneous requests, they will be serviced in the order 4, 5 and then 0. parking may still be used in a round-robin mode, but will not affect the r ound-robin pointer unless the parked master actually perf orms a transfer. handoff will occur to the ne xt master in line after one cycle of arbitration. if the slave port is put into low power park mode the round-r obin pointer will be reset to point at master port 0, giving it the highest priority. each master port has an mx_high_priority input which can be enabled by wr iting the correct data to the sgpcr or asgpcr. if a master?s mx_high_priority input is enabled for a slave port programmed for round-robin mode, that master can force the slave port into fixed priority mode by asserting its mx_high_priority input while making a request to that particul ar slave port. while that (or any enabled) master?s mx_high_priority input is asserted while ma king an access attempt to th at particular slave port, the slave port will remain in fixed priority mode. once that (or a ny enabled) master?s mx_high_priority input is negated, or the ma ster no longer attempts to ma ke accesses to that partic ular slave port, the slave port will revert back to round-robin pr iority mode and the pointer will be set on the last master to access the slave port. 9.4.2 priority assignment each master port needs to be assigned a unique 3-bit pr iority level. if an atte mpt is made to program multiple master ports with the same priority leve l within a register (mpr or ampr) the xbar will respond with an error and the registers will not be updated. 9.4.2.1 context switching the xbar has a hardware input per slave port ( sx_ampr_sel ) which is used to sele ct which registers the master priority levels and general purpos e control bits will be taken from. when sx_ampr_sel is 0 the mpr and sgpcr will be selected, when sx_ampr_sel is 1 the ampr and the asgpcr will be selected. this hardware input is useful for context switching so the user does not have to rewrite the mpr or sgpcr
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-15 preliminary?subject to change without notice if a particular slave port w ould temporarily benefit from modifying the master prio rity levels or functions affected by the bits in the sgpcr. 9.4.2.2 priority elevation the xbar has a hardware input per master port ( mx_high_priority ) which is used to temporarily elevate the master?s priority level on all slave ports. when the master?s mx_high_priority input is asserted the master port will automatically have higher priority than all other ma ster ports that do not have their mx_high_priority input asserted regardless of the priority levels program med in the mpr and ampr. if multiple master ports have their mx_high_priority input asserted they will ha ve higher priority than all master ports which do not have their mx_high_priority inputs asserted. the mpr or ampr priority level (dependent on the state of sx_ampr_sel ) will determine which ma ster port that has its mx_high_priority input asserted has the highest prior ity on a slave port by slave port basis. this functionality is useful because it allows the user to automatically el evate a master port?s priority level throughout the xbar in order to quickly perform temporary tasks such as servicing interrupts. please note that the hpex bits must be set in th e sgpcr or asgpcr in the slave port in order for the mx_high_priority inputs to be received by the slave port. 9.4.3 master port functionality 9.4.3.1 general each master port consists of two de coders, a capture unit, a register sl ice, a mux and a small state machine. the first decoder is used to decode the mx_hsel_slv and control signals coming directly from the master, telling the state machine where the mast er?s next access will be and if it is in fact a legal access. the second decoder receives its input from the capture unit, so it may be looking di rectly at the signals coming from the master or it may be looking at captured signals coming from the master, depe nding entirely on the state of the targeted slave port. the second decoder is then used to generate the acces s requests that go to the slave ports. the capture unit is used to capture the address and control information co ming from the master in the event that the targeted slave port cannot immediately service the master. the capture unit is controlled by outputs from the state machine which tell it to either pass through the original master signals or the captured signals. the register slice contains the registers associated with the specific master port. the registers have a quasi-ip bus interface at this level for reads and writes and the outputs fe ed directly into the state machine. the mux is used simply to select which slave?s read da ta is sent back to the ma ster. the mux is controlled by the state machine. the state machine controls all aspe cts of the master port. it knows wh ich slave port the master wants to make a request to and controls when that request is made. it also has knowledge of each slave port, knowing whether or not the slave port is ready to ac cept an access from the ma ster port. this will determine whether or not the master may immediately have its request taken by the slave port or whether the master port will have to capture the master?s request and queue it at the slave port boundary.
pxd20 microcontroller reference manual, rev. 1 9-16 freescale semiconductor preliminary?subject to change without notice a block diagram of a mast er port can be seen in figure 9-6 . figure 9-6. xbar master port block diagram decoder addr/cntrl next_slave_port[7:0] illegal_access capture unit addr/cntrl async/flopped_sel addr/cntrl decoder addr/cntrl slave_port_rqst[7:0] request_enable state machine next_slave_port[7:0] illegal_access request_enable async/flopped_sel rdata_sel slv_hready[7:0] slv_hresp[7:0] hready_in hready_out slv_is_mine[7:0] hresp mux hrdata slv_hrdata[7:0] sel registers read_sel write_sel xfr_wait xfr_error wdata rdata control_bits control_bits
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-17 preliminary?subject to change without notice 9.4.3.2 master port decoders the decoders are very simple as they ensure an access request is allowed to be made and that the slave port targeted is actually present in th e design. the decoders feeding the st ate machine are always enabled. the decoders that select the slave are enabled only when the master port controlli ng state machine wants to make a request to a slave port. this is necessary so th at if a master port is making an access to a slave port and is being wait stated, and its next access is to a different slave port, the request to the second slave port can be held off until the access to the first slave port is terminated. the decoders also output a ?hole de code? or illegal access signal whic h tells the state machine that the master is trying to access a slave port that does not exist. 9.4.3.3 master port capture unit the capture unit simply capt ures the state of the mast er?s address and control si gnals if the xbar cannot immediately pass the master?s request through to the proper slave port. the capture unit consists of a set of flops and a mux which selects either the asynchr onous path from address a nd control or the flopped (captured) address a nd control information. 9.4.3.4 master port registers the registers in the master port are only those registers as sociated with this particul ar master port. the read and write interface for the registers is a quasi-ip bus interface. it is not a full ip bus interface at this level because not all the ip bus signals ar e routed this deep in the design. there is a register control block at the same level of the master port and slav e port instantiations in the xbar. this control block ensures th at all accesses are 64-bit supervis or accesses before passing them on to the master ports. the register outputs are connected directly to the state machine. 9.4.3.5 master port state machine 9.4.3.5.1 master port state machine states the master side state machine?s main function is to monitor the activities of the master port. the state machine has six states: busy , idle , waiting , stalled , steady state , first cycle error response and second cycle error response . the busy state is used when the master runs a busy cy cle to the master port. the master port maintains its request to the slave port if it cu rrently owns the slave port; however, if it loses control of the slave port it will no longer maintain its request. if the master port loses control of the slave port it will not be allowed to make another request to the slave por t until it runs a nseq or seq cycle. the idle state is used when the master runs a valid idle cycle to the ma ster port. the master port makes no requests to the slave ports (disables the slav e port decoder) and terminates the idle cycle.
pxd20 microcontroller reference manual, rev. 1 9-18 freescale semiconductor preliminary?subject to change without notice the waiting state is used when the hsel signal is negated to the master port, indicating the master is running valid cycles to a local slav e other than the xbar. in this cas e the max disables the slave port decoder and holds hresp and hready negated. the stalled state is used when the master makes a request to a slave port th at is not immediately ready to receive the request. in this case the state machine will direct the capture unit to send out the captured address and control signals and will enable the sl ave port decoder to indicate a pending request to the appropriate slave port. the steady state state is used when the master port and sl ave port are in fully asynchronous mode, making the xbar completely transparent in the access. the state machine selects the appropriate slave?s hresp, hready and hrdata to pass back to the master. the first cycle error response and second cycle error response states are self explanatory. the xbar will respond with an error response to the master if the master tries to access an unimplemented memory location through the xbar (that is, a slave port that does not exist). 9.4.3.5.2 master port stat e machine slave swapping the design of the master side state machine is fairly strai ghtforward. the one real de cision to be made is how to handle the master moving from one slave por t access to another slave port access. the approach that was taken is to minimize or eliminate when pos sible any ?bubbles? that woul d be inserted into the access due to switching slave ports. the state machine will not allow th e master to request access to anot her slave port until the current access being made is terminated. this prevents a single master from owning two slave ports at the same time (the slave port it is currently accessing and the slave port it wishes to access next). the state machine also maintains watch on the slave po rt the master is accessing as well as the slave port the master wishes to switch to. if the new slave port is parked on the mast er then the master will be able to make the switch without incurri ng any delays. the termination of the current access will also act as the launch of the new access on the new sl ave port. if the new slave port is not parked on the master then the master will incur a minimum one clock delay befo re it can launch its acce ss on the new slave port. this is the same for switching from the busy, idle or waiting state to actively acces sing a slave port. if the slave port is parked on the master the state machine will go to the steady state state and the access will begin immediately. if the slave port is not parked on the ma ster (serving a nother master, parked on another master or in low power park mode) then the state machine will transition to the stalled state and at least a one clock penalty will be paid. 9.4.4 slave port functionality 9.4.4.1 general each slave port consists of a register sl ice, a bank of muxes and a state machine. the register slice contains the registers associated with the specific slave port. the registers have a quasi-ip bus interface at this level for reads and writes and the outputs fe ed directly into the state machine.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-19 preliminary?subject to change without notice the muxes are a series of 8 to 1 muxe s that take in all the address, cont rol and write data information from each of the master ports and then pass the correct master?s signals to the slave port. the state machine controls all the muxes. the state machine is where the main slave port arbitrati on occurs, it decides which master is in control of the slave port and which master will be in c ontrol of the slave port in the next bus cycle. a block diagram of a slav e port can be seen in figure 9-7 . figure 9-7. xbar slave port block diagram 9.4.4.2 slave port muxes the block diagram ( figure 9-7 ) shows only one block for all the muxes. in reality that block instantiates many 8 to 1 muxes, one for each master-to-slave signa l in fact. all the muxes are designed in an and - or fashion, so that if no master is selected the output of the muxes wi ll be zero. (this is an important feature for low power park mode.) registers read_sel write_sel xfr_wait xfr_error wdata rdata control_bits state machine master_requests[7:0] m[7:0]_high_priority slv_hresp master_sel[7:0] force_idle control_bits slv_hready slave_halted current_master[7:0] master_hready[7:0] force_nseq halt_request ampr_sel master_hresp[7:0] muxes master_addr[7:0] master_cntrl[7:0] master_wdata[7:0] slv_addr_signals slv_cntrl_signals slv_wdata master_sel[7:0] force_idle force_nseq
pxd20 microcontroller reference manual, rev. 1 9-20 freescale semiconductor preliminary?subject to change without notice the muxes also have an override signal which is used by the slave port to asynchronously force idle cycles onto the slave bus. when the state machine forces an idle cycle it zeros out htrans and hmastlock , making sure the slave bus sees a va lid idle cycle being run by the xbar. the enable to the mux controlling htrans also contains an a dditional control signal from the state machine so that a nseq transaction can be forced. this is done any time the slave por t switches masters to ensure that no idle-seq, busy-seq or ns eq-seq transactions are seen on the slave port when they shouldn?t be. if the state machine indicates to run both an idle and an nseq cycl e, the idle directive will have priority. note idle-seq is in fact an illegal acce ss, but a possible sc enario given the multi-master environment in the xbar unless corrected by the xbar. 9.4.4.3 slave port registers there is a register control block at the same level of the master port and slav e port instantiations in the xbar. this control block ensures th at all accesses are 64-bit supervis or accesses before passing them on to the master and slave ports. the registers in the slave port are onl y those registers associated with th is particular slave port. the read and write interface for the registers is a quasi-ip bus interface. it is not a full ip bus interface at this level because not all the ip bus signals ar e routed this deep in the design. the register outputs are connected direct ly to the slave state machine with the sx_ampr_sel input determining which priority register values, halt priority value, arbitr ation algorithm an d parking control bits are passed to the state machine. the registers ca n be read from an unlimited number of times. the registers can only be written to as l ong as the ro bit is writte n to 0 in the sgpcr, onc e it is written to a 1 only a hardware reset will allow th e registers to be written again. 9.4.4.4 slave port state machine 9.4.4.4.1 slave port state machine states at the heart of the slave port is the state machine. th e state machine is simplicity itself, requiring only four states - steady state , transition state, tr ansition hold state and hold state . either the slave port is owned by the same master it was in the last clock cycle (eith er by active use or by parki ng), it is transitioning to a new master (either for active use or parking), it is transitioning to a new master during wait states or it is being held on the same master pe nding a transition to a new master. 9.4.4.4.2 slave port stat e machine arbitration the real work in the state machine is determining which master port will be in cont rol of the slave port in the next clock cycle, the arbitration. each master is programmed with a fixed 3 bit priority level. a fourth priority bit is derived from the mx_high_priority inputs on the master ports , effectively making each master?s priority level a 4 bit field with mx_high_priority being the msb. the xbar uses these bits in determining priority levels when programmed for fixed priority mode of operation or wh en one of the enabled mx_high_priority inputs is asserted.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-21 preliminary?subject to change without notice arbitration always occurs on a clock edge, but only occurs on edges when a change in mastership will not violate ahb-lite protocols. valid arbitrations points incl ude any clock cycle in which sx_hready is asserted (provide the master is not performing a burst or locked cycle) and any wait state in which the master owning the bus indicates a tr ansfer type of idle (provided the master is not performing a locked cycle). since arbitration can occur on every clock cycle the slave port masks off all master requests if the current master is performing a locked transfer or a protec ted burst transfer, guaranteei ng that no matter how low its priority level it will be allowed to finish its locked or protected portion of a burst sequence. 9.4.4.4.3 slave port stat e machine master handoff the only times the slave port will switch masters when programmed for fixed priority mode of operation is when a higher priority master make s a request or when the current mast er is the highest priority and it gives up the slave port by either running and idle cycle to the slave port or r unning a valid access to a location other than the slave port. if the current master loses control of the slave port because a higher prio rity master takes it away, the slave port will not incur any wasted cycles. the current mast er has its current cycle terminated by the slave port at the same time the new master?s address and control information ar e recognized by the slave port. this appears as a seamless transition on the slave port. if the current master is being wait-stated when the hi gher priority master makes it s request, then the current master will be allowed to make one more transaction on the slave bus before givi ng it up to the new master. figure 9-8 illustrates the effect of a highe r priority master taking control of the bus when the slave port is programmed for a fixed prio rity mode of operation. figure 9-8. low to high priority mastership change 123456789 master 5 master 5 master 4 master 3 master 2 master 3 master 4 none xbar master 5 master 5 master 2 master 3 master 4 xbar idle nseq nseq nseq nseq nseq idle hclk m2 request m3 request m4 request m5 request htrans hready requester priority highest address/cntrl owner 10
pxd20 microcontroller reference manual, rev. 1 9-22 freescale semiconductor preliminary?subject to change without notice if the current master is the highest priority master and it gives up the slave port by running an idle cycle or by running a valid cycle to another location other th an the slave port the next highest priority master will gain control of the slave port. if the current acce ss incurs any wait states then the transition will be seamless and no bandwidth will be lost; however, if the current transaction is terminated without wait states then one idle cycle will be forced onto the sl ave bus by the xbar before the new master will be able to take control of th e slave port. if no other master is requestin g the bus then idle cycles will be run by the xbar but no bandwidth will truly be lost since no master is making a request. figure 9-9 illustrates the effect of a higher priority ma ster giving up control of the bus. figure 9-9. high to low priority mastership change when the slave port is programmed for round-robin mode of arbitration then th e slave port will switch masters any time there is more than one master acti vely making a request to th e slave port. this will happen because any master other than the one which pr esently owns the bus will be considered to have higher priority. figure 9-10 shows an example of round-robin mode of operation. 123456789 master 0 master 2 none master 4 none xbar master 0 xbar master 2 xbar master 4 xbar idle nseq idle nseq idle nseq idle hclk m0 request m2 request m4 request highest address/cntrl htrans hready priority requester owner
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-23 preliminary?subject to change without notice figure 9-10. round-robin mastership change 9.4.4.4.4 slave port state machine parking if no master is currently making a request to the slave port then the slave port will be parked. it will park in one of four places, dictated by the pctl and park bits in the gpcr or agpcr (depending on the state of the sx_ampr_sel ) and the locked state of the last master to access it. if the last master to access the slave port ran a lo cked cycle and continues to r un locked cycles even after leaving the slave port the slav e port will park on that mast er without regard to the bit settings in the gpcr and without regard to pending request s from other masters. this is done so a master can run a locked transfer to the slave port, leave it, and return to it and be guaranteed th at no other master has had access to it (provided the master maintains all transfers are lock ed transfers). if locking is not an issue for parking the gpcr bits will dict ate the parking method. if the pctl bits are set for ?low power park? mode th en the slave port will ente r low power park mode. it will not recognize any master as bein g in control of it and it will not se lect any master?s signals to pass through to the slave bus. in this case al l slave bus activity will effectivel y halt because all slave bus signals being driven from the xbar will be 0. this of course can save quite a bit of power if the slave port will not be in use for some time. the down side is that wh en a master does make a request to the slave port it will be delayed by one cl ock since it will have to arbitrate to acquire ownership of the slave port. if the pctl bits are set to ?park on last? mode then the slave port will park on the last master to access it, passing all that masters signals through to the slave bus. the xbar will asynchronously force htrans[1:0] , hmaster[3:0] , hburst[2:0] and hmastlock to 0 for all access that the master does not run to the slave port. when that master access the slave port again it will not pay any ar bitration penalty; however, if any other master wishes to access the slave por t a one clock arbitration penalty will be imposed. 12345678910 master 1 master 4 master 0 master 4 master 5 none xbar master 1 master 4 master 5 master 0 master 4 master 5 xbar idle nseq nseq nseq nseq nseq nseq idle hclk m0 request m1 request m4 request m5 request highest address/cntrl htrans hready priority requester owner master 5
pxd20 microcontroller reference manual, rev. 1 9-24 freescale semiconductor preliminary?subject to change without notice if the pctl bits are set to ?use park/apark? m ode then the slave port will park on the master designated by the park bits. the beha vior here is the same as for the ?park on last? mode with the exception that a specific master will be parked on instead of the last master to a ccess the slave port. if the master designated by the park bits tries to access the slave port it wi ll not pay an arbitration penalty while any other master will pay a one clock penalty. figure 9-11 illustrates parking on a specific master. figure 9-11. parking on a specific master figure 9-12 illustrates parking on the last master. note that in cycle 6 s imultaneous requests are made by master 2 and master 4. although master 2 has higher priority, the slave bus is parked on mast er 4 so master 4?s access will be taken first. the slave port parks on master 2 once it ha s given control to master 2. this same situation can occur when parking on a specific master as well. 123456789 master 2 master 0 none master 2 none master 4 none master 2 none xbar master 0 master 2 xbar xbar master 4 master 2 xbar idle nseq nseq idle idle nseq nseq idle hclk m0 request m2 request m4 request park highest address/cntrl htrans hready priority requester owner
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-25 preliminary?subject to change without notice figure 9-12. parking on last master 9.4.4.4.5 slave port st ate machine halt mode if the max_halt_request input is asserted the slave port will ev entually halt all slave bus activity and go into halt mode, which is almost iden tical to low power park mode. the hlp bit in the gpcr controls the priority level of the max_halt_request in the arbitration algorithm. if the hlp bit is cleared then the max_halt_request will have the highest priority of any master and will gain control of the slave port at the next arbitration point (most likely the next bus cy cle, unless the current mast er is running a locked or fixed length burst transf er). if the hlp bit is set then the slave port will wait until no masters are actively making requests before moving to halt mode. regardless of the state of the hlp bit, once the sl ave port has gone into halt mode as a result of max_halt_request being asserted, it will re main in halt mode until max_halt_request is negated, regardless of the priority level of any masters that may make requests. in halt mode no master is selected to own the slave port so all the out puts of the slave port are set to 0. 9.5 initialization/application information no initialization is required by or for the xbar. hardwa re reset ensures all the register bits used by the xbar are properl y initialized. 9.6 interface this section provides information on the xbar interface. 123456789 last master master 0 master 4 master 2 master 0 none master 4 none master 2 none xbar master 0 xbar master 4 xbar master 4 master 2 xbar idle nseq idle nseq idle nseq nseq idle hclk m0 request m2 request m4 request park highest address/cntrl htrans hready priority requester owner
pxd20 microcontroller reference manual, rev. 1 9-26 freescale semiconductor preliminary?subject to change without notice 9.6.1 overview the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate in parallel with multiple slaves. in order to maximize da ta throughput it is essential to keep arbitration delays to a minimum. this section examines data throughput from the point of view of mast ers and slaves, detailing when the xbar will stall the masters or insert bubbles on the slave side. 9.6.2 master ports master accesses will receive one of four responses from the xbar. they will either be ignored, terminated, taken, stalled or responded to with an error. 9.6.2.1 ignored accesses a master access will be ignored if the hsel input of the xbar is not asse rted. the xbar will respond to idle transfers when the hsel input is asserted but will not allo w the access to pass through the xbar. 9.6.2.2 terminated accesses a master access will be terminated if the hsel input of the xbar is asserted and the transfer type is idle. the xbar will terminated the access and it wi ll not be allowed to pass through the xbar. 9.6.2.3 taken accesses a master access will be taken if the hsel input of the xbar is asserted and the transfer type is non idle and the slave port to which the access decodes is either currently servicing the master or is parked on the master. in this case the xbar will be completely tr ansparent and the master?s access will be immediately seen on the slave bus and no arbi tration delays will be incurred. 9.6.2.4 stalled accesses a master access will be stalled if the hsel input of the xbar is asserted and the transfer type is non idle and the access decodes to a slave port that is busy serv ing another master, parked on another master or is in low power park mode. the xbar will indicate to the master that the address phase of the access has been taken but will then queue the access to the appropriate slave port to enter into arbitration for access to that slave port. if the slave port is currently parked on another master or is in low power park mode and no other master is requesting access to the slave port then only one clock of ar bitration will be incurre d. if the slave port is currently serving another master of a lower priority and the master ha s a higher priority than all other requesting masters then the master will gain control over the slave port as soon as the data phase of the current access is completed (burst and locked transfer s excluded). if the slave port is currently servicing another master of a hi gher priority then the master will gain c ontrol of the slave port once the other master releases control of the slave port if no other higher priority master is also waiting for the slave port.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 9-27 preliminary?subject to change without notice 9.6.2.5 error respons e terminated accesses a master access will be responded to with an error if the hsel input of the xbar is a sserted and the transfer type is non idle and the access decode s to a location not occupied by a sl ave port. this is the only time the xbar will respond with an erro r response. all other error respons es received by the master are the result of error responses on the slav e ports being passed through the xbar. 9.6.3 slave ports the goal of the xbar with respect to the slave ports is to keep them 100% sa turated when masters are actively making requests. in order to do this the xbar must not in sert any bubbles onto the slave bus unless absolutely necessary. there is only one instance when the xbar will force a bubble onto the slave bus when a master is actively making a request. this occurs when a higher priority master has control of the slave port and is running single clock (zero wait state) accesses while a lower pr iority master is stalled waiting for control of the slave port. when the higher priority master either leaves the slave port or runs an idle cycle to the slave port the xbar will take control of the slave bus and run a single idle cycle before giving the slave port to the lower priority master that was waiting for control of the slave port. the only other times the xbar will ha ve control of the slave port is wh en the xbar is halting or when no masters are making access requests to the slave port and the xbar is fo rced to either park the slave port on a specific master or put the sl ave port into low power park mode. in most instances when the xbar has control of the slave port it will indicate idle for the transfer type, negate all control signals and indicate ownership of the slave bus via the hmaster encoding of 4?b0000. one exception to this rule is when a master running lo cked cycles has left the slave port but continues to run locked cycles. in this case the xbar will contro l the slave port and will indicate idle for the transfer type but it will not aff ect any other signals. note when a master runs a locked cycle through the xbar, the master will be guaranteed ownership of all slave por ts it accesses while running locked cycles for one cycle beyond when the ma ster finishes running locked cycles.
pxd20 microcontroller reference manual, rev. 1 9-28 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-1 preliminary?subject to change without notice chapter 10 deserial serial peripheral interface (dspi) 10.1 introduction this chapter describes the deserial serial peripheral interface (dspi) , which provides a synchronous serial bus for communication between the mcu and an external peripheral device. 10.2 block diagram a block diagram of the dspi is shown in figure 10-1 . figure 10-1. dspi block diagram 10.3 overview the register content is trans mitted using an spi protocol. for queued operations the spi queues reside in inte rnal sram which is external to the dspi. data transfers between the queues and the dspi fifos are accomplished through the use of the edma controller or through host software. cmd dma and interrupt control tx fifo rx fifo tx data rx data 16 16 shift register sout _x spi spi baud rate, delay and transfer control sin _x sck _x cs 0_x cs1:4 _x cs5 _x intc edma 4
pxd20 microcontroller reference manual, rev. 1 10-2 freescale semiconductor preliminary?subject to change without notice figure 10-2 shows a dspi with external queues in internal sram. figure 10-2. dspi with queues and edma 10.4 features the dspi supports these spi features: ? full-duplex, three-wire synchronous transfers ? master and slave mode ? buffered transmit and r eceive operation using the tx and rx fi fos, with depths of five entries ? visibility into tx and rx fifos for ease of debugging ? fifo bypass mode for low-latency updates to spi queues ? programmable transfer attributes on a per-frame basis ? 8 clock and transfer attribute registers ? serial clock with programmable polarity and phase ? programmable delays ? cs to sck delay ? sck to cs delay ? delay between frames ? programmable serial frame size of 4 to 16 bits, expanda ble with software control ? continuously held chip select capability ? 3 peripheral chip select s, expandable to 8 with external demultiplexer ? 2 dma conditions for spi queues residing in ram or flash ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) ? 6 interrupt conditions: ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) internal sram tx queue rx queue address/control tx fifo dspi rx fifo rx data tx data tx data rx data shift register edma controller address/control or host cpu
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-3 preliminary?subject to change without notice ? rx fifo is not empty (rfdf) ? fifo overrun (attempt to transmit with an empt y tx fifo or serial frame received while rx fifo is full) (rfof) ? fifo under flow (slave only and spi mode, the slave is asked to transfer data when the tx fifo is empty) (tfuf) ? modified spi transfer formats for comm unication with slower peripheral devices ? continuous serial comm unications clock (sck) 10.5 modes of operation the dspi has five modes of operation. these modes can be divided into two categories: ? module-specific modes such as mast er, slave, and module disable modes ? mcu-specific modes such as external stop and debug modes the module-specific modes are ente red by host software writing to a register. the mcu-specific modes are controlled by signals external to the dspi. the mcu-specific modes are modes that the entire device may enter, in parallel to the dspi bei ng in one of its module-specific modes. 10.5.1 master mode master mode allows the dspi to in itiate and control seri al communication. in this mode the sck, and cs n signals are controlled by the dspi and confi gured as outputs. (sout is always an output.) for more information, refer to section 10.9.1.1, master mode . 10.5.2 slave mode slave mode allows the dspi to communicate with spi bus masters. in this mode the dspi responds to externally controlled serial transfers. the dspi cannot initiate serial transfers in slave mode. in slave mode, the sck signal and the cs0_ x signal are configured as input s and provided by a bus master. cs0_ x must be configured as input and pul led high. if the internal pullup is be ing used then the appropriate bits in the relevant siu_pcr must be se t (siu_pcr [wpe = 1], [wps = 1]). ? all frames need to be masked when operating in fast continuous mode.(user cannot switch to continuous mode (delay s not masked) and come back to th e fast continuous mode when fast continuous mode of operation is selected). ? cpha is to be kept "1" when op erating in fast continuous mode. for more information, refer to section 10.9.1.2, slave mode . 10.5.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi is stopped while in module disabl e mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. for more information, refer to section 10.9.1.3, module disable mode .
pxd20 microcontroller reference manual, rev. 1 10-4 freescale semiconductor preliminary?subject to change without notice 10.5.4 external stop mode the external stop mode is used for mcu power ma nagement. the dspi supports the ipi green-line interface stop mode mechanism. when a request is made to enter ex ternal stop mode, the dspi block acknowledges the request and complete s the transfer in progress. when the dspi reaches the frame boundary it signals that the system clocks to the dspi block may be shut off. 10.5.5 debug mode debug mode is used for system development and de bugging. if the device enters debug mode while the frz bit in the dspi x _mcr is set, the dspi halts operation on th e next frame boundary. if the device enters debug mode while the frz bit is cleared, the dspi be havior is unaffected and remains dictated by the module-specific mode and c onfiguration of the dspi. for more information, refer to section 10.9.1.5, debug mode . 10.6 device-specific information this device implements dspi 0, dspi 1, and dspi 2. th e "x" appended to signal na mes signifies the dspi module to which the signal applies. thus cs0_0 is the cs0 signal that a pplies to dspi 0, cs0_1 is the cs0 signal that applies to dspi 1, and so on. 10.7 external signal description 10.7.1 signal overview table 10-1 lists off-chip dspi signals. table 10-1. signal properties name i/o type function master mode slave mode cs0_ x output / input peripheral ch ip select 0 slave select cs1:2_x output peripheral chip select 1?2 unused 1 1 the siu allows you to select alte rnate pin functions for the device. sin_x input serial data in serial data in sout_x output serial data out serial data out sck_x output / input serial clock (output) serial clock (input)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-5 preliminary?subject to change without notice 10.7.2 signal names and descriptions 10.7.2.1 peripheral chip sele ct / slave select (cs_0 ) in master mode, the cs_0 signal is a peripheral chip select output that selects the slave device to which the current transmission is intended. in slave mode, the cs_0 signal is a slave select input si gnal that allows an spi ma ster to select the dspi as the target for transmission. cs_0 must be configured as input and pulled high. if the internal pullup is being used then the appropriate bits in the re levant siu_pcr must be set (siu_pcr [wpe = 1], [wps = 1]). set the ibe and obe bits in the si u_pcr for all cs_0 pins when the dspi chip select or slave select primary function is selected for that pin. when the pin is used for dspi master mode as a chip select output, set the obe bit. when the pin is used in dspi sl ave mode as a slave select input, set the ibe bit. 10.7.2.2 peripheral chip selects 1?2 (cs1:2) cs1:2 are peripheral chip select out put signals in master mode. in slav e mode these signals are not used. 10.7.2.3 serial input (sin_ x ) sin_ x is a serial data input signal. 10.7.2.4 serial output (sout_ x ) sout_ x is a serial data output signal. 10.7.2.5 serial clock (sck_ x ) sck_ x is a serial communication clock signal. in mast er mode, the dspi generates the sck. in slave mode, sck_ x is an input from an external bus master. 10.8 memory map and register description 10.8.1 memory map table 10-2 shows the dspi memory map. table 10-2. dspi detailed memory map address register description location base: 0xfff9_0000 (dspi 0) 0xfff9_4000 (dspi 1) 0xfff9_8000 (dspi 2) dspi module configuration register (dspi x _mcr) on page 10-7 base + 0x0004 reserved ?
pxd20 microcontroller reference manual, rev. 1 10-6 freescale semiconductor preliminary?subject to change without notice base + 0x0008 dspi transfer count register (dspi x _tcr) on page 10-10 base + 0x000c dspi clock and transfer attributes register 0 (dspi x _ctar0) on page 10-10 base + 0x0010 dspi clock and transfer attributes register 1 (dspi x _ctar1) on page 10-10 base + 0x0014 dspi clock and transfer attributes register 2 (dspi x _ctar2) on page 10-10 base + 0x0018 dspi clock and transfer attributes register 3 (dspi x _ctar3) on page 10-10 base + 0x001c dspi clock and transfer attributes register 4 (dspi x _ctar4) on page 10-10 base + 0x0020 dspi clock and transfer attributes register 5 (dspi x _ctar5) on page 10-10 base + 0x0024 dspi clock and transfer attributes register 6 (dspi x _ctar6) on page 10-10 base + 0x0028 dspi clock and transfer attributes register 7 (dspi x _ctar7) on page 10-10 base + 0x002c dspi status register (dspi x _sr) on page 10-16 base + 0x0030 dspi dma/interrupt request select and enable register (dspi x _rser) on page 10-18 base + 0x0034 dspi push tx fifo register (dspi x _pushr) on page 10-20 base + 0x0038 dspi pop rx fifo register (dspi x _popr) on page 10-22 base + 0x003c dspi transmit fifo register 0 (dspi x _txfr0) on page 10-23 base + 0x0040 dspi transmit fifo register 1 (dspi x _txfr1) on page 10-23 base + 0x0044 dspi transmit fifo register 2 (dspi x _txfr2) on page 10-23 base + 0x0048 dspi transmit fifo register 3 (dspi x _txfr3) on page 10-23 base + 0x004c dspi transmit fifo register 4 (dspi x _txfr4) on page 10-23 base + 0x0050? base + 0x0078 reserved ? base + 0x007c dspi receive fifo register 0 (dspi x _rxfr0) on page 10-23 table 10-2. dspi detailed memory map (continued) address register description location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-7 preliminary?subject to change without notice 10.8.2 register description 10.8.2.1 dspi module configuration register (dspi x _mcr) the dspi x _mcr contains bits which confi gure attributes of th e dspi operation. the values of the halt and mdis bits can be cha nged at any time, but their effect begi ns on the next frame boundary. the halt and mdis bits in the dspi x _mcr are the only bit valu es software can change while the dspi is running. table 10-3 describes the fields in the d spi module configur ation register. base + 0x0080 dspi receive fifo register 1 (dspi x _rxfr1) on page 10-23 base + 0x0084 dspi receive fifo register 2 (dspi x _rxfr2) on page 10-23 base + 0x0088 dspi receive fifo register 3 (dspi x _rxfr3) on page 10-23 base + 0x008c dspi receive fifo register 4 (dspi x _rxfr4) on page 10-23 base + 0x0090? base + 0x00cc reserved ? address: base + 0x0000 access: r/w 0 1 23456789101112131415 r mst r cont_ scke dconf frz mtf e 0 ro oe 00 pcsi s5 pcsi s4 pcsi s3 pcsi s2 pcsi s1 pcsi s0 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 mdis dis_ txf dis_ rxf clr_ txf clr_ rxf smpl_pt 0000000 halt w w1c w1c reset0 1 00000000000001 figure 10-3. dspi module c onfiguration register (dspi x _mcr) table 10-2. dspi detailed memory map (continued) address register description location
pxd20 microcontroller reference manual, rev. 1 10-8 freescale semiconductor preliminary?subject to change without notice table 10-3. dspi x _mcr field descriptions field description 0 mstr master/slave mode select. configures the dspi for master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode 1 cont_scke continuous sck enable. enables the serial communication clock (sck) to run continuously. refer to section 10.9.6, continuous serial communications clock , for details. 0 continuous sck disabled 1 continuous sck enabled 2?3 dconf [0:1] dspi configuration. the following table lists the dconf values for the various configurations. 4 frz freeze. enables the dspi transfers to be stopped on the next frame boundary when the device enters debug mode. 0 do not halt serial transfers 1 halt serial transfers 5 mtfe modified timing format enable. enables a modified transfer format to be used. refer to section 10.9.5.4, modified spi trans fer format (mtfe = 1, cpha = 1) , for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled 6 reserved. this bit is writable, but has no effect. 7 rooe receive fifo overflow overwrite enable. enables an rx fifo overflow condition to ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is received, the data from the transfer that generated the overfl ow is ignored or put in the shift register. if the rooe bit is set, the incoming data is put in the shift register. if the rooe bit is cleared, the incoming data is ignored. refer to section 10.9.7.6, receive fifo overflow interrupt request (rfof) , for more information. 0 incoming data is ignored 1 incoming data is put in the shift register 8?9 reserved, but implemented. these bits are writable, but have no effect. 10?15 pcsis n peripheral chip select inactive state. determines the inacti ve state of the cs0_ x signal. cs0_ x must be configured as inactive high for slave mode operation. 0 the inactive state of cs0_ x is low 1 the inactive state of cs0_ x is high dconf configuration 00 spi 01 invalid value 10 invalid value 11 invalid value
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-9 preliminary?subject to change without notice 16 reserved. 17 mdis module disable. allows the clock to stop to the non-memory mapped logic in the dspi, effectively putting the dspi in a software controlled power-saving state. refer to section 10.9.8, power saving features, for more information. the reset value of the mdis bit is parameterized, with a default reset value of 0. 0 enable dspi clocks 1 allow external logic to disable dspi clocks 18 dis_txf disable transmit fifo. enables and disables th e tx fifo. when the tx fifo is disabled, the transmit part of the dspi operates as a simplified double-buffered spi. refer to section 10.9.3.3, fifo disable operation, for details. 0 tx fifo is enabled 1 tx fifo is disabled 19 dis_rxf disable receive fifo. enables and disables the rx fifo. when the rx fifo is disabled, the receive part of the dspi operates as a simplified double-buffered spi. refer to section 10.9.3.3, fifo disable operation, for details. 0 rx fifo is enabled 1 rx fifo is disabled 20 clr_txf clear tx fifo. flushes the tx fifo. write a 1 to the clr_txf bit to clear the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter 21 clr_rxf clear rx fifo. flushes the rx fifo. write a 1 to the clr_rxf bit to clear the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter 22?23 smpl_ pt [0:1] sample point. allows the host software to select when the dspi master samples sin in modified transfer format. figure 10-16 shows where the master can sample the sin pin. the following table lists the delayed sample points. 24?30 reserved. 31 halt halt. provides a mechanism for software to start and stop dspi transfers. refer to section 10.9.2, start and stop of dspi transfers , for details on the operation of this bit. 0 start transfers 1 stop transfers table 10-3. dspi x _mcr field descriptions (continued) field description smpl_pt number of system clock cycles between odd-numbered edge of sck_ x and sampling of sin_ x . 00 0 01 1 10 2 11 invalid value
pxd20 microcontroller reference manual, rev. 1 10-10 freescale semiconductor preliminary?subject to change without notice 10.8.2.2 dspi transfer count register (dspi x _tcr) the dspi x _tcr contains a counter that i ndicates the number of spi transf ers made. the tr ansfer counter is intended to assist in queue management. the user must not write to the dspi x _tcr while the dspi is running. table 10-4 describes the field in the dspi transfer count register. 10.8.2.3 dspi clock and transfer attributes registers 0?7 (dspi x _ctar n ) the dspi modules each contain eight cloc k and transfer attr ibute registers (dspi x _ctar n ) which are used to define different transfer attribute configurations. each dspi x _ctar controls: ?frame size ? baud rate and transfer delay values ? clock phase ? clock polarity ? msb or lsb first at the initiation of an spi transf er, control logic selects the dspi x _ctar that contains the transfer?s attributes.do not write to the dspi x _ctars while the dspi is running. in master mode, the dspi x _ctar n registers define combinations of tran sfer attributes such as frame size, clock phase and polarity, data bit or dering, baud rate, and vari ous delays. in slave mode , a subset of the bit address: base + 0x0008 access: r/w 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 10-4. dspi transfer count register (dspi x _tcr) table 10-4. dspi x _tcr field descriptions field description 0?15 spi_tcnt [0:15] spi transfer counter. counts the number of spi transfer s the dspi makes. the spi_tcnt field is incremented every time the last bit of an spi frame is transmitted. a va lue written to spi_tcnt presets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer counter ?wraps around,? incrementing the counter pas t 65535 resets the counter to zero. 16?31 reserved.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-11 preliminary?subject to change without notice fields in the dspi x _ctar0 and dspi x _ctar1 registers are used to set th e slave transfer attributes. refer to the individual bit descriptions for deta ils on which bits are used in slave modes. when the dspi is configured as an spi master, th e ctas field in the command portion of the tx fifo entry selects which of the dspi x _ctar registers is used on a per-frame basis. when the dspi is configured as an spi bus slave, the dspi x _ctar0 register is used. . address: base + 0x000c (dspi x _ctar0) base + 0x0010 (dspi x _ctar1) base + 0x0014 (dspi x _ctar2) base + 0x0018 (dspi x _ctar3) base + 0x001c (dspix_ctar4) base + 0x0020 (dspi x _ctar5) base + 0x0024 (dspi x _ctar6) base + 0x0028 (dspi x _ctar7) access: r/w 0123456789101112131415 r dbr fmsz cpo l cph a lsb fe pcssck pasc pdt pbr w reset0111100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset0000000000000000 figure 10-5. dspi clock and transfer attributes registers 0?7 (dspi x _ctarn) table 10-5. dspi x _ctar n field descriptions field descriptions 0 dbr double baud rate. the dbr bit doubles the effective baud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in ta b l e 1 0 - 6 . see the br field description for details on how to compute the baud rate. if the overall baud rate is divide by two or divide by three of the system clock then neither t he continuous sck enable or the modified timing format enable bits should be set. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is doubled with the duty cycle depending on the baud rate prescaler 1?4 fmsz[0:3] frame size. the fmsz field selects the number of bi ts transferred per frame. the fmsz field is used in master mode and slave mode. ta b l e 1 0 - 7 lists the frame size encodings. when operating in tsb confirmation, the fmsz defines the point with in the 32-bit (maximum length) frame where control of the cs switches from th e dspi_dsicr to the dspi_dsicr1 register. the cross over point must range between 4 bits and 16 bits and is encoded per ta bl e 1 0 - 7 . the remaining frame after the cross over point, regardless of how many bits are remaining, will be controlled by the dspi_dsicr1 register.
pxd20 microcontroller reference manual, rev. 1 10-12 freescale semiconductor preliminary?subject to change without notice 5 cpol clock polarity. the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock po larities. when the continuous selection format (see section 10.9.5.5, continuous selection format ) is selected, switching between clock polarities without stopping the dspi can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high 6 cpha clock phase. the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. this bit is used in both master and slave mode. for successful communication between serial devices, the device s must have identical clock phase settings. continuous sck is only supported for cpha=1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge 7 lsbfe lsb first. the lsbfe bit selects if the lsb or msb of the frame is transferred first. this bit is only used in master mode. when operating in tsb configuration, this bit should be always 1. 0 data is transferred msb first 1 data is transferred lsb first 8?9 pcssck[0:1 ] pcs to sck delay prescaler. the pcssck field se lects the prescaler value for the delay between assertion of pcs and the first edge of the sck. this field is only used in master mode. the table below lists the prescaler values. see the cssck[0:3] field description for details on how to compute the pcs to sck delay. 10?11 pasc[0:1] after sck delay prescaler. the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. this field is only used in master mode. the table below lists the prescaler values. see the asc[0:3] field description for details on how to compute the after sck delay. table 10-5. dspi x _ctar n field descriptions (continued) field descriptions pcssck pcs to sck delay prescaler value 00 1 01 3 10 5 11 7 pasc after sck delay prescaler value 00 1 01 3 10 5 11 7
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-13 preliminary?subject to change without notice 12?13 pdt[0:1] delay after transfer prescaler. the pdt field selects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. the pdt field is only used in master mode. the table below lists the prescaler values. see the dt[0:3] field description for details on how to compute the delay after transfer. 14?15 pbr[0:1] baud rate prescal. the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the frequency of the serial communications clock (sck). the system clock is divided by the prescaler value befo re the baud rate selectio n takes place. the baud rate prescaler values are listed in the table below. see the br[0:3] field description for details on how to compute the baud rate. 16?19 cssck[0:3] pcs to sck delay scaler. the cssck field selects the scaler value for the pc s to sck delay. this field is only used in master mode. the pcs to sc k delay is the delay between the assertion of pcs and the first edge of the sck. ta bl e 1 0 - 8 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is computed according to the following equation: eqn. 10-1 20?23 asc[0:3] after sck delay scaler. the asc field selects the scaler value for the after sck delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. table 10-9 list the scaler values .the after sck delay is a multiple of the system clock period, and it is computed according to the following equation: eqn. 10-2 table 10-5. dspi x _ctar n field descriptions (continued) field descriptions pdt delay after transfer prescaler value 00 1 01 3 10 5 11 7 pbr baud rate prescaler value 00 2 01 3 10 5 11 7 t csc 1 f sys ---------- - pcssck cssck ? ? = t asc 1 f sys ----------- pasc ? asc ? =
pxd20 microcontroller reference manual, rev. 1 10-14 freescale semiconductor preliminary?subject to change without notice 24?27 dt[0:3] delay after transfer scaler. the dt field selects the delay after transfer scaler. this field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. ta b l e 1 0 - 1 0 lists the scaler values. in the continuous serial communicatio ns clock operation the dt value is fixed to one tsck, except when the tsbc bit from dspi_dsicr register is enab ling the tsb configuration. the delay after transfer is a multiple of the system cl ock period and it is co mputed according to the following equation: eqn. 10-3 28?31 br[0:3] baud rate scaler. the br field selects the scaler value for the baud rate. this field is only used in master mode. the prescaled system clock is divided by the baud rate scaler to generate the frequency of the sck. table 10-11 lists the baud rate scaler values.the baud rate is computed according to the following equation: eqn. 10-4 table 10-6. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 10-7. dspi transfer frame size fmsz framesize fmsz framesize 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 10-5. dspi x _ctar n field descriptions (continued) field descriptions t dt 1 f sys ----------- pdt ? dt ? = sck baud rate f sys pbr ----------- - 1dbr + br --------------------- - ? =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-15 preliminary?subject to change without notice table 10-8. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value c ssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 10-9. dspi after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 10-10. dspi delay after transfer scaler dt delay after transfer scaler value dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536
pxd20 microcontroller reference manual, rev. 1 10-16 freescale semiconductor preliminary?subject to change without notice 10.8.2.4 dspi status register (dspi x _sr) the dspi x _sr contains status and flag bits. the bits are se t by the hardware and reflect the status of the dspi and indicate the occurrence of events that can generate interr upt or dma requests. software can clear flag bits in the dspi x _sr by writing a 1 to clear it (w1c). wr iting a 0 to a flag bit has no effect. table 10-12 describes the fields in the dspi status register. table 10-11. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 address: base + 0x002c access: r/w 0 1 2 3 4 5 6 7 8 9 101112131415 r tcf txrx s 0 eoq f tfu f 0tfff0 0 0 0 0 rfo f 0 rfd f 0 w w1c w1c w1c w1c w1c w1c reset0 0 0 0 001000 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0 0 0 0 000000 0 0 0 0 0 0 dspi status register (dspi x _sr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-17 preliminary?subject to change without notice table 10-12. dspi x _sr field descriptions field description 0 tcf transfer complete flag. indicates that all bits in a frame have been shifted out. the tcf bit is set after the last incoming databit is sampled, but before the tasc delay starts. refer to section 10.9.5.1, classic spi transfer format (cpha = 0) for details. the tcf bit is cleared by writing 1 to it. 0 transfer not complete 1 transfer complete 1 txrxs tx and rx status. reflects the status of the dspi. refer to section 10.9.2, start and stop of dspi transfers for information on what clears and sets this bit. 0 tx and rx operations are disa bled (dspi is in stopped state) 1 tx and rx operations are enabled (dspi is in running state) 2 reserved. 3 eoqf end of queue flag. indicates that transmission in progress is the last entry in a queue. the eoqf bit is set when the tx fifo entry has the eoq bi t set in the command halfword and after the last incoming databit is sampled, but before the tasc delay starts. refer to section 10.9.5.1, classic spi transfer format (cpha = 0) for details. the eoqf bit is cleared by writing 1 to it. when th e eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executing command 1 eoq bit is set in the executing spi command note: eoqf does not function in slave mode. 4 tfuf transmit fifo underflow flag. indicates that an und erflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in spi slave mode is empty, and a transfer is initiated by an external spi master. the tfuf bit is cleared by writing 1 to it. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred 5 reserved. 6 tfff transmit fifo fill flag. indicates t hat the tx fifo can be filled. pr ovides a method for the dspi to request more entries to be added to the tx fifo. th e tfff bit is set while t he tx fifo is not full. the tfff bit can be cleared by writing 1 to it, or an by acknowledgement fr om the edma controller when the tx fifo is full. 0 tx fifo is full 1 tx fifo is not full 7?11 reserved. 12 rfof receive fifo overflow flag. indicates that an over flow condition in the rx fifo has occurred. the bit is set when the rx fifo and shift register are full and a transfer is initiated. the bit is cleared by writing 1 to it. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred 13 reserved.
pxd20 microcontroller reference manual, rev. 1 10-18 freescale semiconductor preliminary?subject to change without notice 10.8.2.5 dspi dma / interrupt request select and enable register (dspi x _rser) the dspi x _rser serves two purposes: enables flag bits in the dspi x _sr to generate dma requests or interrupt requests, and selects the type of request to generate . refer to the bit descriptions for the type of requests that are supported. do not write to the dspi x _rser while the dspi is running. 14 rfdf receive fifo drain flag. indicates that the rx fifo can be drained. provides a method for the dspi to request that entries be removed from the rx fifo. the bit is set while the rx fifo is not empty. the rfdf bit can be cleared by writing 1 to it, or by acknowledgement from the edma controller when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty note: in the interrupt service routin e, rfdf must be cleared only after the dspix_ popr register is read. 15 reserved. 16?19 txctr [0:3] tx fifo counter. indicates the nu mber of valid entries in the tx fifo. the txctr is incremented every time the dspi _pushr is written. the tx ctr is decremented every time an spi command is executed and the spi data is transferred to the shift register. 20?23 txnxtptr [0:3] transmit next pointer. indicates which tx fifo entry is transmitted during the next transfer. the txnxtptr field is updated every time spi data is tr ansferred from the tx fifo to the shift register. refer to section 10.9.3.4, transmit first in fi rst out (tx fifo) buffering mechanism for more details. 24?27 rxctr [0:3] rx fifo counter. indicates the number of entr ies in the rx fifo. the rxctr is decremented every time the dspi _popr is read. the rxctr is incremented after the last incoming databit is sampled, but before the tasc delay starts. refer to section 10.9.5.1, classic spi transfer format (cpha = 0) for details. 28?31 popnxtptr [0:3] pop next pointer. contains a pointer to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr is updated when the dspi x _popr is read. refer to section 10.9.3.5, receive first in first out (rx fifo) buffering mechanism for more details. address: base + 0x0030 access: r/w 0123456789101112131415 r tcf_ re 00 eoq f_re tfuf _re 0 tfff _re tfff _ dirs 0000 rfof _re 0 rfdf _re rfdf_ dirs w reset000000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 0 w reset000000000000000 0 figure 10-6. dspi dma / interrupt request select and enable register (dspi x _rser) table 10-12. dspi x _sr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-19 preliminary?subject to change without notice table 10-13 describes the fields in the dspi dma / interrupt re quest and enable register. table 10-13. dspi x _rser field descriptions field description 0 tcf_re transmission complete request enable. enables tcf flag in the dspi x _sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled 1?2 reserved. 3 eoqf_re dspi finished request enable. enables the eoqf flag in the dspi x _sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled 4 tfuf_re transmit fifo underflow request enable. the tf uf_re bit enables the tfuf flag in the dspi x _sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled 5 reserved. 6 tfff_re transmit fifo fill request enable. enables the tfff flag in the dspi x _sr to generate a request. the tfff_dirs bit selects between generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled 7 tfff_dirs transmit fifo fill dma or interrupt request sele ct. selects between generating a dma request or an interrupt request. when the tfff flag bit in the dspi x _sr is set, and the tfff_re bit in the dspi x _rser is set, this bit selects between gener ating an interrupt request or a dma request. 0 interrupt request is selected 1 dma request is selected 8?11 reserved. 12 rfof_re receive fifo overflow request enable. enables the rfof flag in the dspi x _sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled 13 reserved. 14 rfdf_re receive fifo drain request enable. enables the rfdf flag in the dspi x _sr to generate a request. the rfdf_dirs bit selects between generati ng an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled
pxd20 microcontroller reference manual, rev. 1 10-20 freescale semiconductor preliminary?subject to change without notice 10.8.2.6 dspi push tx fifo register (dspi x _pushr) the dspi x _pushr provides a means to write to the tx fifo. data written to this register is transferred to the tx fifo. refer to section 10.9.3.4, transmit first in first out (tx fifo) buffering mechanism , for more information. write accesse s of 8- or 16-bits to the dspi x _pushr transfers 32 bits to the tx fifo. note txdata is used in master and slave modes. table 10-14 describes the fields in the d spi push transmit fifo register. 15 rfdf_dirs receive fifo drain dma or interrupt request se lect. selects between gener ating a dma request or an interrupt request. when the rfdf flag bit in the dspi x _sr is set, and the rfdf_re bit in the dspi x _rser is set, the rfdf_dirs bit selects betw een generating an interrupt request or a dma request. 0 interrupt request is selected 1 dma request is selected 16?31 reserved. address: base + 0x0034 access: r/w 0123456789101112131415 r con t ctas eoq ct cnt 00 00 000 pcs 2 pcs 1 pcs 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset0000000000000000 figure 10-7. dspi push tx fifo register (dspi x _pushr) table 10-13. dspi x _rser field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-21 preliminary?subject to change without notice table 10-14. dspi x _pushr field descriptions field description 0 cont continuous peripheral chip select enable. selects a co ntinuous selection format. the bit is used in spi master mode. the bit enables the selected cs signals to remain asserted between transfers. refer to section 10.9.5.5, continuous selection format , for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers 1?3 ctas [0:2] clock and transfer attributes select. selects which of the dspi x _ctars is used to set the transfer attributes for the spi frame. in spi slave mode, dspi x _ctar0 is used. the following table shows how the ctas values map to the dspi x _ctars. there are eight dspi x _ctars in the device dspi implementation. note: use in spi master mode only. 4 eoq end of queue. provides a means for host software to si gnal to the dspi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi x _sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer note: use in spi master mode only. 5 ctcnt clear spi_tcnt. provides a means for host software to clear the spi transfer counter. the ctcnt bit clears the spi_tcnt field in the dspi x _tcr. the spi_tcnt field is clea red before transmission of the current spi frame begins. 0 do not clear spi_tcnt field in the dspi x _tcr 1 clear spi_tcnt field in the dspi x _tcr note: use in spi master mode only. 6?7 reserved. 8?9 reserved, but implemented. these bits are writable, but have no effect. 10?12 reserved. ctas use clock and transfer attributes from 000 dspi x _ctar0 001 dspi x _ctar1 010 dspi x _ctar2 011 dspi x _ctar3 100 dspi x _ctar4 101 dspi x _ctar5 110 dspi x _ctar6 111 dspi x _ctar7
pxd20 microcontroller reference manual, rev. 1 10-22 freescale semiconductor preliminary?subject to change without notice 10.8.2.7 dspi pop rx fifo register (dspi x _popr) the dspi x _popr allows you to read the rx fifo. refer to section 10.9.3.5, receive first in first out (rx fifo) buffering mechanism for a description of the rx fifo operations. eight or 16-bit read accesses to the dspi x _popr fetch the rx fifo data, a nd update the counter and pointer. note reading the rx fifo field fetches da ta from the rx fifo. once the rx fifo is read, the read data pointer is moved to the next entry in the rx fifo. therefore, read dspi x _popr only when you need the data. for compatibility, configure the tl b (mmu table) entry for dspi x _popr as guarded. table 10-15 describes the fields in the dspi pop receive fifo register. 13?15 pcs x peripheral chip select x . selects which cs x signals are asserted for the transfer. 0 negate the cs x signal 1 assert the cs x signal note: use in spi master mode only. 16?31 txdata [0:15] transmit data. holds spi data for transfe r according to the associated spi command. note: use txdata in master and slave modes. address: base + 0x0038 access: r/o 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 figure 10-8. dspi pop rx fifo register (dspi x _popr) table 10-14. dspi x _pushr field descrip tions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-23 preliminary?subject to change without notice 10.8.2.8 dspi transmit fi fo registers 0?4 (dspi x _txfr n ) the dspi x _txfr n registers provide visibility into the tx fifo for debugging purposes . each register is an entry in the tx fifo. the registers are re ad-only and cannot be m odified. reading the dspi x _txfr n registers does not alter th e state of the tx fifo. table 10-16 describes the fields in the dspi transmit fifo register. 10.8.2.9 dspi receive fifo registers 0?4 (dspi x _rxfr n ) the dspi x _rxfr n registers provide visibility into the rx fifo for debuggi ng purposes. each register is an entry in the rx fifo. the dspi x _rxfr registers are read-only. reading the dspi x _rxfr n registers does not alter the stat e of the rx fifo. table 10-15. dspi x _popr field descriptions field description 0?15 reserved, must be cleared. 16?31 rxdata [0:15] received data. the rxdata field contains the spi dat a from the rx fifo entry pointed to by the pop next data pointer (popnxtptr). address: base + 0x003c (dspi x _txfr0) base + 0x0040 (dspi x _txfr1) base + 0x0044 (dspi x _txfr2) base + 0x0048 (dspi x _txfr3) base + 0x004c (dspi x _txfr4) access: r/o 0123456789101112131415 rtxcmd w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset0000000000000000 figure 10-9. dspi transmit fifo register 0?4 (dspi x _txfr n ) table 10-16. dspi x _txfr n field descriptions field description txcmd transmit command. contains the command that sets the transfer attributes for the spi data. refer to section 10.8.2.6, dspi push tx fifo register (dspix_pushr) , for details on the command field. txdata transmit data. contains the spi data to be shifted out.
pxd20 microcontroller reference manual, rev. 1 10-24 freescale semiconductor preliminary?subject to change without notice table 10-17 describes the field in the dspi receive fifo register. 10.9 functional description the dspi supports full-duplex, s ynchronous serial communications between the mcu and peripheral devices. all communica tions are through an spi-like protocol. the dspi has one configuration: ? serial peripheral interface (spi) configuration in which the dspi operates as a basic spi or a queued spi. the dconf field in the dspi x _mcr register determines the dspi configuration. refer to table 10-3 for the dspi configuration values. the dspi x _ctar0?dspi x _ctar7 registers hold clock and transfer attributes.t he spi configuration can select which ctar to use on a frame by fram e basis by setting the ctas field in the dspi x _pushr. the 16-bit shift register in the master and the 16-bit shift register in the sl ave are linked by the sout_ x and sin_ x signals to form a distributed 32-bit register. when a data tran sfer operation is performed, data is serially shifted a predetermined number of bit pos itions. because the registers are linked, data is exchanged between the master and the slave; the data th at was in the master?s shift register is now in the shift register of the slave, a nd vice versa. at the end of a tr ansfer, the tcf bit in the dspi x _sr is set to indicate a completed transfer. figure 10-11 illustrates how master and slave data is exchanged. address: base + 0x007c (dspi x _rxfr0) base + 0x0080 (dspi x _rxfr1) base + 0x0084 (dspi x _rxfr2) base + 0x0088 (dspi x _rxfr3) base + 0x008c (dspi x _rxfr4) access: r/o 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 figure 10-10. dspi receive fifo registers 0?4 (dspi x _rxfr n ) table 10-17. dspi x _rxfr n field descriptions field description rxdata receive data. contains the received spi data.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-25 preliminary?subject to change without notice figure 10-11. spi serial protocol overview the dspi has three peri pheral chip select (cs x ) signals that are be used to select which of the slaves to communicate with. transfer protocols and timing propert ies are shared by the three dspi c onfigurations; these properties are described independently of the configuration in section 10.9.5, transfer formats . the transfer rate and delay settings are de scribed in section section 10.9.4, dspi baud rate and clock delay generation . refer to section 10.9.8, power saving features for information on the power- saving features of the dspi. 10.9.1 modes of operation the dspi modules have five available distinct modes: ? master mode ? slave mode ? module disable mode ? external stop mode ? debug mode master, slave, and module disable modes are module- specific modes. the exte rnal stop and debug modes are device-specific modes. the module-specific modes are de termined by bits in the dspi x _mcr. the device-specific modes are modes that the entire device can enter in parallel with the dspi being conf igured in one of its module-specific modes. 10.9.1.1 master mode in master mode the dspi can init iate communications with peripheral devices. the dspi operates as bus master when the mstr bit in the dspi x _mcr is set. the serial co mmunications clock (sck) is controlled by the master dspi. all three dspi configurations are va lid in master mode. in spi configuration, master mode tr ansfer attributes are c ontrolled by the spi command in the current tx fifo entry. the ctas field in the spi command selects which of the eight dspi x _ctars are used to set the transfer attributes. transfer attrib ute control is on a fr ame by frame basis. refer to section 10.9.3, serial peripheral interface (spi) configuration for more details. dspi master shift register baud rate generator dspi slave shift register sout_ x sin_ x sout_ x sin_ x sck_ x sck_ x cs_ x cs0_ x
pxd20 microcontroller reference manual, rev. 1 10-26 freescale semiconductor preliminary?subject to change without notice 10.9.1.2 slave mode in slave mode the dspi responds to transfers initiat ed by an spi master. the dspi operates as bus slave when the mstr bit in the dspi x _mcr is negated. the dspi slave is selected by a bus master by having the slave?s cs0_ x asserted. in slave mode the sck is provide d by the bus master. all transfer attributes are controlled by the bus master, except the clock polarit y, clock phase and the numbe r of bits to transfer which must be configured in the dspi slave to communicate correctly. 10.9.1.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi is stopped while in module disabl e mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. refer to section 10.9.8, power saving features , for more details on the module disable mode. 10.9.1.4 external stop mode for devices with low-power mode s, the dspi supports the global signal stop mode mechanism. the dspi will not acknowledge the request to enter external stop mode until it has reach ed a frame boundary. when the dspi has reached a frame boundary it will halt al l operations and indicate th at it is ready to have its clocks shut off. the dspi ex its external stop mode and resumes normal opera tion once the clocks are turned on. serial communications or register accesses made wh ile in external stop mode are ignored even if the clocks have not been shut off yet. see section 10.9.8, power saving features , for more details on the external stop mode. 10.9.1.5 debug mode the debug mode is used for system development a nd debugging. if the mcu ente rs debug mode while the frz bit in the dspi x _mcr is set, the dspi stops all serial transfers and enters a stopped state. if the mcu enters debug mode while th e frz bit is cleared, the ds pi behavior is unaffected and remains dictated by the module-specific mode and conf iguration of the dspi. the dspi enters debug mode when a debug request is asserted by an external controller. refer to figure 10-12 for a state diagram. 10.9.2 start and stop of dspi transfers the dspi has two operating states: stopped and running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the sto pped state no serial transfers are initiated in master mode and no tr ansfers are responded to in slave mode. the stopped state is also a safe state for writing the various c onfiguration registers of the dspi without causin g undetermined results. the txrxs bit in the dspi x _sr is cleared in this state. in the runn ing state, serial transfers take place. the txrxs bit in the dspi x _sr is set in the running state. figure 10-12 shows a state diag ram of the start and stop mechanism.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-27 preliminary?subject to change without notice figure 10-12. dspi start and stop state diagram the transitions are described in table 10-18 . state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 10.9.3 serial peripheral in terface (spi) configuration the spi configuration transfers data se rially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when th e dconf field in the dspi x _mcr is 0b00. the spi frames can be from 4 to 16 bits long. the data to be transmitted can come fr om queues stored in ram external to the dspi. host software or an edma controller can transf er the spi data from the queues to a first-in first-out (fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. host software or an edma controll er transfers the received data from the rx fifo to memory external to the dspi. the fifo buffer operations are described in section 10.9.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 10.9.3.5, receive first in first out (rx fifo) buffering mechanism . the interrupt and dma request conditions are described in section 10.9.7, interrupts/dma requests . the spi configuration supports two module-specific modes; master mode and slave mode. the fifo operations are similar for the master mode and slave mode. the main differ ence is that in master mode the table 10-18. state transitions for start and stop of dspi transfers transition # current st ate next state description 0 reset stopped generic power-on-reset transition 1 stopped running the dspi starts (transitions from stopped to running) when all of the following conditions are true: ? eoqf bit is clear ? debug mode is unselected or the frz bit is clear ? halt bit is clear 2 running stopped the dspi stops (transitions from running to stopped) after the current frame for any one of the following conditions: ? eoqf bit is set ? debug mode is selected and the frz bit is set ?halt bit is set running txrxs = 1 stopped txrxs = 0 reset power-on-reset 0 1 2
pxd20 microcontroller reference manual, rev. 1 10-28 freescale semiconductor preliminary?subject to change without notice dspi initiates and controls the transfer according to the fields in the spi command field of the tx fifo entry. in slave mode the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field of the tx fifo entry is ignored. 10.9.3.1 spi master mode in spi master mode the dspi initia tes the serial transfers by controll ing the serial communications clock (sck_ x ) and the peripheral chip select (cs x ) signals. the spi command fiel d in the executing tx fifo entry determines which ctars are used to set the transfer attributes and which cs x signal to assert. the command field also contains various bi ts that help with queue management and transfer protocol. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout _x ) pin. in spi master mode, each spi frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. refer to section 10.8.2.6, dspi push tx fi fo register (dspix_pushr) , for details on the spi command fields. 10.9.3.2 spi slave mode in spi slave mode the dspi responds to transfers initiated by an spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with an spi master. the spi slave mode transfer attr ibutes are set in the dspi x _ctar0. 10.9.3.3 fifo disable operation the fifo disable mechanisms allo w spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when th e fifos are disabled. the tx and rx fifos are disabled separately. the tx fi fo is disabled by writing a 1 to the dis_txf bit in the dspi x _mcr. the rx fifo is disabled by writing a 1 to the dis_rxf bit in the dspi x _mcr. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi x _pushr and receiv ed data is read from the dspi x _popr. when the tx fifo is disabled, the tfff, tfuf, and txctr fields in dspi x _sr behave as if th ere is a one-entry fifo but the contents of the dspi x _txfrs and txnxtptr are undefined. when the rx fifo is disabled, the rfdf, rfof, a nd rxctr fields in the dspi x _sr behave as if there is a one-entry fifo but the contents of the dspi x _rxfrs and popnxtptr are undefined. disable the tx and rx fifos only if the fifo must be disabled as a requirement of the application's operating mode. a fifo must be disabled before it is accessed. failure to disable a fifo prior to a first fifo access is not supported, and can result in incorrect results. 10.9.3.4 transmit first in first ou t (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands fo r transmission. the tx fifo holds five entries, each consisting of a co mmand field and a data field. spi commands and data are added to the tx fifo by writing to the dspi push tx fifo register (dspi x _pushr). for more information on
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-29 preliminary?subject to change without notice dspi x _pushr. tx fifo entries can only be removed from the tx fifo by being shifted out or by flushing the tx fifo. refer to section 10.8.2.6, dspi push tx fi fo register (dspix_pushr) . the tx fifo counter field (txctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the tx fifo. the txctr is updated every time the dspi _pus hr is written or spi data is transferred into the shift register from the tx fifo. refer to section 10.8.2.4, dspi status register (dspix_sr) for more information on dspi x _sr. the txnxtptr field indicates which tx fifo entr y is transmitted during the next transfer. the txnxtptr contains the pos itive offset from dspi x _txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the dspi x _txfr2 contains the spi data and command for the next transfer. the txnxtptr field is incr emented every time spi da ta is transferred from the tx fifo to the shift register. 10.9.3.4.1 filling the tx fifo host software or the edma controller can add (push) entries to the tx fifo by writing to the dspi x _pushr. when the tx fifo is not full, the tx fifo fi ll flag (tfff) in the dspi x _sr is set. the tfff bit is cleared when the tx fifo is full and the edma controller indi cates that a write to dspi x _pushr is complete or alternatively by host so ftware writing a 1 to the tfff in the dspi x _sr. the tfff can generate a dma request or an interrupt request. refer to section 10.9.7.2, transmit fifo fill interrupt or dma request (tfff) , for details. the dspi ignores attempts to push da ta to a full tx fifo; that is, th e state of the tx fifo is unchanged. no error condition is indicated. 10.9.3.4.2 draining the tx fifo the tx fifo entries are re moved (drained) by shifting spi data out through the sh ift register. entries are transferred from the tx fifo to the shift register and shifted out as l ong as there are valid entries in the tx fifo. every time an entry is tr ansferred from the tx fifo to the sh ift register, the tx fifo counter is decremented by one. at the end of a transfer, the tcf bit in the dspi x _sr is set to indicate the completion of a transfer. the tx fifo is flus hed by writing a 1 to the clr_txf bit in dspi x _mcr. if an external spi bus master init iates a transfer with a dspi slave while the slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi x _sr is set. refer to section 10.9.7.4, transmit fifo unde rflow interrupt request (tfuf) , for details. 10.9.3.5 receive first in first ou t (rx fifo) buffering mechanism the rx fifo functions as a buffer for data receiv ed on the sin pin. the rx fifo holds four received spi data frames. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fifo . spi data is removed (popped) from the rx fifo by reading the dspi x _popr register. rx fifo entries can only be removed from the rx fifo by reading the dspi x _popr or by flushing the rx fifo.
pxd20 microcontroller reference manual, rev. 1 10-30 freescale semiconductor preliminary?subject to change without notice refer to section 10.8.2.7, dspi pop rx fifo register (dspix_popr) for more information on the dspi x _popr. the rx fifo counter field (rxctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the rx fifo. the rxctr is updated ev ery time the dspi _popr is read or spi data is copied from the shift re gister to the rx fifo. the popnxtptr field in the dspi x _sr points to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr contains th e positive, 32-bit word offset from dspi x _rxfr0. for example, popnxtptr equal to two means that the dspi x _rxfr2 contains the received spi data that is returned when dspi x _popr is read. the popnxtptr fiel d is incremented every time the dspi x _popr is read. popnxtptr rolls ove r every four frames on the mcu. 10.9.3.5.1 filling the rx fifo the rx fifo is filled with the rece ived spi data from the shift regist er. while the rx fifo is not full, spi frames from the shift re gister are transferred to the rx fifo. every time an spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transfer is initiated, the rfof bit in the dspi x _sr is set indicating an overflow condition. depending on the state of the rooe bit in the dspi x _mcr, the data from the transfer that gene rated the overflow is ignored or put in the shift register . if the rooe bit is set, the incoming data is put in the shift register. if th e rooe bit is cleared, the incoming data is ignored. 10.9.3.5.2 draining the rx fifo host software or the edma ca n remove (pop) entries from th e rx fifo by reading the dspi x _popr. a read of the dspi x _popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored, the rx fifo counter remains unchanged. the data returned from reading an empty rx fifo is undetermined. refer to section 10.8.2.7, dspi pop rx fifo register (dspix_popr) for more information on dspi x _popr. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi x _sr is set. the rfdf bit is cleared when the rx_fifo is empty and the ed ma controller indicates that a read from dspi x _popr is complete; alternatively the rfdf bit ca n be cleared by the host writing a 1 to it. 10.9.4 dspi baud rate and clock delay generation the sck_ x frequency and the delay values for serial transfer are genera ted by dividing the system clock frequency by a prescaler and a scaler wi th the option of doubling the baud rate. figure 10-13 shows conceptually how th e sck signal is generated. figure 10-13. communications clock prescalers and scalers prescaler 1 scaler 1 + dbr system clock sck_x
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-31 preliminary?subject to change without notice 10.9.4.1 baud rate generator the baud rate is the frequency of the serial communication clock (sck_ x ). the system clock is divided by a baud rate prescaler (defined by dspi x _ctar[pbr]) and baud rate scaler (defined by dspi x _ctar[br]) to produce sck_ x with the possibility of doubling the baud rate. the dbr, pbr, and br fields in the dspi x _ctars select the frequency of sck_ x using the following formula: table 10-19 shows an example of a computed baud rate. 10.9.4.2 cs to sck delay (t csc ) the cs _x to sck _x delay is the length of time from assertion of the cs _x signal to the first sck _x edge. refer to figure 10-14 for an illust ration of the cs _x to sck _x delay. the pcssck and cssck fields in the dspi x _ctar n registers select the cs _x to sck _x delay, and the relationship is expressed by the following formula: table 10-20 shows an example of the computed cs to sck _x delay. 10.9.4.3 after sck delay (t asc ) the after sck _x delay is the length of time between the last edge of sck _x and the negation of cs _x . refer to figure 10-14 and figure 10-15 for illustrations of the after sck _x delay. the pasc and asc fields in the dspi x _ctar n registers select the after sck delay. the relationship between these variables is given in the following formula: table 10-21 shows an example of the computed after sck delay. table 10-19. baud rate computation example f sys pbr prescaler value br scaler value dbr value baud rate 100 mhz 0b00 2 0b0000 2 0 25 mb/sec 20 mhz 0b00 2 0b0000 2 1 10 mb/sec table 10-20. cs to sck delay computation example pcssck prescaler value cssck scaler value f sys cs to sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s sck baud rate f sys pbrprescalervalue ---------------------------------------------------------- 1dbr + brscalervalue -------------------------------------------- ? = t csc = f sys cssck ? pcssck 1 ? asc = f sys asc ? pasc 1 ?
pxd20 microcontroller reference manual, rev. 1 10-32 freescale semiconductor preliminary?subject to change without notice 10.9.4.4 delay after transfer (t dt ) the delay after transfer is the lengt h of time between negation of the cs x signal for a frame and the assertion of the cs x signal for the next frame. the pdt and dt fields in the dspi x _ctar n registers select the delay after transfer. refer to figure 10-14 for an illustration of the delay after transfer. the following formula expresses the pdt/ dt/delay after transfer relationship: table 10-22 shows an example of the computed delay after transfer. when in non-continuous clock mode the t dt delay is configurable as outlined in the dspi_ctarx registers. when in continuous clock mode and tsb is not enabled the de lay is fixed at 1 sck period. when in tsb and continuous mode the dela y is programmed as outli ned in the dspi_ctarx registers but in the event that the delay does not coincide with an sck pe riod in duration the delay is extended to the next sck active edge. table 10-23 shows an example of how to compute the delay after transfer with the clock period of sck defined as t sck . the values calculated assume 1 tsck period = 4 ipg_clk. table 10-21. after sck delay computation example pas c prescaler value asc scaler value f sys after sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s table 10-22. delay after transfer computation example pdt prescaler value dt scaler value f sys delay after transfer 0b01 3 0b1110 32768 100 mhz 0.98 ms t dt = f sys dt ? pdt 1 ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-33 preliminary?subject to change without notice 10.9.5 transfer formats the spi serial communication is controlled by the serial communications clock (sck_ x ) signal and the cs x signals. the sck_ x signal provided by the master device synchronizes shifting and sampling of the data by the sin_ x and sout_ x pins. the cs x signals serve as enable si gnals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi x _ctar n ) select the polarity and phase of the serial clock, sck_ x . the polarity bit selects the idle state of the sck_ x . the clock phase bit selects if the data on sout_ x is valid before or on the first sck_ x edge. when the dspi is the bus slave, cpol and cpha bits in the dspi x _ctar0 (spi slave mode) select the polarity and phase of the serial clock. even though th e bus slave does not control the sck signal, clock polarity, clock phase and number of b its to transfer must be identical for the master device and the slave device to ensure proper transmission. the dspi supports four different transfer formats: table 10-23. delay after transfer computation example in tsb configuration pdt field t dt 1 (tsck) 1 some values are not reachable (i. e. 9, 11, 13, 15, 17, 18, 19...). to calculate these values, please see equation 10-3 . 0123 dt field 0 2 2 the values in this row were rounded to the next integer value. 1234 1 1357 2261014 3 4 12 20 28 4 8 24 40 56 5 164880112 6 32 96 160 224 7 64 192 320 448 8 128 384 640 896 9 256 768 1280 1792 10 512 1536 2560 3584 11 1024 3072 5120 7168 12 2048 6144 10240 14336 13 4096 12288 20480 28672 14 8192 24576 40960 57344 15 16384 49152 81920 114688
pxd20 microcontroller reference manual, rev. 1 10-34 freescale semiconductor preliminary?subject to change without notice ? classic spi with cpha = 0 ? classic spi with cpha = 1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more set up time. the mtfe bit in the dspi x _mcr selects between classic spi format and modified transf er format. the classic spi formats are described in section 10.9.5.1, classic spi transfer format (cpha = 0) and section 10.9.5.2, classic spi transfer format (cpha = 1) . the modified transfer formats are described in section 10.9.5.3, modified spi tr ansfer format (mtfe = 1, cpha = 0) and section 10.9.5.4, modified spi transfer format (mtfe = 1, cpha = 1) . in the spi configuration, the dspi provides the option of keeping the cs signals asserted between frames. refer to section 10.9.5.5, continuous selection format for details. 10.9.5.1 classic spi transfer format (cpha = 0) the transfer format shown in figure 10-14 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format , the master and slave sample their sin_ x pins on the odd-numbered sck_ x edges and change the data on their sout_ x pins on the even-numbered sck_ x edges. figure 10-14. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) sck (cpol = 0) pcs x / ss t asc sck (cpol = 1) master and slave sample master sout / slave sin master sin / slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cscs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs idle time). master (cpha = 0): tcf and eoqf are set and rxctr counter is updated at next to last sck edge of frame (edge 15) slave (cpha = 0): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) 1234567891011121314 16 15
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-35 preliminary?subject to change without notice the master initiates the transfer by placing its first data bit on the sout_ x pin and asserting the appropriate peripheral chip select signals to the slav e device. the slave responds by placing its first data bit on its sout_ x pin. after the t csc delay has elapsed, the master outputs the first edge of sck_ x . this is the edge used by the mast er and slave devices to samp le the first input data bit on their se rial data input signals. at the second edge of the sck_ x the master and slave devices place their second data bit on their serial data output signals. for th e rest of the frame the master and the slave sample their sin_ x pins on the odd-numbered clock edges and cha nges the data on their sout_ x pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the mast er negates the cs signals. a delay of t dt is inserted before a new frame tran sfer can be initiated by the master. for the cpha = 0 condition of the master, tcf and eoqf are set and the rxctr counter is updated at the next to last serial clock edge of the frame (edge 15) of figure 10-14 . for the cpha = 0 condition of the sl ave, tcf is set and the rxctr count er is updated at the last serial clock edge of the frame (edge 16) of figure 10-14 . 10.9.5.2 classic spi transfer format (cpha = 1) this transfer format shown in figure 10-15 is used to communicate with pe ripheral spi slav e devices that require the first sck_ x edge before the firs t data bit becomes avai lable on the slave sout_ x pin. in this format the master and slave devices change the data on their sout_ x pins on the odd-numbered sck_ x edges and sample the data on their sin_ x pins on the even-numbered sck_ x edges. figure 10-15. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) slave (cpha = 1): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (cpol = 0) pcsx / ss t asc sck (cpol = 1) master and slave sample master sout/ slave sin master sin/ slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master (cpha = 1): tcf and eoqf are set and rxctr counter is updated at last sck edge of frame (edge 16) 16
pxd20 microcontroller reference manual, rev. 1 10-36 freescale semiconductor preliminary?subject to change without notice the master initiates the tr ansfer by asserting the cs x signal to the slave. after the t csc delay has elapsed, the master generates the first sck_ x edge and at the same time pla ces valid data on the master sout_ x pin. the slave responds to the first sck_ x edge by placing its first da ta bit on its slave sout_ x pin. at the second edge of the sck_ x the master and slave sample their sin_ x pins. for the rest of the frame the master and the slave change the data on their sout_ x pins on the odd-numbered clock edges and sample their sin_ x pins on the even-numbered clock edges. afte r the last clock edge occurs a delay of t asc is inserted before the master negates the cs x signal. a delay of t dt is inserted before a new frame transfer can be ini tiated by the master. for cpha = 1 the master eoqf and tcf and slave tcf ar e set at the last serial clock edge (edge 16) of figure 10-15 . for cpha = 1 the master a nd slave rxctr counters are upda ted on the same clock edge. 10.9.5.3 modified spi transfer format (mtfe = 1, cpha = 0) in this modified transfer format bot h the master and the slave sample later in the sck period than in classic spi mode to allow for delays in device pads and boa rd traces. these delays become a more significant fraction of the sck period as the sck pe riod decreases with increasing baud rates. note for the modified transfer format to operate correctly, you must thoroughly analyze the spi link timing budget. the master and the slave place data on the sout_ x pins at the assertion of the cs x signal. after the cs x to sck_ x delay has elapsed the first sck_ x edge is generated. the slave samples the master sout_ x signal on every odd numbered sck_ x edge. the slave also places new data on the slave sout_ x on every odd numbered clock edge. the master places its second data bit on the sout_ x line one system clock after odd numbered sck_ x edge. the point where the master samples the slave sout_ x is selected by writing to the smpl_pt field in the dspi x _mcr. table 10-24 lists the number of system clock cycles between the active edge of sck_ x and the master sample point for different values of the smpl_pt bit field. the master sample point can be delayed by one or two system clock cycles. figure 10-16 shows the modified transfer format for cpha = 0. only the condition where cpol = 0 is illustrated. the delayed master sample points are indicated with a lighter shaded arrow. table 10-24. delayed master sample point smpl_pt number of system clock cycles between odd-numbered edge of sck and sampling of sin 00 0 01 1 10 2 11 invalid value
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-37 preliminary?subject to change without notice figure 10-16. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys / 4) 10.9.5.4 modified spi transfer format (mtfe = 1, cpha = 1) at the start of a transfer the dspi asserts the cs signal to the slave de vice. after the cs to sck delay has elapsed the master and the slave put data on their sout pins at the firs t edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the mast er samples the slave sout signal on the odd numbered sck edges starting with the third sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last sl ave sout bit one half sck cycle after the last edge of sck. no clock edge is visible on the master sck pin during the sampling of the last bit. the sck to cs delay must be greater or e qual to half of the sck period. note for the modified transfer format to operate correctly, analyze the spi link timing budget thoroughly. figure 10-17 shows the modified transfer format for cpha = 1. only the condition where cpol = 0 is described. t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs x t asc sck master sample slave sout master sout system clock system clock slave sample t csc
pxd20 microcontroller reference manual, rev. 1 10-38 freescale semiconductor preliminary?subject to change without notice figure 10-17. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys / 4) 10.9.5.5 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential se rial transfers. the continuous selectio n format provides the flexibility to handle both cases. the conti nuous selection format is enabled for the spi configuration by setting the cont bit in the spi command. when the cont bit = 0, the dspi drives the asserted ch ip select signals to their idle states in between frames. the idle states of the chip select si gnals are selected by the pcsis field in the dspi x _mcr. figure 10-18 shows the timing diagram for two four-b it transfers with cpha = 1 and cont = 0. figure 10-18. example of non-continuous format (cpha = 1, cont = 0) t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs t asc sck master sample master sout slave sout slave sample t csc sck (cpol = 0) csx t asc sck (cpol = 1) master sout t dt t csc t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master sin t csc
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-39 preliminary?subject to change without notice when the cont = 1 and the cs signal for the next transf er is the same as for the current transfer, the cs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt ) is not inserted between the transfers. figure 10-19 shows the timing diagram for two 4-b it transfers with cpha = 1 and cont = 1. figure 10-19. example of continuous transfer (cpha = 1, cont = 1) in figure 10-19 , the period length at the start of th e next transfer is the sum of t asc and t csc ; i.e., it does not include a half-clock peri od. the default settings for these provide a total of f our system clocks. in many situations, t asc and t csc must be increased if a full half-clock period is required. when the cont bit = 1 and the cs sign als for the next transfer are differ ent from the present transfer, the cs signals behave as if the cont bit was not set. switching ctar registers or changing which pcs si gnals are asserted betw een frames while using continuous selection can cause errors in the transfer. the pcs signal s hould be negated before ctar is switched or different pcs signals are selected. it is mandatory to fill the txfifo wi th the number of entries that will be concatenated together under one pcs assertion for both master and slave before the txfifo becomes empty. for example, while transmitting in master mode, it should be ensured th at the last entry in the txfifo, after which txfifo becomes empty, must have the c ont bit in the command frame as deasserted (cont bit = 0). while operating in slave mode, it should be ensured that wh en the last-entry in th e txfifo is completely transmitted (i.e. the corresponding tcf flag is asserted and txfifo is em pty) the slave is de-selected for any further serial communication; ot herwise, an underflow error occurs. 10.9.5.6 clock polarity switching between dspi transfers if it is desired to switch polar ity between non-continuous dspi frames, the edge generated by the change in the idle state of the clock occurs one system clock before the assertio n of the chip select for the next frame. refer to section 10.8.2.3, dspi clock and transfer attributes registers 0?7 (dspix_ctarn) . in figure 10-20 , time ?a? shows the one clock interval. time ?b? is user program mable from a minimum of two system clocks. sck (cpol = 0) cs t asc sck (cpol = 1) master sout t csc t csc t csc = cs to sck delay. t asc = after sck delay. master sin
pxd20 microcontroller reference manual, rev. 1 10-40 freescale semiconductor preliminary?subject to change without notice figure 10-20. polarity switching between frames 10.9.6 continuous serial communications clock the dspi provides the option of ge nerating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setti ng the cont_scke bit in the dspi x _mcr. continuous sck is valid in all configurations. continuous sck is only supported fo r cpha = 1. setting cpha = 0 is i gnored if the cont_scke bit is set. continuous sck is supported for modified transfer format. clock and transfer attributes fo r the continuous sck mode are set according to the following rules: ? when the dspi is in spi confi guration, ctar0 is used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame is used. ? in all configurations, the currentl y selected ctar remains in use until the start of a frame with a different ctar specified, or the c ontinuous sck mode is terminated. the device is designed to use the same baud rate for all transfers ma de while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into module disable mode. enabling continuous sck disables the cs to sck delay and th e after sck delay. the delay after transfer is fixed at one sck cycle. figure 10-21 shows timing diagram for continuous sck format with continuous selection disabled. cs system clock sck frame 1 frame 0 cpol = 0 cpol = 1 ab
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-41 preliminary?subject to change without notice figure 10-21. continuous sck timing diagram (cont= 0) if the cont bit in the tx fifo entry is set, cs rema ins asserted between the tr ansfers when the cs signal for the next transfer is the same as for the curren t transfer. under certain co nditions, sck can continue with pcs asserted, but with no data being shifted out of sout (sou t pulled high). this can cause the slave to receive incorrect da ta. those conditions include: ? continuous sck with cont bit set, but no data in the transmit fifo. ? continuous sck with cont bit set a nd entering stopped state (refer to section 10.9.2, start and stop of dspi transfers ). ? continuous sck with cont bit set and en tering stop mode or module disable mode. figure 10-22 shows timing diagram for continuous sck fo rmat with continuous selection enabled. figure 10-22. continuous s ck timing diagram (cont=1) 10.9.7 interrupts/dma requests the dspi has five conditions that can generate interrupt requests only, and two conditions that can generate interrupt. table 10-25 lists the six conditions. sck (cpol = 0) cs sck (cpol = 1) master sout t dt t dt = 1 sck. master sin sck (cpol = 0) sck (cpol = 1) master sout master sin transfer 1 transfer 2
pxd20 microcontroller reference manual, rev. 1 10-42 freescale semiconductor preliminary?subject to change without notice each condition has a flag bit and a request enab le bit. the flag bits are described in the section 10.8.2.4, dspi status register (dspix_sr) and the request enable bi ts are described in the section 10.8.2.5, dspi dma / interrupt request select and enable register (dspix_rser) . the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) gene rate interrupt requests or dma requests depending on the tfff_dirs and rfdf_dirs bits in the dspi x _rser. refer to chapter 10, deserial serial peripheral interface (dspi) and chapter 17, edma channel mux (dmachmux) , for more information on interrupt and dma channel assignments. 10.9.7.1 end of queue interrupt request (eoqf) the end of queue equest indi cates that the end of a tr ansmit queue is reached. th e end of queue request is generated when the eoq bit in the executing spi co mmand is asserted and the eoqf_re bit in the dspi x _rser is set. refer to the eoq bit description in section 10.8.2.4, dspi status register (dspix_sr) . refer to figure 10-14 and figure 10-15 that illustrate when eoqf is set. 10.9.7.2 transmit fifo fill in terrupt or dma request (tfff) the transmit fifo fill request indicates that the tx fifo is not full. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the dspi x _rser is set. the tfff_ dirs bit in the dspi x _rser selects whether a dma request or an interrupt request is generated. 10.9.7.3 transfer complete interrupt request (tcf) the transfer complete request indicates the end of the transfer of a serial frame. the transfer complete request is generated at the end of each frame tr ansfer when the tcf_re bit is set in the dspi x _rser. refer to the tcf bit description in section 10.8.2.4, dspi status register (dspix_sr) . refer to figure 10-14 and figure 10-15 that illustrate when tcf is set. table 10-25. interrupt and dma request conditions condition flag interrupt dma end of transfer queue has been reached (eoq) eoqf x tx fifo is not full tfff x x current frame transfer is complete tcf x tx fifo underflow has occurred tfuf x rx fifo is not empty rfdf x x rx fifo overflow occurred rfof x a fifo overrun occurred 1 1 the fifo overrun condition is created by oring the tfuf and rfof flags together. tfuf ored with rfof x
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-43 preliminary?subject to change without notice 10.9.7.4 transmit fifo underf low interrupt request (tfuf) the transmit fifo unde rflow request indicates that an underflow condition in th e tx fifo has occurred. the transmit underflow condition is detected only fo r dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in slave mode and spi configuration is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfuf_re bit in the dspi x _rser is set, an interrupt request is generated. 10.9.7.5 receive fifo drain in terrupt or dma request (rfdf) the receive fifo drain reque st indicates that the rx fifo is not empty. the r eceive fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdf_re bit in the dspi x _rser is set. the rfdf_dirs bit in the dspi x _rser selects whether a dma request or an interrupt request is generated. 10.9.7.6 receive fifo overfl ow interrupt request (rfof) the receive fifo overflow request in dicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow request is generated when rx fi fo and shift register are full and a transfer is initiated. the rfof_re bit in the dspi x _rser must be set for the inte rrupt request to be generated. depending on the state of the rooe bit in the dspi x _mcr, the data from the tr ansfer that generated the overflow is either ignored or shifted in to the shift re gister. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. 10.9.7.7 fifo overrun request (tfuf) or (rfof) the fifo overrun request indicates th at at least one of th e fifos in the dspi has exceeded its capacity. the fifo overrun request is genera ted by logically or?ing together th e rx fifo overflow and tx fifo underflow signals. 10.9.8 power saving features the dspi supports three power-saving strategies: ? external stop mode ? module disable mode?clock gating of non-memory mapped logic ? clock gating of slave interface signals and clock to memory-mapped logic 10.9.8.1 external stop mode the dspi supports the stop mode protocol. when a reque st is made to enter exte rnal stop mode, the dspi block acknowledges the request by negating ipg_stop_ack. when the dspi is ready to have its clocks shut off the ipg_stop_ack signal is asserted. if a serial transfer is in progress, the dspi wa its until it reaches the frame boundary before it asserts ipg_stop_ack. while th e clocks are shut off, the dspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals ca nnot be changed while in external stop mode. implementation of ipi gr een line stop mode in an soc is optional.
pxd20 microcontroller reference manual, rev. 1 10-44 freescale semiconductor preliminary?subject to change without notice 10.9.8.2 module disable mode module disable mode is a module-specific mode that the dspi can enter to save power. host software can initiate the module disable mode by writ ing a 1 to the mdis bit in the dspi x _mcr. in module disable mode, the dspi is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different affect when the dspi is in the module disa ble mode. reading the rx fifo pop register does not change the state of the rx fifo. likewise, writi ng to the tx fifo push register does not change the state of the tx fifo. cl earing either of the fifos does not have any effect in the module disable mode. changes to the dis_txf a nd dis_rxf fields of the dspi x _mcr does not have any affect in the module disable mode. in the mo dule disable mode, all status bits and register flags in the dspi return the correct values when read, but writing to them has no affect. writing to the dspi x _tcr during module disable mode does not have an effect. interrupt and dma request signals cannot be cleared while in the module disable mode. 10.9.8.3 slave interface signal gating the dspi module enable signal is used to gate sl ave interface signals such as address, byte enable, read/write and data. this prevents toggling slave interface signals fr om consuming power unless the dspi is accessed. 10.10 initialization and application information 10.10.1 how to change queues dspi queues are not part of the dspi module, but the dspi includes features in support of queue management. queues are primarily s upported in spi configuration. this section presents an example of how to change queues for the dspi. 1. the last command word from a queue is execute d. the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the tran sfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the dspi x _sr is set. 3. the setting of the eoqf flag disables both serial transmission, and serial reception of data, putting the dspi in the stopped state. the txrxs bi t is negated to indicate the stopped state. 4. the edma continues to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clea ring the corresponding dma en able request bits in the edma controller. 6. ensure all received data in rx fifo has been transferred to me mory receive queue by reading the rxcnt in dspi x _sr or by checking rfdf in the dspi x _sr after each read operation of the dspi x _popr. 7. modify dma descriptor of tx a nd rx channels for ?new? queues. 8. flush tx fifo by writing a 1 to the clr_txf bit in the dspi x _mcr register and flush the rx fifo by writing a 1 to the clr_rxf bit in the dspi x _mcr register.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-45 preliminary?subject to change without notice 9. clear transfer count eith er by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the dspi x _tcr. 10. enable dma channel by enabling the dma enable request for th e dma channel assigned to the dspi tx fifo, and rx fifo by setting th e corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit. 10.10.2 baud rate settings table 10-26 shows the baud rate that is ge nerated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi x _ctars. the values are calculated at a 64 mhz system frequency with dbr = 0. table 10-26. baud rate values baud rate divider prescaler values (dspi_ctar[pbr]) 2357 baud rate scaler values (dspi_ctar[br]) 2 16.0 mhz 10.7 mhz 6.4 mhz 4.57 mhz 4 8 mhz 5.33 mhz 3.2 mhz 2.28 mhz 6 5.33 mhz 3.56 mhz 2.13 mhz 1.52 mhz 8 4 mhz 2.67 mhz 1.60 mhz 1.15 mhz 16 2 mhz 1.33 mhz 800 khz 571 khz 32 1 mhz 670 khz 400 khz 285 khz 64 500 khz 333 khz 200 khz 142 khz 128 250 khz 166 khz 100 khz 71.7 khz 256 125 khz 83.2 khz 50 khz 35.71 khz 512 62.5 khz 41.6 khz 25 khz 17.86 khz 1024 31.2 khz 20.8 khz 12.5 khz 8.96 khz 2048 15.6 khz 10.4 khz 6.25 khz 4.47 khz 4096 7.81 khz 5.21 khz 3.12 khz 2.23 khz 8192 3.90 khz 2.60 khz 1.56 khz 1.11 khz 16384 1.95 khz 1.31 khz 781 hz 558 hz 32768 979 hz 653 hz 390 hz 279 hz
pxd20 microcontroller reference manual, rev. 1 10-46 freescale semiconductor preliminary?subject to change without notice 10.10.3 delay settings table 10-27 shows the values for the delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in the dspi x _ctars. the values calculated assume a 100 mhz system frequency. 10.10.4 calculation of fifo pointer addresses the user has complete visibility of the tx and rx fifo contents th rough the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is me mory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtpt r). for the rx fifo the first-in pointer is the pop next pointer (popnxtptr). table 10-27. delay values delay prescaler values (dspi_ctar[pbr]) 1357 delay scaler values (dspi_ctar[dt]) 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 ? s 32 320.0 ns 960.0 ns 1.6 ? s2.2 ? s 64 640.0 ns 1.9 ? s3.2 ? s4.5 ? s 128 1.3 ? s3.8 ? s6.4 ? s9.0 ? s 256 2.6 ? s7.7 ? s 12.8 ? s 17.9 ? s 512 5.1 ? s 15.4 ? s 25.6 ? s 35.8 ? s 1024 10.2 ? s 30.7 ? s 51.2 ? s 71.7 ? s 2048 20.5 ? s 61.4 ? s 102.4 ? s 143.4 ? s 4096 41.0 ? s 122.9 ? s 204.8 ? s 286.7 ? s 8192 81.9 ? s 245.8 ? s 409.6 ? s 573.4 ? s 16384 163.8 ? s 491.5 ? s 819.2 ? s 1.1 ms 32768 327.7 ? s 983.0 ? s 1.6 ms 2.3 ms 65536 655.4 ? s 2.0 ms 3.3 ms 4.6 ms
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 10-47 preliminary?subject to change without notice refer to section 10.9.3.4, transmit firs t in first out (tx fifo) buffering mechanism , and section 10.9.3.5, receive first in first out (rx fifo) buffering mechanism , for details on the fifo operation. the tx fifo is chosen for the illustra tion, but the concepts carry over to the rx fifo. figure 10-23 illustrates the concept of first-in and last -in fifo entries along with the fifo counter. figure 10-23. tx fifo pointers and counter 10.10.4.1 address calculation for the firs t-in entry and last-i n entry in the tx fifo the memory address of the first-in entry in th e tx fifo is computed by the following equation: first-in entry address = tx fifo base + 4 (txnxtptr) the memory address of the last-in entry in the tx fifo is computed by the following equation: last-in entry address = txfifo base + 4 x [(txctr + txnxtptr - 1) modulo txfifo depth] where: txfifo base = base a ddress of transmit fifo txctr = transmit fifo counter txnxtptr = transmit next pointer tx fifo depth = transmit fifo depth, implementation specific 10.10.4.2 address calculation for the firs t-in entry and last-i n entry in the rx fifo the memory address of the first-in entry in th e rx fifo is computed by the following equation: first-in entry address = rxfifo base + 4 x (popnxtptr) the memory address of the last-in entry in th e rx fifo is computed by the following equation: last-in entry address = rxfifo base + 4 x [(rxctr + popnxtptr - 1) modulo rxfifo depth] where: entry c entry a (first in) ?? entry b entry d (last in) tx fifo base push tx fifo tx fifo counter shift register sout register transmit next data pointer ? ? ? ? + 1 (txnxtptr)
pxd20 microcontroller reference manual, rev. 1 10-48 freescale semiconductor preliminary?subject to change without notice rxfifo base = base a ddress of receive fifo rxctr = receive fifo counter popnxtptr = pop next pointer rx fifo depth = receive fifo depth, implementation specific
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-1 preliminary?subject to change without notice chapter 11 display control unit (dcu3) 11.1 introduction the display control unit (dcu3) is a system master that fetches graphics stored in internal or external memory and displays them on a tft lcd panel. a wi de range of panel sizes is supported and the timing of the interface signals is highly configurable. graphics are read directly from memory and then blended in real-time, which allows for dyn amic content creation with minimal cpu intervention. graphics may be encoded in a variety of formats to optimise memory usage. the dcu3 al so has the capability of displaying real-time video from an external video source.
pxd20 microcontroller reference manual, rev. 1 11-2 freescale semiconductor preliminary?subject to change without notice 11.1.1 overview figure 11-1. dcu3 block diagram figure 11-1 shows the dcu3 architecture. this comprises two distinct sections. the lower section shows the functional blocks of the dcu3 that fetch the graphic and video content and dr ive the tft lcd panel. the upper section describes the user interface through which th e user configures the graphical content of the tft lcd panel. registers interface (control layer0 layer1 layer2 pixel format converter blending gamma correction out fifo display driver parallel data interface gamma dcu_clk pdi_pclk pdi[17:0] ahb master i/f external video tft display pdi_hsync pdi_vsync timing and control unit pix_clk_in pdi_clk mux pclk, hsync, vsync timing signals to other modules mode ram cursor . . . layer14 layer15 bgcolor (1 kb) (256 x 8 x3) signature calculator crc_ready interrupt crc value ch1 ch2 ch3 ch4 clut/ tile ram in fifo (8 kb) crc pos descriptors for each layer) slave bus i/f in fifo in fifo in fifo ram source
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-3 preliminary?subject to change without notice the sections are analogous to the st ructure of communications modules, such as the flexcan, where one part of the module is configured to connect with the communications bus th rough bit-timin g, parity, baud rate, etc., while a different part is used to store the data content and message identifiers. the configuration of the lower sec tion is dependent on the specific tf t lcd panel and opt ional real-time video hardware that are attached to the dcu3 inputs and outputs. in most cases, this is configured once for the hardware in use before the dcu3 is en abled. when active, this section automatically: ? calculates the relevant gra phical content for each pixel ? fetches the source graphics from memory using its internal dma channels (labelled ch1 to ch4) ? converts the graphic value of each fetched pixe l into full quality color format (if required) ? calculates the required pixel value by blending the values of up to four separate graphics ? performs a gamma correction on the pixel value (if required) ? sends the pixel value to the tft lcd display over its data bus ? sets flags to indicate end of frame, buf fer threshold, and other status changes the upper section describes the characteristics of the graphics to be displayed on the panel and how they are blended together. the dcu3 mana ges the graphical content of the pa nel through sets of registers called layers. there are 16 layers available in the dc u3 and each contains the following information: ? horizontal and vertic al size of graphic ? position of graphic on the panel ? address of graphic in memory ? color encoding format and color palettes (if required) ? type and depth of blending ? range of colors identified for chroma blending ? tile size the values in these registers may be changed at any time, and the pane l content will be updated when the next full frame is ready to be displa yed. the layers are set to a fixed priority, and this is used by the lower section to define which layers are bl ended, in which order, on the panel. the upper section also cont ains configuration register s for a cursor graphic, th e default background color, interrupt enables, test graphic, and simple register pr otection settings. 11.1.2 features the dcu3 has these features: ? full rgb888 output to tft lcd panel ? optional support for panels without built in tcon features using th e on-chip tcon module ? 16 graphics layers, a default background color laye r and a cursor layer with integrated blinking option ? blending of each pixel using up to 4 sour ce layers dependent on size of panel ? programmable panel size up to a maximum of wide vga (800 x 480) ? gamma correction with 8-bit resolution on each color component
pxd20 microcontroller reference manual, rev. 1 11-4 freescale semiconductor preliminary?subject to change without notice ? safety mode for tagging pixels on highest priority layers ? digital video input with and without sync extraction per itu- r bt.656 supporting multiple video input formats including rgb666, rgb565, monochrome and ycbcr422 ? dedicated memory blocks to store a cu rsor and color look up tables (cluts) ? temporal dithering. each graphic layer has th e following attributes: ? can be placed with one pixe l resolution in either axis ? can also be placed in negative x and y directions ? supports multiple color-encoding formats including: ? 1, 2, 4 and 8 bits per pixel inde xed colors with alpha channel ? apal8 indexed colors with alpha channel ? rgb565 and rgb888 direct colors ? argb1555, argb4444, and bgra8888 direct colors with an alpha channel ? ycbcr422 format ? alpha blending with 8-bit resolution ? chroma-key blending fo r anti-mask encoding ? multiple alpha and chroma-key blending modes ? transparency modes for anti -aliased text and graphics ? luminance mode for highlighting content ? tile mode for efficient creati on of textured background content ? support for run length enc oding (rle) compression ? optimized mode for use with ddr memory 11.1.3 modes of operation the dcu3 has four modes of operation: ? dcu_off : when in this mode, the dcu3 is turned off. all the logic in the design is put in reset state to reduce power. ? normal_mode : the dcu3 displays and blends th e graphics specified by the layer descriptors. ? pdi_mode : a mode which fetches video from an external video source and combines that with the graphics configured on the layers. ? colbar_mode : color bar generation for testing purposes.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-5 preliminary?subject to change without notice 11.2 external signal description 11.2.1 overview the dcu3 has up to 22 input signals and up to 30 output signals. see figure 11-2 . the choice of signals used depends on the configuration of the dcu3. all active signals mu st be enabled by configuring the appropriate pcr registers in the siul module. if required, the dcu3 output signals can be configured to drive a pane l which does not have an embedded timing controller by enabling the on-chip tcon module. figure 11-2. external signals 11.2.2 detailed signal descriptions table 11-1. detailed signal descriptions signal direction description parallel data interface (camera interface) pdi_pclk in clock for the parallel data from the input video data pdi_vsync in vertical sync to indicate t he start of new frame for the display pdi_hsync in horizontal sync to indicate the start of new line for the display pdi_de in data enable for the camera data input pdi[17:0] in 18-bit parallel input data for the display display interface dcu_pclk out pixel clock used to drive the display panel dcu_vsync out vertical sync signal, indicating the beginning of a new frame dcu_hsync out horizontal sync signal, indicating the beginning of a new line dcu_tag out when high, this signal indicates t hat the pixel is tagged and an application can calculate crc externally on this pixel. dcu3 top level parallel data interface display interface pdi_pclk dcu_pclk dcu_vsync dcu_hsync dcu_csync (not used) dcu_de dcu_r[7:0], dcu_g[7:0], dcu_b[7:0] pdi[17:0] pdi_vsync pdi_hsync pdi_de dcu_tag
pxd20 microcontroller reference manual, rev. 1 11-6 freescale semiconductor preliminary?subject to change without notice 11.3 memory map and register definition 11.3.1 memory map table 11-2 shows the memory map of the dcu3. 11.3.2 register map table 11-3 provides the register map of the dcu3. only 32-bit writes and 32-bit alig ned access are supported. by te and half-word acce sses are not supported. dcu_de out data enable. qualifies the data output dcu_r[7:0], dcu_g[7:0], dcu_b[7:0] out red, green and blue data output. table 11-2. dcu3 memory map parameter address range register address space 0x0000 ? 0x03ff cursor address space 0x0400 ? 0x07ff gamma_r address space 0x0800 ? 0x0bff gamma_g address space 0x0c00 ? 0x0fff gamma_b address space 0x1000 ? 0x13ff empty space 0x1400 ? 0x1fff clut/tile address space 0x2000 ? 0x3fff table 11-3. dcu3 register map address offset register access reset value location 0x000 ctrldescl0_1 register r/w 0x00000000 on page 11-24 0x004 ctrldescl0_2 register r/w 0x00000000 on page 11-24 0x008 ctrldescl0_3 register r/w 0x00000000 on page 11-25 0x00c ctrldescl0_4 register r/w 0x00000000 on page 11-26 0x010 ctrldescl0_5 register r/w/ 0x00000000 on page 11-28 0x014 ctrldescl0_6 register r/w/ 0x00000000 on page 11-29 0x018 ctrldescl0_7 register r/w/ 0x00000000 on page 11-31 0x01c ctrldescl1_1 register r/w 0x00000000 on page 11-24 0x020 ctrldescl1_2 register r/w 0x00000000 on page 11-24 table 11-1. detailed signal descriptions (continued) signal direction description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-7 preliminary?subject to change without notice 0x024 ctrldescl1_3 register r/w 0x00000000 on page 11-25 0x028 ctrldescl1_4 register r/w 0x00000000 on page 11-26 0x02c ctrldescl1_5 register r/w 0x00000000 on page 11-28 0x030 ctrldescl1_6 register r/w 0x00000000 on page 11-29 0x034 ctrldescl1_7 register r/w 0x00000000 on page 11-31 0x038 ctrldescl2_1 register r/w 0x00000000 on page 11-24 0x03c ctrldescl2_2 register r/w 0x00000000 on page 11-24 0x040 ctrldescl2_3 register r/w 0x00000000 on page 11-25 0x044 ctrldescl2_4 register r/w 0x00000000 on page 11-26 0x048 ctrldescl2_5 register r/w 0x00000000 on page 11-28 0x04c ctrldescl2_6 register r/w 0x00000000 on page 11-29 0x050 ctrldescl2_7 register r/w 0x00000000 on page 11-31 0x054 ctrldescl3_1 register r/w 0x00000000 on page 11-24 0x058 ctrldescl3_2 register r/w 0x00000000 on page 11-24 0x05c ctrldescl3_3 register r/w 0x00000000 on page 11-25 0x060 ctrldescl3_4 register r/w 0x00000000 on page 11-26 0x064 ctrldescl3_5 register r/w 0x00000000 on page 11-28 0x068 ctrldescl3_6 register r/w 0x00000000 on page 11-29 0x06c ctrldescl3_7 register r/w 0x00000000 on page 11-31 0x070 ctrldescl4_1 register r/w 0x00000000 on page 11-24 0x074 ctrldescl4_2 register r/w 0x00000000 on page 11-24 0x078 ctrldescl4_3 register r/w 0x00000000 on page 11-25 0x07c ctrldescl4_4 register r/w 0x00000000 on page 11-26 0x080 ctrldescl4_5 register r/w 0x00000000 on page 11-28 0x084 ctrldescl4_6 register r/w 0x00000000 on page 11-29 0x088 ctrldescl4_7 register r/w 0x00000000 on page 11-31 0x08c ctrldescl5_1 register r/w 0x00000000 on page 11-24 0x090 ctrldescl5_2 register r/w 0x00000000 on page 11-24 0x094 ctrldescl5_3 register r/w 0x00000000 on page 11-25 0x098 ctrldescl5_4 register r/w 0x00000000 on page 11-26 0x09c ctrldescl5_5 register r/w 0x00000000 on page 11-28 0x0a0 ctrldescl5_6 register r/w 0x00000000 on page 11-29 0x0a4 ctrldescl5_7 register r/w 0x00000000 on page 11-31 table 11-3. dcu3 regist er map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 11-8 freescale semiconductor preliminary?subject to change without notice 0x0a8 ctrldescl6_1 register r/w 0x00000000 on page 11-24 0x0ac ctrldescl6_2 register r/w 0x00000000 on page 11-24 0x0b0 ctrldescl6_3 register r/w 0x00000000 on page 11-25 0x0b4 ctrldescl6_4 register r/w 0x00000000 on page 11-26 0x0b8 ctrldescl6_5 register r/w 0x00000000 on page 11-28 0x0bc ctrldescl6_6 register r/w 0x00000000 on page 11-29 0x0c0 ctrldescl6_7 register r/w 0x00000000 on page 11-31 0x0c4 ctrldescl7_1 register r/w 0x00000000 on page 11-24 0x0c8 ctrldescl7_2 register r/w 0x00000000 on page 11-24 0x0cc ctrldescl7_3 register r/w 0x00000000 on page 11-25 0x0d0 ctrldescl7_4 register r/w 0x00000000 on page 11-26 0x0d4 ctrldescl7_5 register r/w 0x00000000 on page 11-28 0x0d8 ctrldescl7_6 register r/w 0x00000000 on page 11-29 0x0dc ctrldescl7_7 register r/w 0x00000000 on page 11-31 0x0e0 ctrldescl8_1 register r/w 0x00000000 on page 11-24 0x0e4 ctrldescl8_2 register r/w 0x00000000 on page 11-24 0x0e8 ctrldescl8_3 register r/w 0x00000000 on page 11-25 0x0ec ctrldescl8_4 register r/w 0x00000000 on page 11-26 0x0f0 ctrldescl8_5 register r/w 0x00000000 on page 11-28 0x0f4 ctrldescl8_6 register r/w 0x00000000 on page 11-29 0x0f8 ctrldescl8_7 register r/w 0x00000000 on page 11-31 0x0fc ctrldescl9_1 register r/w 0x00000000 on page 11-24 0x100 ctrldescl9_2 register r/w 0x00000000 on page 11-24 0x104 ctrldescl9_3 register r/w 0x00000000 on page 11-25 0x108 ctrldescl9_4 register r/w 0x00000000 on page 11-26 0x10c ctrldescl9_5 register r/w 0x00000000 on page 11-28 0x110 ctrldescl9_6 register r/w 0x00000000 on page 11-29 0x114 ctrldescl9_7 register r/w 0x00000000 on page 11-31 0x118 ctrldescl10_1 register r/w 0x00000000 on page 11-24 0x11c ctrldescl10_2 register r/w 0x00000000 on page 11-24 0x120 ctrldescl10_3 register r/w 0x00000000 on page 11-25 0x124 ctrldescl10_4 register r/w 0x00000000 on page 11-26 0x128 ctrldescl10_5 register r/w 0x00000000 on page 11-28 table 11-3. dcu3 regist er map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-9 preliminary?subject to change without notice 0x12c ctrldescl10_6 register r/w 0x00000000 on page 11-29 0x130 ctrldescl10_7 register r/w 0x00000000 on page 11-31 0x134 ctrldescl11_1 register r/w 0x00000000 on page 11-24 0x138 ctrldescl11_2 register r/w 0x00000000 on page 11-24 0x13c ctrldescl11_3 register r/w 0x00000000 on page 11-25 0x140 ctrldescl11_4 register r/w 0x00000000 on page 11-26 0x144 ctrldescl11_5 register r/w 0x00000000 on page 11-28 0x148 ctrldescl11_6 register r/w 0x00000000 on page 11-29 0x14c ctrldescl11_7 register r/w 0x00000000 on page 11-31 0x150 ctrldescl12_1 register r/w 0x00000000 on page 11-24 0x154 ctrldescl12_2 register r/w 0x00000000 on page 11-24 0x158 ctrldescl12_3 register r/w 0x00000000 on page 11-25 0x15c ctrldescl12_4 register r/w 0x00000000 on page 11-26 0x160 ctrldescl12_5 register r/w 0x00000000 on page 11-28 0x164 ctrldescl12_6 register r/w 0x00000000 on page 11-29 0x168 ctrldescl12_7 register r/w 0x00000000 on page 11-31 0x16c ctrldescl13_1 register r/w 0x00000000 on page 11-24 0x170 ctrldescl13_2 register r/w 0x00000000 on page 11-24 0x174 ctrldescl13_3 register r/w 0x00000000 on page 11-25 0x178 ctrldescl13_4 register r/w 0x00000000 on page 11-26 0x17c ctrldescl13_5 register r/w 0x00000000 on page 11-28 0x180 ctrldescl13_6 register r/w 0x00000000 on page 11-29 0x184 ctrldescl13_7 register r/w 0x00000000 on page 11-31 0x188 ctrldescl14_1 register r/w 0x00000000 on page 11-24 0x18c ctrldescl14_2 register r/w 0x00000000 on page 11-24 0x190 ctrldescl14_3 register r/w 0x00000000 on page 11-25 0x194 ctrldescl14_4 register r/w 0x00000000 on page 11-26 0x198 ctrldescl14_5 register r/w 0x00000000 on page 11-28 0x19c ctrldescl14_6 register r/w 0x00000000 on page 11-29 0x1a0 ctrldescl14_7 register r/w 0x00000000 on page 11-31 0x1a4 ctrldescl15_1 register r/w 0x00000000 on page 11-24 0x1a8 ctrldescl15_2 register r/w 0x00000000 on page 11-24 0x1ac ctrldescl15_3 register r/w 0x00000000 on page 11-25 table 11-3. dcu3 regist er map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 11-10 freescale semiconductor preliminary?subject to change without notice 0x1b0 ctrldescl15_4 register r/w 0x00000000 on page 11-26 0x1b4 ctrldescl15_5 register r/w 0x00000000 on page 11-28 0x1b8 ctrldescl15_6 register r/w 0x00000000 on page 11-29 0x1bc ctrldescl15_7 register r/w 0x00000000 on page 11-31 0x1c0 ctrldesccursor_1 register r/w 0x00000000 on page 11-31 0x1c4 ctrldesccursor_2 register r/w 0x00000000 on page 11-32 0x1c8 ctrldesccursor_3 register r/w 0x00000000 on page 11-33 0x1cc ctrldesccursor_4 register r/w 0x00000000 on page 11-33 0x1d0 dcu_mode register r/w 0x00000000 on page 11-34 0x1d4 bgnd register r/w 0x00000000 on page 11-36 0x1d8 disp_size register r/w 0x00000000 on page 11-37 0x1dc hsyn_para register r/w 0x00c01803 on page 11-37 0x1e0 vsyn_para register r/w 0x00c01803 on page 11-38 0x1e4 synpol register r/w 0x00000000 on page 11-39 0x1e8 threshold register r/w 0x0000780a on page 11-40 0x1ec int_status register r 0x00000000 on page 11-41 0x1f0 int_mask regi ster r/w 0x000f4fff on page 11-42 0x1f4 colbar_1 register r/w 0xff000000 on page 11-45 0x1f8 colbar_2 register r/w 0xff0000ff on page 11-45 0x1fc colbar_3 register r/w 0xff00ffff on page 11-46 0x200 colbar_4 register r/w 0xff00ff00 on page 11-46 0x204 colbar_5 regist er r/w 0xffffff00 on page 11-47 0x208 colbar_6 register r/w 0xffff0000 on page 11-47 0x20c colbar_7 register r/w 0xffff00ff on page 11-48 0x210 colbar_8 regist er r/w 0xffffffff on page 11-48 0x214 div_ratio register r/w 0x0000001f on page 11-48 0x218 sign_calc_1 register r/w 0x00000000 on page 11-49 0x21c sign_calc_2 register r/w 0x00000000 on page 11-50 0x220 crc_val register r/w 0x00000000 on page 11-50 0x224 pdi_status register r/w 0x00000000 on page 11-51 0x228 mask_pdi_status register r/w 0x000003ff on page 11-52 0x22c parr_err_status register r/w 0x00000000 on page 11-53 0x230 mask_parr_err_status register r/w 0x000fffff on page 11-56 table 11-3. dcu3 regist er map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-11 preliminary?subject to change without notice 0x234 threshold_inp_buf_1 register r/w 0x7f007f00 on page 11-58 0x238 threshold_inp_buf_2 register r/w 0x7f007f00 on page 11-59 0x23c luma_comp register r/w 0x9512a254 on page 11-59 0x240 chroma_red register r/w 0x03310000 on page 11-60 0x244 chroma_green register r/w 0x06600f38 on page 11-60 0x248 chroma_blue register r/w 0x00000409 on page 11-61 0x24c crc_pos register r/w 0x00000000 on page 11-62 0x250 fg0_fcolor register r/w 0x00000000 on page 11-62 0x254 fg0_bcolor register r/w 0x00000000 on page 11-63 0x258 fg1_fcolor register r/w 0x00000000 on page 11-62 0x25c fg1_bcolor register r/w 0x00000000 on page 11-63 0x260 fg2_fcolor register r/w 0x00000000 on page 11-62 0x264 fg2_bcolor register r/w 0x00000000 on page 11-63 0x268 fg3_fcolor register r/w 0x00000000 on page 11-62 0x26c fg3_bcolor register r/w 0x00000000 on page 11-63 0x270 fg4_fcolor register r/w 0x00000000 on page 11-62 0x274 fg4_bcolor register r/w 0x00000000 on page 11-63 0x278 fg5_fcolor register r/w 0x00000000 on page 11-62 0x27c fg5_bcolor register r/w 0x00000000 on page 11-63 0x280 fg6_fcolor register r/w 0x00000000 on page 11-62 0x284 fg6_bcolor register r/w 0x00000000 on page 11-63 0x288 fg7_fcolor register r/w 0x00000000 on page 11-62 0x28c fg7_bcolor register r/w 0x00000000 on page 11-63 0x290 fg8_fcolor register r/w 0x00000000 on page 11-62 0x294 fg8_bcolor register r/w 0x00000000 on page 11-63 0x298 fg9_fcolor register r/w 0x00000000 on page 11-62 0x29c fg9_bcolor register r/w 0x00000000 on page 11-63 0x2a0 fg10_fcolor register r/w 0x00000000 on page 11-62 0x2a4 fg10_bcolor register r/w 0x00000000 on page 11-63 0x2a8 fg11_fcolor register r/w 0x00000000 on page 11-62 0x2ac fg11_bcolor register r/w 0x00000000 on page 11-63 0x2b0 fg12_fcolor register r/w 0x00000000 on page 11-62 0x2b4 fg12_bcolor register r/w 0x00000000 on page 11-63 table 11-3. dcu3 regist er map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 11-12 freescale semiconductor preliminary?subject to change without notice 11.3.3 register summary figure 11-3 provides a key for register figures and tables and the register summary. the conventions in table 11-4 serve as a key for the register summ ary and individual register diagrams. 0x2b8 fg13_fcolor register r/w 0x00000000 on page 11-62 0x2bc fg13_bcolor register r/w 0x00000000 on page 11-63 0x2c0 fg14_fcolor register r/w 0x00000000 on page 11-62 0x2c4 fg14_bcolor register r/w 0x00000000 on page 11-63 0x2c8 fg15_fcolor register r/w 0x00000000 on page 11-62 0x2cc fg15_bcolor register r/w 0x00000000 on page 11-63 0x2d0 lyr_intpol_en r/w 0x00000000 on page 11-65 0x2d4 lyr_luma_comp register r/w 0x9512a254 on page 11-65 0x2d8 lyr_chroma_red register r/w 0x03310000 on page 11-66 0x2dc lyr_chroma_green register r/w 0x06600f38 on page 11-66 0x2e0 lyr_chroma_blue register r/w 0x00000409 on page 11-67 0x2e4 comp_imsize register r/w 0x00000000 on page 11-68 0x2e8?0x2fc reserved 0x300 global protection register r/w 0x00000000 on page 11-68 0x304 soft lock bit register l0 r/w 0x00000000 on page 11-69 0x308 soft lock bit register l1 r/w 0x00000000 on page 11-71 0x30c soft lock bit register disp_size r/w 0x00000000 on page 11-72 0x310 soft lock bit register vsync/hsync para r/w 0x00000000 on page 11-73 0x314 soft lock bit register pol r/w 0x00000000 on page 11-74 0x318 soft lock bit register l0_transp r/w 0x00000000 on page 11-74 0x31c soft lock bit register l1_transp r/w 0x00000000 on page 11-76 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 11-3. key to register fields table 11-3. dcu3 regist er map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-13 preliminary?subject to change without notice table 11-4. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable fieldname identifies the field. its pres ence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect w write only r/w standard read/write bit. only software can c hange the bit?s value (other than a hardware reset). rwm a read/write bit that can be modified by hardware in some fashion other than by a reset w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the m odule, but it always reads as zero. (previously designated slfclr) s set: pattern on the data bus is ored with and written into the register. c clear: pattern on the data bus is a mask. if a bit on the mask is set, then the corresponding register bit is cleared. reset values 0 resets to zero 1 resets to one ? undefined at reset u unaffected by reset [ signal_name ] reset value is determined by polarity of indicated signal. table 11-5. register descriptions name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ctrldescl0_1 0x000 r000000 height w r000000 width w ctrldescl0_2 0x004 r00000 posy w r00000 posx w
pxd20 microcontroller reference manual, rev. 1 11-14 freescale semiconductor preliminary?subject to change without notice ctrldescl0_3 0x008 r addr w r w ctrldescl0_4 0x00c r en til e_e n dat a_s el saf ety _en trans bpp w r rle_en luoffs 0 bb ab w ctrldescl0_5 0x010 r00000000 ckmax_r w r ckmax_g ckmax_b w ctrldescl0_6 0x014 r00000000 ckmin_r w r ckmin_g ckmin_b w ctrldescl0_7 0x018 r00000 tile_ver_size w r00000000 tile_hor_size w ctrldesccurs or_1 0x1c0 r00000 height w r00000 width w ctrldesccurs or_2 0x1c4 r00000 posy w r00000 posx w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-15 preliminary?subject to change without notice ctrldesccurs or_3 0x1c8 rcu r_e n 0000000 default_cursor_color[0:7] w r default_cursor_color[8:23] w ctrldesccurs or_4 0x1cc r00000000 hwc_blink_off w r0000000 en_blink hwc_blink_on w dcu_mode 0x1d0 r dcu_sw_ reset dither_en addb addg addr 0 blend_iter pdi_sync_lock w r pdi_interpol_en raster_en pdi_en pdi_byte_rev pdi_de_mode pdi_narrow_mode pdi_mode pdi_slave_mode tag_en sig_en pdi_sync 0 en_gamma dcu_mode w bgnd 0x1d4 r00000000 bgnd_r w r bgnd_g bgnd_b w disp_size 0x1d8 r00000 delta_y w r000000000 delta_x w hsyn_para 0x1dc r0 bp_h 00 pw_h[0:3] w r pw_h[4:8] 00 fp_h w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 11-16 freescale semiconductor preliminary?subject to change without notice vsyn_para 0x1e0 r0 bp_v 00 pw_v[0:3] w r pw_v[4:8] 00 fp_v w syn_pol 0x1e4 r0000000000000000 w r00000 inv_pdi_de inv_pdi_hs inv_pdi_vs inv_pdi_clk inv_pxck neg bp_vs bp_hs inv_cs inv_vs inv_hs w threshold 0x1e8 r000000 ls_bf_vs w r out_buf_high out_buf_low w int_status 0x1ec r000000000000 p4_fifo_hi_flag p4_fifo_lo_flag p3_fifo_hi_flag p3_fifo_lo_flag w w1c w1c w1c w1c r0 dma_trans_finish 00 ipm_error prog_end p2_fifo_hi_flag p2_fifo_lo_flag p1_fifo_hi_flag p1_fifo_lo_flag crc_overflow crc_ready vs_blank ls_bf_vs undrun vsync w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-17 preliminary?subject to change without notice int_mask 0x1f0 r000000000000 m_p4_fifo_hi_flag m_p4_fifo_lo_flag m_p3_fifo_hi_flag m_p3_fifo_lo_flag w r0 m_dma_trans_finish 00 m_ipm_error m_prog_end m_p2_fifo_hi_flag m_p2_fifo_lo_flag m_p1_fifo_hi_flag m_p1_fifo_lo_flag m_crc_overflow m_crc_ready m_vs_blank m_ls_bf_vs m_undrun m_vsync w colbar_1 0x1f4 r11111111 colbar_1_r w r colbar_1_g colbar_1_b w colbar_2 0x1f8 r11111111 colbar_2_r w r colbar_2_g colbar_2_b w colbar_3 0x1fc r11111111 colbar_3_r w r colbar_3_g colbar_3_b w colbar_4 0x200 r11111111 colbar_4_r w r colbar_4_g colbar_4_b w colbar_5 0x204 r11111111 colbar_5_r w r colbar_5_g colbar_5_b w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 11-18 freescale semiconductor preliminary?subject to change without notice colbar_6 0x208 r11111111 colbar_6_r w r colbar_6_g colbar_6_b w colbar_7 0x20c r11111111 colbar_7_r w r colbar_7_g colbar_7_b w colbar_8 0x210 r11111111 colbar_8_r w r colbar_8_g colbar_8_b w div_ratio 0x214 r0000000000000000 w r00000000 div_ratio w sign_calc_ 1 0x218 r00000 sig_ver_size w r00000 sig_hor_size w sign_calc_ 2 0x21c r00000 sig_ver_pos w r00000 sig_hor_pos w crc_val 0x220 r crc_val w r w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-19 preliminary?subject to change without notice pdi_status 0x224 r0000000000000000 w r000000 pdi_blanking_err pdi_ecc_err2 pdi_ecc_err1 pdi_lock_lost pdi_lock_det pdi_vsync_det pdi_hsync_det pdi_de_det pdi_clk_lost pdi_clk_det w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c mask_pdi_ status 0x228 r0000000000000000 w r000000 m_pdi_blanking_err m_pdi_ecc_err2 m_pdi_ecc_err1 m_pdi_lock_lost m_pdi_lock_det m_pdi_vsync_det m_pdi_hsync_det m_pdi_de_det m_pdi_clk_lost m_pdi_clk_det w parr_err_ status 0x22c r000000000000 rle_err hwc_err sig_err disp_err w w1c w1c w1c w1c r l15_parr_err l14_parr_err l13_parr_err l12_parr_err l11_parr_err l10_parr_err l9_parr_err l8_parr_err l7_parr_err l6_parr_err l5_parr_err l4_parr_err l3_parr_err l2_parr_err l1_parr_err l0_parr_err w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 11-20 freescale semiconductor preliminary?subject to change without notice mask_parr _err_ status 0x230 r000000000000 m_rle_err m_hwc_err m_sig_err m_disp_err w r m_l15_parr_err m_l14_parr_err m_l13_parr_err m_l12_parr_err m_l11_parr_err m_l10_parr_err m_l9_parr_err m_l8_parr_err m_l7_parr_err m_l6_parr_err m_l5_parr_err m_l4_parr_err m_l3_parr_err m_l2_parr_err m_l1_parr_err m_l0_parr_err w threshold _inp_buf 0x234 r0 inp_buf_p2_hi 0 inp_buf_p2_lo w r0 inp_buf_p1_hi 0 inp_buf_p1_lo w threshold _inp_buf 0x238 r0 inp_buf_p4_hi 0 inp_buf_p4_lo w r0 inp_buf_p3_hi 0 inp_buf_p3_lo w luma_comp 0x23c r y_red y_green[0:4] w r y_green[5:9] y_blue w chroma_re d 0x240 r00000 cr_red w r0000 cb_red w chroma_g reen 0x244 r00000 cr_green w r0000 cb_green w chroma_bl ue 0x248 r00000 cr_blue w r0000 cb_blue w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-21 preliminary?subject to change without notice crc_pos 0x24c r crc_pos w r w fgx_ fcolor 0x250 r11111111 fgx_fcolor[0:7] w r fgx_fcolor[8:23] w fgx_ bcolor 0x254 r11111111 fgx_bcolor[0:7] w r fgx_bcolor[8:23] w lyr_intpol _en 0x2d0 r en 000000000000000 w r0000000000000000 w lyr_luma_ comp 0x2d4 r y_red y_green[0:4] w r y_green[5:9] y_blue w lyr_chrom a_red 0x2d8 r00000 cr_red w r0000 cb_red w lyr_chrom a_green 0x2dc r00000 cr_green w r0000 cb_green w lyr_chrom a_blue 0x2e0 r00000 cr_blue w r0000 cb_blue w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 11-22 freescale semiconductor preliminary?subject to change without notice comp_imsiz e 0x2e4 r0000000000 comp_imsize[10:15] w r comp_imsize[16:31] w global_ protectio n 0x300 r hlb 000000000000000 w r0000000000000000 w soft_lock_bit l0 0x304 r0000 slb_l0_1 slb_l0_2 slb_l0_3 slb_l0_4 0000 slb_l0_5 slb_l0_6 slb_l0_7 0 w wen_lo_1 wen_lo_2 wen_lo_3 wen_lo_4 wen_lo_5 wen_lo_6 wen_lo_7 r0000000000000000 w soft_lock_bit l1 0x308 r0000 slb_l1_1 slb_l1_2 slb_l1_3 slb_l1_4 0000 slb_l1_5 slb_l1_6 slb_l1_7 0 w wen_l1_1 wen_l1_2 wen_l1_3 wen_l1_4 wen_l1_5 wen_l1_6 wen_l1_7 r0000000000000000 w soft_lock_di sp_size 0x30c r0000 slb_disp 00000000000 w wen_disp r0000000000000000 w soft_lock_hs ync/vsync pa r a 0x310 r0000 slb_hsync slb_vsync 0000000000 w wen_hsync wen_vsync r0000000000000000 w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-23 preliminary?subject to change without notice 11.3.4 register descriptions this section describes the dcu3 registers. 11.3.4.1 control descriptor l0 _1 register (ctrldescl0_1) figure 11-4 represents the control descriptor l0_1 register. this register sets the height and width of the layer associated with the register. soft_lock_p ol 0x314 r0000 slb_pol 00000000000 w wen_pol r0000000000000000 w soft_lock l0_transp 0x318 r0000 slb_fcolor slb_bcoloe 0000000000 w wen_fcolor wen_bcolor r0000000000000000 w soft_lock l1_transp 0x31c r0000 slb_fcolor slb_bcoloe 0000000000 w wen_fcolor wen_bcolor r0000000000000000 w table 11-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 11-24 freescale semiconductor preliminary?subject to change without notice figure 11-4. ctrldescl0_1 register 11.3.4.2 control descr iptor l0_2 register figure 11-5 represents the control descriptor l0_2 register. this register sets the origin (top/left) of the layer associated with the register. offsets: 0x000 (ctrldescl0_1) 0x01c (ctrldescl1_1) 0x038 (ctrldescl2_1) 0x054 (ctrldescl3_1) 0x070 (ctrldescl4_1) 0x08c (ctrldescl5_1) 0x098 (ctrldescl6_1) 0x0c4 (ctrldescl7_1) 0x0e0 (ctrldescl8_1) 0x0fc (ctrldescl9_1) 0x118 (ctrldescl10_1) 0x134 (ctrldescl11_1) 0x150 (ctrldescl12_1) 0x16c (ctrldescl13_1) 0x188 (ctrldescl14_1) 0x194 (ctrldescl15_1) access: user read/write 0123456789101112131415 r00000 height w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 width w reset0000000000000000 table 11-6. ctrldescl0_1 field descriptions field description 6?15 height height of the layer in pixels 20?31 width width of the layer (in pixels). the layer width must be in multiples of the number of pixels that can be stored in 32 bits except for the special case of 1 bit per pixel, and therefore differs depending on color encoding. for example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. see section 11.4.4.3, layer size and positioning .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-25 preliminary?subject to change without notice figure 11-5. ctrldescl0_2 register 11.3.4.3 control descr iptor l0_3 register figure 11-6 represents the control descriptor l0_3 register . this register sets th e beginning address of layer data. offsets: 0x004 (ctrldescl0_2) 0x020 (ctrldescl1_2) 0x03c (ctrldescl2_2) 0x058 (ctrldescl3_2) 0x074 (ctrldescl4_2) 0x090 (ctrldescl5_2) 0x0ac (ctrldescl6_2) 0x0c8 (ctrldescl7_2) 0x0e4 (ctrldescl8_2) 0x100 (ctrldescl9_2) 0x11c (ctrldescl10_2) 0x138 (ctrldescl11_2) 0x154 (ctrldescl12_2) 0x170 (ctrldescl13_2) 0x18c (ctrldescl14_2) 0x198 (ctrldescl15_2) access: user read/write 0123456789101112131415 r0000 posy w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 posx w reset0000000000000000 table 11-7. ctrldescl0_2 field descriptions field description posy two?s complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. positive values are below and negative values are above the top row of the panel. posx two?s complement signed value setting the horizon tal position of left hand column of the layer, where 0 is the left-hand column of the panel. positi ve values are to the right and negative values are to the left the left-hand column of the panel.
pxd20 microcontroller reference manual, rev. 1 11-26 freescale semiconductor preliminary?subject to change without notice figure 11-6. ctrldescl0_3 register 11.3.4.4 control descr iptor l0_4 register figure 11-7 represents the control descriptor l0_4 register. this register c ontrols various gr aphics options and whether the layer is enabled. offsets: 0x008 (ctrldescl0_3) 0x024 (ctrldescl1_3) 0x040 (ctrldescl2_3) 0x05c (ctrldescl3_3) 0x078 (ctrldescl4_3) 0x094 (ctrldescl5_3) 0x0b0 (ctrldescl6_3) 0x0cc (ctrldescl7_3) 0x0e8 (ctrldescl8_3) 0x104 (ctrldescl9_3) 0x120 (ctrldescl10_3) 0x13c (ctrldescl11_3) 0x158 (ctrldescl12_3) 0x174 (ctrldescl13_3) 0x18c (ctrldescl14_3) 0x1ac (ctrldescl15_3) access: user read/write 0123456789101112131415 r addr[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr16:31] w reset0000000000000000 table 11-8. ctrldescl0_3 field descriptions field description addr address of layer data in the memory. the address programmed should be 64-bit aligned.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-27 preliminary?subject to change without notice figure 11-7. ctrldescl0_4 register offsets: 0x00c (ctrldescl0_4) 0x028 (ctrldescl1_4) 0x044 (ctrldescl2_4) 0x060 (ctrldescl3_4) 0x07c (ctrldescl4_4) 0x098 (ctrldescl5_4) 0x0b4 (ctrldescl6_4) 0x0d0 (ctrldescl7_4) 0x0ec (ctrldescl8_4) 0x108 (ctrldescl9_4) 0x124 (ctrldescl10_4) 0x140 (ctrldescl11_4) 0x15c (ctrldescl12_4) 0x178 (ctrldescl13_4) 0x190 (ctrldescl14_4) 0x1b0 (ctrldescl15_4) access: user read/write 0123456789101112131415 r en tile _en dat a_s el saf ety _en trans bpp w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rle_en luoffs 0 bb ab w reset0000000000000000 table 11-9. ctrldescl0_4 field descriptions field description 0 en enable the layer 1?b1: on 1?b0: off 1 tile_en enable the tile mode 1?b1: on 1?b0: off 2 data_sel selects the tile data either from mcu memory or clut 1?b0: tile mode data resides in the mcu memory 1?b1: tile mode data resides in the clut 3 safety_en safety mode enable bit. valid only for layer 0 a nd layer 1. for registers of all other layers, this should be set to 0. 1?b1: safety mode is enabled for this layer 1?b0: safety mode is disabled 4?11 trans transparency level. specifies the alpha value for the layer. this value may be used by the blending engine to blend pixels on this layer. value can vary between 0-255 where 0 is completely transparent and 255 is completely opaque.
pxd20 microcontroller reference manual, rev. 1 11-28 freescale semiconductor preliminary?subject to change without notice 11.3.4.5 control descr iptor l0_5 register figure 11-8 represents the control descriptor l0_5 regist er. this register sets the maximum chroma keying values for rgb. refer to section 11.4.4.5, alpha and chroma-key blending, for a description of chroma keying. 12?15 bpp bits per pixel 4?b0000 = 1 bpp 4?b0001 = 2 bpp 4?b0010 = 4 bpp 4?b0011 = 8 bpp 4?b0100 = 16 bpp (rgb565) 4?b0101 = 24 bpp 4?b0110 = 32 bpp (bgra8888) 4?b0111 = transparency mode 4 bpp 4?b1000 = transparency mode 8bpp 4?b1001 = luminance offset mode 4 bpp 4?b1010 = luminance offset mode 8 bpp 4?b1011 = 16 bpp (argb1555) 4?b1100 = 16 bpp (argb4444) 4?b1101 = 16 bpp (apal8) 4?b1110 = ycbcr422 (the blend engine allows only a single ycbcr layer in any blend operation) 4?b1111 = reserved 16 rle_en enable rle mode for layer. 1?b1:enabled 1?b0:disabled 17?27 luoffs look up table offset. value gives the offset to t he start address of the clut or tile (when used in internal tile mode) in the clut/tile ram. 29 bb chroma keying 1?b1: on 1?b0: off 30?31 ab alpha blending 2?b00: no alpha blending 2?b01: blend only the pixels selected by chroma keying in case bb=1?b1 2?b10: blend the whole frame 2?b11: same functionality as 2?b00. table 11-9. ctrldescl0_4 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-29 preliminary?subject to change without notice figure 11-8. ctrldescl0_5 register 11.3.4.6 control descr iptor l0_6 register figure 11-9 represents the control descriptor l0_6 regist er. this register sets the minimum chroma keying values for rgb. refer to section 11.4.4.5, alpha and chroma-key blending, for a description of chroma keying. offset: 0x010 (ctrldescl0_5) 0x02c (ctrldescl1_5) 0x048 (ctrldescl2_5) 0x064 (ctrldescl3_5) 0x080 (ctrldescl4_5) 0x09c (ctrldescl5_5) 0x0b8 (ctrldescl6_5) 0x0d4 (ctrldescl7_5) 0x0f0 (ctrldescl8_5) 0x10c (ctrldescl9_5) 0x128 (ctrldescl10_5) 0x144 (ctrldescl11_5) 0x160 (ctrldescl12_5) 0x17c (ctrldescl13_5) 0x198 (ctrldescl14_5) 0x1b4 (ctrldescl15_5) access: user read/write 0123456789101112131415 r00000000 ckmax_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ckmax_g ckmax_b w reset0000000000000000 table 11-10. ctrldescl0_5 field descriptions field description 8?15 ckmax_r chroma keying max red component 16?23 ckmax_g chroma keying max green component 24?31 ckmax_b chroma keying max blue component
pxd20 microcontroller reference manual, rev. 1 11-30 freescale semiconductor preliminary?subject to change without notice figure 11-9. ctrldescl0_6 register offset: 0x014 (ctrldescl0_6) 0x030 (ctrldescl1_6) 0x04c (ctrldescl2_6) 0x068 (ctrldescl3_6) 0x084 (ctrldescl4_6) 0x0a0 (ctrldescl5_6) 0x0bc (ctrldescl6_6) 0x0d8 (ctrldescl7_6) 0x0f4 (ctrldescl8_6) 0x110 (ctrldescl9_6) 0x12c (ctrldescl10_6) 0x148 (ctrldescl11_6) 0x164 (ctrldescl12_6) 0x180 (ctrldescl13_6) 0x198 (ctrldescl14_6) 0x1b8 (ctrldescl15_6) access: user read/write 0123456789101112131415 r00000000 ckmin_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ckmin_g ckmin_b w reset0000000000000000 table 11-11. ctrldescl0_6 field descriptions field description 8?15 ckmin_r chroma keying minimum red component 16?23 ckmin_g chroma keying minimum green component 24?31 ckmin_b chroma keying minimum blue component
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-31 preliminary?subject to change without notice 11.3.4.7 control descr iptor l0_7 register figure 11-10 represents the control descriptor l0_7 register. figure 11-10. control descriptor l0_7 register for the other 16 layers, the control de scriptor register set is identical. 11.3.4.8 control descriptor cursor 1 register (ctrldesccursor_1) figure 11-11 represents the control desc riptor cursor 1 register. offset: 0x018 (ctrldescl0_7) 0x034 (ctrldescl1_7) 0x050 (ctrldescl2_7) 0x06c (ctrldescl3_7) 0x088 (ctrldescl4_7) 0x094 (ctrldescl5_7) 0x0c0 (ctrldescl6_7) 0x0dc (ctrldescl7_7) 0x0f8 (ctrldescl8_7) 0x114 (ctrldescl9_7 0x130 (ctrldescl10_7) 0x14c (ctrldescl11_7) 0x168 (ctrldescl12_7) 0x184 (ctrldescl13_7) 0x19c (ctrldescl14_7) 0x1bc (ctrldescl15_7) access: user read/write 0123456789101112131415 r00000 tile_ver_size w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 tile_hor_size w reset0000000000000000 table 11-12. control descriptor l0_7 register field description 6?15 tile_ver_size height of the tile (in pixels) 24?31 tile_hor_size width of the tile (in multiples of 16 pixels)
pxd20 microcontroller reference manual, rev. 1 11-32 freescale semiconductor preliminary?subject to change without notice figure 11-11. control descriptor cursor 1 register (ctrldesccursor_1) 11.3.4.9 control descriptor cursor 2 register (ctrldesccursor_2) figure 11-12 represents the control desc riptor cursor 2 register. figure 11-12. control descriptor cursor 2 register (ctrldesccursor_2) offset: 0x1c0 access: user read/write 0123456789101112131415 r00000 height w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 width w reset0000000000000000 table 11-13. ctrldesccursor_1 field descriptions field description 6?15 height height of the cursor in pixels 22?31 width width of the cursor in pixels offset: 0x1c4 access: user read/write 0123456789101112131415 r00000 posy w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 posx w reset0000000000000000 table 11-14. ctrldesccursor_2 field descriptions field description posy y position of the cursor in pixels posx x position of the cursor in pixels
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-33 preliminary?subject to change without notice 11.3.4.10 control descriptor cursor 3 register (ctrldesccursor_3) figure 11-13 represents the control desc riptor cursor 3 register. figure 11-13. control descriptor cursor 3 register (ctrldesccursor_3) 11.3.4.11 control descriptor cursor 4 register (ctrldesccursor_4) figure 11-14 represents the control desc riptor cursor 4 register. figure 11-14. control descriptor cursor 4 register (ctrldesccursor_4) offset: 0x1c8 access: user read/write 0123456789101112131415 r cur _en default_cursor_color[0:8] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r default_cursor_color[9:24] w reset0000000000000000 table 11-15. control descriptor cursor_3 field descriptions field description cur_en cursor enable signal 1?b1: enable the cursor 1?b0: cursor is disabled default_curso r_color default pixel color value for the cursor. in the dcu3 , the pixel value for the cursor is fixed for a particular frame. offset: 0x1cc access: user read/write 0123456789101112131415 r00000000 hwc_blink_off w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 en_blink hwc_blink_on w reset0000000000000000
pxd20 microcontroller reference manual, rev. 1 11-34 freescale semiconductor preliminary?subject to change without notice 11.3.4.12 dcu3 mode re gister (dcu_mode) figure 11-15 represents the dcu_mode register. this re gister sets the mode in which dcu3 is operating. figure 11-15. dcu3 mode register (dcu_mode) table 11-16. ctrldesccursor_4 field descriptions field description hwc_blink_off hwc blink register. loads the counter value (number of frames) for which the cursor will remain turned off. en_blink enable the cursor blink mode. 1?b1:enable the blink mode 1?b0:disable the blink mode hwc_blink_on hwc blink register. loads the counter value (number of frames) for which the cursor will remain turned on. offset: 0x1d0 access: user read/write 0123456789101112131415 r dcu_sw_reset dither_en addb addg addr ddr_mode blend_iter pdi_sync_lock w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pdi_interpol_en raster_en pdi_en pdi_byte_rev pdi_de_mode pdi_narrow_mode pdi_mode pdi_slave_mode tag_en sig_en pdi_sync 0 en_gamma dcu_mode w reset1000000000000000 table 11-17. dcu_mode field descriptions field description dcu_sw_reset used to clear all the registers to reset state 1?b1:all the dcu3 registers are put in reset state dither_en enable dithering mode 1?b1:enabled. 1?b0:disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-35 preliminary?subject to change without notice addb two-bit value to be added to pixel blue component for dithering addg two-bit value to be added to pixel green component for dithering addr two-bit value to be added to pixel red component for dithering ddr_mode enables special ddr mode (see section 11.4.9, special ddr mode ). select blend_iter = 4 when enabled. blend_iter defines the number of planes used for blending. 3?d4:four plane blending 3?d3:three plane blending 3?d2:two plane blending default: two plane blending pdi_sync_lock defines the number of frames which should be received by the pdi validation state machine before it locks and sets the pdi_lock_det bit in the pdi status register (see section 11.3.4.26, pdi status register ) pdi_interpol_e n control bit to decide whether the conversion fr om ycbcr 4:2:2 to 4:4:4 needs to be done using interpolation or chroma value is same for two pixels 1?b1:interpolation is enabled. 1?b0:chroma value is same for two pixels raster_en enables raster scanning of pixel data including the vsync and hsync signals and the pixel data. changes to this bit take effect after the completion of the current frame. 1?b1: enabled 1?b0:disabled pdi_en enables the pdi 1?b1: enabled 1?b0:disabled pdi_byte_rev controls the byte ordering in narrow mode 1?b0:lsb is followed by msb data 1?b1:msb is followed by lsb data pdi_de_mode enables the pdi data enable mode. here data enable is treated as an input. 1?b0: value on data enable signal is ignored 1?b1: data enable signal must be present in incoming stream pdi_narrow_m ode enables the pdi narrow mode (refer to section 11.8.1.5, normal and narrow mode ) 1?b0: narrow mode is disabled 1?b1: narrow mode is enabled pdi_mode defines the different modes in which pdi is operating 2?b00: 8 bit monochrome data input 2?b01: 16 bit rgb 565 format 2?b10:18 bit rgb 666 data format. 2?b11:ycbcr data in 4:2:2 format. pdi_slave_ mode enables pdi slave mode 1?b0:disabled 1?b1:enabled table 11-17. dcu_mode field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 11-36 freescale semiconductor preliminary?subject to change without notice 11.3.4.13 bgnd register figure 11-16 represents the bgnd register. figure 11-16. bgnd register tag_en enables the calculation of crc only on the safety layers 1?b0: crc calculated over the whole area of in terest (area of interest given by sig_desc registers) 1?b1: calculates crc only on safety enabled layers sig_en enables the signature calculator block 1?b0: signature calculator is disabled 1?b1: signature calculator is enabled pdi_sync decides whether the pdi uses external or internal synchronization. 1?b0: external synchronization. the pdi re ceives the sync (hsync, vsync) signals from external source. 1?b1: internal synchronization. pdi extracts the sync information from the digital data. note: ycbcr mode supports internal sync only. therefore, when pdi_ mode = 3, pdi_sync must be set to 0. en_gamma enables/disables the gamma correction 1?b0: gamma correction is disabled 1?b1: gamma correction is enabled dcu_mode dcu3 operating mode 2?b00: dcu3 off (pixel clock active if enabled by i/o) 2?b01: normal mode. panel content controlled by layer configuration. 2?b10: test mode. dcu3 disables all dma fetches and all the pixels of an enabled layer take the value in the clut ram selected by the resp ective luoffs field of control descriptor 4. 2?b11: color bar generation. panel content controlled by color bar registers. offset: 0x1d4 access: user read/write 0123456789101112131415 r00000000 bgnd_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bgnd_g bgnd_b w reset0000000000000000 table 11-17. dcu_mode field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-37 preliminary?subject to change without notice 11.3.4.14 disp_size register figure 11-17 represents the disp_size register figure 11-17. disp_size register 11.3.4.15 hsyn_para register figure 11-18 represents the hsyn_para register. hsyn_para register sets timing parameters related to the horizontal synchronization si gnal generation. the fields fp_h, bp_h, and pw_h stand for hsync signal front-porch, back-porch, a nd active pulse width, respectively. table 11-18. bgnd field descriptions field description 8?15 bgnd_r red component of the default color displayed in the sectors where no layer is active 16?23 bgnd_g green component of the default color display ed in the sectors where no layer is active 24?31 bgnd_b blue component of the default color displayed in the sectors where no layer is active offset: 0x1d8 access: user read/write 0123456789101112131415 r00000 delta_y w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 delta_x w reset0000000000000000 table 11-19. disp_size field descriptions field description 6?15 delta_y sets the display size vertical resolution (in pixels) 24?31 delta_x sets the display size horizontal resolution (in multiples of 16 pixels)
pxd20 microcontroller reference manual, rev. 1 11-38 freescale semiconductor preliminary?subject to change without notice figure 11-18. hsyn_para register 11.3.4.16 vsyn_para register figure 11-19 represents the vsyn_para register. vsyn_para register sets timing parameters related to the vertical synchronization signal generation. th e fields fp_v, bp_v, and pw_v stand for vsync signal front-porch, back-porch, a nd active pulse width, respectively. figure 11-19. vsyn_para register offset: 0x1dc access: user read/write 0123456789101112131415 r0 bp_h 00 pw_h[0:3] w reset0000000011000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pw_h[4:8] 00 fp_h w reset0001100000000011 table 11-20. hsyn_para field descriptions field description 1?9 bp_h hsync back-porch pulse width (in pixel clock cycl es). pulse width has a minimum value of 1. 12?20 pw_h hsync active pulse width (in pixel clock cycles). 23?31 fp_h hsync front-porch pulse width (in pixel clock c ycles). pulse width has a minimum value of 1. offset: 0x1e0 access: user read/write 0123456789101112131415 r0 bp_v 00 pw_v[0:3] w reset0000000011000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pw_v[4:8] 00 fp_v w reset0001100000000011
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-39 preliminary?subject to change without notice 11.3.4.17 syn_pol register figure 11-20 represents the syn_pol register. syn_po l register selects polarity for corresponding synchronize signals (hsync, vsync, csync), and controls the bypass of hsync or vsync with csync signal. figure 11-20. syn_pol register table 11-21. vsyn_para field descriptions field description 1?9 bp_v vsync back-porch pulse width (in horizontal line cycles). pulse width has a minimum value of 1. 12?20 pw_v vsync active pulse width (in horizontal line cycles). 23?31 fp_v vsync front-porch pulse width (i n horizontal line cycles). pulse width has a minimum value of 1. offset: 0x1e4 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 inv_pdi_de inv_pdi_hs inv_pdi_vs inv_pdi_clk inv_pxck neg bp_vs bp_hs inv_cs inv_vs inv_hs w reset0000000000000000 table 11-22. syn_pol field descriptions field description inv_pdi_de polarity change of pdi input data enable. 1?b0: de is active high 1?b1: de is active low inv_pdi_hs polarity change of pdi input hsync. 1?b0: hsync is active high 1?b1: hsync is active low inv_pdi_vs polarity ch ange of pdi input vsync. 1?b0: vsync is active high 1?b1: vsync is active low
pxd20 microcontroller reference manual, rev. 1 11-40 freescale semiconductor preliminary?subject to change without notice 11.3.4.18 threshold register figure 11-21 represents the threshold register. figure 11-21. threshold register inv_pdi_clk polarity change of pdi input clock. 1?b0: dcu3 samples data on the rising edge 1?b1: dcu3 samples data on the falling edge inv_pxck polarity change of pixel clock. 1?b0: display samples data on the falling edge 1?b1: display samples data on the rising edge neg indicates if value at the output (p ixel data output) needs to be negated. 1?b0: output is to remain same 1?b1: output to be negated bp_vs bypass vertical synchronize signal (internal pin muxing). 1?b0: do not bypass vsync signal output 1 ?b1: csync bypass vsync signal, output csync in stead of vsync bp_hs bypass horizontal synchronize signal (internal pin muxing). 1?b0: do not bypass hsync signal output 1?b1: csync bypass hsync signal, output csync instead of hsync inv_cs invert composite synchronize signal. 1?b0: not invert csync signal, active high 1 ?b1: invert csync signal, active low inv_vs invert vertical synchronize signal 1?b0: not invert vsync signal, active high 1 ?b1: invert vsync signal, active low inv_hs invert horizontal synchronize signal. 1?b0: not invert hsync signal, active high 1?b1: invert hsync signal, active low offset: 0x1e8 access: user read/write 0123456789101112131415 r000000 ls_bf_vs w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r out_buf_high out_buf_low w reset0111100000001010 table 11-22. syn_pol field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-41 preliminary?subject to change without notice 11.3.4.19 interrupt status register (int_status) figure 11-22 indicates the interrupt status register. see section 11.5.4, interrupt generation , for a description of how the dcu3 collects interrupt events in to different source groups. figure 11-22. interrupt status register (int_status) table 11-23. threshold register field descriptions field description 6?15 ls_bf_vs lines before vsync threshold value. the ls_bf_vs status flag (in int_status) is set this number of lines before the vsync signal is asserted. 16?23 out_buf_high output buffer high threshold (in pixels). when t he output buffer exceeds this value the datapath clock is suspended. 24?31 out_buf_low output buffer filling low threshold (in pixels ).this value is used to generate the underrun exception (undrun in int_status). offset: 0x1ec access: user read/write 0123456789101112131415 r 000000000000 p4_fifo_hi_flag p4_fifo_lo_flag p3_fifo_hi_flag p3_fifo_lo_flag w w1cw1cw1cw1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 dma_trans_finish 00 ipm_error prog_end p2_fifo_hi_flag p2_fifo_lo_flag p1_fifo_hi_flag p1_fifo_lo_flag crc_overflow crc_ready vs_blank ls_bf_vs undrun vsync w w1c w1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c reset0000000000000000
pxd20 microcontroller reference manual, rev. 1 11-42 freescale semiconductor preliminary?subject to change without notice 11.3.4.20 interrupt mask register (int_mask) figure 11-23 represents the interrupt mask register.this register enables or ma sks corresponding interrupt. table 11-24. int_status field descriptions field description 12 p4_fifo_hi_flag interrupt signal to indicate that high thresh old has been reached for plane 4(fg2plane) input buffer 13 p4_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 4(fg2plane) input buffer 14 p3_fifo_hi_flag interrupt signal to indicate that high thresh old has been reached for plane 3(fg1plane) input buffer 15 p3_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 3(fg1plane) input buffer 17 dma_trans_finis h interrupt signal which indicates that the dcu3 dm a has fetched the last pixel of data from the memory 20 ipm_error interrupt signal which indicates that an error has occurred in the magenta line transaction 21 prog_end interrupt signal which indicates that the duration for programming of dcu3 registers and internal memories is finished 22 p2_fifo_hi_flag interrupt signal to indicate that high threshol d has been reached for plane 2 (fgplane) input buffer 23 p2_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 2 (fgplane) input buffer 24 p1_fifo_hi_flag interrupt signal to indicate that high threshold has been reached for plane 1 (bgplane) input buffer 25 p1_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 1 (bgplane) input buffer 26 crc_overflow interrupt signal to indicate that crc_ready has not been serviced and crc has been calculated for the next frame 27 crc_ready interrupt signal to indicate crc calculation is done and ready to be compared with precomputed crc value by the software 28 vs_blank interrupt signal to indicate vertical blanking peri od. this is the period in which all the registers that affect the visible state of the layers need to be latched. th is is needed so that cpu writes to the register while the display is be ing updated does not cause any errors. 29 ls_bf_vs lines before vsync interrupt. it is generated threshold ls_bf_vs number of lines ahead of the vertical front porch (fp_v) if enabled. th e cpu can program the registers after ls_bf_vs interrupt. 30 undrun under run exception interrupt. asserted when display needs data and output buffer filling is lower than or equal to the out_buf_low threshol d. interrupt is cleared when the data in the output buffer is greater than thres hold and cpu writes 1 to this bit. 31 vsync vertical synchronize interrupt. if enabled, an interrupt is generated at the beginning of a frame.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-43 preliminary?subject to change without notice figure 11-23. interrupt mask register (int_mask) offset: 0x1f0 access: user read/write 0123456789101112131415 r000000000000 m_p4_fifo_hi_flag m_p4_fifo_lo_flag m_p3_fifo_hi_flag m_p3_fifo_lo_flag w reset0000000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 m_dma_trans_finish 00 m_ipm_error m_prog_end m_p2_fifo_hi_flag m_p2_fifo_lo_flag m_p1_fifo_hi_flag m_p1_fifo_lo_flag m_crc_overflow m_crc_ready m_vs_blank m_ls_bf_vs m_undrun m_vsync w reset0100111111111111 table 11-25. int_mask field descriptions field description 12 m_p4_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 13 m_p4_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 14 m_p3_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 15 m_p3_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 17 m_dma_trans_finis h mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 20 m_ipm_error mask the interrupt 1?b1: interrupt is masked 1?b0:not masked
pxd20 microcontroller reference manual, rev. 1 11-44 freescale semiconductor preliminary?subject to change without notice 11.3.4.21 colbar registers the colbar registers are used to generate color bars in functional test mode. ei ght different pixel values are taken as input data, to disp lay 8 color bars on the display. 21 m_prog_end mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 22 m_p2_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 23 m_p2_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 24 m_p1_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 25 m_p1_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 26 m_crc_overflow mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 27 m_crc_ready mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 28 m_vs_blank mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 29 m_ls_bf_vs mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 30 m_undrun mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 31 m_vsync mask the interrupt 1?b1: interrupt is masked 1?b0:not masked table 11-26. colbar_ n register field descriptions field name description colbar_ n _r red component value table 11-25. int_mask field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-45 preliminary?subject to change without notice 11.3.4.21.1 colbar_1 register figure 11-24. colbar_1 register (black) 11.3.4.21.2 colbar_2 register figure 11-25. colbar_2 register (blue) colbar_ n _g green component value colbar_ n _b blue component value offset: 0x1f4 access: user read/write 0123456789101112131415 r11111111 colbar_1_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_1_g colbar_1_b w reset0000000000000000 offset: 0x1f8 access: user read/write 0123456789101112131415 r11111111 colbar_2_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_2_g colbar_2_b w reset0000000011111111 table 11-26. colbar_ n register field descriptions field name description
pxd20 microcontroller reference manual, rev. 1 11-46 freescale semiconductor preliminary?subject to change without notice 11.3.4.21.3 colbar_3 register figure 11-26. colbar_3 register (cyan) 11.3.4.21.4 colbar_4 register figure 11-27. colbar_4 register (green) offset: 0x1fc access: user read/write 0123456789101112131415 r11111111 colbar_3_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_3_g colbar_3_b w reset1111111111111111 offset: 0x200 access: user read/write 0123456789101112131415 r11111111 colbar_4_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_4_g colbar_4_b w reset1111111100000000
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-47 preliminary?subject to change without notice 11.3.4.21.5 colbar_5 register figure 11-28. colbar_5 register (yellow) 11.3.4.21.6 colbar_6 register figure 11-29. colbar_6 register (red) offset: 0x204 access: user read/write 0123456789101112131415 r11111111 colbar_5_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_5_g colbar_5_b w reset1111111100000000 offset: 0x208 access: user read/write 0123456789101112131415 r11111111 colbar_6_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_6_g colbar_6_b w reset0000000000000000
pxd20 microcontroller reference manual, rev. 1 11-48 freescale semiconductor preliminary?subject to change without notice 11.3.4.21.7 colbar_7 register figure 11-30. colbar_7 register (purple) 11.3.4.21.8 colbar_8 register figure 11-31. colbar_8 register (white) 11.3.4.22 divide ratio register (div_ratio) figure 11-32 shows the divide ratio register. offset: 0x20c access: user read/write 0123456789101112131415 r11111111 colbar_7_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_7_g colbar_7_b w reset0000000011111111 offset: 0x210 access: user read/write 0123456789101112131415 r11111111 colbar_8_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_8_g colbar_8_b w reset1111111111111111
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-49 preliminary?subject to change without notice figure 11-32. divide ratio register (div_ratio) 11.3.4.23 sign_calc_1 register figure 11-33 presents the register for vertical/horiz ontal size of the area for crc calculation. figure 11-33. sign _calc_1 register offset: 0x214 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 div_ratio w reset0000000000011111 table 11-27. div_ratio field descriptions field description 24?31 div_ratio specifies the divide value for the input clock. used to generate the pixel clock to support different types of displays. to divide by n, set the div_ratio to (n-1). offset: 0x218 access: user read/write 0123456789101112131415 r00000 sig_ver_size w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 sig_hor_size w reset0000000000000000 table 11-28. sign_calc_1 field descriptions field description 6?15 sig_ver_size vertical size of the window of interest of pixels for crc calculation (in pixels) 22?31 sig_hor_size horizontal size of window of interest of pixels for crc calculations (in pixels)
pxd20 microcontroller reference manual, rev. 1 11-50 freescale semiconductor preliminary?subject to change without notice 11.3.4.24 sign_calc_2 register figure 11-34 represents the register for position of th e window of interest for crc calculation. figure 11-34. sign _calc_2 register 11.3.4.25 crc_val register figure 11-35 represents the register presenting the crc value to the software for comparison. figure 11-35. crc_val register offset: 0x21c access: user read/write 0123456789101112131415 r00000 sig_ver_pos w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 sig_hor_pos w reset0000000000000000 table 11-29. sign_calc_2 field descriptions field description 6?15 sig_ver_pos vertical position of the window of interest of pixels for crc calculation (in pixels) 22?31 sig_hor_pos horizontal position of window of interest of pixels for crc calculation (in pixels) offset: 0x220 access: user read/write 0123456789101112131415 r crc_val[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r crc_val[16:31] w reset0000000000000000
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-51 preliminary?subject to change without notice 11.3.4.26 pdi status register figure 11-36 represents the pdi status register. figure 11-36. pdi status register (pdi_status) table 11-30. crc_val field descriptions field description 0?31 crc_val crc value calculated for safety enabled layers to be presented to the software for comparison. offset: 0x224 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 pdi_blanking_err pdi_ecc_err2 pdi_ecc_err1 pdi_lock_lost pdi_lock_det pdi_vsync_det pdi_hsync_det pdi_de_det pdi_clk_lost pdi_clk_det w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 table 11-31. pdi_status field descriptions field description 22 pdi_blanking_ err status bit to inform the software that 80h,10h sequence is not present during the blanking period in internal sync mode. 1?b1:correct data sequence not present in blanking period 1?b0:correct data sequence present in blanking period 23 pdi_ecc_err2 status bit to inform the software about multibit bit error that is detected. 1?b1: multibit ecc error detected 1?b0: multibit ecc error is not detected 24 pdi_ecc_err1 status bit to inform the software about one bit error is detected. 1?b1: one bit ecc error detected 1?b0: one bit ecc error is not detected 25 pdi_lock_lost status bit to inform the software that frame lock is lost. 1?b1: frame lock is lost 1?b0: frame is locked
pxd20 microcontroller reference manual, rev. 1 11-52 freescale semiconductor preliminary?subject to change without notice 11.3.4.27 pdi status mask register figure 11-37 represents the mask pdi status register figure 11-37. pdi status mask register 26 pdi_lock_det status bit to inform the software pdi is frame locked to the camera interface. 1?b1: frame lock is detected 1?b0: waiting for frame to lock 27 pdi_vsync_det status bit to inform the software that vsyn c for the camera data has been detected. 1?b1: pdi_vsync is detected 1?b0: pdi_vsync not detected 28 pdi_hsync_det status bit to inform the software that hsync for the camera data has been detected. 1?b1: pdi_hsync is detected 1?b0: pdi_hsync not detected 29 pdi_de_det status bit to inform the software that data enable for the camera data has been detected. 1?b1: pdi_de is detected 1?b0: pdi_de not detected 30 pdi_clk_lost status bit to inform the software that pdi_clk is lost 1?b1: pdi_clk is lost 1?b0: pdi_clk is present 31 pdi_clk_det status bit to inform the software that clock for the camera data has been detected. 1?b1: pdi_clk is detected 1?b0: pdi_clk not detected offset: 0x228 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 m_pdi_blanking_err m_pdi_ecc_err2 m_pdi_ecc_err1 m_pdi_lock_lost m_pdi_lock_det m_pdi_vsync_det m_pdi_hsync_det m_pdi_de_det m_pdi_clk_lost m_pdi_clk_det w reset0000001111111111 table 11-31. pdi_status field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-53 preliminary?subject to change without notice 11.3.4.28 parr_err_status register figure 11-38 shows the parameter er ror status register. an error in a layer can occur under the following conditions: a) number of pixels in a tile > maximum tile memory size in case of tile bandwidth optimized mode (when in internal memory mode) b) there is an automatic error checking mechan ism when a layer is enabled that detects a non-valid horizontal size and co lor format combination. see section 11.4.4.3, layer size and positioning, for details. these errors are grouped into a single bit error for each layer. the paramete r error specific to each layer is signalled only when the layer is enabled. table 11-32. pdi status mask register field descriptions field description m_pdi_blanking_err mask the pdi_blanking_err bit 1?b1: mask the pdi_blanking_err interrupt 1?b0: do not mask the pdi_blanking_err interrupt m_pdi_ecc_err2 mask t he pdi_ecc_err2 bit 1?b1: mask the pdi_ecc_err2 interrupt 1?b0: do not mask the pdi_ecc_err2 interrupt m_pdi_ecc_err1 mask t he pdi_ecc_err1 bit 1?b1: mask the pdi_ecc_err1 interrupt 1?b0: do not mask the pdi_ecc_err1 interrupt m_pdi_lock_lost mask t he pdi_lock_lost bit 1?b1: mask the pdi_lock_lost interrupt 1?b0: do not mask the pdi_lock_lost interrupt m_pdi_lock_det mask t he pdi_lock_det bit 1?b1: mask the pdi_lock_det interrupt 1?b0: do not mask the pdi_lock_det interrupt m_pdi_vsync_det mask the pdi_vsync_det bit 1?b1: mask the pdi_vsync_det interrupt 1?b0: do not mask the pdi_vsync_det interrupt m_pdi_hsync_det mask the pdi_hsync_det bit 1?b1: mask the pdi_hsync_det interrupt 1?b0: do not mask the pdi_hsync_det interrupt m_pdi_de_det mask the pdi_de_det bit 1?b1: mask the pdi_de_det interrupt 1?b0: do not mask the pdi_de_det interrupt m_pdi_clk_lost mask t he pdi_clk_lost bit 1?b1: mask the pdi_cl k_lost interrupt 1?b0: do not mask the pdi_clk_lost interrupt m_pdi_clk_det mask the pdi_clk_det bit 1?b1: mask the pdi_clk interrupt 1?b0: do not mask the pdi_clk interrupt
pxd20 microcontroller reference manual, rev. 1 11-54 freescale semiconductor preliminary?subject to change without notice rle_err occurs when more than one layer ha s its rle_en bit set (control descriptor 4). disp_err occurs when the size of di splay (height or width) is set to zero or when the pulse width of hsync/vsync is programmed as zero. sig_err occurs when the area of interest for cal culating crc value is progr ammed with values which are outside the display. hwc_err occurs if size of cursor programme d is greater than memory size(256x32).see section 11.4.5, hardware cursor, for further details on how cursor can be programmed. figure 11-38. parameter error stat us register (parr_err_status) offset: 0x22c access: user read/write 0123456789101112131415 r 000000000000 rle_err hwc_err sig_err disp_err w w1cw1cw1cw1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r l15_parr_err l14_parr_err l13_parr_err l12_parr_err l11_parr_err l10_parr_err l9_parr_err l8_parr_err l7_parr_err l6_parr_err l5_parr_err l4_parr_err l3_parr_err l2_parr_err l1_parr_err l0_parr_err ww1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c reset0000000000000000 table 11-33. parr_err_status field descriptions field description 13 rle_err error signal to indicate that more than one layer has rle mode enabled. 13 hwc_err interrupt signal to indicate hwc error. this can occur if hwc position is out of display area or cursor memory is bigger than the hwc size. when this occurs, the hwc is disabled. 14 sig_err interrupt occurs whenever the area of interest specified by sig_calc r egister is outside the display size. 1?b0: sig_err is not set 1?b1: sig_err is set 15 disp_err interrupt occurs whenever width and height of disp lay, pulse width (both vertical and horizontal sync) value is 0. 1?b0: disp_err is not set 1?b1: disp_err is set
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-55 preliminary?subject to change without notice 16 l15_parr_err interrupt occurs whenever there is an error in layer 15. 1?b0: parameter error is not set 1?b1: parameter error is set 17 l14_parr_err interrupt occurs whenever there is an error in layer 14. 1?b0: parameter error is not set 1?b1: parameter error is set 18 l13_parr_err interrupt occurs whenever there is an error in layer 13. 1?b0: parameter error is not set 1?b1: parameter error is set 19 l12_parr_err interrupt occurs whenever there is an error in layer 12. 1?b0: parameter error is not set 1?b1: parameter error is set 20 l11_parr_err interrupt occurs whenever there is an error in layer 11. 1?b0: parameter error is not set 1?b1: parameter error is set 21 l10_parr_err interrupt occurs whenever there is an error in layer 10. 1?b0: parameter error is not set 1?b1: parameter error is set 22 l9_parr_err interrupt occurs whenever there is an error in layer 9 1?b0: parameter error is not set 1?b1: parameter error is set 23 l08_parr_err interrupt occurs whenever there is an error in layer 8. 1?b0: parameter error is not set 1?b1: parameter error is set 24 l7_parr_err interrupt occurs whenever there is an error in layer 7 1?b0: parameter error is not set 1?b1: parameter error is set 25 l6_parr_err interrupt occurs whenever there is an error in layer 6. 1?b0: parameter error is not set 1?b1: parameter error is set 26 l5_parr_err interrupt occurs whenever there is an error in layer 5. 1?b0: parameter error is not set 1?b1: parameter error is set 27 l4_parr_err interrupt occurs whenever there is an error in layer 4 1?b0: parameter error is not set 1?b1: parameter error is set 28 l3_parr_err interrupt occurs whenever there is an error in layer 3. 1?b0: parameter error is not set 1?b1: parameter error is set 29 l2_parr_err interrupt occurs whenever there is an error in layer 2. 1?b0: parameter error is not set 1?b1: parameter error is set table 11-33. parr_err_status field descriptions (continued) field description 13 rle_err error signal to indicate that more than one layer has rle mode enabled.
pxd20 microcontroller reference manual, rev. 1 11-56 freescale semiconductor preliminary?subject to change without notice 11.3.4.29 mask parr_err status register figure 11-39 shows the mask register for pa rameter error status register. figure 11-39. mask parame ter error status register 30 l1_parr_err interrupt occurs whenever there is an error in layer 1. 1?b0: parameter error is not set 1?b1: parameter error is set 31 l0_parr_err interrupt occurs whenever there is an error in layer 0. 1?b0: parameter error is not set 1?b1: parameter error is set offset: 0x230 access: user read/write 0123456789101112131415 r000000000000 m_rle_err m_hwc_err m_sig_err m_disp_err w reset0000000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m_l15_parr_err m_l14_parr_err m_l13_parr_err m_l12_parr_err m_l11_parr_err m_l10_parr_err m_l9_parr_err m_l8_parr_err m_l7_parr_err m_l6_parr_err m_l5_parr_err m_l4_parr_err m_l3_parr_err m_l2_parr_err m_l1_parr_err m_l0_parr_err w reset1111111111111111 table 11-34. mask parameter error status register field descriptions field description 13 m_rle_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 13 m_hwc_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 14 m_sig_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt table 11-33. parr_err_status field descriptions (continued) field description 13 rle_err error signal to indicate that more than one layer has rle mode enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-57 preliminary?subject to change without notice 15 m_disp_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 16 m_l15_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 17 m_l14_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 18 m_l13_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 19 m_l12_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 20 m_l11_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 21 m_l10_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 22 m_l9_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 23 m_l8_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 24 m_l7_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 25 m_l6_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 26 m_l5_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 27 m_l4_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt table 11-34. mask parameter error status register field descriptions (continued) field description 13 m_rle_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt
pxd20 microcontroller reference manual, rev. 1 11-58 freescale semiconductor preliminary?subject to change without notice 11.3.4.30 threshold_inp_buf_1 register figure 11-40 shows the threshold register for input buffer. figure 11-40. threshold input buffer 1 register (threshold_inp_buf_1) 28 m_l3_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 29 m_l2_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 30 m_l1_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 31 m_l0_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt offset: 0x234 access: user read/write 0123456789101112131415 r0 inp_buf_p2_hi 0 inp_buf_p2_lo w reset0111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 inp_buf_p1_hi 0 inp_buf_p1_lo w reset0111111100000000 table 11-35. threshold_inp_buf_1 field descriptions field description inp_buf_p2_hi high threshold for input buffer for blend stage 2. inp_buf_p2_lo low threshold for input buffer for blend stage 2. inp_buf_p1_hi high threshold for input buffer for blend stage 1 (background). inp_buf_p1_lo low threshold for input buffer for blend stage 1 (background plane). table 11-34. mask parameter error status register field descriptions (continued) field description 13 m_rle_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-59 preliminary?subject to change without notice 11.3.4.31 threshold_inp_buf_2 register figure 11-41 represents the threshold register fo r input buffer for plane 3 and plane 4. figure 11-41. threshold_inp_buf_2 register 11.3.4.32 luma component register figure 11-42 represents the luma component register. figure 11-42. luma component register offset: 0x238 access: user read/write 0123456789101112131415 r0 inp_buf_p4_hi 0 inp_buf_p4_lo w reset0111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 inp_buf_p3_hi 0 inp_buf_p3_lo w reset0111111100000000 table 11-36. threshold_inp_buf_2 field descriptions field description inp_buf_p4_hi high threshold for input buffer for blend stage 4. inp_buf_p4_lo low threshold for input buffer for blend stage 4. inp_buf_p3_hi high threshold for input buffer for blend stage 3. inp_buf_p3_lo low threshold for input buffer for blend stage 3. offset: 0x23c access: user read/write 0123456789101112131415 r y_red 0 y_green[0:4] w reset1001010100010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y_green[5:9] 0 y_blue w reset1010001001010100
pxd20 microcontroller reference manual, rev. 1 11-60 freescale semiconductor preliminary?subject to change without notice 11.3.4.33 red chroma components figure 11-43 represents the red chroma component register. figure 11-43. red chroma component register 11.3.4.34 green chroma component register figure 11-44 represents the green chroma component register table 11-37. luma component register field descriptions field description 0?9 y_red luminance coefficient for red matrix 11?20 y_green luminance coefficient for green matrix 22?31 y_blue luminance coefficient for blue matrix offset: 0x240 access: user read/write 0123456789101112131415 r00000 cr_red w reset0000001100110001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_red w reset0000000000000000 table 11-38. red chroma component register field descriptions field description 5?15 cr_red cr coefficient for red matrix 20?31 cb_green cb coefficient for red matrix
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-61 preliminary?subject to change without notice figure 11-44. green chroma component register 11.3.4.35 blue chroma component register figure 11-45 represents the blue chroma component register. figure 11-45. blue chroma component register offset: 0x244 access: user read/write 0123456789101112131415 r00000 cr_green w reset0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_green w reset0000111100111000 table 11-39. green chroma component register field descriptions field description 5?15 cr_green cr coefficient for green matrix 20?31 cb_green cb coefficient for green matrix offset: 0x248 access: user read/write 0123456789101112131415 r00000 cr_blue w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_blue w reset0000010000001001
pxd20 microcontroller reference manual, rev. 1 11-62 freescale semiconductor preliminary?subject to change without notice 11.3.4.36 crc_pos register figure 11-46 represents the crc_pos register. figure 11-46. crc_pos register 11.3.4.37 fg0_fcolor register figure 11-47 represents the fg0_fcolor register. table 11-40. blue chroma component register field descriptions field description 5?15 cr_blue cr coefficient for blue matrix 20?31 cb_blue cb coefficient for blue matrix offset: 0x24c access: user read/write 0123456789101112131415 r crc_pos[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r crc_pos[16:31] w reset0000000000000000 table 11-41. crc_pos field descriptions field description 0?31 crc_pos crc position value calculated for safety enabled layers to be presented to the software for comparison
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-63 preliminary?subject to change without notice figure 11-47. fg0_fcolor register 11.3.4.38 fg0_bcolor figure 11-48 represents the fg0_bcolor register. offset: 0x250 (fg0_fcolor) 0x258 (fg1_fcolor) 0x260 (fg2_fcolor) 0x268 (fg3_fcolor) 0x270 (fg4_fcolor) 0x278 (fg5_fcolor)) 0x280 (fg6_fcolor) 0x288 (fg7_fcolor) 0x290 (fg8_fcolor) 0x298 (fg9_fcolor) 0x2a0 (fg10_fcolor) 0x2a8 (fg11_fcolor) 0x2b0 (fg12_fcolor) 0x2b8 (fg13_fcolor) 0x2c0 (fg14_fcolor) 0x2c8 (fg15_fcolor) access: user read/write 0123456789101112131415 r00000000 fg0_fcolor[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fg0_fcolor[8:23] w reset0000000000000000 table 11-42. fg0_fcolor field descriptions field description 8?31 fg0_fcolor foreground color for layer fg0 for pre-blending engine
pxd20 microcontroller reference manual, rev. 1 11-64 freescale semiconductor preliminary?subject to change without notice figure 11-48. fg0_bcolor register table 11-43. fg0_color register field description offset: 0x254 (fg0_bcolor) 0x25c (fg1_bcolor) 0x264 (fg2_bcolor) 0x26c (fg3_bcolor) 0x274 (fg4_bcolor) 0x27c (fg5_bcolor)) 0x284 (fg6_bcolor) 0x28c (fg7_bcolor) 0x294 (fg8_bcolor) 0x29c (fg9_bcolor) 0x2a4 (fg10_bcolor) 0x2ac (fg11_bcolor) 0x2b4 (fg12_bcolor) 0x2bc (fg13_bcolor) 0x2c4 (fg14_bcolor) 0x2cc (fg15_bcolor) access: user read/write 0123456789101112131415 r00000000 fg0_bcolor[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fg0_bcolor[8:23] w reset0000000000000000 field description 8?31 fg0_bcolor background color for layer fg0 for pre-blending engine
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-65 preliminary?subject to change without notice 11.3.4.39 lyr_intpol_en figure 11-49 represents lyr_intpol_en register. figure 11-49. lyr_intpol_en register 11.3.4.40 lyr_luma_component figure 11-50 represents the layer luma component register. figure 11-50. layer luma component register offset: 0x2d0 access: user read/write 0123456789101112131415 r en 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-44. lyr_intpol_en field descriptions field description en interpolation enable bit for dcu3 layer coded in ycbcr422 format. this bit controls whether the chroma value for eac h pixel in the conversion from ycbcr 4:2:2 to 4:4:4 should use interpolation or the same value for both pixels. 0 chroma value is same for two pixels 1 interpolation is enabled. offset: 0x2d4 access: user read/write 0123456789101112131415 r y_red 0 y_green[0:4] w reset1001010100010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y_green[5:9] 0 y_blue w reset1010001001010100
pxd20 microcontroller reference manual, rev. 1 11-66 freescale semiconductor preliminary?subject to change without notice 11.3.4.41 lyr_chroma_red figure 11-51 represents the layer red chroma component register. figure 11-51. layer red chroma component register 11.3.4.42 lyr_chroma_green figure 11-52 represents the layer green chroma component register table 11-45. layer luma componen t register field descriptions field description 0?9 y_red luminance coefficient for red matrix 11?20 y_green luminance coefficient for green matrix 22?31 y_blue luminance coefficient for blue matrix offset: 0x2d8 access: user read/write 0123456789101112131415 r00000 cr_red w reset0000001100110001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_red w reset0000000000000000 table 11-46. layer red chroma component register field descriptions field description 5?15 cr_red cr coefficient for red matrix 20?31 cb_green cb coefficient for red matrix
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-67 preliminary?subject to change without notice figure 11-52. layer green chroma component register 11.3.4.43 lyr_chroma_blue figure 11-53 represents the layer blue chroma component register. figure 11-53. layer blue chroma component register offset: 0x2dc access: user read/write 0123456789101112131415 r00000 cr_green w reset0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_green w reset0000111100111000 table 11-47. layer green chroma component register field descriptions field description 5?15 cr_green cr coefficient for green matrix 20?31 cb_green cb coefficient for green matrix offset: 0x2e0 access: user read/write 0123456789101112131415 r00000 cr_blue w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_blue w reset0000010000001001
pxd20 microcontroller reference manual, rev. 1 11-68 freescale semiconductor preliminary?subject to change without notice 11.3.4.44 comp_imsize figure 11-54 represents the compression image size register. figure 11-54. comp_imsize register 11.3.4.45 global protection register figure 11-55 represents the global protection register. table 11-48. layer blue chroma component register field descriptions field description 5?15 cr_blue cr coefficient for blue matrix 20?31 cb_blue cb coefficient for blue matrix offset: 0x2e4 access: user read/write 0123456789101112131415 r0000000000 comp_imsize[21:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r comp_imsize[15:0] w reset0000000000000000 table 11-49. comp_imsize register field descriptions field description comp_imsize compressed image size in bytes for rle coded layer
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-69 preliminary?subject to change without notice figure 11-55. global protection register 11.3.4.46 soft lock bit register l0 figure 11-56 represents the soft lock bit register for la yer0. this is used to protect the 7 control descriptor layer re gisters for layer0. figure 11-56. soft lock register l0 offset: 0x300 access: user read/write 0123456789101112131415 r hlb 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-50. global protection register field descriptions field description 0 hlb hard lock bit. this bit cannot be cleared once it is set by software. it can only be cleared by a system reset. 1?b1:all slb?s are write protected & cannot be modified 1?b0:all slb?s are accessible & can be modified offset: 0x304 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l0_1 slb_l0_2 slb_l0_3 slb_l0_4 0000 slb_l0_5 slb_l0_6 slb_l0_7 0 w wen_lo_1 wen_lo_2 wen_lo_3 wen_lo_4 wen_lo_5 wen_lo_6 wen_lo_7 reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000
pxd20 microcontroller reference manual, rev. 1 11-70 freescale semiconductor preliminary?subject to change without notice table 11-51. soft lock register l0 field descriptions field description 0 wen_l0_1 write enable for soft lock bit slb_l0_1 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_l0_2 write enable for soft lock bit slb_l0_2 1?b1: value is written to slb 1?b0: slb is not modified 2 wen_l0_3 write enable for soft lock bit slb_l0_3 1?b1: value is written to slb 1?b0: slb is not modified 3 wen_l0_4 write enable for soft lock bit slb_l0_4 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_l0_1 soft lock bit for control desc l0_1 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l0_2 soft lock bit for control desc l0_2 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 6 slb_l0_3 soft lock bit for control desc l0_3 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 7 slb_l0_4 soft lock bit for control desc l0_4 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 8 wen_l0_5 write enable for soft lock bit slb_l0_5 1?b1: value is written to slb 1?b0: slb is not modified 9 wen_l0_6 write enable for soft lock bit slb_l0_6 1?b1: value is written to slb 1?b0: slb is not modified 10 wen_l0_7 write enable for soft lock bit slb_l0_7 1?b1: value is written to slb 1?b0: slb is not modified 12 slb_l0_5 soft lock bit for control desc l0_5 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 13 slb_l0_6 soft lock bit for control desc l0_6 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 14 slb_l0_7 soft lock bit for control desc l0_7 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-71 preliminary?subject to change without notice 11.3.4.47 soft lock bit register l1 figure 11-57 represents the soft lock bit register for la yer1. this is used to protect the 7 control descriptor layer re gisters for layer1. figure 11-57. soft lock register l1 offset: 0x308 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l1_1 slb_l1_2 slb_l1_3 slb_l1_4 0000 slb_l1_5 slb_l1_6 slb_l1_7 0 w wen_l1_1 wen_l1_2 wen_l1_3 wen_l1_4 wen_l1_5 wen_l1_6 wen_l1_7 reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-52. soft lock register l1 field descriptions field description 0 wen_l1_1 write enable for soft lock bit slb_l1_1 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_l1_2 write enable for soft lock bit slb_l1_2 1?b1: value is written to slb 1?b0: slb is not modified 2 wen_l1_3 write enable for soft lock bit slb_l1_3 1?b1: value is written to slb 1?b0: slb is not modified 3 wen_l1_4 write enable for soft lock bit slb_l1_4 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_l1_1 soft lock bit for control desc l1_1 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l1_2 soft lock bit for control desc l1_2 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 6 slb_l1_3 soft lock bit for control desc l1_3 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 11-72 freescale semiconductor preliminary?subject to change without notice 11.3.4.48 soft lock disp_size register figure 11-58 represents the soft lock disp_size register. figure 11-58. soft lock disp_size register 7 slb_l1_4 soft lock bit for control desc l1_4 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 8 wen_l1_5 write enable for soft lock bit slb_l1_5 1?b1: value is written to slb 1?b0: slb is not modified 9 wen_l1_6 write enable for soft lock bit slb_l1_6 1?b1: value is written to slb 1?b0: slb is not modified 10 wen_l1_7 write enable for soft lock bit slb_l1_7 1?b1: value is written to slb 1?b0: slb is not modified 12 slb_l1_5 soft lock bit for control desc l1_5 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 13 slb_l1_6 soft lock bit for control desc l1_6 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 14 slb_l1_7 soft lock bit for control desc l1_7 register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x30c access: user read/write 0123456789101112131415 r0 0 0 0 slb_disp 00000000000 w wen_disp reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-52. soft lock register l1 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-73 preliminary?subject to change without notice 11.3.4.49 soft lock hsy nc/vsync para register figure 11-59 represents the soft lo ck hsync/vsync register. figure 11-59. soft lock hsync/vsync para register table 11-53. soft lock disp_size register field descriptions field description 0 wen_disp write enable for soft lock bit slb_disp 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_disp soft lock bit for disp_size register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x310 access: user read/write 0123456789101112131415 r0 0 0 0 slb_hsync slb_vsync 0000000000 w wen_hsync wen_vsync reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-54. soft lock hsync/vsync para register field descriptions field description 0 wen_hsync write enable for soft lock bit slb_hsync 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_vsync write enable for soft lock bit slb_vsync 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_hsync soft lock bit for hsync register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_vsync soft lock bit for vsync register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 11-74 freescale semiconductor preliminary?subject to change without notice 11.3.4.50 soft lock pol register figure 11-60 represents the soft lock pol register. figure 11-60. soft lock pol register 11.3.4.51 soft lock l0_transp register figure 11-61 represents the soft lock l0_transp register. offset: 0x314 access: user read/write 0123456789101112131415 r0 0 0 0 slb_pol 00000000000 w wen_pol reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-55. soft lock pol register field descriptions field description 0 wen_pol write enable for so ft lock bit slb_pol 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_pol soft lock bit for syn_pol register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-75 preliminary?subject to change without notice figure 11-61. soft lock l0_transp register offset: 0x318 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l0_fcolor slb_l0_bcolor 0000000000 w wen_l0_fcolor wen_l0_bcolor reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-56. soft lock l0_transp register field descriptions field description 0 wen_l0_fcolo r write enable for soft lock bit slb_l0_fcolor 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_l0_bcolo r write enable for soft lo ck bit slb_l0_bcolor 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_l0_fcolor soft lock bit for l0_fcolor register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l0_bcolor soft lock bit for l0_bcolor register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 11-76 freescale semiconductor preliminary?subject to change without notice 11.3.4.52 soft lock l1_transp register figure 11-62 represents the soft lock l1_transp register. figure 11-62. soft lock l1_transp register 11.4 functional description the dcu3 is a master on the crossbar switch; it fetc hes graphic source informati on directly from memory and dynamically performs bl ending and bit-blitting opera tions before delivering data to a tft lcd panel. offset: 0x31c access: user read/write 0123456789101112131415 r0 0 0 0 slb_l1_fcolor slb_l1_bcolor 0000000000 w wen_l1_fcolor wen_l1_bcolor reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 table 11-57. soft lock l0_transp register field descriptions field description 0 wen_l1_fcolo r write enable for soft lock bit slb_l1_fcolor 1?b1: value is written to slb 1?b0: slb is not modified. 1 wen_l1_bcolo r write enable for soft lo ck bit slb_l1_bcolor 1?b1: value is written to slb 1?b0: slb is not modified. 4 slb_l1_fcolor soft lock bit for l1_fcolor register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l1_bcolor soft lock bit for l1_bcolor register. 1?b1:associated protected register is locked for write access 1?b0:associated protected regist er is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-77 preliminary?subject to change without notice 11.4.1 graphic sources as the dcu3 is a master on the cros sbar switch, it can access directly a ny memory or device connected to the crossbar switch as a slave. th is includes all on-chip flash, all on-ch ip ram, and any slave capable of providing high enough data rates, such as, for exampl e an expanded bus interface or a quadspi module. therefore, any compatible graphic stored anywhere on -chip or in an accessible interface can be displayed on the connected tft lcd panel with no further interv ention from the cpu, except to program the dcu3 to fetch and place it. the dcu3 also includes a dedicated memory to store the graphic for its cursor layer. 11.4.2 tft lcd panel configuration the nature and timing of the signals required by tf t lcd panels vary greatly between manufacturers. therefore, the dcu3 allows highly flexible and detail ed configuration of these signals. refer to the tcon module chapter for additional options when confi guring timing signal outputs for panels without an embedded timing controller. timing diagrams for tft lcd panels are typically divided into a horiz ontal timing chart and a vertical timing chart. see figure 11-63 for details.
pxd20 microcontroller reference manual, rev. 1 11-78 freescale semiconductor preliminary?subject to change without notice figure 11-63. hsync and vsync timing diagram the number of pixel data slots in the horizontal timing diagram is defi ned by the width of the panel. the number of line data slots is define d by the height of the panel. both of these values are defined in the disp_size register (delta_x, delta_y). the width of the panel must always be defined as a multiple of 16. the timing of the pixel clock is defined by the div_ratio register and the frequency of the clock supplied to the dcu3. in addition to defining the number a nd timing of pixels in each line and the number of lines, it is normal for tft lcd panel manufacturers to de fine other timing signals in terms of pixel clock pe riods or of the number of horizontal lines. the dc u3 also follows this convention. if the tft lcd panel requires a horizontal synchroni zing signal (hsync) and/or a data enable signal, then these can be configured usi ng the fields in the hsyn_para re gister. hsync provides a pulse to give the panel notice that the next line of pixel data is about to start, and the data enable signal indicates when that data is present. the pw _h bit field indicates th e width of the hsync pulse , in pixel data clock pclk pixel data invalid data 12 3 4 delta_x invalid data pw_h bp_h fp_h delta_x hsync data enable hsync invalid data invalid data 1 2 3 4 delta_y bp_v pw_v fp_v line data vsync data enable 1/rr where rr is the frame refresh rate delta_x is the horizontal resolution of the display ?? 1 (de) (de)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-79 preliminary?subject to change without notice periods. the bp_h bit field defines the delay between the end of the hsync pulse and the start of the data enable signal (and pixe l data delivery), in pixel clock peri ods. the fp_h bit field defines the delay between the end of the data enable signal (and pixel data delivery) and the ne xt hsync pulse, in pixel clock periods. fp_h and bp_h have minimum values of 1. if the tft lcd panel require s a vertical synchronizing signal (vsync), then this can be configured using the fields in the vsyn_para register. vsync provide s a pulse to give the pa nel notice that the next frame of pixel data lines is about to start, and the pa nel defines delays before a nd after this pul se, in terms of pixel clock periods. the pw_v bi t field indicates the width of th e vsync pulse in horizontal line periods. the bp_v bit field defines the delay between the end of the vsync pulse and the start of the next pixel data (data enable signa l), in horizontal line periods. the fp_v bit field defines the delay between the end of the last pixel data (data enable signal) and the next vsync pulse, in horizontal line periods. fp_v and bp_v ha ve minimum values of 1. the polarity of all these signals, including the pixel data itself, may be inverted by using the control bits in the syn_pol register. the refresh rate for the pa nel can be calculated using equation 11-1 and equation 11-2 below. eqn. 11-1 where: pix_clk is the pixel clock delta_x is the horizontal resolution (in pixels) delta_y is the vertical resolution (in pixels) fp_h is the hsync front porch pulse width (in pixel clock cycles) bp_h is the hsync back porch pul se width (in pixel clock cycles) pw_h is the hsync active pulse width (in pixel clock cycles) fp_v is the vsync front porch pulse width (in pixel clock cycles) bp_v is the vsync back porch pul se width (in pixel clock cycles) pw_v is the vsync active pulse width (in pixel clock cycles) pixel clock = (dcu3 clock) / prescale value eqn. 11-2 where prescale value is an integer value that can range from 2?32. 11.4.3 dcu3 mode selection and background color once the dcu3 is configured for use with a particular tft lcd panel, it can be enabled for use. there are five modes to choose from, as shown in table 11-58 . table 11-58. list of dcu3 operating modes mode dcu_mode[1:0] pdi_en description off 00 x dcu3 disabled; the tft lcd panel is not driven. color bar 11 x dcu3 displays a test pattern consisting of vertical bands of programmable color. rr pix_clk delta_xfp_hpw_hbp_h ++ + ?? delta_yfp_vpw_vbp_v ++ + ?? ? --------------------- --------------------- --------------------- --------------------- ---------------------- --------------------- ------------------ ---------------- - =
pxd20 microcontroller reference manual, rev. 1 11-80 freescale semiconductor preliminary?subject to change without notice the dcu_mode, pdi_en and pdi_slave_mode cont rol bits are in the dcu_mode register. the dcu3 has an interface enable bit for the tft lc d panel interface called raster_en, also in the dcu_mode register. when raster_en is 0 the raster scanning of pixels to the panel is disabled but the pixel clock continues to run as long if enabled on the i/o pin. color bar mode is intended for testing the interface between the dcu3 and the tft lcd panel. in this mode, the panel is divided into eight vertical strips of equal width, and the strips display a single color whose rgb value is specified in the colbar_1 to colb ar_8 registers. at reset, the colors are set to black, blue, cyan, green, yellow, red, magenta, and white, where positive logic for the rgb values is assumed. the mode can be used to verify correct connection of the in terface to the dcu3 and correct timing configuration of the interface. in this m ode, any layer configurati on settings are ignored. in normal mode, the dcu3 operates a ccording to the timings specified in section 11.4.2, tft lcd panel configuration and displays graphics according to the confi guration of its layers. the bgnd register sets the rgb color of the background shown when no other layers are present. this background color is included in the layer blending proces s but, since it is always the bac kground, it does not include any layer blending settings. in pdi normal mode, the dcu3 adopts the timing provided on the pdi interface and replaces the background color by the pixel data co ming from the pdi interface. the ti ming values set in the dcu3 are ignored in this mode, and the pixe l clock and synchr onization signals are taken from the pdi interface and passed to the tft lcd panel. the c ontent of the panel is a combinati on of the incoming pixel stream and layers generated by the dcu3. pdi slave mode allows the dcu3 to synchronize with the external timing signals on the pdi input. 11.4.4 layer configuration and blending users control the graphical content of the tft panel by manipulating the configurat ion of elements in the dcu3 called layers. each la yer has a control descriptor that defi nes the size, position, memory encoding, blending, and memory location of the graphic to be displayed. the dcu3 provi des 16 independent layers that are identical except that they have a fixed prio rity with respect to each other, and this affects how individual pixels are blended when layers overlap. the blending setting on each layer allo ws the pixels on that layer to be opaque, partially transparent, or fu lly transparent, which allows them to combine with pixels on other layers that they overlap. normal 01 0 dcu3 blends layers and displays result on tft lcd panel. pdi normal 01 1 as normal mode, except that the panel timing is defined by the input on the pdi interface, and the background color is replaced by the content provided on the pdi interface. pdi slave 01 0 the dcu3 synchronizes its timing to an external signal when pdi_slave_mode is enabled. table 11-58. list of dcu3 operating modes mode dcu_mode[1:0] pdi_en description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-81 preliminary?subject to change without notice 11.4.4.1 blending pr iority of layers the 16 layers available in the dcu3 ar e each fixed in priority order, with layer 0 be ing the highest priority, layer 1 being the second highest priority, and so on until layer 15, which is the lowest priority. the priority is used by the dcu3 to define how to blend individual pixels within the layers. fo r example, if layer 0 is defined as not being blended with other layers and a pixel on layer 0 overlaps a pixel on layer 1 then the pixel on layer 0 will be visible on the panel unchanged by the pixel on layer 1. however, if layer 0 is defined as being partia lly transparent, then the dc u3 will blend the overlapping pixel such that the result is a combination of the pixel on layer 0 and the pixel on layer 1. it is possible to blend up to four layers at each pixel position. as there is a maximum number of layers that can ble nded together, then any pixe l on a layer that is lower than the threshold priority will not be included in a ny blend. if a pixel is on a layer that has the lowest priority in any blending sche me, then the blending settings for that pi xel are ignored and th e pixel is treated as a background pixel. this means th at a lower priority layer may have some pixels completely obscured by those on higher priority layers on one part of the panel, and some ot her pixels visible or blended on other parts of the panel. figure 11-64 shows how the pixel blend takes place inside the dcu3. the priori ty of the layers determines at which stage of the blend the pixe l enters. any pixels lower than the threshold priority are ignored and, as can be seen, the blend settings for the lowest pr iority pixel is also ignor ed. the maximum number of pixels in the blend is configured by the blend_iter bit field in th e dcu_mode regist er. as can be seen in the figure, the blending pro cess is iterative so that four-pixel blending takes more dcu3 clock cycles than three-pixel blending, a nd three-pixel blending takes more dc u3 clock cycles than two-pixel blending. figure 11-64. pixel blending stack this priority concept is illustrated in figure 11-65 and figure 11-66 . in this case, there are five layers enabled, and each contains a graphi c that is a solid rectangular block of a single color. the size and shape of each layer is different. the background color of the pane l is set to grey and layers have been placed such that they overlap each other. blend1 blend2 blend3 highest priority pixel next higher priority pixel higher priority pixel lowest priority pixel two-plane blending result three-plane blending result four-plane blending note: all blend stages use the blending settings defined for the upper pixel.
pxd20 microcontroller reference manual, rev. 1 11-82 freescale semiconductor preliminary?subject to change without notice figure 11-65 shows the individual s ource graphics and the case where no layer ha s any blending enabled. here, the highest priori ty layer (in this case layer 0) is fully visible. layer 1 is visibl e where layer 0 does not overlap it. layer 2 is visible wh ere layer 1 does not over lap it. layer 3 is overl apped by layers 0 and 1 and so is only partiall y visible. layer 4 is partially obscured by all of the other layers. no te that layer 4 is higher priority than the background color. figure 11-65. example of layer placement with no blending figure 11-66 shows the same layer configurat ion except that, in this case, th e layers have been made 50% transparent and the depth of the pixel blend is set to 3. the pixels in layer 0 are now blended with pixels in the underlying layers. in part icular, note region a where layer 0 is blended with layer 4 and the background color. this blending effect is repeated across all of the layers; however, note the pixels in region b. in this region the pixels from layer 0 are blended with those on layer 1 and layer 2; however, the pixels from layer 4 and the background color are not in cluded in this blend. this is because the dcu3 is configured to blend three layers onl y, and so the blend setting for laye r 2 is ignored for those pixels in region b.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-83 preliminary?subject to change without notice figure 11-66. example of layer placement with 3-layer blending all blending is performed using fu ll 8-bits-per-component colors. the dcu3 automatically performs a color promotion on source data that is stored in less than rgb888 color. 11.4.4.2 control descriptors the control descriptor for each layer consists of seven regist ers, and all 16 control de scriptors are identical except the two highest priority layers, which have additional control bits for the safety mode. the control descriptors may be written to at any time, and the value presen t in the registers at the start of the next frame refresh cycle defines the content of the panel for that frame. to avoid coherency issues, ensure all control descriptor cha nges are made before the prog_end bi t in the int_status register is asserted. 11.4.4.3 layer size and positioning the size of each layer is defined by register 1 in the control descriptor fo r the layer (ctrldescln_1, where n is the layer number). the re gister contains two b it fields, height and wi dth, which determine the size and shape of the layer. both fields are e xpressed in terms of the number of pixels in each dimension. the height bit field may take any va lue; however, it may not be useful to define a value larger than the height of the panel. the width field has a restriction on the value it ca n take, depending on the data format of the graphic specified by the layer. this field must always be an integer multiple of the number of pixels that are represented by a 32-bit word except in the special case of 1 bit per pixel where th e multiple is 16. the data format can range from 1 bit per pixel to 32 bits per pixe l and so there is a range of multiples from 1 to 32. figure 11-59 shows the multiples for the width bit field and some correct values.
pxd20 microcontroller reference manual, rev. 1 11-84 freescale semiconductor preliminary?subject to change without notice if the width bit field is se t to an invalid multiple, then the layer configuration is inva lid, the layer cannot be made visible, and an error flag is set in the layer parameter error register (parr_err). the position of each layer on the panel is defined by re gister 2 in the control descriptor for the layer (ctrldescln_2, where n is the layer number). the re gister contains two bit fields, posy and posx, which determine the location of the upper left pixel of the layer in the x and y axes. both fields are expressed in terms of the numbe r of pixels in each axis. there are no restrictions on layer placement. any layer can be placed and moved to any panel position. if a layer is placed so that pixels would appear beyond the dimensions of the panel, then the dcu3 displays the pixels on the panel and ignores the pixels off the panel. 11.4.4.4 graphics and data format the memory location of the graphic that is displayed on the layer is defined by register 3 in the control descriptor for the layer (ctrldes cln_3, where n is the layer number). this 32-bit value can contain the address of any 64-bit aligned memory lo cation in the memory map of the mcu. the format of the data that describes the graphic is de fined by the bpp bit field in register 4 in the control descriptor for the layer (ctrldescl n_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 11.4.4.3, layer si ze and positioning ). by choosing an appropriate format, it is possible to optim ize the memory required by the graphics in use. there are five formats where the rgb values of the pi xels are stored directly in the graphic. in these formats, the dcu3 treats the data as de scribing a true rgb color. the formats are: ? bgra8888, where the data defines 8-bit values for the red, gree n, blue, and alpha components of the image. this blends as argb, however, in th is format the order of the bytes is reversed compared to other formats. ? rgb888, where the data defines 8- bit values for the red, green, a nd blue components of the image. ? rgb565 where the data defines 5-bi t values for the red and blue components, and 6-bit values for the green component of the image. table 11-59. example of width multiples for different graphic data formats data format width multiples example values 1 bpp 16 16, 32, 48, 64, ? 2 bpp 16 16, 32, 48, 64, ? 4 bpp 8 8, 16, 24, 32, ? 8 bpp 4 4, 8, 12, 16, ? 16 bpp 2 2, 4, 6, 8, ? 24 bpp 4 (= 3 whole 32-bit words) 4, 8, 12, 16 32 bpp 1 1, 2, 3, 4, ? ycbcr422 4 4, 8, 12, 16, ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-85 preliminary?subject to change without notice ? argb1555 where the data de fines 5-bit values for the red, gree n, and blue components, and a 1-bit value for the alpha channel of the image. ? argb4444, where the data defines 4-bit values for the red, gree n, blue, and alpha components of the image. the three 16-bit formats (rgb 565, argb1555, and argb4444) are prom oted to full 8 bit per component format by shifting the bits left so that th e msb of the component in the 16-bit format becomes the msb of the 24/32 bpp (bit per pixel) format, and th e lsb is filled with the value of the msbs. for example, an rgb565 value of 10000:010000: 11011 becomes 10000100:01000001:11011110. an rgb4444 value of 1010:0011:1100:0101 b ecomes 10101010:00110011:11001100:01010101. an rgb1555 value of 1:10100:01000:11011 becomes 11111111:10100101:01000010:11011110. there are five indexed color formats (1/2/4/8 bpp & apal 8) where the data in the graphic does not define the rgb color to display. instead, th e data defines the entry in a color look-up table (clut) that contains a palette of argb colors. the maximu m number of colors in the clut is defined by the size of the data stored in the graphic. for 1 bpp graphics, there is a maximum of two colors in the clut. for 2 bpp, there is a maximum of four colors. fo r 4 bpp and 8 bpp data, the maximums are 16 and 256 colors, respectively. in apal8 mode(16 bpp), the upper 8 bits define the al pha component of the pixel and the lower 8 bits define the offset in the clut (the alpha component in the clut color is ignored). the address of the first value in th e clut is defined in the luoffs bi t field of register 4 and the clut is the ram block dedicated to th e dcu3 which is described in section 11.4.6, clut/tile ram . since the argb values stored in the clut are 32-bit argb, there is no need for furt her adjustment before blending. the dcu3 also supports graphics encoded using lu minance and chrominance fo rmat. this format is generically known as yuv and stor es the luminance (brightness, y) of a pixel separate from its chrominance (color information, u a nd v). this format is widely used by cameras and is supported by the pdi for direct video in as well as the dcu3 when st ored in memory for display on a layer. the specific implementation used by the dcu3 is more accurately described as ycbcr422 wh ich uses twice as many bits to describe the luminance as to describe the bl ue (cb) and red (cr) difference of the chrominance. the dcu3 takes these pixels and converts them to rgb format using equations configured using its lyr_luma_comp, lyr_chroma_red, lyr_ chroma_green, and lyr_chroma_blue registers. the ycbcr format specifies a common chroma setting for two pixels; however, it is possible to interpolate the chroma for the pixels rather than sett ing both to the same value. this feature is enabled by the lyr_intpol_en[en] field. due to the additional conversion step re quired, the dcu3 is able to blend a maximum of one layer encode d in ycbcr for each pixel. see section 11.8.1.6.3, pdi ycbcr mode and dcu3 ycbcr color format . there are four additional formats de fined by the bpp bit field. these conf igure the graphic in transparency mode and luminance mode (see section 11.4.4.6, transparen cy mode and blending , and section 11.4.4.7, luminance mode , respectively). there is a set storage format for each data format provided by the dcu 3. these formats can be seen in table 11-60 to table 11-70 .
pxd20 microcontroller reference manual, rev. 1 11-86 freescale semiconductor preliminary?subject to change without notice for 16 bpp, data expected is in the fo rm of rgb565, argb 1555, argb4444, or apal8. table 11-60. data layout for bgra8888 address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 b0 g0 r0 a0 b1 g1 r1 a1 0x08 b2 g2 r2 a2 b3 g3 r3 a3 table 11-61. data layout for ycbcr422 format 1 1 the ycbcr422 format encodes chroma information across two pi xels. therefore, the chroma values apply to the even pixel denoted in the table and its adjacent odd pixel. address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00cb0y0cr0y1cb2y2cr2y3 0x08cb4y4cr4y5cb6y6cr6y7 table 11-62. data layout for 24 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 b0 g0 r0 b1 g1 r1 b2 g2 0x08 r2 b3 g3 r3 b4 g4 r4 b5 table 11-63. generic data layout for 16 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel0[15:8] pixel0[7:0] pixel1[15:8] pixel1[7:0] pixel2[15:8] pixel2[7:0] pixel3[15:8] pixel3[7:0] 0x08 pixel4[15:8] pixel4[7:0] pixel5[15:8] pixel5[7:0] pixel6[15:8] pixel6[7:0] pixel7[15:8] pixel7[7:0] table 11-64. data layout for rgb565 format address offset [0:4] [5:10] [11:15] [16:20] [21:26] [27:31] 0x00 r0 g0 b0 r1 g1 b1 0x04 r2 g2 b2 r3 g3 b3 table 11-65. data layout for argb1555 format address offset [0] [1:5] [6:10] [11:15] [16] [17:21] [22:26] [27:31] 0x00 a0 r0 g0 b0 a1 r1 g1 b1 0x04 a2 r2 g2 b2 a3 r3 g3 b3
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-87 preliminary?subject to change without notice the dcu3 includes a flag that indicates when it ha s completed fetching graphics from memory for the current frame refresh. if required, this flag (dma_trans_finish in the int_status register) can be used to determine when changes can be made to the source graphic content. table 11-66. data layout for apal8 format address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 a0 offset 0 a1 offset 1 a2 offset 2 a3 offset 3 0x08 a4 offset 4 a5 offset 5 a6 offset 6 a7 offset 7 table 11-67. data layout for 8 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel0[0:7] pixel1[0:7] pixel2[0:7] pixel3[0: 7] pixel4[0:7] pixel5[0:7] pixel6[0:7] pixel7[0:7] 0x08 pixel8[0:7] pixel9[0:7] pixel10[0:7] pixel11[0:7] pixel12[0:7] pixel13[0:7] pixel14[0:7] pixel15[0:7] table 11-68. data layout for 4 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel1-pixel0 pixel3-pixel2 pixel5-pixel4 pixel7-pixel6 pixel9-pixel8 pixel11- pixel10 pixel13- pixel12 pixel15- pixel14 0x08 pixel17- pixel16 pixel19- pixel18 pixel21- pixel20 pixel23- pixel22 pixel25- pixel24 pixel27- pixel26 pixel29- pixel28 pixel31- pixel30 table 11-69. data layout for 2 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel3-pixel0 pixel7-pixel4 pixel11- pixel8 pixel15- pixel12 pixel19- pixel16 pixel23- pixel20 pixel27- pixel24 pixel31- pixel28 0x08 pixel35- pixel32 pixel39- pixel36 pixel43- pixel40 pixel47- pixel44 pixel51- pixel48 pixel55- pixel52 pixel59- pixel56 pixel63- pixel60 table 11-70. data layout for 1 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel7-pixel0 pixel15-pixel 8 pixel23-pixel 16 pixel31-pixel 24 pixel39-pixel 32 pixel47-pixel 40 pixel55-pixel 48 pixel63-pixel 56 0x08 pixel71-pixel 64 pixel79-pixel 72 pixel87-pixel 80 pixel95-pixel 88 pixel103-pix el96 pixel11-pixel 104 pixel119-pix el112 pixel127-pix el120
pxd20 microcontroller reference manual, rev. 1 11-88 freescale semiconductor preliminary?subject to change without notice 11.4.4.5 alpha and chroma-key blending the blending configuration of each layer is defined by the bb, ab, and tr ans bit fields in register 4 in the control descriptor for the layer (ctrldescln_4, wh ere n is the layer number). the pixels affected by the blending configuration can be further selected by registers 5 and 6 in the control descriptor (ctrldescln_4 and ctrldescln_5). depending on the priority and placement of the layer (see section 11.4.4.1, blending priority of layers ), these bit fields and registers define how pixels from different layers are blended together. the ab and bb bit fields define whether blending is active and whethe r the whole graphic or a selected portion is blended. registers 5 and 6 define the range of rgb colors that define the selected pixels. the trans bit field defines the transp arency of the selected pixels. the bb bit field defines wh ether the whole graphic, or only certain pixels, should be blended. when this bit is set, pixels that have an rg b value that falls into the range defi ned by registers 5 a nd 6 are considered to be selected and treated differentl y to the non-selected pixels in the graphic. this is a process known as chroma-keying since it is the color of the pixel that defines the selection. the selected pixels must be within the range defined by each color component of registers 5 and 6. see table 11-71 for examples of pixels that are selected and not selected when the given range is defined as 0x0080c0 to 0x0fb0ff. the ab bit field defines how any se lected and non-selected pixels are blended. by combining this control with the bb bit field it is possible to define 11 unique ways of blending the pixels on a layer dependent on the type of layer. depending on the configuration defined by the ab and bb bit fields, th e trans bit field combines the two pixels in every blend stage using the alpha value of the upper pi xel (which has the effect of making this pixel more or le ss transparent and revealing more or less of the lower pixel). the result of each blend stage is calculated for all three color components as shown in equation 11-3 . a = (bgpixel*(255 -alpha)) + (fgpixel * alpha) eqn. 11-3 the result of the calculation must then be divide d by 255 to normalize the result. this calculation is performed as follows: //first division output_val = a + (a >> 8) //rounding off first addition & division if (((a>>7) & 0x1) == 0x1) output_val ++ //second division with rounding table 11-71. example of how chroma-key range selects pixels source pixel red 00?0f green 80?b0 blue c0?ff comment 0x000000 p x x not selected 0x08c0c0 p x p not selected 0x08a0c0 p p p pixel is selected
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-89 preliminary?subject to change without notice output_val = output_val >>7; if ((output_val & 0x1) == 0x1)) output_val = output_val + 0x2; output_val = output_val >> 1; the blend can apply to pixels with no alpha channel (rgb) or with an alpha channel (argb) in different ways. table 11-72 defines how the settings of the bb and ab bit fiel ds affect the pixels in the layer; rgb formats are rgb565, and rgb888; argb formats are 1 bpp, 2 bpp, 4 bpp, 8 bpp, apal8, argb1555, argb4444, and bgra8888. pixels in ycbc r format are treated as rgb pixels for the purposes of the blend. table 11-72. blend options for bb and ab configurations case bb ab format function 1 0 00 rgb no blending, underlying pixels are obscured 2 1 00 rgb selected pixels are completely removed 3 0 01 rgb the value in trans becomes the alpha channel of all pixels on the layer 4 1 01 rgb the value in trans becomes the alpha channel of the selected pixels on the layer 5 0 10 rgb same as case 3 6 1 10 rgb selected pixels are completely removed and the value in trans becomes the alpha channel of the non-selected pixels on the layer 7 0 11 rgb reserved 8 1 11 rgb reserved 9 0 00 argb no blending, pixel alpha is ignored and underlying pixels are obscured 10 1 00 argb selected pixels are complete ly removed, pixel alpha is ignored 11 0 01 argb pixel alpha is used to blend layer with underlying pixels. value in trans is ignored. 12 1 01 argb uses the pixel alpha of the selected pixels only to blend layer with underlying pixels. value in trans is ignored. 13 0 10 argb the value in trans is multiplied with the pixel alpha value and the resultant alpha is used to blend all the pixels 14 1 10 argb selected pixels are completely removed, the value in trans is multiplied with the pixel alpha value and the resultant alpha is used to blend the non-selected pixels on the layer 15 0 11 argb reserved 16 1 11 argb reserved
pxd20 microcontroller reference manual, rev. 1 11-90 freescale semiconductor preliminary?subject to change without notice figure 11-67 to figure 11-75 illustrate the effect of the cases identified in table 11-72 . in all cases there is a single active layer and a white background color. figure 11-67. case 1 example (no blend) figure 11-68. case 2 example (remove selected pixels)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-91 preliminary?subject to change without notice figure 11-69. case 3 example (all pixels transparent) figure 11-70. case 4 example (selected pixels transparent)
pxd20 microcontroller reference manual, rev. 1 11-92 freescale semiconductor preliminary?subject to change without notice figure 11-71. case 6 example (selected pixels removed, others transparent) figure 11-72. case 9 example ( no blend, pixel alpha ignored)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-93 preliminary?subject to change without notice figure 11-73. case 10 example (selected pixels removed, pixel alpha ignored) figure 11-74. case 13 example (pixel and layer alpha used in blend)
pxd20 microcontroller reference manual, rev. 1 11-94 freescale semiconductor preliminary?subject to change without notice figure 11-75. case 14 example (selected pixels removed, pixel and layer alpha used in blend) 11.4.4.6 transparency mode and blending transparency mode is a special case for the graphic data format and is defined by the bpp bit field in register 4 in the control descriptor for the laye r (ctrldescln_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 11.4.4.3, layer size and positioning ). by choosing an appropriate format, it is possible to optimize the memory required by the graphics in use. in transparency mode, the source gr aphic does not contain a ny direct or indexed co lor information. instead, the graphic data represents the alpha channel of the graphic. the dcu3 creates the final graphic by pre-blending a foreground colo r and background color using the alpha va lue of each pixel. the result of this pre-blend can then be blended with pixels on other layers using the normal blending process. each layer has dedicated registers to contain the foreground and background colors for this mode. these are fgn_fcolor and fgn_bcolor, wher e n is the layer number. see figure 11-76 .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-95 preliminary?subject to change without notice figure 11-76. transparency mode description transparency mode is typically used when a graphi c must blend smoothly into the underlying layers, but where a rich color palette is not re quired. examples include te xt where this mode allo ws the text to blend smoothly with any background ? th is is known as anti-aliasing. there are two transparency modes available: 4 bpp a nd 8 bpp. the result of the pre-blend can be treated as an rgb888 graphic and ble nded in a similar way to prev iously described, or it can be treated as a special case of argb with only the foregr ound color visible in the final blend. table 11-73 describes the blend options for transparency mode. table 11-73. blend options for transparency mode case bb ab[1:0] mode function 1 0 00 transparency no blending, underlying pixels are obscured 2 1 00 transparency reserved 3 0 01 transparency the value in trans becomes the alpha channel of all pixels on the layer 4 1 01 transparency the value in trans becomes the alpha channel of the selected pixels on the layer 5 0 10 transparency same as case 3 6 1 10 transparency background color is igno red, selected pixels are completely removed, the value in trans is multiplied with the graphic data value (alpha) and the resultant alpha is used to blend the non-selected pixels on the layer 7 0 11 transparency reserved 8 1 11 transparency reserved 8 bpp 4 bpp layer data <<4 alpha a8 pre blend engine fc bc la argb8888 plane 1-4 forecolor rgb888 back color rgb888 layeralpha a8
pxd20 microcontroller reference manual, rev. 1 11-96 freescale semiconductor preliminary?subject to change without notice figure 11-77 ? figure 11-80 illustrate the effect of the cases identified in table 11-73 . in all cases there is a single active transparency layer and a white background color. figure 11-77. case 1 example (no blend) figure 11-78. case 3 example (all pixels transparent) transparency graphic foreground color background color panel
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-97 preliminary?subject to change without notice figure 11-79. case 4 example (selected pixels transparent) figure 11-80. case 6 example (only foreground color blended) 11.4.4.7 luminance mode luminance mode is a special case for the graphic da ta format and is defined by the bpp bit field in register 4 in the control descriptor for the laye r (ctrldescln_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 11.4.4.3, layer size and
pxd20 microcontroller reference manual, rev. 1 11-98 freescale semiconductor preliminary?subject to change without notice positioning ). by choosing an appropriate format, it is possible to optimize the memory required by the graphics in use. in luminance mode, the data in the source graphic does not contain any di rect or indexed color information or alpha information. the data values in a layer in luminance mode modify the values of the pixels on underlying layers only. there are two luminance modes available: 4 bpp and 8 bpp. in both cases, the data values behave as signed integers that are added to each component of the underlyi ng pixel. the 4 bpp mode is left-shifted to form a signed 8 bpp integer. the re sults of the addition are pr evented from overflowing, so that any result greater than 0xff is set to 0xff and any result less than 0x00 is set to 0x00. the result of a blend with a luminance layer is that the intensity of the underlyi ng pixel's color will be increased or decreased. in this way, luminance mode can be used to hi ghlight or dim pixels on the panel without having to modify the source graphic data. table 11-74 describes the effect of luminance blends on an underlying pixel. 11.4.4.8 tile mode tile mode is a special case for the la yer and is enabled by the tile_en bit field in register 4 in the control descriptor for the layer (ctrldescl n_4, where n is the layer number). in this mode the layer size register (ctrldescln_1, wh ere n is the layer number) defines the size of the layer; however, the size of the graphic is defined in control register 7 (c trldescln_7, where n is the layer number). the size of th e graphic must be less than or equal to the size of the laye r. when tile mode is enabled, the graphic is repeated horizontally and vert ically until it fills the whole layer. the horizontal size of the tile is defined by the ti le_hor_size bit field and is restricted to be a multiple of 16 pixels. the vertical size of the tile is de fined by the tile_ver_size bit field. the graphic data for the tile mode can be fetched ei ther from the system memo ry or from the internal clut/tile memory. this is defined by the data_sel bit field in register 4 in th e control descriptor for the layer. if the graphic is fetche d from clut/tile memory then it mu st be in the clut/tile ram direct color format. otherwise the gra phic can be in any previously described data format. see figure 11-81 for an example of a la yer in tile mode. when data_sel is set (to use clut/tile ram) the l uoffs bit-field defines th e start address of the tile graphic. tile mode is not permitted when rle mode is active on a layer. table 11-74. example of a blend with a luminance mode layer pixel value luminance value resultant pixel 0xff8040 0x40 0xffc080 0xff8040 0xc0 0x3f0000
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-99 preliminary?subject to change without notice figure 11-81. tile mode 11.4.5 hardware cursor in addition to the 16 layers, the dcu3 also provides a special layer intended for use as a cursor. this cursor operates in 1 bpp mode and includes it s own ram area to store the graphi c. the cursor may be placed at any location on the pane l and includes an automatic blink option. the hardware cu rsor is conf igured using a dedicated control descriptor. the size of the cursor is defined by register 1 in the control descriptor for the cursor (ctrldesccursor_1). the register contains two bit fields, height and width, which determine the size and shape of the layer. both fields are e xpressed in terms of the number of pixels in each dimension. the height is limited to a maximum of 256 pixels, and the total number of pixels cannot exceed the number of bits in the cursor ram (8192 bits). bits in the cursor ram that are 0 become transparent on the panel. bits that are 1 become fully opaque in the color defined in register 3 in the control descriptor for the cursor (ctrldesccursor_3). the default_cursor_color bit field is in rgb888 format. there are restrictions on the arrangement of bits in the curs or ram depending on how the height and width bit fields are configured. ? the rightmost bit in the cursor ram (bit 31) represents the leftmost pixel on the display. ? when the cursor size is less than 32 bits, each row of th e cursor is contained in a single 32-bit word of cursor ram. the other bits in each row must be filled with zeros. tile size - 64x64 pixels display size- 320 x 240 (qvga) layer size - 192 x 128 pixels
pxd20 microcontroller reference manual, rev. 1 11-100 freescale semiconductor preliminary?subject to change without notice ? when the cursor width is an intege r multiple of 32 bits, the pixels in each row roll from one word in the ram to the next one. the ri ghtmost bit in the first word in the ram is the t op leftmost pixel on the display. the leftmost bit in the word repres ents a pixel that is adjacent to the rightmost bit in the next word (in the same row). the leftmost pixel on the next row is the rightmost bit in the first word after n words that describe the first row. ? when the cursor is greater than 32 bits but not an integer multiple of 32, the pixels in each row roll from one word into the next one such that the ri ghtmost bit in the first word of the row is the leftmost bit on the display. in the fina l word of the row there are unused bits. the position of the cursor on the panel is defined by re gister 2 in the control descriptor for the cursor (ctrldesccursor _2). the register contains two bit fields, posy and posx, which determine the location of the upper left pixel of the cursor in the x and y axes. both fields are expressed in terms of the number of pixels in each axis. placing the cursor beyond the panel area is not allowed. the cursor can be configured to blink at a part icular rate when it is enabled. the en_blink, hwc_blink_on, and hwc_blink_off b it fields define the blink beha vior. these are in register 4 in the control descriptor for the cursor (ctr ldesccursor_4). en_blink enables blinking. the blinking time is based on the frame rate, and the on and off times are inde pendently configurable. hwc_blink_on configures the numbe r of frame refresh cycles for which the cursor is visible. hwc_blink_off configures the number of frame refresh cycles for which the cursor is not visible. for a frame refresh rate of 64 hz, the hwc_blink_ on and hwc_blink_off counters give a range of on/off times up to 4 seconds. the cursor is enabled by setting the cur_en bit field in register 3 in the control descriptor for the cursor (ctrldesccursor_3). if the dcu3 detects an invalid configuration in the cu rsor control descriptor, then the cursor configuration is invalid and it cannot be made visible. in addition, the error flag hwc_err is set in the layer parameter error register (parr_err). the cursor ram may be written at an y time when the tft lcd panel is not being driven with data. this means that the ram can be modified when the dcu3 is not enabled and duri ng the vertical blanking period. 11.4.6 clut/tile ram the internal tile memory and color look up table (c lut) memory share a commo n block of ram internal to the dcu3. color information in this ram is always stored as aligned 32-bit words where the most-significant byte is the alpha co mponent, the next byte contains the red component, the next the green component and the least significant byt e the blue component (0xaarrggbb). this memory block can be used to st ore either color look-up tables or gra phics for use as a tile on a layer. the content of the ram at a specific address is defined by the control de scriptor of a la yer. the luoffs bit field in the layer control descri ptor defines the starting address of the area, and the bpp and tile_en bit fields define what t ype of use th e ram area has.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-101 preliminary?subject to change without notice in figure 11-82 three areas of the ram are de fined for different purposes. area a is used by layer 1 as a clut for its 4 bpp graphic. area b is use by layer 5 as a store for its tile graphic. area c is used by layers 2, 7, and 9 as a clut for their 8 bpp graphics. figure 11-82. an example of use for the clut/tile ram the clut/tile ram is mapped in the dcu3 16k memory space from address 0x2000 to 0x3fff. this gives 2048 entries, which provides up to eight full cluts for 8 bpp layers. the clut/tile ram may be written at any time when the tft lcd panel is not being driven with data. this means that the ram can be modified when the dcu3 is not enabled and dur ing the vertical blanking period. 11.4.7 gamma correction the gamma table allows the user to define an arbi trary transfer function at the output of each color component. the function ( equation 11-4 ) is applied to each pixel after al l blending is complete and before the data is driven to the tft lcd panel. gamma correct ion is optional and can be used to adjust the color output values to match the gamut of a particular tft lcd pa nel, or to perform data inversion or data length reduction on each component. output_color_component = gamma_table[input_color_component] eqn. 11-4 the table is arranged as three separate memory blocks within the dcu3 memory map; one for each of the three color components. each memory block has one entry for every possible 8-bit value and the entries are stored at 32-bit a ligned addresses. this means that the upper 24 bits are not used while reading/writing the gamma memories. see figure 11-83 for details of the memory arrangement. 16 palette entries 64 pixel entries for 8 x 8 tile 256 palette entries clut/tile ram a b c
pxd20 microcontroller reference manual, rev. 1 11-102 freescale semiconductor preliminary?subject to change without notice figure 11-83. gamma correction table organization the gamma table can only be read or written when the dcu3 is not enabled or during the vertical blanking period. 11.4.8 temporal dithering this is a technique that allows th e emulation of a color resolution hi gher than the resolution supported by the display. it is done by changing th e intensity values over time sent to the display. the averaging done by the human eye gives the impression of the intensity of such alternating pixe ls as an interim value between the two supported intensity values . temporal dithering is enabled by the dcu_mode[dither_en] bit. the key features of the dithering block are ? temporal dithering increases the optically perceived depth of a limited tft display ? supports display with 5-8 bits resolution per color component ? independent dither control parameters per color component ? support for safety mode temporal dithering is enabled and controlled by th e en_dither, addb, addg, and addr bits in the dcu_mode register. the addx fields are each 2 bits wide and select how many bits to add to each color component. the typical sett ing is 8 minus the number of bits in each component required by the display. 0x0800 blended pixel gamma adjusted pixel 0x0c00 0x1000 red green blue
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-103 preliminary?subject to change without notice the random number generator (rng) provides a random number of up to 3 bits . the number of bits provided is selected by the values of each component's addx field. when pixels from a safety layer are encountered the rng output is forced to 0 which effectively disables the temporal dithering block and these pi xels are passed to the display unmodified. the add & clamp block adds the eight bit pixel value to the thr ee bit number generated by the rng. the result is then clamped to the range of 0..255. 11.4.9 special ddr mode special ddr mode is a special conf iguration that optimizes the use of an sdram memory by the dcu3 by forcing the dcu3 to fetch data in optimal chunks. in this special mode only the four highest priority layers (0:3) are available in the dcu3. this m ode is enabled using the dcu_mode[ddr_mode] bit. when this mode is enabled the dcu3 will fetch data in 32-byte chunks if the la yer is encoded in 8, 16 or 32 bpp formats, thus optimizing th e sdram throughput. any layers in 1, 2, 4 or 24 bpp formats will be fetched using normal access thus they will not be nefit from any optimizati on and may disrupt optimal access for any 8-, 16- and 32-bit formatted layers if both are in the sdram. therefore it is highly recommended to store any 1, 2, 4 or 24 bpp layers in non-sdram memory such as on-chip sram or flash. depending on the layer configurati on in use this mode may also be nefit other synchronous memory interfaces such as quadspi. this mode only permits operation in four-layer blend mode, therefore, the dcu_mode[blend_iter] field must be set to 4. 11.4.10 run length encoding (rle) mode rle mode is available on the two highest priority layers (layer 0 and laye r 1) and allows the dcu3 to load rle compressed data from memory and directly decode it for use on the panel. th e mode is enabled using the rle_en bit in the control de scriptor 4 register ctrldescln_4. this mode is only available when special ddr mode is enabled and can only be used on a single layer at a time. in addition the mode only supports 8 bpp, 16 bpp (rgb565, argb1555, argb4444, apal8), 24 bpp and 32 bpp bgra8888 formats. when enabled, the dcu3 fetches data in 3-byte c hunks and decompresses it before sending the decoded data to the normal dcu blend process. the dataflow for the rle decoded data is as shown in figure 11-84 .
pxd20 microcontroller reference manual, rev. 1 11-104 freescale semiconductor preliminary?subject to change without notice figure 11-84. rle decoding in dcu3 the decoded data is read by the input fifo once at l east 8 bytes are available in the txfifo.the size of rxfifo is 64x8 bits while the size of txfifo is 16x8 bits. if both layer 0 and layer 1 have rle_en set, then the error flag rle_err is asserted. 11.4.10.1 rle decoding scheme before enabling an rle encoded layer configure th e comp_imsize register with the size of the compressed image. the decoder exp ects to read comp_imsize bytes from the image and produce from that the number of pixels specified in the layer control descriptor 1 register. the format of rle encoded layers is as follows: ? the first data byte read at the image address (l ayer control descriptor 3) is a command byte (cmd[7:0]) ? the ms bit (cmd[7]) i ndicates if the following bytes are raw or compress ed pixels. one pixel can be 8-bit, 16-bit, 24-bit or 32 -bit wide, depending on the bpp bitfield in the layer control descriptor 4 register. ? the remaining 7 command bits (cmd[6:0]) specif y the number of raw or co mpressed pixels that follow the command byte. this count is offset by 1 such that a va lue of 0 means one pixel follows. ? for compressed pixels (cmd[7] = 1), only one pixel follows the command byte. this pixel is repeated count+1 times on the layer. the pixel size may be 8, 16, 24 and 32 bits. ? for raw pixels (cmd[7] = 0) count+1 pixels follow the comm and byte and these are included on the layer as is. the pixel si ze may be 8, 16, 24 and 32 bits. ? if there is more data to decode then a new command follows after cmd+ (1*{pixel width}) bytes. this encoding is repeated until the whole image is decoded. 11.5 timing, error and interrupt management the dcu3 can detect and raise status and error flag s when the status of the system changes and when configuration or operationa l errors are detected. dma rxfifo txfifo rle input fifo decoder
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-105 preliminary?subject to change without notice 11.5.1 synchronizing to panel frame rate since the dcu3 fetches data directly from memory i ndependently of the cpu, there is the possibility that changes to the dcu3 layer configurat ion or content can create incohere nt content on the panel. to help avoid this situa tion there are five timing control flags that define when the dcu3 recognizes and locks changes to its configuration. these can be used to ma nage changes to control descriptors, clut or tile memory, or source graphics and so avoid coherency problems on the pane l. all the timing flags are in the int_status register and can be used to generate interrupts from the dcu3. the dcu3 configuration is completely open during th e vertical blanking period and control descriptors and some other registers may also be programmed at any time. the co nfiguration that is present one hsync before the end of the verti cal blanking period is the configurat ion used by the dcu3 for the panel refresh phase. the vs_blank and ls_bf_vs flags give indication of the start of the vertical blanking period. the vs_blank flag is set at the begi nning of the vertical bl anking period. the ls_bf_vs flag is set a given number of horizontal lines before the start of the vert ical blanking period; the gi ven number of lines is defined by the ls_bf_vs bit fiel d in the threshold register. the prog_end flag indicates that the dcu3 has locked the contents of its confi guration registers for the new panel refresh period. no further ch anges are accepted to the dcu3 conf iguration after this flag is set (until the next vert ical blanking period). the dma_trans_finish flag indicates that the dc u3 has completed fetching all data from memory in the current panel refresh cycle. this normally preced es the vertical blanking period and indicates that it is possible to change the contents of a memory that contains graphics used by the dcu3. the vsync flag indicates that the dcu3 has begun the next panel refresh period. 11.5.2 managing the dcu3 fifos and dma activity the dcu3 fetches graphic data directly from inte rnal and external memory using a dedicated dma system and manages the output of data to the tft lcd panel such that the panel always receives the pixel information when expected. since the panel is sharing access to memo ry with the system dma and cpu it cannot depend on the require d data always being availa ble at all times. it ther efore uses input and output fifos to temporarily stor e incoming and outgoing data until required and thus reduces the opportunity for the panel to be starved of pixel data. the dcu3 manages the supply of graphic data to it s format conversion and blending stages using input fifos that are 256 ? 64 bits in size. the data that is driven to panel is managed usi ng an output fifo that is 128 pixels in size. see figure 11-1 for a diagram of the input fifo and output fifo operation in the dcu3. the input fifos are not accessible to the user but it is possible to set thresholds that control the dcu3 behavior when the fifos are becoming full or empt y and observe when the lower and higher thresholds are reached. this can help de tect and avert situations where the dcu3 is running out of data to send to the panel.
pxd20 microcontroller reference manual, rev. 1 11-106 freescale semiconductor preliminary?subject to change without notice the fifo thresholds are set in the threshold_in put_buf_1/2 registers. the upper thresholds are set by the inp_buf_pm_hi bit fields (where m is the position of the pixel in the blend stack) and these set the point at which the dcu3 pa uses fetching data from memory. the maximum size of any dma burst is fixed to 16 pixels and so is dependent on the graphic encoding. the lower thresholds are set by the inp_buf_pm_lo bit fields. each of the four input fi fos has two flags that indicate whether the fifo has reache d its upper or lower threshold. the pm_fifo_hi_flag flags (where m is the position of the pixel in the blend stack) indicates that the input fifo has reached the upper threshold. the pm_fifo_lo_flag indicates that the input fifo has less data than its low threshold. depending on when the low threshold is reached this may indicate a number of scenarios ? the expected graphical data is not available for the dcu3 to load ? the dcu3 is reaching the end of a frame and does not need to load any more data ? the blend stack does not need pixels of this priority in the situation where the data is not available to the dcu3 then there ma y or may not be an impact to the data visible on the panel. in the situation where the output fifo is fu ll then it is possible for the dcu3 to accept a delay before it require s to use the incoming data. the output fifo is not accessible to the user but it is possible to set thresholds that control the dcu3 behavior when the fifo is becoming full or empty and obser ve the lower threshold. this can help detect and avert situations where the dcu3 is running out of data to send to the panel. the buffer thresholds are set in the threshol d register. the upper threshold is set by the out_buf_high bit field and this indicat es that sufficient data exists in the output buffer and processing should stop until the dcu3 uses some of the values in the fifo. if this value is set too low then the possibility of the dcu3 r unning out of data to drive the panel is increased. the lower threshold is set by the out_buf_low bit field. when the output fifo has emptied below its low threshold (out_buf_low bit field) it sets the undrun bit. in an under run situation there may or may not be an im pact to the data visible on the panel. the impact depends on whether the dc u3 is reaching the end of a fram e and how close to running out the threshold is set. the best guide to indicate whether the dcu3 is able to supply the required pixel information to the panel is the output buffer. if the output is indicating that it is r unning out of data then the input fifos may help identify the areas of memory that ar e restricting the supply of data. usi ng these indicators can help to set the dcu3 thresholds and ensure that the data throughput on the mcu is balanced correctly for all master devices. finally, note that the number of dcu3 clock cycles to fetch and blend each pixel increases with the depth of the blend stack. however, the time taken to proc ess the pixel data is fixed by the timing requirements of the panel. therefore, for full performance across all color encodings the ratio between the dcu3 clock and the pixel clock must increase as the blend stack depth increases: ? for two-pixel blending, the minimum dcu cl ock is the same as the tft pixel clock. ? for three-pixel blending, the minimum dcu3 clock must be twice the tft pixel clock. ? for four-pixel blending, the minimum dcu3 clock must be twice the tft pixel clock.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-107 preliminary?subject to change without notice 11.5.3 error detection the dcu3 asserts error flags when errors are detected in its configuration or wh en the user attempts to modify the configuration at an invalid point in the pa nel refresh period or when it is unable to access the required source data. the error flags may raise an interru pt if enabled to do so by the related mask bit in the corresponding mask register. error flags are stored in the parr_er r_status and int_status registers. errors in the dcu3 configuration are collecte d in the parr_err_status register. the flags ln_parr_err (where n is the layer number) indicate an error in the c onfiguration of the layer which can be either an invalid tile mode size or a layer with a horizont al dimension that is sm aller than the minimum size defined by the layer encoding (see section 11.4.4.3, layer size and positioning ). the disp_err flag indicates that the vsync and hsync pulse widths are configured to the invalid value of 0. the hwc_err flag indicates that the hardwa re cursor is either larger than the available memory or is placed in an off-panel position. the sig_err indicates that the signature calculation specifies an area that extends beyond the panel size. the rle_err indicates that more than one layer has rle enabled. reads of clut/tile ram during the period when the tft lcd panel is being updated do not return the clut/tile ram content. errors caused when the dcu3 is unable to access its required sour ce data are collected in the int_status register. these errors are indicate d by the undrun flag and the pm_fifo_lo_flag flags (where m is the position in the blend stack) 11.5.4 interrupt generation the dcu3 generates interrupt through four lines that are controlled by the contents of six registers: ? int_status ? int_mask ? pdi_status ? mask_pdi_status ? parr_err status ? mask_parr_err status there are four interrupt status lines de fined.these lines are grouped as follows ? timing based interrupts: ?vsync ?ls_bf_vs ? vs_blank ?prog_end ? dma_trans_finish ? functional interrupts: ? undrun ? crc_ready
pxd20 microcontroller reference manual, rev. 1 11-108 freescale semiconductor preliminary?subject to change without notice ? crc_overflow ? p1_fifo_hi_flag ? p1_fifo_lo_flag ? p2_fifo_lo_flag ? p2_fifo_hi_flag ? p3_fifo_hi_flag ? p3_fifo_low_flag ? p4_fifo_hi_flag ? p4_fifo_low_flag ?ipm_error ? parameter error interrupts ?layer error ? signature calculator error ? display error ? hwc_error ? rle error ? pdi-related interrupts (pdi_int) ? this includes pdi related interrupts. see section 11.8.1.8, pdi-related interrupts, for a description. when any interrupt occurs, the host can identify wh ich type of interrupt has occurred by reading the interrupt status register /pdi status register/par r_err status register. 11.6 register protection there is a customized register prot ection scheme on the dcu3 that is different to the protection scheme implemented elsewhere on the mcu. th e scheme provides a mechanism to protect certain registers in the dcu3 from being written. 11.6.1 operation of scheme the register protection scheme provides a two-step protection scheme for the protected register. firstly, each register has an associat ed soft lock bit (slb) that prevents further writes to the register when it is set. each slb has a correspondi ng write enable (wen) bit that must be set in the same write operation as the slb. the slb can be set or cl eared by writing a '1' or '0 ' to it while its wen bi t is set. the slb bits are in the soft lock registers l0 and l1, di sp_size, hsync/vsync_para, pol, l0_transp and l1_transp registers. secondly, there is a hard lock bit (hlb) in the globa l protection register which prevents all changes to soft lock bits. the hlb can only be cleared by a system reset.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-109 preliminary?subject to change without notice if a write is made to a register whose slb is set th en a transfer error occurs that generates an ivor1 exception on the cpu. similarly if the hlb is set then any write to the slb registers causes a transfer error. 11.6.2 list of protected registers the register protection scheme a pplies to the following registers: ? all layer 0 control descriptor s ctrldescl0_1 to ctrldescl0_7 ? all layer 1 control descriptor s ctrldescl1_1 to ctrldescl1_7 ? layer 0 foreground and background register s for transparency mode fg0_fcolor and fg0_bcolor ? layer 1 foreground and background register s for transparency mode fg1_fcolor and fg1_bcolor ? all control descriptors & tran sparency registers for layer1 ? disp_size ? hsync_para ? vsync_para ? syn_pol 11.7 safety mode safety layers are used in a multi-layer dcu3 envir onment for the purpose of guar anteeing that the content is driven to the display re gardless of the setting of remaining layers and the pi xel manipulation algorithms of the dcu3. features such as this are a requirement from qualification institutes to be able to reach a safety level of sil2 or asilb. th e dcu3 has two safety layers (layer 0 and layer 1) which also have the highest priority. when safety m ode is active the safety layers can use chroma keying for complex area description, however alpha blending for the layer is always ignore d. additionally, if a layer has safety mode enabled then a layer format of 32 bpp or luminance is not allowe d. using these formats causes the layer to be disabled. safety mode is implemented using a signature calc ulator module implemented inside the dcu3 that calculates two signatures (pixel valu e and pixel position) for a predefined area of the frame. the user makes layer 0 and/or layer 1 active as a safety layer, defines the window/area of the pixels for which the signature is to be calculated, and enables safety m ode. when enabled, the signature calculator starts to calculate the signature after the first pixel in the sel ected area is available and after the start of the next frame (vsync). it is also possible to calc ulate the signature value for all pixels if dcu_mode[tag_en] = 0. as the pixels in the selected area become availa ble they are "tagged" by the dcu3, except for those removed by chroma-keying. these tags id entify the pixels to be included in the signature calculation. the signature calculation itself is an industry-standard crc. the dcu3 asserts the crc_ready flag at the end of any frame which has safety mode enabled. this can be used to indicate the complete d signature calculations for each full frame of pixels after the mode is enabled. the completed signature can then be compared against a pre-calculated value with any difference
pxd20 microcontroller reference manual, rev. 1 11-110 freescale semiconductor preliminary?subject to change without notice indicating that the pixels displaye d did not match what was expecte d. the signature calculator then continues to calculate the crc for the next frame. if the crc_ready flag is not processed within one frame time period, then the crc_over flow interrupt is issu ed and the latest cal culation overwrites the previous value. since the crc_ready flag is set at the end of any fra me with safety mode enabled, it is possible that a full frame has not yet been comple ted and therefore no signature calculation exists for the frame that set the flag. if the user has set the neg bit for th e dcu3 which indicates th at the pixels fed to th e display are inverted, then the value crc is calculated on non-inverted va lues. the position crc, however, remains as is. normal arbitration takes pl ace only when a pixel has content on layer 0 and layer 1 but where safety mode is enabled in layer 1. the polynomial used for crc calculation is (x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1) eqn. 11-5 for the value crc, the 24-bit value of each output pixel (after decoding) is sent to the polynomial. for the position crc, the value sent is (pixel_delta_y * display.delta_x) + (pixel_delta_x + 1) eqn. 11-6 figure 11-85. safety mode block diagram format converter blending /chroma key gamma correc. display drive display fgplane bgplane 1-32 bpp 1-32 bpp 24 bpp 24 bpp 24 bpp 24 bpp format converter gamma correction display drive display fgplane fg1plane 1-24 bpp 1-24 bpp 25 bpp 25 bpp 25 bpp 24 bpp signature calculator normal mode operation safety mode optional chroma key optional sync tag 25 bpp = 24 bpp rgb + 1 bit safety pixel tag optional external signature checker result interrupt calculator fg2plane bgplane 1-24 bpp 1-24 bpp
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-111 preliminary?subject to change without notice 11.7.1 crc area description 11.7.1.1 configuring the crc calculation 1. crc_val and crc_pos are calculated when safety mode is enabled using dcu_mode[sig_en]. 2. the crc can be calculated for part of the panel as shown in figure 11-86 . the green portion on the panel is identified using the sign_calc_1 and sign_calc _2 registers which defined the size of the area and the location of the area respectively. if sign_c alc_1 and sign_calc_2 are configured appropriately this calculation will cover the whole panel. figure 11-86. safety mode enabled for part of the screen 3. the crc can be calculated exclusively for la yers 0 and 1 by setting dcu_mode[tag_en] and enabling the safety_en bit in contro l descriptor 4 of each of the la yers. in this configuration the crc is calculated using values from the layers only where they inters ect the area of interest defined in sign_calc_1 and sig_calc_2. an ex ample is shown (in dark pink) in figure 11-87 . lenx startx starty area of concern leny note: enable to crc is sent for the green portion
pxd20 microcontroller reference manual, rev. 1 11-112 freescale semiconductor preliminary?subject to change without notice figure 11-87. safety mode with dcu_mode[tag_en] = 1 11.7.2 summary of operation the area included in the crc calculation is summarized in table 11-75 . the initial value on all crc calculations is 0x00000000. table 11-75. supported area area dcu_mode[tag_en] note full 0 sign_calc_2[sig_hor_pos] = 0 sign_calc_2[sig_ver_pos] = 0 sign_calc_1[sig_hor_size] = panel width sign_calc_1[sig_ver_size] = panel height part 0 the sign_calc parameter s have values other than those mentioned above ? see figure 11-86 safety layer (layer 0 and 1 only) 1 the included portion of the safety layers depends on: ? the portion lying within the area defined by sign_calc_1 and sign_calc_2 ? the pixels removed by chroma keying functionality area of interest crc layer (intersection of both area of interest and safety layer) safety layers/tag note: enable to crc is sent for the dark pink portion
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-113 preliminary?subject to change without notice 11.8 parallel data interface (camera interface) 11.8.1 pdi interface description 11.8.1.1 introduction this block extracts the timing and pixe l information from an external vi deo source and passes it to the dcu3 block to synchronize with the timing and di splay the pixel information on the tft lcd screen. the bgnd layer in the dcu3 is replaced by the incoming video stream. the pdi requires that the incoming video stream matc h the resolution and timing at which the dcu3 is driving the tft lcd panel and the inco ming stream must not be interlaced. the pdi can also be configured in slave mode in which case it ignores the pixel information from the external video source and only passes the timing inform ation to the dcu3 to s ynchronize with. in this instance the dcu3 will continue to operate as normal (the bgnd layer will not be altered) but will use the timing from the pdi. the pdi shares configuration registers with the dcu3. 11.8.1.2 pdi interaction with other modules figure 11-88. pdi interacting directly with the external sensor in figure 11-88 , the pdi accepts data and timing directly from the external video source. the external device must output the video in a digital format supported by the pdi. video source video source fed directly to pdi other layer data to mix with pdi pdi dcu3 display driver/ screen data being sent at pdi rate pdi output in format required by dcu3 pxd20 (pdi becomes bg layer)
pxd20 microcontroller reference manual, rev. 1 11-114 freescale semiconductor preliminary?subject to change without notice figure 11-89. pdi interacting with fpga in between in the case shown in figure 11-89 , the video stream is sent to a decoder or an fpga which alters the incoming stream to a format which is compatible w ith the pdi. a decoder/fpga is required if a video source with an analog output format (e.g. ntsc/pal) is used . the decoder should perform analog-to-digital conversion on the stream and ensure the timing matc h that of the dcu3. the incoming stream may also need to be de-interlaced. the pdi is compatible wi th various input formats: ? normal mode: the pdi clock freque ncy must be equal to pixel cl ock frequency required by the tft display driver ? narrow mode: the pdi clock frequency is double the desired pixel clock frequency. ? external synchronization: the ti ming signals (hsync, vsync, a nd de) each have a dedicated input pin. (de is optional) ? internal synchronization: the tim ing signals (hsync, vsync and de) are embedded in the data stream, as such only the data and pclk inputs are required. (see section 11.8.1.4, itu-r bt.656 sync information extraction. ) before the dcu3 locks onto the pdi timing signals it will run on the internal dcu3 clock. after lock has been achieved, the dcu3 will switch to the clock from the pdi stream and the this is then used to send data and timing signal to tft/lcd display driver. in all cases, the resolution of the incoming stream and the hsync and vsync frequency must be the same as that for tft screen. all the horizontal parameters (front po rch width, back porch width, pulse width) and vertical parame ters (front porch width, back porch widt h, pulse width) must be the same as that of tft screen. when pdi is the background layer, no ot her layer can be a bac kground layer for that pa rticular frame. only one background layer is possible i.e. pdi layer when pdi is enabled. sensor input fed directly to decoder/fpga, other layer data to mix with pdi pdi dcu3 display driver/ screen pdi output in format required by dcu3 video sensor/ camera output decoder/ which converts the data to a format required by the pdi. data being sent at pdi rate fpga pxd20 (pdi becomes bg layer)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-115 preliminary?subject to change without notice 11.8.1.3 features the pdi supports the following: ? rgb565, rgb666, 8 bit monochr ome format,ycbcr422 mode ? max input frequency of 32 mh z in 8/16/18 normal mode input ? max input frequency of 64 mhz in 8 bit muxed (narrow) mode ? external synchronization using pdi_ hsync, pdi_vsync, and pdi_clk ? external synchronization us ing pdi_hsync, pdi_vsync, pdi_pclk, and pdi_de ? internal synchronization usi ng pdi[17:0] and pdi_pclk. it is supported for rgb565 and ycbcr422 muxed mode only 11.8.1.4 itu-r bt.656 sync information extraction according to itu-r bt.656 recommendation, the incoming digital video will have a pdi_clk signal and 8 data bits. the data bits can cont ain both the video data and the ti ming reference signals (vsync and hsync). the timing signals are encoded at th e start and end of each line by ti ming reference codes known as start of active video (sav) and end of active video (eav ). the sav and eav codes are identified by their preamble of three bytes (0xff,0x00,0x00) . due to this, neither 0x00 or 0xff can be used during the active video data. the preamble is followed by the xy status word which cont ains a field bit (f), a vertical blanking bit (v) and horizontal blanking bit (h) a nd four protection bits for si ngle bit error correction and detection. the h bit is set to 1 to denote an eav ? that is the end of a line, and the beginning of the horizontal blanking period. the v bit is set to 1 to denote the beginning of the ve rtical blanking pe riod. the f bit is used for interlaced video to denote if the forthcoming line is odd or even. table 11-76. supported rgb format and sync format rgb format data input bus 8-bit monochrome 8 bit rgb565 16 bit rgb666 18 bit rgb565 muxed (uses narrow mode) 8 bit ycbcr (uses narrow mode) 8 bit sync format pin used internal sync (valid only for rgb565and ycbcr in narrow mode) pclk external sync pdi_hsync, pdi_vsync, pdi_pclk external sync (with data en) pdi_hsync, pdi_vsync, pdi_pclk, pdi_de
pxd20 microcontroller reference manual, rev. 1 11-116 freescale semiconductor preliminary?subject to change without notice the remaining 4 bits contains make up the protection bits for single bit error correction and detection. it should be noted that f and v fields are only allowe d to change as part of eav sequences i.e during transitions from h=0 to h=1. an entire line of video comprise s active video + horizontal blanki ng (from the start of the eav code until the end of the sav code) and vert ical blanking (the space where v = 1). note this device supports only 8-bit, non-in terlaced, video. the field (f) value is ignored. figure 11-90. itu-r bt.656 8 bit parallel data format for 525 video system figure 11-91. control byte sequence for 8-bit/10-bit video the bit definitions for the st atus word xy are shown in table 11-77 . table 11-77. status word definitions bit definition f 0 for field 0 1 for field 1 v 1 during vertical blanking period 0 when not in vertical blanking h0 at sav 1 at eav f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y video data active eav code sav code blanking h control signal start of digital line start of digital active line next line data bit firstword secondword thirdword fourthword (ff) (00) (00) (xy) d7(msb) d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 f v h p3 p2 p1 p0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-117 preliminary?subject to change without notice figure 11-92. pdi input data mode figure 11-92 represents the scenario in which data from an itu-r bt.656 compliant video source is fed into the pdi interface. the incoming data includes code s that trigger the start a nd end of the active video and blanking fields. an activity det ector checks for the transitions on the pdi bus. it samples the values on the pdi bus and once it has detected valid activity, se ts a flag in the status register and can optionally trigger an interrupt. the pdi interface has a state machine which extracts the control information from the video data. the machine checks the video data for the preamble field (0xff,0x00,0x00) and then depending on the status bits xy decides if it has received a valid control signal. 11.8.1.5 normal and narrow mode in normal mode, the pdi supports a maximum input frequency of 32 mhz. in narrow mode, the pdi supports a maximum input frequency of 64 mhz. p3 v xor h p2 f xor h p1 f xor v p0 f xor v xor h table 11-77. status word definitions (continued) bit definition video source with embedded itu656 timing clk embedded control pdi_clk activity detector ready data with pdi interface logic
pxd20 microcontroller reference manual, rev. 1 11-118 freescale semiconductor preliminary?subject to change without notice figure 11-93. data transfer in normal and narrow mode the byte transferred first (msb or lsb) depends on the configuration re gister as shown in figure 11-93 .this does not affect the sync preamble sequence in case internal sync mode. on this device, the incoming rgb data is mapped onto the pdi pins as described in table 11-78 . table 11-78. mapping of rgb data onto pdi pins mode mapping normal (full 18-bit pdi interface) pdi[17:12] = dcu3_r[5:0] pdi[11:6] = dcu3_g[5:0] pdi[5:0] = dcu3_b[5:0] normal (rgb565 16-bit pdi interface) pdi[15:11] = dcu3_r[4:0] pdi[[10:5] = dcu3_g[5:0] pdi[4:0] = dcu3_b[4:0] narrow (8-bit pdi interface) rgb565: in first clock cycle, pdi[7:0] = { dcu3_r[4:0], dcu3_g[5:3] } in second clock cycle, pdi[7:0] = { dcu3_g[2:0], dcu3_b[4:0] } ycbcr: in first clock cycle, pdi[7:0] = { dcu3_cb[7:0] } in second clock cycle, pd i[7:0] = { dcu3_y0[7:0] } in third clock cycle, pdi[7:0] = { dcu3_cr[7:0] } in forth clock cycle, pdi[7:0] = { dcu3_y1[7:0] } 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0b 0x0a 0x0d 0x0c 0x0f 0x0e 0x0100 0x0302 0x0504 0x0706 0x0908 0x0b0a 0x0d0c 0x0f0e pdi_data [15:0] rgb565 normal mode (pdi_clk = 64 mhz max) lsb pdi_data [7:0] pdi_clk pdi_clk rgb565 narrow mode (pdi_clk = 64 mhz max) lsb transferred first rgb565 narrow mode (pdi_clk = 64 mhz max) msb transferred first pdi_data [7:0] 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0b 0x0a 0x0d 0x0c 0x0f 0x0e
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-119 preliminary?subject to change without notice 11.8.1.6 modes of operation based on sync extraction 11.8.1.6.1 pdi input dat a (external sync mode) in external sync mode the timing signals (hsync, vsync and, optionall y, date enable) are provided to the pdi input timing pins by the external video source. external sync mode can be used in both normal m ode and 8-bit narrow mode , but cannot be used in conjunction with the ycbcr data format. in the instance that external sync and narrow mode is selected, the external signals are used, and any timing information (eav/sav) em bedded in the data stream is ignored. as in figure 11-95 , pdi data enable (pdi_de) should be low during vsync and hsync pulse, vsync front porch (fp_v) and back porch (bp_v), hsync front porch (fp_h) and back porch (b p_h). this is valid for data enable mode when the pdi_de_en bit is set in the dc u_mode register (i.e. mode with hsync, vsync, pdi_de and pdi_pclk as pin signals). pulse width, front and back porch va lues should be picked from those programmed in dcu3 registers. in order to achieve lock, it must have same value as that of tft screen. front porch and back porch value can be zero. pulse width and tft sc reen size parameters ca nnot be zero. in case th ey are programmed as zero, it might lead to malfunctioni ng of the validation state machine. as in figure 11-94 hsync must occur during the vsync a nd vertical blanking period. the time between 2 hsync should be the same during vsync and vertical blanki ng as during the active line period. as in figure 11-94 the positive edge of hsync and vsync should be aligned. as in figure 11-94 the positive edge of the hsyn c and start of the vertical fr ont/back porch should be aligned. the polarity of hsync and vsync is selectable. figure 11-94. relationship between hsync an d vsync in external synchronization pdi_hsync pdi_vsync end of last active line posedge of vsync and hsync are aligned start of first active line fp_v (vertical front porch) value = 2 (no of hsync) value = 2 (no of hsync) value = 2 (no of hsync) pw_v (vertical pulse width) bp_v (vertical back porch) vertical blanking period
pxd20 microcontroller reference manual, rev. 1 11-120 freescale semiconductor preliminary?subject to change without notice figure 11-95. occurrence of hsync and vsync and pdi_de for the entire frame 11.8.1.6.2 pdi input data (int ernal sync extraction mode) in internal sync mode the timing pa rameters (horizontal and vertical bl anking) are encoded into the data stream. internal sync mode can only be used in 8-bit narrow mode. in figure 11-96 , xy is used to decode the vert ical and horizontal blanking period. table 11-79. xyh value bit value description 7 1'b1 always 1'b1. this is checked while decoding sync preamble 6 f not considered in the state machine logic 5 v 1'b1 during vertical blanking 1'b0 elsewhere 4 h 1'b0 for start of active video 1'b1 for end of active video invalid data 1 2 3 4 delta_x invalid data pdi_pclk pdi[17:0] pdi_hsync pdi_de data enable high during active data bp_h fp_h data enable in the horizontal resolution fp_h and bp_h is programmable through register pdi_pclk invalid data 1 2 3 4 invalid data pdi[17:0] pdi_vsync bp_v fp_v pdi_de ?? 1 delta_x ?? 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-121 preliminary?subject to change without notice figure 11-96. location of sync preamble in narrow mode sync preamble would come continuously for 4 clock cycles as shown in figure 11-96 . it does not depend upon which byte is coming first in data (msb or lsb). sync extraction is done using pdi[7:0] to identify the horizontal and vertical blanki ng period using h and v field of the 'xyh' data as mentioned in table 11-79 . itu 656 sync preamble pattern (ffh 00h 00h) has to be masked out in the rgb and ycbcr data. the data stream must not include ffh 00h 00h as the valid pixel data to avoid malfunction by the validation state machine. horizontal blanking period must continue during the vertical bl anking period. the gap between 2 horizontal blanking periods should be the same during vertical blanking period as during li ne active. all vertical and horizontal para meter values are validated against the dcu3 registers programmed by the user. polarity of hsync and vsync are selectable. horizont al blanking and vertical blanking must be aligned as shown in figure 11-97 . during blanking period the input stre am must be a 80h 10h 80h 10h sequence. this sequence must be present during both horizont al (line) blanking and vertical (frame) blanking. as the pdi does not support interlaced video, the fr aming bit (f field in xyh) will be ignored during timing extraction. narrow mode is compatible with rgb565 and ycbcr422 muxed modes. each header contains an ecc value, which the pdi will check. the pdi is capable of detecting an error but not correcting it. as with external sync mode, the value of front and back porch can be zero but the pulse width and tft screen parameter cannot be zero. 3 2 1 0 p3 p2 p1 p0 protection bits (used to detect ecc errors). it would not be used for bit correction. table 11-79. xyh value (continued) bit value description ff 00 00 xy pdi_data [7:0] pdi_clk 16-bit rgb (narrow mode) with in ternal sync (representation ?? note: preamble sequence is independent of data sequence
pxd20 microcontroller reference manual, rev. 1 11-122 freescale semiconductor preliminary?subject to change without notice figure 11-97. relationship between hbla nk and vblank in internal sync 11.8.1.6.3 pdi ycbcr mode and dcu3 ycbcr color format the dcu3 can process inco ming data from the pdi a nd from memory in ycbcr422 format. both sources use the same rgb conversion and inte rpolation equations, howev er, the coefficients for the equations and enable for the interpolation are independently controlled. in ycbcr mode, the pdi extracts the itu656 sync (ff-00-00) and sends the vi deo to the processing functions. the first processing function converts the 422 stream to a 444 stream, by providing interpolation on the chroma components of the stream depending on pdi_interpol _en bit. the se cond processing function converts the st ream to rgb888/rgb565. the dcu3 can also select ycbcr fo rmat in the bpp field of layer de scriptor 4, which allows the same process to be applied to values stored in memory ra ther than brought in from the pdi. interpolation is controlled for the layers using the lyr_intpol_en register. the rgb pixel value is computed using following equations: eqn. 11-7 eqn. 11-8 eqn. 11-9 note that the first multiplication (i.e (y-16) *ycoeff) is unsigned, the two others are signed. line 1 frame of image data line 480 frame blanking period sav 80 eav 9d eav b6 sav ab line blanking period note: the sav and eav bytes are included as part of the blanking period. red y16 ? ?? yred ? 512 ------------------------------------ - cr 128 ? ?? crred 512 ----------------------------------------- cb 128 ? ?? cbred 512 ------------------------------------------- ++ = green y16 ? ?? ygreen ? 512 -------------------------------------------- - cr 128 ? ?? crgreen 512 ----------------------------------------------- - cb 128 ? ?? cbgreen 512 ------------------------------------------------- - ++ = blue y16 ? ?? yblue ? 512 --------------------------------------- - cr 128 ? ?? crblue 512 -------------------------------------------- cb 128 ? ?? cbblue 512 ---------------------------------------------- ++ =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-123 preliminary?subject to change without notice the register values after reset are as follows: yred = 10?h254 (596/512 = 1.16) crred = 11?h331 (817/512 = 1.6) cbred = 12?h000 ygreen = 10?h254(596/512 = 1.16) crgreen = 11?h660(-416/512 = -0.812) cbgreen = 12?hf38(-200/512 = -0.39) yblue = 10?h254(596/512 = 1.16) crblue = 11?h000 cbblue = 12?h409(1033/512 = 2.017) figure 11-98. ycbc r timing diagram figure 11-99. ycbcr interpolation calculation 11.8.1.7 mode of operation depending on pdi[17:0] pdi supports following modes (other than the slave mode): pdi_data [7:0] pdi_clk cb 0 y 0 cr 0 y 1 y 2 y 4 y 5 y 6 cb 1 y 3 cb 2 cb 3 cr 1 cr 2 cr 3 y 0 y 1 y 2 y 4 y 3 cb 0 ? cb 1 ? cb 2 ? cb 3 ? cb 4 ? cr 0 ? cr 1 ? cr 2 ? cr 3 ? cr 4 ? y_data[7:0] cb_data[7:0] cr_data[7:0] rgb888 ycbcr_pulse rgb_valid cb n ' = cb n/2 (cb (n-1)/2 ' + cb (n+1)/2 )/2 cr n ' = cr n/2 (cr (n-1)/2 ' + cr (n+1)/2 )/2 for even n for even n for odd n for odd n
pxd20 microcontroller reference manual, rev. 1 11-124 freescale semiconductor preliminary?subject to change without notice ? 8-bit monochrome (8-bit input data, each pixel info is coming in 1 clocks) ? 16-bit ? rgb565 (16-bit input data, eac h pixel info is coming in 1 clocks) ? 18-bit ? rgb666 (18-bit input data, eac h pixel info is coming in 1 clocks) ? 16-bit ? rgb565 (8-bit input data, eac h pixel info is coming in 2 clocks) ? 16-bit ? ycbcr422 (8-bit input data, info for 2 co-sited pixels coming in 4 clocks) data info extraction is given in table 11-80 . the 8-bit monochrome image is equivalent to 8-bi t grayscale images. for c onverting 8-bit monochrome data to rgb data, each of the r/g/b components will have a value equal to the 8-bit monochrome value. rgb extraction starts when pdi is enabled (from the next falling edge of va lidated vertical blanking period) 11.8.1.8 pdi-related interrupts pdi can be configured to trigger an interrupt when synchronization is achieved i.e. it receives the prespecified numbers of frames without error. pdi can also give an inte rrupt when synchron ization is lost i.e. it receives any error in frame there after. this interrupt is raised when hsync/vsync is lost. the pdi can also trigger an interrupt if there is either a one bit or a multiple bit error in the ecc value during the extraction of the preamble in internal synchronization mode. blanking sequence error interrupt can be triggered in case 80h 10h is not found in vertical and line blanking period during internal synchronization. activity detection interrupt for clk detection. hsync, vsync and de detection in terrupts can be set to generate upon transitions on the pdi_hsync, pdi_vsync and pdi_de pins. activity lost interrupt for pdi_cl k ? for the pdi_clk lost interrupt, is triggered when the pdi_clk is less than dcu3 module clock frequency divided by 32. (i.e. if dcu3 module clock freq. max = 64 mhz, then the pdi_clk_lost flag will be set if pdi clk freq. min < 2 mhz). all interrupt flags are "w rite-one-to-clear" and al l interrupts are maskable. pdi must reset to show the latest status of the clock activity detect interrupt. table 11-80. data extraction in all possible modes pdi mode narrow mode pins data notes 8-bit monochrome mode 1'b0 8 bit pdi[7:0] ? rgb565 1'b0 16 bit pdi[15:0] ? rgb666 1'b0 18 bit pdi[17:0] ? rgb565 muxed 1'b1 8 bit pdi[7:0] data from two clocks are combined. ycbcr422 1?b1 8 bit pdi[7:0] data from four clocks are combined for 2 pixels.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-125 preliminary?subject to change without notice 11.9 switch between dcu mode and pdi mode (top-level description) figure 11-100. switch to pdi on receiving the interrupt figure 11-101. switch to normal mode from pdi mode pdi_vsync the pdi_vsync_out is generated after validation logic receives the number of frames specified by the users/cpu. pdi lock is generated pdi_vsync_out pdi_lock_status pdi_enb dcu_vsync dcu internal vsync dcu_vsync rising edge sync to dcu internal vsync dcu_vsync falling edge sync to pdi vsync out dcu_vsync switching to pdi once en and lock status is high extended vsync for g ap between the 2 vsync hsync not coming during extended vsync pdi_vsync the pdi_vsync_out is stopped once pdi loses lock or enb is deasserted pdi_vsync_out pdi_lock_status dcu_vsync dcu internal vsync dcu_hsync switching to normal mode on vsync after lock is lost data force to a constant value once lock is lost
pxd20 microcontroller reference manual, rev. 1 11-126 freescale semiconductor preliminary?subject to change without notice 11.9.1 changes in the configuration any changes in the rgb format or the synchronization mode configuration require s the pdi system to be in disable mode i.e. pdi_en should be 0 during this ti me. the resolution of the screen/layer (pdi or tft) cannot change on the fly. 11.9.1.1 pdi slave mode the vsync generated by the dcu3 block is sync hronized to the pdi input vsync; the pdi vsync resets the internal timing genera tion unit. hsync and vsync are gene rated internally corresponding to the external tft screen display parame ters programmed in the dcu3 registers. in slave mode the pdi and dcu3 introduce a fixed latency to the vsync and hsync timing. 11.9.1.2 pdi sync detection/validation pdi declares a lock when it has correctly received the continuous number of frames programmed by the application. pdi declares the sync lost: ? when it receives data enable during the verti cal and horizontal blanking period (in case of data enable mode) ? when the incoming hsync and vsync timing does not match the pr ogrammed parameter values in the dcu3. this also means that if any of control signal info lost, then it also declares sync lost. after pdi_pclk is lost, the pdi requires 64 dcu3 module clock cycles to detect pdi_pclk again. pdi does not declare lost sync in case of blanking and ecc errors. writes to the input fifo are stopped as soon as pdi sync is lost aborting transfer of the current frame data. sync detection works continuou sly, independent of pdi enab le. pdi fires an interrupt on: ? sync lock is achieved ? sync is lost ? activity is detected on hsync ? activity is detected on vsync ? pclk activity detection (it is not generated from the state machine) ? de activity detection (it is not generated from the state machine) ? pclk activity lost (it is not generated from the state machine) on receiving a wrong sync pulse, the dcu3 stops th e hsync and vsync activity detection and gives an interrupt when it finds sync pulse again. the state machine works for zero values of front and back porches but not for pulse wi dth and screen parameters.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 11-127 preliminary?subject to change without notice 11.9.1.3 other assumptions the reset to the pdi clock is synchronized to the peripheral clock. reset sync hronization is done with respect to the pdi clock internally. the pdi clock should be available at least 10 clock after the last valid data. this corresponds to the delay of the pdi block. 11.10 dcu3 initialization the following steps describe a typi cal approach to initializing the dcu3 for use in an application. 1. after reset configure the dcu3 peripheral to be active using the mode entry module and configure the dcu3 clock source in the mc_cgm. 2. if using a panel with an integrated tcon m odule, disable the tcon signals by setting the tcon_bypass bit in the tcon ct rl1 register. due to the conf iguration of the tcon module, the dcu3 pixel clock signal will be output as s oon as it is selected by the siul pcr. this is independent of the dcu3 operating mode. 3. configure the output ports in the siul as required. 4. configure the timing registers to match the tft lcd panel in use ( section 11.4.2, tft lcd panel configuration ). 5. set the background color as required. 6. load the initial tile or palette colors into the clut/tile memory 7. configure the control descriptors for the layers and cursor that are to be used initially 8. enable the dcu3 in the appropriate m ode (dcu_mode and raster_en bit fields).
pxd20 microcontroller reference manual, rev. 1 11-128 freescale semiconductor preliminary?subject to change without notice 11.11 glossary table 11-81. glossary term description argb (also bgra) a data format where the pixel val ues are stored using four components: alpha, red, green and blue. dcu3 supports different variations of this format where different numbers of bits can be used to represent each of the components component part of a pixel that contains a single color (red, green or blue) clut color look-up table. the table that contai ns the palette used by an indexed-color graphic direct color the full 24-bit value actually written to a pixel to create a color frame the collection of all pixels on a panel gamut the set of colors that a panel can display. in most cases a panel cannot display the full gamut of colors visible to the human eye. indexed color an index into a table containing direct-color s. usually smaller in size than the direct color; the dcu3 provides 1, 2, 4, and 8 bits per pixel options palette the list of colors used by a graphic when an indexed colors format is used. the palette is stored in a color look up table and can be from one color up to the maximum of the size of the clut. panel a tft lcd containing an array of colored pixels. pixel the basic graphical element on a tft lcd panel. can display a range of colors depending on the value of the red, green and blue values written to it. normally arranged in a rectangular array. rgb a data format where the pixel values are st ored using three components: red, green and blue. dcu3 supports different variations of this format where different numbers of bits can be used to represent each of the components vertical blanking period a time during the tft lcd panel refresh cycle when no data is being written to the panel
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-1 preliminary?subject to change without notice chapter 12 display control unit lite (dculite) 12.1 introduction the display control unit lite (dculite) module is a system master that fetc hes graphics stored in internal or external memory and displays them on a tft lcd panel. a wide range of panel sizes is supported and the timing of the interf ace signals is highly configurable. graphics are read directly from memory and then blended in real time, which a llows for dynamic content creation with minimal cpu intervention. graphics may be encode d in a variety of formats to optimize memory usage. the dculite also has the capability of displaying real-t ime video from an external video source. 12.1.1 overview figure 12-1 shows the block diagram for dculite.
pxd20 microcontroller reference manual, rev. 1 12-2 freescale semiconductor preliminary?subject to change without notice figure 12-1. dculite block diagram the block diagram comprises two dist inct sections. the lower section s hows the functional blocks of the dculite that fetch the graphic and video conten t and drive the tft lcd panel. the upper section describes the user interface through which the user configures the grap hical content of the tft lcd panel. the sections are analogous to the st ructure of communications modules, such as the flexcan, where one part of the module is configured to connect with the communications bus th rough bit-timin g, parity, baud rate, etc., while a different part is used to store the data content and message identifiers. registers interface (control layer0 layer1 layer2 pixel format converter blending gamma correction out fifo display driver parallel data interface gamma dcu_clk pdi_pclk pdi[17:0] ahb master i/f external video tft display pdi_hsync pdi_vsync timing and control unit pix_clk_in pdi_clk mux pclk, hsync, vsync timing signals to other modules mode ram cursor layer3 (1 kb) (256 x 8 x3) signature calculator crc_ready interrupt crc value ch1 ch2 crc pos descriptors for each layer) slave bus i/f in fifo in fifo ram source bgcolor clut/ palette ram (512x32)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-3 preliminary?subject to change without notice the configuration of the lower sec tion is dependent on the specific tf t lcd panel and opt ional real-time video hardware that are attached to the dculite inputs and outputs. in mo st cases, this is configured once for the hardware in use before the dculite is enabled. when active, this section automatically: ? calculates the relevant gra phical content for each pixel ? fetches the source graphics fr om memory using its internal dma channels (labelled ch1 and ch2) ? converts the graphic value of each fetched pixe l into full quality color format (if required) ? calculates the required pixel value by blending the values of up to two separate graphics ? performs a gamma correction on the pixel value (if required) ? sends the pixel value to the tft lcd display over its data bus ? sets flags to indicate end of frame, buf fer threshold, and other status changes the upper section describes the characteristics of the graphics to be displayed on the panel and how they are blended together. the dculite manages the graphi cal content of the panel through sets of registers called layers. there are 4 layers available in the dculite and each contains the following information: ? horizontal and vertic al size of graphic ? position of graphic on the panel ? address of graphic in memory ? color encoding format and color palettes (if required) ? type and depth of blending ? range of colors identified for chroma blending ? tile size the values in these registers may be changed at any time, and the pane l content will be updated when the next full frame is ready to be displa yed. the layers are set to a fixed priority, and this is used by the lower section to define which layers are bl ended, in which order, on the panel. the upper section also cont ains configuration register s for a cursor graphic, th e default background color, interrupt enables, test graphic, and simple register pr otection settings. 12.1.2 features the dculite has these features: ? full rgb888 output to tft lcd panel ? 4 graphics layers, a default background color laye r and a cursor layer wi th integrated blinking option ? blending of each pixel using up to 2 sour ce layers dependent on size of panel ? programmable panel size up to a maximum of xga (1024 ? 768) ? gamma correction with 8-bit resolution on each color component ? safety mode for tagging pixels on highest priority layers ? digital video input with and without sync extraction per itu- r bt.656 supporting multiple video input formats including rgb666, rgb565, monochrome and ycbcr422
pxd20 microcontroller reference manual, rev. 1 12-4 freescale semiconductor preliminary?subject to change without notice ? dedicated memory blocks to store a cu rsor and color look up tables (cluts) ? temporal dithering. each graphic layer has th e following attributes: ? can be placed with one pixe l resolution in either axis ? can also be placed in negative x & y directions ? supports multiple color-encoding formats including: ? 1, 2, 4 and 8 bits per pixel inde xed colors with alpha channel ? apal8 indexed colors with alpha channel ? rgb565 and rgb888 direct colors ? argb1555, argb4444, and brga 8888 direct colors with an alpha channel ? ycbcr422 format ? alpha blending with 8-bit resolution ? chroma-key blending fo r anti-mask encoding ? multiple alpha and chroma-key blending modes ? transparency modes for anti -aliased text and graphics ? luminance mode for highlighting content ? tile mode for efficient creati on of textured background content ? support for run length encoding (rle) compression ? optimized mode for use with ddr memory 12.1.3 modes of operation the dculite has four modes of operation: ? dcu_off : when in this mode, the dculite is turned of f. all the logic in the design is put in reset state to reduce power. ? normal_mode : the dculite displays and blends the graphics specified by the layer descriptors. ? pdi_mode : a mode which fetches video from an external video source and combines that with the graphics configured on the layers. ? colbar_mode : color bar generation for test ing purposes. it is important for us to generate the color bars within the dculite itself. this is us eful for the user to verify if the dculite is operational without interaction with the system memory. 12.2 external signal description the dculite has up to 22 input signals and up to 30 output signals. see figure 12-2 . the choice of signals used depends on the configur ation of the dculite. all active signals must be enabled by configuring the appropriate pcr registers in the siul module.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-5 preliminary?subject to change without notice figure 12-2. external signals 12.2.1 detailed signal descriptions table 12-1. detailed signal descriptions signal direction description parallel data interface (camera interface) pdi_pclk in clock for the parallel data from the input video data pdi_vsync in vertical sync to indicate t he start of new frame for the display pdi_hsync in horizontal sync to indicate the start of new line for the display pdi_de in data enable for the camera data input pdi[17:0] in 18-bit parallel input data for the display display interface dcu_pclk out pixel clock used to drive the display panel dcu_vsync out vertical sync signal, indicating the beginning of a new frame dcu_hsync out horizontal sync signal, indicating the beginning of a new line dcu_tag out when high, this signal indicates t hat the pixel is tagged and an application can calculate crc externally on this pixel. dcu_de out data enable. qualifies the data output dcu_r[7:0], dcu_g[7:0], dcu_b[7:0] out red, green and blue data output. dculite top external video source display interface pdi_pclk dcu_pclk dcu_vsync dcu_hsync dcu_csync (not used) dcu_de dcu_r[7:0], dcu_g[7:0], dcu_b[7:0] pdi[17:0] pdi _ vsync pdi_ hsync pdi_ de dcu_tag level
pxd20 microcontroller reference manual, rev. 1 12-6 freescale semiconductor preliminary?subject to change without notice 12.3 memory map and register definition 12.3.1 memory map table 12-2 shows the memory map of the dculite. 12.3.2 register map table 12-3 provides the register map of the dculite. only 32-bit writes and 32-bit aligned access are supported. byte half-word access is not supported. table 12-2. dculite memory map parameter address range register address space 0x0000 ? 0x03ff cursor address space 0x0400 ? 0x07ff gamma_r address space 0x0800 ? 0x0bff gamma_g address space 0x0c00 ? 0x0fff gamma_b address space 0x1000 ? 0x13ff empty space 0x1400 ? 0x1fff clut address space (2 kb repeated) 0x2000 ? 0x3fff table 12-3. dculite register map address offset register access reset value location 0x000 ctrldescl0_1 register r/w 0x00000000 on page 12-19 0x004 ctrldescl0_2 register r/w 0x00000000 on page 12-20 0x008 ctrldescl0_3 register r/w 0x00000000 on page 12-21 0x00c ctrldescl0_4 register r/w 0x00000000 on page 12-22 0x010 ctrldescl0_5 register r/w/ 0x00000000 on page 12-23 0x014 ctrldescl0_6 register r/w/ 0x00000000 on page 12-24 0x018 ctrldescl0_7 register r/w/ 0x00000000 on page 12-25 0x01c ctrldescl1_1 register r/w 0x00000000 on page 12-19 0x020 ctrldescl1_2 register r/w 0x00000000 on page 12-20 0x024 ctrldescl1_3 register r/w 0x00000000 on page 12-21 0x028 ctrldescl1_4 register r/w 0x00000000 on page 12-22 0x02c ctrldescl1_5 register r/w 0x00000000 on page 12-23 0x030 ctrldescl1_6 register r/w 0x00000000 on page 12-24 0x034 ctrldescl1_7 register r/w 0x00000000 on page 12-25 0x038 ctrldescl2_1 register r/w 0x00000000 on page 12-19
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-7 preliminary?subject to change without notice 0x03c ctrldescl2_2 register r/w 0x00000000 on page 12-20 0x040 ctrldescl2_3 register r/w 0x00000000 on page 12-21 0x044 ctrldescl2_4 register r/w 0x00000000 on page 12-22 0x048 ctrldescl2_5 register r/w 0x00000000 on page 12-23 0x04c ctrldescl2_6 register r/w 0x00000000 on page 12-24 0x050 ctrldescl2_7 register r/w 0x00000000 on page 12-25 0x054 ctrldescl3_1 register r/w 0x00000000 on page 12-19 0x058 ctrldescl3_2 register r/w 0x00000000 on page 12-20 0x05c ctrldescl3_3 register r/w 0x00000000 on page 12-21 0x060 ctrldescl3_4 register r/w 0x00000000 on page 12-22 0x064 ctrldescl3_5 register r/w 0x00000000 on page 12-23 0x068 ctrldescl3_6 register r/w 0x00000000 on page 12-24 0x06c ctrldescl3_7 register r/w 0x00000000 on page 12-25 0x070?0x1bc reserved 0x1c0 ctrldesccursor_1 register r/w 0x00000000 on page 12-26 0x1c4 ctrldesccursor_2 register r/w 0x00000000 on page 12-26 0x1c8 ctrldesccursor_3 register r/w 0x00000000 on page 12-27 0x1cc ctrldesccursor_4 register r/w 0x00000000 on page 12-28 0x1d0 dcu_mode register r/w 0x00008000 on page 12-28 0x1d4 bgnd register r/w 0x00000000 on page 12-30 0x1d8 disp_size register r/w 0x00000000 on page 12-31 0x1dc hsyn_para register r/w 0x00c01803 on page 12-32 0x1e0 vsyn_para register r/w 0x00c01803 on page 12-32 0x1e4 synpol register r/w 0x00000000 on page 12-33 0x1e8 threshold register r/w 0x0000780a on page 12-34 0x1ec int_status register r 0x00000000 on page 12-35 0x1f0 int_mask register r/w 0x00004fff on page 12-36 0x1f4 colbar_1 register r/w 0xff000000 on page 12-38 0x1f8 colbar_2 register r/w 0xff0000ff on page 12-38 0x1fc colbar_3 register r/w 0xff00ffff on page 12-39 0x200 colbar_4 register r/w 0xff00ff00 on page 12-39 0x204 colbar_5 regi ster r/w 0xffffff00 on page 12-40 0x208 colbar_6 register r/w 0xffff0000 on page 12-40 table 12-3. dculite register map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 12-8 freescale semiconductor preliminary?subject to change without notice 0x20c colbar_7 register r/w 0xffff00ff on page 12-41 0x210 colbar_8 register r/w 0xffffffff on page 12-41 0x214 div_ratio register r/w 0x0000001f on page 12-41 0x218 sign_calc_1 register r/w 0x00000000 on page 12-42 0x21c sign_calc_2 register r/w 0x00000000 on page 12-43 0x220 crc_val register r/w 0x00000000 on page 12-43 0x224 pdi_status register r 0x00000000 on page 12-44 0x228 mask_pdi_status register r/w 0x000003ff on page 12-45 0x22c parr_err_status register r 0x00000000 on page 12-46 0x230 mask_parr_err_status register r/w 0x000f000f on page 12-48 0x234 threshold_inp_buf_1 register r/w 0x7f007f00 on page 12-49 0x238 reserved 0x23c luma_comp register r/w 0x9512a254 on page 12-50 0x240 red register r/w 0x03310000 on page 12-50 0x244 green register r/w 0x06600f38 on page 12-51 0x248 blue register r/w 0x00000409 on page 12-51 0x24c crc_pos register r/w 0x00000000 on page 12-52 0x250 fg0_fcolor register r/w 0x00000000 on page 12-53 0x254 fg0_bcolor register r/w 0x00000000 on page 12-53 0x258 fg1_fcolor register r/w 0x00000000 on page 12-53 0x25c fg1_bcolor register r/w 0x00000000 on page 12-53 0x260 fg2_fcolor register r/w 0x00000000 on page 12-53 0x264 fg2_bcolor register r/w 0x00000000 on page 12-53 0x268 fg3_fcolor register r/w 0x00000000 on page 12-53 0x26c fg3_bcolor register r/w 0x00000000 on page 12-53 0x270?0x2cc reserved 0x2d0 lyr_intpol_en r/w 0x00000000 on page 12-54 0x2d4 lyr_luma_comp register r/w 0x9512a254 on page 12-54 0x2d8 lyr_chroma_red register r/w 0x03310000 on page 12-55 0x2dc lyr_chroma_green register r/w 0x06600f38 on page 12-56 0x2e0 lyr_chroma_blue register r/w 0x00000409 on page 12-56 0x2e4 comp_imsize register r/w 0x00000000 on page 12-57 0x2e8?0x2fc reserved table 12-3. dculite register map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-9 preliminary?subject to change without notice 12.3.3 register summary figure 12-3 provides a key for register figures and tables and the register summary. the conventions in table 12-4 serve as a key for the register summ ary and individual register diagrams. 0x300 global protection register r/w 0x00000000 on page 12-57 0x304 soft lock bit register l0 r/w 0x00000000 on page 12-58 0x308 soft lock bit register l1 r/w 0x00000000 on page 12-59 0x30c soft lock bit register disp_size r/w 0x00000000 on page 12-61 0x310 soft lock bit register vsync/hsync para r/w 0x00000000 on page 12-62 0x314 soft lock bit register pol r/w 0x00000000 on page 12-63 0x318 soft lock bit register l0_transp r/w 0x00000000 on page 12-63 0x31c soft lock bit register l1_transp r/w 0x00000000 on page 12-64 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 12-3. key to register fields table 12-4. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable fieldname identifies the field. its pres ence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect w write only r/w standard read/write bit. only software can c hange the bit?s value (other than a hardware reset). rwm a read/write bit that can be modified by hardware in some fashion other than by a reset w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the m odule, but it always reads as zero. (previously designated slfclr) s set: pattern on the data bus is ored with and written into the register. c clear: pattern on the data bus is a mask. if a bit on the mask is set, then the corresponding register bit is cleared. reset values 0 resets to zero table 12-3. dculite register map (continued) address offset register access reset value location
pxd20 microcontroller reference manual, rev. 1 12-10 freescale semiconductor preliminary?subject to change without notice 1 resets to one ? undefined at reset u unaffected by reset [ signal_name ] reset value is determined by polarity of indicated signal. table 12-5. register descriptions name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ctrldescl0_1 0x000 r00000 height w r00000 width w ctrldescl0_2 0x004 r0000 posy w r0000 posx w ctrldescl0_3 0x008 r addr w r w ctrldescl0_4 0x00c r en til e_e n 0 saf ety _en trans bpp w r rle_en 00 luoffs 0 bb ab w ctrldescl0_5 0x010 r00000000 ckmax_r w r ckmax_g ckmax_b w ctrldescl0_6 0x014 r00000000 ckmin_r w r ckmin_g ckmin_b w table 12-4. register conventions (continued) convention description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-11 preliminary?subject to change without notice ctrldescl0_7 0x018 r00000 tile_vert_size w r00000000 tile_hor_size w ctrldesccurs or_1 0x1c0 r00000 height w r00000 width w ctrldesccurs or_2 0x1c4 r00000 posy w r00000 posx w ctrldesccurs or_3 0x1c8 rcu r_e n 0000000 default_cursor_color[0:7] w r default_cursor_color[8:23] w ctrldesccurs or_4 0x1cc r00000000 hwc_blink_off w r0000000 en_blink hwc_blink_on w dcu_mode 0x1d0 r dcu_sw_ reset dither_en addb addg addr ddr_mode 000 pdi_sync_lock w r pdi_interpol_en raster_en pdi_en pdi_byte_rev pdi_de_mode pdi_narrow_mode pdi_mode pdi_slave_mode tag_en sig_en pdi_sync 0 en_gamma dcu_mode w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 12-12 freescale semiconductor preliminary?subject to change without notice bgnd 0x1d4 r00000000 bgnd_r w r bgnd_g bgnd_b w disp_size 0x1d8 r00000 delta_y w r000000000 delta_x w hsyn_para 0x1dc r0 bp_h 00 pw_h[0:3] w r pw_h[4:8] 00 fp_h w vsyn_para 0x1e0 r0 bp_v 00 pw_v[0:3] w r pw_v[4:8] 00 fp_v w syn_pol 0x1e4 r0000000000000000 w r00000 inv_pdi_de inv_pdi_hs inv_pdi_vs inv_pdi_clk inv_pxck neg bp_vs bp_hs inv_cs inv_vs inv_hs w threshold 0x1e8 r00000 ls_bf_vs w r out_buf_high out_buf_low w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-13 preliminary?subject to change without notice int_status 0x1ec r0000000000000000 w r0 dma_trans_finish 00 ipm_error prog_end p2_fifo_hi_flag p2_fifo_lo_flag p1_fifo_hi_flag p1_fifo_lo_flag crc_overflow crc_ready vs_blank ls_bf_vs undrun vsync w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c int_mask 0x1f0 r0000000000000000 w r0 m_dma_trans_finish 00 m_ipm_error m_prog_end m_p2_fifo_hi_flag m_p2_fifo_lo_flag m_p1_fifo_hi_flag m_p1_fifo_lo_flag m_crc_overflow m_crc_ready m_vs_blank m_ls_bf_vs m_undrun m_vsync w colbar_1 0x1f4 r11111111 colbar_1_r w r colbar_1_g colbar_1_b w colbar_2 0x1f8 r11111111 colbar_2_r w r colbar_2_g colbar_2_b w colbar_3 0x1fc r11111111 colbar_3_r w r colbar_3_g colbar_3_b w colbar_4 0x200 r11111111 colbar_4_r w r colbar_4_g colbar_4_b w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 12-14 freescale semiconductor preliminary?subject to change without notice colbar_5 0x204 r11111111 colbar_5_r w r colbar_5_g colbar_5_b w colbar_6 0x208 r11111111 colbar_6_r w r colbar_6_g colbar_6_b w colbar_7 0x20c r11111111 colbar_7_r w r colbar_7_g colbar_7_b w colbar_8 0x210 r11111111 colbar_8_r w r colbar_8_g colbar_8_b w div_ratio 0x214 r0000000000000000 w r00000000 div_ratio w sign_calc_ 1 0x218 r00000 sig_ver_size w r00000 sig_hor_size w sign_calc_ 2 0x21c r00000 sig_ver_pos w r00000 sig_hor_pos w crc_val 0x220 r crc_val w r w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-15 preliminary?subject to change without notice pdi_status 0x224 r0000000000000000 w r000000 pdi_blanking_err pdi_ecc_err2 pdi_ecc_err1 pdi_lock_lost pdi_lock_det pdi_vsync_det pdi_hsync_det pdi_de_det pdi_clk_lost pdi_clk_det w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c mask_pdi_ status 0x228 r0000000000000000 w r000000 m_pdi_blanking_err m_pdi_ecc_err2 m_pdi_ecc_err1 m_pdi_lock_lost m_pdi_lock_det m_pdi_vsync_det m_pdi_hsync_det m_pdi_de_det m_pdi_clk_lost m_pdi_clk_det w parr_err_ status 0x22c r000000000000 rle_err hwc_err sig_err disp_err w w1c w1c w1c w1c r000000000000 l3_parr_err l2_parr_err l1_parr_err l0_parr_err w w1c w1c w1c w1c table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 12-16 freescale semiconductor preliminary?subject to change without notice mask_parr _err_statu s 0x230 r000000000000 m_rle_err m_hwc_err m_sig_err m_disp_err w r000000000000 m_l3_parr_err m_l2_parr_err m_l1_parr_err m_l0_parr_err w threshold _inp_buf 0x234 r0 inp_buf_p2_hi 0 inp_buf_p2_lo w r0 inp_buf_p1_hi 0 inp_buf_p1_lo w luma_comp 0x23c r y_red y_green[0:4] w r y_green[5:9] y_blue w chroma_ red 0x240 r00000 cr_red w r0000 cb_red w chroma_ green 0x244 r00000 cr_green w r0000 cb_green w chroma_ blue 0x248 r00000 cr_blue w r0000 cb_blue w crc_pos 0x24c r crc_pos w r w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-17 preliminary?subject to change without notice fgx_fcolor 0x250 r11111111 fgx_fcolor[0:7] w r fgx_fcolor[8:23] w fgx_bcolor 0x254 r11111111 fgx_bcolor[0:7] w r fgx_bcolor[8:23] w lyr_intpol _en 0x2d0 r lyr_intpol_en 000000000000000 w r0000000000000000 w ly r _ l u m a _ comp 0x2d4 r y_red y_green[0:4] w r y_green[5:9] y_blue w lyr_chrom a_red 0x2d8 r00000 cr_red w r0000 cb_red w lyr_chrom a_green 0x2dc r00000 cr_green w r0000 cb_green w lyr_chrom a_blue 0x2e0 r00000 cr_blue w r0000 cb_blue w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 12-18 freescale semiconductor preliminary?subject to change without notice comp_imsiz e 0x2e4 r0000000000 comp_imsize[21:16] w r comp_imsize[15:0] w global_protec tion 0x300 r hlb 000000000000000 w r0000000000000000 w soft_lock_bit l0 0x304 r0000 slb_l0_1 slb_l0_2 slb_l0_3 slb_l0_4 0000 slb_l0_5 slb_l0_6 slb_l0_7 0 w wen_lo_1 wen_lo_2 wen_lo_3 wen_lo_4 wen_lo_5 wen_lo_6 wen_lo_7 r0000000000000000 w soft_lock_bit l1 0x308 r0000 slb_l1_1 slb_l1_2 slb_l1_3 slb_l1_4 0000 slb_l1_5 slb_l1_6 slb_l1_7 0 w wen_l1_1 wen_l1_2 wen_l1_3 wen_l1_4 wen_l1_5 wen_l1_6 wen_l1_7 r0000000000000000 w soft_lock_di sp_size 0x30c r0000 slb_disp 00000000000 w wen_disp r0000000000000000 w soft_lock_hs ync/vsync pa r a 0x310 r0000 slb_hsync slb_vsync 0000000000 w wen_hsync wen_vsync r0000000000000000 w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-19 preliminary?subject to change without notice 12.3.4 register descriptions this section describes the dculite registers. 12.3.4.1 control descriptor l0 _1 register (ctrldescl0_1) figure 12-4 represents the control descriptor l0_1 register. this register se ts the height and width of the layer associated with the register. soft_lock_p ol 0x314 r0000 slb_pol 00000000000 w wen_pol r0000000000000000 w soft_lock l0_transp 0x318 r0000 slb_fcolor slb_bcoloe 0000000000 w wen_fcolor wen_bcolor r0000000000000000 w soft_lock l1_transp 0x31c r0000 slb_fcolor slb_bcoloe 0000000000 w wen_fcolor wen_bcolor r0000000000000000 w table 12-5. register descriptions (continued) name offset 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 12-20 freescale semiconductor preliminary?subject to change without notice 12.3.4.2 control descr iptor l0_2 register figure 12-5 represents the control descript or l0_2 register.this register se ts the origin (top/left) of the layer associated with the register offsets: 0x000 (ctrldescl0_1) 0x01c (ctrldescl1_1) 0x038 (ctrldescl2_1) 0x054 (ctrldescl3_1) access: user read/write 0123456789101112131415 r00000 height w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 width w reset0000000000000000 figure 12-4. ctrldescl0_1 register table 12-6. ctrldescl0_1 field descriptions field description height height of the layer in pixels width width of the layer (in pixels). the layer width must be in multiples of the number of pixels that can be stored in 32 bits except for the special case of 1 bit per pixel, and therefore differs depending on color encoding. for example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-21 preliminary?subject to change without notice 12.3.4.3 control descr iptor l0_3 register figure 12-8 represents the control descriptor l0_3 register.this register sets the beginning address of layer data. offsets: 0x004 (ctrldescl0_2) 0x020 (ctrldescl1_2) 0x03c (ctrldescl2_2) 0x058 (ctrldescl3_2) access: user read/write 0123456789101112131415 r0 0 0 0 posy w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 posx w reset0000000000000000 figure 12-5. ctrldescl0_2 register table 12-7. ctrldescl0_2 field descriptions field description posy two?s complement signed value setting the vertic al position of top row of the layer, where 0 is the top row of the panel. positive values are below and negative values are above the top row of the panel. posx two?s complement signed value setting the horizon tal position of left hand column of the layer, where 0 is the left hand column of the panel. posi tive values are to the right and negative values are to the left the left hand column of the panel.
pxd20 microcontroller reference manual, rev. 1 12-22 freescale semiconductor preliminary?subject to change without notice 12.3.4.4 control descr iptor l0_4 register figure 12.3.4.5 represents the control descriptor l0_4 regi ster.his register contro ls various graphics options and whether th e layer is enabled. offsets: 0x008 (ctrldescl0_3) 0x024 (ctrldescl1_3) 0x040 (ctrldescl2_3) 0x05c (ctrldescl3_3) access: user read/write 0123456789101112131415 r addr[0:35] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr[16:31] w reset0000000000000000 figure 12-6. ctrldescl0_3 register table 12-8. ctrldescl0_3 field descriptions field description addr address of layer data in the memory. the address programmed should be 64-bit aligned. offsets: 0x00c (ctrldescl0_4) 0x028 (ctrldescl1_4) 0x044 (ctrldescl2_4) 0x060 (ctrldescl3_4) access: user read/write 0123456789101112131415 r en tile _en 0 saf ety _en trans bpp w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rle_en 00 luoffs 0 bb ab w reset0000000000000000 figure 12-7. ctrldescl0_4 register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-23 preliminary?subject to change without notice table 12-9. ctrldescl0_4 field descriptions field description en enable the layer 1?b1: on 1?b0: off tile_en enable the tile mode 1?b1: on 1?b0: off safety_en safety mode enable bit. valid only for layer 0 and layer 1. for registers of all other layers, this should be set to 0. 1?b1: safety mode is enabled for this layer 1?b0: safety mode is disabled trans transparency level. specifies the alpha value for the layer. this value may be used by the blending engine to blend pixels on this layer. value can vary between 0?255 where 0 is completely transparent and 255 is completely opaque. bpp bits per pixel 4?b0000 = 1 bpp 4?b0001 = 2 bpp 4?b0010 = 4 bpp 4?b0011 = 8 bpp 4?b0100 = 16 bpp (rgb565) 4?b0101 = 24 bpp 4?b0110 = 32 bpp (bgra8888) 4?b0111 = transparency mode 4 bpp 4?b1000 = transparency mode 8bpp 4?b1001 = luminance offset mode 4 bpp 4?b1010 = luminance offset mode 8 bpp 4?b1011 = 16 bpp (argb1555) 4?b1100 = 16 bpp (argb4444) 4?b1101 = 16 bpp (apal8) 4?b1110 = ycbcr422 (the blend engine allows only a single ycbcr layer in any blend operation) 4?b1111 = reserved rle_en enable rle mode for layer. 1?b1:enabled 1?b0:disabled luoffs look up table offset. value gives the offset to the start address of the clut (maximum value = 0x1ff for 512x32-bit entries). bb chroma keying 1?b1: on 1?b0: off ab alpha blending 2?b00: no alpha blending 2?b01: blend only the pixels selected by chroma keying in case bb=1?b1 2?b10: blend the whole frame 2?b11: same functionality as 2?b00.
pxd20 microcontroller reference manual, rev. 1 12-24 freescale semiconductor preliminary?subject to change without notice 12.3.4.5 control descr iptor l0_5 register figure represents the control descriptor l0_5 register . this register sets the maximum chroma keying values for rgb. see section 12.4.4.5, alpha and chroma-key blending, for a description of chroma keying. 12.3.4.6 control descr iptor l0_6 register figure 12-9 represents the control descri ptor l0_6 register. this regist er sets the minimum chroma keying values for rgb. see section section 12.4.4.5, alpha and chroma-key blending, for a description of chroma keying. offsets: 0x010 (ctrldescl0_5) 0x02c (ctrldescl1_5) 0x048 (ctrldescl2_5) 0x064 (ctrldescl3_5) access: user read/write 0123456789101112131415 r00000000 ckmax_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ckmax_g ckmax_b w reset0000000000000000 figure 12-8. ctrldescl0_5 register table 12-10. ctrldescl0_5 field descriptions field description ckmax_r chroma keying max red component ckmax_g chroma keying max green component ckmax_b chroma keying max blue component
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-25 preliminary?subject to change without notice 12.3.4.7 control descr iptor l0_7 register figure 12-10 represents the control descriptor l0_7 register. offsets: 0x014 (ctrldescl0_6) 0x030 (ctrldescl1_6) 0x04c (ctrldescl2_6) 0x068 (ctrldescl3_6) access: user read/write 0123456789101112131415 r00000000 ckmin_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ckmin_g ckmin_b w reset0000000000000000 figure 12-9. ctrldescl0_6 register table 12-11. ctrldescl0_6 field descriptions field description ckmin_r chroma keying minimum red component ckmin_g chroma keying minimum green component ckmin_b chroma keying minimum blue component offsets: 0x018 (ctrldescl0_7) 0x034 (ctrldescl1_7) 0x050 (ctrldescl2_7) 0x06c (ctrldescl3_7) access: user read/write 0123456789101112131415 r00000 tile_ver_size w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 tile_hor_size w reset0000000000000000 figure 12-10. control descriptor l0_7 register
pxd20 microcontroller reference manual, rev. 1 12-26 freescale semiconductor preliminary?subject to change without notice for the other 3 layers, the control de scriptor register set is identical. 12.3.4.8 control descriptor cursor 1 register (ctrldesccursor_1) figure 12-11 represents the control desc riptor cursor 1 register. 12.3.4.9 control descriptor cursor 2 register (ctrldesccursor_2) figure 12-12 represents the control desc riptor cursor 2 register. table 12-12. ctrldescl0_7 field descriptions field description tile_ver_size height of the tile (in pixels) tile_hor_size width of the tile (in multiples of 16 pixels) offset 0x1c0 access: user read/write 0123456789101112131415 r00000 height w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 width w reset0000000000000000 figure 12-11. control descriptor cursor_1 register (ctrldesccursor_1) table 12-13. ctrldesccursor_1 field descriptions field description height height of the cursor in pixels width width of the cursor in pixels
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-27 preliminary?subject to change without notice 12.3.4.10 control descriptor cursor 3 register (ctrldesccursor_3) figure 12-13 represents the control desc riptor cursor 3 register. offset 0x1c4 access: user read/write 0123456789101112131415 r00000 posy w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 posx w reset0000000000000000 figure 12-12. control descriptor cursor 2 register (ctrldesccursor_2) table 12-14. ctrldesccursor_2 field descriptions field description posy y position of the cursor in pixels posx x position of the cursor in pixels offset 0x1c8 access: user read/write 0123456789101112131415 r cur _en default_cursor_color[0:8] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r default_cursor_color[9:24] w reset0000000000000000 figure 12-13. control descriptor cursor_3 register (ctrldesccursor_3) table 12-15. control descriptor cursor_3 field descriptions field description cur_en cursor enable signal 1?b1: enable the cursor 1?b0: cursor is disabled default_curso r_color default pixel color value for the cursor. in the dculite, the pixel value for the cursor is fixed for a particular frame.
pxd20 microcontroller reference manual, rev. 1 12-28 freescale semiconductor preliminary?subject to change without notice 12.3.4.11 control descriptor cursor _4 register (ctrldesccursor_4) figure 12-14 represents the control de scriptor cursor_4 register. 12.3.4.12 dculite mode register (dcu_mode) figure 12-15 represents the dcu_mode re gister.this register sets the mode in which dculite is operating. offset 0x1cc access: user read/write 0123456789101112131415 r00000000 hwc_blink_off w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 en_blink hwc_blink_on w reset0000000000000000 figure 12-14. control descriptor cursor_4 register (ctrldesccursor_4) table 12-16. ctrldesccursor_4 field descriptions field description hwc_blink_off hwc blink register. loads the counter value (number of frames) for which the cursor will remain turned off. en_blink enable the cursor blink mode. 1?b1:enable the blink mode 1?b0:disable the blink mode hwc_blink_on hwc blink register. loads the counter value (number of frames) for which the cursor will remain turned on.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-29 preliminary?subject to change without notice offset 0x1d0 access: user read/write 0123456789101112131415 r dcu_sw_reset dither_en addb addg addr ddr_mode 000 pdi_sync_lock w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pdi_interpol_en raster_en pdi_en pdi_byte_rev pdi_de_mode pdi_narrow_mode pdi_mode pdi_slave_mode tag_en sig_en pdi_sync 0 en_gamma dcu_mode w reset1000000000000000 figure 12-15. dculite mode register (dcu_mode) table 12-17. dcu_mode field descriptions field description dcu_sw_reset used to clear all the registers to reset state 1?b1:all the dculite register s are put in reset state dither_en enable dithering mode 1?b1:enabled. 1?b0:disabled addb two-bit value to be added to pixel blue component for dithering addg two-bit value to be added to pixel green component for dithering addr two-bit value to be added to pixel red component for dithering ddr_mode enables special ddr mode (see section 12.4.9, special ddr mode ) pdi_sync_lock defines the number of frames which s hould be received by the pdi validation state machine before it locks and sets the pdi_lock_det bit in the pdi status register (see section 12.3.4.26, pdi stat us register (pdi_status) ) pdi_interpol_en control bit to decide whether the conver sion from ycbcr 4:2:2 to 4:4:4 needs to be done using interpolation or chroma value is same for two pixels 1?b1:interpolation is enabled. 1?b0:chroma value is same for two pixels raster_en enables raster scanning of pixel data including the vsync and hsync signals and the pixel data. changes to this bit take effect af ter the completion of the current frame. 1?b1: enabled 1?b0: disabled
pxd20 microcontroller reference manual, rev. 1 12-30 freescale semiconductor preliminary?subject to change without notice 12.3.4.13 bgnd register figure 12-16 represents the bgnd register. pdi_en enables the pdi 1?b1: enabled 1?b0: disabled pdi_byte_rev controls the byte ordering in narrow mode 1?b0:lsb is followed by msb data 1?b1:msb is followed by lsb data pdi_de_mode enables the pdi data enable mode. here data enable is treated as an input. 1?b0: value on data enable signal is ignored 1?b1: data enable signal must be present in incoming stream pdi_narrow_mo de enables the pdi narrow mode (refer to section 12.8.1.5, normal and narrow mode ) 1?b0: narrow mode is disabled 1?b1: narrow mode is enabled pdi_mode defines the different modes in which pdi is operating 2?b00: 8 bit monochrome data input 2?b01: 16 bit rgb 565 format 2?b10:18 bit rgb 666 data format. 2?b11:ycbcr data in 4:2:2 format. pdi_slave_mode enables pdi slave mode 1?b0:disabled 1?b1:enabled tag_en enables the calculation of crc only on the safety layers 1?b0: crc calculated over the whole area of inte rest (area of interest given by sig_desc registers) 1?b1: calculates crc only on safety enabled layers sig_en enables the signature calculator block 1?b0: signature calculator is disabled 1?b1: signature calculator is enabled pdi_sync decides whether the camera data needs external or internal synchronization. 1?b0: external synchronization. the pdi receives the sync (hsync, vsync) signals from external source. 1?b1: internal synchronization. pdi extracts the sync information from the digital data. note: ycbcr mode supports internal sync only. therefore, when pdi_mode = 3, pdi_sync must be set to 0. en_gamma enables/disables the gamma correction 1?b0: gamma correction is disabled 1?b1: gamma correction is enabled dcu_mode dculite operating mode 2?b00: dculite off (pixel clock active if enabled by i/o) 2?b01: normal mode. panel content controlled by layer configuration. 2?b10: test mode. dculite disables all dma fetches and all the pixels of an enabled layer take the value in the clut ram selected by the res pective luoffs field of control descriptor 4. 2?b11: color bar generation. panel cont ent controlled by color bar registers. table 12-17. dcu_mode field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-31 preliminary?subject to change without notice 12.3.4.14 disp_size register figure 12-17 represents the disp_size register offset 0x1d4 access: user read/write 0123456789101112131415 r00000000 bgnd_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bgnd_g bgnd_b w reset0000000000000000 figure 12-16. bgnd register table 12-18. bgnd field descriptions field description bgnd_r red component of the default color displayed in the sectors where no layer is active bgnd_g green component of the default color disp layed in the sectors where no layer is active bgnd_b blue component of the default color displayed in the sectors where no layer is active offset 0x1d8 access: user read/write 0123456789101112131415 r00000 delta_y w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 delta_x w reset0000000000000000 figure 12-17. disp_size register table 12-19. disp_size field descriptions field description delta_y sets the display size vertical resolution (in pixels) delta_x sets the display size horizontal resolution (in pixels/16)
pxd20 microcontroller reference manual, rev. 1 12-32 freescale semiconductor preliminary?subject to change without notice 12.3.4.15 hsyn_para register figure 12-18 represents the hsyn_para register. hsyn_para register sets timing parameters related to the horizontal synchronization si gnal generation. the fields fp_h, bp_h, and pw_h stand for hsync signal front-porch, back-porch, a nd active pulse width, respectively. 12.3.4.16 vsyn_para register figure 12-19 represents the vsyn_para register. vsyn_para register sets timing parameters related to the vertical synchronization signal generation. th e fields fp_v, bp_v, and pw_v stand for vsync signal front-porch, back-porch, a nd active pulse width, respectively. offset 0x1dc access: user read/write 0123456789101112131415 r0 bp_h 00 pw_h[0:4] w reset0000000011000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pw_h[5:8] 00 fp_h w reset0001100000000011 figure 12-18. hsyn_para register table 12-20. hsyn_para field descriptions field description bp_h hsync back-porch pulse width (in pixel clock cycles) pw_h hsync active pulse width (in pixel clock cycles) fp_h hsync front-porch pulse width (in pixel clock cycles) offset 0x1e0 access: user read/write 0123456789101112131415 r0 bp_v 00 pw_v[0:4] w reset0000000011000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pw_v[4:05:8] 00 fp_v w reset0001100000000011 figure 12-19. vsyn_para register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-33 preliminary?subject to change without notice 12.3.4.17 syn_pol register figure 12-20 represents the syn_pol re gister. syn_pol register se lects polarity for corresponding synchronize signals (hsync, vsync, csync), and controls the bypass of hsync or vsync with csync signal. table 12-21. vsyn_para field descriptions field description bp_v vsync back-porch pulse width (in pixel clock cycles) pw_v vsync active pulse width (in pixel clock cycles). fp_v vsync front-porch pulse width (in pixel clock cycles) offset 0x1e4 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 inv_pdi_de inv_pdi_hs inv_pdi_vs inv_pdi_clk inv_pxck neg bp_vs bp_hs inv_cs inv_vs inv_hs w reset0000000000000000 figure 12-20. syn_pol register table 12-22. syn_pol field descriptions field description inv_pdi_de polarity change of pdi input data enable. 1?b0: de is active high 1?b1: de is active low inv_pdi_hs polarity change of pdi input hsync. 1?b0: hsync is active high 1?b1: hsync is active low inv_pdi_vs polarity ch ange of pdi input vsync. 1?b0: vsync is active high 1?b1: vsync is active low inv_pdi_clk polarity change of pdi input clock. 1?b0: dculite samples data on the rising edge 1?b1: dculite samples data on the falling edge
pxd20 microcontroller reference manual, rev. 1 12-34 freescale semiconductor preliminary?subject to change without notice 12.3.4.18 threshold register (threshold) figure 12-21 represents the th reshold register. inv_pxck polarity change of pixel clock. 1?b0: display samples data on the falling edge 1?b1: display samples data on the rising edge neg indicates if value at the output (p ixel data output) needs to be negated. 1?b0: output is to remain same 1?b1: output to be negated bp_vs bypass vertical synchronize signal (internal pin muxing). 1?b0: do not bypass vsync signal output 1 ?b1: csync bypass vsync signal, output csync in stead of vsync bp_hs bypass horizontal synchronize signal (internal pin muxing). 1?b0: do not bypass hsync signal output 1?b1: csync bypass hsync signal, output csync instead of hsync inv_cs invert composite synchronize signal. 1?b0: not invert csync signal, active high 1 ?b1: invert csync signal, active low inv_vs invert vertical synchronize signal 1?b0: not invert vsync signal, active high 1 ?b1: invert vsync signal, active low inv_hs invert horizontal synchronize signal. 1?b0: not invert hsync signal, active high 1?b1: invert hsync signal, active low offset 0x1e8 access: user read/write 0123456789101112131415 r00000 ls_bf_vs w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r out_buf_high out_buf_low w reset0111100000001010 figure 12-21. threshold register (threshold) table 12-22. syn_pol field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-35 preliminary?subject to change without notice 12.3.4.19 interrupt status register (int_status) figure 12-22 indicates the interrupt status register. the dculite has only one interrupt signal, and the cpu reads the int_status register to decide whic h exception occurs when an interrupt is detected. table 12-23. threshold field descriptions field description ls_bf_vs lines before vsync threshold value. it is a threshold value used to generate the ls_bf_vs interrupt status. sets the number of lines before vsync that the interrupt would be generated. out_buf_high output buffer filling high threshold (in pixels). it is used to generate the datapath clock enable signal. gates the datapath when output buff er filling is higher than out_buf_high. out_buf_low output buffer filling low threshold (in pi xels).this value is used to generate the underrun exception. offset 0x1ec access: user read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 dma_trans_finish 00 ipm_error prog_end p2_fifo_hi_flag p2_fifo_lo_flag p1_fifo_hi_flag p1_fifo_lo_flag crc_overflow crc_ready vs_blank ls_bf_vs undrun vsync w w1c w1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c reset0000000000000000 figure 12-22. interrupt status register (int_status) table 12-24. int_status field descriptions field description dma_trans_fin ish interrupt signal which indicates that the dculite dma has fetched the last pixel of data from the memory ipm_error interrupt signal which indicates that an error has occurred in the magenta line transaction prog_end interrupt signal which indicates that the duration for programming of dculite registers and internal memories is finished p2_fifo_hi_fla g interrupt signal to indicate that high threshol d has been reached for plane 2 (fgplane) input buffer
pxd20 microcontroller reference manual, rev. 1 12-36 freescale semiconductor preliminary?subject to change without notice 12.3.4.20 interrupt mask register (int_mask) figure 12-23 represents the interrupt mask register.this register enables or ma sks corresponding interrupt. p2_fifo_lo_fla g interrupt signal to indicate that low threshold has been reached for plane 2 (fgplane) input buffer p1_fifo_hi_fla g interrupt signal to indicate that high threshold has been reached for plane 1 (bgplane) input buffer p1_fifo_lo_fla g interrupt signal to indicate that low threshold has been reached for plane 1 (bgplane) input buffer crc_overflow interrupt signal to indicate that crc_ready has not been serviced and crc has been calculated for the next frame crc_ready interrupt signal to indicate crc calculation is done and ready to be compared with precomputed crc value by the software vs_blank interrupt signal to indicate vertical blanking period. this is the period in which all the registers that affect the visible state of the layers need to be latched. this is needed so that cpu writes to the register while the display is being updated does not cause any errors. ls_bf_vs lines before vsync interrupt. it is generat ed threshold ls_bf_vs number of lines ahead of the vertical front porch (fp_v) if enabled. th e cpu can program the registers after ls_bf_vs interrupt. undrun under run exception interrupt. asserted when display needs data and output buffer filling is lower than or equal to the out_buf_low threshold. interrupt is cleared when the data in the output buffer is greater than threshold and cpu writes 1 to this bit. vsync vertical synchronize interrupt. if enabled, an interrupt is generated at the beginning of a frame.. offset 0x1f0 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 m_dma_trans_finish 00 m_ipm_error m_prog_end m_p2_fifo_hi_flag m_p2_fifo_lo_flag m_p1_fifo_hi_flag m_p1_fifo_lo_flag m_crc_overflow m_crc_ready m_vs_blank m_ls_bf_vs m_undrun m_vsync w reset0100111111111111 figure 12-23. interrupt mask register (int_mask) table 12-24. int_status field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-37 preliminary?subject to change without notice 12.3.4.21 colbar registers the colbar registers are used to generate color bars in functional test mode. ei ght different pixel values are taken as input data, to disp lay 8 color bars on the display. table 12-25. int_mask field descriptions field description m_dma_trans_ finish mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_ipm_error mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_prog_end mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_p2_fifo_hi_f lag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_p2_fifo_lo_f lag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_p1_fifo_hi_f lag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_p1_fifo_lo_f lag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_crc_overfl ow mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_crc_ready mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_vs_blank mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_ls_bf_vs mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_undrun mask the interrupt 1?b1: interrupt is masked 1?b0:not masked m_vsync mask the interrupt 1?b1: interrupt is masked 1?b0:not masked
pxd20 microcontroller reference manual, rev. 1 12-38 freescale semiconductor preliminary?subject to change without notice 12.3.4.21.1 colbar_1 register 12.3.4.21.2 colbar_2 register offset 0x1f4 access: user read/write 0123456789101112131415 r11111111 colbar_1_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_1_g colbar_1_b w reset0000000000000000 figure 12-24. colbar_1 register offset 0x1f8 access: user read/write 0123456789101112131415 r11111111 colbar_2_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_2_g colbar_2_b w reset0000000011111111 figure 12-25. colbar_2 register (blue)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-39 preliminary?subject to change without notice 12.3.4.21.3 colbar_3 register 12.3.4.21.4 colbar_4 register offset 0x1fc access: user read/write 0123456789101112131415 r11111111 colbar_3_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_3_g colbar_3_b w reset1111111111111111 figure 12-26. colbar_3 register (cyan) offset 0x200 access: user read/write 0123456789101112131415 r11111111 colbar_4_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_4_g colbar_4_b w reset1111111100000000 figure 12-27. colbar_4 register (green)
pxd20 microcontroller reference manual, rev. 1 12-40 freescale semiconductor preliminary?subject to change without notice 12.3.4.21.5 colbar_5 register 12.3.4.21.6 colbar_6 register offset 0x204 access: user read/write 0123456789101112131415 r11111111 colbar_5_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_5_g colbar_5_b w reset1111111100000000 figure 12-28. colbar_5 register (yellow) offset 0x208 access: user read/write 0123456789101112131415 r11111111 colbar_6_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_6_g colbar_6_b w reset0000000000000000 figure 12-29. colbar_6 register (red)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-41 preliminary?subject to change without notice 12.3.4.21.7 colbar_7 register 12.3.4.21.8 colbar_8 register 12.3.4.22 clock divider ratio (div_ratio) register figure 12-32 shows clock divider rati o (div_ratio) register. offset 0x20c access: user read/write 0123456789101112131415 r11111111 colbar_7_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_7_g colbar_7_b w reset0000000011111111 figure 12-30. colbar_7 register (purple) offset 0x210 access: user read/write 0123456789101112131415 r11111111 colbar_8_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_8_g colbar_8_b w reset1111111111111111 figure 12-31. colbar_8 register (white)
pxd20 microcontroller reference manual, rev. 1 12-42 freescale semiconductor preliminary?subject to change without notice 12.3.4.23 sign_calc_1 register figure 12-33 presents the register for vertical/horiz ontal size of the ar ea for crc calculation. offset 0x214 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 div_ratio w reset0000000000011111 figure 12-32. clock divider register (div_ratio) table 12-26. div_ratio field descriptions field description div_ratio specifies the divide value for the input clock. used to generate the pixel clock to support different types of displays. to divide by n, set the div_ratio to (n-1). offset 0x218 access: user read/write 0123456789101112131415 r00000 sig_ver_size w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 sig_hor_size w reset0000000000000000 figure 12-33. sign_calc_1 register table 12-27. sign_calc_1 field descriptions field description sig_ver_size vertical size of the window of inte rest of pixels for crc calculation (in pixels) sig_hor_size horizontal size of window of interest of pixels for crc calculations (in pixels)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-43 preliminary?subject to change without notice 12.3.4.24 sign_calc_2 register figure 12-34 represents the register fo r position of the window of interest for crc calculation. 12.3.4.25 crc_val register figure 12-35 represents the register presenting the crc value to the software for comparison. offset 0x21c access: user read/write 0123456789101112131415 r00000 sig_ver_pos w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 sig_hor_pos w reset0000000000000000 figure 12-34. sign_calc_2 register table 12-28. sign_calc_2 field descriptions field description 6?15 sig_ver_pos vertical position of the window of interest of pixels for crc calculation (in pixels) 22?31 sig_hor_pos horizontal position of window of interest of pixels for crc calculation (in pixels) offset 0x220 access: user read/write 0123456789101112131415 r crc_val[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r crc_val[16:31] w reset0000000000000000 figure 12-35. crc_val register
pxd20 microcontroller reference manual, rev. 1 12-44 freescale semiconductor preliminary?subject to change without notice 12.3.4.26 pdi status register (pdi_status) figure 12-36 represents the pdi status register. table 12-29. crc_val field descriptions field description crc_val crc value calculated for safety enabled layers to be presented to the software for comparison. offset 0x224 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 pdi_blanking_err pdi_ecc_err2 pdi_ecc_err1 pdi_lock_lost pdi_lock_det pdi_vsync_det pdi_hsync_det pdi_de_det pdi_clk_lost pdi_clk_det w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 12-36. pdi status register (pdi_status) table 12-30. pdi_status field descriptions field description pdi_blanking_e rr status bit to inform the software that 80h,10h sequence is not present during the blanking period in internal sync mode. 1?b1:correct data sequence not present in blanking period 1?b0:correct data sequence present in blanking period pdi_ecc_err2 status bit to inform the software about multibit bit error that is detected. 1?b1: multibit ecc error detected 1?b0: multibit ecc error is not detected pdi_ecc_err1 status bit to inform the software about one bit error is detected. 1?b1: one bit ecc error detected 1?b0: one bit ecc error is not detected pdi_lock_lost status bit to inform the software that frame lock is lost. 1?b1: frame lock is lost 1?b0: frame is locked pdi_lock_det status bit to inform the software pdi is frame locked to the camera interface. 1?b1: frame lock is detected 1?b0: waiting for frame to lock
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-45 preliminary?subject to change without notice 12.3.4.27 pdi status mask register (mask_pdi_status) figure 12-37 represents the mask pdi status register pdi_vsync_det status bit to inform the software that vsync for the camera data has been detected. 1?b1: pdi_vsync is detected 1?b0: pdi_vsync not detected pdi_hsync_det status bit to inform the software that hsync for the came ra data has been detected. 1?b1: pdi_hsync is detected 1?b0: pdi_hsync not detected pdi_de_det status bit to inform the software that data enable for the camera data has been detected. 1?b1: pdi_de is detected 1?b0: pdi_de not detected pdi_clk_lost status bit to inform the software that pdi_clk is lost 1?b1: pdi_clk is lost 1?b0: pdi_clk is present pdi_clk_det status bit to inform the software that clock for the came ra data has been detected. 1?b1: pdi_clk is detected 1?b0: pdi_clk not detected offset 0x228 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 m_pdi_blanking_err m_pdi_ecc_err2 m_pdi_ecc_err1 m_pdi_lock_lost m_pdi_lock_det m_pdi_vsync_det m_pdi_hsync_det m_pdi_de_det m_pdi_clk_lost m_pdi_clk_det w reset0000001111111111 figure 12-37. pdi status mask register (mask_pdi_status) table 12-30. pdi_status field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 12-46 freescale semiconductor preliminary?subject to change without notice 12.3.4.28 parr_err status re gister (parr_err_status) figure 12-38 shows the parameter error status register. an error in a layer can occur when there is an auto matic error checking mechanism when a layer is enabled that detects a non-valid horizontal si ze and color format combination. see section 12.4.4.3, layer size and positioning, for details. these errors are grouped into a single bit error for each layer. the paramete r error specific to each layer is signalled only when the layer is enabled. rle_err occurs when more than one layer ha s its rle_en bit set (control descriptor 4). disp_err occurs when the size of di splay (height or width) is set to zero or when the pulse width of hsync/vsync is programmed as zero. table 12-31. mask_pdi_status field descriptions field description m_pdi_blanking_err mask th e pdi_blanking_err bit 1?b1: mask the pdi_blank_err interrupt 1?b0: do not mask the pdi_blank_err interrupt m_pdi_ecc_err2 mask the pdi_ecc_err2 bit 1?b1: mask the pdi_ecc_err2 interrupt 1?b0: do not mask the pdi_ecc_err2 interrupt m_pdi_ecc_err1 mask the pdi_ecc_err1 bit 1?b1: mask the pdi_ecc_err1 interrupt 1?b0: do not mask the pdi_ecc_err1 interrupt m_pdi_lock_lost mask the pdi_lock_lost bit 1?b1: mask the pdi_lock_lost interrupt 1?b0: do not mask the pd i_lock_lost interrupt m_pdi_lock_det mask the pdi_lock_det bit 1?b1: mask the pdi_lock_det interrupt 1?b0: do not mask the pdi_lock_det interrupt m_pdi_vsync_det mask the pdi_vsync_det bit 1?b1: mask the pdi_vsync_det interrupt 1?b0: do not mask the pdi_vsync_det interrupt m_pdi_hsync_det mask the pdi_hsync_det bit 1?b1: mask the pdi_hsync_det interrupt 1?b0: do not mask the pdi_hsync_det interrupt m_pdi_de_det mask th e pdi_de_det bit 1?b1: mask the pdi_de_det interrupt 1?b0: do not mask the pdi_de_det interrupt m_pdi_clk_lost mask th e pdi_clk_lost bit 1?b1: mask the pdi_clk_lost interrupt 1?b0: do not mask the pdi_clk_lost interrupt m_pdi_clk_det mask the pdi_clk_det bit 1?b1: mask the pdi_clk_det interrupt 1?b0: do not mask the pdi_clk_det interrupt
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-47 preliminary?subject to change without notice sig_err occurs when the area of interest for cal culating crc value is progr ammed with values which are outside the display. hwc_err occurs if size of cu rsor programmed is greater th an memory size (256x32). see section 12.4.5, hardware cursor, for further details on how cursor can be programmed. offset 0x22c access: user read/write 0123456789101112131415 r 000000000000 rle_err hwc_err sig_err disp_err w w1cw1cw1cw1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 l3_parr_err l2_parr_err l1_parr_err l0_parr_err w w1cw1cw1cw1c reset0000000000000000 figure 12-38. parameter error stat us register (parr_err_status) table 12-32. parr_err_status field descriptions field description rle_err error signal to indicate that more than one layer has rle mode enabled. hwc_err interrupt signal to indicate hwc error. this can occur if hwc position is out of display area or cursor memory is bigger than the hwc size. when this occurs, the hwc is disabled. sig_err interrupt occurs whenever the area of intere st specified by sig_calc register is outside the display size. 1?b0: sig_err is not set 1?b1: sig_err is set disp_err interrupt occurs whenever width and height of display, pulse width (both vertical and horizontal sync) value is 0. 1?b0: disp_err is not set 1?b1: disp_err is set l3_parr_err interrupt occurs whenever there is an error in layer 3. 1?b0: parameter error is not set 1?b1: parameter error is set l2_parr_err interrupt occurs whenever there is an error in layer 2. 1?b0: parameter error is not set 1?b1: parameter error is set
pxd20 microcontroller reference manual, rev. 1 12-48 freescale semiconductor preliminary?subject to change without notice 12.3.4.29 mask_parr_err_status register figure 12-39 shows the mask regi ster for parameter error status register. l1_parr_err interrupt occurs whenever there is an error in layer 1. 1?b0: parameter error is not set 1?b1: parameter error is set l0_parr_err interrupt occurs whenever there is an error in layer 0. 1?b0: parameter error is not set 1?b1: parameter error is set offset 0x230 access: user read/write 0123456789101112131415 r000000000000 m_rle_err m_hwc_err m_sig_err m_disp_err w reset0000000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 m_l3_parr_err m_l2_parr_err m_l1_parr_err m_l0_parr_err w reset0000000000001111 figure 12-39. mask parameter error status register (mask_parr_err_status) table 12-33. mask_parr_err_status field descriptions field description m_rle_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt m_hwc_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt m_sig_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt table 12-32. parr_err_status field descriptions (continued) field description rle_err error signal to indicate that more than one layer has rle mode enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-49 preliminary?subject to change without notice 12.3.4.30 threshold_input buf_1 register figure 12-40 shows the threshold re gister for input buffer. m_disp_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt m_l3_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt m_l2_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt m_l1_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt m_l0_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt offset 0x234 access: user read/write 0123456789101112131415 r0 inp_buf_p2_hi 0 inp_buf_p2_lo w reset0111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 inp_buf_p1_hi 0 inp_buf_p1_lo w reset0111111100000000 figure 12-40. threshold input buffer 1 register (threshold_input buf_1) table 12-34. threshold_inpu t buf_1 field descriptions field description inp_buf_p2_hi high threshold for input buffer for plane 2 (fgplane) inp_buf_p2_lo low threshold for input buffer for plane 2 (fgplane) inp_buf_p1_hi high threshold for input buffer for plane 1 (bgplane) inp_buf_p1_lo low threshold for input buffer for plane 1 (bgplane) table 12-33. mask_parr_err_status field descripti ons (continued) field description
pxd20 microcontroller reference manual, rev. 1 12-50 freescale semiconductor preliminary?subject to change without notice 12.3.4.31 luma componen t register (luma) figure 12-41 represents the luma component register. 12.3.4.32 red chroma components (red) figure 12-42 represents the red chro ma component register. offset 0x23c access: user read/write 0123456789101112131415 r y_red 0 y_green[0:4] w reset1001010100010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y_green[5:9] 0 y_blue w reset1010001001010100 figure 12-41. luma component register (luma) table 12-35. luma field descriptions field description y_red luminance coefficient for red matrix y_green luminance coefficient for green matrix y_blue luminance coefficient for blue matrix offset 0x240 access: user read/write 0123456789101112131415 r00000 cr_red w reset0000001100110001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_red w reset0000000000000000 figure 12-42. red chroma component register (red)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-51 preliminary?subject to change without notice 12.3.4.33 green chroma com ponent register (green) figure 12-43 represents the green chroma component register 12.3.4.34 blue chroma component register (blue) figure 12-44 represents the blue ch roma component register. table 12-36. red field descriptions field description cr_red cr coefficient for red matrix cb_red cb coefficient for red matrix offset 0x244 access: user read/write 0123456789101112131415 r00000 cr_green w reset0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_green w reset0000111100111000 figure 12-43. green chroma component register (green) table 12-37. green field descriptions field description cr_green cr coefficient for green matrix cb_green cb coefficient for green matrix
pxd20 microcontroller reference manual, rev. 1 12-52 freescale semiconductor preliminary?subject to change without notice 12.3.4.35 crc_pos register figure 12-45 represents the crc_pos register. offset 0x248 access: user read/write 0123456789101112131415 r00000 cr_blue w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_blue w reset0000010000001001 figure 12-44. blue chroma component register (blue) table 12-38. blue field descriptions field description cr_blue cr coefficient for blue matrix cb_blue cb coefficient for blue matrix offset 0x24c access: user read/write 0123456789101112131415 r crc_pos[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r crc_pos[16:31] w reset0000000000000000 figure 12-45. crc_pos register table 12-39. crc_pos field descriptions field description crc_pos crc position value calculated for safety enabled layers to be presented to the software for comparison
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-53 preliminary?subject to change without notice 12.3.4.36 fg0_fcolor register figure 12-46 represents the fg0_fcolor register. 12.3.4.37 fg0_bcolor figure 12-47 represents the fg0_bcolor register. offsets: 0x250 (fg0_fcolor) 0x258 (fg1_fcolor) 0x260 (fg2_fcolor) 0x268 (fg3_fcolor) access: user read/write 0123456789101112131415 r00000000 fg0_fcolor[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fg0_fcolor[8:23] w reset0000000000000000 figure 12-46. fg0_fcolor register table 12-40. fg0_fcolor field descriptions field description fg0_fcolor foreground color for layer fg0 for pre-blending engine offsets: 0x254 (fg0_bcolor) 0x25c (fg1_bcolor) 0x264 (fg2_bcolor) 0x26c (fg3_bcolor) access: user read/write 0123456789101112131415 r00000000 fg0_bcolor[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fg0_bcolor[8:23] w reset0000000000000000 figure 12-47. fg0_bcolor register
pxd20 microcontroller reference manual, rev. 1 12-54 freescale semiconductor preliminary?subject to change without notice 12.3.4.38 lyr_intpol_en figure 12-48 represents the lyr_intpol_en register. 12.3.4.39 lyr_luma_component figure 12-49 represents the layer lu ma component register. table 12-41. fg0_bcolor register field descriptions field description fg0_bcolor background color for layer fg0 for pre-blending engine offset: 0x2d0 access: user read/write 0123456789101112131415 r en 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-48. lyr_intpol_en register table 12-42. lyr_intpol_en field descriptions field description en interpolation enable bit for dculite layer coded in ycbcr422 format. this bit controls whether the chroma value for each pixel in the co.nversion from ycbcr 4:2:2 to 4:4:4 should use interpolation or the same value for both pixels 0 chroma value is same for two pixels 1 interpolation is enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-55 preliminary?subject to change without notice 12.3.4.40 lyr_chroma_red figure 12-50 represents the layer red chroma component register. offset: 0x2d4 access: user read/write 0123456789101112131415 r y_red 0 y_green[0:4] w reset1001010100010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y_green[5:9] 0 y_blue w reset1010001001010100 figure 12-49. layer luma component register (lyr_luma_component) table 12-43. lyr_luma_com ponent field descriptions field description y_red luminance coefficient for red matrix y_green luminance coefficient for green matrix y_blue luminance coefficient for blue matrix offset: 0x2d8 access: user read/write 0123456789101112131415 r00000 cr_red w reset0000001100110001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_red w reset0000000000000000 figure 12-50. layer red chroma component register (lyr_chroma_red) table 12-44. lyr_chroma_red field descriptions field description cr_red cr coefficient for red matrix cb_red cb coefficient for red matrix
pxd20 microcontroller reference manual, rev. 1 12-56 freescale semiconductor preliminary?subject to change without notice 12.3.4.41 lyr_chroma_green figure 12-51 represents the layer green chroma component register. 12.3.4.42 lyr_chroma_blue figure 12-52 represents the layer blue chroma component register. offset: 0x2dc access: user read/write 0123456789101112131415 r00000 cr_green w reset0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_green w reset0000111100111000 figure 12-51. layer green chroma co mponent register (lyr_chroma_green) table 12-45. lyr_chroma_green field descriptions field description cr_green cr coefficient for green matrix cb_green cb coefficient for green matrix offset: 0x2e0 access: user read/write 0123456789101112131415 r00000 cr_blue w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_blue w reset0000010000001001 figure 12-52. layer blue chroma component register (lyr_chroma_blue)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-57 preliminary?subject to change without notice 12.3.4.43 comp_imsize figure 12-53 represents the compression image size register. 12.3.4.44 global protection register figure 12-54 represents the global protection register. table 12-46. lyr_chroma_blue field descriptions field description cr_blue cr coefficient for blue matrix cb_blue cb coefficient for blue matrix offset: 0x2e4 access: user read/write 0123456789101112131415 r0000000000 comp_imsize[21:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r comp_imsize[15:0] w reset0000000000000000 figure 12-53. comp_imsize register table 12-47. comp_imsize field descriptions field description comp_imsize compressed image size in bytes for rle coded layer offset: 0x300 access: user read/write 0123456789101112131415 r hlb 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-54. global protection register
pxd20 microcontroller reference manual, rev. 1 12-58 freescale semiconductor preliminary?subject to change without notice 12.3.4.45 soft lock bit register l0 figure 12-55 represents the soft lock bit register for la yer0. this is used to protect the 7 control descriptor layer re gisters for layer0. table 12-48. global protection register field descriptions field description hlb hard lock bit. this bit cannot be cleared once it is set by software. it can only be cleared by a system reset. 1?b1:all slb?s are write protected & cannot be modified 1?b0:all slb?s are accessible & can be modified offset: 0x304 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l0_1 slb_l0_2 slb_l0_3 slb_l0_4 0000 slb_l0_5 slb_l0_6 slb_l0_7 0 w wen_lo_1 wen_lo_2 wen_lo_3 wen_lo_4 wen_lo_5 wen_lo_6 wen_lo_7 reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-55. soft lock register l0 table 12-49. soft lock register l0 field descriptions field description wen_l0_1 write enable for soft lock bit slb_l0_1 1?b1: value is written to slb 1?b0: slb is not modified wen_l0_2 write enable for soft lock bit slb_l0_2 1?b1: value is written to slb 1?b0: slb is not modified wen_l0_3 write enable for soft lock bit slb_l0_3 1?b1: value is written to slb 1?b0: slb is not modified wen_l0_4 write enable for soft lock bit slb_l0_4 1?b1: value is written to slb 1?b0: slb is not modified
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-59 preliminary?subject to change without notice 12.3.4.46 soft lock bit register l1 figure 12-56 represents the soft lock bit register for la yer1. this is used to protect the 7 control descriptor layer re gisters for layer1. slb_l0_1 soft lock bit for control desc l0_1 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l0_2 soft lock bit for control desc l0_2 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l0_3 soft lock bit for control desc l0_3 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l0_4 soft lock bit for control desc l0_4 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable wen_l0_5 write enable for soft lock bit slb_l0_5 1?b1: value is written to slb 1?b0: slb is not modified wen_l0_6 write enable for soft lock bit slb_l0_6 1?b1: value is written to slb 1?b0: slb is not modified wen_l0_7 write enable for soft lock bit slb_l0_7 1?b1: value is written to slb 1?b0: slb is not modified slb_l0_5 soft lock bit for control desc l0_5 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l0_6 soft lock bit for control desc l0_6 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l0_7 soft lock bit for control desc l0_7 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable table 12-49. soft lock register l0 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 12-60 freescale semiconductor preliminary?subject to change without notice offset: 0x308 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l1_1 slb_l1_2 slb_l1_3 slb_l1_4 0000 slb_l1_5 slb_l1_6 slb_l1_7 0 w wen_l1_1 wen_l1_2 wen_l1_3 wen_l1_4 wen_l1_5 wen_l1_6 wen_l1_7 reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-56. soft lock register l1 table 12-50. soft lock register l1 field descriptions field description wen_l1_1 write enable for soft lock bit slb_l1_1 1?b1: value is written to slb 1?b0: slb is not modified wen_l1_2 write enable for soft lock bit slb_l1_2 1?b1: value is written to slb 1?b0: slb is not modified wen_l1_3 write enable for soft lock bit slb_l1_3 1?b1: value is written to slb 1?b0: slb is not modified wen_l1_4 write enable for soft lock bit slb_l1_4 1?b1: value is written to slb 1?b0: slb is not modified slb_l1_1 soft lock bit for control desc l1_1 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l1_2 soft lock bit for control desc l1_2 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l1_3 soft lock bit for control desc l1_3 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l1_4 soft lock bit for control desc l1_4 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-61 preliminary?subject to change without notice 12.3.4.47 soft lock disp_size register figure 12-57 represents the soft lock disp_size register. wen_l1_5 write enable for soft lock bit slb_l1_5 1?b1: value is written to slb 1?b0: slb is not modified wen_l1_6 write enable for soft lock bit slb_l1_6 1?b1: value is written to slb 1?b0: slb is not modified wen_l1_7 write enable for soft lock bit slb_l1_7 1?b1: value is written to slb 1?b0: slb is not modified slb_l1_5 soft lock bit for control desc l1_5 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l1_6 soft lock bit for control desc l1_6 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l1_7 soft lock bit for control desc l1_7 register. th is bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x30c access: user read/write 0123456789101112131415 r0 0 0 0 slb_disp 00000000000 w wen_disp reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-57. soft lock disp_size register table 12-50. soft lock register l1 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 12-62 freescale semiconductor preliminary?subject to change without notice 12.3.4.48 soft lock hsy nc/vsync para register figure 12-58 represents the soft lock hsync/vsync register. table 12-51. soft lock disp_size register field descriptions field description wen_disp write enable for soft lock bit slb_disp 1?b1: value is written to slb 1?b0: slb is not modified slb_disp soft lock bit for disp_size register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x310 access: user read/write 0123456789101112131415 r0 0 0 0 slb_hsync slb_vsync 0000000000 w wen_hsync wen_vsync reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-58. soft lock hsync/vsync para register table 12-52. soft lock hsync/vsync p ara register field descriptions field description wen_hsync write enable fo r soft lock bit slb_hsync 1?b1: value is written to slb 1?b0: slb is not modified wen_vsync write enable fo r soft lock bit slb_vsync 1?b1: value is written to slb 1?b0: slb is not modified
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-63 preliminary?subject to change without notice 12.3.4.49 soft lock pol register figure 12-59 represents the soft lock pol register. 12.3.4.50 soft lock l0_transp register figure 12-60 represents the soft lo ck l0_transp register. slb_hsync soft lock bit for hsync register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_vsync soft lock bit for vsync register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x314 access: user read/write 0123456789101112131415 r0 0 0 0 slb_pol 00000000000 w wen_pol reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-59. soft lock pol register table 12-53. soft lock pol register field descriptions field description wen_pol write enable fo r soft lock bit slb_pol 1?b1: value is written to slb 1?b0: slb is not modified slb_pol soft lock bit for syn_pol register. this bit c annot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable table 12-52. soft lock hsync/vsync para register field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 12-64 freescale semiconductor preliminary?subject to change without notice 12.3.4.51 soft lock l1_transp register figure 12-61 represents the soft lock l1_transp register offset: 0x318 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l0_fcolor slb_l0_bcolor 0000000000 w wen_l0_fcolor wen_l0_bcolor reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-60. soft lock l0_transp register table 12-54. soft lock l0_transp register field descriptions field description wen_l0_fcolo r write enable for soft lock bit slb_l0_fcolor 1?b1: value is written to slb 1?b0: slb is not modified wen_l0_bcolo r write enable for soft lo ck bit slb_l0_bcolor 1?b1: value is written to slb 1?b0: slb is not modified slb_l0_fcolor soft lock bit for l0_fcolor register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l0_bcolor soft lock bit for l0_b color register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-65 preliminary?subject to change without notice 12.4 functional description the dculite is a master on the crossbar switch. it fetches graphic source in formation directly from memory and dynamically performs blending and bit-blitting operations before delivering data to a tft lcd panel. offset: 0x31c access: user read/write 0123456789101112131415 r0 0 0 0 slb_l1_fcolor slb_l1_bcolor 0000000000 w wen_l1_fcolor wen_l1_bcolor reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000010000001001 figure 12-61. soft lock l1_transp register table 12-55. soft lock l0_transp register field descriptions field description wen_l1_fcolo r write enable for soft lock bit slb_l1_fcolor 1?b1: value is written to slb 1?b0: slb is not modified. wen_l1_bcolo r write enable for soft lo ck bit slb_l1_bcolor 1?b1: value is written to slb 1?b0: slb is not modified. slb_l1_fcolor soft lock bit for l1_fcolor register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable slb_l1_bcolor soft lock bit for l1_b color register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1:associated protected register is locked for write access 1?b0:associated protected regist er is not locked & writeable
pxd20 microcontroller reference manual, rev. 1 12-66 freescale semiconductor preliminary?subject to change without notice 12.4.1 graphic sources as the dculite is a master on the crossbar switch, it can access directly any memo ry or device connected to the crossbar switch as a slave. this includes al l on-chip flash, all on-chip ram, and any slave capable of providing high enough data rates, such as, for exam ple an expanded bus interfa ce or a quadspi module. therefore, any compatible graphic stored anywhere on -chip or in an accessible interface can be displayed on the connected tft lcd panel with no further inte rvention from the cpu, except to program the dculite to fetch and place it. the dculite also incl udes a dedicated memory to store the graphic for its cursor layer. 12.4.2 tft lcd panel configuration the nature and timing of the signals required by tf t lcd panels vary greatly between manufacturers. therefore, the dculite allows highly flexible and detailed configuration of these signals. timing diagrams for tft lcd panels are typically divided into a horiz ontal timing chart and a vertical timing chart. see figure 12-62 for details.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-67 preliminary?subject to change without notice figure 12-62. hsync and vsync timing diagram the number of pixel data slots in the horizontal timing diagram is defi ned by the width of the panel. the number of line data slots is define d by the height of the panel. both of these values are defined in the disp_size register (delta_x, delta_y). the width of the panel must always be defined as a multiple of 16. the timing of the pixel clock is defined by the div_ratio register and the frequency of the clock supplied to the dculite. in addition to defining the number a nd timing of pixels in each line and the number of lines, it is normal for tft lcd panel manufacturers to de fine other timing signals in terms of pixel clock pe riods or of the number of horizontal lines. the dcul ite also follows this convention. if the tft lcd panel requires a horizontal synchroni zing signal (hsync) and/or a data enable signal, then these can be configured usi ng the fields in the hsyn_para re gister. hsync provides a pulse to give the panel notice that the next line of pixel data is about to start, and the data enable signal indicates when that data is present. the pw _h bit field indicates th e width of the hsync pulse , in pixel data clock pclk pixel data invalid data 12 3 4 invalid data pw_h bp_h fp_h delta_x hsync data enable hsync invalid data invalid data 1 2 3 4 delta_y bp_v pw_v fp_v line data vsync data enable 1/rr where rr is the frame refresh rate delta_x is the horizontal resolution of the display delta_x ?? 1 (de) (de)
pxd20 microcontroller reference manual, rev. 1 12-68 freescale semiconductor preliminary?subject to change without notice periods. the bp_h bit field defines the delay between the end of the hsync pulse and the start of the data enable signal (and pixe l data delivery), in pixel clock peri ods. the fp_h bit field defines the delay between the end of the data enable signal (and pixel data delivery) and the ne xt hsync pulse, in pixel clock periods. fp_h and bp_h have minimum values of 1. if the tft lcd panel require s a vertical synchronizing signal (vsync), then this can be configured using the fields in the vsyn_para register. vsync provide s a pulse to give the pa nel notice that the next frame of pixel data lines is about to start, and the pa nel defines delays before a nd after this pul se, in terms of pixel clock periods. the pw_v bi t field indicates the width of th e vsync pulse in horizontal line periods. the bp_v bit field defines the delay between the end of the vsync pulse and the start of the next pixel data (data enable signa l), in horizontal line periods. the fp_v bit field defines the delay between the end of the last pixel data (data enable signal) and the next vsync pulse, in horizontal line periods. fp_v and bp_v ha ve minimum values of 1. the polarity of all these signals, including the pixel data itself, may be inverted by using the control bits in the syn_pol register. the refresh rate for the pa nel can be calculated using equation 12-1 and equation 12-2 below. eqn. 12-1 where: pix_clk is the pixel clock delta_x is the horizontal resolution (in pixels) delta_y is the vertical resolution (in pixels) fp_h is the hsync front porch pulse width (in pixel clock cycles) bp_h is the hsync back porch pul se width (in pixel clock cycles) pw_h is the hsync active pulse width (in pixel clock cycles) fp_v is the vsync front porch pulse width (in pixel clock cycles) bp_v is the vsync back porch pul se width (in pixel clock cycles) pw_v is the vsync active pulse width (in pixel clock cycles) pixel clock = (dculite clock) / prescale value eqn. 12-2 where prescale value is an integer value that can range from 2?32. 12.4.3 dculite mode selection and background color once the dculite is configured for us e with a particular tft lcd panel, it can be enabled for use. there are five modes to choose from, as shown in table 12-56 . table 12-56. list of dculite operating modes mode dcu_mode[1:0] pdi_en description off 00 x dculite disabled; the tft lcd panel is not driven. color bar 11 x dculite displays a test pattern consisting of vertical bands of programmable color. rr pix_clk delta_xfp_hpw_hbp_h ++ + ?? delta_yfp_vpw_vbp_v ++ + ?? ? --------------------- --------------------- --------------------- --------------------- ---------------------- --------------------- ------------------ ---------------- - =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-69 preliminary?subject to change without notice the dcu_mode, pdi_en and pdi_slave_mode cont rol bits are in the dcu_mode register. the dculite has an interface enable bit for the tft lc d panel interface called raster_en, also in the dcu_mode register. when raster_en is 0 the raster scanning of pixels to the panel is disabled but the pixel clock continues if enabled on the i/o pin. color bar mode is intended for testing the interface between the dculite and the tft lcd panel. in this mode, the panel is divided into eight vertical strips of equal width, and the strips display a single color whose rgb value is specified in the colbar_1 to colb ar_8 registers. at reset, the colors are set to black, blue, cyan, green, yellow, red, magenta, and white, where positive logic for the rgb values is assumed. the mode can be used to verify correct connection of the in terface to the dculite and correct timing configuration of the interface. in this m ode, any layer configurati on settings are ignored. in normal mode, the dculite operates according to the timings specified in section 12.4.2, tft lcd panel configuration , and displays graphics accordi ng to the configuration of its layers. the bgnd register sets the rgb color of the background shown when no ot her layers are present. this background color is included in the layer blending proces s but, since it is always the bac kground, it does not include any layer blending settings. in pdi normal mode, the dculite adopts the timing provided on the pdi interface and replaces the background color by the pixel data co ming from the pdi inte rface. the timing values set in the dculite are ignored in this mode, and the pixel clock and synchronization signals are taken from the pdi interface and passed to the tft lcd pa nel. the content of the pa nel is a combination of the incoming pixel stream and layers generated by the dculite. pdi slave mode allows the dculit e to synchronize with the extern al timing signals on the pdi input. 12.4.4 layer configuration and blending users control the graphical content of the tft panel by manipulating the configurat ion of elements in the dculite called layers. ea ch layer has a control de scriptor that defines the size, position, memory encoding, blending, and memory location of the gr aphic to be displayed. the dculite provides 16 independent layers that are identical except that they have a fixed pr iority with respect to each other, and this affects how individual pixels are blended when layers overlap. the ble nding setting on each layer allows the pixels on that layer to be opaque, partially transparent, or fu lly transparent, which allows them to combine with pixels on othe r layers that they overlap. normal 01 0 dculite blends layers and displays result on tft lcd panel. pdi normal 01 1 as normal mode, except that the panel timing is defined by the input on the pdi interface, and the background color is replaced by the content provided on the pdi interface. pdi slave 01 0 the dculite synchronizes its timing to an external signal when pdi_slave_mode is enabled. table 12-56. list of dculite operating modes mode dcu_mode[1:0] pdi_en description
pxd20 microcontroller reference manual, rev. 1 12-70 freescale semiconductor preliminary?subject to change without notice 12.4.4.1 blending pr iority of layers the 4 layers available in the dculite are each fixed in priority order, with layer 0 being the highest priority, layer 1 being the second highest priority, and so on until layer 3, which is the lowest priority. the priority is used by the dculite to de fine how to blend individual pixels within the layers. for example, if layer 0 is defined as not being blended w ith other layers and a pixel on la yer 0 overlaps a pixel on layer 1 then the pixel on layer 0 will be vi sible on the panel unchanged by the pi xel on layer 1. ho wever, if layer 0 is defined as being partially transparent, then the dculite will blend the overlapping pixel such that the result is a combination of the pixel on layer 0 and th e pixel on layer 1. it is pos sible to blend up to four layers at each pixel position. as there is a maximum number of layers that can ble nded together, then any pixe l on a layer that is lower than the threshold priority will not be included in a ny blend. if a pixel is on a layer that has the lowest priority in any blending sche me, then the blending settings for that pi xel are ignored and th e pixel is treated as a background pixel. this means th at a lower priority layer may have some pixels completely obscured by those on higher priority layers on one part of the panel, and some ot her pixels visible or blended on other parts of the panel. figure 12-63 shows how the pixel blend takes place inside the dculite. the priority of the layers determines at which stage of the bl end the pixel enters. any pixels lowe r than the threshold priority are ignored and, as can be seen, the blend settings for the lowest priority pixel is also ignored. figure 12-63. pixel blending stack this priority concept is illustrated in figure 12-64 and figure 12-65 . in this case, there are five layers enabled, and each contains a graphi c that is a solid rectangular block of a single color. the size and shape of each layer is different. the background color of the pane l is set to grey and layers have been placed such that they overlap each other. figure 12-64 shows the individual source gr aphics and the case where no la yer has any blending enabled. here, the highest priori ty layer (in this case layer 0) is fully visible. layer 1 is visibl e where layer 0 does not overlap it. layer 2 is visible wh ere layer 1 does not over lap it. layer 3 is overl apped by layers 0 and 1 and so is only partiall y visible. layer 4 is partially obscured by all of the other layers. no te that layer 4 is higher priority than the background color. blend1 higher priority pixel lowest priority pixel two-plane blending result note: all blend stages use the blending settings defined for the upper pixel.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-71 preliminary?subject to change without notice figure 12-64. example of layer placement with no blending figure 12-65 shows the same layer configuration except that, in this case, layer 0 and layer 3 have been made 50% transparent. the pixels in layer 0 are blended with those on the layers below including layer 3. however, notice that in the area where layer 0 ove rlaps layer 3 there is no further blending with the underlying layer 4 or the background. this is b ecause the dculite can only blend two layers. figure 12-65. example of layer placement with 3-layer blending
pxd20 microcontroller reference manual, rev. 1 12-72 freescale semiconductor preliminary?subject to change without notice all blending is performed using full 8-bits-per-component colors. the dculite automatically performs a color promotion on source data that is stored in less than rgb888 color. 12.4.4.2 control descriptors the control descriptor for each layer consists of seven registers, and al l 4 control descriptors are identical except the two highest priority layers, which have additional control bits for the safety mode. the control descriptors may be written to at any time, and the value presen t in the registers at the start of the next frame refresh cycle defines the content of the panel for that frame. to avoid coherency issues, ensure all control descriptor cha nges are made before the prog_end bi t in the int_status register is asserted. 12.4.4.3 layer size and positioning the size of each layer is defined by register 1 in the control descriptor fo r the layer (ctrldescln_1, where n is the layer number). the re gister contains two b it fields, height and wi dth, which determine the size and shape of the layer. both fields are e xpressed in terms of the number of pixels in each dimension. the height bit field may take any va lue; however, it may not be useful to define a value larger than the height of the panel. the width field has a restriction on the value it ca n take, depending on the data format of the graphic specified by the layer. this field must always be an integer multiple of the number of pixels that are represented by a 32-bit word except in the special case of 1 bit per pixel where th e multiple is 16. the data format can range from 1 bit per pixel to 32 bits per pixe l and so there is a range of multiples from 1 to 32. figure 12-57 shows the multiples for the width bit field and some correct values. if the width bit field is se t to an invalid multiple, then the layer configuration is inva lid, the layer cannot be made visible, and an error flag is set in the layer parameter error register (parr_err). the position of each layer on the panel is defined by re gister 2 in the control descriptor for the layer (ctrldescln_2, where n is the layer number). the re gister contains two bit fields, posy and posx, table 12-57. example of width multiples for different graphic data formats data format width multiples example values 1 bpp 16 16, 32, 48, 64, ? 2 bpp 16 16, 32, 48, 64, ? 4 bpp 8 8, 16, 24, 32, ? 8 bpp 4 4, 8, 12, 16, ? 16 bpp 2 2, 4, 6, 8, ? 24 bpp 4 (= 3 whole 32-bit words) 4, 8, 12, 16 32 bpp 1 1, 2, 3, 4, ? ycbcr422 4 4, 8, 12, 16, ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-73 preliminary?subject to change without notice which determine the location of the upper left pixel of the layer in the x and y axes. both fields are expressed in terms of the numbe r of pixels in each axis. there are no restrictions on layer placement. any layer can be placed and moved to any panel position. if a layer is placed so that pixels would appear be yond the dimensions of the panel, then the dculite displays the pixels on the panel a nd ignores the pixels off the panel. 12.4.4.4 graphics and data format the memory location of the graphic that is displayed on the layer is defined by register 3 in the control descriptor for the layer (ctrldes cln_3, where n is the layer number). this 32-bit value can contain the address of any 64-bit aligned memory lo cation in the memory map of the mcu. the format of the data that describes the graphic is de fined by the bpp bit field in register 4 in the control descriptor for the layer (ctrldescl n_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 12.4.4.3, layer size and positioning ). by choosing an appropriate format, it is possible to optim ize the memory required by the graphics in use. there are five formats where the rgb values of the pi xels are stored directly in the graphic. in these formats, the dculite treats the data as de scribing a true rgb color. the formats are: ? bgra8888, where the data defines 8-bit values for the red, gree n, blue, and alpha components of the image. this blends as argb, however, in th is format the order of the bytes is reversed compared to other formats. ? rgb888, where the data defines 8- bit values for the red, green, a nd blue components of the image. ? rgb565 where the data defines 5-bi t values for the red and blue components, and 6-bit values for the green component of the image. ? argb1555 where the data de fines 5-bit values for the red, gree n, and blue components, and a 1-bit value for the alpha channel of the image. ? argb4444, where the data defines 4-bit values for the red, gree n, blue, and alpha components of the image. the three 16-bit formats (rgb 565, argb1555, and argb4444) are prom oted to full 8 bit per component format by shifting the bits left so that th e msb of the component in the 16-bit format becomes the msb of the 24/32 bpp (bit per pixel) format, and th e lsb is filled with the value of the msbs. for example, an rgb565 value of 10000:010000: 11011 becomes 10000100:01000001:11011110. an rgb4444 value of 1010:0011:1100:0101 b ecomes 10101010:00110011:11001100:01010101. an rgb1555 value of 1:10100:01000:11011 becomes 11111111:10100101:01000010:11011110. there are five indexed color formats (1/2/4/8 bpp & apal 8) where the data in the graphic does not define the rgb color to display. instead, th e data defines the entry in a color look-up table (clut) that contains a palette of argb colors. the maximu m number of colors in the clut is defined by the size of the data stored in the graphic. for 1 bpp graphics, there is a maximum of two colors in the clut. for 2 bpp, there is a maximum of four colors. fo r 4 bpp and 8 bpp data, the maximums are 16 and 256 colors, respectively. in apal8 mode(16 bpp), the upper 8 bits define the al pha component of the pixel and the lower 8 bits define the offset in the clut (the alpha component in the clut color is ignored).
pxd20 microcontroller reference manual, rev. 1 12-74 freescale semiconductor preliminary?subject to change without notice the address of the first value in th e clut is defined in the luoffs bi t field of register 4 and the clut is the ram block dedicated to th e dculite which is described in section 12.4.6, clut ram . since the argb values stored in the clut are 32-bit argb, there is no need for furt her adjustment before blending. the dculite also supports graphics encoded using lu minance and chrominance format. this format is generically known as yuv and stor es the luminance (brightness, y) of a pixel separate from its chrominance (color information, u a nd v). this format is widely used by cameras and is supported by the pdi for direct video in as well as the dculite when stored in memory fo r display on a layer. the specific implementation used by the dculite is more accurate ly described as ycbcr422 which uses twice as many bits to describe the luminance as to descri be the blue (cb) and red (cr) difference of the chrominance. the dculite takes these pixels and converts them to rgb format using equati ons configured using its lyr_luma_comp, lyr_chroma_red, lyr_ chroma_green, and lyr_chroma_blue registers. the ycbcr format specifies a common chroma setting for two pixels; however, it is possible to interpolate the chroma for the pixels rather than se tting both to the same value. due to the additional conversion step required, the dculit e is able to blend a maximum of one layer encoded in ycbcr for each pixel. this feature is enable d by the lyr_intpol_en[en] field (see section 12.8.1.6.3, ycbcr mode ). there are four additional formats de fined by the bpp bit field. these conf igure the graphic in transparency mode and luminance mode (see section 12.4.4.6, transparency mode and blending , and section 12.4.4.7, luminance mode , respectively). there is a set storage format for each data format pr ovided by the dculite. these formats can be seen in table 12-58 to table 12-67 . table 12-58. data layout for bgra8888 address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 b0 g0 r0 a0 b1 g1 r1 a1 0x08 b2 g2 r2 a2 b3 g3 r3 a3 table 12-59. data layout for ycbcr422 format 1 1 the ycbcr422 format encodes chroma information across two pi xels. therefore, the chroma values apply to the even pixel denoted in the table and its adjacent odd pixel. address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00cb0y0cr0y1cb2y2cr2y3 0x08cb4y4cr4y5cb6y6cr6y7
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-75 preliminary?subject to change without notice for 16 bpp, data expected is in the fo rm of rgb565, argb 1555, argb4444, or apal8. table 12-60. data layout for 24 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 b0 g0 r0 b1 g1 r1 b2 g2 0x08 r2 b3 g3 r3 b4 g4 r4 b5 table 12-61. generic data layout for 16 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel0[15:8] pixel0[7:0] pixel1[15:8] pixel1[7:0] pixel2[15:8] pixel2[7:0] pixel3[15:8] pixel3[7:0] 0x08 pixel4[15:8] pixel4[7:0] pixel5[15:8] pixel5[7:0] pixel6[15:8] pixel6[7:0] pixel7[15:8] pixel7[7:0] table 12-62. data layout for argb1555 format address offset [0] [1:5] [6:10] [11:15] [16] [17:21] [22:26] [27:31] 0x00 a0 r0 g0 b0 a1 r1 g1 b1 0x04 a2 r2 g2 b2 a3 r3 g3 b3 table 12-63. data layout for apal8 format address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 a0 offset 0 a1 offset 1 a2 offset 2 a3 offset 3 0x08 a4 offset 4 a5 offset 5 a6 offset 6 a7 offset 7 table 12-64. data layout for 8 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel0[0:7] pixel1[0:7] pixel2[0:7] pixel3[0: 7] pixel4[0:7] pixel5[0:7] pixel6[0:7] pixel7[0:7] 0x08 pixel8[0:7] pixel9[0:7] pixel10[0:7] pixel11[0:7] pixel12[0:7] pixel13[0:7] pixel14[0:7] pixel15[0:7] table 12-65. data layout for 4 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel1-pixel0 pixel3-pixel2 pixel5-pixel4 pixel7-pixel6 pixel9-pixel8 pixel11- pixel10 pixel13- pixel12 pixel15- pixel14 0x08 pixel17- pixel16 pixel19- pixel18 pixel21- pixel20 pixel23- pixel22 pixel25- pixel24 pixel27- pixel26 pixel29- pixel28 pixel31- pixel30
pxd20 microcontroller reference manual, rev. 1 12-76 freescale semiconductor preliminary?subject to change without notice the dculite includes a flag that in dicates when it has completed fetc hing graphics from memory for the current frame refresh. if required, this flag (dma_trans_finish in the int_status register) can be used to determine when changes can be made to the source graphic content. 12.4.4.5 alpha and chroma-key blending the blending configuration of each layer is defined by the bb, ab, and tr ans bit fields in register 4 in the control descriptor for the layer (ctrldescln_4, wh ere n is the layer number). the pixels affected by the blending configuration can be further selected by registers 5 and 6 in the control descriptor (ctrldescln_4 and ctrldescln_5). depending on the priority and placement of the layer (see section 12.4.4.1, blending pr iority of layers ), these bit fields a nd registers define how pixels from different layers are blended together. the ab and bb bit fields define whether blending is active and whethe r the whole graphic or a selected portion is blended. registers 5 and 6 define the range of rgb colors that define the selected pixels. the trans bit field defines the transp arency of the selected pixels. the bb bit field defines wh ether the whole graphic, or only certain pixels, should be blended. when this bit is set, pixels that have an rg b value that falls into the range defi ned by registers 5 a nd 6 are considered to be selected and treated differentl y to the non-selected pixels in the graphic. this is a process known as chroma-keying since it is the color of the pixel that defines the selection. the selected pixels must be within the range defined by each color component of registers 5 and 6. see table 12-68 for examples of pixels that are selected and not selected when the given range is defined as 0x0080c0 to 0x0fb0ff. table 12-66. data layout for 2 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel3-pixel0 pixel7-pixel4 pixel11- pixel8 pixel15- pixel12 pixel19- pixel16 pixel23- pixel20 pixel27- pixel24 pixel31- pixel28 0x08 pixel35- pixel32 pixel39- pixel36 pixel43- pixel40 pixel47- pixel44 pixel51- pixel48 pixel55- pixel52 pixel59- pixel56 pixel63- pixel60 table 12-67. data layout for 1 bpp address offset [0:7] [8:15] [16:23] [24:31] [0:7] [8:15] [16:23] [24:31] 0x00 pixel7-pixe l0 pixel15-pix el8 pixel23-pix el16 pixel31-pix el24 pixel39-pix el32 pixel47-pix el40 pixel55-pix el48 pixel63-pix el56 0x08 pixel71-pix el64 pixel79-pix el72 pixel87-pix el80 pixel95-pix el88 pixel103-pi xel96 pixel11-pix el104 pixel119-pi xel112 pixel127-pi xel120 table 12-68. example of how chroma-key range selects pixels source pixel red 00?0f green 80?b0 blue c0?ff comment 0x000000 p x x not selected
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-77 preliminary?subject to change without notice the ab bit field defines how any se lected and non-selected pixels are blended. by combining this control with the bb bit field it is possible to define 11 unique ways of blending the pixels on a layer dependent on the type of layer. depending on the configuration defined by the ab and bb bit fields, th e trans bit field combines the two pixels in every blend stage using the alpha value of the upper pi xel (which has the effect of making this pixel more or le ss transparent and revealing more or less of the lower pixel). the result of each blend stage is calculated for all three color components as shown in equation 12-3 . a = (bgpixel*(255 -alpha)) + (fgpixel * alpha) eqn. 12-3 the result of the calculation must then be divide d by 255 to normalize the result. this calculation is performed as follows: //first division output_val = a + (a >> 8) //rounding off first addition & division if (((a>>7) & 0x1) == 0x1) output_val ++ //second division with rounding output_val = output_val >>7; if ((output_val & 0x1) == 0x1)) output_val = output_val + 0x2; output_val = output_val >> 1; the blend can apply to pixels with no alpha channel (rgb) or with an alpha channel (argb) in different ways. table 12-69 defines how the settings of the bb and ab bit fields affect the pi xels in the layer; rgb formats are rgb565, and rgb888; argb formats are 1 bpp, 2 bpp, 4 bpp, 8 bpp, apal8, argb1555, argb4444, and bgra8888. pixels in ycbc r format are treated as rgb pixels for the purposes of the blend. 0x08c0c0 p x p not selected 0x08a0c0 p p p pixel is selected table 12-69. blend options for bb and ab configurations case bb ab format function 1 0 00 rgb no blending, underlying pixels are obscured 2 1 00 rgb selected pixels are completely removed table 12-68. example of how chroma-key range selects pixels source pixel red 00?0f green 80?b0 blue c0?ff comment
pxd20 microcontroller reference manual, rev. 1 12-78 freescale semiconductor preliminary?subject to change without notice figure 12-66 to figure 12-74 illustrate the effect of the cases identified in table 12-69 . in all cases there is a single active layer and a white background color. 3 0 01 rgb the value in trans becomes the alpha channel of all pixels on the layer 4 1 01 rgb the value in trans becomes the alpha channel of the selected pixels on the layer 5 0 10 rgb same as case 3 6 1 10 rgb selected pixels are completely removed and the value in trans becomes the alpha channel of the non-selected pixels on the layer 7 0 11 rgb reserved 8 1 11 rgb reserved 9 0 00 argb no blending, pixel alpha is ignored and underlying pixels are obscured 10 1 00 argb selected pixels are complete ly removed, pixel alpha is ignored 11 0 01 argb pixel alpha is used to blend layer with underlying pixels. value in trans is ignored. 12 1 01 argb uses the pixel alpha of the selected pixels only to blend layer with underlying pixels. value in trans is ignored. 13 0 10 argb the value in trans is multiplied with the pixel alpha value and the resultant alpha is used to blend all the pixels 14 1 10 argb selected pixels are completely removed, the value in trans is multiplied with the pixel alpha value and the resultant alpha is used to blend the non-selected pixels on the layer 15 0 11 argb reserved 16 1 11 argb reserved table 12-69. blend options for bb and ab configurations (continued) case bb ab format function
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-79 preliminary?subject to change without notice figure 12-66. case 1 example (no blend) figure 12-67. case 2 example (remove selected pixels)
pxd20 microcontroller reference manual, rev. 1 12-80 freescale semiconductor preliminary?subject to change without notice figure 12-68. case 3 example (all pixels transparent) figure 12-69. case 4 example (selected pixels transparent)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-81 preliminary?subject to change without notice figure 12-70. case 6 example (selected pixels removed, others transparent) figure 12-71. case 9 example ( no blend, pixel alpha ignored)
pxd20 microcontroller reference manual, rev. 1 12-82 freescale semiconductor preliminary?subject to change without notice figure 12-72. case 10 example (selected pixels removed, pixel alpha ignored) figure 12-73. case 13 example (pixel and layer alpha used in blend)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-83 preliminary?subject to change without notice figure 12-74. case 14 example (selected pixels removed, pixel and layer alpha used in blend) 12.4.4.6 transparency mode and blending transparency mode is a special case for the graphic data format and is defined by the bpp bit field in register 4 in the control descriptor for the laye r (ctrldescln_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 12.4.4.3, layer size and positioning ). by choosing an appropriate format, it is possible to optimize the memory required by the graphics in use. in transparency mode, the source gr aphic does not contain a ny direct or indexed co lor information. instead, the graphic data represents the alpha channel of th e graphic. the dculite creates the final graphic by pre-blending a foreground colo r and background color using the alpha va lue of each pixel. the result of this pre-blend can then be blended with pixels on other layers using the normal blending process. each layer has dedicated registers to contain the foreground and background colors for this mode. these are fgn_fcolor and fgn_bcolor, wher e n is the layer number. see figure 12-75 .
pxd20 microcontroller reference manual, rev. 1 12-84 freescale semiconductor preliminary?subject to change without notice figure 12-75. transparency mode description transparency mode is typically used when a graphi c must blend smoothly into the underlying layers, but where a rich color palette is not re quired. examples include te xt where this mode allo ws the text to blend smoothly with any background ? th is is known as anti-aliasing. there are two transparency modes available: 4 bpp a nd 8 bpp. the result of the pre-blend can be treated as an rgb888 graphic and ble nded in a similar way to prev iously described, or it can be treated as a special case of argb with only the foregr ound color visible in the final blend. table 12-70 describes the blend options for transparency mode. table 12-70. blend options for transparency mode case bb ab[1:0] mode function 1 0 00 transparency no blending, underlying pixels are obscured 2 1 00 transparency reserved 3 0 01 transparency the value in trans becomes the alpha channel of all pixels on the layer 4 1 01 transparency the value in trans becomes the alpha channel of the selected pixels on the layer 5 0 10 transparency same as case 3 6 1 10 transparency background color is igno red, selected pixels are completely removed, the value in trans is multiplied with the graphic data value (alpha) and the resultant alpha is used to blend the non-selected pixels on the layer 7 0 11 transparency reserved 8 1 11 transparency reserved 8 bpp 4 bpp layer data <<4 alpha a8 pre blend engine fc bc la argb8888 plane 1-4 forecolor rgb888 back color rgb888 layeralpha a8
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-85 preliminary?subject to change without notice figure 12-76 ? figure 12-79 illustrate the effect of the cases identified in table 12-70 . in all cases there is a single active transparency layer and a white background color. figure 12-76. case 1 example (no blend) figure 12-77. case 3 example (all pixels transparent) transparency graphic foreground color background color panel
pxd20 microcontroller reference manual, rev. 1 12-86 freescale semiconductor preliminary?subject to change without notice figure 12-78. case 4 example (selected pixels transparent) figure 12-79. case 6 example (only foreground color blended) 12.4.4.7 luminance mode luminance mode is a special case for the graphic da ta format and is defined by the bpp bit field in register 4 in the control descriptor for the laye r (ctrldescln_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 12.4.4.3, layer size and
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-87 preliminary?subject to change without notice positioning ). by choosing an appropriate format, it is possible to optimize the memory required by the graphics in use. in luminance mode, the data in the source graphic does not contain any di rect or indexed color information or alpha information. the data values in a layer in luminance mode modify the values of the pixels on underlying layers only. there are two luminance modes available: 4 bpp and 8 bpp. in both cases, the data values behave as signed integers that are added to each component of the underlyi ng pixel. the 4 bpp mode is left-shifted to form a signed 8 bpp integer. the re sults of the addition are pr evented from overflowing, so that any result greater than 0xff is set to 0xff and any result less than 0x00 is set to 0x00. the result of a blend with a luminance layer is that the intensity of the underlyi ng pixel's color will be increased or decreased. in this way, luminance mode can be used to hi ghlight or dim pixels on the panel without having to modify the source graphic data. table 12-71 describes the effect of luminance blends on an underlying pixel. 12.4.4.8 tile mode tile mode is a special case for the la yer and is enabled by the tile_en bit field in register 4 in the control descriptor for the layer (ctrldescl n_4, where n is the layer number). in this mode the layer size register (ctrldescln_1, wh ere n is the layer number) defines the size of the layer; however, the size of the graphic is defined in control register 7 (c trldescln_7, where n is the layer number). the size of th e graphic must be less than or equal to the size of the laye r. when tile mode is enabled, the graphic is repeated horizontally and vert ically until it fills the whole layer. the horizontal size of the tile is defined by the ti le_hor_size bit field and is restricted to be a multiple of 16 pixels. the vertical size of the tile is defi ned by the tile_ver_size bit field. see figure 12-80 for an example of a layer in tile mode. the graphic data for the tile mode is fetched from the mcu memory according to the a ddress in control descriptor 3 and can be in any pr eviously-described data format. table 12-71. example of a blend with a luminance mode layer pixel value luminance value resultant pixel 0xff8040 0x40 0xffc080 0xff8040 0xc0 0x3f0000
pxd20 microcontroller reference manual, rev. 1 12-88 freescale semiconductor preliminary?subject to change without notice figure 12-80. tile mode 12.4.5 hardware cursor in addition to the 4 layers, the dc ulite also provides a special layer intended for use as a cursor. this cursor operates in 1 bpp mode and includes its own ra m area to store the graphic. the cursor may be placed at any location on the panel and includes an automatic blink option. the hardware cursor is configured using a dedica ted control descriptor. the size of the cursor is defined by register 1 in the control descriptor for the cursor (ctrldesccursor_1). the register contains two bit fields, height and width, which determine the size and shape of the layer. both fields are e xpressed in terms of the number of pixels in each dimension. the height is limited to a maximum of 256 pixels, and the total number of pixels cannot exceed the number of bits in the cursor ram (8192 bits). bits in the cursor ram that are 0 become transparent on the panel. bits that are 1 become fully opaque in the color defined in register 3 in the control descriptor for the cursor (ctrldesccursor_3). the default_cursor_color bit field is in rgb888 format. there are restrictions on the arrangement of bits in the curs or ram depending on how the height and width bit fields are configured. ? the rightmost bit in the cursor ram (bit 31) represents the leftmost pixel on the display. ? when the cursor size is less than 32 bits, each row of th e cursor is contained in a single 32-bit word of cursor ram. the other bits in each row must be filled with zeros. tile size - 64x64 pixels display size- 320 x240 (qvga) layer size - 192 x 128 pixels
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-89 preliminary?subject to change without notice ? when the cursor width is an intege r multiple of 32 bits, the pixels in each row roll from one word in the ram to the next one. the ri ghtmost bit in the first word in the ram is the t op leftmost pixel on the display. the leftmost bit in the word repres ents a pixel that is adjacent to the rightmost bit in the next word (in the same row). the leftmost pixel on the next row is the rightmost bit in the first word after n words that describe the first row. ? when the cursor is greater than 32 bits but not an integer multiple of 32, the pixels in each row roll from one word into the next one such that the ri ghtmost bit in the first word of the row is the leftmost bit on the display. in the fina l word of the row there are unused bits. the position of the cursor on the panel is defined by re gister 2 in the control descriptor for the cursor (ctrldesccursor _2). the register contains two bit fields, posy and posx, which determine the location of the upper left pixel of the cursor in the x and y axes. both fields are expressed in terms of the number of pixels in each axis. placing the cursor beyond the panel area is not allowed. the cursor can be configured to blink at a part icular rate when it is enabled. the en_blink, hwc_blink_on, and hwc_blink_off b it fields define the blink beha vior. these are in register 4 in the control descriptor for the cursor (ctr ldesccursor_4). en_blink enables blinking. the blinking time is based on the frame rate, and the on and off times are inde pendently configurable. hwc_blink_on configures the numbe r of frame refresh cycles for which the cursor is visible. hwc_blink_off configures the number of frame refresh cycles for which the cursor is not visible. for a frame refresh rate of 64 hz, the hwc_blink_ on and hwc_blink_off counters give a range of on/off times up to 4 seconds. the cursor is enabled by setting the cur_en bit field in register 3 in the control descriptor for the cursor (ctrldesccursor_3). if the dculite detects an invalid configuration in the cursor cont rol descriptor, then the cursor configuration is invalid and it cannot be made visible. in addition, the error flag hwc_err is set in the layer parameter error register (parr_err). the cursor ram may be written at an y time when the tft lcd panel is not being driven with data. this means that the ram can be modified when the dcul ite is not enabled and dur ing the vertical blanking period. 12.4.6 clut ram the color look up table (clut) ram is a dedicated me mory in the dculite used to store palettes for indexed colors. color information in this ram is always stored as aligned 32-bit words where the most-significant byte is always the alpha component, the next byte contains the red component, the next the green component and the least significant byte the blue com ponent (0xaarrggbb). the content of the ram at a specific address is defined by the control de scriptor of a la yer. the luoffs bit field in the layer control descript or defines the starting address of th e area, and the bpp bit field defines the maximum size of the palette for that layer. in figure 12-81 three areas of the ram are de fined for different purposes. area a is used by layer 1 as a clut for its 4 bpp graphic. area b is use by layer 5 as a store for its apal8 graphic. area c is used by
pxd20 microcontroller reference manual, rev. 1 12-90 freescale semiconductor preliminary?subject to change without notice layers 2, 7, and 9 as a clut for th eir 8 bpp graphics. in this example, the apal8 palette in area b uses a reduced palette size of 64 entries in stead of its maximum of 256 entries. figure 12-81. an example of use for the clut ram the clut ram is 512 entries ? 32 bits in size and is mapped into th e dculite 16 kb memory space from address 0x2000 to 0x3fff. for compat ibility with the dcu3, the clut repeats at every 2 kb boundary in this space (0x2000, 0x2800, 0x3000, 0x3800). the 512 entrie s provides up to two full cluts for 8 bpp layers. the clut ram may be written at any time when the tft lcd panel is not being driven with data. this means that the ram can be modified when the dcul ite is not enabled and dur ing the vertical blanking period. 12.4.7 gamma correction the gamma table allows the user to define an arbi trary transfer function at the output of each color component. the function ( equation 12-4 ) is applied to each pixel after al l blending is complete and before the data is driven to the tft lcd panel. gamma correct ion is optional and can be used to adjust the color output values to match the gamut of a particular tft lcd pa nel, or to perform data inversion or data length reduction on each component. output_color_component = gamma_table[input_color_component] eqn. 12-4 the table is arranged as three sepa rate memory blocks within the dc ulite memory map; one for each of the three color components. each memory block has one entry for every possible 8- bit value and the entries 16 palette entries 64 palette entries 256 palette entries clut ram a b c
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-91 preliminary?subject to change without notice are stored at 32-bit a ligned addresses. this means that the upper 24 bits are not used while reading/writing the gamma memories. see figure 12-82 for details of the memory arrangement. figure 12-82. gamma correction table organization the gamma table can only be read or written when the dculite is not enable d or during the vertical blanking period. 12.4.8 temporal dithering this is a technique that allows th e emulation of a color resolution hi gher than the resolution supported by the display. it is done by changing th e intensity values over time sent to the display. the averaging done by the human eye gives the impression of the intensity of such alternating pixe ls as an interim value between the two supported intensity values . temporal dithering is enabled by the dcu_mode[dither_en] bit. the key features of the dithering block are ? temporal dithering increases the optically perceived depth of a limited tft display ? supports display with 5-8 bits resolution per color component ? independent dither control parameters per color component ? support for safety mode temporal dithering is enabled and controlled by th e en_dither, addb, addg, and addr bits in the dcu_mode register. the addx fields are each 2 bits wide and select how many bits to add to each color component. the typical sett ing is 8 minus the number of bits in each component required by the display. 0x0800 blended pixel gamma adjusted pixel 0x0c00 0x1000 red green blue
pxd20 microcontroller reference manual, rev. 1 12-92 freescale semiconductor preliminary?subject to change without notice the random number generator (rng) provides a random number of up to 3 bits . the number of bits provided is selected by the values of each component's addx field. when pixels from a safety layer are encountered the rng output is forced to 0 which effectively disables the temporal dithering block and these pi xels are passed to the display unmodified. the add & clamp block adds the eight bit pixel value to the thr ee bit number generated by the rng. the result is then clamped to the range of 0..255. 12.4.9 special ddr mode special ddr mode is a special c onfiguration that optimizes the use of an sdram memory by the dculite by forcing the dculite to fetch data in optimal chunks. in this special mode, only the two highest priority layers (0:1) are available in the dculite. this mode is enabled using the dcu_mode[ddr_mode] bit. when this mode is enabled the dcul ite will fetch data in 32-byte chunks if the la yer is encoded in 8, 16 or 32bpp formats thus optim izing the sdram throughput. any layers in 1, 2, 4 or 24 bpp formats will be fetched using normal access thus they will not be nefit from any optimizati on and may disrupt optimal access for any 8, 16 and 32 bit formatted layers if both are in the sdram. therefore it is highly recommended to store any 1, 2, 4 or 24bpp layers in non-sdram memory such as on-chip sram or flash. depending on the layer configurati on in use this mode may also be nefit other synchronous memory interfaces such as quadspi. 12.4.10 run length encoding (rle) mode rle mode is available on the two highe st priority layers (lay er 0 and layer 1) and allows the dculite to load rle compressed data from memory and directly decode it for use on the panel. the mode is enabled using the rle_en bit in the control descriptor 4 register ctrldescln_4. this mode is only available when special ddr mode is enabled and can only be used on a single layer at a time. in addition the mode only supports 8 bpp, 16 bpp (rgb565, argb1555, argb4444, apal8), 24 bpp and 32 bpp bgra8888 formats. when enabled, the dculite fetches data in 3-byte chunks and decompresses it before sending the decoded data to the normal dculite blend process. the dataflow for the rle decoded data is as shown in figure 12-83 .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-93 preliminary?subject to change without notice figure 12-83. rle decoding in dculite the decoded data is read by the input fifo once at l east 8 bytes are available in the txfifo.the size of rxfifo is 64x8 bits while the size of txfifo is 16x8 bits. if both layer 0 and layer 1 have rle_en set, then the error flag rle_err is asserted. 12.4.10.1 rle decoding scheme before enabling an rle encoded layer configure th e comp_imsize register with the size of the compressed image. the decoder exp ects to read comp_imsize bytes from the image and produce from that the number of pixels specified in the layer control descriptor 1 register. the format of rle encoded layers is as follows: ? the first data byte read at the image address (l ayer control descriptor 3) is a command byte (cmd[7:0]) ? the ms bit (cmd[7]) i ndicates if the following bytes are raw or compress ed pixels. one pixel can be 8-bit, 16-bit, 24-bit or 32 -bit wide, depending on the bpp bitfield in the layer control descriptor 4 register. ? the remaining 7 command bits (cmd[6:0]) specif y the number of raw or co mpressed pixels that follow the command byte. this count is offset by 1 such that a va lue of 0 means one pixel follows. ? for compressed pixels (cmd[7] = 1), only one pixel follows the command byte. this pixel is repeated count+1 times on the layer. the pixel size may be 8, 16, 24 and 32 bits. ? for raw pixels (cmd[7] = 0) count+1 pixels follow the comm and byte and these are included on the layer as is. the pixel si ze may be 8, 16, 24 and 32 bits. ? if there is more data to decode then a new command follows after cmd+ (1*{pixel width}) bytes. this encoding is repeated until the whole image is decoded. 12.5 timing, error and interrupt management the dculite can detect and raise stat us and error flags when the status of the system changes and when configuration or operationa l errors are detected. dma rxfifo txfifo rle input fifo decoder
pxd20 microcontroller reference manual, rev. 1 12-94 freescale semiconductor preliminary?subject to change without notice 12.5.1 synchronizing to panel frame rate since the dculite fetches data dir ectly from memory independently of the cpu, there is the possibility that changes to the dculite layer configuration or c ontent can create incoherent content on the panel. to help avoid this situation there are five timing control flag s that define when th e dculite recognizes and locks changes to its configuration. these can be used to manage changes to control descriptors, clut memory, or source graphics and so avoid coherency problems on the pane l. all the timing flags are in the int_status register and can be used to generate interrupts from the dculite. the dculite configuration is comple tely open during the vertical bla nking period and control descriptors and some other registers may also be programmed at any time. the co nfiguration that is present one hsync before the end of the vertical blanking peri od is the configuration us ed by the dculite for the panel refresh phase. the vs_blank and ls_bf_vs flags give indication of the start of the vertical blanking period. the vs_blank flag is set at the begi nning of the vertical bl anking period. the ls_bf_vs flag is set a given number of horizontal lines before the start of the vert ical blanking period; the gi ven number of lines is defined by the ls_bf_vs bit fiel d in the threshold register. the prog_end flag indicates that the dculite has locked the conten ts of its configur ation registers for the new panel refresh period. no furt her changes are accepted to the dcul ite configuration after this flag is set (until the next vertical blanking period). the dma_trans_finish flag indicates that the dculite has completed fetching all data from memory in the current panel refresh cycle. this normally precedes the ver tical blanking period and indicates that it is possibl e to change the contents of a memory th at contains graphics used by the dculite. the vsync flag indicates that the dculit e has begun the next panel refresh period. 12.5.2 managing the dculit e fifos and dma activity the dculite fetches graphic data directly from in ternal and external memory using a dedicated dma system and manages the output of data to the tft lcd panel such that the panel always receives the pixel information when expected. since the panel is sharing access to memo ry with the system dma and cpu it cannot depend on the require d data always being availa ble at all times. it ther efore uses input and output fifos to temporarily stor e incoming and outgoing data until required and thus reduces the opportunity for the panel to be starved of pixel data. the dculite manages the supply of gr aphic data to its format conversi on and blending stages using input fifos that are 256 ? 64 bits in size. the data that is driven to panel is managed usi ng an output fifo that is 128 pixels in size. see figure 12-1 for a diagram of the input fifo and output fifo operation in the dculite. the input fifos are not accessi ble to the user but it is possible to set thresholds that control the dculite behavior when the fifos are becoming full or empt y and observe when the lower and higher thresholds are reached. this can help detect a nd avert situations where the dculite is running out of data to send to the panel.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-95 preliminary?subject to change without notice the fifo thresholds are set in the threshold_in put_buf_1/2 registers. the upper thresholds are set by the inp_buf_pm_hi bit fields (where m is the position of the pixel in the blend stack) and these set the point at which the dculite pauses fetching data from memory. the maximum size of any dma burst is fixed to 16 pixels and so is dependent on the graphic enc oding. the lower thresholds are set by the inp_buf_pm_lo bit fields. each of the four input fi fos has two flags that indicate whether the fifo has reache d its upper or lower threshold. the pm_fifo_hi_flag flags (where m is the position of the pixel in the blend stack) indicates that the input fifo has reached the upper threshold. the pm_fifo_lo_flag indicates that the input fifo has less data than its low threshold. depending on when the low threshold is reached this may indicate a number of scenarios ? the expected graphical data is not available for the dculite to load ? the dculite is reaching the end of a fram e and does not need to load any more data ? the blend stack does not need pixels of this priority in the situation where the data is not available to the dculite then ther e may or may not be an impact to the data visible on the panel. in the situation where the output fifo is full then it is possible for the dculite to accept a delay before it requires to use the incoming data. the output fifo is not accessible to the user but it is possible to set thresholds that control the dculite behavior when the fifo is becoming full or empty and obser ve the lower threshold. this can help detect and avert situations where th e dculite is running out of data to send to the panel. the buffer thresholds are set in the threshol d register. the upper threshold is set by the out_buf_high bit field and this indicat es that sufficient data exists in the output buffer and processing should stop until the dculite uses some of the values in the fifo. if this value is set too low then the possibility of the dculite running out of data to drive the panel is in creased. the lower threshold is set by the out_buf_low bit field. when the output fifo has emptied below its low threshold (out_buf_low bit field) it sets the undrun bit. in an under run situation there may or may not be an im pact to the data visible on the panel. the impact depends on whether the dculite is reaching the end of a frame and how close to running out the threshold is set. the best guide to indicate whether the dculite is able to supply the required pixel information to the panel is the output buffer. if the output is indicating that it is running out of data then the input fifos may help identify the areas of memory th at are restricting the s upply of data. using these indicators can help to set the dculite thresholds and ensure that the data throughput on the mcu is ba lanced correctly for all master devices. finally, note that the number of dculite clock cycl es to fetch and blend each pixel increases with the depth of the blend stack. however, the time taken to process the pixel data is fixed by the timing requirements of the panel. therefore, for full perfor mance across all color encodi ngs the ratio between the dculite clock and the pixel clock must incr ease as the blend stack depth increases: ? for two-pixel blending, the minim um dculite clock must be the same as the tft pixel clock. ? for three-pixel blending, the minimum dculite clock must be twice the tft pixel clock. ? for four-pixel blending, the minimum dculite clock must be twice the tft pixel clock.
pxd20 microcontroller reference manual, rev. 1 12-96 freescale semiconductor preliminary?subject to change without notice 12.5.3 error detection the dculite asserts error flags when er rors are detected in its configurat ion or when the user attempts to modify the configuration at an invalid point in the pa nel refresh period or when it is unable to access the required source data. the error flags may raise an interru pt if enabled to do so by the related mask bit in the corresponding mask register. error flags are stored in the parr_er r_status and int_status registers. errors in the dculite configuration are collec ted in the parr_err_status register. the flags ln_parr_err (where n is the layer number) indicate an error in the configuration of the layer which indicates a layer with a horizontal dimension that is smal ler than the minimum size defined by the layer encoding (see section 12.4.4.3, layer size and positioning ). the disp_err flag indicates that the vsync and hsync pulse widths are configured to the invalid value of 0. the hwc_err flag indicates that the hardware cursor is either larger than the av ailable memory or is placed in an off-panel position. the sig_err indicates that the signature calculation specifies an area that extends beyond the panel size. the rle_err indicates that more than one layer has rle enabled. reads of clut ram during the period when the tft lcd panel is being updated do not return the clut ram content. errors caused when the dculite is unable to access its required sour ce data are collected in the int_status register. these errors are indicate d by the undrun flag and the pm_fifo_lo_flag flags (where m is the position in the blend stack) 12.5.4 interrupt generation the dculite generates interrupt through four lines that are controlled by the contents of six registers: ? int_status ? int_mask ? pdi_status ? mask_pdi_status ? parr_err status ? mask_parr_err status there are four interrupt status lines de fined.these lines are grouped as follows ? timing based interrupts: ?vsync ?ls_bf_vs ? vs_blank ?prog_end ? dma_trans_finish ? functional interrupts: ? undrun ? crc_ready
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-97 preliminary?subject to change without notice ? crc_overflow ? p1_fifo_hi_flag ? p1_fifo_lo_flag ? p2_fifo_lo_flag ? p2_fifo_hi_flag ? p3_fifo_hi_flag ? p3_fifo_low_flag ? p4_fifo_hi_flag ? p4_fifo_low_flag ?ipm_error ? parameter error interrupts ?layer error ? signature calculator error ? display error ? hwc_error ? rle error ? pdi-related interrupts (pdi_int) ? this includes pdi related interrupts. see section 12.8.1.8, pdi-re lated interrupts, for a description. when any interrupt occurs, the host can identify wh ich type of interrupt has occurred by reading the interrupt status register /pdi status register/par r_err status register. 12.6 register protection there is a customized regist er protection scheme on the dculite that is different to the protection scheme implemented elsewhere on the mcu. th e scheme provides a mechanism to protect certain registers in the dculite from being written. 12.6.1 operation of scheme the register protection scheme provides a two-step protection scheme for the protected register. firstly, each register has an associat ed soft lock bit (slb) that prevents further writes to the register when it is set. each slb has a correspondi ng write enable (wen) bit that must be set in the same write operation as the slb. the slb can be set or cl eared by writing a '1' or '0 ' to it while its wen bi t is set. the slb bits are in the soft lock registers l0 and l1, di sp_size, hsync/vsync_para, pol, l0_transp and l1_transp registers. secondly, there is a hard lock bit (hlb) in the globa l protection register which prevents all changes to soft lock bits. the hlb can only be cleared by a system reset.
pxd20 microcontroller reference manual, rev. 1 12-98 freescale semiconductor preliminary?subject to change without notice if a write is made to a register whose slb is set th en a transfer error occurs that generates an ivor1 exception on the cpu. similarly if the hlb is set then any write to the slb registers causes a transfer error. 12.6.2 list of protected registers the register protection scheme a pplies to the following registers: ? all layer 0 control descriptor s ctrldescl0_1 to ctrldescl0_7 ? all layer 1 control descriptor s ctrldescl1_1 to ctrldescl1_7 ? layer 0 foreground and background register s for transparency mode fg0_fcolor and fg0_bcolor ? layer 1 foreground and background register s for transparency mode fg1_fcolor and fg1_bcolor ? all control descriptors & tran sparency registers for layer1 ? disp_size ? hsync_para ? vsync_para ? syn_pol 12.7 safety mode safety layers are used in a multi-layer dculite environment for the purpose of guaranteeing that the content is driven to the display regardless of the se tting of remaining layers and the pixel manipulation algorithms of the dculite. features su ch as this are a require ment from qualification in stitutes to be able to reach a safety level of sil2 or asilb. the dculite has two safety layers (l ayer 0 and layer 1) which also have the highest priority. when safety mode is active the safety layers can use chroma keying for complex area description; however, alpha blending for th e layer is always ignored. additionally, if a layer has safety mode enabled then a layer format of 32 bpp or luminance is not al lowed. using these formats causes the layer to be disabled. safety mode is implemented using a signature calc ulator module implemented inside the dculite that calculates two signatures (pixel valu e and pixel position) for a predefined area of the frame. the user makes layer 0 and/or layer 1 active as a safety layer, defines the window/area of the pixels for which the signature is to be calculated, and enables safety m ode. when enabled, the signature calculator starts to calculate the signature after the first pixel in the sel ected area is available and after the start of the next frame (vsync). it is also possible to calcul ate the signature value for all pixels if the dcu_mode[tag_en] = 0. as the pixels in the selected area become availabl e they are "tagged" by th e dculite, except for those removed by chroma-keying. these tags id entify the pixels to be included in the signature calculation. the signature calculation itself is an industry-standard crc. the dculite asserts the crc_ready fl ag at the end of any frame whic h has safety mode enabled. this can be used to indicate the complete d signature calculations for each full frame of pixels after the mode is enabled. the completed signature can then be compared against a pre-calculated value with any difference
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-99 preliminary?subject to change without notice indicating that the pixels displaye d did not match what was expecte d. the signature calculator then continues to calculate the crc for the next frame. if the crc_ready flag is not processed within one frame time period, then the crc_over flow interrupt is issu ed and the latest cal culation overwrites the previous value. since the crc_ready flag is set at the end of any fra me with safety mode enabled, it is possible that a full frame has not yet been comple ted and therefore no signature calculation exists for the frame that set the flag. if the user has set the neg bit for the dculite, whic h indicates that the pixels fed to the display are inverted, then the value crc is calculated on non-i nverted values. the position crc, however, remains as is. normal arbitration takes place only wh en a pixel has content on layer 0 an d layer 1 but where safety mode is enabled in layer 1. the polynomial used for crc calculation is (x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1) eqn. 12-5 for the value crc, the 24-bit value of each output pixel (after decoding) is sent to the polynomial. for the position crc, the value sent is (pixel_delta_y * display.delta_x) + (pixel_delta_x + 1) eqn. 12-6 figure 12-84. safety mode block diagram normal mode operation safety mode format converter blending /chroma key gamma correc. display drive display fgplane bgplane 1-32 bpp 1-32 bpp 24 bpp 24 bpp 24 bpp 24 bpp format converter gamma correction display drive display fgplane 1-24 bpp 25 bpp 25 bpp 25 bpp 24 bpp signature calculator optional chroma key optional sync tag 25 bpp = 24 bpp rgb + 1 bit safety pixel tag optional external signature checker result interrupt calculator bgplane 1-24 bpp
pxd20 microcontroller reference manual, rev. 1 12-100 freescale semiconductor preliminary?subject to change without notice 12.7.1 crc area description 12.7.1.1 configuring the crc calculation 1. crc_val and crc_pos are calculated when safety mode is enabled using dcu_mode[sig_en]. 2. the crc can be calculated for part of the panel as shown in figure 12-85 . the green portion on the panel is identified using the sign_calc_1 and sign_calc _2 registers which defined the size of the area and the location of the area respectively. if sign_c alc_1 and sign_calc_2 are configured appropriately this calculation will cover the whole panel. figure 12-85. safety mode enabled for part of the screen 3. the crc can be calculated exclusively for la yers 0 and 1 by setting dcu_mode[tag_en] and enabling the safety_en bit in contro l descriptor 4 of each of the la yers. in this configuration the crc is calculated using values from the layers only where they inters ect the area of interest defined in sign_calc_1 and sig_calc_2. an ex ample is shown (in dark pink) in figure 12-86 . lenx startx starty area of concern leny note: enable to crc is sent for the green portion
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-101 preliminary?subject to change without notice figure 12-86. safety mode with dcu_mode[tag_en] = 1 12.7.2 summary of operation the area included in the crc calculation is summarized in table 12-72 . the initial value on all crc calculations is 0x00000000. table 12-72. supported area area dcu_mode[tag_en] note full 1?b0 sign_calc _2[sig_hor_pos] = 0 sign_calc_2[sig_ver_pos] = 0 sign_calc_1[sig_hor_size] = panel width sign_calc_1[sig_ver_size] = panel height part 1?b0 the sign_calc parameters have values other than those mentioned above ? see figure 12-85 safety layer (layer 0 and 1 only) 1?b1 the included portion of the safety layers depends on ? the portion lying within the area defined by sign_calc_1 and sign_calc_2 ? the pixels removed by chroma keying functionality area of interest crc layer (intersection of both area of interest and safety layer) safety layers/tag note: enable to crc is sent for the dark pink portion
pxd20 microcontroller reference manual, rev. 1 12-102 freescale semiconductor preliminary?subject to change without notice 12.8 parallel data interface (camera interface) 12.8.1 pdi interface description 12.8.1.1 introduction this block extracts the timing and pixe l information from an external vi deo source and passes it to the dculite block to synchronize with the timing and display the pixel information on the tft lcd screen. the bgnd layer in the dculite is replaced by the incoming video stream. the pdi requires that the incoming video stream ma tch the resolution and timing at which the dculite is driving the tft lcd panel and the in coming stream must not be interlaced. the pdi can also be configured in slave mode in which case it ignores the pixel information from the external video source and only passes the timing information to the dculit e to synchronize with. in this instance the dculite will continue to operate as normal (the bgnd layer will not be altered) but will use the timing from the pdi. the pdi shares configuration registers with the dculite. 12.8.1.2 pdi interaction with other modules figure 12-87. pdi interacting directly with the external sensor in figure 12-87 , the pdi accepts data and ti ming directly from the external video source. the external device must output the video in a digital format supported by the pdi. video sensor/ camera output sensor input fed directly to pdi other layer data to mix with pdi pdi dculite display driver/ screen data being sent at pdi rate device pdi output in format required by dculite (pdi becomes bg layer)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-103 preliminary?subject to change without notice figure 12-88. pdi interacting with fpga in between in the case shown in figure 12-88 , the video stream is sent to a de coder or an fpga which alters the incoming stream to a format which is compatible w ith the pdi. a decoder/fpga is required if a video source with an analog output format (e.g. ntsc/pal) is used . the decoder should perform analog-to-digital conversion on the stream and ensure the timing match that of the dculite. the incoming stream may also need to be de-interlaced. the pdi is compatible wi th various input formats: ? normal mode: the pdi clock freque ncy must be equal to pixel cl ock frequency required by the tft display driver ? narrow mode: the pdi clock frequency is double the desired pixel clock frequency. ? external synchronization: the ti ming signals (hsync, vsync, a nd de) each have a dedicated input pin. (de is optional) ? internal synchronization: the tim ing signals (hsync, vsync and de) are embedded in the data stream, as such only the data and pclk inputs are required. (see section 12.8.1.4, itu-r bt.656 sync information extraction. ) before the dculite locks onto the pd i timing signals it will run on the internal dc ulite clock. after lock has been achieved, the dculit e will switch to the clock from the pdi stream and the this is then used to send data and timing signal to tft/lcd display driver. in all cases, the resolution of the incoming stream and the hsync and vsync frequency must be the same as that for tft screen. all the horizontal parameters (front po rch width, back porch width, pulse width) and vertical parame ters (front porch width, back porch widt h, pulse width) must be same as that of tft screen. when pdi is the background layer, no ot her layer can be a bac kground layer for that pa rticular frame. only one background layer is possible i.e. pdi layer when pdi is enabled. sensor input fed directly to decoder/fpga, other layer data to mix with pdi pdi dculite display driver/ screen pdi output in format required by dculite video sensor/ camera output decoder/ which converts the data to a format required by the pdi. data being sent at pdi rate fpga pxd20 (pdi becomes bg layer)
pxd20 microcontroller reference manual, rev. 1 12-104 freescale semiconductor preliminary?subject to change without notice 12.8.1.3 features the pdi supports the following: ? rgb565, rgb666, 8 bit monochr ome format,ycbcr422 mode ? max input frequency of 32 mh z in 8/16/18 normal mode input ? max input frequency of 64 mhz in 8 bit muxed (narrow) mode ? external synchronization using pd i_hsync, pdi_vsync and pdi_pclk ? external synchronization using pdi_hs ync, pdi_vsync, pdi_pclk, and pdi_de ? internal synchronization usi ng pdi[17:0] and pdi_pclk is supported for rgb565 and ycbcr422 muxed mode only 12.8.1.4 itu-r bt.656 sync information extraction according to itu-r bt.656 recommendation, the incoming digital video will have a pdi_clk signal and 8 data bits. the data bits can cont ain both the video data and the ti ming reference signals (vsync and hsync). the timing signals are encoded at th e start and end of each line by ti ming reference codes known as start of active video (sav) and end of active video (eav ). the sav and eav codes are identified by their preamble of three bytes (0xff,0x00,0x00) . due to this, neither 0x00 or 0xff can be used during the active video data. the preamble is followed by the xy status word which cont ains a field bit (f), a vertical blanking bit (v) and horizontal blanking bit (h) a nd four protection bits for si ngle bit error correction and detection. the h bit is set to 1 to denote an eav ? that is the end of a line, and the beginning of the horizontal blanking period. the v bit is set to 1 to denote the beginning of the ve rtical blanking pe riod. the f bit is used for interlaced video to denote if the forthcoming line is odd or even. the remaining 4 bits contains make up the protection bits for single bit error correction and detection. it should be noted that f and v fields are only allowe d to change as part of eav sequences i.e during transitions from h=0 to h=1. table 12-73. supported rgb format and sync format rgb format data input bus 8-bit monochrome 8 bit rgb565 16 bit rgb666 18 bit rgb565 muxed (uses narrow mode) 8 bit sync format pin used internal sync (valid only for rgb565 and ycbcr in narrow mode) pclk external sync pdi_hsync, pdi_vsync, pdi_pclk external sync (with data en) pdi_hsync, pdi_vsync, pdi_pclk, pdi_de
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-105 preliminary?subject to change without notice an entire line of video comprise s active video + horizontal blanki ng (from the start of the eav code until the end of the sav code) and vert ical blanking (the space where v = 1). figure 12-89. itu-r bt.656 8 bit parallel data format for 525 video system the sav and eav codes have a de fined preamble of thre e bytes (0xff,0x00,0x00) fo llowed by xy status word which aside from the field (f), vertical bla nking (v) and horizontal bla nking bits contains four protection bits for single bit error co rrection and detection. also, f and v fi elds are only allowed to change as part of eav sequences i. e transition from h=0 to h=1. figure 12-90. control byte sequence for 8 bit/10 bit video the bit definitions for the st atus word xy are shown in table 12-74 . table 12-74. status word definitions bit definition f 0 for field 0 1 for field 1 v 1 during vertical blanking period 0 when not in vertical blanking h0 at sav 1 at eav p3 v xor h p2 f xor h f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y video data active eav code sav code blanking h control signal start of digital line start of digital active line next line data bit firstword secondword thirdword fourthword (ff) (00) (00) (xy) d7(msb) d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 f v h p3 p2 p1 p0
pxd20 microcontroller reference manual, rev. 1 12-106 freescale semiconductor preliminary?subject to change without notice figure 12-91. pdi input data mode figure 12-91 represents the scenario in which data from an itu-r bt.6 56 compliant video source is fed into the pdi interface. the data has embedded cont rol information (hsync and vsync) in it. an activity detector checks for the transitions on the pdi bus. it sample s the values on the pdi bus and once it has detected valid activity, sets a flag in the stat us register and can optionally trigger an interrupt. the pdi interface has a state machine wh ich extracts the control informati on from the video data. the machine checks the video data for the pr eamble field (0xff,0x00,0x00) and then depending on the status bits xy decides if it has receive d a valid control signal. 12.8.1.5 normal and narrow mode in normal mode, the pdi supports a maximum input frequency of 32 mhz. in narrow mode, the pdi supports a maximum input frequency of 64 mhz. p1 f xor v p0 f xor v xor h table 12-74. status word definitions (continued) bit definition video source with embedded itu656 timing clk embedded control pdi_clk activity detector ready data with pdi interface logic
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-107 preliminary?subject to change without notice figure 12-92. data transfer in normal and narrow mode the byte transferred first (msb or lsb) depends on the configur ation register as shown in figure 12-92 . this does not affect the sync preamble sequence in case internal sync mode. on this device, the incoming rgb data is mapped onto the pdi pins as described in table 12-75 . table 12-75. mapping of rgb data onto pdi pins mode mapping normal (full 18-bit pdi interf ace) pdi[17:12] = dculite_r[5:0] pdi[11:6] = d culite_g[5:0] pdi[5:0] = dculite_b[5:0] normal (rgb565 16-bit pdi inte rface) pdi[15:11] = dculite_r[4:0] pdi[[10:5] = dculite_g[5:0] pdi[4:0] = dculite_b[4:0] narrow (8-bit pdi interface) rgb565: in first clock cycle, pdi[7:0] = { dculite_r[4:0], dculite_g[5:3] } in second clock cycle, pdi[7:0] = { dculite_g[2:0], dculite_b[4:0] } ycbcr: in first clock cycle, pdi[ 7:0] = { dculite_cb[7:0] } in second clock cycle, pdi[ 7:0] = { dculite_y0[7:0] } in third clock cycle, pdi[7:0] = { dculite_cr[7:0] } in forth clock cycle, pdi[7:0] = { dculite_y1[7:0] } 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0b 0x0a 0x0d 0x0c 0x0f 0x0e 0x0100 0x0302 0x0504 0x0706 0x0908 0x0b0a 0x0d0c 0x0f0e pdi_data [15:0] rgb565 normal mode (pdi_clk = 64 mhz max) lsb pdi_data [7:0] pdi_clk pdi_clk rgb565 narrow mode (pdi_clk = 64 mhz max) lsb transferred first rgb565 narrow mode (pdi_clk = 64 mhz max) msb transferred first pdi_data [7:0] 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0b 0x0a 0x0d 0x0c 0x0f 0x0e
pxd20 microcontroller reference manual, rev. 1 12-108 freescale semiconductor preliminary?subject to change without notice 12.8.1.6 modes of operation based on sync extraction 12.8.1.6.1 pdi input dat a (external sync mode) in external sync mode the timing signals (hsync, vsync and, optionall y, date enable) are provided to the pdi input timing pins by the external video source. external sync mode can be used in both normal m ode and 8-bit narrow mode , but cannot be used in conjunction with the ycbcr data format. in the instance that external sync and narrow mode is selected, the external signals are used, and any timing information (eav/sav) em bedded in the data stream is ignored. as in figure 12-94 , pdi data enable (pdi_d e) should be low during vs ync and hsync pulse, vsync front porch (fp_v) and back porch (bp_v), hsync front porch (fp_h) and back porch (b p_h). this is valid for data enable mode when the pdi_de_en bit is set in the dc u_mode register (i.e. mode with hsync, vsync, pdi_de and pdi_pclk as pin signals). pulse width, front and back porch va lues should be picked from those programmed in dculite registers. in order to achieve lock, it must ha ve same value as that of tft scre en. front porch and back porch value can be zero. pulse width and tft sc reen size parameters ca nnot be zero. in case th ey are programmed as zero, it might lead to malfunctioni ng of the validation state machine. as in figure 12-93 hsync must occur during the vsync a nd vertical blanking period. the time between 2 hsync should be same during vsync and vertical bl anking as during th e active line period. as in figure 12-93 the positive edge of hsync and vsync should be aligned. as in figure 12-93 the positive edge of the hsync and start of the vertical front/back porch should be aligned. the polarity of hsync and vsync is selectable. figure 12-93. relationship between hsync an d vsync in external synchronization pdi_hsync pdi_vsync end of last active line posedge of vsync and hsync are aligned start of first active line fp_v (vertical front porch) value = 2 (no of hsync) value = 2 (no of hsync) value = 2 (no of hsync) pw_v (vertical pulse width) bp_v (vertical back porch) vertical blanking period
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-109 preliminary?subject to change without notice figure 12-94. occurrence of hsync, vsyn c, and pdi_de for the entire frame 12.8.1.6.2 pdi input data (int ernal sync extraction mode) in internal sync mode the timing pa rameters (horizontal and vertical bl anking) are encoded into the data stream. internal sync mode can only be used in 8-bit narrow mode. in figure 12-95 , xy is used to decode the vert ical and horizontal blanking period. table 12-76. xyh value bit value description 7 1'b1 always 1'b1. this is checked while decoding sync preamble 6 f not considered in the state machine logic 5 v 1'b1 during vertical blanking 1'b0 elsewhere 4 h 1'b0 for start of active video 1'b1 for end of active video invalid data 1 2 3 4 invalid data pdi_pclk pdi[17:0] pdi_hsync pdi_de data enable high during active data bp_h fp_h data enable in the horizontal resolution fp_h and bp_h is programmable through register pdi_pclk invalid data 1 2 3 4 invalid data pdi[17:0] pdi_vsync bp_v fp_v pdi_de delta_x ?? 1 delta_x ?? 1
pxd20 microcontroller reference manual, rev. 1 12-110 freescale semiconductor preliminary?subject to change without notice figure 12-95. location of sync preamble in narrow mode sync preamble would come continuously for 4 cloc k cycles as shown in figure 12-95 . it does not depend on which byte is coming first in data (msb or lsb). sync extraction is done using pdi[7:0] to identify the horizontal and vertical blanki ng period using h and v field of the 'xyh' data as mentioned in table 12-73 . itu 656 sync preamble pattern (ffh 00h 00h) has to be masked out in the rgb data. the data stream must not include ffh 00h 00h as the va lid pixel data to avoid malfuncti on by the validation state machine. horizontal blanking period must continue during the vertical bl anking period. the gap between 2 horizontal blanking periods should be the same during vertical blanking period as during li ne active. all vertical and horizontal pa rameter values are validated against the dculite registers programmed by the user. polarity of hsync and vsync are selectable. horizontal blanki ng and vertical blanking must be aligned as shown in figure 12-96 . during blanking period the input stream must be a 80h 10h 80h 10h sequence. this sequence must be present during bot h horizontal (line) blanking and vertical (frame) blanking. as the pdi does not support interlaced video, the fr aming bit (f field in xyh) will be ignored during timing extraction. narrow mode is compatible with rgb565 and ycbcr422 muxed modes. each header contains an ecc value, which the pdi will check. the pdi is capable of detecting an error but not correcting it. as with external sync mode, the value of front and back porch can be zero but the pulse width and tft screen parameter cannot be zero. 3 2 1 0 p3 p2 p1 p0 protection bits (used to detect ecc errors). table 12-76. xyh value (continued) bit value description ff 00 00 xy pdi_data [7:0] pdi_clk 16-bit rgb (narrow mode) with in ternal sync (representation ?? note: preamble sequence is independent of data sequence
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-111 preliminary?subject to change without notice figure 12-96. relationship between hbla nk and vblank in internal sync 12.8.1.6.3 ycbcr mode the dculite can process incoming data from the pdi and from memory in ycbcr422 format. both sources use the same rgb conversion and interpolation equations , however, the coefficients for the equations and enable for the interpol ation are independently controlled. in ycbcr mode, the pdi extracts the itu656 sync (ff-00-00) and sends the vi deo to the processing functions. the first processing function converts the 422 stream to a 444 stream, by providing interpolation on the chroma components of the stream depending on pdi_interpol _en bit. the se cond processing function converts the st ream to rgb888/rgb565. the dculite can also sel ect ycbcr format in the b pp field of layer descriptor 4 which allows the same process to be applied to values stored in memory ra ther than brought in from the pdi. interpolation is controlled for the layers using the lyr_intpol_en register. the rgb pixel value is computed using following equations: eqn. 12-7 eqn. 12-8 eqn. 12-9 note that the first multiplication (i.e (y- 16)*ycoeff) is unsigned, the 2 others are signed. line 1 frame of image data line 480 frame blanking period sav 80 eav 9d eav b6 sav ab line blanking period note: the sav and eav bytes are included as part of the blanking period. red y16 ? ?? yred ? 512 ------------------------------------ - cr 128 ? ?? crred 512 ----------------------------------------- cb 128 ? ?? cbred 512 ------------------------------------------- ++ = green y16 ? ?? ygreen ? 512 -------------------------------------------- - cr 128 ? ?? crgreen 512 ----------------------------------------------- - cb 128 ? ?? cbgreen 512 ------------------------------------------------- - ++ = blue y16 ? ?? yblue ? 512 --------------------------------------- - cr 128 ? ?? crblue 512 -------------------------------------------- cb 128 ? ?? cbblue 512 ---------------------------------------------- ++ =
pxd20 microcontroller reference manual, rev. 1 12-112 freescale semiconductor preliminary?subject to change without notice the register values after reset are as follows: yred = 10?h254 (596/512 = 1.16) crred = 11?h331 (817/512 = 1.6) cbred = 12?h000 ygreen = 10?h254(596/512 = 1.16) crgreen = 11?h660(-416/512 = -0.812) cbgreen = 12?hf38(-200/512 = -0.39) yblue = 10?h254(596/512 = 1.16) crblue = 11?h000 cbblue = 12?h409(1033/512 = 2.017) figure 12-97. ycbc r timing diagram figure 12-98. ycbcr interpolation calculation 12.8.1.7 mode of operation depending on pdi[17:0] pdi would support following modes (other than the slave mode): pdi_data [7:0] pdi_clk cb 0 y 0 cr 0 y 1 y 2 y 4 y 5 y 6 cb 1 y 3 cb 2 cb 3 cr 1 cr 2 cr 3 y 0 y 1 y 2 y 4 y 3 cb 0 ? cb 1 ? cb 2 ? cb 3 ? cb 4 ? cr 0 ? cr 1 ? cr 2 ? cr 3 ? cr 4 ? y_data[7:0] cb_data[7:0] cr_data[7:0] rgb888 ycbcr_pulse rgb_valid cb n ??? = cb n/ (cb (n-1)/2 ??? + cb (n+1)/2 )/ cr n ??? = cr n/ (cr (n-1)/2 ??? + cr (n+1)/2 )/ for even n for even n for odd n for odd n
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-113 preliminary?subject to change without notice ? 8-bit monochrome (8 bit input data, e ach pixel info is coming in 1 clocks) ? 16 bit - rgb565 (16 bit i nput data, each pixel info is coming in 1 clocks) ? 18 bit - rgb666 (18 bit i nput data, each pixel info is coming in 1 clocks) ? 16 bit - rgb565 (8 bit input data, each pixel info is coming in 2 clocks) ? 16-bit - ycbcr422 (8-bit input data, info for 2 co-sited pixels coming in 4 clocks) data info extraction is given in table 12-76 . the 8-bit monochrome image is equi valent to 8 bit grays cale images. conversion of 8 bit monochrome to rgb. all rgb components have value equal to 8 bit monochrome value. rgb extraction starts when pdi is enabled (from the next falling edge of va lidated vertical blanking period) 12.8.1.8 pdi-related interrupts pdi can be configured to trigger an interrupt when synchronization is achieved i.e. it receives the pre-specified numbers of frames wit hout error. pdi can also give an in terrupt when synchronization is lost i.e. it receives any error in frame there after. this interrupt is raised when hsync/vsync is lost. the pdi can also trigger an interrupt if there is either a one bit or a multiple bit error in the ecc value during the extraction of the preamble in internal synchronization mode. blanking sequence error interrupt can be triggered in case 80h 10h is not found in vertical and line blanking period during internal synchronization. activity detection interrupt for clk detection. hsync, vsync and de detection in terrupts can be set to generate upon transitions on the pdi_hsync, pdi_vsync and pdi_de pins. activity lost interrupt for pdi_cl k ? for the pdi_clk lost interrupt, is triggered when the pdi_clk is less than dculite module cloc k frequency divided by 32. (i.e. if dculite module clock freq. max = 64 mhz, then the pdi_clk_lost flag will be set if pdi clk freq. min < 2 mhz). all interrupt flags are "w rite-one-to-clear" and al l interrupts are maskable. pdi must reset to show the latest status of the clock activity detect interrupt. table 12-77. data extraction in all possible modes pdi mode narrow mode pins data notes 8-bit monochrome mode 1'b0 8 bit pdi[7:0] ? rgb565 1'b0 16 bit pdi[15:0] ? rgb666 1'b0 18 bit pdi[17:0] ? rgb565 muxed 1'b1 8 bit pdi[7:0] data from two clocks are combined. ycbcr422 1?b1 8 bit pdi[7:0] data from four clocks are combined for 2 pixels.
pxd20 microcontroller reference manual, rev. 1 12-114 freescale semiconductor preliminary?subject to change without notice 12.9 switch between dcu mode and pdi mode (top-level description) figure 12-99. switch to pdi on receiving the interrupt figure 12-100. switch to normal mode from pdi mode pdi_vsync the pdi_vsync_out is generated after validation logic receives the number of frames specified by the users/cpu. pdi lock is generated pdi_vsync_out pdi_lock_status pdi_enb dcu_vsync dcu internal vsync dcu_vsync rising edge sync to dcu internal vsync dcu_vsync falling edge sync to pdi vsync out dcu_hsync switching to pdi once en and lock status is high extended vsync for g ap between the 2 vsync hsync not coming during extended vsync pdi_vsync the pdi_vsync_out is stopped once pdi loses lock or enb is deasserted pdi_vsync_out pdi_lock_status dcu_vsync dcu internal vsync dcu_hsync switching to normal mode on vsync after lock is lost data force to a constant value once lock is lost
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-115 preliminary?subject to change without notice 12.9.1 changes in the configuration any changes in the rgb format or the synchronization mode configuration require s the pdi system to be in disable mode i.e. pdi_en should be 0 during this ti me. the resolution of the screen/layer (pdi or tft) cannot change on the fly. 12.9.1.1 pdi slave mode the vsync generated by the dcul ite block is synchronized to th e pdi input vsync; the pdi vsync resets the internal timing genera tion unit. hsync and vsync are gene rated internally corresponding to the external tft screen display paramete rs programmed in the dculite registers. in slave mode the pdi and dculite introduce a fixed latency to the vsync and hsync timing. 12.9.1.2 pdi sync detection/validation pdi declares a lock when it has correctly received the continuous number of frames programmed by the application. pdi declares the sync lost: ? when it receives data enable during the verti cal and horizontal blanking period (in case of data enable mode) ? when the incoming hsync and vsync timing does not match the pr ogrammed parameter values in the dculite. this also means that if any of control signal info lost, then it also declares sync lost. after pdi_pclk is lost, the pdi requires 64 dculit e module clock cycles to detect pdi_pclk again. pdi does not declare lost sync in case of blanking and ecc errors. writes to the input fifo are stopped as soon as pdi sync is lost aborting transfer of the current frame data. sync detection works continuou sly, independent of pdi enab le. pdi fires an interrupt on: ? sync lock is achieved ? sync is lost ? activity is detected on hsync ? activity is detected on vsync ? pclk activity detection (it is not generated from the state machine) ? de activity detection (it is not generated from the state machine) ? pclk activity lost (it is not generated from the state machine) on receiving a wrong sync pulse, the dculite stops the hsync and vsync activ ity detection and gives an interrupt when it finds sync pulse again. the state machine works for zero values of front and back porches but not for pulse wi dth and screen parameters.
pxd20 microcontroller reference manual, rev. 1 12-116 freescale semiconductor preliminary?subject to change without notice 12.9.1.3 other assumptions the reset to the pdi clock is synchronized to the peripheral clock. reset sync hronization is done with respect to the pdi clock internally. the pdi clock should be available at least 10 clock after the last valid data. this corresponds to the delay of the pdi block. 12.10 dculite initialization the following steps describe a typi cal approach to initializing the dculite for use in an application. 1. after reset configure the dcul ite peripheral to be active using the mode entry module and configure the dculite clock source in the mc_cgm . configure the output ports in the siul as required. 2. configure the timing registers to match the tft lcd panel in use (see section 12.4.2, tft lcd panel configuration ). 3. set the background color as required. 4. load the palette colors into the clut memory. 5. configure the control descriptors for the layers and cursor that are to be used initially. 6. enable the dculite in the appropriate mode (dcu_mode and raster_en bit fields). 12.11 glossary table 12-78. glossary term description argb (also bgra) a data format where the pixel val ues are stored using four components: alpha, red, green and blue. dculite supports different va riations of this format where different numbers of bits can be used to represent each of the components component part of a pixel that contains a single color (red, green or blue) clut color look-up table. the table that contai ns the palette used by an indexed-color graphic direct color the full 24-bit value actually written to a pixel to create a color frame the collection of all pixels on a panel gamut the set of colors that a panel can display. in most cases a panel cannot display the full gamut of colors visible to the human eye. indexed color an index into a table containing direct-color s. usually smaller in size than the direct color; the dculite provides 1, 2, 4, and 8 bits per pixel options palette the list of colors used by a graphic when an indexed colors format is used. the palette is stored in a color look up table and can be from one color up to the maximum of the size of the clut. panel a tft lcd containing an array of colored pixels. pixel the basic graphical element on a tft lcd panel. can display a range of colors depending on the value of the red, green and blue values written to it. normally arranged in a rectangular array.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 12-117 preliminary?subject to change without notice rgb a data format where the pixel values are st ored using three components: red, green and blue. dculite supports different variations of this format where different numbers of bits can be used to represent each of the components vertical blanking period a time during the tft lcd panel refresh cycle when no data is being written to the panel table 12-78. glossary (continued) term description
pxd20 microcontroller reference manual, rev. 1 12-118 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-1 preliminary?subject to change without notice chapter 13 dram controller (dramc) 13.1 introduction the ddr dram controller (dramc ) is a multi-port dram controll er (five ports). it supports mobile-ddr 1 , ddr-1, and ddr-2 memories.a block diagram of the dramc is given in figure 13-1 . figure 13-1. dramc block diagram 1. the jedec standard calls these lpddr. most dram vendors call them mobile-ddr. dram_cs dram_ras dram_cas dram_we dram_ba[2:0] dram_address [15:0] ddr bus 0 ddr bus 1 ddr bus 2 ddr bus 3 ddr_dqs_in ddr_dq_in config ddr_dqs_out ddr_dm_out ddr_dq_out dram_odt config config config all config command bypass ips bus dram_clk dram_clkb int_req dram_odt dram_cke ddr read block ddr write block dram command engine timing manager bus interface write buffers ddr bus 4 (dcu3) (e200z4d instruction and data) (viu2 and dculite) (edma) (gfx2d)
pxd20 microcontroller reference manual, rev. 1 13-2 freescale semiconductor preliminary?subject to change without notice 13.1.1 overview the dramc is a multi-port controll er that listens to incoming reque sts on the five incoming buses and decides on each rising clock edge wh at command needs to be sent to the dram. each incoming bus is a 64-bit bus.the block supports connection of two dram ranks (two chip selects) and supports the four major classes of dram: ? mobile-ddr (lpddr) ? ddr1 ? ddr2 it supports these memories in 16-b it or 32-bit wide configurations. the dramc listens to the incoming requests to all the buses in parallel and then sends commands to the dram from the highest priority bus at the current ti me, while the dram is ready to receive the command from this particular bus. if the dram is blocked because it needs to meet a timing requirement, the controller sends a command from a bus where there is no blockage. for example, suppose bus one has an incoming request on pr iority five, and it hits in bank 1 and the page is not open (the bank needs a precharge+activate co mmand before the request can be serviced). bus two has an incoming request on priority four, it hits in bank two and the correct page is already open. in this case, the dramc accepts the bus two request first. wh ile it is reading from the appropriate bank, it issues the active+precharge command for the bus one request. because the dramc sees it can?t issue the read for the bus one request (the bank needs precharge + activa te), it takes the bus two request first. because it can issue the read, the correct page is open. during th is, it issues the precharge + activate for the bus 1 request in the background. this request does not suffer from the bus two request being serviced first. the embedded priority manager determines the relati ve priority of each bus, and this is used by the dramc to determine which requests are more urgent. 13.2 features ? supports cas latency of 2, 3, or 4 clock cycles. ? master buses ? seven incoming masters shared on five master busses ? supports 16-byte and 32-byte bursts ? supports byte enables ? supports 4-bit priority signal for each bus. ? arbitration protocol ? inside the arbiter block, there are a total of six different arbiters that ea ch take out the highest priority request in a certain class. all the arbiters are dram state aware, meaning they disregard requests that cannot be sent to th e dram because of dr am timing limitations. ? arbiter 1: looks for highest priority read command ? arbiter 2: looks for highe st priority write command ? arbiter 3: looks for highest pr iority activate-for-read command ? arbiter 4: looks for highest prio rity activate-for-write command ? arbiter 5: looks for highest pr iority precharge-for-read command
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-3 preliminary?subject to change without notice ? arbiter 6: looks for highest prio rity precharge-for-write command ? after the first prioritization, th e next round of arbitrating between the different arbiters is done. a fixed-priority schema is followed: ? read and write commands have highest priority ? activate has next-highest priority ? precharge has lowest priority ? the dram is in read or writ e mode. in read mode, reads have priority over writes. in write mode, writes have priority over read. ? dram only switches from read to write mode or vice-versa if: a high-priority write is found, and the write buffer is full. a high-priority read is found. the device is in read m ode, but no more reads pending the device is in write mode , but no more writes pending. ? write buffer contains five 32-byte entries. ? supports 16- and 32-bit-wide mobile -ddr/ddr1/ddr2 and dram devices ? controller supports two chip selects, 8 banks per chip select (16 banks total). ? supports dynamic on-die termination in the host device and in the dram. 13.3 memory map and register definition 13.3.1 memory map table 13-1. dramc memory map offset from dram_base register access reset value location 0x000 dramc_scr?dramc system conf iguration register r/w 0x1000_0000 on page 13-4 0x004 dramc_tc0?dramc time config0 register r/w 0x0000_0000 on page 13-8 0x008 dramc_tc1?dramc time config1 register r/w 0x0000_0000 on page 13-9 0x00c dramc_tc2?dramc time config2 register r/w 0x0000_0000 on page 13-9 0x010 dramc_cmd?dramc command register r/w 0x0000_0000 on page 13-13 0x014 dramc_ccmd?dramc compact command register r/w 0x0000_0000 on page 13-13 0x018?0x034 reserved 0x038 dramc_dqs_oc?dqs config o ffset count register r/w 0x0000_0000 on page 13-15 0x03c dramc_ dqs_ot ? dqs config offset time register r/w 0x0000_0000 on page 13-16 0x040 dramc_ dqs_ds ? dqs delay status register r 0x0000_0000 on page 13-16 0x044?0x05f reserved 0x060 dramc_ extra ? dramc extra attributes r/w 0x0000_0000 on page 13-17 0x064?0xfff reserved
pxd20 microcontroller reference manual, rev. 1 13-4 freescale semiconductor preliminary?subject to change without notice 13.3.2 register descriptions 13.3.2.1 dramc system configuration register (dramc_scr) address: base + 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r rst cke clk on cmd row_sel bk_sel 000 b16 rdly[3] w reset0001000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rdly[2:0] h_dqsdly q_dqsdly wdly[2:0] eodt odt fifo_ovp fifo_uvp 00 fifo_oven fifo_uven w w1c w1c reset0000000000000000 figure 13-2. dramc syst em configuration re gister (dramc_scr) table 13-2. dramc_scr field descriptions field description rst dramc soft reset. when this bit is 0, the dramc is in the reset state. when this bit is 1, the dramc is out of reset. the bit controls the reset to the internal state machines. t he configuration registers are reset by the resets from the hard ware reset block, not by this bit. cke value on the dram cke pin. for functional operation, this needs to be high. during power-down, value can be low. clkon when this bit is 1, the dram clock is running . when this bit is 0, the dram clock is stopped cmd when this bit is 0, the dramc is in normal operati on. when this bit is 1, the dramc is in command mode and does not respond to requests on the incoming buses. command mode is used for dram initialization and to switch the dram into an d out of the different power-down and self-refresh modes. rowsel bk_sel these fields control the multip lexing of the bus address to the dram bank and row address. table 13-5 gives the details. dram column address depends on 16-bit mode bit, and relationship is given in table 13-5 . b16 when this bit is set, the dramc assumes a 16-bit wide memory is used. when this bit is cleared, a 32-bit wide memory is assumed. note: this does not configure the pins for 16-bit mode . that must be done in the pin configuration. rdly[3:0] this field controls the expected delay between sending a read command to the dram and receiving the read data from the dram. rdly, half dqs dly, and quart dqs delay together to code for t dqsen . the t dqsen is the delay between the read command and when the internal dqs enable goes high. see figure 13-3 . timing is internally compensated, and is referred to timing at the device pins. t dqsen should be selected so the l-h transition of dqs enable is always in the preamble of the dqs input of the read command. required t dqsen value depends on the cas latency (cl), the distance between the dram and the device, and the type of dram used. table 13-3 gives the detail on programming t dqsen.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-5 preliminary?subject to change without notice h_dqsdly this field is an extra field to control the expected read delay between issuing the read command and getting read data from the dram. this field offers 1/2 system bus cl ock granularity when programming the delay. see description of field rdly for details. q_dqsdly this field is an extra field to control the expected read delay between issuing the read command, and getting read data from the dram. this field offers 1/4 system bus cl ock granularity when programming the delay. see the description of the rdly bitfield. wdly[2:0] this field controls the write latency (wl) for write commands. eodt this bit needs to be set if write latency is 1 (wdly[2:0] = 001) and on die termination is used with ddr2 dram. it makes sure the dramc assert s the odt signal going to the dram one clock ahead of issuing the write command. odt this bit controls on-die termination (odt) in the cont roller. if this bit is 1, the internal pads generate odt during read. if the bit is 0, no odt is provided. the odt in the dram is controlled via the dram internal configuration registers. please consult dram data sheet for it. fifo_ovp fifo_uvp fifo_oven fifo_uven these bits indicate timing errors and allow the generation of interrupts when these errors occur. the dramc has two interrupts: fifo ov pending and fi fo uv pending. these interrupts are set on overflow or underflow of the fifo in the read bloc k. when a read command is sent to the dram, it is entered into a fifo. the dram is expected to answer by sending back the read data with some up and down edges on the dqs lines (the dqs st robes) used to clock the data. the dramc clocks the read data with the dqs strobes supplied by the dram and retrieves the read command from the fifo after receiving the correct number of read strobes. when the read data strobes returned by the dram do not match the expectations of the controller, the fifo may underflow (if too many dqs strobes are coming back from the dram) or overflow (if not enough dqs strobes are coming back). these underflows and overflows are the re sult of problems with the dram interface or incorrect parameter settings in the controller or the dram. care has been taken during the design of the dramc not to enter a hang-up state when this occurs. however, read data is corrupt and cpu is informed via the fifo overflow and fifo underflow interrupts. the issue is also discussed in section 13.4.7, bus interface. ? fifo_ov_pending and fifo_uv_pending signal to the cpu if an overflow or underflow interrupt is pending. write ?1? to thes e bits clears the corresponding interrupt. ? fifo_ov_en and fifo_uv_en bits are interrupt enable bits. if the pending + enable bit is set at the same time, the interrupt is sent to the cpu. table 13-2. dramc_scr field descriptions (continued) field description wdly[2:0] write latency (csb clocks) 0b001 1 0b010 2 0b011 3 0b100 4
pxd20 microcontroller reference manual, rev. 1 13-6 freescale semiconductor preliminary?subject to change without notice figure 13-3. t dqsen table 13-3. programming t dqsen {rdly, h_dqsdly, q_dqsdly} t dqsen (system bus clock periods) 1000 0 0 0.5 1000 0 1 0.75 1000 1 0 1.0 1000 1 1 1.25 0100 0 0 1.5 0100 0 1 1.75 0100 1 0 2.0 0100 1 1 2.25 0010 0 0 2.5 0010 0 1 2.75 0010 1 0 3.0 0010 1 1 3.25 0001 0 0 3.5 0001 0 1 3.75 0001 1 0 4.0 0001 1 1 4.25 0000 0 0 4.5 0000 0 1 4.75 0000 1 0 5.0 0000 1 1 5.25 table 13-4. number of dram banks addressed and mapping of address to dram bank address bksel number of banks dram bank address 0 4 dram_bank[1:0] = address[11:10] 1 4 dram_bank[1:0] = address[12:11] read tdqsen dram clock dram command dqs enable (internal) dqs (in) dqs enable l-to-h must fall in preamble of dqs (in)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-7 preliminary?subject to change without notice note in 16-bit mode (16bitmode = 1), dd r memories with column address line 0 to 7 are not supported. 2 8 dram_bank[2:0] = address[13:11] 3 4 dram_bank[1:0] = address[13:12] 4 8 dram_bank[2:0] = address[14:12] 5 4 dram_bank[1:0] = address[14:13] 6 8 dram_bank[2:0] = address[15:13] 7 4 dram_bank[1:0] = address[15:14] 8 8 dram_bank[2:0] = address[16:14] 9 4 dram_bank[1:0] = address[25:24] 10 8 dram_bank[2:0] = address[26:24] 11 4 dram_bank[1:0] = address[26:25] 12 8 dram_bank[2:0] = address[27:25] 13 8 dram_bank[2:0] = address[28:26] 14 8 dram_bank[2:0] = address[29:27] 15 8 dram_bank[2:0] = address[30:28] table 13-5. mapping of address to dram column address b16 dram column address 0 dram_column = {address[13:3], 1?b0} 1 dram_column = {address[12:3], 2?b0} table 13-6. mapping of address to dram row address rowsel dram row address 0 dram_row[15:0] = address[25:10] 1 dram_row[15:0] = address[26:11] 2 dram_row[15:0] = address[27:12] 3 dram_row[15:0] = address[28:13] 4 dram_row[15:0] = address[29:14] 5 dram_row[15:0] = address[30:15] 6 dram_row[14:0] = address[30:16] 7 dram_row[13:0] = address[24: 9] table 13-4. number of dram bank s addressed and mapping of address to dram ba nk address (continued) bksel number of banks dram bank address
pxd20 microcontroller reference manual, rev. 1 13-8 freescale semiconductor preliminary?subject to change without notice table 13-7. mapping of address to dram chip select 13.3.2.2 timing configuration 13.3.2.2.1 dramc time configur ation register 0 (dramc_tc0) cs_select 1 1 for the field of register 0x60, see table 13-16 . dram chip select 0 dram_cs_select 2 =0 2 if dram_cs_select = 0 ? use cs0. if dram_cs_select = 1 ? use cs1. 1 dram_cs_select = address[12] 2 dram_cs_select = address[13] 3 dram_cs_select = address[14] 4 dram_cs_select = address[15] 5 dram_cs_select = address[16] 6 dram_cs_select = address[27] 7 dram_cs_select = address[28] 8 dram_cs_select = address[29] 9 dram_cs_select = address[30] address: base + 0x0004 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r0 0 refresh w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cmd pre w reset0000000000000000 figure 13-4. dramc time config uration register 0 (dramc_tc0) table 13-8. dramc_tc0 field descriptions field description refresh refresh interval of the dram. program in this register the number of system bus clocks between any two refresh requests. cmd time-out after sending a command to the dram in bypass mode. for command sent to the dram using the ddr_command and ddr_compact_command register, the normal checking of the timing parameters is not done. instead, any new command to the dram is disabled for dram_command_time[7:0] dram clock periods. this parameter needs to be programmed for the worst-case time-out.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-9 preliminary?subject to change without notice 13.3.2.2.2 dramc time configur ation register 1 (dramc_tc1) 13.3.2.2.3 dramc time configur ation register 2 (dramc_tc2) the ddr_time_config1 and ddr_time_config2 re gisters need to be programmed with the ddr1/ddr2 timing parameters. all ti mes are given in clock cycles. the timing parameters are conceived so the controll er system bus clock cycl es match with the jedec ddr2 specification. to interface wi th ddr1 or mobile-ddr (lpddr), some timing parameters need not be enforced, or are calcula ted differently. refer to the dram datasheet to determine their value. the timing parameters need to be programmed in function of this dram requirement. table 13-9 gives the details. pre time-out. any active bank, that has no outstanding requests, is automatically precharged by the dramc after this time-out has elapsed since the last access to the bank. this time can be set short, which results in open banks being precharged quite fast to long, which results in open banks left open for a long time. the value is a time count in dram clock periods. address: base + 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r rfc wr1 wtr1 rrd w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rrd rc ras w reset0000000000000000 figure 13-5. dramc time config uration register 1 (dramc_tc1) address: base + 0x000c access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r rcd faw rtw1 ccd w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd rtp rp rpa w reset0000000000000000 figure 13-6. dramc time config uration register 2 (dramc_tc2) table 13-8. dramc_tc0 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 13-10 freescale semiconductor preliminary?subject to change without notice table 13-9. timing parameters timing parameter controls jedec parameter (jedec spec) formulae (all times in system bus clock periods) description rfc t rfc rfc = t rfc refresh to active or refresh to refresh command interval. rrd t rrd rrd = t rrd active bank a to active bank b command. rc t rc rc = t rc active to active (same bank) command. ras t ras ras = t ras active to precharge command. rcd t rcd rcd = t rcd active to read or write delay. faw t faw faw 1 =t faw 4-bank activate period. ccd t ccd ccd 2 = max(t ccd ,2) (32-bit mode) max(t ccd ,4)(16-bit mode) cas to cas delay because time is needed for data to be sent over, this time is minimum two clocks in 32-bit mode and four clocks in 16-bit mode. rtp t rtp rtp 3 = t rtp (32-bit mode, ddr2) t rtp +2 (16-bit mode, ddr2) read to precharge delay. rtp is the read-to-precharge delay and t rtp is the internal read-to-precharge delay, hence, the difference for 16-bit mode. figure 13-7 gives the details. rp t rp rp = t rp precharge command period. rpa t rp rpa 4 =t rp + 1 (8 bank device) rpa = t rp (4 bank device) precharge all command period. wr1 t wr wr1 = wl + t wr + 2 (32-bit mode) wl + t wr + 4 (16-bit mode) write recovery time, measured in clocks between write command and precharge command. for this reason, wl (the write latenc y) and the length of the actual write (2 or 4) need to be added to t wr. figure 13-8 gives the details. wtr1 t wtr wtr1 = wl + t wtr + 2 (32-bit mode) wl + t wtr + 4 (16-bit mode) write to read time, measured in clocks between write command and read command. for this reason, wl (the write latenc y) and the length of the actual write (2 or 4) need to be added to t wtr . figure 13-9 gives the details. rtw1 ? rtw1 = cl - wl+2+t bta (32-bit) cl - wl+4+t bta (16-bit) read-to-write time, measured in clocks between the read and write command. there is no limitation on the dram on how to set this parameter. the parameter should be set such that there is no contention on the dq data bus when switching from read to write. equation given at left tries to come up with a formulae that defines the minimum value of dram_time_rtw1 to avoid contention. cl is the cas latency, wl is the write latency, and t bta is the bus turn-around time. t bta is the minimum dead time that needs to be put on the bus between the driving the bus and the dram driving the bus to take into account the transit delay on the pcb, the pad delay, the dram skew, and the on-chip delay.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-11 preliminary?subject to change without notice figure 13-7. read to precharge timing diagram ccd_other 5 ? ccd_other = max(t ccd ,2) (32-bit mode) +1 max(t ccd ,4)(16-bit mode) +1 cas to cas delay from one chip select to the other because time is needed for data to be sent over, this time is minimum 2 clocks in 32-bit mode, 4 clocks in 16-bit mode wtr1_other 5 wtr1_other = wl - rl + 2 + 2(32-bit mode) wl - rl + 4 + 2(16-bit mode) write to read time for write and read happening on different chip selects, measured in clocks between write command and read command . for this reason, wl (the write latenc y) and the length of the actual write (2 or 4) need to be added to t wtr . figure 13-9 gives the details. 1 for drams that do not need this check, set equal to 4 t rrd 2 for ddr1 and mobile-ddr t ccd is 2 for 32-bit operation, 4 for 16-bit operation. 3 for ddr1 and mobile-ddr mode, t rtp is not explicitly given. it is equal to 4 for 16-bit mode, equal to 2 for 32-bit mode. 4 this timing parameter controls precharge all command period duration. the equations shown are the jedec definition of the t rpa . some dram vendors do not follow jedec on this, and list t rpa directly. in this case, set dram_time_rpa =t rpa . 5 field is part of register 0x60, dram_extra_attributes table 13-9. timing parameters (continued) timing parameter controls jedec parameter (jedec spec) formulae (all times in system bus clock periods) description d1 d2 d3 d4 dram_time_rtp read nop nop prechg bank a bank a dram_clk dram_command dram_address dram_dqs dram_dq
pxd20 microcontroller reference manual, rev. 1 13-12 freescale semiconductor preliminary?subject to change without notice figure 13-8. write to precharge timing diagram figure 13-9. write to read timing diagram figure 13-10. read to write timing diagram d1 d2 d3 d4 write nop nop bank a dram_clk dram_command dram_address dram_dqs dram_dq bank a/all t wr dram_write_wr1 prechg d1 d2 d3 d4 write nop nop dram_clk dram_command dram_address dram_dqs dram_dq t wtr dram_time_wtr1 read d1 d2 d3 d4 dram_clk dram_command dram_address dram_dqs dram_dq dram_time_rtw1 read nop nop write
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-13 preliminary?subject to change without notice 13.3.2.3 dramc command register (dramc_cmd) the dram command register (dra mc_cmd) gives the option to send commands directly to the dram. this register only operates when the command mode bit (cmd, bit 3) is set in the dramc_scr register. 13.3.2.4 dramc compact command register (dramc_ccmd) the dramc compact command register (dramc_ccmd) gives the option to send commands to the dram using only a 16-bit interface. address: base + 0x0010 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r0000000 000000000 w cmd reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 wcmd reset0000000000000000 figure 13-11. dramc command register (dramc_cmd) table 13-10. dramc_cmd field descriptions field description cmd[23:0] when the dramc_scr[cmd] bit is set, the value writte n to bits [23:0] of this register is output on the dram address group with following mapping: ? dram_address[14:0] = cmd[14:0] ? dram_address[15] = 0 ? if(dram_command[15] == 1) turn off cke dram attribute bit 1 ? dram_ba[2:0] = cmd[18:16] ? dram_web = cmd[19] ? dram_cas = cmd[20] ? dram_ras = cmd[21] ? dram_cs0 = cmd[22] ? dram_cs1 = cmd[23] note: the intended use of the command interface is to in itialize the dram and to put the dram into or out of the self-refresh and power-down modes. 1 cke is turned off on the same clock cycle as when the requested comm and is being se nt to the dram.
pxd20 microcontroller reference manual, rev. 1 13-14 freescale semiconductor preliminary?subject to change without notice address: base + 0x0014 access: user write-only 0 1 2 3 4 5 6 7 8 9 101112131415 r0000000 0 0000 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 wcmd reset0000000000000000 figure 13-12. compact comma nd register (dramc_ccmd) table 13-11. dramc_ccmd field descriptions field description cmd the compact command register gives the option to send commands to the dram using 16-bit writes. see table 13-12 . table 13-12. dramc_ccmd register options cmd[15:14] description 00 write dram attributes and wait (wait time = wait time till next command) wait is executed after writing attributes. ? cke = cmd[13] ? self ref en = cmd[12] ? clk on = cmd[11] ? cmd mode = cmd[10] ? if (cmd[7] == 1?b1) ? wait time = (cmd[6:0] 512) dram clock periods or ? wait time = (cmd[6:0] 32) dram clock periods 01 dram command ? dram_cs = cmd[12] ? dram_ras = cmd[11] ? dram_cas = cmd[10] ? dram_web = cmd[9] ? dram_ba[2:0] = cmd[8:6] ? dram_address[10] = cmd[5] ? if(cmd[4] == 1?b1) turn off cke dram attribute bit 1 1 cke is turned off the clock cycle when send ing the requested co mmand to the dram. 1x dram set mode registers ?dram_cs=0 ?dram_ras=0 ?dram_cas=0 ?dram_web=0 ? dram_address[13] = 0 ? dram_ba[2] = 0 ? dram_address[12:0] = cmd[12:0] ? dram_address[14:13] = cmd[14:13]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-15 preliminary?subject to change without notice the dramc_ccmd register?s main purpose is to be written during enter/exit of self-refresh (the auto-sequencer). the compact command register allows th ree types of actions to be executed: ? write dram attributes and wa it. wait is executed after updati ng the dram attributes. it is possible to update the cke bit, the self-refresh enable, the clk configuration (on/off), and the cmd mode setting. if, during the time the wait is executed, anot her command is written to the compact command register, this write is delayed until the wait is over. during this time, the peripheral bus and all buses connected to it bl ock and are not able to process any other read or write. ? write a command to dram without controlling the address. in th is mode, it is possible to send refresh, activate, and prechar ge commands to the dram ? write a dram mode register. 13.3.2.5 dqs config offset co unt register (dramc_dqs_oc) address: base + 0x0038 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r off3 off2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r off1 off0 w reset0000000000000000 figure 13-13. dqs config offset count register (dramc_dqs_oc) table 13-13. dramc_dqs_oc register field descriptions field description off[3:0] there is a separate field for each dqs input to t he controller. these fields code for an offset counted in elemental gate delay increments applied to each dqs slave. the number is a two-complement number that can be positive and negative. this register can be used to comp ensate systematic delay shift in th e dramc due to processing. leave this register all-zero, unless freescale issues a report giving a different value.
pxd20 microcontroller reference manual, rev. 1 13-16 freescale semiconductor preliminary?subject to change without notice 13.3.2.6 dqs config offset ti me register (dramc_dqs_ot) 13.3.2.7 dqs delay status (dramc_dqs_ds) address: base + 0x003c access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r0 0 off3 00 off2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 off1 00 off0 w reset0000000000000000 figure 13-14. dqs config offset time register (dramc_dqs_ot) table 13-14. dramc_dqs_ot register field descriptions field description off[3:0] there is a separat e field for each dqs input to the controller. these fields code for an offset counted in time units. this register can be used to advance or delay the re ad strobe. negative values advance the read strobe, positive values retard the read strobe. time delay coded = [field value (two?s complement)] tdram-clock/128. the applied offset range for a 200 mhz clock is approximately ? 290 ps. address: base + 0x0040 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r0000 mc2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 mc1 w reset0000000000000000 figure 13-15. dqs delay status (dramc_dqs_ds) table 13-15. dramc_dqs_ds re gister fiel d descriptions field description mc2 delay count output by the controller for the fi rst dqs master to code for 1/4 csb clock delay. mc1 delay count output by the controller for the second dqs master to code for 1/4 csb clock delay.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-17 preliminary?subject to change without notice 13.3.2.8 dramc extra a ttributes (dramc_extra) 13.4 functional description the dramc is a multi-port dram controller. it li stens to incoming requests on multiple buses and decides on each rising clock edge what co mmand needs to be sent to the dram. a block diagram is given in figure 13-1 . the major blocks of the dramc are described in the following sections. 13.4.1 interfacing with the dram 13.4.1.1 connecting the dram ? 32-bit dram systems need to be connected to all dq, dm, dqs lines. ? 16-bit dram systems need to connected to the low order bits of the data bus. (dq[15:0], dqs[1:0], and dm[1:0]) ? row/column address pins need to be connected starting with bit [0] and ending with the highest order dram bit. leave msb?s unconnected if the dram has fewer address pins than the controller. address: base + 0x0060 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r ccd_other wtr1_other con fig_ sdr con fig_ cas3 con fig_ a15 0 0 000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0000 cs_select w reset0000000000000000 figure 13-16. dramc extra at tributes (dramc_extra) table 13-16. dramc_extra register field descriptions field description ccd_other for description, refer to table 13-9 . wtr1_other for description, refer to table 13-9 . config_sdr 0 ddr mode. 1 reserved. config_cas3 reserved. config_a15 0 a15 pin acts as a15. 1 a15 pin acts as chip select 1. cs_select for description, refer to table 13-7 .
pxd20 microcontroller reference manual, rev. 1 13-18 freescale semiconductor preliminary?subject to change without notice ? dram bank address pins need to be connected starting with bit [0] and ending with the highest order bank address bit. leave msb unconnected if the dram has fewer bank address pins than the controller. ? electrical characteristics for the dram inte rface signals are conf igured using the pad configuration registers (pcrs) described in chapter 43, system integrat ion unit lite (siul). 13.4.2 programming dram device in ternal configuration register ? set burst type to sequential. ? burst length is always 16-byte. means 4-beat bur sts in a 32-bit system, 8-beat burst in a 16-bit system. ? set cas latency to lowest value dram can tolera te at intended speed, and then set write latency and read latency accordingly. ? set posted cas additive latency to 0. ? controller never uses auto-p recharge on read or write. ? configure dqs operation for single-ended operation. ? rtt and output drive strength configuration depends on el ectrical characteristics. 13.4.3 dram command engine this block decides what command to send to the dr amc next. there are four different commands that can be sent to the dram to service inco ming requests from the five incoming buses. ? precharge ? activate ? read ?write on every rising clock edge, the dram command engine first determines using parallel logic what is highest priority pending precharge, activate, read and write command. next, it decides which of these commands to send to the dram. the arbiters that make the decisions about what co mmand to send next to the dram are aware of the current state the dram is in. wh en arbitrating a command on the dr am bus, the following information is processed: ? for each bank, if it is precharged or not ? for each incoming request, if it hits in an already active bank or not ? for each bank, if the dram currently can accept a precharge command to it ? for each bank, if the dram currently can accept an activate command to it ? for each bank, if the dram currentl y can accept a read command to it ? for each bank, if the dram currentl y can accept a write command to it
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 13-19 preliminary?subject to change without notice the logic keeping track of what is currently possible on each of the ba nks is not in the dram command engine. it is part of the timing manager, whose ta sk is to signal to the dram command engine that commands are currently possible. 13.4.4 write buffer all incoming writes are sent first to the write buffer , part of the command engine . writes are sent to the dram in background, whenever possi ble. the dram tries to postpone the writes until there are no further outstanding read requests. however, when the wr ite buffer is full, or when there is a new request for an address already inside the write buffer, the dr amc writes the content of the write buffer to the dram. 13.4.5 timing manager the timing manager consists of a bank of counters. these counters keeps track of all dram timing parameters and signals to the dram command engine when a precharge, activate, read or write command is possible. this information is supplied to th e dram command engine for each bank separately. all timing parameters are programmable in software. 13.4.6 dram read block and dram write block sending a read or write command to the dram is a two-step process. first, the command is sent, which is done by the command engine. after some clock cycles, the data must follow. manipulating the read data is done by the read bl ock. for every read command sent to the dram, the command engine informs the re ad block. upon receiving th e read command, the read block delays this to account for dram pipelining. then, it receives the co rrect amount of data from the dram dq inputs and forwards this data to the correct bus. manipulating the write data is done by the write bloc k. it works the same way as the read block. the command engine informs the write block of a pendi ng write. upon receiving the command, the write block delays this to account for dram pipe lining. then, it r eceives the relevant data from the write buffer and transmits this to the dram. 13.4.7 bus interface the bus interface accepts a slave peripheral bus. the bus interface fulfills several functions: ? it contains all conf iguration registers ? it contains logic to send an erro r interrupt to the processor. the error interrupt is active when the fifo overflow or fifo underflow error condition and corresponding interrupt enable in register dramc_scr is set. the register summary is given in table 13-1 . the fifo overflow and underflow flag s are tied to a fifo that k eeps track of the number of dqs strobes the dram is expected to produce. if a read command is sent to the dram, the dram is expected to answer after producing the read da ta on its dq outputs, with some edges on its dqs output used by the controller to cl ock the read data. if the dramc produces the read strobes at an
pxd20 microcontroller reference manual, rev. 1 13-20 freescale semiconductor preliminary?subject to change without notice incorrect time, or produces not enough or too many read strobes, the dramc may detect some error conditions because they resu lt in an overflow or underflow of the fifo that keeps track of the number of outstanding dqs pulses. these bits do not detect timing configuration errors. underflows and overflows signaled by the read fi fo point to following possible error sources: ? incorrect configuration of the dram. burst length set incorrectly ? incorrect configuration of the dramc. ? incorrect rdly ? incorrect h_dqsdly ? incorrect q_dqsdly ? incorrect dram timing parameters or mis-match betwee n various settings. ? problems with the electrical connec tions between the dramc and the dram ? it contains a bypass path to send commands to the dram. this is because the dramc contains no logic to take care of dram initialization, programming the mo de registers, or putting the dram into or out of the sleep and standby modes li ke self-refresh. essentially, these functions are made available over the peripheral bus. to program the mode registers, the dramc needs to be put in a bypass mode, where inco ming requests are not serviced. in this bypass mode, commands are sent from the periphera l interface directly to the dram to program the mode registers or to put the dram into or out of sleep mode. ? during bypass mode, all reads and writes are bloc ked. refresh keeps running, but can be separately disabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-1 preliminary?subject to change without notice chapter 14 dramc priority manager 14.1 introduction the multi-port dram controller (dramc) has built-in arbiters that use a 4-bit priority signal. the dramc will try to service the request with the highest priority first. as a result of this, the dramc itself has no built-in way to fairly split the dram bandwidth over the different masters, taking into account their requirements. the task of setting the priorities is done by this bl ock, the priority manager. it will in a dynamic way set the priorities of the 7 dram busses in such a way that bandwidth is divided fair ly, and that each master gets its fair share of the bandwidth. the priority manager does this in a dynamic way. if a channel is not serviced dur ing some time, it will increase its priority. if a channel is serviced, it will d ecrease the priority. operation of the priority manager can be configured under software control. a block diagram of the priority manager is given in figure 14-1 . it accepts the request and ack (acknowledge) signals for all 7 dram busses, and produces the priority signals for the 7 busses. figure 14-1. priority manager block diagram the priority manager uses an ack-based schema, m eaning that the priority is dependent on how many times for the last n requests accep ted by the dramc, the current own bus won the request . the algorithm is given in figure 14-2 . a running average counter keeps track of how many acks on the memory busses out of the last n acks have been for the own bus, this number is then put in a look-up table that is configurable by writing some config registers, and the output of the look-up table then is the priority for the next request on this bus. ipmx0_prio_in (dcu) ipmx0_req ipmx1_req ipmx2_req ipmx3_req ipmx4_req priority manager ipmx0_ack ipmx1_ack ipmx2_ack ipmx3_ack ipmx4_ack ips interface slave bus ipmx0_prio[0:3] ipmx1_prio[0:3] ipmx2_prio[0:3] ipmx3_prio[0:3] ipmx4_prio[0:3]
pxd20 microcontroller reference manual, rev. 1 14-2 freescale semiconductor preliminary?subject to change without notice figure 14-2. priority manager algorithm this priority schema is versatile, as programming the look-up table allows controlling relative priority to other channels, and the average share of the bandwidth the current master will ge t. the priority schema introduces fairness, as the look-up ta ble can be programmed to reduce the priority of a bus that has ?won? a lot of requests, and increase the priority of a bus that lost a lot of requests. 14.2 features ? dynamic priority calculation based on ack-in history ? fully programmable using look-up table. ? can be configured for high or lo w latency and high or low bandwidth ? separate control over average latency and average bandwidth ? versatile so it can mimic the csb arbitration schema. ? fairness guaranteed by reducing priority of channe ls that receive a lot of grants, and increasing priority of channels that are denied the bus often. ? repeat transfer built into the dramc. priori ty manager can set the maximum repeat count by controlling when lowest priority occurs. ? feed-through mode where dcu priority is controlled di rectly by the dcu 14.3 detailed signal description table 14-1. detailed signal description signal i/o description ipg_clk i system clock ipg_hard_reset_b i system reset ips_clk_en i clock enable to signal edges on ips_clk ipmx0_req i dramc request for bus 0 ipmx1_req i dramc request for bus 1 ipmx2_req i dramc request for bus 2 ipmx3_req i dramc request for bus 3 ipmx4_req i dramc request for bus 4 ipmx0_req_ack i dramc request acknowledge for bus 0 ipmx0_req_ack all other acks count how many ipmx0_req_ack?? out of last n acks on all channels combined look up table (configuration) ipmx0_prio[0:3]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-3 preliminary?subject to change without notice 14.4 memory map and register definition 14.4.1 memory map ipmx1_req_ack i dramc request acknowledge for bus 1 ipmx2_req_ack i dramc request acknowledge for bus 2 ipmx3_req_ack i dramc request acknowledge for bus 3 ipmx4_req_ack i dramc request acknowledge for bus 4 ipmx0_prio_in[0:3] i incoming priority signal for dcu (bus 0) ipmx0_prio[0:3] o outgoing priority signal to dramc for bus 0 ipmx1_prio[0:3] o outgoing priority signal to dramc for bus 1 ipmx2_prio[0:3] o outgoing priority signal to dramc for bus 2 ipmx3_prio[0:3] o outgoing priority signal to dramc for bus 3 ipmx4_prio[0:3] o outgoing priority signal to dramc for bus 4 ips_module_en i slave bus module enable ips_addr[0:8] i slave bus address ips_rwb i slave bus read/write signal ips_byte_en[0:3] i slave bus byte enables ips_wdata[0:31] i slave bus write data bus ips_rdata[0:31] o slave bus read data bus table 14-2. priority manager memory map offset or address register access reset value location 0x80 prioman_config1 (cfg1) r/w 0x0007_7777 on page 14-5 0x84 prioman_config2 (cfg2) r/w 0x0000_0011 on page 14-5 0x88 hiprio_config (hpcfg) r/w 0x0 on page 14-7 0x8c lut 0 main upper (mlutu0) r/w 0x01111_1222 on page 14-8 0x90 lut 1 main upper (mlutu1) r/w 0x01111_1222 on page 14-8 0x94 lut 2 main upper (mlutu2) r/w 0x01111_1222 on page 14-8 0x98 lut 3 main upper (mlutu3) r/w 0x01111_1222 on page 14-8 0x9c lut 4 main upper (mlutu4) r/w 0x01111_1222 on page 14-8 0xa0 lut 0 main lower (mlutl0) r/w 0x2334_567a on page 14-9 0xa4 lut 1 main lower (mlutl1) r/w 0x2334_567a on page 14-9 table 14-1. detailed signal description signal i/o description
pxd20 microcontroller reference manual, rev. 1 14-4 freescale semiconductor preliminary?subject to change without notice 0xa8 lut 2 main lower (mlutl2) r/w 0x2334_567a on page 14-9 0xac lut 3 main lower (mlutl3) r/w 0x2334_567a on page 14-9 0xb0 lut 4 main lower (mlutl4) r/w 0x2334_567a on page 14-9 0xb4 lut 0 alternate upper (alutu0) r/w 0x0 on page 14-10 0xb8 lut 1 alternate upper (alutu1) r/w 0x0 on page 14-10 0xbc lut 2 alternate upper (alutu2) r/w 0x0 on page 14-10 0xc0 lut 3 alternate upper (alutu3) r/w 0x0 on page 14-10 0xc4 lut 4 alternate upper (alutu4) r/w 0x0 on page 14-10 0xc8 lut 0 alternate lower (alutl0) r/w 0x0 on page 14-11 0xcc lut 1 alternate lower (alutl1) r/w 0x0 on page 14-11 0xd0 lut 2 alternate lower (alutl2) r/w 0x0 on page 14-11 0xd4 lut 3 alternate lower (alutl3) r/w 0x0 on page 14-11 0xd8 lut 4 alternate lower (alutl4) r/w 0x0 on page 14-11 0xdc performance monitor config (pmcfg) r/w 0x0 on page 14-12 0xe0 event time counter (evtmr) r/w 0x0 on page 14-13 0xe4 event time preset (evprst) r/w 0x0 on page 14-13 0xe8 performance monitor 1 address low (pm1l) r/w 0x0 on page 14-14 0xec performance monitor 2 address low (pm2l) r/w 0x0 on page 14-14 0xf0 performance monitor 1 address high (pm1h) r/w 0x0 on page 14-14 0xf4 performance monitor 2 address high (pm2h) r/w 0x0 on page 14-14 0xf8?0xfc reserved 0x100 performance monitor 1 read counter (pm1cntr) r 0x0 on page 14-14 0x104 performance monitor 2 read counter (pm2cntr) r 0x0 on page 14-14 0x108 performance monitor 1 write counter (pm1cntw) r 0x0 on page 14-14 0x10c performance monitor 2 write counter (pm2cntw) r 0x0 on page 14-14 0x110 granted ack counter 0 (gackctr0) r on page 14-14 0x114 granted ack counter 1 (gackctr1) r on page 14-14 0x118 granted ack counter 2 (gackctr2) r on page 14-14 0x11c granted ack counter 3 (gackctr3) r on page 14-14 0x120 granted ack counter 4 (gackctr4) r on page 14-14 0x124 cumulative wait counter 0 (cumwctr0) r on page 14-14 0x128 cumulative wait counter 1 (cumwctr1) r on page 14-14 table 14-2. priority manager memory map (continued) offset or address register access reset value location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-5 preliminary?subject to change without notice 14.4.2 register descriptions 14.4.2.1 prioman_config1, prioman_config2 (cfg1, cfg2) 0x12c cumulative wait counter 2 (cumwctr2) r on page 14-14 0x130 cumulative wait counter 3 (cumwctr3) r on page 14-14 0x134 cumulative wait counter 4 (cumwctr4) r on page 14-14 0x138 summed priority counter 0 (sprioctr0) r on page 14-14 0x13c summed priority counter 1 (sprioctr1) r on page 14-14 0x140 summed priority counter 2 (sprioctr2) r on page 14-14 0x144 summed priority counter 3 (sprioctr3) r on page 14-14 0x148 summed priority counter 4 (sprioctr4) r on page 14-14 offset: 0x80 read/write 0123456789101112131415 r lutsel4 lutsel3 lut sel2 lutsel1 lutsel0 ackcnt4 w reset00000000 00000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ackcnt3 ackcnt2 ackcnt1 ackcnt0 w reset01110111 01110111 = unimplemented or reserved figure 14-3. prioman_config1 register (cfg1) table 14-2. priority manager memory map (continued) offset or address register access reset value location
pxd20 microcontroller reference manual, rev. 1 14-6 freescale semiconductor preliminary?subject to change without notice offset: 0x84 read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r con g dcu ovr acks el4 acks el3 acks el2 acks el1 acks el0 w reset00000000 00010001 = unimplemented or reserved figure 14-4. prioman_config2 register (cfg2) table 14-3. cfg1 and cfg2 field descriptions field description cong 1: congested flag is set 0: congested flag is cleared dcuovr 1: priority for channel 0 taken from dcu directly 0: dcu priority follows normal schema. acksel4 acksel2 acksel2 acksel1 acksel0 there is one of these bits for each priority manager channel. they determine what happens if the current channel is not requesting 1: if current channel is not requesting, every ack fo r other channel is treated like a ack for the current channel. will regulate default priority to quite low value 0: no special overrule lutsel4 lutsel3 lutsel2 lutsel1 lutsel0 selectors between primary and secondary look-up table configuration register 0: select main look-up table configuration register 1: select alternate look-up table configuration register 2: select alternate look-up table configuration register if congested flag is set 1 3: select alternate look-up table configuration register if dcu incoming priority bit 3 is high. 1 congested flag is explained in section 14.4.2.2, hpcfg ackcnt4 ackcnt3 ackcnt2 ackcnt1 ackcnt0 configuration fields, one for every channel, that determi nes over how many requests the number of acks for the self channel is counted. 2 0 : 1 1 : 2 2 : 3 3 : 4 4 : 6 5 : 8 6 : 12 7 : 16 8 : 24 9 : 32 10 : 48 11 : 63
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-7 preliminary?subject to change without notice 14.4.2.2 hpcfg this register controls the hiprio de tection logic. the hiprio detection l ogic detect what percentage of the requests acked by the dram c are ack-ed with a priority larger than 8. 2 look-up table input is running average of the number of acks fo r the self channel counted over the grant total of the last n acks. ack_count[2:0] cont rols the parameter n. offset: 0x88 read/write 0123456789101112131415 r setcglvl clrcglvl w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fltrband avghipr w reset00000000 00000000 = unimplemented or reserved figure 14-5. hpcfg register table 14-4. hpcfg field descriptions field description avghipr average number of hi priority requests to dram, coded between values 0x1000 and 0x0000 0x1000: 100% high-priority requests 0x0000: 0% high-priority requests fltrband this setting controls the averaging time of the filter used fo r average_hipriority[12:0] 0: time constant w0 = 8 acks, k = 0.125 1: time constant w0 = 16 acks, k = 0.0625 2: time constant w0 = 32 acks, k = 0.0312 3: time constant w0 = 64 acks, k = 0.0156 4: time constant w0 = 128 acks, k = 0.0078 5: time constant w0 = 256 acks, k = 0.0039 6: time constant w0 = 512 acks, k = 0.0020 7: time constant w0 = 1024 acks, k = 0.0010 setcglvl if(average_hipriority[4:12] > setcglvl) -> set the congested flag clrcglvl if(average_hipriority[4:12] < clrcglvl) -> clear the congested flag
pxd20 microcontroller reference manual, rev. 1 14-8 freescale semiconductor preliminary?subject to change without notice 14.4.2.3 lookup table main upper registers (mlutu0?mlutu4) these registers contain the u pper 8 entries of the look-up tables for channels 0 to 4, main table. all registers contain identical fields. the content of these registers if the ?main? table is enabled for the particular lut. offsets: 0x8c (mluto0) 0x90 (mlutu1) 0x94 (mlutu2) 0x98 (mlutu3) 0x9c (mlutu4) read/write 0123456789101112131415 r prio15 prio14 prio13 prio12 w reset00010001 00010001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prio11 prio10 prio9 prio8 w reset00010010 00100010 figure 14-6. mlutu registers table 14-5. mlutu field descriptions field description prio15 priority setting if 15 or more ack?s for own channel counted prio14 priority setting if 14 ack?s for own channel counted prio13 priority setting if 13 ack?s for own channel counted prio12 priority setting if 12 ack?s for own channel counted prio11 priority setting if 11 ack?s for own channel counted prio10 priority setting if 10 ack?s for own channel counted prio9 priority setting if 9 ack?s for own channel counted prio8 priority setting if 8 ack?s for own channel counted
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-9 preliminary?subject to change without notice 14.4.2.4 lookup table main lower registers (mlutl0?mlutl4) these registers contain the u pper 8 entries of the look-up tables for channels 0 to 4, main table. all registers contain identical fields. the content of these registers if the ?main? table is enabled for the particular lut. offsets: 0xa0 (mlutl0) 0xa4 (mlutl1) 0xa8 (mlutl2) 0xac (mlutl3) 0xb0 (mlutl4) read/write 0123456789101112131415 r prio7 prio6 prio5 prio4 w reset00100011 00110100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prio3 prio2 prio1 prio0 w reset01010110 01111010 figure 14-7. mlutl registers table 14-6. mlutl field descriptions field description prio7 priority setting if 7 ack?s for own channel counted prio6 priority setting if 6 ack?s for own channel counted prio5 priority setting if 5 ack?s for own channel counted prio4 priority setting if 4 ack?s for own channel counted prio3 priority setting if 3 ack?s for own channel counted prio2 priority setting if 2 ack?s for own channel counted prio1 priority setting if 1 ack for own channel counted prio0 priority setting if 0 ack?s for own channel counted
pxd20 microcontroller reference manual, rev. 1 14-10 freescale semiconductor preliminary?subject to change without notice 14.4.2.5 lookup table alternate upper registers (alutu0?alutu4) these registers contain the u pper 8 entries of the look-up tables for channels 0 to 4, main table. all registers contain identical fields. the content of these registers if the ?alternate? table is enabled for the particular lut. offsets: 0xb4 (alutu0) 0xb8 (alutu1) 0xbc (alutu2) 0xc0 (alutu3) 0xc4 (alutu4) read/write 0123456789101112131415 r prio15 prio14 prio13 prio12 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prio11 prio10 prio9 prio8 w reset00000000 00000000 figure 14-8. alutu registers table 14-7. alutu field descriptions field description prio15 priority setting if 15 or more ack?s for own channel counted prio14 priority setting if 14 ack?s for own channel counted prio13 priority setting if 13 ack?s for own channel counted prio12 priority setting if 12 ack?s for own channel counted prio11 priority setting if 11 ack?s for own channel counted prio10 priority setting if 10 ack?s for own channel counted prio9 priority setting if 9 ack?s for own channel counted prio8 priority setting if 8 ack?s for own channel counted
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-11 preliminary?subject to change without notice 14.4.2.6 lookup table alternate lower registers (alutl0?alutl4) these registers contain the upper 8 entries of the look- up tables for channels 0 to 4, alternate table. all registers contain identical fields. the content of thes e registers if the ?alternate? table is enabled for the particular lut. offsets: 0xc8 (alutl0) 0xcc (alutl1) 0xd0 (alutl2) 0xd4 (alutl3) 0xd8 (alutl4) read/write 0123456789101112131415 r prio7 prio6 prio5 prio4 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prio3 prio2 prio1 prio0 w reset00000000 00000000 figure 14-9. alutl registers table 14-8. alutl field descriptions field description prio7 priority setting if 7 ack?s for own channel counted prio6 priority setting if 6 ack?s for own channel counted prio5 priority setting if 5 ack?s for own channel counted prio4 priority setting if 4 ack?s for own channel counted prio3 priority setting if 3 ack?s for own channel counted prio2 priority setting if 2 ack?s for own channel counted prio1 priority setting if 1 ack for own channel counted prio0 priority setting if 0 ack?s for own channel counted
pxd20 microcontroller reference manual, rev. 1 14-12 freescale semiconductor preliminary?subject to change without notice 14.4.2.7 performance monitor config register (pmcfg) offset: 0xdc read/write 0123456789101112131415 r int inte n dma req dma rstp evt tim w clri nt evt tim trg reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lutsel4 lutsel3 lutsel2 lutsel1 lutsel0 w reset00000000 00000000 = unimplemented or reserved figure 14-10. performance monitor config register (pmcfg) table 14-9. pmcfg field descriptions field description int (read-only)(sticky bit) - interrupt pending register - set when interrupt is made pending clrint (write only) - writing this bit ?1? clears bit ?int? to zero. inten interrupt enable - when this bit is ?1? and bit ?int? is ?1?, the processor gets an interrupt request dmareq (read-only) - dma request - set when ?event counter time? reaches terminal count. cleared when first coun ter register is read. dmarstp 1 1 this bit should be set as long as the dma channel is not co nfigured to handle the request. after configuring the dma, clear the bit, and data will start to be transferred on every time tick. (read/write) - when this bit is ?1?, the dma request is cleared, and cannot get set. when this bit is ?0?, the dmareq functions as expected. evttim 1: event counter free run - after reaching terminal count, the event time counter is reloaded from event time preset f, and a new cycle starts. 0 : event counter single-shot - after reaching term inal count, the event time counter stays at 0, and is not reloaded. evttimtrg (write-only bit) - writing to this bit causes all count registers to be transferred to the buffer registers, and subsequent be cleared. it causes the event counter to be reloaded from the event time preset register. no interrupt or dma request is generated on writing this register, but both will be generated when the event time counter register reaches terminal count. lutsel4 lutsel3 lutsel2 lutsel1 lutsel0 selectors between primary and secondary look-up table configuration register these selectors determine which lut is used for the ?summed priority co unters?. the priorities entered into these counters may depend on a different lut than the priorities sent to the dramc. 0: select main look-up table configuration register 1: select alternate look-up table configuration register 2: select alternate look-up table configuration register if congested flag is set 2 3: select alternate look-up table configuration register if dcu incoming priority bit 3 is high 2 congested flag is explained in section 14.5.3, congestion detector .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-13 preliminary?subject to change without notice 14.4.2.8 event time timer (evtmr) this 32-bit register has only one field - the 24-bit event time counter. the counter decrements to 0, on reaching 0, the interrupt a nd the dma request are made pending. on reaching 0, the counter will re-load from event count preset register if the bit eventcountfreerun is set in the perfmon_config register. on reaching terminal count, all pe rformance monitor count register s are loaded in the performance monitor buffer registers, and cleared. the register is read/write. 14.4.2.9 event time preset (evprst) the event_time_preset register contai ns the 24-bit preset value to be lo aded into the event time counter register in case this preloads. offset: 0xe0 read/write 0123456789101112131415 r evtmr[23:16] w reset?000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r evtmr[15:0] w reset0000000000000000 = unimplemented or reserved figure 14-11. event time counter register (evtmr) offset: 0xe4 read/write 0123456789101112131415 r evprst[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r evprst[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-12. event time preset register (evprst)
pxd20 microcontroller reference manual, rev. 1 14-14 freescale semiconductor preliminary?subject to change without notice 14.4.2.10 performance monitor address registers these registers determine if a cp u (e200) access hits in the perfor mance monitor 1 or performance monitor 2 address space. 1. if ((e200 cpu address >= perfor mance monitor 1 address low) && (e200 cpu address < performa nce monitor 1 address hi)) - increment performance mon itor 1 read counter on reads - increment performance monito r 1 write counter on writes. 2. if ((e200 cpu address >= perf ormance monitor 2address low) && (e200 cpu address < performa nce monitor 3address hi)) - increment performance mon itor 2 read counter on reads - increment performance monito r 2 write counter on writes. 14.4.2.11 counter registers offsets: 0xe8 (pm1l) 0xec (pm2l) 0xf0 (pm1h) 0xf4 (pm2h) read/write 0123456789101112131415 r addr[31:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr [15:5] w reset00000000 00000000 = unimplemented or reserved figure 14-13. performance monitor address registers offset: 0x100 (pm1cntr) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-14. performance monitor 1 read counter (pm1cntr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-15 preliminary?subject to change without notice offset: 0x104 (pm2cntr) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-15. performance monitor 2 read counter (pn2cntr) offset: 0x108 (pm1cntw) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-16. performance moni tor 1 write counter (pm1cntw) offset: 0x10c (pm2cntw) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-17. performance moni tor 2 write counter (pm2cntw)
pxd20 microcontroller reference manual, rev. 1 14-16 freescale semiconductor preliminary?subject to change without notice offset: 0x110 (gackctr0) read 0123456789101112131415 r sprioctr2[7:0] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-18. granted ack counter 0 (gackctr0) offset: 0x114 (gackctr1) read 0123456789101112131415 r sprioctrl2[15:8] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-19. granted ack counter 1 (gackctr1) offset: 0x118 (gackctr2) read 0123456789101112131415 r sprioctr2[23:16] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-20. granted ack counter 2 (gackctr2)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-17 preliminary?subject to change without notice offset: 0x11c (gackctr3) read 0123456789101112131415 r sprioctr3[7:0] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-21. granted ack counter 3 (gackctr3) offset: 0x120 (gackctr4) read 0123456789101112131415 r sprioctr3[15:8] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-22. granted ack counter 4 (gackctr4) offset: 0x124 (cumwctr0) read 0123456789101112131415 r sprioctr3[23:16] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-23. cumulative wait counter 0 (cumwctr0)
pxd20 microcontroller reference manual, rev. 1 14-18 freescale semiconductor preliminary?subject to change without notice offset: 0x128 (cumwctr1) read 0123456789101112131415 r sprioctr4[7:0] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-24. cumulative wait counter 1 (cumwctr1) offset: 0x12c (cumwctr2) read 0123456789101112131415 r sprioctr4[15:8] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-25. cumulative wait counter 2 (cumwctr2) offset: 0x130 (cumwctr3) read 0123456789101112131415 r sprioctr4[23:16] cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-26. cumulative wait counter 3 (cumwctr3)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-19 preliminary?subject to change without notice offset: 0x134 (cumwctr4) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-27. cumulative wait counter 4 (cumwctr4) offset: 0x138 (sprioctr0) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-28. summed priority counter 0 (sprioctr0) offset: 0x13c (sprioctr1) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-29. summed priority counter 1 (sprioctr1)
pxd20 microcontroller reference manual, rev. 1 14-20 freescale semiconductor preliminary?subject to change without notice the counter registers contain 19 diff erent 24-bit counter values. all th ese counter values count certain events. xxx gives the details on the na ture of the event. counter values summed priority counter 2, summed priority counter 3 and summed priority counter 4 are available in 2 sets of registers. firstly, they are available in the registers with the same name, but they are also available in a set of 3 other registers ( granted ack counter or cumulative wait counter registers). the multiple -mapping of the 3 upper summed priority counter registers is done to allow easy and compac t dma transfer to memory. because of the multiple mapping, all 19 count values can be transferred to memory wi th a 64-byte dma transfer starting offset: 0x140 (sprioctr2) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-30. summed priority counter 2 (sprioctr2) offset: 0x144 (sprioctr3) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-31. summed priority counter 3 (sprioctr3) offset: 0x148 (sprioctr4) read 0123456789101112131415 r cntr[23:16] w reset?0000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cntr[15:0] w reset00000000 00000000 = unimplemented or reserved figure 14-32. summed priority counter 4 (sprioctr4)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-21 preliminary?subject to change without notice at address 0x100. the multiple mapping allows the dm a to get all information with a 64-byte transfer, but some decompression is needed on de coding the data, while the cpu can read the 19 registers, and just mask out the upper 8 bits to get relevant information. table 14-10. monitor counter descriptions field description performance monitor 1 read counter every time the powerpc performs a read access, whose address is higher or equal than the performance monitor 1 address low , and lower than the performance monitor 1 address high , this counter is incremented 1 . performance monitor 2 read counter every time the powerpc performs a read access, whose address is higher or equal than the performance monitor 2 address low , and lower than the performance monitor 2 address high , this counter is incremented 1 . performance monitor 1 write counter every time the powerpc per forms a write access, whose address is higher or equal than the performance monitor 1 address low , and lower than the performance monitor 1 address high , this counter is incremented 1 . performance monitor 2 write counter every time the powerpc per forms a write access, whose address is higher or equal than the performance monitor 2 address low , and lower than the performance monitor 2 address high , this counter is incremented 1 . granted ack counter 0 every time the dramc grants a request for channel 0, this counter is incremented 1 . granted ack counter 1 every time the dramc grants a request for channel 1, this counter is incremented 1 . granted ack counter 2 every time the dramc grants a request for channel 2, this counter is incremented 1 . granted ack counter 3 every time the dramc grants a request for channel 3, this counter is incremented 1 . granted ack counter 4 every time the dramc grants a request for channel 4, this counter is incremented 1 . cumulative wait counter 0 every time there is a requ est pending to the dramc for channel 0, and its not granted in the current cycle, this counter is incremented 1 . cumulative wait counter 1 every time there is a requ est pending to the dramc for channel 1, and its not granted in the current cycle, this counter is incremented 1 . cumulative wait counter 2 every time there is a requ est pending to the dramc for channel 2, and its not granted in the current cycle, this counter is incremented 1 . cumulative wait counter 3 every time there is a requ est pending to the dramc for channel 3, and its not granted in the current cycle, this counter is incremented 1 . cumulative wait counter 4 every time there is a requ est pending to the dramc for channel 4, and its not granted in the current cycle, this counter is incremented 1 . summed priority counter 0 every time a request is gr anted by the dramc for channel 0, a priority code 2 is added to this counter 1 . summed priority counter 1 every time a request is gr anted by the dramc for channel 1, a priority code 2 is added to this counter 1 . summed priority counter 2 every time a request is gr anted by the dramc for channel 2, a priority code 2 is added to this counter 1 . summed priority counter 3 (sprioctr3) every time a request is granted by the dramc for channel 3, a priority code 2 is added to this counter 1 . this counter shares a register location with granted ack counters 3 and 4 and cumulative wait counter 0. summed priority counter 4 (sprioctr4) every time a request is granted by the dramc for channel 4, a priority code 2 is added to this counter 1 . this counter shares a register location with cumulative wait counters 1, 2 and 3.
pxd20 microcontroller reference manual, rev. 1 14-22 freescale semiconductor preliminary?subject to change without notice 14.5 functional description the priority manager calculates the outgoing priority fo r all 5 channels of dramc. the priority of any channel at a given time, is a function of the request granting history of the dram c. a granted request is called an ack, so this schema is called an ack-based schema, becaus e the priority is determined by the history of which channels have been ack-ed in the past and when. the block diagram in figure 14-2 makes this dependency clear: priori ty manager determines priority on the basis of the outstanding requests, and th e requests granted (the ack?s) by the dramc. the priority manager calculates the priorities in a dynamic way. this means, a prio rity is never constant, but changes over time, even when the request is not serviced. as a request ages while its not being serviced, its priority will escalate to higher level, and as the level increase s, it will eventually be serviced. the dramc has a built-in preference to offer repeat for any incoming read request. the repeat goes on as long as the requesting channel keeps requesting, a nd its priority is greater than 0. when the outgoing priority for any channel is 0, the dr amc will no longer servic e or repeat the request . this feature allows the priority manager to control the maxi mum repeat count for any incoming channel. 14.5.1 description of operation ? overview priority calculation for all channels is independent. so, there is no direct cross-depende ncy of the priority of one channel on the priority of another channel. th e algorithm looks at the la st n arbitration cycles on the bus. n is a programmable number, set by fields ack_count in register prio_man , described in figure 14-3 . for the last n arbitration cycl es, the number of time s the own channel won the bus, is summed up, and saturated to a maximum of 15. this number of 0 to 15 is then input in to the applicable look-up table, and the value for the particular number, is the priority code going to the dramc. if e.g. n is set to 16, and the own channel was granted the bus 4 times in the last 16 bus grant, the index into the look-up table is 4, and the field prio4 of the relevant look-up table will be the priority going to the dramc. there are 2 look-up tables for every channel. the ?mai n? look-up table, and the ?alternate? look-up table. the algorithm may switch between both, depending on some settings. ? the ?default? look-up table is the ?main.? however, the ?alternate? will be used if 1 all counters in this table are double-b uffered. figure at the left gives the details. there are always 2 registers associated with every counter. the first register is the ?counter?. it counts the events mentioned in the table. when the trigger condition occurs- the time event counter reaching terminal count -, the ?counter? register is transfe rred to the ?buffer? register, and the ?counter? register is cleared. when accessing the register, its always the buffer register value that is returned. 2 the priority code added may or may not be the same as the priority code the request used on the dramc. the codes will be equal if the lut sel field for the channel is the same in registers prioman_config and perfmon_config . if the lut sel fields differ, the field in prioman_config is used to calculate the channel priority code on the dram, and the field in perfmon_config is used to calculate the priority code added to this register. the possibility to use unequal lut sel fields, makes it possible to use the ?main? look-up tables for dram priority programming , and the ?alternate? look-up tables for per formance monitoring. making the look-up tables independent, opens a wide possibility in what can be monitored. +1 r en readable value tercount condition event "counter" register "buffer" register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-23 preliminary?subject to change without notice ? the particular channel has been configured to look at the dcu incoming priority, and the dcu incoming priority is 8 or higher. ? the particular channel has been configured to look at the congestion monitor, and this block indicates the multi-port dram is congested. 14.5.2 description of operation ? block diagram a block diagram of the block is given in figure 14-33 . figure 14-33. priority channel block diagram shift register 1 shifts in information of the recent ack?s. its a 63-stage shift register, so it contains information on the last 63 bus cycles of the dramc. the shift register is shifted any ti me a read or write request has been granted to the dram. (an ack to the requesting bus), or when there is an idle_pulse. an idle pulse is gene rated every time th e dram is idle for 4 consecutive clock cycles. idle means none of the 5 incoming busses is making a request. the shift data in is the corrected ack for the self channel. if the shift register shifts because the current cycle is granted to the ?self? channel, a ?1? is shifted in, if not a ?0? is sh ifted in. it always occurs like this when the own channel is requesting access. howeve r, if the own channel is not requesting access, depending on control bit ack_sel , a ?1? or a ?0? is shifted in. if ack_sel is ?1?, a ?1? will be shifted in all the time when the self channel is not re questing, and there is an ack on any ot her channel, or there is an idle pulse. if ack_sel is ?0?, zeros are shifted in. the correction for the non-requesting channel allows th e user to steer the ?default? priority, i.e., the priority that the channel will get, when it has not been requesting for some time. if ack_sel is set ?1?, the default priority will be low. this setting is appropriate for peripherals with (large) fifo?s. when they are read or write on any channel or idle pulse en 63-bit 1 data in own channel serviced or own channel not requesting combinatorial logic 3 22 ack_count 21 20 2 4 + lut 0 1 5 6 alternate lut 27 main lut 26 01 7 lut sel 26 alternate lut 27 congested 24 dcu priority 23 d 8 1 28 dcu priority[3:0] dcu overrule 29 chan_priority [3:0] 30 only dcu channel
pxd20 microcontroller reference manual, rev. 1 14-24 freescale semiconductor preliminary?subject to change without notice not requesting, the fifo is quite full, and when they do get on the bus, its ok for them to start with low priority, and escalate to higher after some time. setting ack_sel to ?0? is appropriate for periphera ls that desire high priority. the e200z4d and gfx2d gpu are in this case. when they ar e not on the bus, its because they find the instruction or data that they need in the processor caches, so th ey don?t request. when the cache mi sses, the request comes on the bus, and need to be serviced fast. theref ore, ack_sel is set ?0?, the default priority will be high, and servicing fast. if e200z4d and/or gfx2d get on the bus a lot (e.g. due to a lot of cache swapping), the priority manager will detect this, a nd degrade their priorities over time, so th e other masters still get their fair share of bus bandwidth. the output of the shift register anded in 2 to look at only the last n ack?s. combinatorial logic 3 decodes the and-ing code from register field ack_count . the number of ones afte r the and-ing is added up in adder 4 , and saturated, so that the result out of adder 4 is a number in the range of 0 to 15. this number is input in the look-up table 5 . table look-up content is taken for e.g. channel 1 from register lut 1 main[63:0] or lut 1 alternate[63:0] . because of the 64-bit nature of the registers, actually 4 32-bit registers are involved, whos e description is given in figure 14-6 , figure 14-7 , figure 14-8 , and figure 14-9 . selection on whether to use the ?main? or the ?alternate ? register, is done via mux 6 . the mux condition has 2 possible sources again, selected by mux 7 , by means of control bit lut sel , described in register prioman_config , with details in figure 14-3 . if lut sel is ?1?, alternate table is selected when the multi-port controller is congested. if lut sel is ?0?, alternate table is selected when dc u incoming priority is higher than 8. pipeline register 8 is present purely for implementation reasons. it has no algorithmic function. for the dcu, an additional bypass mux 9 is present. it overrules the prioman logic, and inserts the incoming dcu priority in the output, if control bit dcu overrule is set. this bit is present in register prioman_config , with details in figure 14-3 . 14.5.3 congestion detector the congestion detectors purpose is to detect when the dramc is co ngested. congestion is assumed if the share of the requests with priori ties equal or greater than 8 is more than a certain percentage. if congestion occurs, the priority manager may react by exchanging the look-up tabl es with the alternate look-up tables, and in this way, reduc e the average priority of the incoming requests. the reduced priorities mean that on average, every incoming channel gets a lower priority, and the dramc will try harder to optimize on bandwidth, and less to optimize to service the high-priority requests first. the switch-over is driven by the congestion state. if many requests come in on ?hi gh priority,? so they al l need to be serviced ?first,? the ?congested? flag goes high, and the controll er reacts to this by reduc ing the request priorities (by switching in the alternate tables ), so it can concentrate on the ones that are ?really? important, and get room again to optimized bandwidth.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 14-25 preliminary?subject to change without notice figure 14-34. congestion detector - simplified block diagram a block diagram of the conges tion detector is given in figure 14-34 . the congestion dete ctor consists of an averaging block, followed by a comparator with hysteresis. the averaging block calculates the weighted average of the percentage of high-priority requests, like given below. the weighted average uses an expone ntial weighting when looking at th e past granted requests. requests that have been granted in a more distant past, get a lower weighting co efficient. the weighting coefficient uses an exponential back-off, following the formulae in this formulae, weight(k) is the weighting coefficient that is used for the request that was granted k acknowledges ago, meaning k other requests have been granted after this one. the coefficient w0 is programmable, dependent on the contro l field filter bandwidth in regi ster hiprio_config, detailed in figure 14-5 . the value input in the weighting block, val(k) is dependent on the pr iority of the request granted. it is 0 if the priority was 7 or lower, it is 0x10000 if the priority was 8 or lower. the result of the weighted average is a number be tween 0 and 0x10000, that is input in the comparator with hysteresis. this result, average_hipriority, can be monitored in register hiprio_config . the weighted averaging block is followed by a compar ator with hysteresis, whose high and low threshold are programmable. ?if average_hipriority is greater than set_congest_level , the ?congested? flag is set. ?if average_hipriority is lower than clear_congest_level , the ?congested? flag is cleared. requests granted requests granted to high or low priority weighted average over programmable averaging past granted requests depth set congest level clear congest level comparator with hysteresis congested average high priority averagepriority weigth k ?? val k ?? ? ? = weigth k ?? 1 w0 -------- - k w0 -------- - ? ?? ?? exp ? =
pxd20 microcontroller reference manual, rev. 1 14-26 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 15-1 preliminary?subject to change without notice chapter 15 e200z4d core this chapter provides an overview of the e200z4d microprocessor core pres ent in this device. it includes the following: ? an overview of the core, including the block diagram ( figure 15-1 ) ? a summary of the feature set for this core (see section 15.2, features ) ? a description of th e execution units (see section 15.2.1, execution unit features ) ? a description of the memory management architecture (see section 15.2.3, memory management unit features ) ? high-level details of the core memory and coherency model (see section 15.2.4, system bus (core complex interface) features ) ? high-level details of the nexus 3+ features (see section 15.2.5, nexus 3+ features ) ? a summary of the programming model for this core (see section 15.3, programming model ) ? an overview of the register set (see section 15.3.1, register set ) ? an overview of the instruction set (see section 15.3.2, instruction set) ? an overview of interrupts and exception handling (see section 15.3.3, interrupts and exception handling ) ? a summary of instruction pipeline and flow (see section 15.4, microarchitecture summary ) 15.1 overview the e200z4d processor family is a set of cpu core s that implement low-cost versions of power architecture technology. the e200z4d core is a dual- issue, 32-bit design with 64-bit general-purpose registers (gprs). the e200z4d integrates a cpu co re, a memory management unit (mmu), a 4-kb instruction cache, and a nexus class 3+ real-tim e debug unit. separate instruction and data ahb 2.v6 system interfaces are provided. the e200z4d is compliant with the po werpc instruction set architecture (isa). it does not support power isa floating-point instructions in hardware, but traps them so they can be emulated by software. instructions of the embedded floating-point categor y are provided to support r eal-time single-precision embedded numerics operations using the general-purpose registers. instructions of the signal processing extension ( spe) category are provided to support real-time simd fixed-point and single-precision embe dded numerics operations using the general-purpose registers. all arithmetic instructions that execut e in the core operate on data in the general-purpose registers (gprs). the gprs have been extended to 64-bits in order to support vector instruc tions defined by the spe category. these instructions operate on a vector pair of 16-bit or 32-bit data types and de liver vector and scalar results. in addition to the base power isa embedded category instruction set, the co re also implements the variable-length encoding category (vle), whic h provides improved code density. see the eref and
pxd20 microcontroller reference manual, rev. 1 15-2 freescale semiconductor preliminary?subject to change without notice supplementary vle programmi ng environments manual ( vlepem) for more information about the vle extension. the processor integrates a pair of integer execution units, a branch control unit, instruction fetch unit and load/store unit, and a multi-ported re gister file capable of sustaining si x read and three wr ite operations per clock cycle. most integer instructions execute in a single clock cycle. branch target prefetching is performed by the branch unit to allow single-cycle branches in many cases. throughout the remainder of this document, the core is referred to as the ?e200z4d? when speaking of e200z4d-specific implementations, the ?e200z4xx? when speaking of a specific variety of e200z4 core, or ?e200? when referring to the whole e200 family. figure 15-1 shows the block diagram for the device. figure 15-1. e200z4d block diagram 15.2 features key features of the e200z4d ar e summarized as follows: ? dual-issue, 32-bit power isa-compliant core ? implementation of the vle cate gory for reduced code footprint ? in-order execution and retirement instruction bus interface unit software-managed instruction memory unit mas registers 32 gprs (64-bit) xer cr 1-, 4-, 16-, 64-, 256 kb, 1-, 4-, 16-, 64-, 256 mb, 1-, 4 gb page sizes execution units additional load/store write-back stage tw o / fo u r instructions 32 64 n address data control additional features ? once/nexus 1/nexus 3 control logic ? dual ahb 2.v6 buses ? spe (simd) ? embedded scalar/ vector floating-point ? power management ?time base/decrementer counter + l1 unified mmu unit ctr lr two-instruction, in-order dispatch two-instruction, in -order write-back ? ? ? 16-entry fully associative tlb ea calc tw o - s t a g e , single-path execute pipeline with overlapped execution and fetch unit branch processing unit instruction/control unit instruction buffer (8/16 instructions) decode 8-entry branch stage + ea calc one-stage fetch program counter target buffer data bus interface unit execute stage feed forwarding 32 64 n address data control sprs 2- or 4-way set-associative 4-kbyte instruction cache executes all e200z4d instructions (including power isa base, spe, and vle categories). as many as two instructions can execute simultaneously.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 15-3 preliminary?subject to change without notice ? precise exception handling ? branch processing unit (bpu) ? dedicated branch address calculation adder ? branch target prefetching using an 8-entry branch target buffer (btb) ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory by means of independent instruction and data bus interface units. ? load/store unit ? 64-bit general-purpose register file ? dual advanced high-performanc e (ahb) 2.v6 64-bit system buses ? memory management unit (mmu) with 16-entry fu lly associative tlb and multiple page-size support ? 4 kb, 2/4-way set-associative instruction cache ? signal processing extension uni t, version 1.1 supporting simd fi xed-point operations using the 64-bit general-purpose register file ? embedded floating-point (fpu) unit, vers ion 2 supporting scalar and vector simd single-precision floating-point operations using the 64-bit ge neral-purpose register file ? nexus class 3+ real -time development unit ? power management ? low power design?extensive clock gating ? dedicated power saving state: wait ? dynamic power management of execution units, cache, and mmu see the following sections for more details about specific units. 15.2.1 execution unit features the following subsections describes the execution units? main features. 15.2.1.1 instructi on unit features the instruction unit feat ures the following: ? 64-bit path to cache supports fetching of two 32-bit power isa instructions or four 16-bit vle instructions per clock cycle. ? instruction buffer holds up to eight 32-bit po wer isa instructions or sixteen 16-bit vle instructions. ? dedicated program counter (pc) increm enter supports instruction prefetches. ? branch unit with dedicated branch address adde r and branch target buffer supports single-cycle execution of successfully predicted branches.
pxd20 microcontroller reference manual, rev. 1 15-4 freescale semiconductor preliminary?subject to change without notice 15.2.1.2 integer unit features the integer units feature support fo r single-cycle execution of most integer instructions, as follows: ? 32-bit au for arithmetic and comparison operations ? 32-bit lu for logical operations ? 32-bit priority encoder fo r count-leading-zeros function ? 32-bit single-cycle barrel shifte r for static shifts and rotates ? 32-bit mask unit for data masking and insertion ? divider logic for signed and unsigned divide in ? 14 clock cycles with mi nimized execution timing (integer unit 1 only) ? pipelined 32 ? 32 hardware multiplier array supports 32 ? 32 ? 32 multiply with 2 clock latency, 1 clock throughput 15.2.1.3 load/store unit features the load/store unit supports load, store, and load mu ltiple/store multiple instructions by means of the following: ? 32-bit effective address adder for data memory addr ess calculations ? pipelined operation supports throughput of one load or store operation per cycle ? dedicated 64-bit interface to me mory supports saving and restoring of up to two regi sters per cycle for load multiple and store multiple word instructions ? two-cycle load latency ? big- and little-endian support ? misaligned access support 15.2.2 l1 cache features the l1 cache features the following: ? 4 kb, 2- or 4-way configurable set-associative instruction cache ? 64-bit data, 32-bit address bus plus attributes and control ? 32-byte line size ? cache line locking ? way allocation ? tag and data parity or multi-bit edc protec tion with correction/auto-invalidation capability ? virtually indexed, physically tagged ? pseudo round-robin repl acement algorithm ? line-fill buffer ? hit under fill
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 15-5 preliminary?subject to change without notice 15.2.3 memory management unit features the memory management unit features the following: ? virtual memory support ? 32-bit virtual and physical addresses ? 8-bit process identifier ? 16-entry fully associative tlb ? hardware assist for tlb miss exceptions ? per-entry multiple page size support from 1 kbyte to 4 gbyte ? entry flush protection ? software managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions ? freescale eis mmu architecture compliant ? support for external control of en try matching for a subset of ti d values to support non-intrusive runtime mapping modifications 15.2.4 system bus (core comp lex interface) features the core complex interface features the following: ? independent instruction and data buses ? advanced microcontroller bus arch itecture (amba) ahb 2.v6 protocol ? 32-bit address bus, 64-bit data bus , plus attributes and control ? separate unidirectional 64-bit read and write data buses ? support for hclk running at a slower rate than cpu clock 15.2.5 nexus 3+ features the nexus 3+ module provide s real-time development ca pabilities for e200z4d pro cessors in compliance with the ieee-isto 5001?-2008 standard. the ?3+? suff ix indicates that some nexus class 4 features are available. a portion of the pin in terface (the jtag port) is also sh ared with the once/nexus 1 unit. the following features are implemented: ? program trace by means of branch trace messaging. ? branch trace messaging displays program flow di scontinuities (direct a nd indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. thus, stat ic code may be traced. ? data trace by means of data write messaging and data read messaging. ? provides the capability for the de velopment tool to trace reads and/ or writes to selected internal memory resources. ? ownership trace by means of ow nership trace messaging (otm).
pxd20 microcontroller reference manual, rev. 1 15-6 freescale semiconductor preliminary?subject to change without notice ? otm facilitates ownership trace by providing vi sibility of which pr ocess id or operating system task is activated.an owne rship trace message is transmitte d when a new process/task is activated, allowing the developmen t tool to trace ownership flow. ? allows enhanced download/upload capabilities. ? data acquisition messaging ? allows code to be instrumented to export cust omized information to the nexus auxiliary output port. ? watchpoint messaging by means of the auxiliary interface ? watchpoint trigger enable of pr ogram and/or data trace messaging ? run-time access to the processor memo ry map by means of the jtag port all features are controllable and conf igurable by means of the jtag port. 15.3 programming model this section describes the register model, instruction model, and the in terrupt model as they are defined by the power isa, freescale eis, and the e200z4d implementation. 15.3.1 register set figure 15-2 and figure 15-3 show the complete e200z4d re gister set, including the se ts of the registers that are accessible in supervisor mode and the set of regist ers that are accessible in user mode. the number to the right of the special-purpose regi sters (sprs) is the decimal number us ed in the instruction syntax to access the register. for example, the inte ger exception register (xer) is spr 1. figure 15-2 shows the registers that can be accessed by supervisor-level soft ware. user-level software can access only those registers listed in figure 15-3 .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 15-7 preliminary?subject to change without notice figure 15-2. e200z4d supervisor mode programmer?s model esr spr 62 exception syndrome data exception address spr general exception handling/control registers save and restore mmu assist memory management registers machine state msr pvr processor control registers decrementer timers time base (writeonly) mas0 mas1 mas2 mas3 mas4 mas6 spr 624 spr 625 spr 626 spr 627 spr 628 spr 630 sprg0 sprg1 sprg2 sprg3 sprg4 sprg5 sprg6 sprg7 sprg8 sprg9 spr 272 spr 273 spr 274 spr 275 spr 276 spr 277 spr 278 spr 279 spr 604 spr 605 dear spr 61 spr 26 spr 27 spr 58 spr 59 spr 574 spr 575 spr 570 spr 571 tbl spr 284 tbu spr 285 dec spr 22 process id pid0 spr 48 processor id pir spr 286 decar spr 54 ivor0 ivor1 ivor15 spr 400 spr 401 spr 415 interrupt vector prefix ivpr spr 63 interrupt vector offset control and status tcr spr 340 tsr spr 336 spr 528 spr 530 ivor32 2 ivor34 2 processor version control & configuration spr 1012 spr 1015 spr 688 spr 689 hardware implementation dependent 1 hid0 hid1 spr 1008 spr 1009 mmucsr0 mmucfg tlb0cfg tlb1cfg spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 gpr31 spr 1 xer xer general registers spr 256 user spr usprg0 sp e status and control spr 512 spefscr spe register spr 287 system version 2 svr spr 1023 machine check syndrome register mcsr spr 572 btb control 1 spr 1013 bucsr btb register srr0 srr1 csrr0 csrr1 dsrr0 2 dsrr1 2 mcsrr0 2 mcsrr1 2 machine check address register mcar spr 573 accumulator acc cache control spr 1011 l1csr1 cache registers spr 515 cache configuration (read-only) l1cfg0 spr 959 l1finv1 spr 516 l1cfg1 iac1 iac2 iac3 iac4 iac5 iac6 iac7 iac8 debug registers 2 debug control dbcr0 dbcr1 dbcr2 dbcr3 1 dbcr4 1 dbcr5 1 dbcr6 1 dberc0 1 spr 308 spr 309 spr 310 spr 561 spr 563 spr 564 spr 603 spr 569 instruction address compare spr 312 spr 313 spr 314 spr 315 spr 565 spr 566 spr 567 spr 568 data address compare dac1 dac2 spr 316 spr 317 debug status dbsr spr 304 debug counter 1 dbcnt spr 562 data value compare (64-bit) dvc1 dvc2 spr 318 spr 319 1 - these e200-specific registers may not be supported by other processors built on power architecture technology 2 - optional registers defined by the power isa embedded architecture cache access registers cdacntl cdadata dcr 351 dcr 350 psu registers pscr pssr pshr pslr dcr 272 dcr 273 dcr 274 dcr 275 device control registers (dcrs) 1 psctr psuhr psulr dcr 276 dcr 277 dcr 278
pxd20 microcontroller reference manual, rev. 1 15-8 freescale semiconductor preliminary?subject to change without notice figure 15-3 shows the user-mode special-purpose registers. figure 15-3. e200z4d user mode programmer?s model sprs the gprs are accessed through instru ction operands. access to other regi sters can be explicit, by using instructions for that purpose such as the move to special -purpose register ( mtspr ) and move from special-purpose register ( mfspr ) instructions. access to ot her registers can also be implicit, as part of the execution of an instruction. some registers are accessed both explic itly and implicitly. 15.3.2 instruction set the e200z4d supports the power is a instruction set for 32-bit embedded implementations. this is composed primarily of the user-level instructions defined by the user instruction set architecture (uisa). the e200z4d does not include the power isa floating-po int, load string, or stor e string instructions. the e200z4d core implements the fo llowing architectur al extensions: ? the vle category ? the integer select category (isel) ? enhanced debug and the debug notif y halt instruction categories ? the machine check category ? the wait category ? the volatile context save/restore category ? the embedded floating- point unit, version 2 ? the signal processing extension unit, version 1.1 ? the cache line locking category ? the enhanced reservations category timers (read only) time base spr 515 cache configuration l1cfg0 tbl spr 268 tbu spr 269 cache register (read-only) spr 9 general-purpose registers count register ctr spr 8 link lr condition register cr spr 1 xer xer general registers spr general (read-only) control registers sprg4 sprg5 sprg6 sprg7 spr 260 spr 261 spr 262 spr 263 spr 256 user spr usprg0 spe status and control register spr 512 spefscr category registers gpr0 gpr1 ? ? gpr31 accumulator acc spr 516 l1cfg1 ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 15-9 preliminary?subject to change without notice 15.3.3 interrupts and exception handling the e200z4d core supports an extended exception handl ing model with nested interrupt capability and extensive interrupt vector programmabi lity. in general, interrupt processi ng begins with an exception that occurs due to external conditions, errors, or program execution problems. when an exception occurs, the processor checks whether interrupt processing is enabled for that pa rticular exception. if enabled, the interrupt causes the state of the processor to be save d in the appropriate registers and begins execution of the handler located at the associated vect or address for that particular exception. once the handler is executing, the implementation may need to check bits in the exception syndrome register (esr), the machine check syndrome register (mcsr), or the signal processing and embedded floating-point status and control regi ster (spefscr) to verify the specific cause of the exception and take appropriate action. the core complex supports the interrupts described in table 15-1. table 15-1. interrupt registers register description noncritical interrupt registers srr0 save/restore register 0?on noncritical interrupts , stores either the address of the instruction causing the exception or the address of the in struction that executes after the rfi instruction. srr1 save/restore register 1?saves machine state on noncritical interrupts and restores machine state after an rfi instruction is executed. critical interrupt registers csrr0 critical save/restore register 0?on critical in terrupts, stores either the address of the instruction causing the exception or the address of the instruction that executes after the rfci instruction. csrr1 critical save/restore register 1?saves machine state on critical interrupts and restores machine state after an rfci instruction is executed. debug interrupt registers dsrr0 debug save/restore register 0?on debug interr upts, stores either the address of the instruction causing the exception or the address of the instruction that executes after the rfdi instruction. dsrr1 debug save/restore register 1?saves machine st ate on debug interrupts and restores machine state after an rfdi instruction is executed. machine check interrupts mcsrr0 machine check save/restore register 0?on mach ine check interrupts, stores either the address of the instruction causing the exception or the address of the instruction that executes after the rfmci instruction. mcsrr1 machine check save/restore register 1?saves machine state on machine check interrupts and restores those values when an rfmci instruction is executed syndrome registers mcsr machine check syndrome register?saves machine check syndrome information on machine check interrupts.
pxd20 microcontroller reference manual, rev. 1 15-10 freescale semiconductor preliminary?subject to change without notice each interrupt has an associated interrupt vector address, obtained by concatenating iv pr[32?47] with the address index in the associated ivor (that is, ivpr[32?47] || ivor n [48?59] || 0b0000). the resulting address is that of the instruction to be executed wh en that interrupt occurs. ivpr and ivor values are indeterminate on reset and must be ini tialized by the system software using mtspr . table 15-2 lists ivor registers implemented on th e e200z4d and the associated interrupts. esr exception syndrome register?provides a syndrome to differentiate among the different kinds of exceptions that generate the same interrupt type. upon generation of a specific exception type, the associated bits are set and all other bits are cleared. spe interrupt registers spefscr signal processing and embedded floating-point stat us and control register?provides interrupt control and status as well as various co ndition bits associated with the ope rations performed by the spe. see ta b l e 1 5 - 2 for a list of the associated ivors. other interrupt registers dear data exception address register?contains the addre ss that was referenced by a load, store, or cache management instruction t hat caused an alignment, data tl b miss, or data storage interrupt. ivpr ivors together, ivpr[32?47] || ivor n [48?59] || 0b0000 define the address of an interrupt-processing routine. see ta b l e 1 5 - 2 for more information. msr machine state register?defines th e state of the processor. when an interrupt occurs, it is updated to preclude unrecoverable interrupts from occurring duri ng the initial portion of the interrupt handler table 15-2. exceptions and conditions ivor n interrupt type ivor n interrupt type none 1 1 vector to [ p_rstbase[0:29] ]||0xffc. system reset (not an interrupt) 9 ap unavailable (not used by this core) 0 2 2 the cpu supports external vector override options on these ivors when they are provided on the device. for example an intc module may provide a separate vector for each of its sources when in hardware mode. critical input 10 decrementer 1 machine check 11 fixed-interval timer machine check (non-maskable interrupt) 12 watchdog timer 2 data storage 13 data tlb error 3 instruction storage 14 instruction tlb error 4 2 external input 15 debug 5 alignment 16?31 reserved 6 program 32 spe unavailable 7 floating-point unavailable 33 spe data exception 8 system call 34 spe round exception table 15-1. interrupt registers (continued) register description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 15-11 preliminary?subject to change without notice 15.4 microarchitecture summary the e200z4d processor utilizes a five-s tage pipeline for instruction exec ution. these stages operate in an overlapped fashion, allowing single clock-cycle instruction execution for most instructions. the stages are as follows: 1. instruction fetch 2. instruction decode/register file read/effective address calculation 3. execute 0/memory access 0 4. execute 1/memory access 1 5. register write-back the integer execution units consist of a 32-bit arithmetic unit, a logic unit, a 32-bit barrel shifter, a mask-insertion unit, a condition register manipulation unit, a count-leading-zer os unit, a 32 ? 32 hardware multiplier array, and result feed-forward hardwa re. integer unit 1 also s upports hardware division. most arithmetic and logical operations are executed in a single cycle with the exce ption of multiply, which is implemented with a 2-cycle pipeli ned hardware array, and the divide instructions. a c ount-leading-zeros unit operates in a single clock cycle. the instruction unit contains a pr ogram counter incrementer and dedi cated branch address adder to minimize delays during change-of-flow operations. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching using the btb is performed to accelerate taken branches. prefetched instructions are placed into an 8-en try instruction buffer, with each entry capable of holding a single 32-bit instru ction or a pair of 16-bit instructions. branch target addresses are calculat ed in parallel with branch inst ruction decode. c onditional branches that are not taken execute in a single clock cycle. br anches with successful bt b target prefetching have an effective execution time of one clock cycle if correctly predicted. all other taken branches have an execution time of two clock cycles. memory load and store operations are provided for byte, ha lf-word, word (32-bit) , and double-word data with automatic zero or sign extensi on of byte and half-word load data as well as optional byte reversal of data. these instructions can be pipelined to allow effective single-cycle throughput. load and store multiple word instructions allow low-overhead cont ext save and restore operations. the load/store unit contains a dedicated effective addr ess adder to allow effective addre ss generation to be optimized. there is a single load-to-use bubble for load instructions. the condition register unit supports the condition regist er (cr) and condition regi ster operations defined by the architecture. the conditio n register consists of eight 4-bit fiel ds that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions. it also provides a mechanism for testing and branching. vectored and autovectored interrupt s are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt sources to have unique in terrupt handlers invoked with no software overhead. the spe or spe2 category supports vector instructions operating on 8- , 16-, and 32-bit fixed-point data types, as well as 32-bit ieee std. 754? single- precision floating-point formats. it supports single-precision floating- point operations in a pipelined fashion.
pxd20 microcontroller reference manual, rev. 1 15-12 freescale semiconductor preliminary?subject to change without notice the 64-bit general-purpose register fi le is used for source and destinat ion operands, and there is a unified storage model for single-precision fl oating-point data types of 32-bits and the normal integer type. low latency fixed-point and floating- point add, subtract, multiply, mu ltiply-add, multiply-sub, divide, compare, and conversion opera tions are provided. most ope rations can be pipelined. 15.5 availability of detailed documentation detailed documentation of the e200z4d core will be pr ovided in a separate core reference manual (crm). when the crm is available, a link to it will be added to it in this document.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-1 preliminary?subject to change without notice chapter 16 enhanced direct memory access (edma) 16.1 introduction the dma (direct memory access) is a second-generation platform module capable of performing complex data transfers with minimal intervention from a host processor via 16 programmable channels. intended for use as part of the st andard product platform (spp), the ha rdware microarchitecture includes a dma engine which performs source and destination address calculati ons, and the actual data movement operations, along with a loca l memory containing the transfer control descriptors (tcd) for the channels. this sram-based implementation is used to minimize the overall module size. figure 16-1 is a block diagram of the dma module. figure 16-1. dma block diagram j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba ahb ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] bus 64 dma_ipd_done[n-1:0]
pxd20 microcontroller reference manual, rev. 1 16-2 freescale semiconductor preliminary?subject to change without notice 16.1.1 overview the dma is a highly-programmable da ta transfer engine, which has been optimized to minimize the required intervention from the host pro cessor. it is intended for use in a pplications where the data size to be transferred is st atically known, and is not defined within the data pack et itself. the dma hardware supports: ? single design supporting 16- channel implementation ? connections to the amba-ahb crossbar switch for bus mastering the da ta movement, slave bus for programming the module ? parameterized support for 32- and 64-bit amba-ahb datapath widths ? 32-byte transfer control descriptor per channel stored in local memory ? 32 bytes of data registers, used as te mporary storage to support burst transfers throughout this document, n is used to reference the channel numbe r. additionally, data sizes are defined as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit). 16.1.2 features the dma module supports the following features: ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source, destinat ion addresses, transfer size, plus support for enhanced addressing modes ? transfer control descriptor organized to support two-deep, nested transfer operations ?an inner data transfer loop defined by a ?minor? byte transfer count ?an outer data transfer loop define d by a ?major? iteration count ? channel service request via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for c ontinuous transfers ? independent channel linking at e nd of minor loop and/or major loop ? peripheral-paced hardware requests (one per channel) ? for all three methods, one service request per execution of the minor loop is required ? support for fixed-priority and round-robin channel arbitration ? channel completion reported vi a optional interrupt requests ? one interrupt per channel, optionally asse rted at completion of major iteration count ? error terminations are optionally enabled per ch annel, and logically summed together to form a small number of error interrupt outputs ? support for scatter/ga ther dma processing ? support for complex data structures ? support to cancel transfers via software or hardware
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-3 preliminary?subject to change without notice 16.2 memory map/register definition the dma?s programming model is pa rtitioned into two sections, both mapped into the slave bus space: the first region defines a number of registers providing control f unctions, while the second region corresponds to the local transfer control descriptor memory. reading an unimplemented register bit or memory location will return the value of zero. write the value of zero to unimplemented register bits. any access to a reserved memory location will result in a bus error. reserved memory locations are indicated in the memory map. for 16-channel implementation, reserved memory also includes the high order "h" register s containing channels 63-32 data (i.e., dmaerqh, dmaeeih, dmainth, dmaerrh). many of the control registers have a bit width that matches the number of channels implemented in the module, i.e., 16-, 32- or 64-bits in size. for 16-channel designs, the unused bits are not im plemented: reads return zeroes, and writes are ignored. the dma module does not include any logic which pr ovides access control. rather, this function is supported using the standard access control logic provided by the pbridge controller. table 16-1 is a 32-bit view of the dma?s memory map. table 16-1. dma 32-bit memory map dma offset register 0x0000 dma control register (dmacr) 0x0004 dma error status (dmaes) 0x0008 dma enable request high (dmaerqh, channels 63-32) 0x000c dma enable request low (dmaerql, channels 31-00) 0x0010 dma enable error interrupt high (dmaeeih, channels 63-32) 0x0014 dma enable error interrupt low (dmaeeil, channels 31-00) 0x0018 dma set enable request (dmaserq) dma clear enable request (dmacerq) dma set enable error interrupt (dmaseei) dma clear enable error interrupt (dmaceei) 0x001c dma clear interrupt request (dmacint) dma clear error (dmacerr) dma set start bit (dmassrt) dma clear done status bit (dmacdne) 0x0020 dma interrupt request high (dmainth, channels 63-32) 0x0024 dma interrupt request low (dmaintl, channels 31-00) 0x0028 dma error high (dmaerrh, channels 63-32) 0x002c dma error low (dmaerrl, channels 31-00) 0x0030 dma hardware request status high (dmahrsh, channels 63-32) 0x0034 dma hardware request status low (dmahrsl, channels 31-00) 0x0038 reserved 0x003c? 0x00fc reserved 0x0100 dma channel 0 priority (dchpri0) dma channel 1 priority (dchpri1) dma channel 2 priority (dchpri2) dma channel 3 priority (dchpri3) 0x0104 dma channel 4 priority (dchpri4) dma channel 5 priority (dchpri5) dma channel 6 priority (dchpri6) dma channel 7 priority (dchpri7)
pxd20 microcontroller reference manual, rev. 1 16-4 freescale semiconductor preliminary?subject to change without notice 16.2.1 register descriptions 16.2.1.1 dma control register (dmacr) the 32-bit dmacr defines the basic ope rating configuratio n of the dma. the dma arbitrates channel service requests in groups of 16 channels. arbitration within a group can be conf igured to use either a fixed-prio rity or a round-robin selection. in fixed-priority arbitration, the highest priority cha nnel requesting service is selected to execute. the priorities are assigne d by the channel priority registers (see section 16.2.1.16, dma channel n priority (dchprin), n = 0,..., {15} ). in round-robin arbitration mode, the channel priorities are ignored and the channels within each group are cycled through without regard to priority. the group priorities operate in a si milar fashion. in group fi xed-priority arbitrati on mode, channel service requests in the highest priority group are executed firs t where priority level 3 is the highest and priority level 0 is the lowest. the group prio rities are assigned in the grpnpri re gisters. all group priorities must have unique values prior to any channel service reque sts occur, otherwise a conf iguration error will be reported. unused group priority regi sters, per configuration, are unimp lemented in the dmacr. in group round-robin mode, the group prioriti es are ignored and the groups are cycled through without regard to priority. 0x0108 dma channel 8 priority (dchpri8) dma channel 9 priority (dchpri9) dma channel 10 priority (dchpri10) dma channel 11 priority (dchpri11) 0x010c dma channel 12 priority (dchpri12) dma channel 13 priority (dchpri13) dma channel 14 priority (dchpri14) dma channel 15 priority (dchpri15) 0x0110 reserved 0x0114 reserved 0x0118 reserved 0x011c reserved 0x0120 reserved 0x0124 reserved 0x0128 reserved 0x012c reserved 0x0130 reserved 0x0134 reserved 0x0138 reserved 0x013c reserved 0x0140-0x0ffc reserved 0x1000-0x11fc tcd00-tcd15 0x1200-0x13fc tcd16-tcd31 0x1400-0x15fc tcd32-tcd47 0x1600-0x17fc tcd48-tcd63 table 16-1. dma 32-bit memory map (continued) dma offset register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-5 preliminary?subject to change without notice minor loop offsets are address offset values added to the fina l source address (saddr) or destination address (daddr) upon minor loop completion. wh en minor loop offsets are enable d, the minor loop offset (mloff) is added to the final source address (saddr), or the final destination address (da ddr), or both prior to the addresses being written back into the tcd. if the ma jor loop is complete, the minor loop offset is ignored and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr values. when minor loop mapping is enabled (dmacr[emlm] = 1), tcdn word2 is redefined. a portion of tcdn word2 is used to specify multiple fields: an sour ce enable bit (smloe) to sp ecify the minor loop offset should be applied to the source a ddress (saddr) upon minor loop comple tion, an destination enable bit (dmloe) to specify the minor loop offset should be applied to the destinatio n address (daddr) upon minor loop completion, and the sign extended mi nor loop offset value (mloff). the same offset value (mloff) is used for both source and des tination minor loop offsets. when either minor loop offset is enabled (smloe set or dmloe set), the nbytes field is redu ced to 10 bits. when both minor l oop offsets are disabled (smloe cleared and dmloe cleared), the nbytes field is a 30-bit vector. when minor loop mapping is disabled (dmacr[emlm] = 0), all 32 bits of tcdn word2 are assigned to the nbytes field. see section 16.2.1.17, transfer co ntrol descriptor (tcd), for more details. see figure 16-2 and table 16-2 for the dmacr definition. figure 16-2. dma control register (dmacr) register address: dma_offset + 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cx ecx w reset: 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r grp3pri grp2pri grp1pri grp0pri eml m clm halt hoe erg a erc a edb g ebw w reset: 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 = unimplemented table 16-2. dma control regist er (dmacr) field descriptions name description value cx cancel transfer 0 normal operation. 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the cxfr bit clears itself after the ca ncel has been honored. this cancel retires the channel normally as if the minor loop was completed.
pxd20 microcontroller reference manual, rev. 1 16-6 freescale semiconductor preliminary?subject to change without notice ecx error cancel transfer 0 normal operation. 1 cancel the remaining data transfer in the same fashion as the cx cancel transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the ecx bit clears itself after the cancel has been honored. in addition to cancelling the transfer, the ecx treats the cancel as an error condition; thus updating the dmaes register and generating an optional error interrupt (see section 16.2.1.2, dma error status (dmaes) ). grp3pri channel group 3 priority group 3 priority level when fixed priority group arbitration is enabled. grp2pri channel group 2 priority group 2 priority level when fixed priority group arbitration is enabled. grp1pri channel group 1 priority group 1 priority level when fixed priority group arbitration is enabled. grp0pri channel group 0 priority group 0 priority level when fixed priority group arbitration is enabled. emlm enable minor loop mapping 0 minor loop mapping disabled. tcdn.word2 is defined as a 32-bit nbytes field. 1 minor loop mapping enabled. when set, tcdn.word2 is redefined to include individual enable fields, an offset field and the nbytes field. the individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. the nbytes field is reduced when either offset is enabled. clm continuous link mode 0 a minor loop channel link made to itself will go through channel arbitration before being activated again. 1 a minor loop channel link made to itself will not go through channel arbitration before being activated again. upon minor loop completion the channel will active again if that channel has a minor loop channel link enabled and the link channel is itself. this effectively applies the minor loop offsets and restarts the next minor loop. halt halt dma operations 0 normal operation. 1 stall the start of any new channels. executing channels are allowed to complete. channel execution will resume when the halt bit is cleared. hoe halt on error 0 normal operation. 1 any error will cause the halt bit to be set. subsequently, all service requests will be ignored until the halt bit is cleared. erga enable round robin group arbitration 0 fi xed priority arbitration is used for selection among the groups. 1 round robin arbitration is used for selection among the groups. table 16-2. dma control regist er (dmacr) field descriptions name description value
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-7 preliminary?subject to change without notice 16.2.1.2 dma error status (dmaes) the dmaes register provides informat ion concerning the last recorded ch annel error. channel errors can be caused by a configuration error (an illegal setting in the transfer contro l descriptor or an illegal priority register setting in fixed arbitration mode) or an error terminati on to a bus master re ad or write cycle. a configuration error is caused when the starting source or destinati on address, source or destination offsets, minor loop byte count and th e transfer size represent an incons istent state. the addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destinat ion transfer sizes. all source read s and destination writes must be configured to the natural boundary of the programmed transfer size respect ively. in fixed arbitration mode, a configuration error is caused by any two channel priorities being equal within a group, or any group priority levels being equa l among the groups. all channel priority le vels within a group must be unique and all group priority levels among th e groups must be unique when fixe d arbitration mode is enabled. if a scatter/gather operation is enab led upon channel completion, a configur ation error is reported if the scatter/gather address (dlast_sga) is not aligned on a 32-byte boundary . if minor loop channel linking is enabled upon channel completion, a conf iguration error is reported when the link is attempted if the tcd.citer.e_link bit does not equal the tcd.biter.e_ link bit. all configurati on error conditions except scatter/gather and minor loop link error are reported as th e channel is activated and assert an error interrupt request, if enabled. a scatter/gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enable d. a minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. if a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. in this case, the state of the cha nnel?s transfer control desc riptor is updated by the dma engine with the current source addr ess, destination address and current iteration count at the point of the fault. when a system bus error occurs, the channel is terminated after the read or write transaction which is already pipelined after errant access, has complete d. if a bus error occurs on the last read prior to beginning the write sequence, the write will execute using the data cap tured during the bus error. if a bus erca enable round robin channel arbitration 0 fixed priority arbitration is used for channel selection within each group. 1 round robin arbitration is used for channel selection within each group. edbg enable debug 0 the assertion of the ipg_debug input is ignored. 1 the assertion of the ipg_debug input causes the dma to stall the start of a new channel. executing channels are allowed to complete. channel execution will resume when either the ipg_debug input is negated or the edbg bit is cleared. ebw enable buffered writes 0 the buffer able write signal (hprot[2]) is not asserted during amba ahb writes. 1 the bufferable write signal (hprot[2]) is asserted on all amba ahb writes except for the last write sequence. table 16-2. dma control regist er (dmacr) field descriptions name description value
pxd20 microcontroller reference manual, rev. 1 16-8 freescale semiconductor preliminary?subject to change without notice error occurs on the last write prior to switching to the next read sequenc e, the read seque nce will execute before the channel is terminated due to the destination bus error. a transfer may be cancelled by software via the dmacr[cx ] bit or hardware via the dma_cancel_xfer input signal. when a cancel transfer request is recognized, the dma engine stops pr ocessing the channel. the current read-write sequence is allowed to finish. if the cancel occurs on th e last read-write sequence of a major or minor loop, the ca ncel request is discarded and the channel retires normally. the error cancel transfer is the sa me as a cancel transfer except the dmaes register is updated with the cancelled channel number and error cancel bit is set. the tcd of a cancelled channel has the source address and destination address of the last transfer saved in the tcd. it is the responsibility of the user to initialize the tcd again should the channel need to be restarted because the aforementioned fields have been modified by the dma engine and no longer repres ent the original parameters. when a transfer is cancelled via the error cancel tr ansfer mechanism (setting the dmacr[ecx] or asserting the dma_err_cancel_xfer input), the channel number is loaded into the errchn field and the ecx and vld bits are set are set in the dmae s register. in addition, an error inte rrupt may be gene rated if enabled. see section 16.2.1.14, dma error (dmaerrh, dmaerrl) for error interrupt details. the occurrence of any type of error causes the dma engine to immediately stop, and the appropriate channel bit in the dma error register to be asserte d. at the same time, the details of the error condition are loaded into the dmaes register. the major loop complete indicators, sett ing the transfer control descriptor done flag and the possible a ssertion of an interrupt request, are not affected when an error is detected. see figure 16-3 and table 16-3 for the dmaes definition. figure 16-3. dma error status (dmaes) register register address: dma_offset + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vld 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ecx w reset: 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpe cpe errchn[0:5] sae soe dae doe nce sge sbe dbe w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented table 16-3. dma error status (dmaes) field descriptions name description value vld logical or of all dmaerrh and dmaerrl status bits. 0 no dmaerr bits are set. 1 at least one dmaerr bit is set indicating a valid error exists that has not been cleared. ecx transfer cancelled 0 no cancelled transfers. 1 the last recorded entry was a cancelled transfer via the error cancel transfer input.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-9 preliminary?subject to change without notice gpe group priority error 0 no group priority error. 1 the last recorded error was a configuration error among the group priorities. all group priorities are not unique. cpe channel priority error 0 no channel priority error. 1 the last recorded error was a configuration error in the channel priorities within a group. all channel priorities within a group are not unique. errchn[0:5] error channel number or cancelled channel number the channel number of the last recorded error (excluding gpe and cpe errors) or last recorded transfer that was error cancelled. sae source address error 0 no source address c onfiguration error. 1 the last recorded error was a configuration error detected in the tcd.saddr field. tcd.saddr is inconsistent with tcd.ssize. soe source offset error 0 no source offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.soff field. tcd.soff is inconsistent with tcd.ssize. dae destination address error 0 no destination address configuration error. 1 the last recorded error was a configuration error detected in the tcd.daddr field. tcd.daddr is inconsistent with tcd.dsize. doe destination offset error 0 no destination offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.doff field. tcd.doff is inconsistent with tcd.dsize. nce nbytes/citer configuration error 0 no nbytes/citer configuration error. 1 the last recorded error was a configuration error detected in the tcd.nbytes or tcd.citer fields. tcd.nbytes is not a multiple of tcd.ssize and tcd.dsize, or tcd.citer is equal to zero, or tcd.citer.e_link is not equal to tcd.biter.e_link. sge scatter/gather configuration error 0 no scatter/gather configuration error. 1 the last recorded error was a configuration error detected in the tcd.dlast_sga field. this field is checked at the beginning of a scatter/gather operation after major loop completion if tcd.e_sg is enabled. tcd.dlast_sga is not on a 32 byte boundary. sbe source bus error 0 no source bus error. 1 the last recorded error was a bus error on a source read. dbe destination bus error 0 no destination bus error. 1 the last recorded error was a bus error on a destination write. table 16-3. dma error status (dmaes) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 16-10 freescale semiconductor preliminary?subject to change without notice 16.2.1.3 dma enable request (dmaerqh, dmaerql) the dmaerq{h,l} registers provide a bit map for the implemented channels {16} to enable the request signal for each channel. dmaerq h supports channels 63-32, while dmaeqrl covers channels 31-00. the state of any given channel enable is directly affe cted by writes to this register; it is also affected by writes to the dmaserq and dmacerq registers. the dma{s,c}erq registers are provided so that the request enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the dmaerq{h,l} registers. both the dma request input signal and this enable re quest flag must be asse rted before a channel?s hardware service request is accepted. the st ate of the dma enable request flag does not affect a channel service request made explicitly through so ftware or a linked channel request. see figure 16-4 and table 16-4 for the dmaerq definition. figure 16-4. dma enable request (dmaerqh, dmaerql) registers as a given channel completes the processing of its majo r iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the dm aerq bit for that channel. if the tcd.d_req register address: dma_offset + 0x0008 (dmaerqh), +0x000c (dmaerql) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r erq 63 erq 62 erq 61 erq 60 erq 59 erq 58 erq 57 erq 56 erq 55 erq 54 erq 53 erq 52 erq 51 erq 50 erq 49 erq 48 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented table 16-4. dma enable request (dmaerqh, dmaerql) field descriptions name description value erqn, n = 0,... 15 enable dma request n 0 the dma request signal for channel n is disabled. 1 the dma request signal for channel n is enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-11 preliminary?subject to change without notice bit is set, then the corresponding dm aerq bit is cleared, disabling the dma request; else if the d_req bit is cleared, the state of the dmaerq bit is unaffected. 16.2.1.4 dma enable error in terrupt (dmaeeih, dmaeeil) the dmaeei{h,l} registers provide a bit map for th e implemented channels {16} to enable the error interrupt signal for each channel. dmaeeih supports channels 63-32, while dmaeeil covers channels 31-00. the state of any given ch annel?s error interrupt enable is directly affected by writes to this register; it is also affected by writes to the dmaseei and dmaceei register s. the dma{s,c}eei registers are provided so that the erro r interrupt enable for a single channel can easily be modi fied without the need to perform a read-modify-write sequenc e to the dmaeei{h,l} registers. both the dma error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. see figure 16-5 and table 16-5 for the dmaeei definition. figure 16-5. dma enable error interr upt (dmaeeih, dmaeeil) registers table 16-5. dma enable error interrupt (dmaeeih, dmaeeil) field descriptions register address: dma_offset + 0x0010 (dmaeeih), +0x0014 (dmaeeil) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r eei6 3 eei6 2 eei6 1 eei6 0 eei5 9 eei5 8 eei5 7 eei5 6 eei5 5 eei5 4 eei5 3 eei5 2 eei5 1 eei5 0 eei4 9 eei4 8 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value eein, n = 0,... 15 enable error interrupt n 0 the error signal for channel n does not generate an error interrupt. 1 the assertion of the error signal for channel n generate an error interrupt request.
pxd20 microcontroller reference manual, rev. 1 16-12 freescale semiconductor preliminary?subject to change without notice 16.2.1.5 dma set enable request (dmaserq) the dmaserq register provides a simple memory -mapped mechanism to set a given bit in the dmaerq{h,l} registers to enable the dma request fo r a given channel. the data value on a register write causes the corresponding bit in the dmaerq{h,l} register to be set. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global set function, forcing the entire contents of dmaerq{h,l} to be asse rted. if bit 7 is set, the command is ignored. this allows multiple byte registers to be writ ten as a 32-bit word. reads of this register return all zeroes. see figure 16-6 and table 16-6 for the dmaserq definition. figure 16-6. dma set enable request (dmaserq) register table 16-6. dma set enable request (dmaserq) field descriptions 16.2.1.6 dma clear enable request (dmacerq) the dmacerq register provides a simple memory-m apped mechanism to clea r a given bit in the dmaerq{h,l} registers to disable the dma request fo r a given channel. the data value on a register write causes the corresponding bit in the dmaerq{h,l} re gister to be cleared. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaerq{h,l} to be zeroed, disabli ng all dma request inputs. if bit 7 is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 16-7 and table 16-7 for the dmacerq definition. figure 16-7. dma clear enable request (dmacerq) register register address: dma_offset + 0x0018 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop serq[0:3] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 serq[0:3] set enable request 0-15 set the corresponding bit in dmaerq{h,l} 64-127 set all bits in dmaerq{h,l} register address: dma_offset + 0x0019 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cerq[0:6] reset: 0 0 0 0 0 0 0 = unimplemented
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-13 preliminary?subject to change without notice table 16-7. dma clear enable request (dmacerq) field descriptions 16.2.1.7 dma set enable er ror interrupt (dmaseei) the dmaseei register provides a simple memory -mapped mechanism to set a given bit in the dmaeei{h,l} registers to enable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the dmaeei{h,l} register to be set. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global set function, forcing the entire contents of dmaeei{h,l} to be asserted. if bit 7 is set, the command is ignor ed. this allows multiple byte registers to be writ ten as a 32-bit word. reads of this register return all zeroes. see figure 16-8 and table 16-8 for the dmaseei definition. figure 16-8. dma set enable er ror interrupt (dmaseei) register table 16-8. dma set enable error interrupt (dmaseei) field descriptions 16.2.1.8 dma clear enable error interrupt (dmaceei) the dmaceei register provides a simple memory-m apped mechanism to clear a given bit in the dmaeei{h,l} registers to disable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the dmaeei{h,l} register to be cleared. a data va lue of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaeei{h,l} to be zeroed, disabling all dma request inputs. if bit 7 is set, the command is ignored. this allows multi ple byte registers to be writ ten as a 32-bit word. reads of this register return all zeroes. see figure 16-9 and table 16-9 for the dmaceei definition. name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cerq[0:3] clear enable request 0-63 clear corresponding bit in dmaerq{h,l} 64-127 clear all bits in dmaerq{h,l} register address: dma_offset + 0x001a 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop seei[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 seei[0:6] set enable error interrupt 0-63 set the corresponding bit in dmaeei{h,l} 64-127 set all bits in dmaeei{h,l}
pxd20 microcontroller reference manual, rev. 1 16-14 freescale semiconductor preliminary?subject to change without notice figure 16-9. dma clear enable er ror interrupt (dmaceei) register table 16-9. dma clear enable error interrupt (dmaceei) field descriptions 16.2.1.9 dma clear interrupt request (dmacint) the dmacint register provides a simple memory-mapped mechanism to clear a given bit in the dmaint{h,l} registers to disable th e interrupt request for a given channel. the gi ven value on a register write causes the corresponding bit in the dmaint{h,l} register to be cleared. a da ta value of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaint{h,l} to be zeroed, disabling all dma interrupt requests. if bit 7 is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 16-10 and table 16-10 for the dmacint definition. figure 16-10. dma clear interrupt request (dmacint) fields table 16-10. dma clear interrupt request (dmacint) field descriptions 16.2.1.10 dma clear error (dmacerr) the dmaceer register provides a simple memory-mapped mechanism to clear a given bit in the dmaerr{h,l} registers to disable the error conditi on flag for a given channel. the given value on a register write causes the corresponding bit in the dmaerr{h,l} register to be cleared. a data value of 64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the register address: dma_offset + 0x001b 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop ceei[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 ceei[0:6] clear enable error in terrupt 0-63 clear corresponding bit in dmaeei{h,l} 64-127 clear all bits in dmaeei{h,l} register address: dma_offset + 0x001c 0 1 2 3 4 5 6 7 r 00000000 w nop cint[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cint[0:6] clear interrupt request 0-63 clear the corresponding bit in dmaint{h,l} 64-127 clear all bits in dmaint{h,l}
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-15 preliminary?subject to change without notice entire contents of the dmaerr{h,l} to be zeroed, clearing all ch annel error indicators. if bit 7 is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 16-11 and table 16-11 for the dmacerr definition. figure 16-11. dma clear error (dmacerr) register table 16-11. dma clear error (dmacerr) field descriptions 16.2.1.11 dma set start bit (dmassrt) the dmassrt register provides a simple memory-mapped mechanism to set the start bit in the tcd of the given channel. the data valu e on a register write causes the st art bit in the corresponding transfer control descriptor to be set. a data value of 64 to 127 (regardless of the numbe r of implemented channels) provides a global set func tion, forcing all start bits to be set. if bit 7 is set, the command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of th is register return all zeroes. see table 16-27 for the tcd start bit definition. figure 16-12. dma set star t bit (dmassrt) register table 16-12. dma set start bit (dmassrt) field descriptions 16.2.1.12 dma clear done status (dmacdne) the dmacdne register provides a s imple memory-mapped mechanism to clear the done bit in the tcd of the given channel. the data value on a regi ster write causes the done bit in the corresponding register address: dma_offset + 0x001d 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cerr[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cerr[0:6] clear error indicator 0-63 clear corresponding bit in dmaerr{h,l} 64-127 clear all bits in dmaerr{h,l} register address: dma_offset + 0x001e 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop ssrt[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 ssrt[0:6] set start bit (channel service request) 0-63 set the corresponding channel?s tcd.start 64-127 set all tcd.start bits
pxd20 microcontroller reference manual, rev. 1 16-16 freescale semiconductor preliminary?subject to change without notice transfer control descriptor to be cleared. a data value of 64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing al l done bits to be clea red. if bit 7 is set, the command is ignored. this allows multiple byte regi sters to be written as a 32-bit word. reads of this register return all zeroes. see table 16-27 for the tcd done bit definition. figure 16-13. dma clear done status (dmacdne) register table 16-13. dma clear done stat us (dmacdne) field descriptions 16.2.1.13 dma interrupt request (dmainth, dmaintl) the dmaint{h,l} registers provide a bit map for the implemented channels {16} signaling the presence of an interrupt request for each channel. dmainth supports channe ls 63-32, while dmaintl covers channels 31-00. the dma engine si gnals the occurrence of a program med interrupt upon the completion of a data transfer as defi ned in the transfer control descriptor by setting the appropr iate bit in this register. the outputs of this register are directly routed to the platform?s interrupt controller. during the execution of the interrupt service rout ine associated with any given channel, it is software?s responsibility to clear the appropriate bit, negating the in terrupt request. typically, a write to the dmacint register in the interrupt service routine is used for this purpose. the state of any given channel?s interr upt request is directly affected by wr ites to this register; it is also affected by writes to the dmacint register. on writ es to the dmaint, a one in any bit position clears the corresponding channel?s interrupt request. a zero in any bit position has no affect on the corresponding channel?s current interrupt status . the dmacint register is provided so the in terrupt request for a single channel can easily be cleared wi thout the need to perform a read-modify-write sequence to the dmaint{h,l} registers. see figure 16-14 and table 16-14 for the dmaint definition. register address: dma_offset + 0x001f 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cdne[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cdne[0:6] clear done status bit 0-63 clear the corresponding channel?s done bit 64-127 clear all tcd done bits
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-17 preliminary?subject to change without notice figure 16-14. dma interrupt request (dmainth, dmaintl) registers table 16-14. dma interrupt request (dmainth, dmaintl) field descriptions 16.2.1.14 dma error (dmaerrh, dmaerrl) the dmaerr{h,l} registers provide a bit map fo r the implemented channels {16} signaling the presence of an error for each channel. dmaerrh supports cha nnels 63-32, while dmaerl covers channels 31-00. the dma engine signals the occurrence of a error condition by se tting the appropriate bit in this register. the outputs of this register are en abled by the contents of the dmaeei register, then logically summed across groups of 16, 32 and 64 channels to form several group error interrupt requests which is then routed to the platform?s interrupt c ontroller. during the executi on of the interrupt service routine associated with any dma errors, it is software?s responsibilit y to clear the appropr iate bit, negating the error interrupt request. typically, a write to the dm acerr register in the interrupt service routine is used for this purpose. recall the normal dma channel completion indicators, setti ng the transfer control descriptor done flag and the possible a ssertion of an interrupt request, are not affected when an error is detected. the contents of this register can also be polled a nd a non-zero value indicates th e presence of a channel error, regardless of the state of th e dmaeei register. the state of any given channel?s error indicators is affected by writes to this register; it is also affected by writes to the dmacerr register. on writes to the register address: dma_offset + 0x0020 (dmainth), +0x0024 (dmaintl) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r int6 3 int6 2 int6 1 int6 0 int5 9 int5 8 int5 7 int5 6 int5 5 int5 4 int5 3 int5 2 int5 1 int5 0 int4 9 int4 8 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value intn, n = 0,... 15 dma interrupt request n 0 the interrupt request for channel n is cleared. 1 the interrupt request for channel n is active.
pxd20 microcontroller reference manual, rev. 1 16-18 freescale semiconductor preliminary?subject to change without notice dmaerr, a one in any bit position clears the corres ponding channel?s error status. a zero in any bit position has no affect on the corresponding channel?s current error status. the dmacerr register is provided so the error indicator for a single channel can easily be cleared. see figure 16-15 and table 16-15 for the dmaerr definition. figure 16-15. dma error (dmaerrh, dmaerrl) registers table 16-15. dma error (dmaerrh, dmaerrl) field descriptions 16.2.1.15 dma hardware request status (dmahrsh, dmahrsl) the dmahrs{h,l} registers provide a bit map for the implemented ch annels {16} to show the current hardware request status for each channel. dmahr sh supports channels 63- 32, while dmahrsl covers channels 31-00. hardware request status reflects the current state of the registered and qualified (via the dmaerq field) ipd_req lines as seen by the dma2?s arbitration logic. this view into the hardware request signals may be used for debug purposes. see figure 16-16 and figure 16-16 for the dmahrs definition. register address: dma_offset + 0x0028 (dmaerrh), +0x002c (dmaerrl) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r err 63 err 62 err 61 err 60 err 59 err 58 err 57 err 56 err 55 err 54 err 53 err 52 err 51 err 50 err 49 err 48 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value errn, n = 0,... 15 dma error n 0 an error in channel n has not occurred. 1 an error in channel n has occurred.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-19 preliminary?subject to change without notice figure 16-16. dma hardware request st atus (dmahrsh, dmahrsl) registers table 16-16. dma hardware request status (dmahrsh, dmahrsl) field descriptions 16.2.1.16 dma channel n priority (dchprin), n = 0,..., {15} when the fixed-priority channel ar bitration mode is enab led (dmacr[erca] = 0), th e contents of these registers define the unique priorities associated with each channel within a group. the channel priorities are evaluated by numeric value, i.e., 0 is the lowest pr iority, 1 is the next higher priority, then 2, 3, etc. software must program the channel priorities with unique values, otherwise a c onfiguration error will be reported. the range of the priority va lue is limited to the va lues of 0?15. when rea d, the grppri bits of the dchprin register reflect the cu rrent priority level of the group of channels in which the corresponding channel resides. grppri bits are not affected by write s to the dchprin registers. the group priority is assigned in the dmacr. see figure 16-2 and table 16-2 for the dmacr definition. register address: dma_offset + 0x0030 (dmahrsh), +0x0034 (dmahrsl) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hrs 63 hrs 62 hrs 61 hrs 60 hrs 59 hrs 58 hrs 57 hrs 56 hrs 55 hrs 54 hrs 53 hrs 52 hrs 51 hrs 50 hrs 49 hrs 48 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value hrsn, n = 0,... 15 dma hardware request status n 0 a hardware service request for channel n is not present. 1 a hardware service request for channel n is present. note: the hardware request status reflects the state of the request as seen by the arbitration logic. therefore, this status is affected by the dmaerqn bit.
pxd20 microcontroller reference manual, rev. 1 16-20 freescale semiconductor preliminary?subject to change without notice channel preemption is enabled on a per channel basi s by setting the ecp bit in the dchprin register. channel preemption allows the executin g channel?s data transfers to be temporarily suspended in favor of starting a higher priority channel. after the preempting channel has comp leted all of its minor loop data transfers, the preempted channel is restored and resumes execution. af ter the restored channel completes one read/write sequence, it is agai n eligible for preemption. if any hi gher priority channel is requesting service, the restored channel will be suspended and the higher priority channel will be serviced. nested preemption (attempting to preempt a preempting channel) is not su pported. after a preempting channel begins execution, it cannot be preempt ed. preemption is only available wh en fixed arbitration is selected for both group and channel arbitration modes. a channel?s ability to preempt a nother channel can be disabled by setting the dpa bit in the dchprin register. when a channel?s preempt ability is disa bled, that channel cannot suspend a lower priority channel?s data transfer; regardless of the lower priority channel?s ecp setting. this allo ws for a pool of low priority, large data moving channels to be define d. these low priority channe ls can be configured to not preempt each other, thus preven ting a low priority channel from c onsuming the preempt slot normally available a true, high priority channel. see figure 16-17 and table 16-17 for the dchprin definition. figure 16-17. dma channel n priority (dchprin) register table 16-17. dma channel n priority (dchprin) field descriptions 16.2.1.17 transfer control descriptor (tcd) each channel requires a 32-byte tr ansfer control descriptor for de fining the desired data movement operation. the tcd structure was prev iously discussed in detail in section 16.1.2, features. the channel descriptors are stored in the local memory in sequential order: ch annel 0, channel 1, ... channel [n-1]. the definitions of the tcd are pres ented as eight 32-bit values. table 16-18 is a 32-bit view of the basic tcd structure. register address: dma_offset + 0x100 + n 0 1 2 3 4 5 6 7 r ecp dpa grppri[0:1] chpri[0:3] w reset: 0 0 * * * * * * = unimplemented, * = defaults to channel number (n) after reset name description value ecp enable channel preemption 0 channel n cannot be suspended by a higher priority channel?s service request. 1 channel n can be temporarily suspended by the service request of a higher priority channel. dpa disable preempt ability 0 channel n can suspend a lower priority channel. 1 channel n cannot suspend any channel, regardless of channel priority. grppri[0:1] channel n current group priority gr oup priority assigned to this channel group when fixed-priority arbitration is enabled. these two bits are read only; writes are ignored. chpri[0:3] channel n arbitration priority channel priority when fixed-priority arbitration is enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-21 preliminary?subject to change without notice figure 16-18 and table 16-19 define word 0 of the tcdn structure, the saddr field. figure 16-18. tcdn word 0 (tcdn.saddr) field table 16-19. tcdn word 0 (tcdn.saddr) field description figure 16-19 and table 16-20 define word 1 of the tcdn structure, the soff and transfer attribute fields. table 16-18. tcdn 32-bit memory structure dma offset tcdn field 0x1000 + (32 x n) + 0x00 source address (saddr) 0x1000 + (32 x n) + 0x04 transfer attributes (smod, ssize, dmod, dsize) signed source address offset (soff) 0x1000 + (32 x n) + 0x08 signed minor loop offset (smloe, dmloe, mloff) inner ?minor? byte count (nbytes) 0x1000 + (32 x n) + 0x0c last source address adjustment (slast) 0x1000 + (32 x n) + 0x10 destination address (daddr) 0x1000 + (32 x n) + 0x14 current ?major? iteration co unt (citer) signed destinat ion address offset (doff) 0x1000 + (32 x n) + 0x18 last destination addre ss adjustment/scatter gath er address (dlast_sga) 0x1000 + (32 x n) + 0x1c beginning ?major? iteration count (biter) channel control/status (bwc, major.linkch, done, active, major.e_link, e_sg, d_req, int_half, int_maj, start) register address: dma_offset + 0x1000 + (32 x n) + 0x00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r saddr[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r saddr[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value saddr[[0:31] source address memory address pointing to the source data.
pxd20 microcontroller reference manual, rev. 1 16-22 freescale semiconductor preliminary?subject to change without notice figure 16-19. tcdn word 1 (tcdn.{soff,smod,ssize,dmod,dsize}) fields register address: dma_offset + 0x1000 + (32 x n) + 0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smod[0:4] ssize[0:2] dmod[0:4] dsize[0:2] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r soff[0:15] w reset: - - - - - - - - - - - - - - - - = unimplemented table 16-20. tcdn word 1 (tcdn.{smod,ssize,dmod,dsize,soff}) field descriptions name description value smod[0:4] source address modulo 0 sourc e address modulo feature is disabled. non-0 the value defines a specific address bit which is selected to be either the value after saddr + soff calculation is performed or the original register value. this feature provides the ability to easily implement a circular data queue. for data queues requiring power-of-2 ?size? bytes, the queue should be based at a 0-modulo-size address and the smod field set to the appropriate value to freeze the upper address bits. the bit select is defined as ((1 << smod[4:0]) - 1) where a resulting 1 in a bit location selects the next state address for the corresponding address bit location and a 0 selects the original register value for the corresponding address bit location. for this application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0-modulo-size range. ssize[0:2] source data transfer size 000 8-bit 001 16-bit 010 32-bit 011 64-bit 100 16-byte (32-bit ahb bus, wrap4 burst) 100 reserved (64-bit ahb bus, reserved) 101 32-byte (if supported by the platform) 110 reserved 111 reserved the attempted specification of a 64-bit source size in a 32-bit amba ahb bus implementation produces a configuration error. likewise, the attempted specification of a 16-byte source size in a 64-bit amba ahb bus implementation generates a configuration error. the attempted specification of a 32-byte burst on platforms that do not support such a transfer type will result in a configuration error.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-23 preliminary?subject to change without notice figure 16-20 and table 16-21 define word 2 of the tcdn structure, the nbytes field. figure 16-20. tcdn word 2 (tcdn.nbytes) field (dmacr[emlm] = 0) table 16-21. tcdn word 2 (tcdn.nbytes) field description when minor loop mapping (dmacr[emlm] = 1) is enab led, tcd word2 is redefi ned as four fields: a source minor loop offset enable, a destination minor loop offset enable, a minor loop offset field and a nbytes field. dmod[0:4] destination address modul o see the smod[5:0] definition. dsize[0:2] destination data transfer size see the ssize[2:0] definition. soff[16:31] source address signed offset sign-extended offset applied to the current source address to form the next-state value as each source read is completed. register address: dma_offset + 0x1000 + (32 x n) + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nbytes[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r nbytes[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value nbytes[0:31] inner ?minor? byte transfer count nu mber of bytes to be transferred in each service request of the channel. as a channel is activat ed, the contents of the appropriate tcd is loaded into the dma engine, and the appropriate reads and wr ites performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. after the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. the nbytes value 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gb transfer. table 16-20. tcdn word 1 (tcdn.{smod,ssize,dm od,dsize,soff}) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 16-24 freescale semiconductor preliminary?subject to change without notice figure 16-21. tcdn word 2 (tcdn.nbytes) field (dmacr[emlm] = 1) register address: dma_offset + 0x1000 + (32 x n) + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smlo e dmlo e mloff[0:13] or nbytes[0:13] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mloff[14:19] or nbytes[14:19] nbytes[20:29] w reset: - - - - - - - - - - - - - - - - = unimplemented table 16-22. tcdn word 2 (tcdn.nbytes) field descriptions name description value smloe source minor loop offset enable this flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 the minor loop offset is not applied to the saddr. 1 the minor loop offset is applied to the saddr. dmloe destination minor loop offset enable this flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 the minor loop offset is not applied to the daddr. 1 the minor loop offset is applied to the daddr. nbytes[0:19] or mloff[0:19] inner ?minor? byte transfer count or minor loop offset if both smloe and dmloe are cleared, this field is part of the byte transfer count. if either smloe or dmloe are set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is completed. nbytes[0:9] inner ?minor? byte transfer count numb er of bytes to be transferred in each service request of the channel. as a channel is activat ed, the contents of the appropriate tcd is loaded into the dma engine, and the appropriate reads and wr ites performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. this field is extended to 30 bits when both smloe and dmloe are cleared (disabled).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-25 preliminary?subject to change without notice figure 16-22 and table 16-23 define word 3 of the tcdn structure, the slast field. figure 16-22. tcdn word 3 (tcdn.slast) field table 16-23. tcdn word 3 (tcdn.slast) field descriptions figure 16-23 and table 16-24 define word 4 of the tcdn structure, the daddr field. figure 16-23. tcdn word 4 (tcdn.daddr) field table 16-24. tcdn word 4 (tcdn.daddr) field description figure 16-24 and table 16-25 define word 5 of the tcdn stru cture, the citer and doff fields. register address: dma_offset + 0x1000 + (32 x n) + 0x0c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r slast[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r slast[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value slast[0:31] last source address adjustment adjust ment value added to the source address at the completion of the outer major iteration count. this value can be applied to ?restore? the source address to the initial value, or adjust the address to reference the next data structure. register address: dma_offset + 0x1000 + (32 x n) + 0x10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r daddr[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r daddr[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value daddr[0:31] destination address memory addr ess pointing to the destination data.
pxd20 microcontroller reference manual, rev. 1 16-26 freescale semiconductor preliminary?subject to change without notice figure 16-24. tcdn word 5 (tcdn.{citer,doff}) fields register address: dma_offset + 0x1000 + (32 x n) + 0x14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r citer. e_link citer[0:5] or citer.linkch[0:5] citer[6:14] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r doff[0:15] w reset: - - - - - - - - - - - - - - - - = unimplemented table 16-25. tcdn word 5 (tcdn.{doff,citer}) field descriptions name description value citer.e_link enable channel-to-channel linking on minor loop complete as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[5:0]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bit of the specified channel. if channel linking is disabled, the citer value is extended to 15 bits in place of a link channel number. if the "major" loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. this bit must be equal to the biter.e_link bit otherwise a configuration error will be reported. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. citer[0:5] or citer.linkch[0:5] current ?major? iteration count or link channel number if (tcd.citer.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. tcd word 5, bits [30:25] are used to form a 15 bit citer field. else after the "minor" loop is exhausted, the dma engine initiates a channel service request at the channel defined by citer.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in citer.linkch[5:0] must not exceed the number of implemented channels.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-27 preliminary?subject to change without notice figure 16-25 and table 16-26 define word 6 of the tcdn structure, the dlast_sga field. figure 16-25. tcdn word 6 (tcdn.dlast_sga) field citer[6:14] current ?major? iterat ion count this 9 or 15-bit count represents the current major loop count for the channel. it is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. once the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the citer field from the beginning iteration count (biter) field. when the citer field is initially loaded by software, it must be set to the same value as that contained in the biter field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. doff[16:31] destination address signed offset sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. register address: dma_offset + 0x1000 + (32 x n) + 0x18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dlast_sga[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dlast_sga[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented table 16-25. tcdn word 5 (tcdn.{doff,citer}) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 16-28 freescale semiconductor preliminary?subject to change without notice table 16-26. tcdn word 6 (tcdn.dlast_sga) field description figure 16-26 and table 16-27 define word 7 of the tcdn structure, the biter and control/status fields. figure 16-26. tcdn word 7 (tcdn.{biter,control/status}) fields name description value dlast_sga[31:0 0:31] last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) if (tcd.e_sg = 0) then adjustment value added to the destination address at the completion of the outer major iteration count. this value can be applied to ?restore? the destination address to the initial value, or adjust the address to reference the next data structure. else this address points to the beginning of a 0-modulo-32 region containing the next transfer control descriptor to be loaded into this channel. this channel reload is performed as the major iteration count completes. the scatter/gather address must be 0-modulo-32, else a configuration error is reported. register address: dma_offset + 0x1000 + (32 x n) + 0x1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r biter[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bwc major.linkch[0:5] done active major. e_link e_sg d_req int_ha lf int_m aj start w reset: - - - - - - - - 0 0 - - - - - 0 = unimplemented table 16-27. tcdn word 7 (tcdn.{biter, control/status}) field descriptions name description value biter.e_link enable channel-to-channel linking on minor loop complete this is the initial value copied into the citer.e_link field when the major loop is completed. the citer.e_link field controls channel linking during channel execution. this bit must be equal to the citer.e_link bit otherwise a configuration error will be reported. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-29 preliminary?subject to change without notice biter[0:5] or biter.linkch[0:5] beginning ?major? iteration count or beginning link channel number this is the initial value copied into the citer field or citer.linkch field when the major loop is completed. the citer fields controls the iteration count and linking during channel execution. if (tcd.biter.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. tcd word 5, bits [30:25] are used to form a 15 bit biter field. else after the "minor" loop is exhausted, the dma engine initiates a channel service request at the channel defined by biter.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in biter.linkch[5:0] must not exceed the number of implemented channels. biter[6:14] beginning ?major? iteration count this is the initial value copied into the citer field or citer.linkch field when the major loop is completed. the citer fields controls the iteration count and linking during channel execution. this 9- or 15-bit count represents the beginning major loop count for the channel. as the major iteration count is exhausted, the contents of the entire 16-bit biter entry is reloaded into the 16-bit citer entry. when the biter field is initially loaded by software, it must be set to the same value as that contained in the citer field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. table 16-27. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 16-30 freescale semiconductor preliminary?subject to change without notice bwc[0:1] bandwidth control this two-bit fi eld provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the dma. in general, as the dma processes the inner minor loop, it continuously generates read/write, read/write, ... sequences until the minor count is exhausted. this field forces the dma to stall after the completion of each read/write access to control the bus request bandwidth seen by the platform?s cross-bar arbitration switch. to minimize start-up latency, bandwidth control stalls are suppressed for the first two ahb bus cycles a nd after the last write of each minor loop. the dynamic priority elevation setting elevates the priority of the dma as seen by the cross-bar arbitration switch for the executing channel. dynamic priority elevation is suppressed during the first two ahb bus cycles. 00 no dma engine stalls 01 dynamic priority elevation 10 dma engine stalls for 4 cycles after each r/w 11 dma engine stalls for 8 cycles after each r/w major.linkch[0:5] link channel number if (tcd.major.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the outer "major" loop counter is exhausted. else after the "major" loop counter is exhausted, the dma engine initiates a channel service request at the channel defined by major.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in major.linkch[5:0] must not exceed the number of implemented channels. done channel done this flag indicates the dma has completed the outer major loop. it is set by the dma engine as the citer count reaches zero; it is cleared by software, or the hardware when the channel is activated. this bit must be cleared in order to write the major.e_link or e_sg bits. active channel active this flag signals the channel is currently in execution. it is set when channel service begins, and is cleared by the dma engine as the inner minor loop completes or if any error condition is detected. table 16-27. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-31 preliminary?subject to change without notice major.e_link enable channel-to-channel linking on major loop complete as the channel completes the outer major loop, this flag enables the linking to another channel, defined by major.linkch[5:0]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bi t of the specified channel. to support the dynamic linking coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. e_sg enable scatter/gather processing as the channel completes the outer major loop, this flag enables scatter/gather processing in the current channel. if enabled, the dma engine uses dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. to support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the current channel?s tcd is ?normal? format. 1 the current channel?s tcd specifies a scatter gather format. the dlast_sga field provides a memory pointer to the next tcd to be loaded into this channel after the outer major loop completes its execution. d_req disable request if this flag is set, the dma hardware automatically clears the corresponding dmaerq bit when the current major iteration count reaches zero. 0 the channel?s dmaerq bit is not affected. 1 the channel?s dmaerq bit is cleared when the outer major loop is complete. int_half enable an interrupt when major counter is half complete if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the dmaint register when the current major iteration count reaches the halfway poi nt. specifically, the comparison performed by the dma engine is (citer == (biter >> 1)). this halfway point interrupt request is provided to support double-buffered schemes or other types of data movement where the processor needs an early indication of the transfer?s progress. 0 the half-point interrupt is disabled. 1 the half-point interrupt is enabled. note: if biter = 1, do not use int_half; use int_major instead. table 16-27. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 16-32 freescale semiconductor preliminary?subject to change without notice 16.3 functional description this section provides an overview of the microarchitecture and func tional operation of the dma module. 16.3.1 dma microarchitecture the dma module is partitioned into two major m odules: the dma engine and the transfer control descriptor local memory. additionall y, the dma engine is further partitioned into four submodules, which are detailed below. ? dma engine ? addr_path : this module implements registered vers ions of two channel transfer control descriptors: channel ?x? and channel ?y?, and is responsible for all the master bus address calculations. all the implemen ted channels provide the exact same functionality. this hardware structure allows the data transfers asso ciated with one channel to be preempted after the completion of a read/write sequence if a highe r priority channel service request is asserted while the first channel is active. once a channel is activated, it runs until the minor loop is completed unless preempted by a higher prio rity channel. this capability provides a mechanism (optionally enabled by dchprin[ecp ]) where a large data move operation can be preempted to minimize the time anothe r channel is blocke d from execution. when any other channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the regist ers of the other addr _path.channel_{x,y}. once the inner minor loop completes execut ion, the addr_path hardware wr ites the new values for the tcdn.{saddr, daddr, citer} back into the loca l memory. if the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the tcdn.citer field, a nd a possible fetch of the next tc dn from memory as part of a scatter/gather operation. ? data_path : this module implements the actual bus ma ster read/write datapath. it includes 32 bytes of register storage (match ing the maximum transfer size) and the necessary mux logic to support any required data alignm ent. the amba-ahb read data bus is the primary input, and int_maj enable an interrupt when major iteration count completes if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the dmaint register when the current major iteration count reaches zero. 0 the end-of-major loop interrupt is disabled. 1 the end-of-major loop interrupt is enabled. start channel start if this flag is set, the channel is requesting service. the dma hardware automatica lly clears this flag after the channel begins execution. 0 the channel is not explicitly started. 1 the channel is explicitly started via a software initiated service request. table 16-27. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-33 preliminary?subject to change without notice the ahb write data bus is the primary output. the addr_ and data_path modules directly support the 2-stage pipelined amba-ahb bus. the addr_path module represents the 1st stage of th e bus pipeline (the address phase), while the data_path module implements the 2nd stag e of the pipeline (the data phase). ? pmodel_charb : this module implements the first s ection of dma?s programming model as well as the channel arbitration logic. the pr ogramming model registers are connected to the ips bus (not shown). the ipd_req[n] inputs and dma_ipi_int[n] outputs are also connected to this module (via the control logic). ? control : this module provides all the control functi ons for the dma engine. for data transfers where the source and destination sizes are equal, the dma engine performs a series of source read, destination write ope rations until the number of bytes specified in the inner ?minor loop? byte count has been moved. for de scriptors where the sizes are not equal, multiple access of the smaller size data are required for each refere nce of the larger size. as an example, if the source size references 16-bit data and the des tination is 32-bit data, two reads are performed, then one 32-bit write. ? transfer_control_descriptor local memory ? memory controller : this logic implements the require d dual-ported controller, handling accesses from both the dma engine as well as references from the ips bus. as noted earlier, in the event of simultaneous acce sses, the dma engine is given pr iority and the ips transaction is stalled. the hooks to a bist controller for the local tcd memory are included in this module. ? memory array : the tcd is implemented using a single-ported, synchr onous compiled ram memory array 16.3.2 dma basic data flow the basic flow of a data transfer can be pa rtitioned into three se gments. as shown in figure 16-27 , the first segment involves the channel service request. in the diagram, this example uses the assertion of the ipd_req[n] signal to request service for channel n. channel service re quest via software and the tcdn.start bit follows the same basic flow as an ipd_req. the ipd_req[n] input signal is registered internally and then routed to through the dma engine, first through the control module, then into the programming model/channel arbitration (pmodel_char b) module. in the next cycle, th e channel arbitration is performed, either using the fixed-priority or round-robin algorithm. after the arb itration is complete, the activated channel number is sent through the a ddress path (addr_path) and convert ed into the required address to access the tcd local memory. next, the tcd memory is accessed and the required descriptor read from the local memory and loaded into the dma_engi ne.addr_path.channel_{x,y} regi sters. the tcd memory is organized 64-bits in width to mi nimize the time needed to fetch the activated channel?s descriptor and load it into the dma_engine .addr_path.channel_{x,y} registers.
pxd20 microcontroller reference manual, rev. 1 16-34 freescale semiconductor preliminary?subject to change without notice figure 16-27. dma operation, part 1 in the second part of the basic data flow as shown in figure 16-28 , the modules associated with the data transfer (addr_path, data_path a nd control) sequence through the requi red source reads and destination writes to perform the actual data movement. the source reads are in itiated and the fetched data is temporarily stored in the data_pa th module until it is gated on to the amba-ahb bus during the destination write. this source re ad/destination write pro cessing continues until th e inner minor byte count has been transferred. the dma_ipd_done[n ] signal is asserted at the end of the minor byte count transfer. j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] dma_ipd_done[n-1:0]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-35 preliminary?subject to change without notice figure 16-28. dma operation, part 2 once the inner minor byte count has been moved, the fina l phase of the basic data flow is performed. in this segment, the addr_path logic performs the required updates to ce rtain fields in the channel?s tcd, e.g., saddr, daddr, citer. if the outer ma jor iteration count is exhausted, th en there are additional operations which are performed. these in clude the final addr ess adjustments and reloading of the biter field into the citer. additionally, asserti on of an optional interrupt request occurs at this time, as doe s a possible fetch of a new tcd from memory using the s catter/gather address poi nter included in the descriptor. the updates to the tcd memory and the assertion of an interrupt request are shown in figure 16-29 . j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] dma_ipd_done[n-1:0]
pxd20 microcontroller reference manual, rev. 1 16-36 freescale semiconductor preliminary?subject to change without notice figure 16-29. dma operation, part 3 16.3.3 dma performance this section addresses the performance of the dma module, focusing on two sepa rate metrics. in the traditional data movement context, pe rformance is best expressed as the peak data transfer rates achieved using the dma. in most im plementations, this transfer rate is limited by the speed of the source and destination address spaces. in a s econd context where device-paced m ovement of single data values to/from peripherals is dominant, a me asure of the requests which can be se rviced in a fixed time is a more interesting metric. in this environment, the speed of the source and destination address spaces remains important, but the microarchitectur e of the dma also factors signifi cantly into the resulting metric. the peak transfer rates for several different source and destination tr ansfers are shown in table 16-28 . the following assumptions apply to table 16-28 and table 16-29 : ? platform sram can be accessed with zero wait-states when viewed from the amba-ahb data phase j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] dma_ipd_done[n-1:0]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-37 preliminary?subject to change without notice ? all ips reads require two wait-states, and ips wr ites three wait-states, again viewed from the system bus data phase ? all ips accesses are 32 bits in size table 16-28 presents a peak transfer rate comparison, measured in megabyte s per second. in this table, the platform_sram-to-platform_sram tran sfers occur at the native platform datapath width, i.e., either 32- or 64-bits per access. for a ll transfers involving the ips bus, 32-bit transfer sizes are used. in all cases, the transfer rate includes the time to read the s ource plus the time to write the destination. the second performance metric is a measure of the number of dma reque sts which can be serviced in a given amount of time. for this metric, it is assumed the peripheral request cause s the channel to move a single ips-mapped operand to/from the platform sram. the same timing assumptions used in the previous example apply to this calculation. in partic ular, this metric also re flects the time required to activate the channel. the dma design supports the following hardware service request sequence: ? cycle 1: ipd_req[n] is asserted ? cycle 2: the ipd_req[n] is registered locally in the dma module and qualified (tcd.start bit initiated requests start at this point with th e registering of the ip s write to tcd word7) ? cycle 3: channel arbitration begins ? cycle 4: channel arbitration completes. the tran sfer control descriptor local memory read is initiated. ? cycle 5 - 6: the first two parts of the activated channel?s tcd is read from the local memory. the memory width to the dma engine is 64 bits, so the entire descriptor can be accessed in four cycles. ? cycle 7: the first amba-ahb read cycle is initiated, as the third pa rt of the channe l?s tcd is read from the local memory. depending on the state of the platform?s cros sbar switch, arbi tration at the system bus may insert an ad ditional cycle of delay here. ? cycle 8 - ?: the last part of the tcd is read in. this cycle represen ts the 1st data phase for the read, and the address phase for the destination write. the exact timing from this point is a function of the response ti mes for the channel?s read and write accesses. in this case of an ips read and a plat form sram write, the comb ined data phase time is 4 cycles. for an sram read a nd ips write, it is 5 cycles. table 16-28. dma peak transfer rates [mb/s] platform speed, width platform sram-to- platform sram 32-bit ips-to- platform sram platform sram-to- 32-bit ips 66.7 mhz, 32-bit 133.3 66.7 53.3 66.7 mhz, 64-bit 266.7 66.6 53.3 83.3 mhz, 32-bit 166.7 83.3 66.7 83.3 mhz, 64-bit 333.3 83.3 66.7 100.0 mhz, 32-bit 200.0 100.0 80.0 100.0 mhz, 64-bit 400.0 100.0 80.0 133.3 mhz, 32-bit 266.7 133.3 106.7 133.3 mhz, 64-bit 533.3 133.3 106.7 150.0 mhz, 32-bit 300.0 150.0 120.0 150.0 mhz, 64-bit 600.0 150.0 120.0
pxd20 microcontroller reference manual, rev. 1 16-38 freescale semiconductor preliminary?subject to change without notice ? cycle ?+1: this cycle represents the da ta phase of the last destination write ? cycle ?+2: the dma engine completes the executi on of the inner minor loop and prepares to write back the required tcdn fields in to the local memory. tcd word7 is read and checked for channel linking or scatter/gather requests. ? cycle ?+3: the appropriate fields in the first pa rt of the tcdn are written back into the local memory ? cycle ?+4: the fields in the second part of the tcdn are written back into the local memory. this cycle coincides with the next channel arbitration cycle start. ? cycle ?+5: the next channel to be activated performs the read of th e first part of its tcd from the local memory. this is equivalent to cycle 4 for the first channel?s service request. assuming zero wait states on the ahb system bus, dma requests can be processed every 9 cycles. assuming an average of the access times associated with ips-to-sram (4 cycles) and sram-to-ips (5 cycles), dma requests can be processed every 11.5 cycles (4 + (4+5) ? 2 + 3). this is the time from cycle 4 to cycle ??+5.? the resulting peak request rate , as a function of the platform frequency, is shown in table 16-29 . this metric represents millions of requests per second. a general formula to compute the peak re quest rate (with overl apping requests) is: peakreq = freq ? [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: peakreq - peak request rate freq - platform frequency entry - channel startup (4 cycles) read_ws - wait states seen during the system bus read data phase write_ws - wait states seen duri ng the system bus write data phase exit - channel shutdown (3 cycles) for example: consider a platform with the following characteristics: table 16-29. dma peak request rate [mreq/sec] platform speed request rate (zero wait state) request rate (with wait states) 66.6 mhz 7.4 5.8 83.3 mhz 9.2 7.2 100.0 mhz 11.1 8.7 133.3 mhz 14.8 11.6 150.0 mhz 16.6 13.0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-39 preliminary?subject to change without notice ? platform sram can be accessed with one wait-state when view ed from the amba-ahb data phase ? all ips reads require two wait-states, and ips wr ites three wait-states, again viewed from the system bus data phase ? platform operates at 150 mhz for an sram to ips transfer: peakreq = 150 mhz ? [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 mreq/sec for an ips to sram transfer: peakreq = 150 mhz ? [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 mreq/sec assuming an even distribution of the two transfer types, the average peak request rate would be: peakreq = (11.5 mreq/sec + 12.5 mreq/sec) ? 2 = 12.0 mreq/sec the minimum number of cycles to pe rform a single read/write, zero wait states on the system bus, from a cold start (where no channel is executing, dma is idle) are: ? 11 cycles for a software (tcd.start bit) request ? 12 cycles for a hardware (ipd_req signal) request two cycles account for the arbitratio n pipeline and one extra cycle on th e hardware request resulting from the internal registering of the ipd_re q signals. for the peak request rate calculations above, the arbitration and request registering is absorbed in or overlap the previous executing channel. note when channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selecti on and startup. this allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for ne xt channel selection. 16.4 initialization/application information 16.4.1 dma initialization a typical initialization of the dma is: 1. write the dmacr register if a configuration other than the default is desired. 2. write the channel priority levels into the dchp rin registers if a conf iguration other than the default is desired. 3. enable error interrupts in the dmaeei registers if so desired. 4. write the 32 byte tcd for each ch annel that may request service. 5. enable any hardware service requests via the dmaerq register.
pxd20 microcontroller reference manual, rev. 1 16-40 freescale semiconductor preliminary?subject to change without notice 6. request channel service by either software (setting the tcd.start bit) or by hardware (slave device asserting its ipd_req signal). after any channel requests service, a channel is select ed for execution based on th e arbitration and priority levels written into the programmer' s model. the dma engine will read the entire tcd for the selected channel into its internal address path module. as the tc d is being read, the first transfer is initiated on the ahb bus unless a configuration erro r is detected. transfers from th e source (as defined by the source address, tcd.saddr) to the destinat ion (as defined by the destination address, tcd.daddr ) continue until the specified number of bytes (tcd.nbytes) have been transferred. when the transfer is complete, the dma engine's local tcd.saddr, tcd .daddr, and tcd.citer are written ba ck to the main tcd memory and any minor loop channe l linking is performed, if enabled. if the major loop is exhausted, further post processing is executed, i.e. interrupt s, major loop channel li nking, and scatter/gather operations, if enabled. 16.4.2 dma programming errors the dma performs various tests on the transfer control descriptor to verify cons istency in the descriptor data. most programming errors are reported on a per ch annel basis with the excep tion of two errors; group priority error and channel priority error, gp e and cpe in the dmaes register respectively. for all error types other than group or channel priori ty errors, the channel number causing the error is recorded in the dmaes register. if the error source is not removed before th e next activation of the problem channel, the error will be detected and recorded again. the sequence listed below is correct. for item 2, th e dma_ipd_ack{done} lines will assert only if the selected channel is requesti ng service via the ipd_req signa l. i think the typical application will enable error interrupts for all channels. so the user will get an error interrupt , but the channel num ber for the dmaerr register and the error interrupt re quest line may be wrong because th ey reflect the selected channel. channel priority errors are identifi ed within a group after that group has been selected as the active group. for example: 1. the dma is configured for fixed gro up and fixed channel arbitration modes. 2. group3 is the highest priority and al l channels are unique in that group. 3. group2 is the next highest priority and has two channels with the same priority level. 4. if group3 has any service requests, those requests will be executed. 5. once all of group3 requests have complete d, group2 will be the next active group. 6. if group2 has a service request, then an undefined channel in group2 will be selected and a channel priority error will occur. 7. this will repeat until the all of group2 reque sts have been removed or a higher priority group3 request comes in. a group priority error is globa l and any request in any group wi ll cause a group priority error. in general, if priority levels are not unique, the highe st (channel/group) priority that has an active request will be selected, but the lowest num bered (channel/group) with that priori ty will be select ed by arbitration
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-41 preliminary?subject to change without notice and executed by the dma engine. the hardware servi ce request handshake signals, error interrupts and error reporting will be associat ed with the selected channel. 16.4.3 dma arbitration mode considerations 16.4.3.1 fixed group arbitration, fixed channel arbitration in this mode, the channel service request from the hi ghest priority channel in the highest priority group will be selected to execute. if the dma is programmed so the channels within one group use ?fixed? priorities, and that group is assigned the highest ?fixed? prio rity of all groups, it is possible for that group to take all the bandwidth of the dma controller ? i.e. no other groups will be serv iced if there is always at least one dma request pending on a ch annel in the highest priority gro up when the controller arbitrates the next dma request. the advantage of this scenario is that latency can be small for channels that need to be serviced quickly. preemption is available in this scenario only. 16.4.3.2 round-robin grou p arbitration, fixed channel arbitration the occurrence of one or more dma requests from one or more gr oups, the channel with the highest priority from a specific group will be serviced first. groups are serviced starting with the highest group number with an service request and rotating thr ough to the lowest group number containing a service request. once the channel request is serviced, the group round robin algorithm will se lect the highest pending request from the next group in the round robin sequence. servicing cont inues round robin, always servicing the highest priority channel in the next gr oup in the sequence, or just skipping a group if it has no pending requests. if a channel requests service at a ra te that equals or exceeds the round ro bin service rate, then that channel will always be serviced before lower priority cha nnels in the same group, and thus the lower priority channels will never be serviced. the advantage of this scenario is that no one group uses all the dma bandwidth. the highest priority channel sel ection latency is potentially great er than fixed/fixed arbitration. excessive request rates on high priority channels can prevent the servicing of lower priority channels in the same group. 16.4.3.3 round-robin group arbitration, round-robin channel arbitration groups will be servic ed as described in section 16.4.3.2, round -robin group arbitration, fixed channel arbitration, but this time channels will be serviced in channel number order. only one channel is serviced from each requesting group for each round robin pass through the groups. within each group, channels are serv iced starting with the highest ch annel number and rotating through to the lowest channel number without re gard to channel priority levels.
pxd20 microcontroller reference manual, rev. 1 16-42 freescale semiconductor preliminary?subject to change without notice because channels are serviced in round robin manner, any channel that generates dma reque sts faster than a combination of the group round robin service rate and the channel service ra te for its group will not prevent the servicing of other channels in its group. any dma requests that are not serviced are simply lost, but at least one channel will be serviced. this scenario ensures that all channe ls will be guaranteed se rvice at some point, regardless of the request rates. however, the potential latency could be quite high. all channels are treated equally. priority leve ls are not used in r ound robin/round robin mode. 16.4.3.4 fixed group arbitration, round-robin channel arbitration the highest priority group with a requ est will be serviced. lo wer priority groups will be serviced if no pending requests exist in th e higher priority groups. within each group, channels are serv iced starting with the highest ch annel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. this scenario could cause the same bandwid th consumption problem as indicated in section 16.4.3.1, fixed group arbitration, fi xed channel arbitration, but all the channels in the highest priority group will be serviced. service latency will be short on the highest priori ty group, but can become much longer as the group priority decreases. 16.4.4 dma transfer 16.4.4.1 single request to perform a simply transfer of ?n? bytes of data w ith one activation, set the major loop to one (tcd.citer = tcd.biter = 1). the data transf er will begin after the channel serv ice request is acknowledged and the channel is selected to exec ute. once the transfer is co mplete, the tcd.done bit will be set and an interrupt will be generated if properly enabled. for example, the following tcd entry is configured to transfer 16 byte s of data. the dm a is programmed for one iteration of the major loop transferring 16 bytes per iteration. the source memory has a byte wide memory port located at 0x1000. the destination memory has a word wide port located at 0x2000. the address offsets are programmed in increments to matc h the size of the transfer; one byte for the source and four bytes for the destination. the fi nal source and destinati on addresses are adjusted to return to their beginning values. tcd.citer = tcd.biter = 1 tcd.nbytes = 16 tcd.saddr = 0x1000 tcd.soff = 1 tcd.ssize = 0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-43 preliminary?subject to change without notice tcd.slast = -16 tcd.daddr = 0x2000 tcd.doff = 4 tcd.dsize = 2 tcd.dlast_sga= -16 tcd.int_maj = 1 tcd.start = 1 (tcd.word7 should be written last after all other fields have been initialized) all other tcd fields = 0 this generates the following sequence of events: 1. ips write to the tcd.start bit requests channel service 2. the channel is selected by arbitration for servicing 3. dma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 4. dma engine reads: channel tcd data from local memory to internal register file 5. the source to destination transfers are executed as follows: a. read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b. write_word(0x2000) -> first iteration of the minor loop c. read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d. write_word(0x2004) -> second iteration of the minor loop e. read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f. write_word(0x2008) -> third iteration of the minor loop g. read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h. write_word(0x200c) -> last iteration of the minor loop -> major loop complete 6. dma engine writes: tcd.saddr = 0x1000, tcd.daddr = 0x2000, tcd.citer = 1 (tcd.biter) 7. dma engine writes: tcd.active = 0, tcd.done = 1, dmaint[n] = 1 8. the channel retires the dma goes idle or se rvices next channel. 16.4.4.2 multiple requests the next example is the sa me as the previous example, with the exception of transfer ring 32 bytes via two hardware requests. the only fields that change are the major loop iteration count and the final address offsets. the dmais programmed for two iterations of the major loop transferri ng 16 bytes per iteration. after the channel?s hardware requests is enabled in the dmaerq register, channel service requests are initiated by the slave device.
pxd20 microcontroller reference manual, rev. 1 16-44 freescale semiconductor preliminary?subject to change without notice tcd.citer = tcd.biter = 2 tcd.slast = -32 tcd.dlast_sga = -32 this would generate the fo llowing sequence of events: 1. first hardware (ipd_req) request for channel service 2. the channel is selected by arbitration for servicing 3. dma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 4. dma engine reads: channel tcd data from local memory to internal register file 5. the source to destination transfers are executed as follows: a. read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b. write_word(0x2000) -> first iteration of the minor loop c. read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d. write_word(0x2004) -> second iteration of the minor loop e. read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f. write_word(0x2008) -> third iteration of the minor loop g. read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h. write_word(0x200c) -> last iteration of the minor loop 6. dma engine writes: tcd.saddr = 0x1010, tcd.daddr = 0x2010, tcd.citer = 1 7. dma engine writes: tcd.active = 0 8. the channel retires -> one iteration of the major loop the dma goes idle or se rvices next channel. 9. second hardware (ipd_req) requests channel service 10. the channel is selected by arbitration for servicing 11. dma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 12. dma engine reads: channel tcd data from local memory to internal register file 13. the source to destination transfers are executed as follows: a. read_byte(0x1010), rea d_byte(0x1011), read_byte( 0x1012), read_byte(0x1013) b. write_word(0x2010) -> first iteration of the minor loop c. read_byte(0x1014), rea d_byte(0x1015), read_byte( 0x1016), read_byte(0x1017) d. write_word(0x2014) -> second iteration of the minor loop e. read_byte(0x1018), rea d_byte(0x1019), read_byte(0 x101a), read_byte(0x101b) f. write_word(0x2018) -> third iteration of the minor loop g. read_byte(0x101c), r ead_byte(0x101d), read_byte (0x101e), read_byte(0x101f)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-45 preliminary?subject to change without notice h. write_word(0x201c) -> last iteration of the minor loop -> major loop complete 14. dma engine writes: tcd.saddr = 0x1000, tcd.daddr = 0x2000, tcd.citer = 2 (tcd.biter) 15. dma engine writes: tcd.active = 0, tcd.done = 1, dmaint[n] = 1 16. the channel retires -> major loop complete the dma goes idle or services the next channel. 16.4.5 tcd status 16.4.5.1 minor loop complete there are two methods to test for minor loop completi on when using software init iated service requests. the first method is to read the tcd.citer field and test for a change. anothe r method may be extracted from the sequence shown below. the second method is to test the tcd.start bit an d the tcd.active bit. the minor loop complete condition is indicated by both bits reading zer o after the tcd.start was written to a one. polling the tcd.active bit may be inconclusi ve because the active status may be missed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: 1. tcd.start = 1, tcd.active = 0, tcd.done = 0 (channel service request via software) 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing) 3. tcd.start = 0, tcd.active = 0, tc d.done = 0 (channel has complete d the minor loop and is idle) or tcd.start = 0, tcd.active = 0, tc d.done = 1 (channel has complete d the major loop and is idle) the best method to test for minor loop completion wh en using hardware initiate d service requests is to read the tcd.citer field and test for a change. the hardware request and acknowledge handshakes signals are not visible in the programmer?s model. the tcd status bits execute the following sequence for a hardware activated channel: 1. ipd_req asserts (channel se rvice request via hardware) 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing) 3. tcd.start = 0, tcd.active = 0, tc d.done = 0 (channel has complete d the minor loop and is idle) or tcd.start = 0, tcd.active = 0, tc d.done = 1 (channel has complete d the major loop and is idle) for both activation types, the major loop complete stat us is explicitly indica ted via the tcd.done bit. the tcd.start bit is cleared automatically when th e channel begins execution regardless of how the channel was activated.
pxd20 microcontroller reference manual, rev. 1 16-46 freescale semiconductor preliminary?subject to change without notice 16.4.5.2 active channel tcd reads the dma will read back th e ?true? tcd.saddr, tcd.dadd r, and tcd.nbytes values if read while a channel is executing. the ?true? values of th e saddr, daddr, and nbytes are the va lues the dma engine is currently using in its internal register file and not the values in the tcd local memory for that channel. the addresses (saddr and daddr) and nbyt es (decrements to zero as the tr ansfer progresses) can give an indication of the progress of the tr ansfer. all other values are read back from the tcd local memory. 16.4.5.3 preemption status preemption is only available when fixed arbitration is selected for both group and channel arbitration modes. a preempt-able situ ation is one in which a preempt-ena bled channel is running and a higher priority request be comes active. when the dma engine is not operating in fixed group, fixed channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. channel a nd/or group priorities are treated as equal (constantly rotating) when round-robin arbitration mode is selected. the tcd.active bit for the preempted channel remain s asserted throughout the preemption. the preempted channel is temporarily suspended wh ile the preempting channel executes one iteration of the major loop. two tcd.active bits set at the same time in the overa ll tcd map indicates a high er priority channel is actively preempting a lo wer priority channel. the worst case latency when switching to a preempt channel is the summation of: ? arbitration latency (2 cycles) ? bandwidth control stalls (if enabled) ? the time to execute two read/write sequences (including ahb bus holds ; a system dependency driven by the slave devices or the crossbar) 16.4.6 channel linking channel linking (or chaining) is a m echanism where one channel sets the tcd.start bit of another channel (or itself) thus initiating a service request for that channel. this operation is automatically performed by the dma engine at the conclusion of the ma jor or minor loop when properly enabled. the minor loop channel linking occurs at the completio n of the minor loop (or one iteration of the major loop). the tcd.citer.e_link field are used to determ ine whether a minor loop link is requested. when enabled, the channel link is made after each iterati on of the major loop except for the last. when the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. for example, with the initial fields of: tcd.citer.e_link = 1 tcd.citer.linkch = 0xc tcd.citer value = 0x4 tcd.major.e_link = 1 tcd.major.linkch = 0x7
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-47 preliminary?subject to change without notice will execute as: 1. minor loop done -> set channel 12 tcd.start bit 2. minor loop done -> set channel 12 tcd.start bit 3. minor loop done -> set channel 12 tcd.start bit 4. minor loop done, major loop done -> set channel 7 tcd.start bit when minor loop linking is enabled (t cd.citer.e_link = 1), the tcd.citer field uses a nine bit vector to form the current iteration count. when minor loop linking is disabled (t cd.citer.e_link = 0), the tcd.citer fi eld uses a 15 bit vector to form the current iteration count. the bits associated with the tcd.citer.linkch field are concatenated onto the citer value to increase the range of the citer. note the tcd.citer.e_link bit and the tcd .biter.e_link bit must equal or a configuration error will be reported. th e citer and biter vector widths must be equal to calculate the major loop, half-way done interrupt point. 16.4.7 dynamic programming this section provides recommended methods to cha nge the programming model during channel execution. 16.4.7.1 dynamic priority changing the following two options are r ecommended for dynamically changing channel priority levels: 1. switch to round-robin channel arbi tration mode, change the channel priorities, then switch back to fixed arbitration mode. 2. disable all the channels within a group, then change the channel prio rities within that group only, then enable the appropriate channels. the following two options are av ailable for dynamically changing group priority levels: 1. switch to round-robin group arbitr ation mode, change the group priorities, then switch back to fixed arbitration mode. 2. disable all channels, change the group priori ties, then enable the appropriate channels. 16.4.7.2 dynamic channel linki ng and dynamic scatter/gather dynamic channel linking and dynamic scatter/gather is the process of changing the tcd.major.e_link or tcd.e_sg bits during channel execution. these bits are read from the tcd local memory at the end of channel execution thus allowing the user to en able either feature dur ing channel execution. because the user is allowed to change the configur ation during execution, a c oherency model is needed. consider the scenario where the user attempts to execute a dynamic channel link by enabling the tcd.major.e_link bit at the same time the dma engi ne is retiring the channel. the tcd.major.e_link would be set in the programmer?s m odel, but it would be unclear whet her the actual link was made before the channel retired.
pxd20 microcontroller reference manual, rev. 1 16-48 freescale semiconductor preliminary?subject to change without notice the following coherency model is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. set the tcd.major.e_link bit. 2. read back the tcd.major.e_link bit. 3. test the tcd.major.e_link request status: a. if the bit is set, the dynamic link attempt was successful. b. if the bit is cleared, the attempted dynami c link did not succeed, the channel was already retiring. this same coherency model is tr ue for dynamic scatter/gather opera tions. for both dynamic requests, the tcd local memory controller forces the tcd.major.e_ link and tcd.e_sg bits to zero on any writes to a channel?s tcd.word7 after that channel?s tcd.done bit is set indicating the major loop is complete. note the user must clear the tcd.done bi t before writing th e tcd.major.e_link or tcd.e_sg bits. the tcd.done bit is cleared automatically by the dma engine after a channel begins execution. 16.4.8 hardware request release timing this section provides a timing di agram for deasserting the ipd_r eq hardware request signal. figure 16-30 shows two read write sequen ces with grey indicating the release of the ipd_req hardware request signal. figure 16-30. ipd_req hardware handshake rd1 wr1 rd2 wr2 hclk htrans ahb_ap ipd_req ipd_ack ipd_done hwrite rd1 wr1 rd2 wr2 ahb_dp done_lw ipd_complete note: ipd_req must de-assert in this cycl e unless another service request is intended
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 16-49 preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 16-50 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-1 preliminary?subject to change without notice chapter 17 edma channel mux (dmachmux) 17.1 introduction 17.1.1 overview the dmachmux controls the routing of multiple dma peripheral sources (cal led slots) to 16 edma channels. this is illustrated in figure 17-1 . figure 17-1. dmachmux block diagram 17.1.2 features the dma channel mux provides these features: ? 41 peripheral slots + 8 always-on sl ots can be routed to 16 channels ? 16 independently selectab le dma channels routers ? the first 8 channels additionally provide a trigger functionality source #1 source #2 source #3 dma channel #1 dma channel #0 dmachmux always #1 trigger #1 dma channel # 15 trigger # 8 always # 8 source # 63
pxd20 microcontroller reference manual, rev. 1 17-2 freescale semiconductor preliminary?subject to change without notice ? each channel router can be assigned to one of 41 possible peri pheral dma slots or to one of the 8 always-on slots. 17.1.3 modes of operation the following operation modes are available: ? disabled mode in this mode, the dma channel is disabled. sinc e disabling and enabling of dma channels is done primarily via the dma conf iguration registers, this mode is us ed mainly as the reset state for a dma channel in the dma channel mux. it may al so be used to temporarily suspend a dma channel while reconfiguration of the system takes place (e.g. changing the period of a dma trigger). ? normal mode in this mode, a dma source (such as dspi transmit or dspi rece ive for example) is routed directly to the specified dma channel. the operation of the dma mux in this mode is completely transparent to the system. ? periodic trigger mode in this mode, a dma source may only request a dma transfer (such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. conf iguration of th e period is done in the registers of the periodic in terrupt timer (pit). this mode is only available for channels 0-8. 17.2 external signal description 17.2.1 overview the dma channel mux has no external pins. 17.3 memory map and register definition this section provides a detailed description of al l memory-mapped registers in the dma channel mux. table 17-1 shows the memory map for the dma channel m ux. note that all addresses are offsets; the absolute address may be computed by adding the specified offset to th e base address of the dma channel mux. table 17-1. module memory map address use access location base + 0x00 channel #0 configuration (chconfig0) r/w on page 17-3 base + 0x01 channel #1 configuration (chconfig1) r/w on page 17-3 .. .. .. .. base + 0x #n-1 channel #n configuration (chconfig #n-1 ) 1 1 in the table n refers to the number of channels - 1 r/w on page 17-3
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-3 preliminary?subject to change without notice all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. as an example, chconfig0 through chconfig3 are accessible by a 32-bit read/write to address ?base + 0x00?, but performing a 32-bit access to ad dress ?base + 0x01? is illegal. 17.3.1 register descriptions the following memory-mapped registers ar e available in the dma channel mux. 17.3.1.1 channel configuration registers each of the dma channels can be independently enab led/disabled and associat ed with one of the dma slots (peripheral slots or alwa ys-on slots) in the system. address: base + #n access: user read/write 0 1 2 3 4 5 6 7 r enbl trig source w reset 0 0 0 0 0 0 0 0 figure 17-2. channe l configuration re gisters (chconfig #n ) table 17-2. chconfig xx field descriptions field description enbl dma channel enable. enbl enables the dma channel 0 dma channel is disabled. this mode is primarily used during configuration of the dma mux. the dma has separate channel enables/disables, which should be used to disable or re-configure a dma channel. 1 dma channel is enabled trig dma channel trigger enable (for triggered channels only). trig enables the periodic trigger capability for the dma channel 0 triggering is disabled. if triggering is disabled, and the enbl bit is set, the dma channel will simply route the specified source to the dma channel. 1 triggering is enabled source dma channel source (slot). source specifies wh ich dma source, if any, is routed to a particular dma channel. please check your soc-guide for further details about the peripherals and their slot numbers. table 17-3. channel and trigger enabling enbl trig function mode 0 x dma channel is disabled disabled mode 1 0 dma channel is enabled with no triggering (transparent) normal mode 1 1 dma channel is enabled with triggering periodic trigger mode
pxd20 microcontroller reference manual, rev. 1 17-4 freescale semiconductor preliminary?subject to change without notice note setting multiple chconfig registers with the same source value will result in unpredictable behavior. note before changing the trigger or sour ce settings a dma ch annel must be disabled via the chconfig[ #n ].enbl bit. table 17-4. dmachmux request assignments dma requesting module dmachmux source number (ipd_ref_peripher[n periphs :1]) channel disable 1 dma mux source #0 dspi 0 tx dma mux source #1 dspi 0 rx dma mux source #2 dspi 1 tx dma mux source #3 dspi 1 rx dma mux source #4 dspi 2 tx dma mux source #5 dspi 2 rx dma mux source #6 i2c_0 tx dma mux source #7 i2c_0 rx dma mux source #8 i2c_1 tx dma mux source #9 i2c_1 rx dma mux source #10 i2c_2 tx dma mux source #11 i2c_2 rx dma mux source #12 i2c_3 tx dma mux source #13 i2c_3 rx dma mux source #14 emios0_flag_f9 dma mux source #15 emios0_flag_f11 dma mux source #16 emios0_flag_f13 dma mux source #17 emios0_flag_f15 dma mux source #18 emios0_flag_f17 dma mux source #19 emios0_flag_f19 dma mux source #20 emios0_flag_f21 dma mux source #21 emios1_flag_f9 dma mux source #22 emios1_flag_f11 dma mux source #23 emios1_flag_f13 dma mux source #24 emios1_flag_f15 dma mux source #25
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-5 preliminary?subject to change without notice emios1_flag_f17 dma mux source #26 emios1_flag_f19 dma mux source #27 emios1_flag_f21 dma mux source #28 reserved dma mux source #29 reserved dma mux source #30 linflexd_a rx fifo fill dma mux source #31 linflexd_a tx fifo fill dma mux source #32 linflexd_b rx fifo fill dma mux source #33 linflexd_b tx fifo fill dma mux source #34 linflexd_c rx fifo fill dma mux source #35 linflexd_c tx fifo fill dma mux source #36 linflexd_d rx fifo fill dma mux source #37 linflexd_d tx fifo fill dma mux source #38 dramc priority manager dma req dma mux source #39 quadspi_rx dma mux source #40 reserved dma mux source #41 reserved dma mux source #42 sgm-ch0 dma mux source #43 sgm-ch1 dma mux source #44 sgm-ch2 dma mux source #45 sgm-ch3 dma mux source #46 reserved dma mux source #47 reserved dma mux source #48 reserved dma mux source #49 reserved dma mux source #50 adc dma mux source #51 reserved dma mux source #52 rle tx fifo (data out) dma mux source #53 rle rx fifo (data in) dma mux source #54 reserved dma mux source #55 always requestors dma mux source #56 always requestors dma mux source #57 table 17-4. dmachmux request assignments (continued) dma requesting module dmachmux source number (ipd_ref_peripher[n periphs :1])
pxd20 microcontroller reference manual, rev. 1 17-6 freescale semiconductor preliminary?subject to change without notice 17.4 functional description this section provides a functional description of the dma channel mux. the primary purpose of the dma channel mux is to provide flex ibility in the system?s use of th e available dma channels. as such, configuration of the dma mux is intended to be a static procedure done duri ng execution of the system boot code. however, if the procedure outlined in section 17.5.3, enabling and configuring sources , is followed, the configuration of th e dma channel mux may be changed during the normal operation of the system. functionally, the dma channel mux channels may be divided into two classes: channels, which implement the normal routing functionality plus periodic triggering capability, and channels, which implement only the normal routing functionality. 17.4.1 dma channels with peri odic triggering capability besides the normal routing functionalit y, the first 8 channels of the dma mux provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or packets at fixed intervals without the need for pr ocessor intervention. the trigger is generated by the periodic interrupt timer (pit); as such, the configuration of the peri odic triggering interval is done via configuration registers in the pit. please refer to chapter 32, periodic interrupt timer (pit), for more information on this topic. table 17-5 shows the mapping of pit channels to dma channels for triggering. always requestors dma mux source #58 always requestors dma mux source #59 always requestors dma mux source #60 always requestors dma mux source #61 always requestors dma mux source #62 always requestors dma mux source #63 1 configuring a dma channel to select source 0 or any reserved sources will disable that dma channel. table 17-5. pit-dma channel mapping pit channel number dmachmux channel number for triggering 0 0 1 1 2 2 3 3 table 17-4. dmachmux request assignments (continued) dma requesting module dmachmux source number (ipd_ref_peripher[n periphs :1])
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-7 preliminary?subject to change without notice note because of the dynamic nature of the system (i.e. dma ch annel priorities, bus arbitration, interrupt service routin e lengths, etc.), the number of clock cycles between a trigger and the actu al dma transfer ca nnot be guaranteed. figure 17-3. dma mux triggered channels the dma channel triggering capability allows the syst em to ?schedule? regula r dma transfers, usually on the transmit side of certain periphe rals, without the intervention of th e processor. this trigger works by gating the request from the peripheral to the dma until a trigger event has been s een. this is illustrated in figure 17-4 . figure 17-4. dma mux channel triggering: normal operation dma channel #0 tr i g g e r # 1 tr i g g e r # 0 source #1 source #2 source #3 always #1 dma channel # 3 always # 8 trigger #3 source # 63 periph request tr i g g e r dma request
pxd20 microcontroller reference manual, rev. 1 17-8 freescale semiconductor preliminary?subject to change without notice once the dma request has been servic ed, the peripheral will negate its request, effectively resetting the gating mechanism until the periphe ral re-asserts its request and the next trigger event is seen. this means that if a trigger is seen, but the peripheral is not reque sting a transfer, that trigge red will be ignored. this situation is illustrated in figure 17-5 . figure 17-5. dma mux channel triggering: ignored trigger this triggering capability may be used with any periphe ral that supports dma transf ers, and is most useful for two types of situations: ? periodically polling external devices on a particular bus. as an exampl e, the transmit side of an spi is assigned to a dma channel with a trigger, as described above. once setup, the spi will request dma transfers (presumably from memory) as long as its transmit buffer is empty. by using a trigger on this channel, the spi transfer s can be automatically performed every 5 ? s (as an example). on the receive side of the spi, the spi and dma can be configured to transfer receive data into memory, effectively implementing a met hod to periodically read data from external devices and transfer the results into memory without processor intervention. ? using the gpio ports to drive or sample waveform s. by configuring the dma to transfer data to one or more gpio ports, it is possible to create complex waveforms using ta bular data stored in on-chip memory. conversely, using the dma to peri odically transfer data from one or more gpio ports, it is possible to sample co mplex waveforms and store the resu lts in tabular form in on-chip memory. a more detailed description of the capability of each trigger (i.e.-resolu tion, range of values, etc.) may be found in the periodic interrupt timer (pit) block guide. 17.4.2 dma channels with no triggering capability the other channels of the dma mux provide the normal routing functionali ty as described in section 17.1.3, modes of operation . 17.4.3 "always enabled" dma sources in addition to the peripherals that can be used as dma sources, there are 8 a dditional dma sources that are "always enabled". unlike the peri pheral dma sources, where the peripheral controls the flow of data during dma transfers, the "always enabled" sources pr ovide no such "throttling" of the data transfers. these sources are most useful in the following cases: ? doing dma transfers to/from gpio - moving data from/to one or more gpio pins, either un-throttled (i.e.-as fast as possible), or pe riodically (using the dma triggering capability). periph request tr i g g e r dma request
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-9 preliminary?subject to change without notice ? doing dma transfers from memory to memory - moving data from memory to memory, typically as fast as possible, sometimes with software activation. ? doing dma transfers from memory to the external bus (or vice-versa) - similar to memory to memory transfers, this is typically done as quickly as possible. ? any dma transfer that requires so ftware activation - any dma transf er that should be explicitly started by software. in cases where software s hould initiate the start of a dma transfer, a "always enabled" dma source can be used to provide maximum flexibility. when activating a dma channel via software, subsequent executions of the minor loop require a new "start" ev ent be sent. this can ei ther be a new software activation, or a transfer request from the dm a channel mux. the options for doing this are: ? transfer all data in a si ngle minor loop. by configuring the dma to transfer all of the data in a single minor loop (i.e.-major loop counter = 1), no re-activation of the channel is necessary. the disadvantage to this option is the reduced granularity in determining the load that the dma transfer will incur on the system. for this option, the dma channel should be disabl ed in the dma channel mux. ? use explicit software re-activati on. in this option, the dma is confi gured to transfer the data using both minor and major loops, but the processor is re quired to re-activate the channel (by writing to the dma registers) after every minor loop . for this option, the dma channel should be disabled in the dma channel mux. ? use a "always enabled" dma source. in this opti on, the dma is configured to transfer the data using both minor and major loops, and the dma channel mux does the channel re-activation. for this option, the dma channe l should be enabled and pointing to an "always enabled" source. note that the re-activation of the chan nel can be continuous (dma trigge ring is disabled) or can use the dma triggering capability. in this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 17.5 initialization/application information 17.5.1 reset the reset state of each individua l bit is shown within the regi ster description section (see section 17.3.1, register descriptions ). in summary, after reset, all channels ar e disabled and must be explicitly enabled before use. 17.5.2 low power considerations the dma channel mux has no direct involvement wi th operations to place the mcu into low power modes, however, it is possible for the low power tr ansition to be blocked under certain circumstances. specifically, the mcu may not enter a low power mode (halt/stop/standby) when all the below conditions are true simultaneously: ? a peripheral with dma capability is pr ogrammed to work on a divided clock.
pxd20 microcontroller reference manual, rev. 1 17-10 freescale semiconductor preliminary?subject to change without notice ? this peripheral is programmed to be stopped in the required low power mode and active in run mode. ? and this peripheral is active with a dma transf er when software requests a transition to low power mode. to ensure correct operation, ensure that all the dm a enabled peripherals have completed their transfers before requesting transi tion to low power mode. 17.5.3 enabling and configuring sources enabling a source with periodic triggering 1. determine with which dma channel the source will be associated. note th at only the first 8 dma channels have periodic triggering capability. 2. clear the enbl and trig bits of the dma channel 3. ensure that the dma channel is properly conf igured in the dma. the dma channel may be enabled at this point 4. configure the corresponding timer 5. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set example 17-1. configure source #5 transmit for use with dma channel 2, with periodic triggering capability 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the dm a, including enabling the channel 3. configure a timer for the desired trigger interval 4. write 0xc5 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h"
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-11 preliminary?subject to change without notice : : *chconfig2 = 0x00; *chconfig2 = 0xc5; enabling a source without periodic triggering 1. determine with which dma channel the source will be associated. note th at only the first 8 dma channels have periodic triggering capability. 2. clear the enbl and trig bits of the dma channel 3. ensure that the dma channel is properly conf igured in the dma. the dma channel may be enabled at this point 4. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl is set and the trig bit is cleared example 17-2. configure source #5 transmit for use with dma channel 2, with no periodic triggering capability. 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the dm a, including enabling the channel 3. write 0x85 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0x85; disabling a source
pxd20 microcontroller reference manual, rev. 1 17-12 freescale semiconductor preliminary?subject to change without notice a particular dma source may be disabled by not writing the correspon ding source value into any of the chconfig registers. additionally, some module spec ific configuration may be necessary. please refer to the appropriate section for more details. switching the source of a dma channel 1. disable the dma channel in the dma and re -configure the channel for the new source 2. clear the enbl and trig bits of the dma channel 3. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set example 17-3. switch dma channel 8 from source #5 transmit to source #7 transmit 1. in the dma configuration registers, disable dma channel 8 and re-con figure it to handle the transfers to peripheral slot 7. this example assu mes channel 8 doesn?t have triggering capability. 2. write 0x00 to chconfig8 (base address + 0x08) 3. write 0x87 to chconfig8 (base ad dress + 0x08). (in this example, setting the tr ig bit would have no effect, due to the assumption that ch annels 8 does not support the periodic triggering functionality). the following code example il lustrates steps #2 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig8 = 0x00; *chconfig8 = 0x87;
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 17-13 preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 17-14 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-1 preliminary?subject to change without notice chapter 18 enhanced modular io subsystem (emios) 18.1 introduction the configurable enhanced modul ar input/output subsystem (emi os200 or just emios) provides functionality to generate or measure time events. the emios200 bui lds on this concept by using a unified channel module that provides a supers et of the functionality of all th e individual mios channels, while providing a consistent user interface. each unified ch annel can be programmed fo r different functions in different applications of the chip . besides that, emios200 architectur e uses dedicated channels which perform specific functions not in cluded in mios inheritance. figure 18-1 shows the block diagram of the configurable emios200 block. figure 18-1. emios200 block diagram biu counter buses (time bases) ip interface submodules all iib interrupt signals slave bus signals global signals dma interface signals enhanced modular input/output system clock prescaler system clock internal counter clock enable ................ output disable control bus see note 1 notes: 1. connection between uc[n-1] and uc[n] ch[8] emiosi[8] emioso[8] ipp_obe_emios_ch[8] emios_flag_out[8] ch[15] emiosi[15] emioso[15] ipp_obe_emios_ch[15] emios_flag_out[15] [c] ch[16] emiosi[16] emioso[16] ipp_obe_emios_ch[16] emios_flag_out[16] ch[23] emiosi[23] emioso[23] ipp_obe_emios_ch[23] emios_flag_out[23] [d] counter buses (time bases) ................ necessary to implement qdec mode output disable input[0:3] (clock sent to all channels which support in internal counter) [a]
pxd20 microcontroller reference manual, rev. 1 18-2 freescale semiconductor preliminary?subject to change without notice 18.2 features the basic features of the emios200 are the following: ? 32 channels (16 on emios0 and 16 in emios1 ) chosen among unified or dedicated channels. numbered channel 8:23. ? data registers of 16-bit width ? counter buses c, and d can be driven by unified channel 8, and 16, respectively ? counter bus a can be driven by the unified channel #23 ? each channel has its own time base , alternative to the counter buses ? one global prescaler ? one prescaler per channel (cp) ? shared timebases through the counter buses ? control and status bits grouped in a single register ? synchronization among timebases ? global flag register ? state of the uc can be frozen for debug purposes ? motor control capability 18.3 modes of operation the unified channels can be configured to operate in the following modes: ? general purpose input/output ? single action input capture ? single action output compare ? modulus counter buffered ? output pulse width and frequency modulation buffered ? output pulse width modulation buffered ? quadrature decode these modes are described in section 18.7.1.1, uc modes of operation . each channel can have a specific set of mode s implemented, according to devices requirements. if an unimplemented mode is selected the results ar e unpredictable such as writing a reserved value to mode[0:6] in section 18.6.2.8, emios200 uc control register (ccr[n]). 18.4 device-specific information this device includes two emios modules, emios0 and emios1. both are 16-channel modules. the emios provides timer (ic/oc), pwm functionality, and quadrature decode functionality. on this chip, the emios modules have ch annels clocked by either a m odulated or a non-modulated clock.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-3 preliminary?subject to change without notice 18.4.1 unsupported features ? real-time signal bus client ? wheel speed channels ? emios0 channels 0?7 ? channels 9-15 do not support ope rations on internal counter ? emios1 channels 0?7 18.4.2 device-specific configuration ? both emios0 and emios1 can work on a ny of the four auxiliary clock sources: ?irc ?fxosc ? fmpll0 ? fmpll1 ? for emios0: ? counter bus a is driven by unified channel #23 ? counter bus c is driven by unified channel #8 ? counter bus d is driven by unified channel #16 ? unified channels 9?15 do not have their own time base ? for emios1: ? counter bus a is driven by unified channel #23 ? counter bus c is driven by unified channel #8 ? counter bus d is driven by unified channel #16 18.4.3 emios clocking configuration the clocking configurations of the emios0 a nd emios1 modules on this device are shown in figure 18-2 .
pxd20 microcontroller reference manual, rev. 1 18-4 freescale semiconductor preliminary?subject to change without notice figure 18-2. emios clocking configuration 18.4.4 channel types the channels of the emios0 and emios1 blocks on this device are implemented using a variety of different channel configurations. the available m odes of operation for each channel are shown in table 18-1 and table 18-2 . table 18-1. emios0 channel configurations channel number channel type mode (see table 18-3 ) gpio saic saoc mcb opwfmb opwmb 8ic/oc counter xxxx?? 9 ic/oc x x x ? ? ? 10 xxx??? 11 xxx??? 12 xxx??? 13 xxx??? 14 xxx??? 15 xxx??? fmpll_0 emios0 cgm_ac1_sc[selctl] modulated clock fmpll_1 cgm_ac2_sc[selctl] non_modulated clock 8 channels 8 channels 16 mhz irc 4-16 mhz fxosc emios1 8 channels 8 channels
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-5 preliminary?subject to change without notice 16pwm counter xxxxxx 17pwm xxx?xx 18 xxx?xx 19 xxx?xx 20 xxx?xx 21 xxx?xx 22 xxx?xx 23pwm counter xxxxxx table 18-2. emios1 channel configurations channel number channel type mode (see table 18-3 ) gpio saic saoc mcb opwfmb opwmb qdec 8 ic/oc counter x x x x ? ? ? 9ic/oc x x x?x x? 10 x x x?x x? 11 xxx?xxx 12 x x x?x x? 13 xxx?xxx 14 x x x?x x? 15 x x x?x x? 16 pwm counter x x x x x x ? 17pwm x x x?x x? 18 x x x?x x? 19 xxx?xxx 20 x x x?x x? 21 xxx?xxx 22 x x x?x x? 23 pwm counter x x x x x x ? table 18-1. emios0 channel configurations (continued) channel number channel type mode (see table 18-3 ) gpio saic saoc mcb opwfmb opwmb
pxd20 microcontroller reference manual, rev. 1 18-6 freescale semiconductor preliminary?subject to change without notice 18.4.5 unified channel block figure 18-3 shows the block diagram of unified channel bl ock as it is implemented in this device. figure 18-3. unified channel block table 18-3. emios channel configuration abbreviations abbreviation meaning gpio general-purpose input/output mcb modulus counter buffered opwfmb output pulse width and frequency modulation buffered opwmb output pulse width modulation buffered qdec quadrature decode saic single action input compare saoc single action output compare
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-7 preliminary?subject to change without notice 18.5 external signal description 18.5.1 overview each channel has one external input and one external out put signal, as described in table 18-4 . the input and output signals are connected to a single bidirectional pin. 18.5.2 detailed signal descriptions 18.5.2.1 emiosi[n] - emios 200 channel input signal emiosi[n] is synchronized and filtered by the input programmabl e filter (ipf). the output of the ipf is then used by the channel logic and is available to be read by the mcu through the ucin bit of the csr[n] register. 18.5.2.2 emioso[n] - emios2 00 channel output signal emioso[n] is a registered output and is available for reading by th e mcu through the ucout bit of the csr[n] register. whilst the channel is opera ting in input modes th e signal state is unknown. 18.5.2.3 emios_flag_out[n] - em ios200 channel flag signal emios_flag_out[n] outputs the state of f[n] bit of gfr register. 18.6 memory map and register description 18.6.1 memory map the overall address map or ganization is shown in table 18-5 . whenever an access to either an absent register or absent channel is perf ormed the emios200 responds asserting transfer error signal from the slave bus in terface, as well as for access to reserved address. table 18-4. external signals signal direction function reset state pull up emiosi[n] input emios200 channel n input ? chip dependent emioso[n] output emios200 channel n output 0/ hi-z 1 1 value ?0? refers to the reset value of the signal. hi-z refers to the state of the external pin if a tristate output buffer is controlled by the corresponding ipp_obe_emios_ch[n] signal. chip dependent emios_flag_out[n] output emios200 channel n flag 0 chip dependent
pxd20 microcontroller reference manual, rev. 1 18-8 freescale semiconductor preliminary?subject to change without notice 18.6.1.1 unified channel memory map addresses of unified channel register s are specified as offsets from the channel?s base address, otherwise the emios200 base address is used as reference. table 18-6 describes the unified channel memory map. table 18-5. emios200 memory map emios n base address description location 0x000 0x003 module configuration register (mcr) on page 18-9 0x004 0x007 global flag register (gfr) on page 18-10 0x008 0x00b output update disable (oudr) on page 18-11 0x00c 0x00f disable channel (ucdis) on page 18-12 0x010 0x11f reserved ? 0x120 0x21f channel [8] to channel [15] 0x220 0x31f channel [16] to channel [23] 0x320 0xfff reserved ? table 18-6. unified channel memory map uc[n] base address description location 0x00 a register (cadr[n]) on page 18-14 0x04 b register (cbdr[n]) on page 18-14 0x08 counter register (ccntr[n]) on page 18-15 0x0c control register (ccr[n]) on page 18-16 0x10 status register (csr[n]) on page 18-20 0x14 alternate a register (altcadr[n]) on page 18-21 0x18?0x1f reserved
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-9 preliminary?subject to change without notice 18.6.2 register description all control registers are 32 bits wi de. this document illustrates the emios200 with 24 unified channels and 16-bit wide data registers. 18.6.2.1 emios200 module co nfiguration register (mcr) the mcr contains global contro l bits for the emios200 block. address: emios200 base address +0x00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 mdis frz 0 0 gpre n 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpre 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-4. emios200 module c onfiguration register (mcr) table 18-7. mcr field descriptions field description mdis module disable puts the emios200 in low power mode. the mdis bit is used to stop the clock of the block, except the access to registers mcr, oudr and ucdis. 1 = enter low power mode 0 = clock is running frz freeze enable the emios200 to freeze the registers of the unified channels when debug mode is requested at mcu level. each unified channel should have fren bit set in order to enter freeze state. while in freeze state, the emios200 continues to operate to allow the mcu access to the unified channels registers. the unified channel will remain frozen until the frz bit is written to zero or the mcu exits debug mode or the unified channel fren bit is cleared. 1 = stops unified channels operation when in debug mode and the fren bit is set in the ccr[n] register 0 = exit freeze state
pxd20 microcontroller reference manual, rev. 1 18-10 freescale semiconductor preliminary?subject to change without notice 18.6.2.2 emios200 global flag register (gfr) the gfr is a read-only register that groups the flag bits from all channels. this organization improves interrupt handling on simpler devices. each bit relates to one channel. the two modules on this device, emio s0 and emios1, have the same stru cture for this re gister as shown in figure 18-5 . for unified channels these bits are mirrors of the flag bits in the csr[n] register. gpren global prescaler enable the gpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock) and prescaler counter is cleared note: prescaler must be enabled or no clock (interna l or otherwise) will be present on any channel. gpre[0:7] global prescaler the gpre[0:7] bits select the clock divider value for the global prescaler, as shown in ta b l e 1 8 - 8 . table 18-8. global prescaler clock divider gpre[0:7] divide ratio 00000000 1 00000001 2 00000010 3 00000011 4 . . . . . . . . 11111110 255 11111111 256 table 18-7. mcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-11 preliminary?subject to change without notice f[n] ? channel [n] flag bit channels that occupy a pair of slots are referred to by their lower slot number (l sb=0 standard), therefore the bits corresponding to their hi gher slot number always read 0. 18.6.2.3 emios200 output update disable (oudr) the two modules on this device, emio s0 and emios1, have the same stru cture for this re gister as shown in figure 18-6 . address: emios0 base address +0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 f23 f22 f21 f20 f19 f18 f17 f16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r f15 f14 f13 f12 f11 f10 f9 f8 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-5. emios200 globa l flag register (gfr)
pxd20 microcontroller reference manual, rev. 1 18-12 freescale semiconductor preliminary?subject to change without notice 18.6.2.4 emios200 disa ble channel (ucdis) the two modules on this device, emio s0 and emios1, have the same stru cture for this re gister as shown in figure 18-7 . address: emios0 base address +0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 ou23 ou22 ou21 ou20 ou19 ou18 ou17 ou16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ou15 ou14 ou13 ou12 ou11 ou10 ou9 ou8 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-6. emios200 output update disable register (oudr) table 18-9. oudr field descriptions field description ou[n] channel [n] output update disable bit when running mcb or an output mode, values are written to registers a2 and b2. ou[n] bits are used to disable transfers from registers a2 to a1 and b2 to b1. each bit controls one channel. 1 = transfers disabled 0 = transfer enabled. depending on the operation mode, transfer may occur immediately or in the next period. unless stated otherwise, transfer occurs immediately.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-13 preliminary?subject to change without notice address: emios0 base address +0x0c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 chdi s23 chdi s22 chdi s21 chdi s20 chdi s19 chdi s18 chdi s17 chdi s16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chdi s15 chdi s14 chdi s13 chdi s12 chdi s11 chdis 10 chdi s9 chdi s8 0 0 0 0 0 0 0 0 w reset: 0000000000000000 figure 18-7. emios200 enable channel register (ucdis) table 18-10. ucdis field descriptions field description chdis[n] enable channel [n] bit the chdis[n] bit is used to disable each of t he channels by stopping its respective clock. 1 = channel [n] disabled 0 = channel [n] enabled note: channels that occupy a pair of slots are referr ed to as by their lower slot number (lsb=0 standard), therefore the bits corresponding to their higher slot number are reserved and read 0.
pxd20 microcontroller reference manual, rev. 1 18-14 freescale semiconductor preliminary?subject to change without notice 18.6.2.5 emios200 uc a register (cadr[n]) depending on the mode of operation, in ternal registers a1 or a2, used for matches and captures, can be assigned to address cadr[n]. both a1 and a2 are cl eared by reset. figure 18-11 summarizes the cadr[n] writing and reading acces ses for all operation modes. for more information see section section 18.7.1.1, uc modes of operation. 18.6.2.6 emios200 uc b register (cbdr[n]) address: uc[n] base address + 0x00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcadr w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-8. emios200 uc a register (cadr[n]) address: uc[n] base address + 0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rcbdr w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-9. emios200 uc b register (cbdr[n])
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-15 preliminary?subject to change without notice depending on the mode of operation, in ternal registers b1 or b2 can be assigned to address cbdr[n]. both b1 and b2 are cleared by reset. table 18-11 summarizes the cbdr[n] writ ing and reading accesses for all operation modes. for mo re information see section section 18.7.1.1, uc modes of operation. 18.6.2.7 emios200 uc counter register (ccntr[n]) the ccntr[n] contains the value of the internal counter. when gpio mode is selected or the channel is frozen, the ccntr[n] is read/write. for all others m odes, the ccntr[n] is a read-only register. when entering some operation modes, this register is automa tically cleared (refer to section 18.7.1.1, uc modes of operation, for details). table 18-11. cadr[n], cbdr[n] and altcadr[n] value assignments operation mode register access write read write read alt write alt read gpio a1, a2 a1 b1, b2 b1 a2 a2 saic 1 ? a2 b2 b2 ? ? saoc 1 1 in these modes, the register cbdr[n] is not used, but b2 can be accessed. a2 a1 b2 b2 ? ? mcb 1 a2 a1 b2 b2 ? ? opwfmb a2 a1 b2 b1 ? ? opwmb a2 a1 b2 b1 ? ? qdec 1 a1 a1 b2 b2 ? ? address: uc[n] base address + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w 1 1 in gpio mode or freeze action, this register is writable. reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccntr w 1 reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-10. emios200 uc counter register (ccntr[n])
pxd20 microcontroller reference manual, rev. 1 18-16 freescale semiconductor preliminary?subject to change without notice 18.6.2.8 emios200 uc cont rol register (ccr[n]) the control register gathers bits reflecting the stat us of the uc input/output signals and the overflow condition of the internal counter, as we ll as several read/write control bits. address: uc[n] base address + 0x0c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fren odis odissl ucpre ucpr en dma 0 if fck fen 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 bsl edse l edpo l mode w forc ma forc mb reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved figure 18-11. emios200 uc control register (ccr[n]) table 18-12. ccr[n] field descriptions field description fren freeze enable bit the fren bit, if set and validated by mcr[frz], a llows the channel to enter freeze state, freezing all registers values when in debug mode and allowing the mcu to perform debug functions. 1 = freeze uc registers values 0 = normal operation odis output disable bit the odis bit allows disabling the output pin when running any of the output modes with the exception of gpio mode. 1 = if the flag is set in the channel selected by the odissl bits, the output pin goes to edpol for opwfmb and opwmb modes and to the complement of edpol for other output modes, but the unified channel continues to operate normally, i. e., it continues to produce flag and matches. when the selected output disable input signal is negated, the output pin operates normally 0 = the output pin operates normally odissl output disable select bits the odissl[0:1] bits select one of the four channels which can be used as the output disable signal, as shown in table 18-13 . ucpre prescaler bits the ucpre[0:1] bits select the clock divider value for the internal prescaler of unified channel, as shown in table 18-14 .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-17 preliminary?subject to change without notice ucpren prescaler enable bit the ucpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock)0:1 note: prescaler must be enabled or no clock (interna l or otherwise) will be present on the channel. dma direct memory access bit the dma bit selects if the flag generation will be used as an interrupt or as a dma request. 1 = flag/overrun assigned to dma request 0 = flag/overrun assigned to interrupt request if input filter bits the if[0:3] bits control the programmable input filt er, selecting the minimum input pulse width that can pass through the filter, as shown in table 18-15 . for output modes, these bits have no meaning. fck filter clock select bit the fck bit selects the clock source for the programmable input filter. 1 = main clock 0 = prescaled clock fen flag enable bit the fen bit allows the unified channel flag bit to generate an interrupt signal or a dma request signal (the type of signal to be generated is defined by the dma bit). 1 = enable (flag will generate an interrupt or dma request) 0 = disable (flag does not generate an interrupt or dma request) forcma force match a bit for output modes, the forcma bit is equivalent to a successful comparison on comparator a (except that the flag bit is not set). this bit is cleared by reset and is always read as zero. this bit is valid for every output operation mode which us es comparator a, othe rwise it has no effect. 1 = force a match at comparator a 0 = has no effect note: for input modes, the forcma bit is not used and writing to it has no effect. forcmb force match b bit for output modes, the forcmb bit is equivalent to a successful comparison on comparator b (except that the flag bit is not set). this bit is cleared by reset and is always read as zero. this bit is valid for every output operation mode which us es comparator b, otherwise it has no effect. 1 = force a match at comparator b 0 = has not effect note: for input modes, the forcmb bit is not used and writing to it has no effect. bsl bus select bits the bsl[0:1] bits are used to select either one of the counter buses or the internal counter to be used by the unified channel. refer to ta b l e 1 8 - 1 6 for details. table 18-12. ccr[n] field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 18-18 freescale semiconductor preliminary?subject to change without notice edsel edge selection bit for input modes, the edsel bit selects whether the internal counter is triggered by both edges of a pulse or just by a single edge as defined by the edpol bit. when not shown in the mode of operation description, this bit has no effect. 1 = both edges triggering 0 = single edge triggering defined by the edpol bit for gpio in mode, the edsel bit selects if a flag can be generated. 1 = no flag is generated 0 = a flag is generated as defined by the edpol bit for saoc mode, the edsel bit selects the behavi or of the output flip-flop at each match. 1 = the output flip-flop is toggled 0 = the edpol value is transferred to the output flip-flop edpol edge polarity bit for input modes (except qdec mode), the edpol bi t asserts which edge triggers either the internal counter or an input capture or a flag. when not shown in the mode of operation description, this bit has no effect. 1 = trigger on a rising edge 0 = trigger on a falling edge for qdec (mode[6] cleared), the edpol bit selects the count direction according to direction signal (uc[n] input). 1 = counts up when uc[n] is asserted 0 = counts down when uc[n] is asserted note: uc[n-1] edpol bit selects which edge clocks the internal counter of uc[n] 1 = trigger on a rising edge 0 = trigger on a falling edge for qdec (mode[6] set), the edpol bit selects the count direction according to the phase difference. 1 = internal counter increments if phase_a is ahead phase_b signal 0 = internal counter decrements if phase_a is ahead phase_b signal note: in order to operate properly, edpol bit must contain the same value in uc[n] and uc[n-1] for output modes, the edpol bit is used to select the logic level on the output pin. 1 = a match on comparator a sets the output f lip-flop, while a match on comparator b clears it 0 = a match on comparator a clears the output flip -flop, while a match on comparator b sets it mode mode selection bits the mode[0:6] bits select the mode of operation of the unified channel, as shown in table 18-17 . note: if a reserved value is written to mode the results are unpredictable. table 18-13. uc odissl selection odissl[0:1] emios0 channel emios1 channel input signal 00 emios_flag_out[8] emios_flag_out[8] output disable input 0 01 emios_flag_out[9] emios_flag_out[9] output disable input 1 10 emios_flag_out[10] emios_flag_out[10] output disable input 2 11 emios_flag_out[11] emios_flag_out[11] output disable input 3 table 18-12. ccr[n] field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-19 preliminary?subject to change without notice table 18-14. uc internal prescaler clock divider ucpre[0:1] divide ratio 00 1 01 2 10 3 11 4 table 18-15. uc input filter bits if[0:3] 1 1 filter latency is 3 clock edges. minimum input pulse width [flt_clk periods] 0000 bypassed 2 2 the input signal is synchronized befor e arriving to the digital filter. 0001 02 0010 04 0100 08 1000 16 all others reserved table 18-16. uc bsl bits bsl[0:1] selected bus 00 all channels: counter bus[a] 01 channels 8 to 15: counter bus[c] channels 16 to 23: counter bus[d] 10 reserved 11 all channels: internal counter table 18-17. uc mode bits mode 1 mode of operation 0000000 general purpose input/output mode (input) 0000001 general purpose input/output mode (output) 0000010 single action input capture 0000011 single action output compare 0000100 to 0001011 reserved 000110b quadrature decode 0001110 to 1001111 reserved 101000b modulus counter buffered (up counter)
pxd20 microcontroller reference manual, rev. 1 18-20 freescale semiconductor preliminary?subject to change without notice 18.6.2.9 emios200 uc stat us register (csr[n]) csr[n] address: uc[n ] base address + 0x10 figure 18-12. emios200 uc status register (csr[n]) 1010010 1010011 reserved 10101bb modulus counter buffered (up/down counter) 10110b0 output pulse width and frequency modulation buffered 10110b1 to 10111b1 reserved 11000b0 output pulse width modulation buffered 1100001 to 1111111 reserved 1 b = adjust parameters for the mode of operation. refer to section 18.7.1.1, uc mo des of operation, for details. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ovr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w w1c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovf l 0 0 0 0 0 0 0 0 0 0 0 0 ucin uco ut fla g w w1c w1c reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved table 18-17. uc mode bits (continued) mode 1 mode of operation
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-21 preliminary?subject to change without notice 18.6.2.10 emios200 uc alternat e a register (altcadr[n]) altcadr[n] address: uc [n] base address + 0x14 figure 18-13. emios200 uc alte rnate a register (altcadr[n]) the altcadr[n] provides an alternate address to access a2 channel registers in restri cted modes (gpio) only. if cadr[n] is used along with altcadr[n], both a1 and a2 registers can be accessed in these modes. table 18-11 summarizes the altcadr[n] writing and reading accesse s for all operation modes. table 18-18. csr[n] field descriptions field description ovr overrun bit. the ovr bit indicates that flag generation occurred when the flag bit was already set. 1 = overrun has occurred 0 = overrun has not occurred ovfl overflow bit. the ovfl bit indicates that an over flow has occurred in the inte rnal counter. ovfl must be cleared by software writing a 1 to the ovflc bit. 1 = an overflow has occurred 0 = no overflow ucin unified channel input pin bit. the ucin bit reflects the input pin state after being filtered and synchronized. ucout unified channel output pin bit. the ucout bit reflects the output pin state. flag flag bit. the flag bit is set when an input capture or a match event in the comparators occurred. 1 = flag set event has occurred 0 = flag cleared note: emios_flag_out reflects the flag bit value. when dma bit is set, the flag bit can be cleared by the dma controller. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r altcadr w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented or reserved
pxd20 microcontroller reference manual, rev. 1 18-22 freescale semiconductor preliminary?subject to change without notice 18.7 functional description the emios200 provides i ndependent channels (uc) that can be configured and accessed by a host mcu. up to three time bases can be shared by the cha nnels through three counter buses and each channel can generate its own time base. the emios200 module is based on a mult i-bus timer architecture in which several timer channels are used to drive counter buses that are shared among the channels. there are 3 counter buses in the module: ? one global counter bus, shared by all channels ? two 2 local counter buses, each one dedicated to a slice of 8 channels counter bus a is referred to as th e global counter bus. counter buses c and d are the local counter buses. the emios200 counter buses ar e driven by channels in specific locati ons. the global count er bus is driven by the channel in channel slot [23] . counter buses c and d are driven by channels in slots [8] and [16], respectively. counter bus a drives all channels. counter bus c drives channels in slots from [8] through [15]. counter bus d drives channels in slots from [16] through [23]. no te that the first channel in an 8-channel slice drives the local count er bus for that slice, therefore th is channel should not be assigned to be driven by the same counter bus , otherwise a loop occurs. the emio s200 interrupt request signal, dma transfer request signal among others, are wired to a sp ecific channel, thus the chip integrator should connect those signals having the emio s200 channel configuration in mind. the emios200 block is reset asynchronously . all registers ar e cleared on reset. figure 18-15 describes an emios200 block c onfigured with 32 unified cha nnels. note that the redline is also present. note also that independent of the c onfiguration the channels are fixed in their slots, thus for example if channel [2] is not required this locat ion will be empty, meaning that the other channels locations are not affected. in this cas e the application software should not access any re gister located in the channel[2] memory. any attempt to access those regist ers will return no meaningful data and a transfer error will be generated.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-23 preliminary?subject to change without notice figure 18-14. emios prescalers divide by emios global prescaler of 1 to 256 (gpre) auxiliary clock 1/2 emios internal counter clock 24-bit counter cnt[0] divide by channel prescaler of 1 to 4 (ucpre) unified channel prescaler enable (ucpren) channel 8 ? ? ? 24-bit counter cnt[23] divide by channel prescaler of 1 to 4 (ucpre) unified channel prescaler enable (ucpren) channel 23 global prescaler enable (gpren)
pxd20 microcontroller reference manual, rev. 1 18-24 freescale semiconductor preliminary?subject to change without notice figure 18-15. emios200 full channel configuration using unified channels only 18.7.1 unified channel (uc) each unified channel consists of: ? counter bus selector, which selects the time base to be used by the channel for all timing functions ? a programmable clock prescaler channel[23] channel[16] channel[15] channel[8] bus [d] bus [c] global counter bus [a] emios[15] emios[8] emios[23] emios[16] output disable inputs[3:0] biu all global prescaler all system ip clock global regs interface output disable bus[3:0] enhanced modular i/o subsystem emios200 channels channels (source for internal counter)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-25 preliminary?subject to change without notice ? two double buffered data registers a and b that allow up to two input capture and/or output compare events to occur before software intervention is needed. ? two comparators (equal only) a and b, which compares the selected counter bus with the value in the data registers ? internal counter, which can be used as a local time base or to count input events ? programmable input filter, which ensures that only valid pin transitions are received by channel ? programmable input edge de tector, which detects the ri sing, falling or either edges ? an output flip-flop, which holds the logic level to be applied to the output pin ? emios200 status and control register ? an output disable input selector that selects which channels flag signal will be used as output disable for the current channel figure 18-16 shows both the unified channel control and datapath block di agram. the control block is responsible for the generation of signa ls to control the multiplexes in the datapath sub-block. each mode is implemented by a dedicated logic independent from others modes, t hus allowing to optimize the logic by disabling the mode and therefore its associated logic. the unused gates are removed during the synthesis phase. targeting the logic optimization a set of registers is shared by the modes thus providing sequential events to be stored. the datapath block provides the channel a and b regi sters, the internal time base and comparators. multiplexors select the input of comp arators and data for the registers inputs, thus c onfiguring the datapath in order to implement the channel m odes. the outputs of a and b compar ators are connected to the uc_ctrl control block.
pxd20 microcontroller reference manual, rev. 1 18-26 freescale semiconductor preliminary?subject to change without notice figure 18-16. unified channel control and datapath block diagrams 18.7.1.1 uc modes of operation the mode of operation of the unified channel is dete rmined by the mode select bits mode[0:6] in the ccr[n] (see figure 18-17 for details). when entering an output mode (except for gpio mode), the output flip-flop is set to disabled state according to odis bit in the ccr[n]. as the internal counter ccntr[n] continues to run in all modes (except for gpio mode), it is possible to use this as a time base if the resour ce is not used in the current mode. in order to provide smooth waveform generation even if a and b registers are ch anged on the fly, in the mcb, opwfmb, and opwmb the a an d b registers are double buffered. a2 b2 b1 a1 cnt local counter bus global counter bus[a] a comparator bsl[0] bsl[1]+logic bsl[1]+logic bsl[1]+logic internal counter [c/d] b comparator uc_datapath uc_ctrl control signals input filter input mode 0 logic general purpose registers mode 1 logic mode n logic mode decoder mode register == ==
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-27 preliminary?subject to change without notice 18.7.1.1.1 general purpose i nput/output mode (gpio) mode in gpio mode, all input capture and output compare functions of the uc are disabled, the internal counter (ccntr[n]) is cleared and disabled. all control bits remain accessible. in order to prepare the uc for a new operation mode, writing to cadr[n ] or cbdr[n] stores th e same value in regi sters a1/a2 or b1/b2, respectively. writing to altcadr[n] st ores a value only in register a2. mode[6] bit selects between input (mode[6] = 0) and output (mode[6] = 1) modes. caution when changing mode[0:6], the appli cation software must go to gpio mode first in order to reset the uc?s internal functions properly. failure to do this could lead to in valid and unexpected output compare or input capture results or the flags being set incorrectly. in gpio input mode (mode[0:6]=0000000), the flag generation is determined according to edpol and edsel bits and the input pin status ca n be determined by reading the ucin bit. in gpio output mode (mode[0:6]=0000001), the unified channel is used as a single output port pin and the value of the edpol bit is permanen tly transferred to the output flip-flop. 18.7.1.1.2 single action in put capture (saic) mode in saic mode (mode[0:6]=0000010), when a triggeri ng event occurs on the i nput pin, the value on the selected time base is captured into register a2. the flag bit is set along with the capture event to indicate that an input capture has occurred. cadr[n] returns th e value of register a2. as soon as the saic mode is entered coming out from gpio mode the channel is ready to capture events. the events are captured as soon as they occur thus read ing register a always returns the value of the latest captured event. subsequent captures are enabled with no need of further reads from cadr[n]. the flag is set at any time a new event is captured. the input capture is triggered by a rising, falling or either edges in the input pin, as configured by the edpol and edsel bits in ccr[n]. figure 18-17 and figure 18-18 shows how the unified channel can be used for input capture. figure 18-17. single action input capture with rising edge triggering example selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 flag pin/register a2 (captured) value 2 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edge detect edge detect edge detect notes: 1. after input filter 2. cadr[n] <= a2 edsel = 0 edpol = 1
pxd20 microcontroller reference manual, rev. 1 18-28 freescale semiconductor preliminary?subject to change without notice figure 18-18. single action i nput capture with both edges triggering example 18.7.1.1.3 single action out put compare (saoc) mode in saoc mode (mode[0:6]=0000011) a match value is loaded in regi ster a2 and then immediately transferred to register a1 to be compared with the selected time ba se. when a match occurs, the edsel bit selects whether the output flip-fl op is toggled or the value in edpo l is transferred to it. along with the match the flag bit is set to indicate that th e output compare match has o ccurred. writing to cadr[n] stores the value in register a2 and reading to cadr[n] returns the value of register a1. an output compare match can be simulated in softwa re by setting the forcma bit in ccr[n]. in this case, the flag bit is not set. when saoc mode is entered coming out from gpio mo de the output flip-flop is set to the complement of the edpol bit in ccr[n]. counter bus can be either internal or extern al and is selected th rough bsl[0:1] bits. figure 18-19 and figure 18-20 show how the unified channel can be used to perform a single output compare with edpol value being transferred to the output flip-flop and toggli ng the output flip-flop at each match, respectively. note that once in saoc m ode the matches are enabled thus the desired match value on register a1 must be written before the mode is entered. a1 register can be updated at any time thus modifying the match value which will reflect in the output signal generated by the channel. subsequent matches are enabled with no need of furthe r writes to cadr[n]. the fl ag is set at the same time a match occurs. note the channel internal counter in sa oc mode is free-running. it starts counting as soon as the saoc mode is entered. selected counter bus 0x001000 0x001102 flag set event a2 (captured) value 2 0xxxxxxx 0x001000 input signal 1 edge detect notes: 1. after input filter 2. cadr[n] <= a2 0x001103 0x001108 0x001104 0x001105 0x001106 0x001107 0x001001 flag pin/register edge detect flag clear edge detect 0x001103 0x001108 edsel = 1 edpol = x
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-29 preliminary?subject to change without notice figure 18-19. saoc example with edpol value being transferred to the output flip-flop figure 18-20. saoc example toggling the output flip-flop 18.7.1.1.4 modulus counter buffered (mcb) mode the mcb mode provides a time base which can be shared with other ch annels through the internal counter buses. register a1 is double buffere d thus allowing smooth transitions between cycles when changing a2 register value on the fly. a1 register is updated at th e cycle boundary, which is defined as when the internal counter transitions to 0x1. the internal counter values operates within a range from 0x1 up to register a1 value. if when entering mcb mode coming out from gpio mode the internal counter value is not within that range then the a match will not occur causing the channe l internal counter to wrap at th e maximum counter value which is 0xff_ffff for a 24-bit c ounter. after the counter wrap occurs it returns to 0x1 and resume normal mcb mode operation. thus in order to avoid the counter wr ap condition make sure its value is within the 0x1 to a1 register value range when the mcb mode is entered. selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 output flip-flop update to a1 a1 value 1 0xxxxxxx 0x001000 flag pin/register 0x001000 0x001000 0x001000 a1 match a1 match a1 match notes: 1. cadr[n] = a2 edsel = 0 edpol = 1 a2 = a1 according to ou[n] bit selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 a1 value 1 0xxxxxxx 0x001000 output flip-flop update to a1 flag pin/register a1 match a1 match a1 match 0x001000 0x001000 0x001000 notes: 1. cadr[n] = a2 edsel = 1 edpol = x a2 = a1 according to ou[n] bit selected counter bus 0x0 0x2 flag set event a2 value 1 0x1 output flip-flop note: 1. cadr[n] <= a2 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock a1 match edpol = x
pxd20 microcontroller reference manual, rev. 1 18-30 freescale semiconductor preliminary?subject to change without notice mode[6] bit selects internal clock source if cleared or external if set. when exte rnal clock is selected the input channel pin is used as the channel clock source. the active edge of this clock is defined by edpol and edsel bits in ccr[n]. when entering in mcb mode, if up counter is selected by mode[4]=0 (mode[0:6]=101000b), the internal counter starts c ounting from its current value to up direct ion until a1 match occurs. the internal counter is set to 0x1 when its value matches a1 value and a clock tick occurs (either prescaled clock or input pin event). if up/down counter is selected by setting mode[4]= 1, the counter changes dire ction at a1 match and counts down until it reaches the valu e 0x1. after it has reache d 0x1 it is set to count in up direction again. b1 register is used to generate a match in order to set the internal c ounter in up-count di rection if up/down mode is selected. register b1 cannot be changed while this mode is selected. note that the mcb mode counts betw een 0x1 and a1 register value. only values greater than 0x1 must be written at a1 register. loading values other than th ose leads to unpredictable results. the counter cycle period is equal to a1 value in up counter mode. if in up/down counter mode the period is defined by the expression: (2*a1)-2. figure 18-21 describes the counter cycle for several a1 valu es. register a1 is loaded with a2 register value at the cycle boundary. thus any value written to a2 register within cycle n will be updated to a1 at the next cycle boundary and ther efore will be used on cycle n+1 . the cycle boundary between cycle n and cycle n+1 is defined as when the internal count er transitions from a1 value in cycle n to 0x1 in cycle n+1 . note that the flag is generated at the cycle boundary and has a s ynchronous operation, meaning that it is asserted one system clock cycle after the flag set event. figure 18-21. modulus counter buffered (mcb) up count mode figure 18-22 describes the mcb in up/down counter mo de (mode[0:6]=10101bb) . a1 register is updated at the cycle boundary. if a2 is written in cycle n , this new value will be used in cycle n+1 for a1 match. flags are generated on ly at a1 match start if mode[5] is 0. if mode[5] is set to 1 flags are also generated at the cycle boundary. emioscnt[n] time write to a2 match a1 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n cycle n+1 cycle n+2 flag clear
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-31 preliminary?subject to change without notice figure 18-22. modulus counter buffered (mcb) up/down mode figure 18-23 describes in more detail the a1 register update process in up counter mode. the a1 load signal is generated at the last syst em clock period of a counter cycle. thus, a1 is updated with a2 value at the same time that the counter (ccntr[n]) is loaded with 0x1. the load signal pulse has the duration of one system clock period. if a2 is written within cycle n its value is available at a1 at the first clock of cycle n+1 and the new value is us ed for match at cycle n+1 . the update disable b its ou[n] of oudr can be used to control the update of this register, t hus allowing to delay the a1 register update for synchronization purposes. figure 18-23. mcb mode a1 register update in up counter mode figure 18-24 describes the a1 register update in up/down co unter mode. note that a2 can be written at any time within cycle n in order to be used in cycle n+1 . thus a1 receives this new value at the next cycle boundary. note that the update disabl e bits ou[n] of oudr can be used to disable the update of a1 register. emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n+1 cycle n+2 cycle n flag clear a1 value 0x000008 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000008 0x000004 0x000006 0x000002 0x000004 0x000006 write to a2 write to a2 match a1 match a1 a1 load signal 8 4 6 match a1 counter = a1 time cycle n cycle n+1 cycle n+2 prescaler ratio = 2
pxd20 microcontroller reference manual, rev. 1 18-32 freescale semiconductor preliminary?subject to change without notice figure 18-24. mcb mode a1 register update in up/down counter mode 18.7.1.1.5 output pulse wi dth and frequency modulatio n buffered (opwfmb) mode this mode (mode[0:6]=10110b0) provides waveforms with variable duty cycle and frequency. the internal channel counter is automatica lly selected as the time base when this mode is selected. a1 register indicates the duty cycle and b1 register the frequenc y. both a1 and b1 registers are double buffered to allow smooth signal generation when changing the regi sters values on the fly. 0% and 100% duty cycles are supported. at opwfmb mode entry the output flip-flop is se t to the value of the edpol bit in the ccr[n]. if when entering opwfmb mode co ming out from gpio mode the intern al counter value is not within that range then the b match will not occur causing th e channel internal counter to wrap at the maximum counter value which is 0xff_ffff for a 24-bit c ounter. after the counter wrap occurs it returns to 0x1 and resume normal opwfmb mode operation. thus in orde r to avoid the counter wrap condition make sure its value is within the 0x1 to b1 register va lue range when the opwfmb mode is entered. when a match on comparator a occurs the output register is set to the value of edpol. when a match on comparator b occurs the output register is set to th e complement of edpol. b1 match also causes the internal counter to transition to 0x1, thus restarting the counter cycle. only values greater than 0x1 are allowed to be written to b1 register. loading valu es other than those leads to unpredictable results. figure 18-25 describes the operation of the opwfmb mode regarding output pin transitions and a1/b1 registers match events. note that the output pin tran sition occurs when the a1 or b1 match signal is deasserted which is indicated by the a1 match negedge detection signal. if register a1 is set to 0x4 the output pin transitions 4 count er periods after the cycle had started, plus one system clock cycle. note that in the example shown in figure 18-25 the internal counter prescaler has a ratio of two. a1 value 0x000006 a2 value 0x000006 0x000005 0x000006 0x000005 a1 load signal counter = 2 emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000006 cycle n cycle n+1 cycle n+2 prescaler ratio = 2
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-33 preliminary?subject to change without notice figure 18-25. opwfmb a1 and b1 match to output register delay figure 18-26 describes the generated output signal if a1 is set to 0x0. since the counter does not reach zero in this mode, the channel internal logic infers a match as if a1=0x1 with the difference that in this case, the posedge of the matc h signal is used to trigge r the output pin transition in stead of the negedge used when a1=0x1. note that a1 pos edge match signal from cycle n+1 occurs at the same time as b1 negedge match signal from cycle n . this allows to use the a1 posedge match to mask the b1 negedge match when they occur at the same time. the result is that no tr ansition occurs on the output flip-flop and a 0% duty cycle is generated. figure 18-26. opwfmb mode with a1 = 0 (0% duty cycle) 8 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler prescaler ratio = 2 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection no transition at this point 1 cycle n cycle n+1 prescaler ratio = 2
pxd20 microcontroller reference manual, rev. 1 18-34 freescale semiconductor preliminary?subject to change without notice figure 18-27 describes the timing for the a1 and b1 register s load. the a1 and b1 load use the same signal which is generated at the last sy stem clock period of a counter cy cle. thus, a1 and b1 are updated respectively with a2 and b2 values at the same time that the counter (ccntr[n]) is loaded with 0x1. this event is defined as the cycle boundary. the load signa l pulse has the duration of one system clock period. if a2 and b2 are written within cycle n their values are available at a1 and b1, respectively, at the first clock of cycle n+1 and the new values are used for matches at cycle n+1 . the update disable bits ou[n] of oudr can be used to control the update of these registers, thus allowing to delay the a1 and b1 registers update for synchronization purposes. in figure 18-27 it is assumed that both the channel and global prescalers ar e set to 0x1 (each divide ratio is two), meaning that the channel internal counter tr ansitions at every four sy stem clock cycles. flags can be generated only on b1 matches when mode[5] is cleared, or on both a1 and b1 matches when mode[5] is set. since b1 flag occurs at the cycle bounda ry, this flag can be used to indicate that a2 or b2 data written on cycle n were loaded to a1 or b1, respectiv ely, thus generating matches in cycle n+1 . note that the flag has a synchronous operation, meaning that it is assert ed one system cl ock cycle after the flag set event. figure 18-27. opwfmb a1 and b1 registers update and flags figure 18-28 describes the operation of the output disable feat ure in opwfmb mode . the output disable forces the channel output flip-flop to edpol bit value. this functionali ty targets applications that use active high signals and a high to low transition at a1 match. in this ca se edpol should be set to 0. note that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that the channel internal counter transiti ons at every system clock cycle. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value 1 b1 value b2 value 0x8 0x2 0x6 0x8 0x1 internal counter 0x4 0x6 mode [6] = 1 a2 value 1 0x2 0x4 0x6 0x2 0x4 0x6 0x8 0x6 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 a1/b1 load signal due to b1 match cycle n-1 flag set event flag pin/register prescaler ratio = 4 flag clear
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-35 preliminary?subject to change without notice figure 18-28. opwfmb mode with active output disable note that the output disabl e has a synchronous operation, meaning that the assertion of th e output disable input pin causes the channel output flip-flop to transition to edpol at the next system clock cycle. if the output disable input is deasserted the output pin transition at the following a1 or b1 match. in figure 18-28 it is assumed that the output disable input is enabled and selected for the channel. see section 18.6.2.8, emios200 uc control register (ccr[n]), for a detailed description about the odis and odissl bits, respectively enable and se lection of the output disable inputs. the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on comparators a or b respectively. simi larly to a b1 match forcmb sets the internal counter to 0x1. the flag bit is not set by the forcma or forcmb bits being asserted. figure 18-29 describes the generation of 100% and 0% duty cycle signals. it is assumed edpol =0 and the resultant prescaler valu e is 1. initially a1= 0x8 and b1=0x8. in this case, b1 match has precedence over a1 match, thus the output flip-flop is set to the comp lement of edpol bit. this cycle corresponds to a 100% duty cycle signal. the same out put signal can be generated for any a1 value greater or equal to b1. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 internal counter 0x000004 0x000006 mode [6] = 1 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 due to b1 match cycle n-1 flag set event output disable flag pin/register prescaler ratio = 1 flag set event
pxd20 microcontroller reference manual, rev. 1 18-36 freescale semiconductor preliminary?subject to change without notice figure 18-29. opwfmb mode from 100% to 0% duty cycle a 0% duty cycle signal is gene rated if a1=0x0 as shown in figure 18-29 cycle 9. in this case b1=0x8 match from cycle 8 occurs at the same ti me as the a1=0x0 match from cycle 9. see figure 18-26 for a description of the a1 and b1 match generation. in this case a1 match has precedence over b1 match and the output signal transitions to edpol. 18.7.1.1.6 output pulse width m odulation buffered (opwmb) mode opwmb mode (mode[0:6]=11000b0) is used to genera te pulses with programma ble leading and trailing edge placement. an external counter driven in mcb up mode or opwfmb mode must be selected from one of the counter buses. a1 register value defines the first edge and b1 the second edge. the output signal polarity is defined by the edpol bit. if edpol is zero, a negative edge occurs when a1 matches the selected counter bus; and a posit ive edge occurs when b1 matc hes the selected counter bus. the a1 and b1 registers are double buffered and updated from a2 and b2, respectively, at the cycle boundary. the load operation is similar to the opwfmb mode. see figure 18-27 for more information about a1 and b1 registers update. flag can be generated at b1 matches, when mode[5 ] is cleared, or in both a1 and b1 matches, when mode[5] is set. if subsequent matches occur on co mparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a1 or b1 respectively. flag bi t is not set by the forcma and forcmb operations. at opwmb mode entry the output flip-flop is se t to the value of the edpol bit in the ccr[n]. following are described some rule s applicable to the opwmb mode: ? b1 matches have precedence over a1 matches if they occur at the same time within the same counter cycle ? a1=0 match from cycle n has precedence over b1 match from cycle n-1 ? a1 matches are masked out if they occur after b1 match within the same cycle ? any value written to a2 or b2 on cycle n is loaded to a1 and b1 re gisters at the following cycle boundary (assuming ou[n] bit of oudr is not asserted). thus the new values will be used for a1 and b1 matches in cycle n+1 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% emioscnt edpol = 0 a1 value b1 value output pin 0x000008 prescaler ratio = 1 cycle 1cycle 2cycle 3cycle 4cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value 0x000008 0x000001
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-37 preliminary?subject to change without notice figure 18-30 describes the operation of the opwmb mode regarding a1 and b1 matches and the transition of the channel output pin. in this example edpol is set to zero. figure 18-30. opwmb mode matches and flags note that the output pin transiti ons are based on the negedges of the a1 and b1 match signals. figure 18-30 shows in cycle n+1 the value of a1 register being set to zero. in th is case the match posedge is used instead of the negedge to transition the output flip-flop. figure 18-31 describes the channel operation for 0% duty cy cle. note that the a1 match posedge signal occurs at the same time as the b1=0x8 negedge si gnal. in this case a1 match has precedence over b1 match, causing the output pin to rema in at edpol bit value, thus generating a 0% duty cycle signal. 1 4 match a1 negedge detection 6 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000006 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 6 flag set event selected counter bus flag pin/register
pxd20 microcontroller reference manual, rev. 1 18-38 freescale semiconductor preliminary?subject to change without notice figure 18-31. opwmb mode with 0% duty cycle figure 18-32 describes the operation of the opwmb mode wi th the output disable signal being asserted. the output disable forces a transition in the output pin to the edpol bit value. after deasserted, the output disable allows the output pin to transition at the following a1 or b1 match. note that the output disable does not modify the flag b it behavior. note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to edpol. 1 4 match a1 negedge detection 8 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 selected time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 counter bus flag set event flag pin/register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-39 preliminary?subject to change without notice figure 18-32. opwmb mode with active output disable figure 18-33 shows a waveform changing from 100% to 0% duty cycle. edpol in this case is zero. in this example b1 is programmed to the same value as the period of the external selected time base. figure 18-33. opwmb mode from 100% to 0% duty cycle in figure 18-33 if b1 is set to a value lower than 0x8 it is not possible to achieve 0% duty cycle by only changing a1 register value. since b1 matches have precedence ove r a1 matches the out put pin transitions to the opposite of edpol bit at b1 match. note also that if b1 is set to 0x9, for inst ance, b1 match does not occur, thus a 0% duty cycle signal is generated. 18.7.1.1.7 quadratur e decode (qdec) mode quadrature decode mode uses uc[n] operating in qdec mode and the input pr ogrammable filter (ipf) from uc[n-1]. note that uc[n-1] can be configured, at the same time, to an operation mode that does not edpol = 0 cycle n cycle n+1 cycle n+2 a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 selected 0x000004 0x000006 mode [6] = 1 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 due to b1 match cycle n-1 flag set event output disable counter bus flag pin/register flag clear 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% selected edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1cycle 2cycle 3cycle 4cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 counter bus 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value
pxd20 microcontroller reference manual, rev. 1 18-40 freescale semiconductor preliminary?subject to change without notice use i/o pins, such as mc mode (m odulus counter). the connection among the ucs is circular, i.e., when uc[0] is running in qdec mode, the input progr ammable filter from uc [23] is being used. this mode generates a flag every tim e the internal counter matches a1 register. the internal counter is automatically selected and is not cleared when entering this mode. mode[6] bit selects which type of encoder will be used: count & direction encoder or phase_a & phase_b encoders. when operating with count & direction encoder (mode[6] cleared), uc[n ] input pin must be connected to the direction signal and uc[n-1] input pin must be connected to the count signal of the quadrature encoder. uc[n] edpol bit select s count direction according to direction signal and uc[n-1] edpol bit selects if the internal counter is cloc ked by the rising or falling edge of the count signal. when operating with phase_a & phase_b encoder (mode[6] set), uc[n] i nput pin must be connected to the phase_a signal and uc[n-1] input pin must be connected to the phase_b signal of the quadrature encoder. edpol bit selects the count directio n according to the phase difference between phase_a & phase_b signals. figure 18-34 and figure 18-35 show two unified channels configur ed to quadrature decode mode for count & direction encoder and phase_a & phase_b encoders, respectively. figure 18-34. quadrature decode mode example with count & direction encoder notes: 1. cadr[n] => a1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 -1 -1 -1 -1 -1 ccntr[n] inc/dec direction (from uc[n]) count (from uc[n-1]) 0x000000 ccntr[n] time a1 write a1 match flag pin/register a1 match value 1 (value 1) mode [6] = 0 edpol = 1 + 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-41 preliminary?subject to change without notice figure 18-35. quadrature de code mode example with phase_a & phase_b encoder 18.7.1.2 input programmable filter (ipf) the ipf ensures that only valid i nput pin transitions are received by the unified channel edge detector. a block diagram of the ipf is shown in figure 18-36 . the ipf is a 5-bit programmable up counter that is in cremented by the selected clock source, according to bits if[0:3] in ccr[n]. figure 18-36. lnput programmable filter submodule diagram the input signal is synchronized by sy stem clock. when a state change occurs in this signal, the 5-bit counter starts counti ng up. as long as the new state is stable on the pin, the counter remains incrementing. if a counter overflows occurs , the new pin value is valida ted. in this case, it is transmitted as a pulse edge to the edge detector. if the opposite edge appears on the pin before validation (o verflow), the counter is reset. at the next pin tran sition, the counter starts coun ting again. any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge de tector. a timing diagram of the input filter is shown in figure 18-37 . notes: 1. cadr[n] = a1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 -1 -1 -1 -1 -1 + 1 + 1 + 1 + 1 + 1 + 1 -1 ccntr[n] inc/dec phase a (from uc[n]) phase b (from uc[n-1]) 0x000000 ccntr[n] time a1 write a1 match flag pin/register a1 match a1 match a1 match a1 match a1 write value 2 value 1 (value 1) (value 2) mode [6] = 1 -1 + 1 + 1 -1 -1 -1 -1 -1 + 1 + 1 + 1 + 1 + 1 + 1 -1 -1 + 1 if3 filter out ipg_clk prescaled clock if2 if1 if0 clk fck emiosi 5-bit up counter synchronizer clock
pxd20 microcontroller reference manual, rev. 1 18-42 freescale semiconductor preliminary?subject to change without notice figure 18-37. input programmable filter example the filter is not disa bled during freeze state. 18.7.1.3 clock prescaler (cp) the cp divides the gcp output signal to generate a cl ock enable for the internal counter of the unified channels. the gcp output signal is prescaled by the value defined in figure 18-14 according to the ucpre[0:1] bits in ccr[ n]. the prescaler is enabled by setting the ucpren bit in the ccr[n] and can be stopped at any time by cl earing this bit, thereby stopping the inte rnal counter in the unified channel. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write 0 at both mcr[gpren] and ucpren bit in ccr[n], thus disabling prescalers; 2. write the desired value fo r prescaling rate at ucpr e[0:1] bits in ccr[n]; 3. enable channel prescaler by writ ing 1 at ucpren bit in ccr[n]; 4. enable global prescaler by setting mcr[gpren]. the prescaler is not disa bled during freeze state. 18.7.1.4 effect of freeze on the unified channel when in debug mode, mcr[fr z] and the fren bit in the ccr[n] are both set, the internal counter and unified channel capture and compar e functions are halted. the uc is frozen in its current state. during freeze, all registers are accessi ble. when the unified channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. note that for input modes, any i nput events that may occur while the channel is frozen are ignored. when exiting debug mode or freeze enable bit is clear ed (mcr[frz] or fren in the ccr[n]) the channel actions resume, but may be inconsistent until channel enters gpio mode again. 18.7.2 global clock prescaler submodule (gcp) the gcp divides the system clock to generate a clock for the cps of the channels. the main clock signal is prescaled by the value defined in figure 18-8 according to the gpre[0:7] bits in mcr. the global time selected clock emiosi 5-bit counter filter out if [0:3] = 0010
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-43 preliminary?subject to change without notice prescaler is enabled by setting the mc r[gpren] bit and can be stopped at any time by clea ring this bit, thereby stopping the internal counters in all the channels. in order to ensure safe working and avoid glitches the following steps must be performed whenever any updtate in the prescali ng rate is desired: 1. write mcr[gpren] = 0, thus disabling global prescaler; 2. write the desired value for prescali ng rate at gpre[0:7] bits in mcr; 3. enable global prescaler by setting mcr[gpren]. the prescaler is not disa bled during freeze state. 18.7.2.1 effect of freeze on the gcp when the mcr[frz] bit is set and the module is in debug mode, the operation of gcp submodule is not affected, i.e., there is no free ze function in this submodule. 18.8 initialization/application information on resetting the emios200 the unified channels enter gpio input mode. 18.8.1 considerations before changing an operating mode, the uc must be programmed to gpio mode and cadr[n] and cbdr[n] must be updated with the correct values fo r the next operating mode. then the ccr[n] can be written with the new operating mode. if a uc is ch anged from one mode to another without performing this procedure, the first operation cycl e of the selected time base can be random, i.e., matches can occur in random time if the contents of cadr[n] or cbdr[n] were not update d with the correct value before the time base matches the previous contents of cadr[n] or cbdr[n]. when interrupts are enabled, the software must clear the flag bits before exi ting the interrupt service routine. 18.8.2 application information correlated output signals can be generated by all output operation modes. bi ts ou[n] of oudr can be used to control the update of these output signals. in order to guarantee that the inte rnal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before en abling the global prescaler. if the internal prescalers are set after enabling the global presca ler, the internal counters may increment in the same ratio, but at a different clock cycle. it is recommended to drive output disable input si gnals with the emios_fla g_out signals of some ucs running in saic mode. when an out put disable condition happens, the so ftware interrupt routine must service the output channels before servicing the channels running saic. this procedure avoid glitches in the output pins.
pxd20 microcontroller reference manual, rev. 1 18-44 freescale semiconductor preliminary?subject to change without notice 18.8.2.1 time ba se generation for the opwfm with internal clock source operation m ode, the internal counter rate can be modified by configuring the clock prescaler ratio. figure 18-38 shows an example of a time base with prescaler ratio equal to one. note mcb and opwfmb modes have a different behavior. figure 18-38. time base period when running in the fastest prescaler ratio if the prescaler ratio is greater than one or external clock is selected, the c ounter may behave in three different ways dependi ng on the channel mode: ? if mc mode and clear on match start and external clock sour ce are selected the internal counter behaves as described in figure 18-39 . ? if mc mode and clear on match start and internal clock source are selected the internal counter behaves as described in figure 18-40 . ? if mc mode and clear on match end are selected the internal counter behaves as described in figure 18-41 . ? if opwfm mode is selected the intern al counter behaves as described in figure 18-40 . the internal counter clears at the star t of the match signal, skips the ne xt prescaled clock edge and then increments in the subsequent prescaled clock edge. note mcb and opwfmb modes have a different behavior. system clock input event/prescaler clock enable = 1 internal counter match value = 3 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 pre scaled clock ratio = 1 (bypassed) see note 1 flag set event note 1: when a match occurs, the first clock cycle is used to clear the internal counter, starting another period. flag pin/register flag clear
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 18-45 preliminary?subject to change without notice figure 18-39. time base generation with external clock and clear on match start figure 18-40. time base generation with internal clock and clear on match start figure 18-41. time base generation with clear on match end system clock input event internal counter match value = 3 1 2 3 0 see note 1 note 1: when a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge of prescaler clock enable 1 2 the counter will start counting. 1 2 3 0 flag set event flag clear flag pin/register system clock prescaler clock enable internal counter match value = 3 0 1 3 0 2 0 3 0 prescaled clock ratio = 3 see note 1 note 1: when a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of pre scaled clock 1 2 the counter will start counting. flag set event flag clear flag pin/register system clock input event/prescaler clock enable internal counter match value = 3 0 1 3 2 0 prescaled clock ratio = 3 see note 1 note 1: the match occurs only when the input event/prescaler clock enable is active. then, the internal counter is immediately cleared. 1 2 3 flag set event flag clear flag pin/register
pxd20 microcontroller reference manual, rev. 1 18-46 freescale semiconductor preliminary?subject to change without notice 18.8.2.2 coherent accesses the flag set event can be detected by polling the fl ag bit or by enabling the interrupt or dma request generation. reading the cadr[n] again in the same period of the last read of cbdr[n] may lead to incoherent results. this will occur if the last read of cbdr[n] occurred after a disabled b2 to b1 transfer. 18.8.2.3 channel/modes initialization the following basic steps summarize basic output mode startup, assuming the cha nnels are initially in gpio mode: 1. [global] disable global prescaler; 2. [timebase channel] disable channel prescaler; 3. [timebase channel] write initial value at internal counter; 4. [timebase channel] set a/b register; 5. [timebase channel] set channel to mc(b) up mode; 6. [timebase channel] set prescaler ratio; 7. [timebase channel] enable channel prescaler; 8. [output channel] disable channel prescaler; 9. [output channel] set a/b register; 10. [output channel] select timebase input through bsl[1:0] bits; 11. [output channel] enter output mode; 12. [output channel] set prescaler ratio (same ratio as timebase channel); 13. [output channel] enable channel prescaler; 14. [global] enable global prescaler. the timebase channel and the output channel may be the same for some applications such as in opwfm(b) mode or whenever the output channe l is intended to run the timebase itself. at any time the flags can be configured.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-1 preliminary?subject to change without notice chapter 19 error correction status module (ecsm) 19.1 introduction the error correction status module (e csm) provides a myriad of miscel laneous control functions for the device including program-visible info rmation about configuration, a rese t status register, and optional features such as information on memory errors re ported by error-correcting c odes. its supervisor-mode access protection feature provides access protection for slave modules intc, ecsm, mpu, pram2p, stm, and swt. 19.2 overview the error correction status module is mapped into the ips space and s upports a number of miscellaneous control functions for the device. 19.3 features the ecsm includes these features: ? program-visible information on th e device configurat ion and revision ? optional registers for capturing information on memory errors if error-correcting codes (ecc) are implemented ? optional registers to specify the generation of si ngle- and double-bit memory data inversions for test purposes if error-correcting codes are implemented ? spp_ips_reg_protection provides privileged-only ac cess to selected on-plat form slave devices: intc, ecsm, mpu, stm, and swt. 19.4 memory map and register description 19.4.1 memory map table 19-1 provides the register map of the ecsm. table 19-1. ecsm memory map address offset register location 0x00?0x20 reserved 0x24 miscellaneous user-defined control register (mudcr) on page 19-2 0x28?0x42 reserved 0x43 ecc configuration register (ecr) on page 19-4 0x44?0x46 reserved 0x47 ecc status register (esr) on page 19-5
pxd20 microcontroller reference manual, rev. 1 19-2 freescale semiconductor preliminary?subject to change without notice 19.4.2 register description attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. unle ss noted otherwise, writes to the programming model must match the size of the register, e.g., an n-bit re gister only supports n-bit writes, etc. attempted writes of a different size than the re gister width produce an erro r termination of the bus cycle and no change to the targeted register. 19.4.2.1 miscellaneous user-defined control register (mudcr) the mudcr provides a program-v isible register for user-defined contro l functions. it typi cally is used as configuration control for miscellane ous device-level modules. the conten ts of this register is simply output from ecsm to other modules where the user -defined control functions are implemented. see figure 19-1 and table 19-2 for the miscellaneous user-defin ed control register definition. 0x48?0x49 reserved 0x4a ecc error generation register (eegr) on page 19-7 0x4c?0x4f reserved 0x50 flash ecc address register (fear) on page 19-10 0x54?0x55 reserved 0x56 flash ecc master number register (femr) on page 19-10 0x57 flash ecc attributes (feat) on page 19-11 0x58?5b reserved 0x5c flash ecc data register (fedr) on page 19-12 0x60 ram ecc address register (rear) on page 19-13 0x64 reserved 0x65 ram ecc syndrome register (resr) on page 19-13 0x66 ram ecc master register (remr) on page 19-15 0x67 ram ecc attributes (reat) on page 19-16 0x68?0x6b reserved 0x6c ram ecc data register (redr) on page 19-17 table 19-1. ecsm memory map (continued) address offset register location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-3 preliminary?subject to change without notice 19.4.2.2 ecc registers for designs including error- correcting code (ecc) impl ementations to improve th e quality and reliability of memories, there are a number of program-visible registers for the so le purpose of reporting and logging of memory failures. these optional registers include: ? ecc configuration register (ecr) ? ecc status register (esr) ? ecc error generation register (eegr) ? flash ecc address register (fear) ? flash ecc master number register (femr) ? flash ecc attributes register (feat) ? flash ecc data register (fedr) ? ram ecc address register (rear) ? ram ecc syndrome register (resr) register address: ecsm base + 0x24 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mudcr[0] sram_add_one_ws mudcr[2:15] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mudcr[16:31] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-1. miscellaneous user-def ined control (m udcr) register table 19-2. miscellaneous user-defined co ntrol register (mudcr) field descriptions field description mudcr[0], mudcr[2:31] user-defined control register 0 = the control associated with this mudcr bit is disabled. 1 = the control associated with this mudcr bit is enabled. sram_add_ one_ws this bit dynamically controls the ahb read response of the sram controller; it is intended as a means to increase achievable frequency. 1 = one wait state is inserted in all ahb read responses. 0 = the sram controller adheres to a zero-wait-state response.
pxd20 microcontroller reference manual, rev. 1 19-4 freescale semiconductor preliminary?subject to change without notice ? ram ecc master number register (remr) ? ram ecc attributes register (reat) ? ram ecc data register (redr) the details on the ecc registers are provided in th e subsequent sections. if the design does not include ecc on the memories, these addresses are reserved locations within the ecsm?s programming model. 19.4.2.3 ecc configuration register (ecr) the ecc configuration register is an 8-bit control register for specifying which t ypes of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases , this error termination is reported directly by the initiating bus master. however, there are certain si tuations where the occurrence of this type of non-correctable error is not reported by the master. examples include speculative instruction fetches which are discarded due to a change-of-f low operation, and buffered operand wr ites. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific inform ation (memory address, attributes and data, bus master number, etc.) which may be useful for subsequent failure analysis. the reporting of single-bit memory corrections can only be enabled vi a a an soc-configurable module input signal. while not direc tly accessible to a user, this capability is viewed as important for error logging and failure analysis. see figure 19-2 and table 19-3 for the ecc configurat ion register definition. register address: ecsm base + 0x43 0 1 2 3 4 5 6 7 r 0 0 er1br ef1br 0 0 erncr efncr w reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-2. ecc configuration (ecr) register table 19-3. ecc configuration (ecr) field descriptions field description er1br enable ram 1-bit reporting 0 = reporting of single-bit ram corrections is disabled. 1 = reporting of single-bit ram corrections is enabled. this bit can only be set if the soc-configurable in put enable signal is asserted. the occurrence of a single-bit ram correction generates a ecsm ecc interrupt request as signalled by the assertion of esr[r1bc]. the address, attributes and data are al so captured in the rear, resr, remr, reat and redr registers.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-5 preliminary?subject to change without notice 19.4.2.4 ecc status register (esr) the ecc status register is an 8-bit control regist er for signaling which types of properly-enabled ecc events have been detected. the es r signals the last, prope rly-enabled memory event to be detected. ecc interrupt generation is separated in to single-bit error detection/correc tion, uncorrectable error detection and the combination of the two as defined by the following boolean equations. in these equations, ?&? refers to a bitwise and operator an d ?|? refers to a bitw ise or operator; bitwis e and has precedence of bitwise or. bitwise and has precedence of bitwise or. ecsm_ecc1bit_irq = ecr[er1br] & esr[r1bc]// ram, 1-bit correction | ecr[ef1br] & esr[f1bc]// flash, 1-bit correction ecsm_eccrncr_irq = ecr[erncr] & esr[rnce]// ram, noncorrectable error ecsm_eccfncr_irq = ecr[efncr] & esr[fnce]// flash, noncorrectable error ecsm_ecc2bit_irq = ecsm_eccrncr_irq// ram, noncorrectable error | ecsm_eccfncr_irq// flash, noncorrectable error ecsm_ecc_irq = ecsm_ecc1bit_irq // 1-bit correction | ecsm_ecc2bit_irq// noncorrectable error where the combination of a properly-enabled categor y in the ecr and the dete ction of the corresponding condition in the esr produces the interrupt request. ef1br enable flash 1-bit reporting 0 = reporting of single-bit flash corrections is disabled. 1 = reporting of single-bit flash corrections is enabled. this bit can only be set if the soc-configurable in put enable signal is asserted. the occurrence of a single-bit flash correction generates a ecsm ecc inte rrupt request as signalled by the assertion of esr[f1bc]. the address, attributes and data are al so captured in the fear, femr, feat and fedr registers. erncr enable ram non-correctable reporting 0 = reporting of non-correctable ram errors is disabled. 1 = reporting of non-correctable ram errors is enabled. the occurrence of a non-correctable multi-bit ram error generates a ecsm ecc interrupt request as signalled by the assertion of esr[rnce]. the faulting address, attributes and data are also captured in the rear, resr, remr, reat and redr registers. efncr enable flash non-correctable reporting 0 = reporting of non-correctable flash errors is disabled. 1 = reporting of non-correctable flash errors is enabled. the occurrence of a non-correctable multi-bit flash error generates a ecsm ecc interrupt request as signalled by the assertion of esr[fnce]. the faulting ad dress, attributes and data are also captured in the fear, femr, feat and fedr registers. table 19-3. ecc configuration (ecr ) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 19-6 freescale semiconductor preliminary?subject to change without notice the ecsm allows a maximum of one b it of the esr to be asserted at any given time. this preserves the association between the esr and the corresponding addr ess and attribute registers, which are loaded on each occurrence of an properly-enabled ecc event. if there is a pending ecc interrupt and another properly-enabled ecc event occurs, the ecsm ha rdware automatically handles the esr reporting, clearing the previous data and loading the new state and thus gua ranteeing that only a single flag is asserted. to maintain the coherent software view of the reported event, the fo llowing sequence in the ecsm error interrupt service routine is suggested: 1. read the esr and save it. 2. read and save all the address and attribute reporting registers. 3. re-read the esr and verify the current contents matches the original contents. if the two values are different, go back to step 1 and repeat. 4. when the values are identical, write a 1 to the a sserted esr flag to negate the interrupt request. see figure 19-3 and table 19-4 for the ecc status register definition. register address: ecsm base + 0x47 0 1 2 3 4 5 6 7 r 0 0 r1bc f1bc 0 0 rnce fnce w w1c w1c w1c w1c reset: 0 0 0 0 0 0 0 0 = unimplemented figure 19-3. ecc status (esr) register table 19-4. ecc status (esr) field descriptions field description r1bc ram 1-bit correction 0 = no reportable single-bit ram correction has been detected. 1 = a reportable single-bit ram correction has been detected. this bit can only be set if ecr[er1br] is assert ed. the occurrence of a pr operly-enabled single-bit ram correction generates a ecsm ecc interrupt requ est. the address, attributes and data are also captured in the rear, resr, remr, reat and redr regi sters. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. f1bc flash 1-bit correction 0 = no reportable single-bit flas h correction has been detected. 1 = a reportable single-bit flash correction has been detected. this bit can only be set if ecr[ef1br] is assert ed. the occurrence of a properly-enabled single-bit flash correction generates a ecsm ecc interrupt re quest. the address, attributes and data are also captured in the fear, femr, feat and fedr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-7 preliminary?subject to change without notice in the event that multiple status flags are signale d simultaneously, ecsm records the event with the r1bc as highest priority, then f1bc, then rnce, and finally fnce. 19.4.2.5 ecc error genera tion register (eegr) the ecc error generation register is a 16-bit control register used to force the generati on of single- and double-bit data inversions in the memo ries with ecc, most notably the ram. this capability is provided for two purposes: ? it provides a software-controlled mechanism for ?injecting? errors into the memories during data writes to verify the integrity of the ecc logic. ? it provides a mechanism to allow testing of the so ftware service routines associated with memory error logging. it should be noted that while the eeg r is associated with th e ram, similar capabiliti es exist for the flash, i.e., the ability to program the non- volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. for both types of memories (ram and flash), the intent is to generate er rors during data write cycles, such that subsequent reads of the corrupt ed address locations generate ecc ev ents, either singl e-bit corrections or double-bit noncorrectable er rors that are terminated with an error response. the enabling of these error generation modes requires the same soc-configurable input enable signal (as that used to enable single-bit correction reporting) be asserted. see figure 19-4 and table 19-5 for the ecc configurat ion register definition. rnce ram non-correctable error 0 = no reportable non-correctable ram error has been detected. 1 = a reportable non-correctable ram error has been detected. the occurrence of a properly-enabled non-correct able ram error generates a ecsm ecc interrupt request. the faulting address, attributes and data ar e also captured in the rear, resr, remr, reat and redr registers. to clear this interrupt flag, wr ite a 1 to this bit. writing a 0 has no effect. fnce flash non-correctable error 0 = no reportable non-correctable flash error has been detected. 1 = a reportable non-correctable flash error has been detected. the occurrence of a properly-enabled non-correctab le flash error generates a ecsm ecc interrupt request. the faulting address, attributes and data are also captured in the fear, femr, feat and fedr registers. to clear this interrupt flag, wr ite a 1 to this bit. writing a 0 has no effect. table 19-4. ecc status (esr) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 19-8 freescale semiconductor preliminary?subject to change without notice register address: ecsm base + 0x4a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r rw bit 0 frc1 bi fr11 bi 0 0 frcn ci fr1 nci 0 errbit w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented figure 19-4. ecc error generation (eegr) register table 19-5. eegr field descriptions field description rwbit redundant writable bit this bit has no function, but may be read and written. frc1bi force ram continuous 1-bit data inversions 0 = no ram continuous 1-bit data inversions are generated. 1 = 1-bit data inversions in t he ram are continuously generated. the assertion of this bit forces the ram controller to create 1-bit data inversions, as defined by the bit position specified in errbit[0:6], co ntinuously on every write operation. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to in troduce a 1-bit ecc event in the ram. after this bit has been enabled to generate another co ntinuous 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all ot her values result in undefined behavior. fr11bi force ram one 1-bit data inversion 0 = no ram single 1-bit data inversion is generated. 1 = one 1-bit data inversion in the ram is generated. the assertion of this bit forces the ram controller to create one 1-bit data inversion, as defined by the bit position specified in errb it[0:6], on the first write oper ation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to in troduce a 1-bit ecc event in the ram. after this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all ot her values result in undefined behavior.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-9 preliminary?subject to change without notice frcnci force ram continuous noncorrectable data inversions 0 = no ram continuous 2-bit data inversions are generated. 1 = 2-bit data inversions in t he ram are continuously generated. the assertion of this bit forces the ram controller to create 2-bit data inversions, as defined by the bit position specified in errbit[0:6] and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another c ontinuous noncorrectable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are in verted to introduce a 2-bit ecc error in the ram. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all ot her values result in undefined behavior. fr1nci force ram one noncorrectable data inversions 0 = no ram single 2-bit data inversions are generated. 1 = one 2-bit data inversion in the ram is generated. the assertion of this bit forces the ram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit[0:6] and the overall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are in verted to introduce a 2-bit ecc error in the ram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. all ot her values result in undefined behavior. errbit error bit position the vector defines the bit position which is complemented to create the data inversion on the write operation. for the creation of 2-bit data inversions, the bi t specified by this field plus the odd parity bit of the ecc code are inverted. the ram controller follows a vector bit ordering sc heme where lsb=0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the ram width. for example, consider a 32-bit ram implementation. the 32-bit ecc approach requires 7 code bits for a 32-bit word. for pram data width of 32 bits, the actual sram (32b data + 7b for ecc) = 39 bits. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, then ram[0] of the odd bank is inverted if errbit = 1, then ram[1] of the odd bank is inverted ... if errbit = 31, then ram[31] of the odd bank is inverted if errbit = 64, then ecc parity[0] of the odd bank is inverted if errbit = 65, then ecc parity[1] of the odd bank is inverted ... if errbit = 70, then ecc parity[6] of the odd bank is inverted for errbit values of 32 to 63 and greater than 70, no bit position is inverted. table 19-5. eegr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 19-10 freescale semiconductor preliminary?subject to change without notice if an attempt to force a non-correctable invers ion (by asserting eegr[f rcnci] or eegr[frc1nci]) and eegr[errbit] equals 64, then no da ta inversion will be generated. 19.4.2.6 flash ecc address register (fear) the fear is a 32-bit register for cap turing the address of the last, prope rly-enabled ecc event in the flash memory. depending on the state of th e ecc configuration regi ster, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-5 and table 19-6 for the flash ecc addr ess register definition. 19.4.2.7 flash ecc master number register (femr) the femr is a 4-bit register for capturing the axbs bus master number of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attri butes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-6 and table 19-7 for the flash ecc master number register definition. register address: ecsm base + 0x50 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fear[0:15] w reset: x x x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fear[16:31] w reset: x x x x x x x x x x x x x x x x = unimplemented figure 19-5. flash ecc a ddress (fear) register table 19-6. flash ecc address (fear) field descriptions name description 0-31 fear[0:31] flash ecc address register this 32-bit register contains the faulting acce ss address of the last, properly-enabled flash ecc event.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-11 preliminary?subject to change without notice 19.4.2.8 flash ecc attributes (feat) register the feat is an 8-bit register for capturing the axbs bus master attributes of the last, properly-enabled ecc event in the flash memory. depe nding on the state of the ecc conf iguration register, an ecc event in the flash causes the address, attri butes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-7 and table 19-8 for the flash ecc attri butes register definition. register address: ecsm base + 0x56 0 1 2 3 4 5 6 7 r 0 0 0 0 femr[0:3] w reset: 0 0 0 0 - - - - = unimplemented figure 19-6. flash ecc master number (femr) register table 19-7. flash ecc master number (femr) field descriptions name description 4-7 femr[0:3] flash ecc master number register this 4-bit register contains the axbs bus master number of the faulti ng access of the last, properly-enabled flash ecc event. register address: ecsm base + 0x57 0 1 2 3 4 5 6 7 r write size[0:2] protection[0:3] w reset: x x x x x x x x = unimplemented figure 19-7. flash ecc attributes (feat) register table 19-8. flash ecc attributes (feat) field descriptions name description 0 write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access
pxd20 microcontroller reference manual, rev. 1 19-12 freescale semiconductor preliminary?subject to change without notice 19.4.2.9 flash ecc data register (fedr) the fedr is a 32-bit regist er for capturing the data associated wi th the last, properly-enabled ecc event in the flash memory. depending on th e state of the ecc configuration re gister, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-8 and table 19-9 for the flash ecc data register definition. 1-3 size[0:2] amba-ahb hsize[0:2] 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b1xx = reserved 4-7 protection[0:3] amba-ahb hprot[0:3] protection[3]: cacheable 0 = non-cacheable,1 = cacheable protection[2]: bufferable0 = n on-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data register address: ecsm base +0x5c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fedr[0:15] w reset: x x x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedr[16:31] w reset: x x x x x x x x x x x x x x x x = unimplemented figure 19-8. flash ecc data (fedr) register table 19-9. flash ecc data (fedr) field descriptions name description 0-31 fedr[0:31] flash ecc data register this 32-bit register contains the data associated with the faulting access of the last, properly-enabled flash ecc event. the register contains the dat a value taken directly from the data bus. table 19-8. flash ecc attributes (feat) field descriptions (continued) name description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-13 preliminary?subject to change without notice 19.4.2.10 ram ecc address register (rear) the rear is a 32-bit register for capturing the addr ess of the last, properly-enabled ecc event in the ram memory. depending on the stat e of the ecc configuration regi ster, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the rear, resr, remr, reat and redr registers, a nd the appropriate flag (r1bc or rn ce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-9 and table 19-10 for the ram ecc address register definition. 19.4.2.11 ram ecc syndrome register (resr) the resr is an 8-bit register for capturing the error syndrome of the last, properly-enabled ecc event in the ram memory. depending on the stat e of the ecc configuration regi ster, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the rear, resr, remr, reat and redr registers, a nd the appropriate flag (r1bc or rn ce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-10 and table 19-11 for the ram ecc syndrom e register definition. register address: ecsm base + 0x60 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r rear[0:15] w reset: x x x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rear[16:31] w reset: x x x x x x x x x x x x x x x x = unimplemented figure 19-9. ram ecc address (rear) register table 19-10. ram ecc address (rear) field descriptions name description 0-31 rear[0:31] ram ecc address register this 32-bit register contains the faulting acce ss address of the last, properly-enabled ram ecc event.
pxd20 microcontroller reference manual, rev. 1 19-14 freescale semiconductor preliminary?subject to change without notice note: ta b l e 1 9 - 1 1 associates the upper 7 bits of the ecc syndrome with the exact data bit in error for single-bit correctable codewords. this table follows the bit vectoring notation wher e the lsb=0. note that the syn drome value of 0x01 implies no error condition but this value is not readable when the presr is read for the no error case. register address: ecsm base + 0x65 0 1 2 3 4 5 6 7 r resr[0:7] w reset: x x x x x x x x = unimplemented figure 19-10. ram ecc syndrome (resr) register table 19-11. ram ecc syndrome (resr) field descriptions name description 0-7 resr[0:7] ram ecc syndrome register this 8-bit syndrome field includes 6 bits of hammi ng decoded parity plus an odd-parity bit for the entire 39-bit (32-bit data + 7 ecc) code word. the upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. for correctable single-bit errors, the mapping shown in table 19-11 associates the upper 7 bits of the syndrome with the data bit in error. table 19-12. ram syndrome mapping for single-bit correctable errors resr[0:7] data bit in error 0x00 ecc odd[0] 0x01 no error 0x02 ecc odd[1] 0x04 ecc odd[2] 0x06 data odd bank[31] 0x08 ecc odd[3] 0x0a data odd bank[30] 0x0c data odd bank[29] 0x0e data odd bank[28] 0x10 ecc odd[4] 0x12 data odd bank[27] 0x14 data odd bank[26] 0x16 data odd bank[25] 0x18 data odd bank[24] 0x1a data odd bank[23] 0x1c data odd bank[22] 0x50 data odd bank[21] 0x20 ecc odd[5] 0x22 data odd bank[20]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-15 preliminary?subject to change without notice 19.4.2.12 ram ecc master number register (remr) the remr is a 4-bit register for capturing the axbs bus master number of the last, properly-enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associ ated with the access to be loaded into the rear, resr, remr, reat and redr regist ers, and the appropriate flag (r 1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-11 and table 19-13 for the ram ecc master nu mber register definition. 0x24 data odd bank[19] 0x26 data odd bank[18] 0x28 data odd bank[17] 0x2a data odd bank[16 0x2c data odd bank[15] 0x58 data odd bank[14] 0x30 data odd bank[13] 0x32 data odd bank[12] 0x34 data odd bank[11] 0x64 data odd bank[10] 0x38 data odd bank[9] 0x62 data odd bank[8] 0x70 data odd bank[7] 0x60 data odd bank[6] 0x40 ecc odd[6] 0x42 data odd bank[5] 0x44 data odd bank[4] 0x46 data odd bank[3] 0x48 data odd bank[2] 0x4a data odd bank[1] 0x4c data odd bank[0] 0x03,0x05........0x4d multiple bit error > 0x4d multiple bit error table 19-12. ram syndrome mapping for single-bit correctable errors (continued) resr[0:7] data bit in error
pxd20 microcontroller reference manual, rev. 1 19-16 freescale semiconductor preliminary?subject to change without notice 19.4.2.13 ram ecc attributes (reat) register the reat is an 8-bit register for capturing the axbs bus master attributes of the last, properly-enabled ecc event in the ram memory. depe nding on the state of the ecc conf iguration register, an ecc event in the ram causes the address, attributes and data as sociated with the access to be loaded into the rear, resr, remr, reat and redr regist ers, and the appropriate flag (r 1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-12 and table 19-14 for the ram ecc attributes register definition. register address: ecsm base + 0x66 0 1 2 3 4 5 6 7 r 0 0 0 0 remr[0:3] w reset: 0 0 0 0 x x x x = unimplemented figure 19-11. ram ecc master number (remr) register table 19-13. ram ecc master number (remr) field descriptions name description 4-7 remr[0:3] ram ecc master number register this 4-bit register contains the axbs bus master number of the faulting access of the last, properly-enabled ram ecc event. register address: ecsm base + 0x67 0 1 2 3 4 5 6 7 r write size[0:2] protection[0:3] w reset: x x x x x x x x = unimplemented figure 19-12. ram ecc attributes (reat) register table 19-14. ram ecc attributes (reat) field descriptions name description 0 write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 19-17 preliminary?subject to change without notice 19.4.2.14 ram ecc data register (redr) the redr is a 32-bit register for capturing the data associated with the last, properly-enabled ecc event in the ram memory. depending on the state of the e cc configuration register , an ecc event in the ram causes the address, attributes an d data associated with the access to be loaded into the rear, resr, remr, reat and redr registers, a nd the appropriate flag (r1bc or rn ce) in the ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 19-13 and table 19-15 for the ram ecc data register definition. 1-3 size[0:2] amba-ahb hsize[0:2] 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b1xx = reserved 4-7 protection[0:3] amba-ahb hprot[0:3] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data register address: ecsm base +0x6c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r redr[0:15] w reset: x x x x x x x x x x x x x x x x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redr[16:31] w reset: x x x x x x x x x x x x x x x x = unimplemented figure 19-13. ram ecc da ta (redr) register table 19-14. ram ecc attributes (reat) field descriptions (continued) name description
pxd20 microcontroller reference manual, rev. 1 19-18 freescale semiconductor preliminary?subject to change without notice 19.4.3 high priority enables e200 processors can be configured to support criti cal and/or external interrupts. furthermore, each processor can be configured to em ploy priority elevation on critical and/or external interrupt events. critical interrupts come from outside the platform, and are routed dire ctly to the processor?s critical interrupt input. external interrupts are routed through th e interrupt controller. in addition to the interrupt notification signals, va rious processor-specific c onfiguration flags from the processor?s machine check register (mcr[ee,ce]) and the hard ware implementation re gister (hid1) are sent to the ecsm to determine when interrupt servicing is enabled and when high-priority elevation should be enabled. if the corresponding processor is configured to allow high-priority elevation on critical interrupt events, the ecsm generates the high-priority signal upon critical interrupt detection and holds it active throughout the duration of interrupt servicing. if the correspondi ng processor is configured to allow hi gh-priority elevation on external interrupt even ts, the ecsm generates the high-priority signal upon external interrupt detection and holds it active throughout the duration of interrupt servicing. during interrupt servicing the processor status output, p_stat, is monitored fo r indication of a return from interrupt (rfi). great care needs to be taken when using the priority el evation as it can enable a master to starve the rest of the masters in th e system. please see chapter 9, crossbar switch (xbar), for information on priority elevation. 19.4.4 supervisor mode access protection the supervisor mode access protection logic provides hardware enforcement of supervisor mode access protection for five on-platform i ps modules: intc, ecsm, mpu, stm, and swt. this logic resides between the on-platform bus sourced by the aips bu s controller and the indi vidual slave modules. it monitors the bus access type (supervisor or user) and if a user access is at tempted, the transfer is terminated with an error and inhibited from reach ing the slave module. identical logic is replicated for each of the five, targeted slave modules. table 19-15. ram ecc data (redr) field descriptions name description 0-31 redr[0:31] ram ecc data register this 32-bit register contains the data asso ciated with the faulting access of the last, properly-enabled ram ecc event. the register co ntains the data value taken directly from the data bus.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-1 preliminary?subject to change without notice chapter 20 flexcan 20.1 introduction the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. a ge neral block diagram is shown in figure 20-1 , which describes the main sub-blocks implemented in the flexcan module, including two embedded memories, one for storing message buffers (mb) and another one for storing rx indivi dual mask registers. support for up to 64 message buffers is provided (see the device user guide for the actual size implemented on the mcu). the functions of the sub-modules are described in subsequent sections. figure 20-1. flexcan block diagram 20.1.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this fi eld: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the 288/544/1056- bus interface unit max mb # (0??6 ip bus interface can message can tx can rx mb1 mb0 mb62 mb63 clocks, address & data buses, interrupt and test signals buffer management protocol interface byte ram message buffer storage 64/128/256- rximr1 rximr0 rximr62 rximr63 byte ram id mask storage
pxd20 microcontroller reference manual, rev. 1 20-2 freescale semiconductor preliminary?subject to change without notice can protocol specificati on, version 2.0 b [ref. 1], which support s both standard and extended message frames. a flexible number of messa ge buffers (16, 32 or 64) is also supported. the message buffers are stored in an embedded ra m dedicated to the flexcan module. pl ease refer to th e device-specific information section for the actual number of message buffers conf igured in the mcu. the can protocol interface (cpi) sub-module ma nages the serial comm unication on the can bus, requesting ram access for receiving and transmitting message frames, va lidating received messages and performing error handling. the me ssage buffer management (mbm ) sub-module handles message buffer selection for reception and transmission, taking care of arbitrat ion and id matching algorithms. the bus interface unit (biu) sub-module controls the acce ss to and from the internal interface bus, in order to establish connecti on to the cpu and to other bl ocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. 20.1.2 flexcan module features the flexcan module includes these distinctive features: ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mb/sec ? content-related addressing ? flexible message buffers (up to 64) of zero to eight bytes data length ? each mb configurable as rx or tx, al l supporting standard and extended messages ? individual rx mask registers per message buffer ? includes up to 1024 bytes (64 mbs) of ram used for mb storage ? includes up to 256 bytes (64 mbs) of ram used for individual rx mask registers ? full featured rx fifo with storage capacity for 6 frames and internal pointer handling ? powerful rx fifo id filtering, capable of ma tching incoming ids against either 8 extended, 16 standard or 32 partial (8 bits) id s, with individual masking capability ? selectable backwards compatibilit y with previous flexcan version ? programmable clock source to th e can protocol interface, either bus clock or crystal oscillator ? unused mb and rx mask register space ca n be used as general purpose ram space ? listen only mode capability ? programmable loop-back mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-3 preliminary?subject to change without notice ? short latency time due to an arbitration scheme for high-priority messages ? low power modes 20.1.3 modes of operation the flexcan module has four func tional modes: normal mode (use r and supervisor), freeze mode, listen-only mode and loop-back mode. there is also a low-power mode, disable mode. ? normal mode (user or supervisor): in normal mode, the module operates receiving a nd/or transmitting message frames, errors are handled normally and all the can protocol functions are enable d. user and supervisor modes differ in the access to some restricted control registers. ? freeze mode: it is enabled when the frz bit in the mcr register is asserted. if enabled, freeze mode is entered when the halt bit in mcr is set or when debug m ode is requested at mcu level. in this mode, no transmission or reception of frames is done a nd synchronicity to the can bus is lost. see section 20.5.9.1, freeze mode for more information. ? listen-only mode: the module enters this mode when the lom bit in the control regist er is asserted. in this mode, transmission is disable d, all error counters are frozen and the module operates in a can error passive mode [ref. 1]. only messa ges acknowledged by another can station will be received. if flexcan detects a message that has not been ac knowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. ? loop-back mode: the module enters this mode when the lpb bit in the control register is asserted. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessi ve state (logic ?1?). flexcan behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. in this mode , flexcan ignores the bit sent during the ac k slot in the can frame acknowledge field to ensure proper reception of its own messa ge. both transmit and receive interrupts are generated. ? module disable mode: this low power mode is entered when the mdis bit in the mcr register is asserted. when disabled, the module shuts down the clocks to th e can protocol interface and message buffer management sub-modules. exit from this mode is done by negating the can_mcr[mdis] bit. see section 20.5.9.2, module disable mode for more information. 20.2 device-specific information this device implements flexcan 0, flexcan 1, and flexcan 2. the "x" appended to signal names signifies the flexcan module to which the signal appl ies. thus cantx_0 is the transmit signal that applies to flexcan 0, cantx_1 is the transmit signal that applies to flexcan 1, and so on. all flexcan modules feature 64 message buffers.
pxd20 microcontroller reference manual, rev. 1 20-4 freescale semiconductor preliminary?subject to change without notice 20.3 external signal description 20.3.1 overview the flexcan module has two i/o si gnals connected to the external mcu pins. these signals are summarized in table 20-1 and described in more detail in the next sub-sections. 20.3.2 signal descriptions 20.3.2.1 can rx this pin is the receive pin from the can bus transceive r. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. 20.3.2.2 can tx this pin is the transmit pin to th e can bus transceiver. dominant stat e is represented by logic level ?0?. recessive state is represented by logic level ?1?. 20.4 memory map and register description this section describes the registers and data structures in the flexca n module. the base address of the module depends on the particul ar memory map of the mcu. the addres ses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes fo r registers starting at the module base address, followed by mb storage space in embedded ram st arting at address 0x0060, and an extra id mask storage space in a separate em bedded ram starting at address 0x0880. 20.4.1 flexcan memory mapping the complete memory map fo r a flexcan module with 64 mb s capability is shown in table 20-2 . each individual register is identified by its complete name and the corresponding mnemonic. the access type can be supervisor (s) or unrestricted (u). most of the registers ca n be configured to ha ve either supervisor or unrestricted access by pr ogramming the mcr[supv] bit. these registers are identified as s/u in the access column of table 20-2 . the ifrh and imrh registers are c onsidered reserved space when flexcan is configured with 16 or 32 mbs. the rx global mask (rxgmask), rx buffer 14 mask (rx14mask) and the rx buffer 15 mask table 20-1. flexcan signals signal name 1 1 the actual mcu pins may have different names. please consult the device user guide for the actual signal names. direction description can rx input can receive pin can tx output can transmit pin
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-5 preliminary?subject to change without notice (rx15mask) registers are provided for backwards compatibility, a nd are not used when the bcc bit in mcr is asserted. the address ranges 0x0060?0x047f a nd 0x0880?0x097f are occupied by two separate embedded memories. these two ranges are completely occ upied by ram (1056 and 256 bytes, respectively) only when flexcan is configured with 64 mbs. when it is c onfigured with 16 mbs, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180?0x047f and 0x08c0?0x097f are c onsidered reserved space. when it is configured with 32 mbs, the memory sizes are 544 a nd 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are considered reserved sp ace. furthermore, if the bcc bit in mcr is negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space. table 20-2. module memory map address use access type affected by hard reset affected by soft reset location base + 0x0000 module configuration (mcr) s yes yes on page 20-11 base + 0x0004 control register (ctrl) s/u yes no on page 20-15 base + 0x0008 free running timer (timer) s/u yes yes on page 20-18 base + 0x000c reserved base + 0x0010 rx global mask (rxgmask) s/u yes no on page 20-19 base + 0x0014 rx buffer 14 mask (rx14mask) s/u yes no on page 20-21 base + 0x0018 rx buffer 15 mask (rx15mask) s/u yes no on page 20-21 base + 0x001c error counter register (ecr) s/u yes yes on page 20-21 base + 0x0020 error and status register s/u yes yes on page 20-23 base + 0x0024 interrupt mask register high (imrh) s/u yes yes on page 20-25 base + 0x0028 interrupt mask register low (imrl) s/u yes yes on page 20-26 base + 0x002c interrupt flag register high (ifrh) s/u yes yes on page 20-27 base + 0x0030 interrupt flag register high (ifrl) s/u yes yes on page 20-28 base + 0x0034?0x007f reserved base + 0x0080?0x017f message buffers mb0 ? mb15 s/u no no ? base + 0x0180?0x027f message buffers mb16 ? mb31 s/u no no ? base + 0x0280?0x047f message buffers mb32 ? mb63 s/u no no ? base + 0x0480-087f reserved base + 0x0880-0x08bf rx individual mask registers rximr0-rximr15 s/u no no on page 20-29
pxd20 microcontroller reference manual, rev. 1 20-6 freescale semiconductor preliminary?subject to change without notice the flexcan module stores can messages for tran smission and reception us ing a message buffer structure. each individual mb is formed by 16 bytes mapped on memory as described in table 20-3 . table 20-3 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). 20.4.2 message buffer structure the message buffer structure used by the flexcan module is represented in figure 20-2 . both extended and standard frames (29-bit identifier and 11-bit identifier, re spectively) used in the can specification (version 2.0 part b) are represented. base + 0x08c0-0x08ff rx individual mask registers rximr16-rximr31 s/u no no on page 20-29 base + 0x0900-0x097f rx individual mask registers rximr32-rximr63 s/u no no on page 20-29 table 20-3. message buffer mb0 memory mapping address offset mb field 0x80 control and status (c/s) 0x84 identifier field 0x88 ? 0x8f data field 0 ? data field 7 (1 byte each) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0 code s r r id e rt r length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved figure 20-2. message buffer structure table 20-2. module memory map (continued) address use access type affected by hard reset affected by soft reset location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-7 preliminary?subject to change without notice table 20-4. message buffer structure field descriptions field description code message buffer code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitr ation process. the encoding is shown in ta bl e 2 0 - 5 and ta bl e 2 0 - 6 . see section 20.5, functional description for additional information. srr substitute remote request fixed recessive bit, used only in extended format. it must be set to ?1? by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 1 = recessive value is compulsory for transmission in extended format frames 0 = dominant is not a valid value for transmission in extended format frames ide id extended bit this bit identifies whether the frame format is standard or extended. 1 = frame format is extended 0 = frame format is standard rtr remote transmission request this bit is used for requesting transmissions of a data frame. if flexcan transmits this bit as ?1? (recessive) and receives it as ?0? (dominant), it is interpreted as arbitration loss. if this bit is transmitted as ?0.? (dominant), then if it is received as ?1? (recessive), the flexcan module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. do not configure last message buffer to be rtr frame. 1 = indicates the current mb has a remote frame to be transmitted 0 = indicates the current mb has a data frame to be transmitted length length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx data, which is located in offset 0x8 through 0xf of the mb space (see ta b l e 2 0 - 2 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. in transmission, this field is written by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the length field. time stamp free-running counter time stamp this 16-bit field is a copy of the free-running time r, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority this 3-bit field is only used when lprio_en bit is set in mcr and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 20.5.3, ar bitration process . id frame identifier in standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for frame identification in both receive and transmit cases. data data field up to eight bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. for tx frames, the cpu prepares the data field to be transmitted within the frame.
pxd20 microcontroller reference manual, rev. 1 20-8 freescale semiconductor preliminary?subject to change without notice table 20-5. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: mb is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. refer to section 20.5.5, matching process for details about overrun behavior. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame mu st be written, the mb will be overwritten again, and the code will remain overrun. refer to section 20.5.5, matching process for details about overrun behavior. 0xy1 1 1 note that for tx mbs (see ta bl e 2 0 - 6 ), the busy bit should be ignored upon read, except when aen bit is set in the mcr register. busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). table 20-6. message buffer code for tx buffers rtr initial tx code code after successful transmission description x 1000 ? inactive: mb does not partic ipate in the arbitration process. 0 1100 1000 transmit data frame unconditi onally once. after transmission, the mb automatically returns to the inactive state.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-9 preliminary?subject to change without notice 20.4.3 rx fifo structure when the fen bit is set in the m cr, the memory area from 0x80 to 0x ff (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. figure 20-3 shows the rx fifo data structure. the region 0x0-0xc contains an mb stru cture which is the port through wh ich the cpu reads data from the fifo (the oldest frame r eceived and not read yet). the region 0x10- 0xdf is reserved for internal use of the fifo engine. the region 0xe0-0xff contains an 8-entry id table that specifies filtering criteria for accepting frames into the fifo. figure 20-4 shows the three different format s that the elements of the id table can assume, depending on the idam field of the mcr. note that all elements of the table must have the same format. see section 20.5.7, rx fifo for more information. 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to ?1110? to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to ?1010? to restart the process again. 0 1110 1010 this is an intermediate code th at is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to ?1010?. the cpu can also write this code with the same effect. table 20-6. message buffer code for tx buffers (continued) rtr initial tx code code after successful transmission description
pxd20 microcontroller reference manual, rev. 1 20-10 freescale semiconductor preliminary?subject to change without notice 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0 s r r id e rt r length time stamp 0x4 id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 0x10 reserved to 0xdf 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 20-3. rx fifo structure 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 a r e m e x t rxida (standard = 2-12, extended = 2-30) b r e m e x t rxidb_0 (standard =2-12, extended = 2-15) r e m e x t rxidb_1 (standard = 18-28, extended = 18-31) crxidc_0 (std/ext = 0-7) rxidc_1 (std/ext = 8-15) rxidc_2 (std/ext = 16-23) rxidc_3 (std/ext = 24-31) = unimplemented or reserved figure 20-4. id table 0 - 7
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-11 preliminary?subject to change without notice 20.4.4 register descriptions the flexcan registers are described in this section in as cending address order. 20.4.4.1 module configur ation register (mcr) this register defines global system configurations, such as the m odule operation mode (e.g., low power) and maximum message buffer configuratio n. most of the fields in this re gister can be acce ssed at any time, except the maxmb field, which should only be ch anged while the module is in freeze mode. table 20-7. rx fifo structure field descriptions field description rem remote frame this bit specifies if remote frames are accept ed into the fifo if they match the target id. 1 = remote frames can be acc epted and data frames are rejected 0 = remote frames are rejected and data frames can be accepted ext extended frame specifies whether extended or standard frames are a ccepted into the fifo if they match the target id. 1 = extended frames can be accepted and standard frames are rejected 0 = extended frames are rejected an d standard frames can be accepted rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (2 to 12)are used for frame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, the 11 most significant bits (a full standard id) (2 to 12)are used for frame identification. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance criter ia for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id.
pxd20 microcontroller reference manual, rev. 1 20-12 freescale semiconductor preliminary?subject to change without notice base + 0x0000 0123456789101112131415 r mdis frz fen halt not_ rdy 0soft _rst frz_ ack supv 0 wrn_ en lpm_ ack 0d_rs vd srx _dis bcc w reset: note 1 1 reset value of this bit is different on various platform s. consult the specific mcu documentation to determine its value. 101100note 2 2 different on various platforms, but it is always the opposite of the mdis reset value. 100note 3 3 different on various platforms, but it is always the same as the mdis reset value. 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00lprio _en aen 0 0 idam 0 0 maxmb w reset: 0000000000001111 = unimplemented or reserved figure 20-5. module configuration register (mcr) table 20-8. mcr field descriptions field description mdis module disable this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the clocks to the can protocol interface and message buffer management sub-modules. this is the only bit in mcr not affected by soft reset. see section 20.5.9.2, module disable mode for more information. 1 = disable the flexcan module 0 = enable the flexcan module frz freeze enable the frz bit specifies the flexcan behavior when the halt bit in the mcr register is set or when debug mode is requested at mcu level. when frz is asserted, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 1 = enabled to enter freeze mode 0 = not enabled to enter freeze mode fen fifo enable this bit controls whether the fifo feature is enabled or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xff) is used by the fifo engine. see section 20.4.3, rx fifo structure and section 20.5.7, rx fifo for more information. 1 = fifo enabled 0 = fifo not enabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-13 preliminary?subject to change without notice halt halt flexcan assertion of this bit puts the flexcan module into freeze mode. the cpu should clear it after initializing the message buffers and control register . no reception or transmission is performed by flexcan before this bit is cleared. while in freeze mode, the cpu has write access to the error counter register, that is otherwise read-only. freeze mode can not be entered while flexcan is in any of the low power modes. see section 20.5.9.1, freeze mode for more information. 1 = enters freeze mode if the frz bit is asserted. 0 = no freeze mode request. not_rdy flexcan not ready this read-only bit indicates that flexcan is either in disable mode or freeze mode. it is negated once flexcan has exited these modes. 1 = flexcan module is either in disable mode freeze mode 0 = flexcan module is either in normal mode, listen-only mode or loop-back mode soft_rst soft reset when this bit is asserted, flexcan resets its internal state machines and some of the memory mapped registers. the following registers are reset: mcr (except the mdis bit), timer, ecr, esr, imrl, imrh, ifrl, and ifrh. confi guration registers that control the interface to the can bus are not affected by soft reset. the following registers are unaffected: ?ctrl ? rximr0?rximr63 ? rxgmask, rx14mask, rx15mask ? all message buffers the soft_rst bit can be asserted di rectly by the cpu when it writes to the mcr register, but it is also asserted when global soft reset is requested at mcu level. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the soft_rst bit remains asserted while reset is pending, and is automatically negated when reset completes. therefor e, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in any of the low power modes. the module should be first removed from low power mode, and then soft reset can be applied. 1 = resets the registers marked as ?affected by soft reset? in table 20-2 0 = no reset request frz_ack freeze mode acknowledge this read-only bit indicates that flexcan is in freeze mode and its prescaler is stopped. the freeze mode request cannot be granted until current transmi ssion or reception processes have finished. therefore the software can poll the frz_ack bit to know when flexcan has actually entered freeze mode. if freeze mode request is negate d, then this bit is negated once the flexcan prescaler is running again. if freeze mode is requested while flexcan is in any of the low power modes, then the frz_ack bit will only be set when the low power mode is exited. see section 20.5.9.1, freeze mode for more information. 1 = flexcan in freeze mode, prescaler stopped 0 = flexcan not in freeze mode, prescaler running supv supervisor mode this bit configures some of the flexcan registers to be either in supervisor or unrestricted memory space. the registers affected by this bit ar e marked as s/u in the access type column of ta b l e 2 0 - 2 . reset value of this bit is ?1?, so the affected registers start with supervisor access restrictions. 1 = affected registers are in supervisor memory space. any access withou t supervisor permission behaves as though the access was done to an unimplemented register location 0 = affected registers are in unrestricted memory space table 20-8. mcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 20-14 freescale semiconductor preliminary?subject to change without notice wrn_en warning interrupt enable when asserted, this bit enables the generation of the twrn_int and rwrn_int flags in the error and status register. if wrn_en is negated, the twrn_int and rwrn_int flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. 1 = twrn_int and rwrn_int bits are set when t he respective error counter transition from <96 to ? 96. 0 = twrn_int and rwrn_int bits are zero, independent of the values in the error counters. lpm_ack low power mode acknowledge this read-only bit indicates that flexcan is in di sable mode. this mode cannot be entered until all current transmission or reception processes have finished, so the cpu can poll the lpm_ack bit to know when flexcan has actually entered low power mode. see section 20.5.9.2, module disable mode , for more information. 1 = flexcan is either in disable mode 0 = flexcan not in any of the low power modes d_rsvd reserved bit. this bit is writable but should be kept as value 0. srx_dis self reception disable this bit defines whether flexcan is allowed to rece ive frames transmitted by itself. if this bit is asserted, frames transmitted by the module will not be stored in any mb, regardless if the mb is programmed with an id that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. 1 = self reception disabled 0 = self reception enabled bcc backwards compatibility configuration this bit is provided to support backwards compatib ility with previous flexcan versions. when this bit is negated, the following configuration is applied: ? for mcus supporting individual rx id masking, th is feature is disabled. instead of individual id masking per mb, flexcan uses its previous masking scheme with rxgmask, rx14mask and rx15mask. ? the reception queue feature is disabled. upon receiving a message, if the first mb with a matching id that is found is still occupied by a previous unread message, flexcan will not look for another matching mb. it will override this mb with the new message and set the code field to ?0110? (overrun). upon reset this bit is negated, allowing legacy software to work without modification. 1 = individual rx masking and queue feature are enabled. 0 = individual rx masking and queue feature are disabled. lprio_en local priority enable this bit is provided for backwards compatibility reas ons. it controls whether the local priority feature is enabled or not. it is used to extend the id us ed during the arbitration process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted id still has 11-bit for standard frames and 29-bit for extended frames. 1 = local priority enabled 0 = local priority disabled table 20-8. mcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-15 preliminary?subject to change without notice 20.4.4.2 control register (ctrl) this register is defined for specifi c flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warni ng). it also determines th e division factor for the clock prescaler. most of the fields in this register shoul d only be changed while the module is in disable mode or in freeze mode. exceptions are the boff_msk, err_msk, twrn_msk, rwrn_msk and boff_rec bits, that can be accessed at any time. idam id acceptance mode this 2-bit field identifies the format of the elemen ts of the rx fifo filter table, as shown in ta bl e 2 0 - 9 . note that all elements of the table are configur ed at the same time by this field (they are all the same format). see section 20.4.3, rx fifo structure . maxmb maximum number of message buffers this 6-bit field defines the maximum number of me ssage buffers that will take part in the matching and arbitration processes. the reset value (0x0f) is equivalent to 16 mb configuration. this field should be changed only while the module is in freeze mode. maximum mbs in use = maxmb + 1 note: maxmb has to be programmed with a value smal ler or equal to the number of available message buffers, otherwise flexcan will not transmit or receive frames. table 20-9. idam coding idam format explanation 00 a one full id (standard or ex tended) per filter element. 01 b two full standard ids or two partia l 14-bit extended ids per filter element. 10 c four partial 8-bit ids (standard or extended) per filter element. 11 d all frames rejected. table 20-8. mcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 20-16 freescale semiconductor preliminary?subject to change without notice base + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r presdiv rjw pseg1 pseg2 w reset: 0000 0 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boff _msk err_ msk clk_ src lpb twrn _msk rwrn _msk 00smpboff _rec tsyn lbuf lom propseg w reset: 0000 0 0 0000000000 = unimplemented or reserved figure 20-6. control register (ctrl) table 20-10. control register (ctrl) field descriptions field description 0-7 presdiv prescaler division factor this 8-bit field defines the ratio between the cpi clock frequency and the serial clock (sclock) frequency. the sclock period defines the time quant um of the can protocol. for the reset value, the sclock frequency is equal to the cpi clock frequency. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section 20.5.8.4, protocol timing . sclock frequency = cpi clock frequency / (presdiv + 1) 8-9 rjw resync jump width this 2-bit field defines the maximum number of time quanta 1 that a bit time can be changed by one resynchronization. the valid programmable values are 0 ? 3. resync jump width = rjw + 1. 10-12 pseg1 pseg1 ? phase segment 1 this 3-bit field defines the length of phase buffer segment 1 in the bit time. the valid programmable values are 0 ? 7. phase buffer segment 1 = (pseg1 + 1) x time-quanta. 13-15 pseg2 pseg2 ? phase segment 2 this 3-bit field defines the length of phase buffer segment 2 in the bit time. the valid programmable values are 1 ? 7. phase buffer segment 2 = (pseg2 + 1) x time-quanta. 16 boff_msk bus off mask this bit provides a mask for the bus off interrupt. 1= bus off interrupt enabled 0 = bus off interrupt disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-17 preliminary?subject to change without notice 17 err_msk error mask this bit provides a mask for the error interrupt. 1 = error interrupt enabled 0 = error interrupt disabled 18 clk_src can engine clock source this bit selects the clock source to the can protocol interface (cpi) to be either the peripheral clock (driven by the pll) or the crystal oscillator clock. the selected clock is the one fed to the prescaler to generate the serial clock (sclock). in order to guarantee reliable operation, this bit should only be changed while the module is in disable mode. see section 20.5.8.4, protocol timing for more information. 1 = the can engine clock source is the bus clock 0 = the can engine clock source is the oscillator clock note: this clock selection feature may not be available in all mcus. a particular mcu may not have a pll, in which case it would have only the o scillator clock, or it may use only the pll clock feeding the flexcan module. in these cases, this bit has no effect on the module operation. 19 twrn_msk tx warning interrupt mask this bit provides a mask for the tx warning interrupt associated with the twrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = tx warning interrupt enabled 0 = tx warning interrupt disabled 20 rwrn_msk rx warning interrupt mask this bit provides a mask for the rx warning interrupt associated with the rwrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = rx warning interrupt enabled 0 = rx warning interrupt disabled 21 lpb loop back this bit configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan b ehaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. 1 = loop back enabled 0 = loop back disabled 24 smp sampling mode this bit defines the sampling mode of can bits at the rx input. 1 = three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used 0 = just one sample is used to determine the bit value table 20-10. control register (ctr l) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 20-18 freescale semiconductor preliminary?subject to change without notice 20.4.4.3 free running timer (timer) this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flex can bit-clock (which de fines the baud rate on the can bus). during a message transmission/recepti on, it increments by one for each bit that is received or transmitted. when 25 boff_rec bus off recovery mode this bit defines how flexcan recovers from bus off state. if this bit is negated, automatic recovering from bus off state occu rs according to the can specification 2.0b. if the bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user. if the negation occurs before 128 sequences of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boff_rec bit had never been asserted. if the negation occurs after 128 sequen ces of 11 recessive bits occurred, then flexcan will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boff_rec bit can be re-asserted again during bus off, but it will only be effective the next time the module enters bus off. if boff_rec was negated when the module entered bus off, asserting it during bus off will not be effective for the current bus off recovery. 1 = automatic recovering fr om bus off state disabled 0 = automatic recovering from bus off state enabled, according to can spec 2.0 part b 26 tsyn timer sync mode this bit enables a mechanism that resets the fr ee-running timer each time a message is received in message buffer 0. this feature provides mean s to synchronize multiple flexcan stations with a special ?sync? message (i.e., global network time ). if the fen bit in mcr is set (fifo enabled), mb8 is used for timer synchronization instead of mb0. 1 = timer sync feature enabled 0 = timer sync feature disabled 27 lbuf lowest buffer transmitted first this bit defines the ordering mechanism for message buffer transmission. when asserted, the lprio_en bit does not affect the priority arbitration. 1 = lowest number buffer is transmitted first 0 = buffer with highest priority is transmitted first 28 lom listen-only mode this bit configures flexcan to operate in listen on ly mode. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode [ref. 1]. only messages acknowledged by another can station w ill be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. 1 = flexcan module operates in listen only mode 0 = listen only mode is deactivated 29-31 propseg propagation segment this 3-bit field defines the length of the pr opagation segment in the bit time. the valid programmable values are 0?7. propagation segment time = (propseg + 1) * time-quanta. time-quantum = one sclock period. 1 one time quantum is equal to the sclock period. table 20-10. control register (ctr l) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-19 preliminary?subject to change without notice there is no message on the bus, it counts using the previously program med baud rate. du ring freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. writing to the timer is an indirect operation. the data is first written to an auxili ary register and then an internal request/acknowledge procedur e across clock domains is executed. all this is transparent to the user, except for the fact that the da ta will take some time to be actuall y written to the register. if desired, software can poll the register to discove r when the data was actually written. 20.4.4.4 rx global mask (rxgmask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rxgmask regi ster to have no effect on the m odule operation. for mcus not supporting individual masks per mb, this re gister is always effective. rxgmask is used as acceptance mask for all rx mbs, excluding mbs 14 ? 15, which have individual mask registers. when the fen bit in mcr is set (fifo enabled), the rxgmask also applies to all elements of the id filter table, except elements 6-7, which have individual masks. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. to avoid mask misalignment for rx fifo, it is reco mmended to take one of the following actions for avoiding problems: base + 0x0008 0 1 2 3 4 5 6 7 8 9 101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset: 0000000000000000 = unimplemented or reserved figure 20-7. free running timer (timer)
pxd20 microcontroller reference manual, rev. 1 20-20 freescale semiconductor preliminary?subject to change without notice ? do not enable the rxfifo. if mcr[fen]=0 then the rx fifo is disabled and thus the ma sksrxgmask, rx14mask and rx15mask do not affect it. ? enable rx individual mask regist ers. if mcr[bcc] = 1, then the rximrs are enabled and thus th e masks rxgmask, rx14mask and rx15mask are not used. ? do not use masks rxgmask, rx 14mask and rx15mask (i.e., let the min reset value) when mcr[fe n] = 1 and mcr[bcc] = 0. in this case, filter in processes for both rx mbs and rxfifo are not affected by those masks. ? do not configure any mb as rx (i.e., le t all mbs as either tx or inactive) when mcr[fen] = 1 and mcr[bcc] = 0. in this case, the masks rxgmask, rx14mask and rx15mask can be usedto affect id tables without affecting fi ltering process for rx mbs. base + 0x0010 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi 26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 m i8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 1111111111111111 = unimplemented or reserved figure 20-8. rx global mask register (rxgmask) table 20-11. rx global mask regist er (rxgmask) field descriptions field description 0-31 mi31 - mi0 mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-21 preliminary?subject to change without notice 20.4.4.5 rx 14 mask (rx14mask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rx14mask register to ha ve no effect on the module operation. rx14mask is used as acceptance mask for the identi fier in message buffer 14. when the fen bit in mcr is set (fifo enabled), the rxg14mask also applies to element 6 of the id filt er table. this register has the same structure as the rx global mask regi ster. it must be programmed while the module is in freeze mode, and must not be m odified when the module is tr ansmitting or receiving frames. ? address offset: 0x14 ? reset value: 0xffff_ffff 20.4.4.6 rx 15 mask (rx15mask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rx15mask register to ha ve no effect on the module operation. when the bcc bit is negated, rx15mask is used as ac ceptance mask for the identifier in message buffer 15. when the fen bit in mcr is set (fifo enabled), the rxg14mask also applies to element 7 of the id filter table. this register has the same structure as the rx global ma sk register. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. ? address offset: 0x18 ? reset value: 0xffff_ffff 20.4.4.7 error counte r register (ecr) this register has 2 8-bit fields re flecting the value of two flexcan error counters: transmit error counter (tx_err_counter field) and receive error counter (rx_err_counter field) . the rules for increasing and decreasing these counters are descri bed in the can protocol and are completely implemented in the flexcan module. both counters are read only except in fr eeze mode, where they can be written by the cpu. writing to the error counter register while in free ze mode is an indirect ope ration. the data is first written to an auxiliary register an d then an internal request/acknowle dge procedure acro ss clock domains is executed. all this is transparent to the user, except for the fact that the data wi ll take some time to be actually written to the register. if desired, software can poll the regist er to discover when the data was actually written. flexcan responds to any bus state as described in th e protocol, e.g. transmit ?e rror active? or ?error passive? flag, delay its transmission start time (?error passive?) and avoid any influence on the bus when in ?bus off? state. the following are the basic rules for flexcan bus state transitions. ? if the value of tx_err_counter or rx_err_counter increases to be greater than or equal to 128, the flt_conf field in the error and status register is updated to reflect ?error passive? state.
pxd20 microcontroller reference manual, rev. 1 20-22 freescale semiconductor preliminary?subject to change without notice ? if the flexcan state is ?error passive?, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while the other already sati sfies this condition, the flt_conf field in the error and status register is updated to reflect ?error active? state. ? if the value of tx_err_c ounter increases to be greater than 255, the flt_conf field in the error and status register is updated to reflect ?bus off? state, and an interrupt may be issued. the value of tx_err_counter is then reset to zero. ? if flexcan is in ?bus off? state, then tx_err_co unter is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, tx_err_counter is reset to zero a nd counts in a manner where the in ternal counter counts 11 such bits and then wraps around wh ile incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the flt_conf field in th e error and status register is updated to be ?error active? and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal coun ter resets itself to zero without affecting the tx_err_counter value. ? if during system start-up, only one node is operati ng, then its tx_err_counter increases in each message it is trying to transmit, as a result of acknowledge erro rs (indicated by the ack_err bit in the error and status register). after the transi tion to ?error passive? state, the tx_err_counter does not increment anymore by acknow ledge errors. therefore the device never goes to the ?bus off? state. ? if the rx_err_counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to ?error active? state. base + 0x001c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_err_counter tx_err_counter w reset: 0000000000000000 = unimplemented or reserved figure 20-9. error counter register (ecr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-23 preliminary?subject to change without notice 20.4.4.8 error and status register (esr) this register reflects various error conditions, some genera l status of the de vice and it is th e source of four interrupts to the cpu. the reported er ror conditions (bits 16-21) are those th at occurred since the last time the cpu read this register. the cpu read acti on clears bits 16-21. bits 22-27 are status bits. most bits in this register ar e read only, except twrn_int, rwrn _int, boff_int and err_int, that are interrupt flags that can be cleared by writi ng ?1? to them (writing ?0? has no effect). see section 20.5.10, interrupts for more details. base + 0x0020 0123456789101112131415 r 00000000000000twrn _int rwrn _int w reset: 00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1_ err bit0_ err ack_ err crc_ err frm_ err stf_ err tx_w rn rx_w rn idle txrx flt_conf 0 boff _int err_ int 0 w reset: 00000000000000 0 0 = unimplemented or reserved figure 20-10. error and status register (esr) table 20-12. error and status register (esr) field descriptions field description 14 twrn_int tx warning interrupt flag if the wrn_en bit in mcr is asserted, the twrn_ int bit is set when the tx_wrn flag transition from ?0? to ?1?, meaning that the tx error coun ter reached 96. if the corresponding mask bit in the control register (twrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = the tx error counter transition from < 96 to ? 96 0 = no such occurrence 15 rwrn_int rx warning interrupt flag if the wrn_en bit in mcr is asserted, the rwrn_int bit is set when the rx_wrn flag transition from ?0? to ?1?, meaning that th e rx error counters reached 96. if the corresponding mask bit in the control register (rwrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = the rx error counter transition from < 96 to ? 96 0 = no such occurrence
pxd20 microcontroller reference manual, rev. 1 20-24 freescale semiconductor preliminary?subject to change without notice 16 bit1_err bit1 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as recessive is received as dominant 0 = no such occurrence note: this bit is not set by a transmitter in case of ar bitration field or ack slot, or in case of a node sending a passive error flag that detects dominant bits. 17 bit0_err bit0 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as dominant is received as recessive 0 = no such occurrence 18 ack_err acknowledge error this bit indicates that an acknowledge error has been detected by the transmitter node, i.e., a dominant bit has not been detected during the ack slot. 1 = an ack error occurred since last read of this register 0 = no such occurrence 19 crc_err cyclic redundancy check error this bit indicates that a crc error has been detect ed by the receiver node, i.e., the calculated crc is different from the received. 1 = a crc error occurred since last read of this register. 0 = no such occurrence 20 frm_err form error this bit indicates that a form error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 1 = a form error occurred since last read of this register 0 = no such occurrence 21 stf_err stuffing error this bit indicates that a stuffing error has been detected. 1 = a stuffing error occurred since last read of this register. 0 = no such occurrence. 22 tx_wrn tx error counter this bit indicates when repetitive errors are occurring during message transmission. 1 = tx_err_counter ? 96 0 = no such occurrence 23 rx_wrn rx error counter this bit indicates when repetitive errors are occurring during message reception. 1 = rx_err_counter ?? 96 0 = no such occurrence 24 idle can bus idle state this bit indicates when can bus is in idle state. 1 = can bus is now idle 0 = no such occurrence table 20-12. error and status register (esr) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-25 preliminary?subject to change without notice 20.4.4.9 interrupt mask register high (imrh) this register allows any num ber of a range of 32 message buffer in terrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to de termine which buffer generates an interrupt after a successful transmission or recep tion (i.e. when the corresponding ifrh bit is set). 25 txrx current flexcan status (transmitting/receiving) this bit indicates if flexcan is transmitting or receiving a message when the can bus is not in idle state. this bit has no meaning when idle is asserted. 1 = flexcan is transmitting a message (idle=0) 0 = flexcan is receiving a message (idle=0) 26-27 flt_conf fault confinement state this 2-bit field indicates the confinement state of the flexcan module, as shown in table 20-13 . if the lom bit in the control register is asserted, the flt_conf field will indicate ?error passive.? since the control register is not affected by soft reset, the flt_conf field will not be affected by soft reset if the lo m bit is asserted. 29 boff_int bus off? interrupt this bit is set when flexcan enters ?bus off? st ate. if the corresponding mask bit in the control register (boff_msk) is set, an interrupt is genera ted to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = flexcan module entered ?bus off? state 0 = no such occurrence 30 err_int error interrupt this bit indicates that at least one of the error bits (bits 16-21) is set. if the corresponding mask bit in the control register (err_msk) is set, an interr upt is generated to the cpu. this bit is cleared by writing it to ?1?.writing ?0? has no effect. 1 = indicates setting of any error bit in the error and status register 0 = no such occurrence 31 reserved table 20-13. fault confinement state value meaning 00 error active 01 error passive 1x bus off table 20-12. error and status register (esr) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 20-26 freescale semiconductor preliminary?subject to change without notice 20.4.4.10 interrupt mask register low (imrl) this register allows to enable or disable any number of a ra nge of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, en abling the cpu to determine which bu ffer generates an interrupt after a successful transmission or reception (i.e ., when the corresponding ifrl bit is set). base + 0x0024 0123456789101112131415 r buf 63m buf 62m buf 61m buf 60m buf 59m buf 58m buf 57m buf 56m buf 55m buf 54m buf 53m buf 52m buf 51m buf 50m buf 49m buf 48m w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47m buf 46m buf 45m buf 44m buf 43m buf 42m buf 41m buf 40m buf 39m buf 38m buf 37m buf 36m buf 35m buf 34m buf 33m buf 32m w reset: 0000000000000000 figure 20-11. interrupt mask register high (imrh) table 20-14. imrh field descriptions field description buf63m ? buf32m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb32 to mb63) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note: setting or clearing a bit in the imrh register can assert or negate an interrupt request, if the corresponding ifrh bit is set.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-27 preliminary?subject to change without notice 20.4.4.11 interrupt flag register high (ifrh) this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or re ception sets the corresponding ifrh bi t. if the corresponding imrh bit is set, an interrupt will be generated. the interrupt fl ag must be cleared by writi ng it to ?1?. writing ?0? has no effect. base + 0x0028 0 1 2 3 4 5 6 7 8 9 101112131415 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset: 0000000000000000 figure 20-12. interrupt mask register low (imrl) table 20-15. imrl field descriptions field description buf31m ? buf0m buf31m?buf0m ? buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb0 to mb31) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note: setting or clearing a bit in the imrl register can assert or negate an interrupt request, if the corresponding ifrl bit is set.
pxd20 microcontroller reference manual, rev. 1 20-28 freescale semiconductor preliminary?subject to change without notice 20.4.4.12 interrupt flag register low (ifrl) this register defines the flags fo r 32 message buffer interrupts and fi fo interrupts. it contains one interrupt flag bit per buffer. each successful transmis sion or reception sets the corresponding ifrl bit. if the corresponding imrl bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when the mcr[fen] is set (fifo enabled), the functi on of the 8 least significan t interrupt flags (buf7i - buf0i) is changed to support the fifo opera tion. buf7i, buf6i and bu f5i indicate operating conditions of the fifo, while buf4i to buf0i are not used. base + 0x002c 0123456789101112131415 r buf 63i buf 62i buf 61i buf 60i buf 59i buf 58i buf 57i buf 56i buf 55i buf 54i buf 53i buf 52i buf 51i buf 50i buf 49i buf 48i w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47i buf 46i buf 45i buf 44i buf 43i buf 42i buf 41i buf 40i buf 39i buf 38i buf 37i buf 36i buf 35i buf 34i buf 33i buf 32i w reset: 0000000000000000 figure 20-13. interrupt flag register high (ifrh) table 20-16. ifrh field descriptions field description buf32i ? buf63i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb32 to mb63) interrupt. 1 = the corresponding buffer has successfu lly completed transmission or reception 0 = no such occurrence
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-29 preliminary?subject to change without notice 20.4.4.13 rx individual mask registers (rximr0 ? rximr63) these registers are used as acceptan ce masks for id filtering in rx mbs and the fifo. if the fifo is not enabled, one mask register is provi ded for each available message buff er, providing id masking capability base + 0x0030 0123456789101112131415 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w reset: 0000000000000000 figure 20-14. interrupt flag register low (ifrl) table 20-17. ifrl field descriptions field description buf31i ? buf8i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb8 to mb31) interrupt. 1 = the corresponding mb has successfully completed transmission or reception 0 = no such occurrence buf7i buffer mb7 interrupt or ?fifo overflow? if the fifo is not enabled, this bit flags the inte rrupt for mb7. if the fifo is enabled, this flag indicates an overflow condition in the fi fo (frame lost because fifo is full). 1 = mb7 completed transmission/reception or fifo overflow 0 = no such occurrence buf6i buffer mb6 interrupt or ?fifo warning? if the fifo is not enabled, this bit flags the inte rrupt for mb6. if the fifo is enabled, this flag indicates that 4 out of 6 buffers of the fi fo are already occupied (fifo almost full). 1 = mb6 completed transmission/reception or fifo almost full 0 = no such occurrence buf5i buffer mb5 interrupt or ?frames available in fifo? if the fifo is not enabled, this bit flags the inte rrupt for mb5. if the fifo is enabled, this flag indicates that at least one frame is available to be read from the fifo. 1 = mb5 completed transmission/reception or frames available in the fifo 0 = no such occurrence buf4i ? buf0i buffer mb i interrupt or ?reserved? if the fifo is not enabled, these bits flag the inte rrupts for mb0 to mb4. if the fifo is enabled, these flags are not used and must be considered as reserved locations. 1 = corresponding mb completed transmission/reception 0 = no such occurrence
pxd20 microcontroller reference manual, rev. 1 20-30 freescale semiconductor preliminary?subject to change without notice on a per message buffer basis. when the fifo is en abled (fen bit in mcr is set), the first 8 mask registers apply to the 8 elements of the fifo filter table (on a one-t o-one correspondence), while the rest of the registers apply to the regular mbs, starting from mb8. the individual rx mask regi sters are implemented in ram, so they are not affected by reset and must be explicitly initialized prior to any reception. furtherm ore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesse s are blocked and read accesses will return ?all zeros.? furthermore, if the bcc bit in the mcr register is nega ted, any read or write operation to these registers results in access error. 20.5 functional description 20.5.1 overview the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox syst em is composed by a set of up to 64 message buffers (mb) that store configuration and control data, ti me stamp, message id and data (see section 20.4.2, message buffer structure ). the memory corresponding to the first 8 mbs can be configured to support a fifo reception scheme with a powerful id filteri ng mechanism, capable of checking in coming frames against a table of ids (up to 8 extended ids or 16 standard ids or 32 8-bi t id slices), each one wi th its own i ndividual mask register. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received frames only in to mbs that have the same id base + 0x0004 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi 26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 m i8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 0000000000000000 figure 20-15. rx individual mask registers (rximr0 - rximr63) table 20-18. rx individual mask registers (rximr0 - rximr63) field descriptions field description 0-31 mi31?mi0 mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-31 preliminary?subject to change without notice programmed on its id field. a masking scheme makes it possibl e to match the id programmed on the mb with a range of ids on received can frames. for tr ansmission, an arbitratio n algorithm decides the prioritization of mbs to be transm itted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?active? at a given time if it can participate in the matchi ng and arbitrat ion algorithms that are happening at that time. an rx mb with a ?0000? code is inactive (refer to table 20-5 ). similarly, a tx mb with a ?1000? or ?1001? c ode is also inac tive (refer to table 20-6 ). an mb not programmed with ?0000?, ?1000? or ?1001? will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section 20.5.6.1, message buffer deactivation ). 20.5.2 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: ? write the id word. ? write the data bytes. ? write the length, control and c ode fields of the control and status word to activate the mb. once the mb is activated in the fourth step, it will participate into the arbitrat ion process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag regi ster and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code fi eld after transmission de pends on the code that was used to activate the mb in step four (see table 20-5 and table 20-6 in section 20.4.2, message buffer structure ). 20.5.3 arbitration process the arbitration process is an algorithm executed by the mbm that scans th e whole mb memory looking for the highest priority message to be transmitted. all mbs program med as transmit buffers will be scanned to find the lowest id 1 or the lowest mb number or the hi ghest priority, depending on the lbuf and lprio_en bits on the control register. the arbitr ation process is triggered in the following events: ? during the crc field of the can frame ? during the error delimiter field of the can frame ? during intermission, if the winner mb defined in a previous arbitration was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of a ny mb after the previous arbitration finished ? when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb ? upon leaving freeze mode 1. actually, if lbuf is negated, the arbitration considers not only the id, but also the rtr and ide bits placed inside the id a t the same positions they are tr ansmitted in the can frame.
pxd20 microcontroller reference manual, rev. 1 20-32 freescale semiconductor preliminary?subject to change without notice when lbuf is asserted, the lprio_en bit has no effect and the lowest number buffer is transmitted first. when lbuf and lprio_en ar e both negated, the mb with the lowest id is transmitted fi rst but. if lbuf is negated and lprio_en is asserte d, the prio bits augment the id us ed during the arb itration process. with this extended id concept, arbi tration is done based on the full 32- bit id and the prio bits define which mb should be transmitted first, therefore mbs wi th prio = 000 have higher pr iority. if two or more mbs have the same priority, the regul ar id will determine th e priority of transmission. if two or more mbs have the same priority (3 extra bits) and the same regular id, the lowest mb will be transmitted first. once the highest priority mb is sel ected, it is transferred to a tem porary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called ?move-out? and after it is done, wr ite access to the corresponding mb is blocked (if the aen bit in mcr is asserted). the write access is released in the following events: ? after the mb is transmitted ? flexcan enters in halt or bus off ? flexcan loses the bus arbitration or th ere is an error during the transmission at the first opportunity window on the can bus, the me ssage on the smb is tran smitted according to the can protocol rules. flexc an transmits up to eight data bytes, even if the dlc (data length code) value is bigger. 20.5.4 receive process to be able to receive can frames into the mail box mbs, the cpu must prep are one or more message buffers for reception by executing the following steps: ? write the id word ? write ?0100? to the code field of the c ontrol and status word to activate the mb once the mb is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the mb is updated by the mbm as follows: ? the value of the free running timer is written into the time stamp field ? the received id, data (8 bytes at most) and length fields are stored ? the code field in the control and status word is updated (see table 20-5 and table 20-6 in section 20.4.2, message buffer structure ) ? a status flag is set in the interrupt flag regist er and an interrupt is generated if allowed by the corresponding interrupt mask register bit upon receiving the mb interrupt, the cpu should se rvice the received frame using the following procedure: ? read the control and status word (mandatory ? activates an internal lock for this buffer) ? read the id field (optional ? needed only if a mask was used) ? read the data field ? read the free running timer (optional ? releases the internal lock) upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until th is bit is negated. reading the free running timer is not mandatory. if
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-33 preliminary?subject to change without notice not executed the mb remains locke d, unless the cpu reads th e c/s word of another mb. note that only a single mb is locked at a time. th e only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 20.5.6, data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific mb in one of the interrupt flag (ifrl, ifrh) register s and not by the code fiel d of that mb. polling the code field does not work because once a frame was received and the cpu se rvices the mb (by readi ng the c/s word followed by unlocking the mb), the code field will not return to empty. it wi ll remain full, as explained in table 20-5 . if the cpu tries to workaround this behavior by writing to the c/s word to force an empty code after reading the mb, the mb is actually deactivated from any currently ongoing ma tching process. as a result, a newly received frame matching th e id of that mb may be lost. in summary: never do polling by reading directly the c/s word of the mbs. instead, read the in terrupt flag (ifrl, ifrh) registers. note that the received id field is al ways stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking. note also that flexcan does r eceive frames transmitted by itself if there exists an rx matching mb, provi ded the srx_dis bit in the mcr is not asserted. if srx_dis is asserted, flexcan will not store frames transmitted by itself in any mb, even if it contains a matching mb, and no interrupt flag or interrupt si gnal will be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enab le and configure the fifo during freeze mode (see section 20.5.7, rx fifo ). upon receiving the frames avai lable interrupt from fifo, the cpu should service the received fram e using the following procedure: ? read the control and status word (optional ? ne eded only if a mask wa s used for ide and rtr bits) ? read the id field (optional ? needed only if a mask was used) ? read the data field ? clear the frames available interr upt (mandatory ? release the buffe r and allow the cpu to read the next fifo entry) 20.5.5 matching process the matching process is an algorithm executed by th e mbm that scans the mb memory looking for rx mbs programmed with the same id as the one receiv ed from the can bus. if the fifo is enabled, the 8-entry id table from fifo is sca nned first and then, if a match is not found within the fifo table, the other mbs are scanned. in the event that the fifo is full, the matching algorithm will always look for a matching mb outside the fifo region. when the frame is received, it is te mporarily stored in a hi dden auxiliary mb called serial message buffer (smb). the matching process takes pl ace during the crc field of the receiv ed frame. if a matching id is found in the fifo table or in one of the regular mbs, the contents of the smb will be transferred to the fifo or to the matched mb during the 6th bit of the end-of-frame field of the can protocol. this operation is called ?move-in.? if a ny protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox mbs, an mb is said to be ?free to receive? a new frame if the following conditions are satisfied:
pxd20 microcontroller reference manual, rev. 1 20-34 freescale semiconductor preliminary?subject to change without notice ? the mb is not locked (see section 20.5.6.2, message buffer lock mechanism ) ? the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb) if the first mb with a matching id is not ?free to receive? the new frame, then the matching algorithm keeps looking for another free mb until it finds one. if it can not find one that is fr ee, then it will overwrite the last matching mb (unless it is locked) and set the code field to overrun (refer to table 20-5 and table 20-6 ). if the last matching mb is locked, then th e new message remains in the smb, waiting for the mb to be unlocked (see section 20.5.6.2, message buffer lock mechanism ). suppose, for example, that the fifo is disabled a nd there are two mbs with the same id, and flexcan starts receiving messages with that id. let us say that these mbs are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code of this mb is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 again, but it is not ?free to receive,? so it will keep looking and find mb number 5 and store the message there. if yet anothe r message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are ?free to receiv e,? so it decides to overwrite the last matched mb, which is number 5. in doing so, it se ts the code field of th e mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fi fo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received me ssages will be queued into the mbs. the cpu can examine the time stamp field of the mbs to dete rmine the order in which the messages arrived. the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the bcc bit in mcr is negated, the matchi ng algorithm stops at the first mb with a matching id that it founds, whether this mb is free or not. as a result, the message queueing feature does not work if the bcc bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. please refer to section 20.4.4.13, rx individual mask registers (rximr0?rximr63) . during the matching algorithm, if a ma sk bit is asserted, th en the corresponding id bi t is compared. if the mask bit is negated, the corresponding id bit is ?d on?t care.? please note th at the individual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed if the bcc bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking sche me with only three mask registers (rgxmask, rx14mask and rx15mask) for backwards compatibilit y. this alternate masking scheme is enabled when the bcc bit in the mcr register is negated. 20.5.6 data coherence in order to maintain data cohere ncy and flexcan proper ope ration, the cpu must obe y the rules described in transmit process and section 20.5.4, receive process . any form of cpu accessing an mb structure within flexcan other than those specified may ca use flexcan to behave in an unpredictable way.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-35 preliminary?subject to change without notice 20.5.6.1 message buffer deactivation deactivation is mechanism pr ovided to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the control and status word of an mb causes that mb to be excluded from the tran smit or receive processes during the current matching or arbitration round. the de activation is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb ma y no longer be coherent, therefore de activation of that mb is done. even with the coherence mechanism described above, writing to the control and status word of active mbs when not in freeze mode may produ ce undesirable results. examples are: ? matching and arbitration are one-p ass processes. if mbs are deactivated after they are scanned, no re-evaluation is done to determine a new match/ winner. if an rx mb with a matching id is deactivated during the matching proce ss after it was scanned, then this mb is marked as invalid to receive the frame, and flexcan wi ll keep looking for another matc hing mb within the ones it has not scanned yet. if it can not find one, then the message will be lost . suppose, for example, that two mbs have a matching id to a recei ved frame, and the user deactivat ed the first matching mb after flexcan has scanned the second. the received frame will be lost ev en if the second matching mb was ?free to receive.? ? if a tx mb containing th e lowest id is deactivated after fl excan has scanned it, then flexcan will look for another winner within the mbs that it has not scanned yet. ther efore, it may transmit an mb with id that may not be the lowest at the time because a lo wer id might be present in one of the mbs that it had already scanned before the deactivation. ? there is a point in time until which the deactivati on of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not updated. 20.5.6.2 message buffer lock mechanism besides mb deactivation, flexcan ha s another data coherence mechanis m for the receive process. when the cpu reads the control and status word of an ?active not empty? rx mb, flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb. th e mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note the locking mechanism only applies to rx mbs which have a code different than inactive (?0000?) or empty 1 (?0100?). also, tx mbs can not be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two 1. in previous flexcan versions, reading the c/s word locked the mb even if it was empty. this behavior will be honoured when the bcc bit is negated.
pxd20 microcontroller reference manual, rev. 1 20-36 freescale semiconductor preliminary?subject to change without notice mbs. suppose now that the cpu decide s to read mb number 5 and at th e same time another message with the same id is arriving. when the cpu reads the cont rol and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no ?free to receive? mbs, so it decides to override mb number 5. however, this mb is lock ed, so the new me ssage can not be written there. it will remain in the smb waiting fo r the mb to be unlocked, a nd only then will be written to the mb. if the mb is not unlocke d in time and yet anothe r new message with the same id arrives, then the new message overwrites th e one on the smb and there wi ll be no indication of lo st messages either in the code field of the mb or in the error and status register. while the message is being moved-in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. deactivation takes precedence over lock ing. if the cpu deactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid fo r the current matching round. any pending message on the smb will not be transferred anymore to the mb. 20.5.7 rx fifo the receive-only fifo is enabled by a sserting the fen bit in the mcr. the reset value of this bit is zero to maintain software backwards comp atibility with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the me mory region normally occ upied by the first 8 mbs (0x80-0xff) is now reserved for use of the fifo engine (see section 20.4.3, rx fifo structure ). management of read and write pointers is done inte rnally by the fifo engine. the cpu can read the received frames sequentially, in the order they we re received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store up to six frames pending service by the cpu. an interrupt is sent to the cpu when new frames are available in the fifo. upon receiv ing the interrupt, the cpu must read the frame (accessing an mb in the 0x80 address) a nd then clear the interrupt. the act of clearing the interrupt triggers the fifo engine to replace the mb in 0x80 with the next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more fram es. a warning interrupt is also generated when four frames are accumulated in the fifo. a powerful filtering scheme is provided to accept onl y frames intended for the target application, thus reducing the interrupt servicing work load. the filtering criteria is sp ecified by programmin g a table of 8 32-bit registers that can be configured to one of the following formats (see also section 20.4.3, rx fifo structure ): ? format a: 8 extended or standard ids (including ide and rtr) ? format b: 16 standard ids or 16 extended 14-bit id slices (i ncluding ide and rtr) ? format c: 32 standard or extended 8-bit id slices
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-37 preliminary?subject to change without notice note a chosen format is applied to all eight re gisters of the filter table. it is not possible to mix formats within the table. the eight elements of the filter ta ble are individually affected by the first eight individual mask registers (rximr0 - rximr7), allowing very powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affe ct the regular mbs, starting from mb8. if the bcc bit is negated (or if the rximr are not available for the particular mcu), then the fifo filt er table is affected by the legacy mask registers as follows: elem ent 6 is affected by rx14mask, el ement 7 is affected by rx15mask and the other elements (0 to 5) are affected by rxgmask. 20.5.8 can protocol related features 20.5.8.1 remote frames remote frame is a special kind of frame. the user can program a mb to be a request remote frame by writing the mb as transmit with th e rtr bit set to ?1?. after the remote request frame is transmitted successfully, the mb becomes a receive message buffer, with the same id as before. when a remote request frame is received by flexcan, its id is compared to the ids of the transmit message buffers with the code fi eld ?1010?. if there is a matching id, then this mb frame will be transmitted. note that if the matching mb has the rt r bit set, then flexcan will transmit a remote frame as a response. a received remote request frame is no t stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask re gisters are not used in remote fram e matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was r eceived and matched an mb, this message buffer immediately enters the internal arbi tration process, but is considered as normal tx mb, with no higher priority. the data length of this fr ame is independent of the dlc field in the remote frame that initiated its transmission. if the rx fifo is enabled (bit fen set in mcr), flexcan will not generate an automatic response for remote request frames that match the fifo filteri ng criteria. if the remote frame matches one of the target ids, it will be stor ed in the fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select wh ether remote frames are ac cepted or not. for format c, remote frames are always accepted (if they match the id). 20.5.8.2 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: ? detection of a dominant bit in th e first/second bit of intermission ? detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) ? detection of a dominant bit at th e 8th bit (last) of error fram e delimiter or overload frame delimiter
pxd20 microcontroller reference manual, rev. 1 20-38 freescale semiconductor preliminary?subject to change without notice 20.5.8.3 time stamp the value of the free running timer is sampled at the beginning of th e identifier field on the can bus, and is stored at the end of ?move -in? in the time stamp field, provi ding network behavior with respect to time. note that the free running timer can be reset upon a specific frame recepti on, enabling network time synchronization. refer to tsyn description in section 20.4.4.2, control register (ctrl) . 20.5.8.4 protocol timing figure 20-16 shows the structure of the clock generation ci rcuitry that feeds the can protocol interface (cpi) sub-module. the clock source bit (clk_src) in the ctrl register defines whether the internal clock is connected to the output of a crystal oscill ator (oscillator clock) or to the peripheral clock (generally from a pll). in order to guarantee reliable opera tion, the clock source s hould be selected while the module is in disable mode (bit mdis set in the module c onfiguration register). figure 20-16. can engine clocking scheme the crystal oscillator cloc k should be selected whenever a tight to lerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter pe rformance than pll generated clocks. note this clock selection featur e may not be available in all mcus. a particular mcu may not have a pll, in which case it would have only the oscillator clock, or it may use only the pll cl ock feeding the flexcan module. in these cases, the clk_src bit in the ctrl register has no effect on the module operation. the flexcan module supports a variet y of means to setup bi t timing parameters th at are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2 and rjw. see section 20.4.4.2, control register (ctrl) . the presdiv field controls a prescal er that generates the serial cloc k (sclock), whose period defines the ?time quantum? used to compose th e can waveform. a time quantum is the atomic unit of time handled by the can engine. peripheral clock (pll) oscillator clock (xtal) clk_src prescaler (1 .. 256) sclock cpi clock f tq f canclk prescaler v alue t ?? ---------------------- ----------------- ---------------- - =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-39 preliminary?subject to change without notice a bit time is subdivided into three segments 1 (reference figure 20-17 and table 20-19 ): ? sync_seg: this segment has a fixed length of one time quantum. signal e dges are expected to happen within this section ? time segment 1: this segment includes the propa gation segment and the phase segment 1 of the can standard. it can be program med by setting the propseg and th e pseg1 fields of the ctrl register so that their sum (plus 2) is in the range of 4 to 16 time quanta ? time segment 2: this segment represents the ph ase segment 2 of the can standard. it can be programmed by setting the pse g2 field of the ctrl register (plu s 1) to be 2 to 8 time quanta long figure 20-17. segments within the bit time table 20-20 gives an overview of the can compliant segmen t settings and the related parameter values. 1. for further explanation of the underlying concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol specification dated september 1991 for bit timing. table 20-19. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. bit rate f tq number of time quanta tt t ?? ------------------- ------------------ ----------------- ------------------ ---------------- - = t sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point
pxd20 microcontroller reference manual, rev. 1 20-40 freescale semiconductor preliminary?subject to change without notice note it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. 20.5.8.5 arbitration a nd matching timing during normal transmission or rece ption of frames, the arbitrati on, matching, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in figure 20-18 . figure 20-18. arbitration, match and move time windows when doing matching and arbitration, flexcan needs to scan the whole message bu ffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: ? a valid can bit timing must be programmed, as indicated in table 20-20 ? the peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e. the pll can not be programmed to divi de down the oscillator clock ? there must be a minimum ratio between the peri pheral clock frequency and the can bit rate, as specified in table 20-21 table 20-20. can standard compliant bit time segment settings time segment 1 time segment 2 resynchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-41 preliminary?subject to change without notice a direct consequence of the first re quirement is that the minimum numbe r of time quanta per can bit must be 8, so the oscillator cl ock frequency should be at least 8 times the can bit ra te. the minimum frequency ratio specified in table 20-21 can be achieved by choosing a high e nough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 mbs, if the oscillator and peripheral clock frequencies are e qual and the can bit timing is progr ammed to have 8 time quanta per bit, then the prescaler factor (pre sdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 time quanta per bit, the ratio between peripheral and os cillator clock frequencies should be at least 2. 20.5.9 modes of operation: details 20.5.9.1 freeze mode this mode is entered by asserting the halt bit in the mcr register or when the mcu is put into debug mode. in both cases it is also n ecessary that the frz bit is asserted in the mcr register and the module is not in any of the low power modes (disable, stop) . when freeze mode is re quested during transmission or reception, flexcan does the following: ? waits to be in either intermission, passive error, bus off or idle state ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores the rx input pin and dr ives the tx pin as recessive ? stops the prescaler, thus halt ing all can prot ocol activities ? grants write access to the erro r counters register, which is read-only in other modes ? sets the not_rdy and frz_ack bits in mcr after requesting freeze mode, the us er must wait for the frz_ack bit to be asserted in mcr before executing any other action, otherwise flexcan may operate in an unpredic table way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: ? cpu negates the frz bit in the mcr register ? the mcu is removed from debug mode and/or the halt bit is negated once out of freeze mode, fl excan tries to resynchronize to the can bus by waiting fo r 11 consecutive recessive bits. table 20-21. minimum ratio between peri pheral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16
pxd20 microcontroller reference manual, rev. 1 20-42 freescale semiconductor preliminary?subject to change without notice 20.5.9.2 module disable mode this low power mode is entered when the mdis bit in the mcr register is asserted. if the module is disabled during freeze mode, it shuts down the clocks to the cpi and mbm sub-modules, sets the lpm_ack bit and negates the frz_ack bit. if the m odule is disabled during tr ansmission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for th e third bit of intermission and then checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? shuts down the clocks to the cpi and mbm sub-modules ? sets the not_rdy and lpm_ack bits in mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register and the message buffers, which cannot be accessed when the module is in disable mode . exiting from this mode is done by negating the mdis bit, which will resume the clocks and negate the lpm_ack bit. 20.5.10 interrupts the module can generate up to 8 inte rrupt sources (6 interrupts due to message buffers a nd 2 interrupts due to ored interrupts from mbs, bus off, error, tx warning, and rx warning. the individual mb interrupts are grouped as follows: ? groups of four interrupts (up to mb 16) ? mb16_31 ? mb32_63 these are then used as the interrupt source. each one of the message buffers can be an interrupt s ource, if its corresponding ma sk bit is set. there is no distinction between tx and rx in terrupts for a particular buffer, unde r the assumption that the buffer is initialized for either transmission or reception. each of the buffers has assigned a flag bit in the ifrl or ifrh registers. the bit is set when the corresponding buffer completes a successf ul transmission/reception and is cleared when the cpu writes it to ?1? (unles s another interrupt is gene rated at the same time). note it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulati on instructions (bset) must not be used to clear interrupt flags. thes e instructions may cause accidental clearing of interrupt flags which are se t after entering the current interrupt service routine. if the rx fifo is enable d (mcr[fen] bit set), the interrupts corr esponding to mbs 0 to 7 have a different behavior. bit 7 of the ifrl become s the ?fifo overflow? flag; bit 6 b ecomes the fifo warning flag, bit
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-43 preliminary?subject to change without notice 5 becomes the ?frames available in fi fo flag? and bits 4-0 are unused. see section 20.4.4.12, interrupt flag register low (ifrl) for more information. a combined interrupt for all mbs is also generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs generate s an interrupt. in this case the cpu must read the ifrl and ifrh registers to determ ine which mb caused the interrupt. the other 4 interrupt sources (bus off, error, tx wa rning, and rx warning) generate interrupts like the mb ones, and can be read from th e error and status register. the bu s off, error, tx warning and rx warning interrupt mask bits are located in the control register. 20.5.11 bus interface the cpu access to flexcan registers ar e subject to the following rules: ? read and write access to supe rvisor registers in user mo de results in access error. ? read and write access to unimplement ed or reserved address space al so results in access error. any access to unimplemented mb or rx individual mask regist er locations results in access error. any access to the rx individual mask register space when the bcc bit in mcr is negated results in access error. ? if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general pu rpose ram space. note that the rx individual mask registers can only be accessed in freeze mode , and this is still true for unused space within this memory. note also that re served words within ram cannot be used. as an example, suppose flexcan is configured with 64 mbs and maxmb is program med with zero. the maximum number of mbs in this case b ecomes one. the mb memory star ts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space fr om 0x0080 to 0x008f is used by the one mb. this leaves us wi th the available space from 0x0090 to 0x047f. the available memory in the mask registers space would be from 0x0884 to 0x097f. note unused mb space must not be us ed as general purpose ram while flexcan is transmitting an d receiving can frames. 20.6 initialization/application information this section provide instructions for initializing the flexcan module. 20.6.1 flexcan initialization sequence the flexcan module may be reset in three ways: ? mcu level hard reset, which resets all memory mapped re gisters asynchronously ? mcu level soft reset, which rese ts some of the memory mapped re gisters synchronous ly (refer to table 20-2 to see what registers are affected by soft reset) ? soft_rst bit in mcr, which has the same effect as the mcu level soft reset
pxd20 microcontroller reference manual, rev. 1 20-44 freescale semiconductor preliminary?subject to change without notice soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to full y propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while clocks ar e shut down in any of the low power modes. the low power mode should be exited and the cloc ks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disa ble mode. after the clock source is selected and the module is enabled (mdis bit negated), fl excan automatically goes to freeze mode. in freeze mode, flexcan is un-synchronized to the can bus, the halt and frz bits in mcr register are set, the internal state machines ar e disabled and the frz_ack and not_rdy bits in the mcr register are set. the tx pin is in recessive state a nd flexcan does not initi ate any transmission or reception of can frames. note that the message buffers and the rx in dividual mask registers are not affected by reset, so they ar e not automatically initialized. for any configuration change/initialization it is re quired that flexcan is put into freeze mode (see section 20.5.9.1, freeze mode ). the following is a ge neric initialization seque nce applicable to the flexcan module: ? initialize the module configuration register ? enable the individual filtering per mb and r eception queue features by setting the bcc bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self re ception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the local priority feature by setting the lprio_en bit ? initialize the control register ? determine the bit timing parame ters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field ? determine the internal ar bitration mode (lbuf bit) ? initialize the message buffers ? the control and status word of all message buffers must be initialized ? if fifo was enabled, the 8-entr y id table must be initialized ? other entries in each message buffer should be initialized as required ? initialize the rx individual mask registers ? set required interrupt mask bits in the mask registers (for all mb interrupts) and in ctrl register (for bus off and error interrupts) ? negate the mcr[halt] bit starting with the last event, flexcan attempts to synchronize to the can bus. 20.6.2 flexcan addressing an d ram size configurations there are 3 ram configurations that can be impl emented within the flexcan module. the possible configurations are: ? for 16 mbs: 288 bytes for mb memory an d 64 bytes for individual mask registers
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 20-45 preliminary?subject to change without notice ? for 32 mbs: 544 bytes for mb memory an d 128 bytes for individual mask registers ? for 64 mbs: 1056 bytes for mb memory a nd 256 bytes for individual mask registers in each configuration the user ca n program the maximum number of mbs that will take part in the matching and arbitration proce sses using the maxmb field in the mcr register. for 16 mb configuration, maxmb can be any number between 0?15. for 32 mb configuration, maxmb can be any number between 0?31. for 64 mb configura tion, maxmb can be a ny number between 0 ? 63.
pxd20 microcontroller reference manual, rev. 1 20-46 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-1 preliminary?subject to change without notice chapter 21 flash memory 21.1 introduction this chapter presents information about the following components on this device: ? the 2 mb flash memory module ? the 2-port platform flash me mory controller (pflash2p) the primary function of the flash memory is to serve as electrically programmable and erasable non-volatile memory. the nvm memory can be used fo r instruction and data storage. the flash is a non-volatile solid-state silicon memory device consisting of blocks of si ngle-transistor storage elements, an electrical means for selectively adding (programming) and re moving (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. the flash is addressable by word (32 bits) and page (128 bits). the flash memory module is arranged as two main f unctional units. the first functional unit is the flash core (fc). the fc is composed of arrayed non-volatile stor age elements, sense amp lifiers, row selects, column selects, charge pumps, a nd redundancy logic. the arrayed st orage elements in the fc are sub-divided into physically separate units referred to as blocks. the second functional unit of the flash is the memory interface (mi). the mi contains the registers and logic which control the operation of the fc. the mi is also the interface to the platform flash memory controller (pflash2p). the pflash2p has two ahb-lite slav e ports enabling efficient used of a single flash memory module by multiple ahb masters. each ahb po rt has dedicated line buffers to support single cycle read accesses and to limit accesses to the flash ar ray. port0 of the pflash2p is dedi cated for cpu accesses to the flash. port1 of the pflash2p is for all othe r ahb master accesses to the flash 21.1.1 block diagram figure 21-1 shows a block diagram of the flash memory module. the pflash2p is addressed through the system bus while the flash control and status registers ar e addressed through the slave (peripheral) bus.
pxd20 microcontroller reference manual, rev. 1 21-2 freescale semiconductor preliminary?subject to change without notice figure 21-1. flash system block diagram 21.1.2 flash memory block segmentation the flash memory core has three address spaces. th e low-address space is 256 kb. the mid-address space is also 256 kb. the high-address space is 1.5 mb. the 256 kb of low memory is implemented using eight 16 kb blocks and two 64 kb blocks. the mid-addre ss memory is implemented using two 128 kb blocks. the high memory is implemente d using three 512 kb blocks. figure 21-2 shows the segmentation for the flash memory on pxd20. platform (pflash2p) flash memory flash memory module flash core control/status registers interface (mi) v flash v ss v dd slave bus system bus (fc) flash controller system bus port 0 port 1 (cpu instruction)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-3 preliminary?subject to change without notice figure 21-2. flash memory segmentation 21.1.3 features the flash memory has these major features: ? 2mb of flash memory configured with 8 x 16k b, 2 x 64kb, 2 x 128kb and 6 x 256kb blocks. ? support for a 64-bit data bus for instruction fetch, cpu data, dma and display controller (dcu accesses). ? byte, halfword, word and doubleword reads ar e supported. only aligned word and doubleword writes are supported. ? configurable read buffering and line prefetch support. two sets of f our line read buf fers (128 bits wide) and a prefetch controller are used to s upport single-cycle read responses for hits in the buffers. ? hardware and software configur able read and write access protec tions on a per-master basis. ? interface to the flash array c ontroller is pipelined with a dept h of 1, allowing overlapped accesses to proceed in parallel for interleave d or pipelined flash array designs. ? configurable access timing allowing use in a wide range of system frequencies. ? multiple-mapping support and mapping-based bl ock access timing (0-31 additional cycles) allowing use for emulati on of other memory types. low-address space high-address space mid-address space flash memory array blocks low-address space???256 k mid-address space???256 k high-address space???1.5 8 x 16 kb + 2 x 64 kb 2 x 128 kb 2x256kb 2x256kb 2x256kb
pxd20 microcontroller reference manual, rev. 1 21-4 freescale semiconductor preliminary?subject to change without notice ? software programmable block progr am/erase restriction control for low, mid and high address spaces. ? erase of selected block(s). ? read page size of 128 bits (4 words). ? ecc with single-bit corr ection, double-bit detection. ? minimum program size is 2 cons ecutive 32 bit words, aligned on a 0-modulo-8 byte address, due to ecc. ? embedded hardware program and erase algorithm. ? read while write (rww) with multiple partitions. ? sleep mode for low power stand-by. ? erase suspend, program suspe nd and erase-suspended program. ? automotive flash which meets automotive endurance and reliability requirements. ? shadow information stored in non-volatile shadow block. 21.1.4 modes of operation the flash module supports the following modes of operation: 21.1.4.1 flash user mode user mode is the default operating mode of the flash module. in this mode , it is possible to read and write, program and erase the flash module. 21.1.4.2 low power mode in low power mode the flash memory module turns of f most current sources, although logic/charge pumps to enable quick recovery to read are enabled for faster wake up time than power down mode. 21.1.4.3 power down mode in power down mode, the flash module turns off all dc current sources and no reads from or writes to the module and registers are possible. all power di ssipation is due to leakage in this mode. 21.1.4.4 user test mode (utest) user test mode (utest) provides a li mited set of tests to end users. 21.2 external signal description there are no external signals for the flash module but it should be noted that the vdde_b i/o supply is shared with the flash module. see chapter 3, signal description.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-5 preliminary?subject to change without notice 21.3 memory map and registers this section provides a detailed description of all flash memory and pflash2p registers. 21.3.1 module memory map the flash memory map is shown in table 21-1 . the addresses are given as an offset to the flash memory base address. the flash register memory map is shown in table 21-2 . there are no program-vis ible registers that physically reside inside the flash. the flash receives control and configuration in formation from the flash array controller to determine opera ting configurations. thes e are part of the flas h array controller?s configuration registers mapped into the ips address space but are described herein. these registers should only be referenced with 32-bit acce sses. also included in the flash memory map is a block that contains non-volatile configuration values that are used to initialize certain fl ash and soc features. this is known as the shadow flash and is included in this table for completeness but is not intended for storage of user program or data. table 21-1. flash memory map offset from flash_base (0x0000_0000) use block 1 partition 0x0000_0000 low-address space l0 1 0x0000_4000 l1 0x0000_8000 l2 0x0000_c000 l3 0x0001_0000 l4 2 0x0001_4000 l5 0x0001_8000 l6 0x0001_c000 l7 0x0002_0000 l8 3 0x0003_0000 l9 0x0004_0000 mid-address space m0 4 0x0006_0000 m1 0x0008_0000 high-address space h0 5 0x000c_0000 h1 0x0010_0000 h2 6 0x0014_0000 h3 0x0018_0000 h4 7 0x001c_0000 h5 0x0020_0000?0x00ff_bfff reserved
pxd20 microcontroller reference manual, rev. 1 21-6 freescale semiconductor preliminary?subject to change without notice 0x00ff_c000?0x00ff_fdd7 general use s all 2 0x00ff_fdd8 serial passcode (0xfeed_face_cafe_beef) 0x00ff_fde0 censorship control word (0x55aa_55aa) 0x00ff_fde4 general use 0x00ff_fde8 lml reset configuration (0x0010_0000) 0x00ff_fdec general use 0x00ff_fdf0 hbl reset configuration (0x0fff_ffff) 0x00ff_fdf4 general use 0x00ff_fdf8 sll reset conf iguration (0x000f_ffff) 0x00ff_fdfc general use 0x00ff_fe00 pfapr reset configuration 0x00ff_fe04 general use 0x00ff_fe08 pfsacc reset configuration 0x00ff_fe0c general use 0x00ff_fe10 nvusro register 0x00ff_fe20 - 0x00ff_ffff general use 1 l n = low address space, m n = mid address space, h n = high address space, s = shadow block. 2 for read while write operations, the shadow ro w behaves as if it is in all partitions. table 21-2. flash memory config uration register memory map offset from flash_regs_base (0xc3f8_8000) register location 0x0000 mcr?module configuration register on page 21-7 0x0004 lml?low-/mid-address space block locking register on page 21-11 0x0008 hbl?high-address space block locking register on page 21-12 0x000c sll?secondary low-/mid-address space block locking register on page 21-13 0x0010 lms?low-/mid-address s pace block select register on page 21-14 0x0014 hbs?high-address space block select register on page 21-15 0x0018 adr?address register on page 21-16 0x001c pfcrp0?platform flash configuration register for port 0 on page 21-17 0x0020 pfcrp1?platform flash configuration register for port 1 on page 21-17 0x0024 pfapr?platform flash access protection register on page 21-20 0x0028 pfsacc?platform flash supervisor access control register on page 21-21 0x002c pfdacc?platform flash data access control register on page 21-23 table 21-1. flash memory map (continued) offset from flash_base (0x0000_0000) use block 1 partition
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-7 preliminary?subject to change without notice 21.3.2 register descriptions this section lists the flash memory re gisters in address order and describes the register s and their bit fields. 21.3.2.1 module configur ation register (mcr) the mcr register is shown in figure 21-3 and table 21-3 . 0x0030 ? 0x0038 reserved 0x003c ut0?utest register 0 on page 21-23 0x0040 ut0?utest register 1 on page 21-25 0x0044 ut0?utest register 2 on page 21-26 0x0048 um0?user multiple i nput signature register 0 on page 21-26 0x004c um1?user multiple i nput signature register 1 on page 21-26 0x0050 um2?user multiple i nput signature register 2 on page 21-26 0x0054 um3?user multiple i nput signature register 3 on page 21-26 0x0058 um4?user multiple i nput signature register 4 on page 21-26 0x0048 ? 0x3fff reserved offset: flash_regs_base + 0x0000 access: user read/write 01234 56789101112131415 r00000 size 0 las 000mas w reset0000010101000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eer rwe sbc 0 peas done peg 0000 pgm psus ers esus ehv w w1c w1c w1c reset000001100 0000000 figure 21-3. module configuration register (mcr) table 21-2. flash memory configuration register memory map (continued) offset from flash_regs_base (0xc3f8_8000) register location
pxd20 microcontroller reference manual, rev. 1 21-8 freescale semiconductor preliminary?subject to change without notice table 21-3. mcr field descriptions field description size array space size. the value of the size field depends on the size of the flash module. for pxd20, this bit field is 0b101, indicating a 2.0 mb array size (with 1.5 mb in high-address space). size is read only. las low address space. the value of the las field correspo nds to the configuration of the low address space. for pxd20, this bit field is 0b100, indicating eight 16 kb blocks and two 64 kb blocks. las is read only. mas mid address space. the value of the mas field corresp onds to the configuration of the mid address space. the value of the mas field depends on the size of the flash module. for pxd20, this bit field is 0b0, indicating two 128 kb blocks. mas is read only. eer ecc event error. eer provides information on previous reads. if a double bit detection occurred, the eer bit is set to a 1. this bit must then be cleared, or a reset must occur before this bit returns to a 0 state. this bit may not be set by the user. in the event of a single bit detection and corre ction, this bit is not be set. if eer is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of eer) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0 reads are occurring normally. 1 an ecc error occurred during a previous read. rwe read while write event error. rwe provides informatio n on previous rww reads. if a read while write error occurs, this bit is set to 1. this bi t must then be cleared, or a reset must oc cur before this bit returns to a 0 state. this bit may not be written to a 1 by the user. if rwe is no t set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) are correct. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register loca tion. a write of 0 has no effect. 0 reads are occurring normally. 1 a read while write error occurred during a previous read. sbc single bit correction. sbc provides information on previous reads provided the ut0[spce] is set. if a single bit correction occurred, the sbc bit is set to a 1. this bit mu st then be cleared, or a reset must occur before this bit returns to a 0 state. if sbc is not set, or remains 0, this indicates that all previous re ads (from the last reset, or clearing of sbc) did not require a correction. since this bit is an error flag, it must be cleared to a 0 by writing a 1 to the register location. a write of 0 has no effect. 0 reads are occurring without corrections. 1 a single bit correction occurred during a previous read. peas program/erase access space. peas is us ed to indica te which space is valid for program and erase operations, either main array space or shadow space. peas = 0 indicates that the main address space is active for all fc program and erase operations. peas = 1 indicates the shad ow address space is active for program/erase. the value in peas is captured and held when the shadow block is enabled with the first interlock write done for program or erase operations. the value of peas is retained betw een sampling events (i.e.,subsequent first interlock writes). the value in peas may be changed during erase-suspended program, and reverts back to its original state once the erase-suspended program is completed. peas is read only. 0 shadow address space is disabled for program/erase and main address space enabled. 1 shadow address space is enabled for program/erase and main address space disabled. done state machine status. indicates if the flash module is performing a high-voltage operation. done is set to a 1 on termination of the flash module reset, at the end of program and erase high-voltage sequences and after a successful abort of a high voltage operation. done is cl eared upon commencement of a high voltage operation or on the resumption of a suspended operation. 0 flash is executing a high-voltage operation 1 flash is not executing a high-voltage operation
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-9 preliminary?subject to change without notice peg program/erase good. the peg bit indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/eras e high voltage operation causes peg to be cleared, indicating the sequence failed. peg is set to a 1 when the module is reset. peg is read only. the value of peg is valid only when pgm = 1 and/or ers = 1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase operation. peg is va lid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by psus or esus being set to logic 1. if pgm and ers are both 1 when done makes a qualifying 0 to 1 transition the value of peg indicates the completion status of the pgm sequence. this happens in an erase-suspended program operation. 0 program or erase operation failed. 1 program or erase operation successful. note: if program or erases are attempted on blocks that are locked, the response from flash is peg = 1, indicating that the operation was successful, and the contents of t he block are properly protected from the program or erase operation. pgm program. pgm is used to set up flash for a program op eration. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under one of the following conditions: ? user mode read (ers is low and ute is low). ? erase suspend (ers and esus are 1) with ehv low. pgm can be cleared by the user only when psus and ehv are low and done is high. pgm is cleared on reset. 0 flash is not executing a program sequence. 1 flash is executing a program sequence. note: in an erase-suspended program, programming flash locati ons in blocks which were being operated on in the erase may corrupt fc data. this should be avoided due to reliability implications. psus program suspend. psus is used to indicate the flash module is in program suspend or in the process of entering a suspend state. the module is in program susp end when psus = 1 and done = 1. psus can be set high only when pgm and ehv are high. a 0 to 1 transition of psus starts the sequence which sets done and places the flash module in program suspend. psus can be cleared only when done and ehv are high. a 1 to 0 transition of psus with ehv = 1 starts the sequence which clears done and returns the flash module to program. the module ca nnot exit program suspend and clear done while ehv is lo w. psus is cleared on reset. 0 program sequence is not suspended. 1 program sequence is suspended. ers erase. ers is used to set up flash for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can only be set only in user mode read (pgm is low and ute is low). ers can be cleared by the user only when esu s and ehv are low and done is high. ers is cleared on reset. 0 flash is not executing an erase sequence. 1 flash is executing an erase sequence. table 21-3. mcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 21-10 freescale semiconductor preliminary?subject to change without notice 21.3.2.1.1 mcr simult aneous register writes a number of mcr bits are protected agai nst write when another bit, or set of bits, is in a specific state. these write locks are covered on a bi t by bit basis in the preceding sectio n. the write locks detailed in the previous section do not consider the effects of trying to write two or more bits simultaneously. the effects of writing bits simultaneously which put the module in an illegal state are detailed here. the flash module does not allow the user to write bits simultaneously wh ich put the device into an illegal state. this is implemented through a priority mech anism among the bits. the bit changing priorities are detailed in table 21-4 . esus erase suspend. esus is used to indicate that the flas h module is in erase suspend or in the process of entering a suspend state. the module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transi tion of esus starts the sequence which sets done and places the flash in erase suspend. esus can be cleared only when done and ehv are high a nd pgm is low. a 1 to 0 transition of esus with ehv = 1 starts the sequence which clears done and returns the module to erase. the flash module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0 erase sequence is not suspended. 1 erase sequence is suspended. ehv enable high voltage. the ehv bit enables the flash modul e for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock writ e to start a program/erase sequence. ehv may be set, initiating a program/erase, after an interlock under one of the following conditions: ? erase (ers = 1, esus = 0). ? program (ers = 0, esus = 0, pgm = 1, psus = 0). ? erase-suspended program (ers = 1, esus = 1, pgm = 1, psus = 0). if a program operation is to be initiated while an erase is suspended the user must clear ehv while in erase suspend before setting pgm. in normal operation, a 1 to 0 transition of ehv with done high, psus and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 transiti on of ehv with done low and the suspend bit for the current program/erase sequence low. an abort causes the value of peg to be clear ed, indicating a failed program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a suspended operation cannot be aborted. ehv may be written during suspend. ehv must be high for the flash module to exit suspend. ehv may not be written after a susp end bit is set high and befo re done transitions high. ehv may not be set low after the current suspend bit is set low and before done transitions low. 0 flash is not enabled to perform a high voltage operation. 1 flash is enabled to perform a high voltage operation. note: aborting a high voltage operation leaves fc addresses in an indeterminate data state. this may be recovered by executing an erase on the affected blocks. table 21-4. mcr bit set/ clear priority levels priority level mcr bit(s) 1ers 2pgm 3ehv 4 esus, psus table 21-3. mcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-11 preliminary?subject to change without notice if the user attempts to write two or more mcr bits simultaneously then only the bit with the lowest priority level is written. setting two bits wi th the same priority level is prev ented by existing write locks or do not put the flash in an illegal state. for example, setting ers and pgm simultaneously re sults in only ers being set. attempting to clear ehv while setting psus results in ehv being cleared, while psus is unaffected. 21.3.2.2 low/mid address space block locking register (lml) the low/mid address block locking register (lml) provides a means to protect blocks from being modified. these bits, along with bits in the seconda ry llock (sll), determine if the block is locked from program or erase. an ?or? of lml and sll determine the final lock status. note a reset value of 1* in figure 21-4 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. the lml register is shown in figure 21-4 and table 21-5 . offset: flash_regs_base + 0x000 4 access: user read/write 0 123456789101112131415 rlme0000000000 slock 00 mlock w reset0 0000000000 1* 001*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 00000 llock w reset0000001*1*1*1*1*1*1*1*1*1* figure 21-4. low/mid address block locking register (lml)
pxd20 microcontroller reference manual, rev. 1 21-12 freescale semiconductor preliminary?subject to change without notice 21.3.2.3 high address space block locking register (hbl) the high address space block lock ing register (hbl) provides a mean s to protect blocks from being modified. table 21-5. lml field descriptions field description lme low/mid address lock enable. this bit is used to enable the lock registers (slock, mlock and llock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to write a password, and if the password matches, the lme bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for lme, the password 0xa1a1_1111 must be written to the lml register. 0 low/mid address locks are disabled, and cannot be modified. 1 low/mid address locks are enabled to be written. slock shadow lock. this bit is used to lock the shadow bl ock from programs and erases. the slock register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation. likewise, slock register is not writable if a high voltage o peration is suspended. slock is also not writeable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into the slock register. the slock bit may be written as a register. reset causes t he bits to go back to their shadow block value. the default value of the slock bits (assuming erased shadow location) is locked. slock is not writable unless lme is high. 0 the shadow block can receive program and erase pulses. 1 the shadow block is locked for program and erase. mlock[1:0] mid address space block lock. a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lo ck register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for mid address space starts with mlock[0] and continues until all blocks are accounted. the lock register is not writable once an interlock writ e is completed until mcr[done] is set at the completion of the requested operation. likewise, the lock register is not writable if a high voltage operation is suspended. mlock is also not writeable during utest operations, when aie is high. upon reset, information from the shadow block is loaded into the block registers. the lock bits may be written as a register. reset causes t he bits to go back to their shadow block value. the default value of the lock bits (assuming erased shadow location) is locked. in the event that blocks are not present (due to configuration or total memory size), the lock bits default to be locked, and are not writable. the reset value is al ways 1 (independent of the shadow block), and register writes have no effect. mlock is not writable unless lme is high. llock[9:0] low address space block lock. a value of 1 in a bit of the lock register signifies that the corresponding block is locked for program and erase. a value of 0 in the lo ck register signifies that the corresponding block is available to receive program and erase pulses. the block numbering for low address space starts with llock[0] and continues until all blocks are accounted. for more details on llock, please see mlock bit description. llock is not writable unless lme is high.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-13 preliminary?subject to change without notice note a reset value of 1* in figure 21-5 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. the hbl register is shown in figure 21-5 and table 21-6 . 21.3.2.4 secondary low/mid address sp ace block locking register (sll) the secondary low/mid addr ess block locking register (sll) provides an alte rnative means to protect blocks from being modified. this ha s the effect of creating a ?tiered? locking scheme to enable different flash users to provide different default locking on bloc ks. these bits, along with bits in the llock (lml), determine if the block is locked from program or erase. an ?or? of lml a nd sll determine the final lock status. note a reset value of 1* in figure 21-6 indicates that the reset value of these registers is determined by flash valu es in the shadow block. an erased shadow block causes th e reset value to be 1. offset: flash_regs_base + 0x0008 access: user read/write 0123456789101112131415 rhbe000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 hlock w reset00000000001*1*1*1*1*1* figure 21-5. high address space block locking register (hbl) table 21-6. hbl field descriptions field description hbe high address lock enable this bit is used to enable the lock registers (hlock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to provide a password, and if the password ma tches, the hbe bit is set to reflect the status of enabled, and is enabled until a reset opera tion occurs. for hbe, the password 0xb2b2_2222 must be written to the hbl register. 0 high address locks are disabled, and cannot be modified. 1 high address locks are enabled to be written. hlock[5:0] high address space block lock. hlock has the same characteristics as llock. please see this description for more information. the block numbering for high a ddress space starts with hlock[0] and continues until all blocks are accounted. hlock is not writable unless hbe is high.
pxd20 microcontroller reference manual, rev. 1 21-14 freescale semiconductor preliminary?subject to change without notice the sll register is shown in figure 21-6 and table 21-7 . 21.3.2.5 low/mid address space block select register (lms) the low/mid address space block se lect register (lms) provides a m eans to select blocks to be operated on during erase. the lms register is shown in figure 21-7 and table 21-8 . offset: flash_regs_base + 0x000c access: user read/write 0123456789101112131415 rsle0000000000 ss lock 00 sm lock w reset000000000001*001*1* 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 sllock w reset0000001*1*1*1*1*1*1*1*1*1* figure 21-6. secondary low/mid address block locking register (sll) table 21-7. sll field descriptions field description sle secondary low/mid address lock enable. this bit is used to enable the lock registers (sslock, smlock, and sllock) to be set or cleared by register writes. this bit is a status bit only, and may not be written or cleared, and the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the sle bit is set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle, the password 0x c3c3_3333 must be written to the sll register 0 secondary low/mid address locks are disabled, and cannot be modified. 1 secondary low/mid address locks are enabled to be written. sslock secondary shadow lock. this bit is an alternative method that may be used to lock the shadow block from programs and erases. sslock has the same de scription as slock. sslock is not writable unless sle is high. smlock[1:0] secondary mid address block lock. this bit is an alternative method that ma y be used to lock the mid address space blocks from programs and erases. smlock has the same description as mlock. smlock is not writable unless sle is high. sllock[9:0] secondary low address block lock. this bit is an alternative method that may be used to lock the low address space blocks from programs and erases. sllock has the same description as llock. sllock is not writable unless sle is high.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-15 preliminary?subject to change without notice 21.3.2.6 high address space block select register (hbs) the high address space block select register (hbs) provides a means to select blocks to be operated on during erase. the hbs register is shown in figure 21-8 and table 21-9 . offset: flash_regs_base + 0x0010 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00000000000000 msel w reset00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 lsel w reset00000000000000 0 0 figure 21-7. low/mid address space block select register (lms) table 21-8. lms field descriptions field description msel[1:0] mid address space block select. a value of 1 in th e select register signifies t hat the block is selected for erase. a value of 0 in the select regi ster signifies that the block is not selected. t he reset value for the select registers is 0, or un-selected. the blocks must be selected (or un-selected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation, or if a hi gh voltage operation is suspended. msel is also not writeable during utest operations, when aie is high. in the event that blocks are not pres ent (due to configuration or total memory size), the corresponding select bits default to un-selected, and are not writable. the reset value is always 0, and register writes have no effect. lsel[9:0] low address space block select. a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select regi ster signifies that the block is not selected. t he reset value for the select registers is 0, or un-selected. the blocks must be selected (or un-selected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed until mcr[done] is set at the completion of the requested operation, or if a hi gh voltage operation is suspended. lsel is also not writeable during utest operations, when aie is high. in the event that blocks are not pres ent (due to configuration or total memory size), the corresponding select bits default to un-selected, and are not writable. the reset value is always 0, and register writes have no effect.
pxd20 microcontroller reference manual, rev. 1 21-16 freescale semiconductor preliminary?subject to change without notice 21.3.2.7 address register (adr) the address register (adr) provides the first fail ing address in the event module failures (ecc or pgm/erase state machine) the adr register is shown in figure 21-9 and table 21-10 . offset: flash_regs_base + 0x0014 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 hsel w reset0000000000000000 figure 21-8. high address space block select register (hbs) table 21-9. hbs field descriptions field description hsel[5:0] high address space block select. high address block select has the same characteristics as lsel. offset: flash_regs_base + 0x0018 access: user read/write 0123456789101112131415 rsad0000000000 addr w reset000000000000 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 raddr 000 w reset000000000000 0 0 0 0 figure 21-9. address register (adr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-17 preliminary?subject to change without notice 21.3.2.8 platform flash configuration registers (pfcrp0 and pfcrp1) the pflash configuration register for port 0 (pfcrp0) is used to specif y operation of port p0 of the flash memory module. this register also has two bits (a rb and pri) to control ar bitration between the p0/p1 ports. the pflash configuration register for port 1 (pfcrp1) is used to specif y operation of port p1 of the flash memory module. the pfcrp n registers are shown in figure 21-10 , figure 21-11 , and table 21-11 . master id mapping can be found in table 9-1 . table 21-10. adr field descriptions field description sad shadow address. the sad bit qualifies the address captur ed during an ecc event error, single bit correction, or state machine operation. the sad register is not writable. 0 address captured is from main array space. 1 address captured is from shadow array space. addr[20:3] address. the a dr register provides the first failing address in the event of ecc event error (mcr[eer] set), single bit correction (mcr[sbc] set), as well as providing the address of a failure that may have occurred in a state machine operation (mcr[peg] cleared). ecc event erro rs take priority over single bit corrections, which take priority over state machine errors. this is especia lly valuable in the event of a rww operation, where the read senses an ecc error or single bit correction, and the state machine fails simultaneously. this address is always a double word address that selects 64 bits. the adr register is writable, and can be used in the utest ecc logic check. if the ecc logic check is enabled (ut0[eie] = 1) then the adr register will not update for ecc event error, sing le bit correction, or state machine errors. if mcr[eer] or mcr[sbc] are set, the adr register is locked from writing. mcr[ peg] does not affect the writability of the adr register. offset: flash_regs_base + 0x001c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r lbcfg arb pri 00 m7pfe m6pfe m5pfe m4pfe m3pfe m2pfe m1pfe m0pfe w reset0000000011111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r apc wwsc rwsc 0 dpfen 0 ipfen 0 pflim bfen w reset0111101101010111 figure 21-10. platform flash configuration register for port 0 (pfcrp0)
pxd20 microcontroller reference manual, rev. 1 21-18 freescale semiconductor preliminary?subject to change without notice offset: flash_regs_base + 0x0020 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r lbcfg 00 0 0 m7pfe m6pfe m5pfe m4pfe m3pfe m2pfe m1pfe m0pfe w reset0000000011111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r apc wwsc rwsc 0 dpfen 0 ipfen 0 pflim bfen w reset0111101101010111 figure 21-11. platform flash configuration register for port 1 (pfcrp1) table 21-11. pfcrp0 and pfcrp1 field descriptions field description lbcfg line buffer configuration. controls the configuration of the four line buffers in the pflash controller. the buffers can be organized as a pool of available resources or wi th a fixed partition between instruction and data buffers. in all cases, when a buffer miss occurs, it is allocated to the least recently used buffer within the group and the just-fetched entry then marked as most recently used. if the flash access is fo r the next sequential line, the buffer is not marked as most recently used unt il the given address produces a buffer hit. for pfcrp0, this field is set to 0b0000 by hardware rese t. for pfcrp1, this field is set to 0b0011 by hardware reset. xx00 all four buffers are available for any flash access, i. e., there is no partitioning of the buffers based on the access type. xx01 reserved. xx10 the buffers are partitioned into two groups: buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. xx11 the buffers are partitioned into two groups: buffers 0, 1, 2 allocated for instruction fetches and buffer 3 for data accesses. arb arbitration mode. this field controls which arbitration mo de is used. in both fixed priority or round-robin modes, write requests are prioritized higher t han read requests, and read requests ar e prioritized higher than speculative prefetch requests whenever both ports issue concurrent requests. this bit is set to 1 by hardware reset. 0 fixed-priority arbitration is used; the por t specified in pri has highest fixed priority. 1 round-robin arbitration is used. note: this bit is only available in pfcrp0. for pfcrp1, treat this bit as reserved with a reset value of 0. pri fixed priority. controls which port has highest fixed priori ty when fixed priority arbitration is selected. this field has no effect when operating in round-robin mode. this bit is cleared by hardware reset. 0 port p0 is given highest fixed priority. 1 port p1 is given highest fixed priority. note: this bit is only available in pfcrp0. for pfcrp1, treat this bit as reserved with a reset value of 0. m n pfe n = 0:2, 4:6 master n prefetch enable. used to control whether prefet ching may be triggered based on the ahb hmaster attribute. for example, m0pfe enables prefetching for accesses where hmaster[3:0] = 0b0000. likewise, m4pfe enables prefetching only when hmaster[3:0] == 0b0100. note that hmaster[3] is ignored when determining which m n pfe to use for a given access. these bits are cleared by hardware reset. 0 no prefetching may be triggered by this master. 1 prefetching may be triggered by this master. note: these bits refer to the master id, not the amba port number. please refer to ta bl e 9 - 1 for details.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-19 preliminary?subject to change without notice apc[2:0] address pipelining cont rol. used to control the number of cycles between pipelined access requests. this field must be set to a value corresponding to the operating frequency of the pflash. the settings are documented in the pxd20 microcontroller data sheet . higher operating frequencies require non-zero settings for this field for proper flash operation. 000 accesses may be pipelined back-to-back. 001 access requests require one additi onal hold cycle. 010 access requests require two additional hold cycles. ... 110 access requests require six additional hold cycles. 111 no address pipelining. note: the settings for apc and rwsc should be the same. wwsc[1:0] write wait state control. used to control the number of wait states to be added to the best case flash array access time for writes. this field must be set to a value corresponding to the operating frequency of the pflash. higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b11 by hardware reset. 00 no additional wait-states are added. 01 one additional wait-state is added. 10 two additional wait-states are added. 11 three additional wait-states are added. rwsc[2:0] read wait state control. used to control the number of wait states to be added to the best case flash array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pflash. this field is set to 0b111 by hardware reset. 000 no additional wait states are added. 001 one additional wait state is added. ... 111 seven additional wait states are added. note: the settings for apc and rwsc should be the same. dpfen data prefetch enable. enables or di sables prefetching initiated by a data r ead access. this field is cleared by hardware reset. 0 no prefetching is triggered by a data read access. 1 prefetching may be triggered by any data read access. ipfen instruction prefetch enable. enables or disables prefetching initiated by an instruction read access. this field is cleared by hardware reset. 0 no prefetching is triggered by an instruction read access. 1 prefetching may be triggered by any instruction read access. table 21-11. pfcrp0 and pfcrp1 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 21-20 freescale semiconductor preliminary?subject to change without notice 21.3.2.9 platform flas h access protection register (pfapr) pflim[1:0] pflash prefetch limit. contro ls the prefetch algorithm used by the pflash prefetch controller. this field defines a limit on the maximum number of sequential prefet ches that are attempted between buffer misses. in all situations when enabled, only a single prefetch is initiate d on each buffer miss or hit. this field is cleared by hardware reset. 00 no prefetching or buffering is performed. 01 the referenced line is prefetched on a buffer miss, i.e., prefetch on miss. 1 x the referenced line is prefetched on a buffer miss, or th e next sequential line is prefetched on a buffer hit (if not already present), i.e., prefetch on miss or hit. bfen pflash line read buffers enable. enables or disables line read buffer hits. it is also used to invalidate the buffers. this bit is cleared by hardware reset. 0 the line read buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the line read buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. offset: flash_regs_base + 0x0024 access: user read/write 0123456789101112131415 r m7ap m6ap m5ap m4ap m3ap m2ap m1ap m0ap w reset**************** 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r shsacc 0000 shdacc 0000 w reset****0000****0000 * = initialized by hardware reset figure 21-12. pflash access protection register (pfapr) table 21-12. pfapr field descriptions field description m n ap master n access protection. these fields are used to cont rol whether read and write accesses to the flash memory are allowed based on the master id of a requesting master. 00 no accesses may be performed by this master. 01 only read accesses may be performed by this master. 10 only write accesses may be performed by this master. 11 both read and write accesses may be performed by this master. note: for a list of master ids, see the m n pfe field description in table 21-11 . table 21-11. pfcrp0 and pfcrp1 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-21 preliminary?subject to change without notice 21.3.2.10 pflash supervisor acc ess control register (pfsacc) shsacc[7:4] shadow block supervisor access control. this bit field defines supervisor/user mode access control for each 4 kb sector within the shadow bl ock region of the flash array. 0 shadow block sector n can be accessed in both user and supervisor mode. 1 shadow block sector n can be accessed only in supervisor mode. an attempted user mode access is terminated with an ahb error response. if the reques ting bus master is the processor core, the error response typically generates an instruction abort or data abort exception. this field is mapped into the shadow block (shadow_ block = 0x00ff_c000) with sector base addresses of: shsacc[4] = shadow_block + 0x0000 shsacc[5] = shadow_block + 0x1000 shsacc[6] = shadow_block + 0x2000 shsacc[7] = shadow_block + 0x3000 this field is initialized by hardware reset to the value contained in address 0x3e00 of the shadow block of the flash array. an erased or unprogrammed flash sets this field to 0xff. the contents of the pfapr are combined with the shsacc field to determine the final flash attributes. shdacc[7:4] shadow block data access control. this bit field defines code/data a ccess control for each 4 kbyte sector within the shadow block region of the flash array. 0 shadow block sector n can only be accessed as data. an attemp ted instruction fetch access is terminated with an ahb error response. if the requesting bus ma ster is the processor core, the error response typically generates an instructi on abort or data abort exception. 1 shadow block sector n can be accessed as either code or data. this field is mapped into the shadow block using the same definition as the shsacc field above. this field is initialized by hardware reset to the value contained in address 0x3e00 of the shadow block of the flash array. an erased or unprogrammed flash sets this field to 0xff. the contents of the pfapr are combined with the shdacc field to determine the final flash attributes. offset: flash_regs_base + 0x0028 access: user read/write 0123456789101112131415 r0 sacc[30:16] w reset0*************** 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sacc[15:0] w reset**************** * = initialized by hardware reset figure 21-13. pflash supervisor access control register (pfsacc) table 21-12. pfapr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 21-22 freescale semiconductor preliminary?subject to change without notice table 21-13. pfsacc field descriptions field description sacc supervisor access control. this bit field defines super visor/user mode access control for each sector within the main flash array. 0 flash array sector n can be accessed in both user and supervisor mode. 1 flash array sector n can be accessed only in supervisor mode. an attempted user mode access is terminated with an ahb error response. if the requesting bus master is the processor core, the error response typically generates an instruction abort or data abort exception. the mapping of this bit field to the main flash array is defined in table 21-14 this field is initialized by hardware reset to the value contained in address 0x3e08 of the shadow block of the flash array. an erased or unprogrammed fl ash sets this field to 0xffff_ffff. table 21-14. {s,d}acc register to flash array mapping register bit starting flash array address sector size xacc[0] 0x00_0000 16 kb xacc[1] 0x00_4000 16 kb xacc[2] 0x00_8000 16 kb xacc[3] 0x00_c000 16 kb xacc[4] 0x01_0000 16 kb xacc[5] 0x01_4000 16 kb xacc[6] 0x01_8000 16 kb xacc[7] 0x01_c000 16 kb xacc[8] 0x02_0000 16 kb xacc[9] 0x02_4000 16 kb xacc[10] 0x02_8000 16 kb xacc[11] 0x02_c000 16 kb xacc[12] 0x03_0000 16 kb xacc[13] 0x03_4000 16 kb xacc[14] 0x03_8000 16 kb xacc[15] 0x03_c000 16 kb xacc[16] 0x04_0000 256 kb xacc[17] 0x08_0000 256 kb xacc[18] 0x0c_0000 256 kb xacc[19] 0x10_0000 256 kb xacc[20] 0x14_0000 256 kb xacc[21] 0x18_0000 256 kb xacc[22] 0x1c_0000 256 kb xacc[23] 0x20_0000 256 kb xacc[24] 0x24_0000 256 kb xacc[25] 0x28_0000 256 kb xacc[26] 0x2c_0000 256 kb xacc[27] 0x30_0000 256 kb
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-23 preliminary?subject to change without notice 21.3.2.11 pflash data access control register (pfdacc) 21.3.2.12 user test register 0 (ut0) the user test register 0 (ut0) provi des a means to control utest. the utest mode gives the users of the flash module the ability to perform te st features on the flash. this register is only wr itable when the flash is put into utest mode by writing a passcode. xacc[28] 0x34_0000 256 kb xacc[29] 0x38_0000 256 kb xacc[30] 0x3c_0000 256 kb xacc[31] reserved offset: flash_regs_base + 0x002c access: user read/write 0123456789101112131415 r0 dacc[30:16] w reset0111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dacc[15:0] w reset1111111111111111 figure 21-14. pflash data access control register (pfsacc) table 21-15. pfdacc field descriptions field description dacc data access control. this bit field defines code/data access control for each sector within the main flash array. 0 flash array sector n can be accessed only by a data reference. an attempted instruction fetch is terminated with an ahb error response. if the requesting bus ma ster is the processor core, the error response typically generates an instructio n abort or data abort exception. 1 flash array sector n can be accessed either as an instruction or data reference. the mapping of this bit field to the main flash array is defined in ta b l e 2 1 - 1 4 . this field is initialized by hardware reset to the value contained in address 0x3e10 of the shadow block of the flash array. table 21-14. {s,d}acc register to flash array mapping (continued) register bit starting flash array address sector size
pxd20 microcontroller reference manual, rev. 1 21-24 freescale semiconductor preliminary?subject to change without notice offset: flash_regs_base + 0x003c access: user read/write 0123456789101112131415 r ute scbe 000000 dsi w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 mre mrv eie ais aie aid w reset0000000000000001 figure 21-15. user test register 0 (ut0) table 21-16. ut0 field descriptions field description ute utest enable. this status bit gives indication when utest is enabled. all bits in ut0, ut1, ut2, um0, um1, um2, um3, and um4 are locked when this bit is 0. this bit is not writeable to a 1, but may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is clear ed by a register write. the ute password will only be accepted if mcr[pgm] = 0 and mcr [ers] = 0 (program and erase are not being requested). ute can only be cleared if ut0[aid] = 1, ut0[aie] and ut0[eie] = 0. while clearing ute, wr ites to set aie or set eie will be ignored. for ute, the password 0xf9f9_99 99 must be written to the ut0 register. scbe single bit correction enable. sbc enables single bit correction results to be observed in mcr[sbc]. also is used as an enable for interrupt signals created by th e flash module. ecc corrections that occur when sbce is cleared will not be logged. 0 single bit corrections observation is disabled. 1 single bit correction observation is enabled. dsi data syndrome input. these bits en able checks of ecc logic by allowing check bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dsi[7:0] correspond to the 8 ecc check bits on a double word. mre margin read enable. mre combined with mrv enables factory margin reads to be done. margin reads are only active during array integrity checks. normal user reads are not affected by mre. mre is not writable if aid is low. 0 margin reads are not enabled. 1 margin reads are enabled during array integrity checks. mrv margin read value. mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). in order for this value to be valid, mre must also be set. mrv is not writable if aid is low. 0 zero?s margin reads are requested. 1 one?s margin reads are requested. eie ecc data input enable. eie enables the input registers (dsi and dai) to be the source of data for the array. this is useful in the ecc logic check. if this bit is set, data read through a pflash2p read request will be from the dsi and dai registers when an address match is achieved to the adr register. eie is not simultaneously writable to a 1 as uti is being cleared to a 0. 0 data read is from the flash array. 1 data read is from the dsi and dai registers.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-25 preliminary?subject to change without notice 21.3.2.13 user test register 1 (ut1) the user test register 1 (ut1) provi des added controllability to utest. ais array integrity sequence. ais determines the address sequence to be used during array integrity checks. the default sequence (ais = 0) is meant to replicate sequenc es normal ?user? code follows, and thoroughly checks the read propagation paths. this sequenc e is proprietary. the alternative sequence (ais = 1) is just logically sequential. it should be noted that the time to run a sequential se quence is significantly shorter than the time to run the proprietary sequence. if mre is set, ais has no effect. 0 array integrity sequence is proprietary sequence. 1 array integrity sequence is sequential. aie array integrity enable. aie set to one starts the arra y integrity check done on all selected and unlocked blocks. the address sequence selected is determined by ais, and the misr (um0 through um4) can be checked after the operation is complete, to determine if a correct signa ture is obtained. once an ar ray integrity operation is requested (aie = 1), it may be terminated by clearing aie if the operation has finished (aid = 1) or aborted by clearing aie if the operation is ongoing (aid = 0). aie is not simultaneously writ able to a 1 as uti is being cleared to a 0. 0 array integrity checks are not enabled. 1 array integrity checks are enabled. aid array integrity done. aid is cleared upon an array in tegrity check being enabled (to signify the operation is ongoing). once completed, aid is set to indicate th at the array integrity check is complete. at this time the misr (umr registers) can be checked. aid ca n not be written, and is status only. 0 array integrity check is ongoing. 1 array integrity check is done. offset: flash_regs_base + 0x0040 access: user read/write 0123456789101112131415 r dai w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai w reset0000000000000000 figure 21-16. user test register 1 (ut1) table 21-17. ut1 field descriptions field description dai [31:0] data array input. these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array integrity checks. the dai[31:0] correspond to the 32 array bits representing word 0 of the double word selected in the adr register. table 21-16. ut0 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 21-26 freescale semiconductor preliminary?subject to change without notice 21.3.2.14 user test register 2 (ut2) 21.3.2.15 user multiple input signature register [0:4] (um n ) the user multiple input signature registers (um n ) provide a means to evaluate array integrity. offset: flash_regs_base + 0x0044 access: user read/write 0123456789101112131415 r dai w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai w reset0000000000000000 figure 21-17. user test register 2 (ut2) table 21-18. ut2 field descriptions field description dai [63:32] data array input. these bits enable checks of ecc logic by allowing data bits to be input into the ecc logic and then read out by doing array reads or array integr ity checks. the dai[63:32] correspond to the 32 array bits representing word 1of the double word selected in the adr register. offset flash_regs_base + 0x0048 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr[31:0] w reset00000000000000000000000000000000 figure 21-18. user multiple input signature register 0 (um0) offset flash_regs_base + 0x004c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr[63:32] w reset00000000000000000000000000000000 figure 21-19. user multiple input signature register 1 (um1) offset flash_regs_base + 0x0050 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr[95:64] w reset00000000000000000000000000000000 figure 21-20. user multiple input signature register 2 (um2)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-27 preliminary?subject to change without notice offset flash_regs_base + 0x0054 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r misr[127:96] w reset00000000000000000000000000000000 figure 21-21. user multiple input signature register 3 (um3) offset flash_regs_base + 0x0058 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 misr[143:128] w reset00000000000000000000000000000000 figure 21-22. user multiple input signature register 4 (um4) table 21-19. um n field descriptions field description misr multiple input signature register bi ts. the misr bitfields accumulate a sig nature from an array integrity event. the misr captures all data fields, as well as ecc fields, and the read transfer error signal. the misr can be seeded to any value by writing the misr registers. the misr register provides a means to calc ulate a misr during array integrity operations. the misr can be represented by the following polynomial: x 145 +x 6 +x 5 +x 1 +1 the misr is calculated by taking the previous misr value and then ?exclusiv e oring? the new data. in addition the most significant bit (in this case it is misr[144]), is th en ?exclusive ored? into input of misr[6], misr[5], misr[1], and misr[0]. the result of the ?exclus ive or? is shifted left on each read. the misr register is used in array integrity operations. if during address sequencing, reads extend into an invali d address location (i.e. greater than the maximum address for a given array size) or locked/un-selected blocks. reads ar e still executed to the arra y, but the results from the array read are not deterministic. in this instance, the misr registers is not re -calculated, and the previous value is retained.
pxd20 microcontroller reference manual, rev. 1 21-28 freescale semiconductor preliminary?subject to change without notice 21.3.2.16 nonvolatile private censor ship password 0 register (nvpwd0) the nonvolatile private censorship pa ssword 0 register contains the 32 lsb of the password used to validate the censorship informati on contained in nvscc0?1 registers. 21.3.2.17 nonvolatile private censor ship password 1 register (nvpwd1) the nonvolatile private censorship pa ssword 1 register contains the 32 msb of the password used to validate the censorship informati on contained in nvscc0?1 registers. note in a secured device, starting with a se rial boot, it is possible to read the content of the four flash memory locat ions where the rchw can be stored. for example if the rchw is stored at address 0x00000000, the reads at address 0x00000000, 0x00000004, 0x00000008 and 0x0000000c will return a correct value. any other flash memory address cannot be accessed. offset: 0x03dd8 1 1 see device memory map table for base address information of shadow flash. access: read / write 0123456789101112131415 r pwd31 pwd30 pwd29 pwd28 pwd27 pwd26 pwd25 pwd24 pwd23 pwd22 pwd21 pwd20 pwd19 pwd18 pwd17 pwd16 w reset 2 2 reset values labeled ?x? are loaded from the nvlml va lue which is preprogrammed at the factory. the default value from the factory for this register is 0xfeed_f ace. the default value can be reprogrammed by the user. xxxxxxx xxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd15 pwd14 pwd13 pwd12 pwd11 pwd10 pwd09 pwd08 pwd07 pwd06 pwd05 pwd04 pwd03 pwd02 pwd01 pwd00 w resetxxxxxxxxxxxxxx xx figure 1. nonvolatile private censorship password 0 register (nvpwd0) table 23. nvpwd0 field descriptions field description pwd[31:00] password 31-00 (read/write) the pwd31-00 registers represent the 32 l sb of the private censorship password.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-29 preliminary?subject to change without notice 21.3.2.18 nonvolatile system censorin g information 0 register (nvscc0) offset: 0x03ddc 1 1 see device memory map table for base address information of shadow flash. access: read / write 0123456789101112131415 r pwd63 pwd62 pwd61 pwd60 pwd59 pwd58 pwd57 pwd56 pwd55 pwd54 pwd53 pwd52 pwd51 pwd50 pwd49 pwd48 w reset 2 2 reset values labeled ?x? are loaded from the nvlml va lue which is preprogrammed at the factory. the default value from the factory for this regi ster is 0xcafe_beef. the default value can be reprogrammed by the user. xxxxxxxxxxxxxx xx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd47 pwd46 pwd45 pwd44 pwd43 pwd42 pwd41 pwd40 pwd39 pwd38 pwd37 pwd36 pwd35 pwd34 pwd33 pwd32 w resetxxxxxxxxxxxxxx xx figure 2. nonvolatile private censorship password 1 register (nvpwd1) table 24. nvpwd1 field descriptions field description pwd[63:32] password 63-32 (read/write) the pwd63-32 registers represent the 32 ms b of the private censorship password. offset: 0x03de0 1 1 see device memory map table for base address information of shadow flash. delivery value: 0x55aa_55aa 0123456789101112131415 r sc15 sc14 sc13 sc12 sc11 sc10 sc9 sc8 sc7 sc6 sc5 sc4 sc3 sc2 sc1 sc0 w reset 2 2 reset values labeled ?x? are loaded from the nvlml va lue which is preprogrammed at the factory. the default value from the factory for this register is 0x55aa_55aa. the default value can be reprogrammed by the user. xxxxxxxxxxxxxx xx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 w resetxxxxxxxxxxxxxx xx figure 3. nonvolatile system censoring information 0 register (nvscc0)
pxd20 microcontroller reference manual, rev. 1 21-30 freescale semiconductor preliminary?subject to change without notice the nonvolatile system censoring information 0 register stores the 32 lsb of the censorship control word of the device. the nvscc0 is a nonvolatile re gister located in the shad ow sector: it is read dur ing the reset phase of the flash memory module and the protection m echanisms are activated consequently. the parts are delivered uncensored to the user. 21.3.2.19 nonvolatile system censorin g information 1 register (nvscc1) the nonvolatile system censoring information 1 regist er stores the 32 msb of the censorship control word of the device. the nvscc1 is a nonvolatile re gister located in the shad ow sector: it is read dur ing the reset phase of the flash memory module and the protection m echanisms are activated consequently. the parts are delivered uncensored to the user. table 25. nvscc0 field descriptions field description sc[15:0] serial censorship control word 15-0 (read/write) these bits represent the 16 lsb of the se rial censorship control word (sccw). if sc15-0 = 0x55aa and nvscc1 = n vscc0 the public access is disabled. if sc15-0 ? 0x55aa or nvscc1 ? nvscc0 the public access is enabled. cw[15:0] censorship control word 15-0 (read/write) these bits represent the 16 lsb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvscc1 = nvscc0 the censored mode is disabled. if cw15-0 ? 0x55aa or nvscc1 ? nvscc0 the censored mode is enabled. offset: 0x03de4 1 1 see device memory map table for base address information of shadow flash. access: read / write 0123456789101112131415 r sc31 sc30 sc29 sc28 sc27 sc26 sc25 sc24 sc23 sc22 sc21 sc20 sc19 sc18 sc17 sc16 w reset 2 2 reset values labeled ?x? are loaded from the nvlml va lue which is preprogrammed at the factory. the default value from the factory for this register is 0x55aa_55aa. the default value can be reprogrammed by the user. xxxxxxxxxxxxxx xx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 w resetxxxxxxxxxxxxxx xx figure 4. nonvolatile system censoring information 1 register (nvscc1)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-31 preliminary?subject to change without notice 21.3.2.20 nonvolatile user options register (nvusro) the nonvolatile user options regist er contains configuration inform ation for the user application. the nvusro register is a 64-bit register, of which th e 32 most significa nt bits 63:32 ar e ?don?t care? and eventually used to manage ecc codes. table 26. nvscc1 field descriptions field description sc[31:16] serial censorship control word 31-16 (read/write) these bits represent the 16 msb of the serial censorship control word (sccw). if sc15-0 = 0x55aa and nvscc1 = nvscc0 the public access is disabled. if sc15-0 ? 0x55aa or nvscc1 ? nvscc0 the public access is enabled. cw[31:16] censorship control word 31-16 (read/write) these bits represent the 16 msb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvscc1 = nvscc0 the censored mode is disabled. if cw15-0 ? 0x55aa or nvscc1 ? nvscc0 the censored mode is enabled. offset: 0x03e18 1 1 see device memory map table for base address information of shadow flash. access: read / write 0123456789101112131415 r watchdog_en uo3 0 uo2 9 uo2 9 uo2 7 uo2 6 smd_pad3v5v uo2 4 uo2 3 uo2 2 uo2 1 uo2 0 uo1 9 uo1 8 uo1 7 uo1 6 w reset 2 2 reset values labeled ?x? are loaded from the nvlml va lue which is preprogrammed at the factory. the default value from the factory for this re gister is 0xxxxx_xxxx. the default value can be reprogrammed by the user. xxxxxxxxxxxxxx xx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r uo1 5 uo1 4 uo1 3 uo1 2 uo1 1 uo1 0 uo0 9 uo0 8 uo0 7 uo0 6 uo0 5 uo0 4 uo0 3 uo0 2 uo0 1 uo0 1 w resetxxxxxxxxxxxxxx xx figure 5. nonvolatile user options register (nvusro) table 27. nvusro field descriptions field description uo user options (read/write) the uo generic field is reset based on the information stored in nvusro.
pxd20 microcontroller reference manual, rev. 1 21-32 freescale semiconductor preliminary?subject to change without notice 21.4 functional description the flash module may operate in various mode s. the modes that ar e available include: ? user mode ? low power mode ? power down mode ? utest mode each of these modes are discussed in the following chapters, and more details provided about each mode. 21.4.1 user mode in user mode the flash module may be read and writte n (register writes and inte rlock writes), programmed or erased. the following sub-sections define al l actions that may be performed in user mode. 21.4.1.1 read and write the default state of the flash module is read. the main and shadow addr ess space can be read only in the read state. the mcr is always available for read, ex cept when the module is in low power mode or power down mode. the flash module enters the read state on reset. the module is in the read state under four sets of conditions: stcu_en self mbist enable (read/write) 1: disable after reset 0: enable after reset default manufacturing value before flash memory initialization is ?1?. uo[20:04] user options 20:04 (read/write) the uo20-4 generic registers are reset base d on the information stored in nvusro. pad3v5v[0] high voltage supply for v dd_hv_b domain 0: high voltage supply is 5.0 v 1: high voltage supply is 3.3 v default manufacturing value before flash memory initialization is ?1? (3.3 v) which should ensure correct minimum slope for boundary scan. pad3v5v[1] high voltage supply for v dd_hv_a domain 0: high voltage supply is 5.0 v 1: high voltage supply is 3.3 v default manufacturing value before flash memory initialization is ?1? (3.3 v) which should ensure correct minimum slope for boundary scan. uo[01] user options 01 (read/write) the uo01 generic register is reset based on the information stored in nvusro. watchdog_en 0: disable after reset 1: enable after reset default manufacturing value before flash memory initialization is ?1? table 27. nvusro field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-33 preliminary?subject to change without notice ? the read state is active when the module is enabled (user mode read or utest). ? the read state is active when mcr[pgm] a nd/or mcr[ers] are high and high voltage operation is ongoing (read while write). note reads done to the partition(s) be ing operated on (either erased or programmed) result in an erro r and the mcr[rwe] bit is set. ? the read state is active when mcr[pgm] and mcr[psus] are high (program suspend). ? the read state is active when mcr[ers] and mcr[esus] are hi gh and mcr[pgm] is low (erase suspend). in the flash module, fc reads return 128 bits (1 page). mcr reads return 32 bits of data. warning fc reads are done through the pflash2p. in many cases the pflash2p does ?read page buffering? to allow sequential reads to be done with higher performance. this could provide a da ta coherency issue that must be handled with software. data coherenc y may be an issue after a program or erase operation, as well as shadow block operations. in user mode, registers may be written. ar ray may be written to do interlock writes. register reads to unmapped register address space return all 0?s. array reads attempted to invalid locations result in indeterminate data and i ndeterminate error flags. invalid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. register writes to unmapped regi ster address space have no effect. interlock writes attempted to invalid locations (due to bloc ks that do not exist in non 2 n array sizes), result in an interlock occurring, but attemp ts to program these blocks does not occur since they are forced to be locked. erase occurs to selected a nd unlocked blocks even if the interl ock write is to an invalid location. 21.4.1.2 flash programming a flash program sequence operates on any page within the fc. up to 4 words within the page may be altered in a single program operati on. whenever the array is program, the ecc bits also get programmed. ecc is handled on a 64 bit boundary. thus, if onl y 1 word in any given 64 bit ecc segment is programmed, the adjoining word (in that segment) should not be pr ogrammed since ec c calculation has already completed for that 64-bit segment. attempts to program the adjoining word results in an operation failure (most likely). it is recomm ended that all programming operations be from 64 bits to 128 bits, and be 64 bit aligned. the programming operation should co mpletely fill selected ecc segments within the page. only one program is allowed pe r 64 bit ecc segment between erases. warning in rare cases ?over programming? of a 64 bit ecc segment may be done (eeprom emulation).
pxd20 microcontroller reference manual, rev. 1 21-34 freescale semiconductor preliminary?subject to change without notice programming changes the value stored in an array b it from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. note if a logic 0 is attempted to be ?over programmed? by a logic 1, the resulting operation will fail (mcr[pe g] = 0), and the 0?s that are interlocked will be merged (ored) with 0?s that are alr eady present in the 64 bit ecc segment. addresses in locked/disabled blocks cannot be progra mmed. the user may program the values in any or all of 4 words, within a page, with a single progr am sequence. page-bound words have addresses which differ only in address bits [3:2]. the program opera tion consists of the following sequence of events: 1. change the value in the mcr[pgm] bit from a 0 to a 1. note ensure the block that contains the address to be programmed is unlocked. 2. write the first address to be programmed with th e program data. the flash module latches address bits [20:4] and soc specific shadow enable at th is time. the flash module latches data written as well. this write is referr ed to as a program data interlock write. an interlock write may be as large as 64 bits, and as small as 32 bits. 3. if more than 1 word or double word is to be programmed, write eac h additional address in the page with data to be programmed. this is referred to as a program data write. the flash module ignores address bits [20:4] and soc specific shadow enab le for program data writ es. all unwritten data words default to 0xffff ffff. 4. write a logic 1 to the mcr[ehv] bit to start the internal program sequence or skip to step to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the mcr[pgm] bi t to terminate the program sequence. the program sequence is pr esented graphically in figure 21-28 . the program suspe nd operation detailed in figure 21-28 is discussed in section 21.4.1.2.2, program suspend/resume. the first write after a program is initiated determines the page addr ess to be programmed. program may be initiated with the 0 to 1 transition of the mcr[ pgm] bit or by clearing the mcr[ehv] bit at the end of a previous program. this first writ e is referred to as an interlock write. the interlock write determines if the shadow or normal array space is to be pr ogrammed by sampling soc specific shadow enable and causing mcr[peas] to be set/cleared. in the case of an erase-suspende d program, the values in mcr[peas] may be modified via the program interlock write, enabling erase-suspende d programs to and from shadow space. an interlock write must be perfor med before setting ehv. the user may terminate a pr ogram sequence by clearing mcr[pgm] prior to setting mcr[ehv].
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-35 preliminary?subject to change without notice after the interlock write, additiona l writes only affect the data to be programmed at the word location determined by address bits [3:2]. unwritten locations default to a data value of 0xffff_ffff. if multiple writes are done to the same lo cation the data for the last write is used in programming. while done is low, ehv is high and psus is low the user may clear ehv, result ing in a program abort. a program abort forces the module to step 8 of the program sequenc e. an aborted program results in peg being set low, indicating a failed operation. the data space being operated on before the abort contains indeterminate data. the user may not abort a program sequence while in program suspend. warning aborting a program operation leaves the fc addresses being programmed in an indeterminate data state. this may be recovered by executing an erase on the affected blocks.
pxd20 microcontroller reference manual, rev. 1 21-36 freescale semiconductor preliminary?subject to change without notice figure 21-28. program sequence erase suspend user mode read state write mcr pgm = 1 program write step 1 step 2 step 3 write mcr ehv = 1 high voltage active access mcr done step 4 write psus = 1 read mcr done = 1 program suspend pgm = 0 user mode read state peg = 0 read mcr done = 1 done = 0 write mcr psus = 0 ehv = 1 abort write ehv = 0 step 5 step 6 peg success peg = 1 write mcr failure peg = 0 step 7 ehv = 0 pgm more words step 8 ? no yes write mcr pgm = 0 user mode read state step 9 go to step 2 note: peg remains valid under this condition until ehv is set high or pgm is cleared. note: psus cannot be cleared while ehv = 0. psus and ehv cannot both be changed in a single write operation. peg valid period last write ? yes no esus ? 0 1 erase suspend or erase suspend ? value ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-37 preliminary?subject to change without notice 21.4.1.2.1 program software locking a software mechanism is provided to independently lock/unlock each high, mi d and low address space block against program and erase. software locking is done through the lml (low/mid address space block lock) or hbl (high address space block lock) registers. thes e may be written through register writes, and may be read through register reads. 21.4.1.2.2 program suspend/resume the program sequence may be suspende d to allow read access to the fc. it is not possibl e to erase during a program suspend, or program during a program suspend. read while write may also be used to read the array during a program sequence providin g the read is to a different partition. a program suspend can be initiated by changing th e value of the mcr[psus] bit from a 0 to a 1. mcr[psus] can be set high at any time when mcr[pgm] and mcr[e hv] are high. a 0 to 1 transition of mcr[psus] causes the flash module to start the sequence to enter program suspend, which is a read state. the user must wait until mcr[done] = 1 before the module is suspended. at this time fc reads may be attempted. mcr[done] goes high no more than tpsus (appendix a) after mcr[psus] is set to a 1. once suspended, the fc may only be read. read s to the block(s) being programmed/erased return indeterminate data. the program sequence is resumed by writing a logic 0 to mcr[psus]. mcr[ehv] must be set to a 1 before clearing mcr[psus] to resume operation. when the operation resumes, the flash module continues the program sequen ce from one of a set of predefined points. this may extend the time required for the program operation. warning repeated suspends at a high frequenc y may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0) . the minimum time between suspends to ensure this does not occur is 100us. 21.4.1.3 flash erase erase changes the value stored in all bits of the selected bl ock(s) to logic 1. an erase sequence operates on any combination of blocks in the low, mid or high address space, or the shadow block. the erase sequence is fully automated within the flash. the user only needs to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks ca nnot be erased. if multiple blocks are selected for erase during an erase sequence, the blocks are erased sequentially star ting with the lowest numbered block and terminating with the highest. the erase sequenc e consists of the following sequence of events: 1. change the value in the mc r[ers] bit from 0 to a 1. 2. select the block, or blocks to be erased by writing ones to the a ppropriate registers in lms or hbs registers. if the shadow block is to be erased, this step ma y be skipped, and lms and hbs are ignored.
pxd20 microcontroller reference manual, rev. 1 21-38 freescale semiconductor preliminary?subject to change without notice note lock and select are independent. if a block is selected and locked, no erase occurs. 3. write to any address in flash. th is is referred to as an erase interlock write. the interlock write causes the values of soc specific shadow enable to be captured and causing mcr[peas] to be set/cleared. 4. write a logic 1 to the mcr[ehv] bit to start an internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr[ers] bit to terminate the erase. the erase sequence is presented graphically in figure 21-29 . the erase suspend operation detailed in figure 21-29 is discussed in section section 21.4.1.3.2, erase suspend/resume. after setting ers, one write, referred to as an inte rlock write, must be perfor med before ehv can be set to a 1. this interlock causes the values of soc specifi c shadow enable to be ca ptured. data words written during erase sequence interlock writ es are ignored. the user may ter minate the erase sequence by clearing ers before setting ehv. an erase operation may be aborted by clearing ehv assuming done is low, ehv is high and esus is low. an erase abort forces the module to step 8 of the erase sequence. an abor ted erase results in peg being set low, indicating a failed operation. the block(s) being operated on before the abort contain indeterminate data. the user may not abort an erase sequence while in erase suspend. warning aborting an erase operation leaves th e fc blocks being erased in an indeterminate data state. this may be recovered by executing an erase on the affected blocks.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-39 preliminary?subject to change without notice figure 21-29. erase sequence 21.4.1.3.1 erase software locking software locking affect erase op eration. for details on this see section 21.4.1.2.1, program software locking . user mode read state write mcr ers = 1 select blocks erase interlock write step 1 step 2 step 3 write mcr ehv = 1 high voltage active access mcr done ? step 4 write esus = 1 read mcr done = 1 erase suspend ers = 0 user mode read state peg = 0 read mcr done = 1 done = 0 write mcr esus = 0 ehv = 1 abort write ehv = 0 step 5 step 6 peg ? success peg = 1 write mcr failure peg = 0 step 7 ehv = 0 erase more blocks step 8 ? no yes write mcr ers = 0 user mode read state step 9 ehv = 0 write mcr pgm = 1 program, step 2 go to step 2 note: peg remains valid under this condition until ehv is set high or ers is cleared. note: esus cannot be cleared while ehv = 0. esus and ehv cannot be changed in a single write operation. peg valid period
pxd20 microcontroller reference manual, rev. 1 21-40 freescale semiconductor preliminary?subject to change without notice 21.4.1.3.2 erase suspend/resume the erase sequence may be suspended to allow read access to the fc. the erase sequence may also be suspended to program (erase-suspe nded program) the fc. a program started during erase suspend can in turn be suspended. only one eras e suspend and one program suspend are allowed at a time during an operation. it is not possible to eras e during an erase suspend, or prog ram during a program suspend. during suspend, all reads to fc locations targeted for program and blocks targeted for erase return indeterminate data. programming locations in blocks targeted for erase during erase- suspended program may result in corrupted data. read while write may also be used to read the array during an erase sequence providing the read is to a partiti on not selected for erase. an erase suspend can be initiated by changing th e value of the mcr[esus] bit from a 0 to a 1. mcr[esus] can be set to a 1 at any time when mcr[er s] and mcr[ehv] are high and mcr[pgm] is low. a 0 to 1 transition of mcr[esus] causes the m odule to start the sequence which places it in erase suspend. the user must wa it until mcr[done] = 1 before the modul e is suspended and further actions are attempted. mcr[done] goes high no more than tesus (appendix a) after mcr[esus] is set to a 1. once suspended, the array may be read or a progr am sequence may be initi ated (erase-suspended program). before initiating a progr am sequence the user must firs t clear mcr[ehv]. if a program sequence is initiated the values of soc specific sh adow enable is recapture d. once the erase-suspended program is completed, the value of pe as is returned to its? ?erase? value. fc reads while mcr[esus] = 1 from the block(s) being eras ed return indeterminate data. the erase sequence is resumed by wr iting a logic 0 to mcr[esus]. mc r[ehv] must be set to a 1 and mcr[pgm] must be cleared (in the event of an erase suspended program) before mcr[esus] can be cleared to resume the operation. the module continues the erase sequence fr om one of a set of predefined points. this may extend the time required for the erase operation. warning repeated suspends at a high frequenc y may result in the operation timing out, and the flash module will respond by completing the operation with a fail code (mcr[peg] = 0) . the minimum time between erase suspends to ensure this does not occur is 200us. warning in an erase-suspended program, program ming fc locations in blocks which were being operated on in th e erase may corrupt fc data. 21.4.2 low power mode after low power mode is requested, the flash memo ry module turns off most current sources, although logic/charge pumps to enable quick recovery to read are enabled for fa ster wake up time than power down mode. when in low power mode, register access is prevente d. fc accesses are also prevented until power down mode is exited. fc reads and writes may occur as soon as sleep mode is exited. the flash module returns to its pre-low power state wh en enabled in all cases unless in the process of executing a program or erase high voltage operation at the time of sleep. if the flash memory module is
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-41 preliminary?subject to change without notice put into low power mode during a program or erase high voltage opera tion, the appropriate suspend bit is set to a 1. the user may resume the program or erase operation at the time the module is enabled by clearing the appropriate suspend bit. ehv must be high for the module to resume operation. if both the esus and psus bits are set to a 1 the user must cl ear psus to resume the program. the erase may be resumed after the program ends. 21.4.3 power down mode after entering power down mode, the flash module turns off all dc curr ent sources and no reads from or writes to the module are possible. all power dissipation is due to l eakage in this mode. when in power down mode, register access is preven ted. fc accesses are also prevented until power down mode is exited. the flash memory module returns to its pre-power do wn state when enabled in all cases unless in the process of executing a program or erase high voltage operation at the ti me of entering power down mode. if the flash memory module is configured to ente r power down mode during a program or erase high voltage operation, the appropr iate suspend bit is set to a 1. the user may resu me the program or erase operation at the time the module is enabled by clearing the appropriate su spend bit. ehv must be high for the module to resume operatio n. if both the esus and psus bits are set to a 1 the user must clear psus to resume the program. the erase may be resumed after the program ends. 21.4.4 utest mode utest mode is a mode that customers can put the flash module in to do specific te sts to check the integrity of the flash module. 21.4.4.1 array integrity self check array integrity is checked using a pre-defined addr ess sequence (based on ut0[ais]), and this operation is executed on selected and unlocked blocks. the data to be read is customer spec ific, thus a customer can provide user code into the flash and the correct misr value is calculated. the cust omer is free to provide any random or non-random code, and a valid misr signature is calc ulated. once the operations is completed, the results of the reads ca n be checking by reading the misr va lue, to determine if an incorrect read, or ecc detection was noted. arra y integrity is controlled by the syst em clock (ipg), a nd it is required that the read wait states and address pipelined cont rol registers in the pflash2p be set to match the user defined frequency being used. the array integr ity check consists of the following sequence of events: 1. enable utest mode. 2. select the block, or blocks to be receive arra y integrity check by writi ng ones to the appropriate registers in lms or hbs registers. note locked blocks can be tested with ar ray integrity if se lected in lms and hbs.
pxd20 microcontroller reference manual, rev. 1 21-42 freescale semiconductor preliminary?subject to change without notice note it is not possible to do utest operations on the shadow block. 3. if desired, set the ut0[ais] bit to 1 for sequential addressing only. note for normal integrity checks of the fl ash memory, sequential addressing is recommended. note if it is required to more fully check th e read path (in a diagnostic mode), it is recommend that ais be left at 0, to use the addr ess sequence that checks the read path more fully, and examin e read transitions. this sequence takes more time. 4. seed the misr um0 thru um4 with desired values. 5. set the ut0[aie] bit. c) if desired, the array integrity operation may be aborted prior to ut 0[aid] going high. this may be done by clearing the ut0[ai e] bit and then continuing to the next step. it should be noted that in the event of an aborted array in tegrity check the misr registers will contain a signature for the portion of the ope ration that was completed prior to the abort, and will not be deterministic. prior to doing another array integrity opera tion, the um0, um1, um2 and um3 registers may need to be initialized to the desired seed value by doing register writes. 6. wait until the ut0[aid] bit goes high. 7. read values in the misr registers (um0 through um4) to ensure correct signature. 8. write a logic 0 to the ut0[aie] bit. 21.4.4.2 factory margin read factory margin read must be done following ?initial factory conditi ons.? one factory margin read is allowed per erase. factory margin read may be done to selected and unlocked blocks by combining ut0[mre] and ut0[mrv] with the array integrity check. if ut0[mre] is set, ut0[ ais] has no affect, and the reads will be done sequentially. the data to be read is customer specific, thus a cu stomer can provide user c ode into the flash and the correct misr value is calculated. the customer is free to provide any random or non-random code, and a valid misr signature is calculate d. once the operations is completed, the results of the reads can be checking by reading the misr value. factory margin re ad is a self timed event, and is independent of system clocks, or wait st ates selected. margin ecc corrections or detections are not done during the factory margin read test: 1. enable utest mode. 2. select the block, or blocks to be receive marg in read check by writing ones to the appropriate registers in lms or hbs/ehs re gisters. make sure that sel ected blocks are also unlocked.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-43 preliminary?subject to change without notice note it is not possible to do utest operations on the shadow block. note it is possible to do user mode array reads during the factory margin read test, if desired, but the partition ru les for read while write used during program and erase are in effect during factory margin reads. note if it is desired to do 2 or more margin reads, and it is desired to re-seed the misr, then a reset is re quired between operations. if the subsequent margin reads can be performed with the previ ously calculated misr value, then a reset is not required. 3. set the ut0[mre] bit. 4. set the ut0[mrv] bit to desired value depending on it is desired to do one?s margin or zero?s margin. 5. seed the misr um0 thru um4 with desired values. 6. set the ut0[aie] bit. a) if desired, the margin read operation may be aborte d prior to ut0[aid] going high. this may be done by clearing the ut0[aie] bit and then cont inuing to the next step. it should be noted that in the event of an aborted margin read ch eck the misr registers w ill contain a signature for the portion of the operation that was comple ted prior to the abort, and will not be deterministic. 7. wait until the ut0[aid] bit goes high. 8. read values in the misr registers (um0 through um4) to ensure correct signature. 9. write a logic 0 to the ut0[aie] bit. 21.4.4.3 ecc logic check ecc logic can be checked by providing data to be r ead in the ut0[dsi], ut1[dai] and/or ut2[dai] registers. then array reads can be done, ensuring exp ected results. the ecc logi c check consists of the following sequence of events: 1. enable utest mode. 2. write ut0[eie] to 1. 3. write ut0[dsi], ut1[dai] and/or ut2[dai] bits to provide data a nd check bit values to be read. single or double bit det ections/corrections can be simulated by properly choosing data and check bit combinations. 4. write double word address to receive the data inputted in step 3 into the adr register. 5. reads can now be done through the pflash2p in a read request type fash ion. in the event of a pflash2p read requested from an address that matches the address in the adr register, expected data, and corrections or detecti ons should be observed based on da ta written into the ut0[dsi], ut1[dai] and/or ut2[dai] registers. mcr[eer] a nd mcr[sbc] can be checked to evaluate the status of reads done.
pxd20 microcontroller reference manual, rev. 1 21-44 freescale semiconductor preliminary?subject to change without notice note in the event of an ecc error or si ngle bit correction, during the ecc logic check (uto[eie] high), the adr regist er will not be loaded, and the address tagged to receive the ut0[ dsi], ut1[dai] and/or ut2[dai] values will be persevered. 6. once completed, clear the ut0[eie] bit to 0. 21.4.5 pflash2p the pflash2p has two ahb-lite slave ports and a single flash array interf ace. the dual ported design of the pflash2p enables efficient use of a single flash memory array the cp u and other ahb masters. each ahb port has dedicated line buffers to support si ngle-cycle read accesses and to limit accesses to the flash array. the pflash2p generates read and write enables, the fl ash array address, write size, and write data as inputs to the flash array controller. the pflash2p capt ures read data from the flash array interface and drives it onto the appropriate ahb port. if line buffering is enabled, when data is read from the array it is stored in a line buffer. up to four lines of data (128 bits) are buffered by the pflash2p for each ahb port. if pre-fetching is enabled, data is read in advance and stored in the li ne buffers allowing single-cycle (zero ahb wait-states) read data responses on buffer hits. prefetch triggering may be restricted to instruction accesses only, data accesses only, or may be unrestricted. prefetch tri ggering may also be controlled on a per-master basis. arbitration between the two ahb ports for access to the flash interface is primaril y based on the type of access; writes have priority over reads which have prio rity over prefetches. if bo th ports are doing the same type of access, priority is based on th e settings of the arbitration and pr iority bits in the pfcrp0 register. 21.4.5.1 line read buffers and prefetch operation the pflash2p_h7fb contains four read buffers per ahb port which ar e used to hold line and ecc data read from the flash array. each buf fer operates independently, and is fi lled using a single array access. the buffers are used for both prefetch and normal demand fetches. prefetch triggering is controllable on a per-master and access-type basi s. bus masters may be enabled or disabled from triggering prefetches , and triggering may be further re stricted based on whether a read access is for instruction or data. a read access to the pflash2p_h7fb ma y trigger a prefetch to the next sequential line of array da ta on the cycle following the request. th e access address is incremented to the next-higher 16 byte boundary, and a flash array prefetch is initiated if the data is not already resident in a line read buffer. prefetched data is always loaded into the least-recently-used buffer. buffers may be in one of six states , listed here in prioritized order: ? invalid - the buffer contains no valid data ? used - the buffer contains valid data which has been provided to satisfy an ahb burst type read ? valid - the buffer contains valid data which ha s been provided to satisf y an ahb single type read
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-45 preliminary?subject to change without notice ? prefetched - the buffer contains valid data which ha s been prefetched to sa tisfy a potential future ahb access ? busy ahb - the buffer is currently being used to satisfy an ahb burst read ? busy fill - the buffer has been allocated to receive data from the flash array, and the array access is still in progress selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. first, the buffers are examined to determine if there are any invalid buffers. if there are multiple invalid buffers, the one to be used is selected using a reverse num eric priority, where buffer 0 is selected first, then buffer 1, etc. 2. if there are no invalid buffers, the least-re cently-used buffer is se lected for replacement. once the candidate line buffer has been selected, the fl ash array is accessed and read data loaded into the buffer. if the buffer load was in response to a miss , the just-loaded buffer is immediately marked as most-recently-used. if the buffer load was in response to a speculative fetch to the next-sequential line address after a buffer hit, the recently-used status is not changed . rather, it is marked as most-recently-used only afte r a subsequent buffer hit. this policy maximizes performance based on refere nce patterns of flash accesses and allows for prefetched data to remain valid when non-prefe tch enabled bus masters are granted flash access. several algorithms are available for prefetch c ontrol which trade off performance for power. more aggressive prefetching increases power due to the number of wasted (discarded) prefetches, but may increase performance by lowe ring average read latency. in order for prefetching to occur, pfcrpx[bfen] mu st be set to ?1?; pfcrpx[pflim] must be non-zero; either pfcrpx[ipfen] or pfcrpx[dpfen] mu st be ?1? and pfcrpx[mxpfe] must be ?1?. 21.4.5.2 instruction / data prefetch triggering prefetch triggering may be enabled for instruction reads via th e pfcrpx[ipfen] control bit, while prefetching for data reads is enabled via the pfcrpx[dpfen] control bit. additionally, the pfcrpx[pflim] must also be set to enable prefetching. prefetches ar e never triggered by write cycles. 21.4.5.3 per-master prefetch triggering prefetch triggering may be cont rolled for individual bus master s via the pfcrpx[mxpfe] control field. 21.4.5.4 buffer allocation allocation of the line read buffers is controlled vi a the pfcrpx control register for each ahb port. the lbcfg field of this regist er defines the operating orga nization of the four line buffers. the buffers can be organized as a ?pool? of ava ilable resources with all four buffers av ailable for either in struction or data. they can also be configured with a fixed partiti on between buffers allocated to instruction or data accesses. for the fixed partition, tw o configurations are supported. in one configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. in the second configuration, buffers 0, 1 and 2 are allocated for in struction fetches and buffer 3 reserv ed for data accesses. in this con-
pxd20 microcontroller reference manual, rev. 1 21-46 freescale semiconductor preliminary?subject to change without notice figuration data prefetching is disabled. 21.4.5.5 buffer invalidation the line read buffers may be invalidated by cleari ng the pfcrpx[bfen] bit, which also disables the buffers. software may then restore th e pfcrpx[bfen] bit to its previous state, and the buf fers will have been invalidated. 21.5 initialization information a reset is the highest priority operation for the flash module and terminates all other operations. the flash module uses reset to initialize register and st atus bits to their default reset values. if the flash module is executing a program or erase operation (pgm and/or ers = 1) and a reset is issued, the operation is aborted and the module disables the high voltage logic w ithout damage to the high voltage circuits. reset aborts all operations and forces the fl ash module into user mode ready to receive accesses. after reset is requested, mcr[done] goes low, and remains low during reset and reset recovery. at the end of reset recovery, mcr[done ] transitions from a 0 to a 1. after reset is negated, register reads may be done, al though it should be noted that registers that require updating from shadow information, or other inputs, may not read updated values until mcr[done] transitions high. during reset recovery, regist er writes are not allowed until the mcr[done] bit tran sitions high to indicate reset recovery is completed. 21.6 application information 21.6.1 background flash array access is relatively slow compared to a full speed system clock ba sed on the pll. to prevent wait states on every flash access, li ne buffers are implement ed. while wait states are required between the flash array and line buffer, no wait states are re quired between a line buffe r and the system bus. for example, if the cpu is accessing seque ntial instructions starting at locat ion 0, the first 32 bits (one line) fetched will require wait states. th e number of wait states is based on system clock frequency. however, subsequent instructions containe d in that 128 bit line buffer can be accessed without wait states. furthermore, with prefetching conf igured, the next sequential instruct ions outside the current line buffer can be prefetched to differ ent line buffer. after fetchi ng all the instructions in cu rrent line buffer, the next instruction is fetched for the next line buffer without delay. prefetching only helps perf ormance when sequential accesses typically occur, such as for instructions. since data typically is not arrange d sequentially (except for perhaps gr aphic data) prefetching for data generally is not recommended. the flash module on this device has tw o ports. port 0 is always connected to the cpu. port 1 is connected to the other non-cpu masters.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 21-47 preliminary?subject to change without notice configuring the flash bus interface pa rameters is done by writing to the platform flash configuration registers pfcrp0:1 and platform flas h access protection register pfapr. 21.6.2 flash memory setting recommendations table 21-1 provides an example of recomm ended settings for a common scenario with this device. this example assumes port 0 (core) instruction accesses ar e typically sequential, but not data. port 1 (other masters) will not have any instruct ion accesses. for illustration, this example assumes port 1 accesses have a significant amount of sequential data (such as for gr aphics) which are larger than a line buffer, so prefetching data would make sense. if graphic data were not in the internal flash, then prefetching data on port 1 would not be exp ected to be a benefit. table 21-1. general flash memory setting recommendations for 125 mhz system clock parameter general recommendations port 0 (cpu instruction only) port 1 (cpu data, other masters) parameter symbol in register pfcr0 comments parameter symbol in register pfcr1 comments line buffer configuration bfen = 1 enable port?s buffers bfen = 1 enable port?s buffers instruction prefetch enable ipfen = 1 instruct ions are mostly sequential so prefeching can improve performance. ipfen = 0 no instruction access on port 1 data prefetch enable dpfen = 0 data accesses are expected to generally be random not sequential dpfen = 1 enable prefetching assuming there is significant sequential data prefetch limit pflim = 3 prefetch on hit or miss pflim = 1 prefetch on miss only (allows more bandwidth for core) line buffer configuration lbcfg = 3 allocate 3 line buffers for instructions, 1 for data lbcfg = 0 all 4 line buffers available for any access read wait states rwsc = 3 values are system clock frequency dependent rwsc = 3 values are system clock frequency dependent write wait states wwsc = 3 wwsc = 3 adv. pipeline ctl. apc = 3 apc = 3 result value for recommendations in pfcr0 = 0x3001_7b17, pfcr1 = 0x007c_7b43
pxd20 microcontroller reference manual, rev. 1 21-48 freescale semiconductor preliminary?subject to change without notice table 21-2 illustrates flash access and prot ection by master. note that pfapr? s initial value is loaded from shadow flash location 0x3e00 after re set. the ?master? numbers corres pond to the cro ssbar masters, which for this device can be found in table 9-1 . table 21-2. access and protection setting recommendations parameter parameter symbol in pfapr comments arbitration mode arbm = 3 start with round-bin (2 or 3).change to fixed priority if application analysis indicates improved performance. master n prefetch disable mnpfd = 0 for core instructions, edma and dcu3; 1 for core data start with allowing prefetching (0) for cpu instructions since it is expected the core will have mostly sequential instruction accesses. also, allow prefetching for edma and dcu3, assuming there are large blocks of graphic data accessed. master n access protection mnap = 3 for core data, 1 for core instructions, edma & dcu3 assuming only the cpu will program flash, allow read and write access (3) for the cpu data bus, but read access only (1) for cpu instructions, edma and dcu3.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-1 preliminary?subject to change without notice chapter 22 graphics accelerator gasket (gxg) 22.1 introduction the graphics accelerator gasket (gxg) provides the openvg graphi cs accelerator (gfx2d) with a 32-bit ips to ahb bridge to the slave port and a 64-bi t axi to ahb bridge to the master port. it also provides a direct axi connectio n to the dram controller. the gxg has an address filter c onsisting of four programmable wi ndows. upon addres s detection, the gxg has several byte swapping options per window for the read or write data bus. to save on-chip graphics ram space during write tr ansactions, the gxg has the capabil ity to suppress transactions upon address detection of alpha buffers, and to convert color depth from 32 to 24 bits per pixel upon address detection of frame buffers. du ring read transactions of de tected addresses, an 8-bit constant is returned for each alpha byte component. table 22-1. acronyms and abbreviated terms term meaning aips ahb 2.v6 to ips interface unit ahb advanced high performance bus ahb 2.v6 amba ahb-lite vers ion 2.0 with v6 extensions amba advanced microcontroller bus architecture argb alpha, red, green, blue comp onents of 32-bit color format axi amba advanced extensible interface axbs amba crossbar switch dram dynamic random access memory gfx2d openvg graphics accelerator gram graphics random access memory gxg graphics accelerator gasket ips skyblue line ip interface quadspi quad serial peripheral interface
pxd20 microcontroller reference manual, rev. 1 22-2 freescale semiconductor preliminary?subject to change without notice 22.1.1 block diagram figure 22-1. graphics accelerator gasket block diagram 22.1.2 features ? 32-bit slave port ips to ahb ? 64-bit master port axi to ahb ? axi bus matrix ? active transactions to only a single slave at a time ? transactions forwarded in the same order that they were initiated. ? address filter with up to four programmable windows gfx2d 64-bit axi master 32-bit ahb slave port port 64-bit axi to ahb master bridge alpha suppressor / color depth converter axi dram 32-bit ips to ahb slave bridge aips-lite ahb axbs ahb ips gxg control registers address filter axi semaphore handshake quadspi bus matrix axi 1x2 byte swapper axi axi axi ips req grant
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-3 preliminary?subject to change without notice ? byte swapper for r ead and write data ? supports only 64-bit access ? frame buffer color dept h conversion (32bpp to 24bpp) ? programmable destination base address ? byte indicator for alpha component ? supports only 32-byte incrementing bursts ? alpha buffer write suppressi on and read constant return ? semaphore handshake for exclusive access to external serial flash 22.2 external signal description the gxg does not include any external signals. 22.3 memory map and register definition this section provides a detailed description of all gxg registers. 22.3.1 memory map the gxg 16k space memory map is shown in table 22-2 . the address of each regist er is given as an offset to the gxg base address. table 22-2. gxg memory map offset register access reset value section/page 0x00 gxgcnfg0?window 0 c onfiguration r/w 0x0000_0000 22.3.2.1/22-4 0x04 gxgbase0?window 0 destinat ion base address r/w 0x0000_0000 22.3.2.2/22-5 0x08 gxgfrst0?window 0 first address r/w 0x0000_0000 22.3.2.3/22-6 0x0c gxglast0?window 0 last address r/w 0x0000_0000 22.3.2.4/22-7 0x10 gxgcnfg1?window 1 c onfiguration r/w 0x0000_0000 22.3.2.1/22-4 0x14 gxgbase1?window 1 destinat ion base address r/w 0x0000_0000 22.3.2.2/22-5 0x18 gxgfrst1?window 1 first address r/w 0x0000_0000 22.3.2.3/22-6 0x1c gxglast1?window 1 last address r/w 0x0000_0000 22.3.2.4/22-7 0x20 gxgcnfg2?window 2 c onfiguration r/w 0x0000_0000 22.3.2.1/22-4 0x24 gxgbase2?window 2 destinat ion base address r/w 0x0000_0000 22.3.2.2/22-5 0x28 gxgfrst2?window 2 first address r/w 0x0000_0000 22.3.2.3/22-6 0x2c gxglast2?window 2 last address r/w 0x0000_0000 22.3.2.4/22-7 0x30 gxgcnfg3?window 3 c onfiguration r/w 0x0000_0000 22.3.2.1/22-4 0x34 gxgbase3?window 3 destinat ion base address r/w 0x0000_0000 22.3.2.2/22-5
pxd20 microcontroller reference manual, rev. 1 22-4 freescale semiconductor preliminary?subject to change without notice 22.3.2 registers description this section describes the gxg registers and their bit fields. 22.3.2.1 window configuration (gxgcnfg0-3) 0x38 gxgfrst3?window 3 first address r/w 0x0000_0000 22.3.2.3/22-6 0x3c gxglast3?window 3 last address r/w 0x0000_0000 22.3.2.4/22-7 0x40 gxgstride - gfx2d stride setting r/w 0x0000_0001 22.3.2.5/22-7 0x3fff reserved offset 0x00 (gxgcnfg0) 0x10 (gxgcnfg1) 0x20 (gxgcnfg2) 0x30 (gxgcnfg3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 rwd rhw rby 0 wwd whw wby alpha w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r mode 00 stride w reset00000000 0 0000000 figure 22-2. window configuration (gxgcnfg0-3) table 22-3. window configuration (gxgcnfg0-3) fi eld description field description 31 reserved. 30 rwd read word-wide swap. see section 22.4.5, byte swapper , for details. 0 word swapper disabled. 1 word swapper enabled. 29 rhw read half word-wide swap. see section 22.4.5, byte swapper , for details. 0 halfword swapper disabled. 1 halfword swapper enabled. 28 rby read byte-wide swap. see section 22.4.5, byte swapper . for details. 0 byte swapper disabled. 1 byte swapper enabled. 27 reserved. table 22-2. gxg memory map (continued) offset register access reset value section/page
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-5 preliminary?subject to change without notice 22.3.2.2 window destination base address (gxgbase0-3) 26 wwd write word-wide swap. see section 22.4.5, byte swapper . for details. 0 word swapper disabled. 1 word swapper enabled. 25 whw write halfword-wide swap. see section 22.4.5, byte swapper . for details. 0 halfword swapper disabled. 1 halfword swapper enabled. 24 wby write byte-wide swap. see section 22.4.5, byte swapper . for details. 0 byte swapper disabled. 1 byte swapper enabled. 23?16 alpha alpha. 8-bit constant used on read access to return the frame buffer alpha component or the 8-bit alpha buffer. 15?14 mode buffer conversion mode. 00 no conversions (transparent). 01 alpha buffer write suppression and constant read return. 10 frame buffer color depth conversion for pixels with al pha component on last byte ([31:24]) of pixel format. 11 frame buffer color depth conversion for pixels with alpha component on first byte ([7:0]) of pixel format. 13?12 reserved. 11?0 stride stride. width of the frame buffer (number of pixels) in physical ram. offset 0x04 (gxgbase0) 0x14 (gxgbase1) 0x24 (gxgbase2) 0x34 (gxgbase3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r base[31:16] w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r base[15:5] base[4:0] w reset00000000 0 0000000 figure 22-3. window destination base address (gxgbase0-3) table 22-3. window configuration (gxg cnfg0-3) field descri ption (continued) field description
pxd20 microcontroller reference manual, rev. 1 22-6 freescale semiconductor preliminary?subject to change without notice 22.3.2.3 window first address (gxgfrst0-3) table 22-4. window destination base ad dress (gxgbase0-3) field descriptions field description 31?0 base destination base address. translated addresses during color depth conversion are remapped to this base address. offset 0x08 (gxgfrst0) 0x18 (gxgfrst1) 0x28 (gxgfrst2) 0x38 (gxgfrst3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r first[31:16] w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r first[15:5] first[4:0] w reset00000000 0 0000000 figure 22-4. window first address (gxgfrst0-3) table 22-5. window first address (gxgfrst0-3) field descriptions field description 31?0 first first address. start address boundary for window. addresses greater than or equal (>=) to first and less than (<) last are detected by window.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-7 preliminary?subject to change without notice 22.3.2.4 window last address (gxglast0-3) 22.3.2.5 gfx2d stride setting (gxgstride) offset 0x0c (gxglast0) 0x1c (gxglast1) 0x2c (gxglast2) 0x3c (gxglast3) access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r last[31:16] w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r last[15:5 last[4:0] w reset00000000 0 0000000 figure 22-5. window last address (gxglast0-3) table 22-6. window last address (gxglast0-3) field descriptions field description 31?0 last last address. end address boundary for window. addresses greater than or equal (>=) to first and less than (<) last are detected by window. offset 0x40 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r stride w reset00000000 0 0000000 figure 22-6. gfx2d stride setting (gxgstride)
pxd20 microcontroller reference manual, rev. 1 22-8 freescale semiconductor preliminary?subject to change without notice 22.4 functional description 22.4.1 ips to ahb bridge this bridge acts as an interface between the ip skyblue specification and th e ahb bus. the ips signals are connected to the aips block and the ahb signals are connected to the gfx2d 32-bit slave port. a transfer error is asserted with an access to an ips address offs et greater than or equal to 0x800. 22.4.2 axi to ahb bridge this unidirectional bridge converts 64-bit axi transactions into appr opriate 64-bit ahb transactions and handles the multiplexing of the data channels. it has an axi slave port as an input port and an ahb-lite master port as an output port. 22.4.3 1x2 axi bus matrix the axi bus matrix enables the gf x2d 64-bit master port to communicate with tw o axi slave ports. it has active transactions to only a single slave at a time and is responsible for forwarding all axi transactions in the same order that the transactions were initiated. table 22-8 shows the default parameter se ttings for the axi bus matrix. table 22-7. gfx2d stride setti ng (gxgstride) field descriptions field description 2-0 stride configuration of stride used by the gxg to match the setting applied to the gfx2d in an openvg driver. 3?b000 - 4096 3?b001 ? 2048 3?b010 ? 1024 3?b011 ? 512 3?b100 ? 256 3?b101 - 128 3?b110 - 64 table 22-8. bus matrix default parameters slave ports regions start address end address mapped regions slave 0 (dram controller) 00 0x0000_0000 0x1fff_ffff no 01 0x2000_0000 0x3fff_ffff yes 02 0xa000_0000 0xbfff_ffff yes 03 0xc000_0000 0xffff_ffff no slave 1 (cross bar switch) 10 0x4000_0000 0x5fff_ffff yes 11 0x6000_0000 0x7fff_ffff yes 12 0x8000_0000 0x8fff_ffff yes 13 0x9000_0000 0x9fff_ffff no
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-9 preliminary?subject to change without notice 22.4.4 address filter since the type of access (which inte rnal client) is not tagged by the gfx2 d master port, an address filter is used to screen for addresses that are within four programmable address windows. transactions with detected addresses are modified according to the configuration parameters of the respective window. transactions with addresses th at are outside all of the window s proceed without modifications. if address regions overlap, window 0 has priority over window 1, which has priority over window 2, which has priority over window 3. a window is disabled if last address is programmed to be less than or equal to first address. 22.4.5 byte swapper the address filter is used to screen for transact ions that need byte swapping. the purpose of the byte swapper is to provide endi anness compatibility across platforms. tr ansactions with det ected addresses are modified with the byte swapping para meters of the respective window. tr ansactions with addresses that are outside all of the windows proceed without modifications. the byte swapper is onlythe byte swa pper contains three cascaded multip lexers for the r ead data bus and three cascaded multiplexers for the write data bus and byte strobes. the three type of multiplexers are: 1. byte-wide swapper. see figure 22-7 . 2. halfword-wide swapper. see figure 22-8 . 3. word-wide swapper. see figure 22-9 . figure 22-7. byte-wide swap 6 7 4 5 2 3 0 1 00 11 22 33 44 55 66 77 11 00 33 22 55 44 77 66 7 6 5 4 3 2 1 0 data[63:0] data[63:0] wstrb[7:0] wstrb[7:0] bit 63 bit 0 63 0 bit bit wstrb[7] wstrb[7] wstrb[0] wstrb[0] 32 31 32 31
pxd20 microcontroller reference manual, rev. 1 22-10 freescale semiconductor preliminary?subject to change without notice figure 22-8. halfword-wide swap figure 22-9. word-wide swap each swapper can be enabled separately. see table 22-3 for the description of th e byte swapper enable bits. table 22-9 shows the mapping of the read or write data bus. table 22-10 shows the mapping of the write byte strobes. table 22-9. 64-bit data bus mapping input data [63:56] [55:48] [47:40] [ 39:32] [31:24] [23:16] [15:8] [7:0] wd hw by output data 0 0 0 [63:56] [55:48] [47:40] [39:3 2] [31:24] [23:16] [15:8] [7:0] 0 0 1 [55:48] [63:56] [39:32] [47:4 0] [23:16] [31:24] [7:0] [15:8] 0 1 0 [47:40] [39:32] [63:56] [55:4 8] [15:8] [7:0] [31:24] [23:16] 0 1 1 [39:32] [47:40] [55:48] [63:5 6] [7:0] [15:8] [23:16] [31:24] 1 0 0 [31:24] [23:16] [15:8] [7:0] [ 63:56] [55:48] [47:40] [39:32] 1 0 1 [23:16] [31:24] [7:0] [15:8] [55:48] [63:56] [ 39:32] [47:40] 1 1 0 [15:8] [7:0] [31:24] [23:16] [47:40] [39:32] [ 63:56] [55:48] 1 1 1 [7:0] [15:8] [23:16] [31:24] [39:32] [47:40] [ 55:48] [63:56] 5 4 7 6 1 0 3 2 00 11 22 33 44 55 66 77 11 00 33 22 55 44 77 66 7 6 5 4 3 2 1 0 data[63:0] data[63:0] wstrb[7:0] wstrb[7:0] bit 63 bit 0 63 0 bit bit wstrb[7] wstrb[7] wstrb[0] wstrb[0] 32 31 32 31 3 2 1 0 7 6 5 4 00 11 22 33 44 55 66 77 44 55 66 77 00 11 22 33 7 6 5 4 3 2 1 0 data[63:0] data[63:0] wstrb[7:0] wstrb[7:0] bit 63 bit 0 63 0 bit bit wstrb[7] wstrb[7] wstrb[0] wstrb[0] 32 31 32 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-11 preliminary?subject to change without notice 22.4.6 frame buffer color depth converter to save space in on-chip gram, the gxg implements a color depth converter to reduce gfx2d 32-bpp frame buffers to 24-bpp before storing into ram. since conversion is only done for frame buffers, the gxg uses the address filter to detect frame buffer acce ss. each window of the addr ess filter can be enabled for color depth conversion by progr amming the respective mode bits . the gxg supports conversions only for 32-byte transactions with 16-byte aligned input addresses. th e gfx2d stride must match the gxg stride which is adjusted using the gxgstride register. during the address phase of the transaction, the input address from the gfx2d is translated to an output address in physical ram according to equation . table 22-10. write byte strobes mapping input write byte strobes wstrb[7] wstrb[6] wstrb[5] wstrb[4] wstrb[3] wstrb[2] wstrb[1] wstrb[0] wd hw by output write byte strobes 000 wstrb[7] wstrb[6] wstrb[5] wstrb[4] wstrb[3] wstrb[2] wstrb[1] wstrb[0] 001 wstrb[6] wstrb[7] wstrb[4] wstrb[5] wstrb[2] wstrb[3] wstrb[0] wstrb[1] 010 wstrb[5] wstrb[4] wstrb[7] wstrb[6] wstrb[1] wstrb[0] wstrb[3] wstrb[2] 011 wstrb[4] wstrb[5] wstrb[6] wstrb[7] wstrb[0] wstrb[1] wstrb[2] wstrb[3] 100 wstrb[3] wstrb[2] wstrb[1] wstrb[0] wstrb[7] wstrb[6] wstrb[5] wstrb[4] 101 wstrb[2] wstrb[3] wstrb[0] wstrb[1] wstrb[6] wstrb[7] wstrb[4] wstrb[5] 110 wstrb[1] wstrb[0] wstrb[3] wstrb[2] wstrb[5] wstrb[4] wstrb[7] wstrb[6] 111 wstrb[0] wstrb[1] wstrb[2] wstrb[3] wstrb[4] wstrb[5] wstrb[6] wstrb[7] inpadr ? input address from gfx2d to be translated. firstn ? window first address. see section 22.3.2.3, window first address (gxgfrst0-3) . ofs ? intermediate offset calculation basen ? destination base address. see section 22.3.2.2, window destination base address (gxgbase0-3) . striden ? width of the frame bu ffer in physical ram. see section 22.3.2.1, window configuration (gxgcnfg0-3) . outadr ? translated output address to physical ram. z ? value of gxgstride register (0 to 6). see section 22.3.2.5, gfx2d stride setting (gxgstride) . ofs 23:0 ?? inpadr 31:2 ?? firstn 31:2 ?? ? = outadr basen 4 ofs 23: 12 z + ?? ?? striden ? ?? ? 3ofs11:0 ?? ? ++ =
pxd20 microcontroller reference manual, rev. 1 22-12 freescale semiconductor preliminary?subject to change without notice during the data phase of write tran sactions, the 8-bit alpha component of each 32-bit pixel is suppressed, and the byte strobes of partially written double-words (firs t and last double-words depending on alignment) are masked. table 22-11 and table 22-12 show the color depth conversion ma pping. the gfx2d address shown is relative to the first address and the physical a ddress shown is relative to the base address. during the data phase of read tran sactions, the programmable 8-bit al pha constant is returned in the alpha component byte lane. if mode[1] is set to enable color depth conve rsion, mode[0] indicates which byte is the alpha component (first or last byte) in the 32-bit pixel value. table 22-11. color depth conversion mapping (mode[0] = 0) offset address 64-bit gfx2d data offset address 64-bit physical ram data [7:0] [15:8 ] [23:1 6] [31:2 4] [39:3 2] [47:4 0] [55:4 8] [63:5 6] [7:0] [15:8 ] [23:1 6] [31:2 4] [39:3 2] [47:4 0] [55:4 8] [63:5 6] 0x00 r 0 g 0 b 0 a 0 r 1 g 1 b 1 a 1 0x00 r 0 g 0 b 0 r 1 g 1 b 1 r 2 g 2 0x08 r 2 g 2 b 2 a 2 r 3 g 3 b 3 a 3 0x08 b 2 r 3 g 3 b 3 r 4 g 4 b 4 r 5 0x10 r 4 g 4 b 4 a 4 r 5 g 5 b 5 a 5 0x10 g 5 b 5 r 6 g 6 b 6 r 7 g 7 b 7 0x18 r 6 g 6 b 6 a 6 r 7 g 7 b 7 a 7 0x18 r 8 g 8 b 8 r 9 g 9 b 9 r 10 g 10 ? ? ? ? 0x50 r 20 g 20 b 20 a 20 r 21 g 21 b 21 a 21 0x38 b 18 r 19 g 19 b 19 r 20 g 20 b 20 r 21 0x58 r 22 g 22 b 22 a 22 r 23 g 23 b 23 a 23 0x40 g 21 b 21 r 22 g 22 b 22 r 23 g 23 b 23 0x60 r 24 g 24 b 24 a 24 r 25 g 25 b 25 a 25 0x48 r 24 g 24 b 24 r 25 g 25 b 25 r 26 g 26 0x68 r 26 g 26 b 26 a 26 r 27 g 27 b 27 a 27 0x50 b 26 r 27 g 27 b 27 r 28 g 28 b 28 r 29 ? ? ? ? 0xe0 r 56 g 56 b 56 a 56 r 57 g 57 b 57 a 57 0xa8 r 56 g 56 b 56 r 57 g 57 b 57 r 58 g 58 0xe8 r 58 g 58 b 58 a 58 r 59 g 59 b 59 a 59 0xb0 b 58 r 59 g 59 b 59 r 60 g 60 b 60 r 61 0xf0 r 60 g 60 b 60 a 60 r 61 g 61 b 61 a 61 0xb8 g 61 b 61 r 62 g 62 b 62 r 63 g 63 b 63 0xf8 r 62 g 62 b 62 a 62 r 63 g 63 b 63 a 63 0xc0 r 64 g 64 b 64 r 65 g 65 b 65 r 66 g 66
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 22-13 preliminary?subject to change without notice 22.4.7 alpha buffer write suppressor certain graphic accelerator operations may perform redunda nt memory writes. this particularly applies to alpha buffer operations. to save space in ram, each gxg window can suppress writes into memory at addresses specified in the window. in addition reads from this window will be replaced with a fixed "alpha" value. program this mode by selecting the value 1 for the va lue of mode in the window configuration register. the fixed "alpha" value is provided by the alpha bit-field in the same register. 22.4.8 serial flash exclusive access the gxg is configured to use the exclusive access capability of the quadspi module. this is provided to avoid the situation where a graphic operation is underway and another master requests a different quadspi operation thus disrupting th e flow of data to the gxg. if a graphic operation requires access to the quadspi then the gxg will suspend operations unt il the quadspi modules grants exclusive access. table 22-12. color depth conversion mapping (mode[0] = 1) offset address 64-bit gfx2d data offset address 64-bit physical ram data [7:0] [15:8 ] [23:1 6] [31:2 4] [39:3 2] [47:4 0] [55:4 8] [63:5 6] [7:0] [15:8 ] [23:1 6] [31:2 4] [39:3 2] [47:4 0] [55:4 8] [63:5 6] ? ? ? ? 0x30 a 12 r 12 g 12 b 12 a 13 r 13 g 13 b 13 0x20 b 10 r 11 g 11 b 11 r 12 g 12 b 12 r 13 0x38 a 14 r 14 g 14 b 14 a 15 r 15 g 15 b 15 0x28 g 13 b 13 r 14 g 14 b 14 r 15 g 15 b 15 0x40 a 16 r 16 g 16 b 16 a 17 r 17 g 17 b 17 0x30 r 16 g 16 b 16 r 17 g 17 b 17 r 18 g 18 0x48 a 18 r 18 g 18 b 18 a 19 r 19 g 19 b 19 0x38 b 18 r 19 g 19 b 19 r 20 g 20 b 20 r 21 ? ? ? ? 0x80 a 32 r 32 g 32 b 32 a 33 r 33 g 33 b 33 0x60 r 32 g 32 b 32 r 33 g 33 b 33 r 34 g 34 0x88 a 34 r 34 g 34 b 34 a 35 r 35 g 35 b 35 0x68 b 34 r 35 g 35 b 35 r 36 g 36 b 36 r 37 0x90 a 36 r 36 g 36 b 36 a 37 r 37 g 37 b 37 0x70 g 37 b 37 r 38 g 38 b 38 r 39 g 39 b 39 0x98 a 38 r 38 g 38 b 38 a 39 r 39 g 39 b 39 0x78 r 40 g 40 b 40 r 41 g 41 b 41 r 42 g 42 ? ? ? ? 0xb0 a 44 r 44 g 44 b 44 a 45 r 45 g 45 b 45 0x80 b 42 r 43 g 43 b 43 r 44 g 44 b 44 r 45 0xb8 a 46 r 46 g 46 b 46 a 47 r 47 g 47 b 47 0x88 g 45 b 45 r 46 g 46 b 46 r 47 g 47 b 47 0xc0 a 48 r 48 g 48 b 48 a 49 r 49 g 49 b 49 0x90 r 48 g 48 b 48 r 49 g 49 b 49 r 50 g 50 0xc8 a 50 r 50 g 50 b 50 a 51 r 51 g 51 b 51 0x98 b 50 r 51 g 51 b 51 r 52 g 52 b 52 r 53
pxd20 microcontroller reference manual, rev. 1 22-14 freescale semiconductor preliminary?subject to change without notice once access is granted the gxg will commence the gr aphic operation and on conclusion will release the exclusive access. see the quadspi chapter for more details on th e operation of the ex clusive access function. table 22-13 shows the default parameter settings for the exclusive access. table 22-13. exclusive access default parameters start address end address 0x8000_0000 0x8fff_fdff
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 23-1 preliminary?subject to change without notice chapter 23 graphics static ram (gsram) 23.1 introduction this document provides a description of the graphics static ram (gsram). cont ained in this document is a user?s level view of performance and overall block functionality descriptions. 23.1.1 overview the gsram on this device consists of a block of ram and an asynchronous rese t, ram array controller (pram2p) with dual ahb input ports. the module act s as a dual ported memory controller interfacing two ahb input ports and a ram array. this contro ller has specific enhancements from previous controllers including the two ports, c onnection to a half speed memory a rray, port specific configurability, and fill function to put the ram into a known state without using any system bus bandwidth. figure 23-1 shows the gsram integrated into a basic platform. figure 23-1. simplified system block diagram in figure 23-1 the platform bus is the amba ahb, the xbar is the ahb cr ossbar switch (arbiter), and the pbridge is the ahb to ips protocol interface. 23.1.2 features ? supports up to 8 mb of ram ? dual 64-bit ahb input ports ? 128-bit slower ram array interface cpu core complex x b a r ram array(s) edma ahb platform off platform master ahb pbridge ips ips slave(s) pram2p ctl
pxd20 microcontroller reference manual, rev. 1 23-2 freescale semiconductor preliminary?subject to change without notice ? support for byte (8-bit), half word (16-bit), word (32-bit) and double word (64-bit) access sizes ? full support for amba v6 extensio ns related to unaligned accesses ? includes support for non-contiguous byte strobes on writes ? independent data buffers (one per ahb port) for maximum system performance ? optimized for burst transfers (read + write) ? programmable read prefetch capabilities ? 32-bit ips interface for access to program model ? arbitration control giving priority to port 0 or port 1 or round robin ? port 0 and 1 prefetch control ? fill function for memory initialization ? region of initialization is configurable wi th start and end addresses on modulo 32 byte boundaries ? initialization can be a load of all-zeroes or all-ones ? status register available for the system to monitor fill operation 23.1.3 modes of operation the gsram supports all modes of operation. if a stand by or low power mode is de sired, it should be taken care of off platform. 23.2 external signal description this module has no external signals. 23.2.1 memory map the gsram programming model consis ts of six 32-bit registers. th e programming model can only be accessed using 32-bit (wor d) accesses. references using a different size are invalid and will return an error. other types of invalid acces ses include: writes to read only register s, and accesses to reserved addresses. table 23-1. gsram memory map address offset register access reset value location general registers 0x0 pram2p_cr - control register r/w 0x0000_0000 on page 23-3 0x4 pram2p_sr?status register r 0x0000_0000 on page 23-4 0x8 pram2p_beg?beginning address for fill register r/w 0x0000_0000 on page 23-4 0xc pram2p_end?end address for fill register r/w 0x0000_0000 on page 23-5 0x10 pram2p_fil?fill register r/w 0x0000_0000 on page 23-5
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 23-3 preliminary?subject to change without notice 23.2.2 register descriptions the following sections detail the individual registers within the gs ram programming model. 23.2.2.1 pram2p control register (pram2p_cr) the pram2p_cr register contains fields for c ontrolling and configuring the 2 slave ports on the gsram. offset 0x0 access: user read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 pfe1 pfe0 00 pri w reset0000000000000000 figure 23-2. pram2p control register(pram2p_cr) table 23-2. pram2p_cr field descriptions field description pfe n port n prefetch enable. 0 array prefetching for port n disabled. 1 array prefetching for port n enabled. pri prioritization of slave ports? access to the ram array. 00 round robin. 01 port 0 has priority over port 1. 10 port 1 has priority over port 0. 11 reserved.
pxd20 microcontroller reference manual, rev. 1 23-4 freescale semiconductor preliminary?subject to change without notice 23.2.2.2 pram2p status register (pram2p_sr) the pram2p_sr is s read only regist er containing the ram array busy fl ag. all writes to this register will return an error. 23.2.2.3 pram2p fill region begin address register (pram2p_beg) offset 0x4 access: user read 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 00 000busy w reset0000000000000000 figure 23-3. pram2p control register(pram2p_cr) table 23-3. pram2p_cr field descriptions field description busy when a fill operation is in progress, the portion of the arra y that is ?to be filled? is unavailable and accesses to those area will be returned with an error. areas not targeted as we ll as areas that have already been filled are accessible and can interrupt the fill operation's access to the array. the busy bit indicates that a fill operation is in progress. 0 array is available. 1 a fill operation is in progress. offset 0x8 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 000 beg_addr[23:4] 0 0 00 w reset00000000000000000000000000000000 figure 23-4. pram2p fill region be gin address register (pram2p_beg) table 23-4. pram2p_beg field descriptions field description beg_ addr [23:4] fill operation will begin at gsram base address + {beg _addr[23:4],4?b0}. while the gsram is busy filling indicated by the busy bit in the pram2p_s r, this register will not be writable. an y write access to this register will return an error.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 23-5 preliminary?subject to change without notice 23.2.2.4 pram2p fill region end address register (pram2p_end) 23.2.2.5 pram2p fill register (pram2p_fil) the pram2p fill register is used to begin the initi alization of the ram array. the array can be filled with either ones or zeroes depending on the fill bit. offset 0xc access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 000 end_addr[23:4] 0 0 00 w reset00000000000000000000000000000000 figure 23-5. pram2p fill region end address register (pram2p_end) table 23-5. pram2p_end field descriptions field description end_ addr [23:4] fill operation will end at gsram base address + {end_addr[ 23:4],4?b0}. while the gsram is buy filling indicated by the busy bit in the pram2p_sr, this register will not be writable. any write access to this register will return an error. offset 0x10 access: user read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 fill 0000 w star t reset0000000000000000 figure 23-6. pram2p fill register(pram2p_fil) table 23-6. pram2p_fil field descriptions field description fill fill is a writable bit which determines whet her the memory is filled with ones or zeroes. start when start is written 0x1, the fill operation will be begin writing 0x0s or 0x1s to the ram array from the address in pram2p_beg,23.2.2.3, to pram2p_end , 23.2.2.4. while filling, all accesses to the parts of t he array that are ?to be filled? will return an error. areas not targeted as well as areas that have already been filled are accessible and can interrupt the fill operation's access to the array this r egister will also be read only until the fill operation is complete returning an error on all writes.
pxd20 microcontroller reference manual, rev. 1 23-6 freescale semiconductor preliminary?subject to change without notice 23.3 functional description the gsram has three main ports: two amba-ahb sl ave ports and one ram array master port. the slave ports are running at the same frequency as the rest of the system. to help system speed with larger ram arrays, the ram array is operati ng at a slower speed. with two acti ve ports and a slower array clock, the access times can vary. assuming th at the other port is idle and the a rray is running at half speed, each port should see the performance described in table 23-7 . the pram2p_cr includes configurab ility bits to help customiz e the gsram performance for a particular application. th is includes giving one port priority ove r the other and enabling prefetching on reads. table 23-8 shows which masters are assigned to which ports for the pxd20. if a particular port is given priority over the other, it will ha ve priority access to the array. if a burst on the non prioritized port has begun however, it will not be interrupted by a read from the prioritized port and it will be held until the burst is complete. each port has a read buffer wh ich will be filled with 128 bits on each read. if prefetching is enabled in the pram2p_cr, the port will acc ess the next location in the array and lo ad it into a prefetch buffer. if that location is accessed, it will move in to the read buffer, and the prefetch buffer will go to the array for the next location and so on. if there are a lot of different masters accessing th e same port, the prefetch feature table 23-7. ideal access performance for access type size cycles 1 1 because of the slower array clock, the amba-ahb access may come in out of phase with the array side causing an extra cycle in the initial access. read single 8,16,32, and 64-bit 2 or 3 (1 if read hits buffer) 4-beat bursts 2-1-1-1 or 3-1-1-1 sequential 4-beat bursts with prefetching 2-1-1-1-1-1-1..... or 3-1-1-1-1-1-1-1... write single 8, 16, 32, and 64-bit 1 4-beat bursts 1-1-1-1 or 2-1-1-1 table 23-8. master assignments port 0 port 1 gfx2d e200z4d instruction port e200z4d data port edma viu2 dculite dcu3
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 23-7 preliminary?subject to change without notice may actually cause a performance degradation. for th is reason the pfen bits in the pram2p_cr allow enabling and disabled of the prefetch feature. when bursting a total size larger than the read buffe r, the consequent accesses ne eded from the array will be prefetched whether prefetching is enabled or not. in the case of a wr ap burst, the correct prefetch is accessed whether the next access is above or below the current read location. the gsram provides a memory initia lization function with the register pram2p_fil. the value in the fill bit will be loaded into every bit in th e ram array from pram2p_beg to pram2p_end. if pram2p_end is less than or e qual to pram2p_beg, the command will be ignored. if pram2p_end is greater than the memory size, the command will al so be ignored. during a fill operation, all accesses to locations in the array that will be fill ed will be returned with an error. as the fill progresses, the areas which have been filled will be acce ssible again. all writes to pram2p _beg, pram2p_end, or pram2p_fil will also return an error during a fill. if a port is currently busy with an access when the fill request is started, the gsram will wait until bo th ports are idle before beginning the fill. software should read the pram2p_sr register to confirm av ailability before accessing the ram. 23.4 initialization information out of reset, all of the ram array entries are unknow n. the best way to initialize the ram array to a known state is to use the fill function provided in the gsram to initialize it to ones or zeroes. 23.5 application information one should take care in configuri ng the gsram using the pram2p_cr. if priority is given to one port, all of the masters on the adjacent port could be star ved out of the ram and le ft waiting. along the same lines, if prefetch is enabled on a port which has several mast ers accessing several area s, there may be a lot of excessive accesses to the ram array slowing down the other port?s access to the ram array.
pxd20 microcontroller reference manual, rev. 1 23-8 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-1 preliminary?subject to change without notice chapter 24 ieee 1149.1 test access port controller (jtagc) 24.1 introduction the jtag port of the device consists of three inputs and one output. these pins include test data input (tdi), test data output (tdo), test mode select (tms), and test cloc k input (tck). tdi, tdo, tms, and tck are compliant with the ieee 1149.1-2001 standard and are shared with the ndi through the test access port (tap) interface. ieee 1149.7 (cjtag) is not supported on this device. 24.2 block diagram figure 24-1 is a block diagram of the jtag controller (jtagc). figure 24-1. jtag controller block diagram 24.3 overview the jtagc provides the means to test chip functionality and connectivit y while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan t echnique, as defined in the ieee 1149.1-2001 standard. in additi on, instructions can be executed th at allow the test access port (tap) to be shared with other modules on the mcu. all data input to and output from the jtagc is communicated in serial format. tck tms tdi test access port (tap) tdo 32-bit device identification register boundary scan register . . controller 1-bit bypass register . 5-bit tap instruction decoder 5-bit tap instruction register . . . power-on reset
pxd20 microcontroller reference manual, rev. 1 24-2 freescale semiconductor preliminary?subject to change without notice 24.4 features the jtagc is compliant with the ieee 1149.1-2001 st andard, and supports th e following features: ? ieee 1149.1-2001 test access port (tap) interface ? 4 pins (see section 24.6, external signal description ) ?tdi ?tms ?tck ?tdo ? a 5-bit instruction register th at supports several ieee 1149.1-2001 defined instru ctions, as well as several public and private mcu specific instructions ? three test data registers, a bypass register, and a de vice identification register ? a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry 24.5 modes of operation the jtagc uses a power-on reset indication as it s primary reset signals. several ieee 1149.1-2001 defined test modes are supporte d, as well as a bypass mode. 24.5.1 reset the jtagc is placed in reset when the tap controller state machine is in the test-logic-reset state. the test-logic-reset state is ente red upon the assertion of the power -on reset signal, or through tap controller state machine transitions controlled by tms. as serting power-on reset results in asynchronous entry into the reset state. while in reset, the following actions occur: ? the tap controller is forced into the test-logic- reset state, thereby disa bling the test logic and allowing normal operation of the on-chip system logic to continue unhindered. ? the instruction register is load ed with the idcode instruction. in addition, execution of certain instructions can result in assertion of the internal system reset. these instructions include extest. 24.5.2 ieee 1149.1-2001 defined test modes the jtagc supports several ieee 1149.1- 2001 defined test modes. the test mode is selected by loading the appropriate instruction into the instruction re gister while the jtagc is enabled. supported test instructions include extest, sample and sample/ preload. each instruction defines the set of data registers that can operate and in teract with the on-chip system logi c while the instruction is current. only one test data register path is enabled to shift data betwee n tdi and tdo for each instruction. the boundary scan register is external to jtagc but can be accessed by jtagc tap through extest, sample, and sample/preload instructions. the func tionality of each test mode is explained in more detail in section 24.8.4, jtagc instructions .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-3 preliminary?subject to change without notice 24.5.2.1 bypass mode when no test operation is required, the bypass instruction can be load ed to place the jtagc into bypass mode. while in bypass mode, the single-bit bypass shif t register is used to provide a minimum-length serial path to shift da ta between tdi and tdo. 24.5.2.2 tap sharing mode there are three selectable auxiliar y tap controllers that share the tap with the jtagc. selectable tap controllers include the nexus port controller (npc) and platfrom. the instructions required to grant ownership of the tap to the auxiliary tap controllers are access_aux_tap_npc, access_aux_tap_once, access_aux_tap_tcu. in struction opcodes for each instruction are shown in table 24-3 . when the access instruction fo r an auxiliary tap is loaded, control of the jtag pins is transferred to the selected tap controller. a ny data input via tdi and tm s is passed to the selected tap controller, and any tdo output from the selected tap c ontroller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jt ag port during the update-dr st ate if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. for more information on the tap controllers refer to chapter 30, nexus development interface (ndi). 24.6 external signal description the jtagc consists of four signals that connect to off-chip development tools and allow access to test support functions. the jtagc signals are outlined in table 24-1 . all 4 jtag pins (tck/tms/tdi/tdo) are shared with gpio pins, so that the software may configure these pins as input/output by progr amming the appropriate registers. to ensure the proper working of jtag, these registers have a reset value such th at these pins behave as jtag pins when the por is lifted: ? tdi : input/pull-up ? tck : input/pull-up ? tms : input/pull-up ? tdo : high-z/pull-disabled table 24-1. jtag signal properties name i/o function reset state tck 1 1 in low power mode, tck frequency should not be greater than 16 mhz or irc. i test clock pull up tdi i test data in pull up tdo o test data out high z tms i test mode select pull up
pxd20 microcontroller reference manual, rev. 1 24-4 freescale semiconductor preliminary?subject to change without notice 24.7 memory map and register description this section provides a detailed de scription of the jtagc registers accessible thr ough the tap interface, including data registers and the instru ction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory-mapped a nd can only be accessed through the tap. 24.7.1 instruction register the jtagc uses a 5-bit instruction register as shown in figure 24-2 . the instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched inst ruction value can only be changed in the update-ir and te st-logic-reset tap controller st ates. synchronous entry into the test-logic-reset state results in the idcode inst ruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap co ntroller state, the instruction sh ift register is loaded with the value 0b10101, making this value the register?s read value when the ta p controller is sequenced into the shift-ir state. 24.7.2 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass, or reserve instructions are active. after entry into the captur e-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. 24.7.3 device identification register the device identification register, shown in figure 24-3 , allows the part revisi on number, design center, part identification number, and manuf acturer identity code to be dete rmined through the tap. the device identification register is selected for serial data transfer betw een tdi and tdo when the idcode instruction is active. entry into the capture-dr stat e while the device identificat ion register is selected loads the idcode into the shift regi ster to be shifted out on tdo in the shift-dr st ate. no action occurs in the update-dr state. 43210 r1 0 1 01 w instruction code reset00001 figure 24-2. 5-bit instruction register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-5 preliminary?subject to change without notice 24.7.4 boundary scan register the boundary scan register is connected betw een tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin da ta, force fixed values on output pins, and select a logic value and direction fo r bidirectional pins. each bit of the boundary scan register represents a sepa rate boundary scan register cell, as described in the ieee 1149.1-2001 standard and discussed in section 24.8.5, boundary scan . the size of the boundary sc an register is 464 bits. 24.8 functional description 24.8.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the inst ruction register is loaded with the idcode instruction. 24.8.2 ieee 1149.1-2001 (j tag) test access port the jtagc uses the ieee 1149.1-2001 tap for accessing re gisters. this port can be shared with other tap controllers on the mcu. for more detail on tap sharing via jtagc in structions refer to section 24.8.4.2, access_aux_tap_x instructions . ir[4:0]: 0_0001 (idcode) access: r/o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prn dc pin mic id w reset 00001010111001100101000000011101 figure 24-3. device identification register table 24-2. device identification register field descriptions field description 0?3 prn part revision number. contains the revision number of the device. this field changes with each revision of the device or module. 4?9 dc design center. 10?19 pin part identification number. contains the part number of the device. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id for freescale, 0xe 31 id idcode register id. identifies th is register as the device identification register and not the bypass register. always set to 1.
pxd20 microcontroller reference manual, rev. 1 24-6 freescale semiconductor preliminary?subject to change without notice data is shifted between tdi and tdo though the selected register starting wi th the least significant bit, as illustrated in figure 24-4 . this applies for the instruction regist er, test data registers, and the bypass register. figure 24-4. shifting data through a register 24.8.3 tap controller state machine the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 24-5 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 24-5 shows, holding tms at logic 1 while cloc king tck through a suffic ient number of rising edges also causes the state machine to enter the test-logic-reset state. selected register msb lsb tdi tdo
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-7 preliminary?subject to change without notice figure 24-5. ieee 1149.1-2001 tap c ontroller finite state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck.
pxd20 microcontroller reference manual, rev. 1 24-8 freescale semiconductor preliminary?subject to change without notice 24.8.3.1 selecting an ie ee 1149.1-2001 register access to the jtagc data registers is done by loading the instruction register with any of the jtagc instructions while the jtagc is enab led. instructions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this poi nt, all data register access is perf ormed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update-dr state. wh en reading a register, there is no requirement to shift out the entire register c ontents. shifting can be terminated afte r fetching the required number of bits. 24.8.4 jtagc instructions this section gives an overview of each instructi on, refer to the ieee 1149.1-2001 standard for more details. the jtagc implements the ieee 1149.1-2001 defined instructions listed in table 24-3 . table 24-4 shows the implementation for sili con cut1. by mistake, the access to nexus port controller is not using the standard powerpc instruction. for silicon cut2, the instruction coding will be ch anged to be 100% compatible with existing powerpc. table 24-3. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device identification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset access_aux_tap_tcu 11011 grants th e tcu ownership of the tap access_aux_tap_once 10001 grants the platfrom ownership of the tap access_aux_tap_npc 10000 grants the nexus port controller (npc) ownership of the tap bypass 11111 selects bypass register for data operations factory debug reserved 1 1 intended for factory debug, and not customer use 00101 00110 01010 intended for factory debug only reserved 2 2 freescale reserves the right to change the decoding of reserved instruction codes all other codes decoded to select bypass register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-9 preliminary?subject to change without notice 24.8.4.1 bypass instruction bypass selects the bypass register, creating a single-bit shift regist er path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid move ment of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. 24.8.4.2 access_aux_tap_ x instructions the access_aux_tap_ x instructions allow the ne xus modules on the mcu to ta ke control of the tap. when this instruction is loaded, control of the tap pins is transferred to the selected auxiliary tap controller. any data input via tdi and tms is passed to the selected tap contro ller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. 24.8.4.3 extest ? extern al test instruction extest selects the boundary scan regi ster as the shift path between td i and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloa ded data contained in the boundary scan register onto the syst em output pins. typically, th e preloaded data is loaded into the boundary scan register using the sample/preload instruction before the selecti on of extest. extest asserts the table 24-4. jtag instructions for silicon cut1 instruction code[4:0] instruction summary idcode 00001 selects device identi fication register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register fo r shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset access_aux_tap_tcu 10000 grants the tcu ownership of the tap access_aux_tap_once 10001 grants the platform ownership of the tap access_aux_tap_npc 10010 grants the nexus por t controller (npc) ownership of the tap bypass 11111 selects bypass register for data operations factory debug reserved 1 1 intended for factory debug, and not customer use 00101 00110 01010 intended for factory debug only reserved 2 2 freescale reserves the right to change the decoding of reserved instruction codes all other codes decoded to select bypass register
pxd20 microcontroller reference manual, rev. 1 24-10 freescale semiconductor preliminary?subject to change without notice internal system reset for the mcu to force a predictable internal st ate while performing external boundary scan operations. 24.8.4.4 idcode instruction idcode selects the 32-bit device identification regist er as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determ ine its version number and other part identification data. idcode is the instruction placed into th e instruction register when the jtagc is reset. 24.8.4.5 sample instruction the sample instruction obtains a samp le of the system data and contro l signals present at the mcu input pins and just before the boundary scan register cells at the output pins . this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through th e boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update -dr state. both the data capture and the shift operation are transparent to system operation. 24.8.4.6 sample/preload instruction the sample/preload instru ction has two functions: ? the sample part of the instruction samples the system data and control signals on the mcu input pins and just before the boundary scan register ce lls at the output pins. this sampling occurs on the rising-edge of tck in the capture-dr state wh en the sample/preload in struction is active. the sampled data is viewed by shifting it thr ough the boundary scan register to the tdo output during the shift-dr state. both th e data capture and the shift operation are transparent to system operation. ? the preload part of the instruction initializes the boundary scan register cells before selecting the extest instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary sc an register during the shift-dr st ate. the initialization data is transferred to the parallel outputs of the boundary s can register cells on the falling edge of tck in the update-dr state. the data is applied to the external output pins by the extest instruction. system operation is not affected. 24.8.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage asso ciated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift -register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-11 preliminary?subject to change without notice 24.9 e200z0 once controller the e200z0 core once controller s upports a complete set of nexus 1 de bug features, as we ll as providing access to the nexus2+ configuration registers. a complete discussion of the e200z0 once debug features is available in the e200z0 reference manual . 24.9.1 e200z0 once controller block diagram figure 24-6 is a block diagram of the e200z0 once block. figure 24-6. e200z0 once block diagram 24.9.2 e200z0 once controlle r functional description the functional description for the e200z0 once controller is the same as for the jtagc, with the differences described below. 24.9.2.1 enabling the tap controller to access the e200z0 once controller, the proper jt agc instruction needs to be loaded in the jtagc instruction register, as discussed in section 24.5.2.2, tap sharing mode . tck e200z0_tms tdi test access port (tap) e200z0_tdo bypass register external data register . . controller tap instruction register . once mapped debug registers auxiliary data register . . . e200z0_trst (once ocmd) tdo mux control { from jtagc (to jtagc)
pxd20 microcontroller reference manual, rev. 1 24-12 freescale semiconductor preliminary?subject to change without notice 24.9.3 e200z0 once controller register description most e200z0 once debug register s are fully documented in the e200z0 reference manual . 24.9.3.1 once command register (ocmd) the once command register (ocmd) is a 10-bit shift re gister that receives its serial data from the tdi pin and serves as the instruction re gister (ir). it holds th e 10-bit commands to be used as input for the e200z0 once decoder. th e ocmd is shown in table 24-5 . the ocmd is updated when the tap controller enters the update -ir state. it contains fields for cont rolling access to a resource, as well as controlling single-step operati on and exit from once mode. although the ocmd is updated during the update-ir tap controller stat e, the correspondi ng resource is accessed in the dr scan sequence of the tap cont roller, and as such, the update-dr state must be transitioned through in order for an access to occu r. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionali ty to be performed, even though the command appears to have no data resour ce requirement associated with it. 012 3 456789 r r/w go ex rs[0:6] w reset:000 0 011011 table 24-5. once command register (ocmd) table 24-6. e200z0 once register addressing rs[0:6] register selected 000 0000 ? 000 0001 reserved 000 0010 jtag id (read-only) 000 0011 ? 000 1111 reserved 001 0000 cpu scan register (cpuscr) 001 0001 no register selected (bypass) 001 0010 once control register (ocr) 001 0011 ? 001 1111 reserved 010 0000 instruction address compare 1 (iac1) 010 0001 instruction address compare 2 (iac2) 010 0010 instruction address compare 3 (iac3) 010 0011 instruction address compare 4 (iac4) 010 0100 data address compare 1 (dac1) 010 0101 data address compare 2 (dac2) 010 0110 data value compare 1 (dvc1)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 24-13 preliminary?subject to change without notice 24.10 initialization/application information the test logic is a static logic de sign, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchroni zed to tck internally. a ny mixed operation using both the test logic and the system functional logic requires extern al synchronization. to initialize the jtagc module and enable access to registers, the follow ing sequence is required: 1. place the jtagc in reset through tap controller state machine transitions controlled by tms 2. load the appropriate instruction for the test or action to be performed. 010 0111 data value compare 2 (dvc2) 010 1000 ? 010 1111 reserved 011 0000 debug status register (dbsr) 011 0001 debug control register 0 (dbcr0) 011 0010 debug control register 1 (dbcr1) 011 0011 debug control register 2 (dbcr2) 011 0100 ? 101 1111 reserved (do not access) 110 1111 reserved (do not access) 111 0000 ? 111 1001 general purpose register selects [0:9] 111 1010 ? 111 1011 reserved 111 1100 nexus2+ access 111 1101 lsrl select (factory test use only) 111 1110 enable_once 111 1111 bypass table 24-6. e200z0 once register addressing (continued) rs[0:6] register selected
pxd20 microcontroller reference manual, rev. 1 24-14 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-1 preliminary?subject to change without notice chapter 25 inter-integrated circuit bus controller module (i 2 c) 25.1 introduction 25.1.1 overview the inter-integrated circuit (i 2 c? or iic) bus is a two wire bidirect ional serial bus that provides a simple and efficient method of data excha nge between devices. it minimizes the number of external connections to devices and does not require an external address decoder. this bus is suitable for applicat ions requiring occasional communications over a short distance between a number of devices. it also provides flexibility, allowing additional device s to be connected to the bus for further expansion and system development. the interface is designed to operate up to 100 kbps with maximum bus lo ading and timing. the device is capable of operating at higher baud rates, up to a ma ximum of module clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. 25.1.2 features the i 2 c module has the following key features: ? compatible with i 2 c bus standard ? multi-master operation ? software programmable for one of 256 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection features not supported: ? no support for general call address ? not compliant to ten-bit addressing 25.1.3 block diagram the block diagram of the i 2 c module is shown in figure 25-1 .
pxd20 microcontroller reference manual, rev. 1 25-2 freescale semiconductor preliminary?subject to change without notice figure 25-1. i 2 c block diagram 25.2 modes of operation the i 2 c module has the followi ng modes of operation: ? run mode: this is the basic mode of operation. ? stop mode: this is the lowest power saving mode and allows the system to turn of all the clocks to the i 2 c module. this state can only be entered wh en there are no active transfers on the bus. 25.3 external signal description 25.3.1 overview the inter-integrated circuit (i 2 c) module has 2 external pins. 25.3.2 detailed signal descriptions 25.3.2.1 scl this is the bidirectional serial clock line (scl) of the module, compatible with the i 2 c-bus specification. 25.3.2.2 sda this is the bidirectional seri al data line (sda) of the module, compatible with the i 2 c-bus specification. in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock i 2 c registers
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-3 preliminary?subject to change without notice 25.4 memory map and register description 25.4.1 overview this section provides a detailed descripti on of all memory-mapped registers in the i 2 c module. 25.4.2 module memory map the memory map for the i 2 c module is given below in table 25-1 . the total address for each register is the sum of the base address for the i 2 c module and the address offset for each register. all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be ali gned to 32-bit boundaries. as an example, the ibdf register for the frequency divi der is accessible by a 16- bit read/write to address base + 0x000, but performing a 16-bit access to base + 0x001 is illegal. 25.4.3 register description this section consists of re gister descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. 25.4.3.1 i 2 c bus address register this register contai ns the address the i 2 c bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. table 25-1. module memory map address register location base + 0x00 i 2 c bus address register (ibad) on page 25-3 base + 0x01 i 2 c bus frequency divider register (ibfd) on page 25-4 base + 0x02 i 2 c bus control register (ibcr) on page 25-13 base + 0x03 i 2 c bus status register (ibsr) on page 25-14 base + 0x04 i 2 c bus data i/o register (ibdr) on page 25-16 base + 0x05 i 2 c bus interrupt configur ation register (ibic) on page 25-16 base + 0x06 unused ? base + 0x07 unused ? base + 0x08 ? base + 0x3fff reserved ? always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 25-2. key to register fields
pxd20 microcontroller reference manual, rev. 1 25-4 freescale semiconductor preliminary?subject to change without notice 25.4.3.2 i 2 c bus frequency divider register offset 0x00000 access: read/write any time 0 1 2 3 4 5 6 7 r adr 0 w reset 0 0 0 0 0 0 0 0 figure 25-3. i 2 c bus address register (ibad) table 25-2. ibad field descriptions field description adr slave address. specific slave address to be used by the i 2 c bus module. note: the default mode of i 2 c bus is slave mode for an address match on the bus. offset 0x0001 access: read/write any time 0 1 2 3 4 5 6 7 r ibc w reset 0 0 0 0 0 0 0 0 figure 25-4. i 2 c bus frequency divider register (ibfd) table 25-3. ibfd field descriptions field description ibc i-bus clock rate. this field is used to prescale the clock for bit rate selection. the bit clock generator is implemented as a prescale divider. the ibc bits ar e decoded to give the tap and prescale values as follows: 0?1 select the prescaled shift register (see ta bl e 2 5 - 4 ) 2?4 select the prescaler divider (see ta bl e 2 5 - 5 ) 5?7 select the shift r egister tap point (see table 25-6 ) table 25-4. i-bus multiplier factor ibc[0:1] mul 00 01 01 02 10 04 11 reserved
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-5 preliminary?subject to change without notice the number of clocks from the falling edge of scl to the first tap (tap[1 ]) is defined by the values shown in the scl2tap column of table 25-5 . all subsequent tap points are separated by 2 ibc[2:4] as shown in the tap2tap column in table 25-5 . the scl tap is used to generate th e scl period and the sda tap is used to determine the delay from the falling edge of scl to the change of state of sda i.e. the sda hold time. table 25-5. i-bus prescaler divider values ibc[2:4] scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 000 2 7 4 1 001 2 7 4 2 010 2 9 6 4 011 6 9 6 8 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128 table 25-6. i-bus tap and prescale values ibc[5:7] scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4
pxd20 microcontroller reference manual, rev. 1 25-6 freescale semiconductor preliminary?subject to change without notice figure 25-5. sda hold time figure 25-6. scl divider and sda hold the equation used to generate the divi der values from the ibfd bits is: scl divider = mul x {2 x (scl2tap + [(scl_tap -1) x tap2tap] + 2)} eqn. 25-1 the sda hold delay is equal to the cpu clock pe riod multiplied by the sda hold value shown in table 25-7 . the equation used to generate the sd a hold value from the ibfd bits is: sda hold = mul x {scl2tap + [(sda_tap - 1) x tap2tap] + 3} eqn. 25-2 the equation for scl hold values to generate the start and stop conditions fr om the ibfd bits is: scl hold(start) = mul x [scl2start + (scl_tap - 1) x tap2tap] eqn. 25-3 scl hold(stop) = mul x [scl2stop + (scl_tap - 1) x tap2tap] eqn. 25-4 scl divider sda hold scl sda sda scl start condition stop condition scl hold(start) scl hold(stop)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-7 preliminary?subject to change without notice table 25-7. i 2 c divider and hold values ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul = 1 00 20 7 6 11 01 22 7 7 12 02 24 8 8 13 03 26 8 9 14 04 28 9 10 15 05 30 9 11 16 06 34 10 13 18 07 40 10 16 21 08 28 7 10 15 09 32 7 12 17 0a 36 9 14 19 0b 40 9 16 21 0c 44 11 18 23 0d 48 11 20 25 0e 56 13 24 29 0f 68 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 17 54 57
pxd20 microcontroller reference manual, rev. 1 25-8 freescale semiconductor preliminary?subject to change without notice mul = 1 1b 128 17 62 65 1c 144 25 70 73 1d 160 25 78 81 1e 192 33 94 97 1f 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 mul = 1 2b 512 65 254 257 2c 576 97 286 289 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 table 25-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-9 preliminary?subject to change without notice mul = 1 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921 mul = 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 mul = 2 4b 80 18 32 42 4c 88 22 36 46 4d 96 22 40 50 4e 112 26 48 58 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 59 192 18 92 98 5a 224 34 108 114 table 25-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd20 microcontroller reference manual, rev. 1 25-10 freescale semiconductor preliminary?subject to change without notice mul = 2 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 28 156 162 61 384 28 188 194 62 448 32 220 226 63 512 32 252 258 64 576 36 284 290 65 640 36 316 322 66 768 40 380 386 67 960 40 476 482 68 640 28 316 322 69 768 28 380 386 6a 896 36 444 450 mul = 2 6b 1024 36 508 514 6c 1152 44 572 578 6d 1280 44 636 642 6e 1536 52 764 770 6f 1920 52 956 962 70 1280 36 636 642 71 1536 36 764 770 72 1792 52 892 898 73 2048 52 1020 1026 74 2304 68 1148 1154 75 2560 68 1276 1282 76 3072 84 1532 1538 77 3840 84 1916 1922 78 2560 36 1276 1282 79 3072 36 1532 1538 7a 3584 68 1788 1794 table 25-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-11 preliminary?subject to change without notice mul = 2 7b 4096 68 2044 2050 7c 4608 100 2300 2306 7d 5120 100 2556 2562 7e 6144 132 3068 3074 7f 7680 132 3836 3842 mul = 4 80 80 28 24 44 81 88 28 28 48 82 96 32 32 52 83 104 32 36 56 84 112 36 40 60 85 120 36 44 64 86 136 40 52 72 87 160 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 36 56 76 mul = 4 8b 160 36 64 84 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 table 25-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd20 microcontroller reference manual, rev. 1 25-12 freescale semiconductor preliminary?subject to change without notice mul = 4 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 mul = 4 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 30 2560 260 1272 1284 b1 3072 260 1528 1540 b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 table 25-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-13 preliminary?subject to change without notice 25.4.3.3 i 2 c bus control register mul = 4 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 offset 0x0002 access: read/write any time 0 1 2 3 4 5 6 7 r mdis ibie ms/sl tx/rx noack 0 dmaen d_rsvd w rsta reset 1 0 0 0 0 0 0 0 figure 25-7. i 2 c bus control re gister (ibcr) table 25-8. ibcr field descriptions field description mdis module disable. this bit controls the software reset of the entire i 2 c bus module. 1 the module is reset and disabled. this is the power-o n reset situation. when high, the interface is held in reset, but registers can still be accessed 0the i 2 c bus module is enabled. this bit must be clear ed before any other ibcr bits have any effect note: if the i 2 c bus module is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corr upt. this would ultimately result in either the current bus master or the i 2 c bus module losing arbitration, afte r which, bus operation would return to normal. ibie i-bus interrupt enable. 1 interrupts from the i 2 c bus module are enabled. an i 2 c bus interrupt occurs pr ovided the ibif bit in the status register is also set. 0 interrupts from the i 2 c bus module are disabled. note that this does not clear any currently pending interrupt condition ms/sl master/slave mode select. upon reset, this bit is clea red. when this bit is changed from 0 to 1, a start signal is generated on the bus and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave. a stop signal should be generated only if the ibif flag is set. ms/sl is cleared without generating a stop signal when the master loses arbitration. 1 master mode 0slave mode table 25-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd20 microcontroller reference manual, rev. 1 25-14 freescale semiconductor preliminary?subject to change without notice 25.4.3.4 i 2 c bus status register tx/rx transmit/receive mode select. th is bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software according to the srw bit in the status register. in master mode this bit should be set according to t he type of transfer required. therefore, for address cycles, this bit will always be high. 1 transmit 0 receive noack data acknowledge disable. this bit specifies the value driven onto sda during data acknowledge cycles for both master and slave receivers. the i 2 c module will always acknowledge address matches, provided it is enabled, regardless of the val ue of noack. note that values written to this bit are only used when the i 2 c bus is a receiver, not a transmitter. 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data rsta repeat start. writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a lo w. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 0 no effect dmaen dma enable. when this bit is set, the dma tx and rx lines will be asserted when the i 2 c module requires data to be read or written to the data register. no tr ansfer done interrupts will be generated when this bit is set, however an interrupt will be generated if t he loss of arbitration or addressed as slave conditions occur. the dma mode is only valid when the i 2 c module is configured as a master and the dma transfer still requires cpu intervention at the start and the end of each frame of data. see the dma application information section for more details. 1 enable the dma tx/rx request signals 0 disable the dma tx/rx request signals d_rsv d reserved bit. this bit is writable but should be kept as value 0. offset 0x0003 access: read-only any time 1 1 with the exception of ibif and ibal , which are software clearable. 0 1 2 3 4 5 6 7 r tcf iaas ibb ibal 0 srw ibif rxak w w1c w1c reset 1 0 0 0 0 0 0 0 figure 25-8. i 2 c bus status register (ibsr) table 25-8. ibcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-15 preliminary?subject to change without notice table 25-9. ibsr field descriptions field description tcf transfer complete. while one byte of data is being transf erred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that this bit is only valid during or immediately following a transfer to the i 2 c module or from the i 2 c module. 1 transfer complete 0 transfer in progress iaas addressed as a slave. when its own specific addre ss (i-bus address register) is matched with the calling address, this bit is set. the cpu is interrupted prov ided the ibie is set. then the cpu needs to check the srw bit and set its tx/rx mode accordingly. writing to the i-bus control register clears this bit. 1 addressed as a slave 0 not addressed ibb bus busy. this bit indicates the status of the bus. when a start signal is detect ed, the ibb is set. if a stop signal is detected, ibb is cl eared and the bus enters idle state. 1 bus is busy 0 bus is idle ibal arbitration lost. the arbitration lost bit (ibal) is set by hardware when the arbitration procedure is lost. arbitration is lost in the following circumstances: ? sda is sampled low when the master drives a high during an address or data transmit cycle. ? sda is sampled low when the master drives a hi gh during the acknowledge bi t of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. this bit must be cleared by software, by writing a one to it. a write of zero has no effect. srw slave read/write. when iaas is se t, this bit indicates th e value of the r/w comm and bit of the calling address sent from the master. this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no othe r transfers have been initiated. by programming this bit, the cpu can select slave transmit/receive mode according to the command of the master. 1 slave transmit, master reading from slave 0 slave receive, master writing to slave ibif i-bus interrupt flag. the ibif bit is set when one of the following conditions occurs: ? arbitration lost (ibal bit set) ? byte transfer complete (tcf bit set and dmaen bit not set) ? addressed as slave (iaas bit set) ? noack from slave (ms & tx bits set) ?i 2 c bus going idle (ibb high-low transition and enabled by biie) a processor interrupt request will be caused if the ibie bit is set. this bit must be cleared by software, by writing a one to it. a write of zero has no effect on this bit. in dma mode (dmaen set), a byte transfer complete condition will not trigger the settin g of ibif. all other conditions still apply. rxak received acknowledge. this is the value of sda duri ng the acknowledge bi t of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates an ackn owledge signal has been received afte r the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. this bit is valid only after transfer is complete. 1 no acknowledge received 0 acknowledge received
pxd20 microcontroller reference manual, rev. 1 25-16 freescale semiconductor preliminary?subject to change without notice 25.4.3.5 i 2 c bus data i/o register in master transmit mode, when data is written to ibdr , a data transfer is initia ted. the most significant bit is sent first. in master receive mode, reading this re gister initiates next byte data receiving. in slave mode, the same functions are availabl e after an address match has occurred. note that the tx/rx bit in the ibcr must correctly reflect the desired direction of transf er in master and slave m odes for the transmission to begin. for instance, if the i 2 c is configured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. reading the ibdr will return th e last byte received while the i 2 c is configured in eith er master receive or slave receive modes. the ibdr does not refl ect every byte that is transmitted on the i 2 c bus, nor can software verify that a byte has been writte n to the ibdr correctly by reading it back. in master transmit mode, the first byte of data written to the ibdr following assertion of ms/sl is used for the address transfer and should comprise the ca lling address (in position d 7?d1) concatenated with the required r/w bit (in position d0). 25.4.3.6 i 2 c bus interrupt configuration register offset 0x0004 access: read/write any time 0 1 2 3 4 5 6 7 r data w reset 0 0 0 0 0 0 0 0 figure 25-9. i 2 c bus data i/o register (ibdr) offset 0x0005 access: read/write any time 0 1 2 3 4 5 6 7 r biie 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 figure 25-10. i 2 c bus interrupt configuration register (ibic) table 25-10. ibic field descriptions field description biie bus idle interrupt enable bit. this config bit can be used to enable the generation of an interrupt once the i 2 c bus becomes idle. once this bit is set, an ibb high -low transition will set the ibif bit. this feature can be used to signal to the cpu the completion of a stop on the i 2 c bus. 1 bus idle interrupts enabled 0 bus idle interrupts disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-17 preliminary?subject to change without notice 25.5 functional description 25.5.1 general this section provides a complete functional de scription of the inter-integrated circuit (i 2 c). 25.5.2 i-bus protocol the i 2 c bus system uses a serial data line (sda) and a serial clock li ne (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logical and function is exercised on both lines with external pull-up resistors. the value of th ese resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave addr ess transmission, data transfer and stop signal. they are described briefly in the following sect ions and illustrated in figure 25-11 . figure 25-11. i 2 c bus transmission signals 25.5.2.1 start signal when the bus is free, i.e. no master device is enga ging the bus (both scl and sda lines are at logical high), a master may initiate communicati on by sending a start signal. as shown in figure 25-11 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transf er (each data transfer may contain several bytes of da ta) and brings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
pxd20 microcontroller reference manual, rev. 1 25-18 freescale semiconductor preliminary?subject to change without notice figure 25-12. start and stop conditions 25.5.2.2 slave address transmission the first byte of data transfer im mediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer - the slave transmits data to the master 0 = write transfer - the master transmits data to the slave only the slave with a calling address that matche s the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pulling the sda low at the 9th clock (see figure 25-11 ). no two slaves in the system may have the same address. if the i 2 c bus is master, it must not transmit an address that is equal to it s own slave address. the i 2 c bus cannot be master and slave at the same time. however, if arbitration is lost during an address cycle the i 2 c bus will revert to slave mode and operate correctly, even if it is bei ng addressed by another master. 25.5.2.3 data transfer once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 25-11 . there is one clock pulse on scl fo r each data bit, the msb being transferred first. each data byte must be follow ed by an acknowledge bit, wh ich is signalled from the receiving device by pulling the sda lo w at the ninth clock. therefore, one complete data byte transfer needs nine clock pulses. sda scl start condition stop condition
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-19 preliminary?subject to change without notice if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the da ta transfer or a start signal (repeated start) to commence a new calling. if the master receiver doe s not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda li ne for the master to generate a stop or start signal. 25.5.2.4 stop signal the master can terminate the comm unication by generating a stop signa l to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-hi gh transition of sda while scl is at logical ?1? (see figure 25-11 ). the master can generate a stop even if the slave has generated an acknowledge, at which point the slave must release the bus. 25.5.2.5 repeated start signal as shown in figure 25-11 , a repeated start signal is a start signal generate d without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 25.5.2.6 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock sync hronization procedur e determines the bus clock, for which the low period is equal to the longest clock low pe riod and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure. a bus master lo ses arbitration if it tr ansmits logic ?1? while a nother master transmits logic ?0.? the losing masters immediately switch ov er to slave receive mode and stop driving the sda output. in this case, the transitio n from master to slave mode doe s not generate a stop condition. meanwhile, a status bit is set by hard ware to indicate loss of arbitration. 25.5.2.7 clock synchronization since wire-and logic is performed on the scl line, a high-to-low tran sition on the scl line affects all the devices connected on the bus. the devices start counting their low pe riod and once a device's clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 25-13 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again.
pxd20 microcontroller reference manual, rev. 1 25-20 freescale semiconductor preliminary?subject to change without notice figure 25-13. i 2 c bus clock synchronization 25.5.2.8 handshaking the clock synchronization mechanism can be used as a handshake in data transf er. slave devices may hold the scl low after completion of one byt e transfer (9 bits). in such cases , it halts the bus clock and forces the master clock into wait state un til the slave releases the scl line. 25.5.2.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low, the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 25.5.3 interrupts 25.5.3.1 general the i 2 c module uses only one interrupt vector. table 25-11. interrupt summary interrupt offset vector pr iority source description i 2 c interrupt ? ? ? ibal, tcf, iaas, ibb bits in ibsr register when any of ibal, tcf or iaas bi ts is set an interrupt may be caused based on arbitration lost, transfer complete or address detect conditions. if enabled by biie, the deassertion of ibb can also cause an interrupt, indicating that the bus is idle. scl1 scl2 scl internal counter reset wait start counting high period
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-21 preliminary?subject to change without notice 25.5.3.2 interrupt description there are five types of internal interrupts in the i 2 c. the interrupt service routine can determine the interrupt type by reading the status register. i 2 c interrupt can be generated on ? arbitration lost condition (ibal bit set) ? byte transfer condition (tcf bit set) ? address detect condition (iaas bit set) ? no acknowledge from slave received when expected ? bus going idle (ibb bit not set) the i 2 c interrupt is enabled by the ibie bit in the i 2 c control register. it must be cleared by writing ?1? to the ibif bit in the interrupt service routine. th e bus going idle interrupt needs to be additionally enabled by the biie bit in the ibic register. 25.6 initialization/application information 25.6.1 i 2 c programming examples 25.6.1.1 initialization sequence reset will put the i 2 c bus control register to its default state. before the in terface can be used to transfer serial data, an initializat ion procedure must be ca rried out, as follows: 1. update the frequency divider re gister (ibfd) and sel ect the required divisi on ratio to obtain scl frequency from system clock. 2. update the i 2 c bus address register (ibad) to define its slave address. 3. clear the ibdis bit of the i 2 c bus control register (ibcr) to enable the i 2 c interface system. 4. modify the bits of the i 2 c bus control register (ibcr) to select master/slave mode, transmit/receive mode and interr upt enable or not. op tionally also modify the bits of the i 2 c bus interrupt config register (ibic) to further refine the interrupt behavior. 25.6.1.2 generation of start after completion of the initialization procedure, seri al data can be transmitte d by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the i 2 c bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the fi rst byte (the slave address) can be sent. the data written to the data register comprises the slave calli ng address and the lsb, which is set to indicate the direction of transfer re quired from the slave. the bus free time (i.e., the time between a stop condition and the fo llowing start condition) is built into the hardware that generates the start cycle. depending on the relative fr equencies of the system
pxd20 microcontroller reference manual, rev. 1 25-22 freescale semiconductor preliminary?subject to change without notice clock and the scl period, it may be necessary to wait until the i 2 c is busy after writi ng the calling address to the ibdr before proceeding with th e following instructions. this is ill ustrated in the following example. an example of the sequence of events which genera tes the start signal and transmits the first byte of data (slave address) is shown below: while (bit 5, ibsr ==1)// wait in loop for ibb flag to clear bit4 and bit 5, ibcr = 1// set transmit and master mode, i.e. generate start condition ibdr = calling_address// send the calling address to the data register while (bit 5, ibsr ==0)// wait in loop for ibb flag to be set 25.6.1.3 post-transfer software response transmission or reception of a byte will set the data transferring bit (tcf) to 1, which indicates one byte communication is finished. the i 2 c bus interrupt bit (ibif) is set also; an interrupt will be generated if the interrupt function is enabled during in itialization by setting the ibie bit. the ibif (i nterrupt flag) can be cleared by writing 1 (in the interrupt service routine, if interrupts are used). the tcf bit will be cleared to indi cate data transfer in progress by reading the ibdr data register in receive mode or writing the ibdr in transmit mode. the tcf bit should not be used as a data transfer complete flag as the flag timing is depe ndent on a number of factors including the i 2 c bus frequency. this bit may not conclusively provide an indication of a transfer complete situation. it is recommended that transfer complete situations ar e detected using the ibif flag. software may service the i 2 c i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that polling should monitor the ibif bit rather than the tcf bit since their operation is different when arbitration is lost. note that when a ?transfer complete? interrupt occurs at the end of the address cycle, the master will always be in transmit mode, i.e. the address is tran smitted. if master receive mode is required, indicated by r/w bit in ibdr, then the tx/rx bi t should be toggled at this stage. if master does not receive an ack from slave, then transmission must be re-initiated or terminated. during slave mode address cycles (iaa s=1) the srw bit in the status register is read to determine the direction of the subsequent transfer and the tx/rx bit is programmed accordingl y. for slave mode data cycles (iaas=0, the srw bit is not va lid. the tx/rx bit in the control regi ster should be read to determine the direction of the current transfer. the following is an example software sequence for 'master transmitter' in the interrupt routine. clear bit 1, ibsr// clear the ibif flag if (bit 5, ibcr ==0) slave_mode()// run slave mode routine if (bit 4, ibcr ==0)) receive_mode()// run receive_mode routine if (bit 0, ibsr == 1)// if no ack end();// end transmission else ibdr = data_to_transmit// transmit next byte of data
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-23 preliminary?subject to change without notice 25.6.1.4 generation of stop a data transfer ends with a stop signal generated by the 'master' devi ce. a master transmitter can simply generate a stop signal afte r all the data has been transmitted. th e following is an example showing how a stop condition is generated by a master transmitter. if (tx_count == 0) or// check to see if all data bytes have been transmitted (bit 0, ibsr == 1) {// or if no ack generated clear bit 5, ibcr// generate stop condition } else { ibdr = data_to_transmit// write byte of data to data register tx_count --// decrement counter } // return from interrupt if a master receiver wants to te rminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting th e transmit acknowledge bit (txak) before reading the 2nd last byte of data. before readi ng the last byte of data, a stop signal must first be generated. the following is an ex ample showing how a stop signal is generated by a master receiver. rx_count --// decrease the rx counter if (rx_count ==1)// 2nd last byte to be read ? bit 3, ibcr = 1// disable ack if (rx_count == 0)// last byte to be read ? bit 1, ibcr = 0// generate stop signal else data_received = ibdr// read rx data and store 25.6.1.5 generation of repeated start at the end of data transfer, if the master still wa nts to communicate on the bus , it can generate another start signal followed by another slave address wi thout first generating a stop signal. a program example is as shown. bit 2, ibcr = 1// generate another start ( restart) ibdr == calling_address// transmit the calling address 25.6.1.6 slave mode in the slave interrupt service routin e, the module addressed as slave bit (iaas) shoul d be tested to check if a calling of its own address has just been re ceived. if iaas is set, software should set the transmit/receive mode sel ect bit (tx/rx bit of ib cr) according to the r/w co mmand bit (srw). writing to the ibcr clears iaas automatically. note that the only time i aas is read as set is from the interrupt at the end of the address cycle wher e an address match occurred. interr upts resulting from subsequent data transfers will have iaas cleared. a data transfer may now be initiate d by writing information to ibdr for slave transmits or dummy reading from ibdr in slave receive mode. the slave will drive scl low in-between byte transfers scl is released when the ibdr is accessed in the required mode. in slave transmitter routine, the r eceived acknowledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from th e master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal.
pxd20 microcontroller reference manual, rev. 1 25-24 freescale semiconductor preliminary?subject to change without notice 25.6.1.7 arbitration lost if several masters try to engage the bus simultan eously, only one master wins and the others lose arbitration. the devices that lost arbitration are immediately switch ed to slave receive mode by the hardware. their data output to the sda line is stopped, but scl is still generated until the end of the byte during which arbitration was lo st. an interrupt occurs at the falling e dge of the ninth cloc k of this transfer with ibal=1 and ms/sl=0. if one master attempts to start transmission, while the bus is being engaged by another master, the hardware will inhibit the transmission, switch th e ms/sl bit from 1 to 0 without generating a stop condition, generate an interrupt to cpu and set the ibal to indicate that the attempt to engage the bus is failed. when considering these cases, the slave service routine should test the ibal first and the software should clear the ibal bit if it is set.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 25-25 preliminary?subject to change without notice figure 25-14. flow-chart of typical i 2 c interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n ibif address transfer data transfer
pxd20 microcontroller reference manual, rev. 1 25-26 freescale semiconductor preliminary?subject to change without notice 25.6.2 dma application information the dma interface on the i2c is not completely au tonomous and requires interv ention from the cpu to start and to terminate the frame transfer. dma mode is only valid for master tran smit and master receive modes. software must ensure that the ibcr[dmaen] bit is not set when the i 2 c module is configured in master mode. the dma controller must only transfer one byte of da ta per tx/rx request. this is because there is no fifo on the i 2 c block. the cpu should also keep the i 2 c interrupt enabled during a dma transf er to detect the arbitration lost condition and take action to recover from this situation. the ibcr[dmaen ] bit works as a disable for the transfer complete interrupt. this m eans that during normal tran sfers (no errors) there wi ll always be either an interrupt or a re quest to the dma controller, depending on the setting of the dm aen bit. all error conditions will trigger an interr upt and require cpu intervention. th e address match condition will not occur in dma mode as the i 2 c should never be configured for slave operation.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-1 preliminary?subject to change without notice chapter 26 interrupt controller (intc) 26.1 introduction the intc provides priority-based preemptive schedul ing of interrupt service requests (isrs). this scheduling scheme is suitable for statically scheduled hard real-t ime systems. the intc supports 171 interrupt requests. it is targeted to work with power arch itecture technology and au tomotive applications where the isrs nest to multiple levels, but it also can be used with other pr ocessors and applications. for high-priority interrupt requests in these target applications, the time from the assertion of the peripheral?s interrupt request to wh en the processor is performing usef ul work to service the interrupt request needs to be minimized. the intc supports this goal by pr oviding a unique vector for each interrupt request source. it also pr ovides 16 priorities so that lower prio rity isrs do not de lay the execution of higher priority isrs. because each individual application will have different priori ties for each source of interrupt request, the priority of each interrupt request is configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interrupt requests to each other through software configurable interrupt requests. these software configurable interrupt requests can also be used to separate the work involved in servicing an interrupt request into a high-priority portion and a low-priority portion. the high-priority portion is initiated by a peripheral interrupt request, but then the isr can assert a software configurable interrupt request to finish the servicing in a lower priority isr. therefore th ese software configurable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. 26.2 features ? supports 163 peripheral and 8 software-c onfigurable interrupt request sources ? unique 9-bit vector per interrupt source ? each interrupt source can be progr ammed to one of 16 priorities ? preemption ? preemptive prioritized inte rrupt requests to processor ? isr at a higher priority preempts isrs or tasks at lower priorities ? automatic pushing or popping of preemp ted priority to or from a lifo ? ability to modify the isr or task priority; modi fying the priority can be used to implement the priority ceiling protocol fo r accessing shared resources. ? low latency - three clocks from re ceipt of interrupt reque st from peripheral to interrupt request to processor
pxd20 microcontroller reference manual, rev. 1 26-2 freescale semiconductor preliminary?subject to change without notice 26.3 block diagram figure 26-1 is a block diagram of the intc. 1 the total number of interrupt sources is 187, which includes 8 software sources. figure 26-1. intc block diagram 26.4 modes of operation 26.4.1 normal mode in normal mode, the intc has two handshaking modes with the processor: software vector mode and hardware vector mode. 26.4.1.1 software vector mode in software vector mode, the interrupt exception handl er software must read a register in the intc to obtain the vector associated with the interrupt request to the processor. the intc will use software vector mode for a given processor when it s associated hven bit in intc_mcr is negated. the hardware vector enable signal to processor 0 or processor 1 is driven as negated when its associ ated hven bit is negated. the vector is read from intc_iac kr. reading the intc_iackr negate s the interrupt request to the associated processor. even if a higher priority inte rrupt request arrived while waiting for this interrupt acknowledge, the interrupt reque st to the processor will negate for at least one clock. the reading also pushes the pri value in intc_cpr onto the associ ated lifo and updates pri in the associated intc_cpr with the new priority. hardware vector enable software set/clear interrupt registers flag bits priority select registers peripheral interrupt requests module configuration register highest priority 4 priority comparator slave interface for reads & writes 1 push/update/acknowledge 1 1 1 update interrupt vector 1 interrupt request to processor memory mapped registers non-memory mapped logic end of interrupt register request selector priority arbitrator highest priority interrupt requests n 1 n 1 vector encoder interrupt vector 9 processor 0 interrupt acknowledge register interrupt vector 9 n 1 8 n 1 x 4-bits new priority 4 current priority 4 processor 0 current priority register processor 0 priority lifo pop 1 lowest vector interrupt request 1 vector table entry size pushed priority 4 popped priority 4 interrupt acknowledge peripheral bus
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-3 preliminary?subject to change without notice furthermore, the interrupt vector to the processor is driven as all 0s. the interrupt acknowledge signal from the associated processor is ignored. 26.4.1.2 hardware vector mode in hardware vector mode, the hardware signals the in terrupt vector from the in tc in conjunction with a processor that can use that vector. this hardware causes the first instruction to be executed in handling the interrupt request to the processor to be specific to that vector. therefore, the interrupt exception handler is specific to a peripheral or software configurable interrupt request rather than being common to all of them. the intc uses hardware vector mode for a given processor when the associated hven bit in the intc_mcr is asserted. the hardware vector enable signal to the asso ciated processor is driven as asserted. when the interrupt request to the associated processor asserts, the in terrupt vector signal is updated. the value of that interrupt ve ctor is the unique vector associ ated with the preempting peripheral or software configurable interrupt request. the vector value matches the value of the intvec field in the intc_iackr field in the intc_i ackr, depending on which processo r was assigned to handle a given interrupt source. the processor negates the interrupt request to the pr ocessor driven by the intc by asserting the interrupt acknowledge signal for one cl ock. even if a higher priority interrupt request arrived while waiting for the interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. the assertion of the interrupt acknowledge signal for a given processor pushes the associated pri value in the associated intc_cpr register onto the associ ated lifo and updates the associated pri in the associated intc_cpr register with the new priority . this pushing of the pri value onto the associated lifo and updating pri in the asso ciated intc_cpr does not occur when the associated interrupt acknowledge signal asserts and intc_sscir0_3?intc_sscir4_7 is writt en at a time such that the pri value in the associated intc_cpr register would need to be pushed and the previously last pushed pri value would need to be popped simu ltaneously. in this ca se, pri in the associated intc_cpr is updated with the new priority, and the associ ated lifo is neither pushed or popped. 26.4.1.3 debug mode the intc operation in debug mode is iden tical to its operation in normal mode. 26.4.1.4 stop mode the intc supports stop mode. the intc can have its cl ock input disabled at any time by the clock driver on the device. while its clocks are disabl ed, the intc registers are not accessible. the intc requires clocking in order for a peripheral inte rrupt request to generate an interrupt request to the processor. since the intc is not clocked in stop mode, peripheral interrupt re quests can not be used as a wakeup source, unless the clock, reset, and power m odule (crp) supports that interrupt request as a wakeup source.
pxd20 microcontroller reference manual, rev. 1 26-4 freescale semiconductor preliminary?subject to change without notice 26.5 memory map and register description 26.5.1 module memory map table 26-1 shows the intc memory map. 26.5.2 register description with exception of the intc_ssci n and intc_psr n , all registers are 32 bits in width. any combination of accessing the four bytes of a register with a si ngle access is supported, provi ded that the access does not cross a register boundary. these suppor ted accesses include type s and sizes of eight bits, aligned 16 bits, misaligned 16 bits to the middle two bytes, and aligned 32 bits. although intc_ssci n and intc_psr n are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided th at the access does not cross a 32-bit boundary. in software vector mode, the side ef fects of a read of intc _iackr arethe same rega rdless of the size of the read. in either software or hardware vector mode, the size of a write to either intc_sscir0_3?intc_sscir4_7 or intc_eoir does not affect the opera tion of the write. table 26-1. intc memory map offset from intc_base_ addr 1 1 intc_base_addr = 0xfff4_8000 register access reset value location 0x0000 intc_mcr?intc module conf iguration register r/w 0x0000_0000 on page 26-5 0x0004 reserved ? ? ? 0x0008 intc_cpr?intc current prio rity register r/w 0x0000_000f on page 26-5 0x00c reserved 0x0010 intc_iackr?intc interrupt acknowledge register r 2 /w 2 when the hven bit in the intc module configuration register (intc_mcr) is asserted, a read of the intc_iackr has no side effects. 0x0000_0000 on page 26-7 0x0014 reserved 0x0018 intc_eoir?intc end of interrupt register w 0x0000_0000 on page 26-7 0x001c reserved 0x0020? 0x0027 intc_sscir[0:7]?intc software set/clear interrupt register [0:7] r/w 0x0000_0000 on page 26-8 0x0028? 0x003c reserved ? ? ? 0x0040? 0x012c intc_psrn -intc priority select register [0:238] 3 3 the pri fields are ?reserved? for peripheral interrupt requests whose vectors are labeled as reserved in figure 26-3 r/w 0x0000_0000 on page 26-9
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-5 preliminary?subject to change without notice 26.5.2.1 intc module configur ation register (intc_mcr) the module configuration register is us ed to configure options of the intc. 26.5.2.2 intc current priority regi ster for processor (intc_cpr) offset: 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 vtes 0 0 0 0 hven w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-2. intc module configuration register (intc_mcr) table 26-2. intc_mcr field descriptions field description vtes vector table entry size. controls the number of ?0?s to the right of intvec in section 26.5.2.3, intc interrupt acknowledge register (intc_iackr) ). if the contents of intc_iackr are used as an address of an entry in a vectortable as in softwar e vector mode, then the nu mber of rightmost ?0?s will determine the size of each vector table entry. vtes impacts software vector mode operation but also affects intc_iackr[intvec] position in both hardware vector mode and software vector mode. 0 4 bytes. 1 8 bytes. hven hardware vector enable. controls whether the intc is in hardware vector mode or software vector mode. refer to section 26.4, modes of operation, for the details of the handshaking with the processor in each mode. 0 software vector mode. 1 hardware vector mode. offset: 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pri w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 figure 26-3. intc current priority register (intc_cpr)
pxd20 microcontroller reference manual, rev. 1 26-6 freescale semiconductor preliminary?subject to change without notice the intc_cpr masks any peripheral or software settable interrupt re quest set at the same or lower priority as the current value of the intc_cpr[pri] field from genera ting an interrupt request to the processor. when the intc interrupt acknowledge regi ster (intc_iackr) is r ead in software vector mode or the interrupt acknowledge signal from the pr ocessor is asserted in ha rdware vector mode, the value of pri is pushed onto the li fo, and pri is updated with the pr iority of the preempting interrupt request. when the intc end-of-inter rupt register (intc_eoir) is wr itten, the lifo is popped into the intc_cpr?s pri field. the masking priority can be raised or lowered by wr iting to the pri field, supporting the pcp. refer to section 26.7.5, priority ceiling protocol. note a store to modify the pri fi eld that closely precedes or follows an access to a shared resource can result in a non- coherent access to the resource. refer to section 26.7.5.2, ensuring coherency , for example code to ensure coherency. table 26-3. intc_cpr field descriptions field description pri priority. pri is the priority of the currently ex ecuting isr according to the field values defined in ta bl e 2 6 - 4 . table 26-4. pri values pri meaning 1111 priority 15?highest priority 1110 priority 14 1101 priority 13 1100 priority 12 1011 priority 11 1010 priority 10 1001 priority 9 1000 priority 8 0111 priority 7 0110 priority 6 0101 priority 5 0100 priority 4 0011 priority 3 0010 priority 2 0001 priority 1 0000 priority 0?lowest priority
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-7 preliminary?subject to change without notice 26.5.2.3 intc interrupt acknowledge register (intc_iackr) the interrupt acknowledge register provides a va lue that can be used to load the address of an isr from a vector table. the vector table ca n be composed of addresses of th e isrs specific to their respective interrupt vectors. in software vector mode, the intc _iackr has side effects from re ads. therefore, it must not be speculatively read while in this m ode. the side effects are the same regardless of the size of the read. reading the intc_iackr does not have si de effects in hardware vector mode. 26.5.2.4 intc end-of-interrupt register (intc_eoir) offset: 0x0010 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vtba (most significant 16 bits) w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba (least significant five bits) intvec 1 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 when the vtes bit in intc_mcr is asserted, intvec is sh ifted to the left one bit. bit 29 is read as a 0. vtba is narrowed to 20 bits in width. figure 26-4. intc interrupt acknowledge register (intc_iackr) table 26-5. intc_iackr field descriptions field description vtba vector table base address. can be the base addr ess of a vector table of addresses of isrs. the vtba only uses the leftmost 20 bits when the vtes bit in intc_mcr is asserted. intvec interrupt vector.it is the vector of the peripher al or software configurable interrupt request that caused the interrupt request to the processor. wh en the interrupt request to the processor asserts, the intvec is updated, whether the intc is in software or hardware vector mode. note: if intc_mcr[vtes] = 1, then the intvec field is shifted left one position to bits 20?28. vtba is then shortened by one bit to bits 0?19. offset 0x0018 access: write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-5. intc end-of-interrupt register (intc_eoir)
pxd20 microcontroller reference manual, rev. 1 26-8 freescale semiconductor preliminary?subject to change without notice writing to the end-of-interrupt regi ster signals the end of the servici ng of the interrupt request. when the intc_eoir is written, the priority last pushed on th e lifo is popped into intc _cpr. an exception to this behavior is described in section 26.4.1.2, hardwa re vector mode . the values and size of data written to the intc_eoir are ignored. the values and sizes written to this regi ster neither update the intc_eoir contents or affect whet her the lifo pops. for possible future compatib ility, write four bytes of all 0s to the intc_eoir. reading the intc_eoir has no effect on the lifo. 26.5.2.5 intc software set/clear interrupt registers (intc_sscir0_3?i ntc_sscir4_7) offset: 0x0020 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 clr0 0 0 0 0 0 0 0 clr1 w set0 set1 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr2 0 0 0 0 0 0 0 clr3 w set2 set3 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-6. intc software set/clear interrupt register 0?3 (intc_sscir[0:3]) offset: 0x0024 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 clr4 0 0 0 0 0 0 0 clr5 w set4 set5 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr6 0 0 0 0 0 0 0 clr7 w set6 set7 reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-7. intc software set/clear interrupt register 4?7 (intc_sscir[4:7])
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-9 preliminary?subject to change without notice the software set/clear interrupt regi sters support the setting or clearing of software configurable interrupt request. these registers cont ain eight independent sets of bits to set and clea r a corresponding flag bit by software. excepting being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit ge nerates an interrupt request within the intc like a periphera l interrupt request. writing a 1 to set x will leave set x unchanged at 0 but sets clr x . writing a 0 to set x has no effect. clr x is the flag bit. writing a 1 to clr x clears it. writing a 0 to clr x has no effect. if a 1 is written simultaneously to a pair of set x and clr x bits, clr x will be asserted, rega rdless of whether clr x was asserted before the write. 26.5.2.6 intc priority select regi sters (intc_psr0_ 3?intc_psr206_238) table 26-6. intc_sscir[0:7] field descriptions field description set set flag bits. writing a 1 sets the corresponding clr x bit. writing a 0 has no effect. each set x always will be read as a 0. clr clear flag bits. clr x is the flag bit. writing a 1 to clr x clears it provided that a 1 is not written simultaneously to its corresponding set x bit. writing a 0 to clr x has no effect. 0 interrupt request not pending within intc. 1 interrupt request pending within intc. offset: 0x0040 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pri0 0 0 0 0 pri1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 pri2 0 0 0 0 pri3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-8. intc priority select register 0?3 (intc_psr[0:3])
pxd20 microcontroller reference manual, rev. 1 26-10 freescale semiconductor preliminary?subject to change without notice offset: 0x00d0 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 pri236 0 0 0 0 pri237 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 pri238 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 26-9. intc priority select register 236-238 (intc_psr[236:238]) table 26-7. intc_psr0_3?intc_psr236_238 field descriptions field description pri n priority select. pri x selects the priority for interrupt requests. refer to section 26.6, functional description . table 26-8. intc priority select register address offsets intc_psr x _ x offset address intc_psr x _ x offset address intc_psr0_3 0x0040 intc_psr120_123 0x00b8 intc_psr4_7 0x0044 intc_psr124_127 0x00bc intc_psr8_11 0x0048 intc_psr128_131 0x00c0 intc_psr12_15 0x004c intc_psr132_135 0x00c4 intc_psr16_19 0x0050 intc_psr136_139 0x00c8 intc_psr20_23 0x0054 intc_psr140_143 0x00cc intc_psr24_27 0x0058 intc_psr144_147 0x00d0 intc_psr28_31 0x005c intc_psr148_151 0x00d4 intc_psr32_35 0x0060 intc_psr152_155 0x00d8 intc_psr36_39 0x0064 intc_psr156_159 0x00dc intc_psr40_43 0x0068 intc_psr160_163 0x00e0 intc_psr44_47 0x006c intc_psr164_167 0x00e4 intc_psr48_51 0x0070 intc_psr168_171 0x00e8 intc_psr52_55 0x0074 intc_psr172_175 0x00ec intc_psr56_59 0x0078 intc_psr176_179 0x00f0 intc_psr60_63 0x007c intc_psr180_183 0x00f4 intc_psr64_67 0x0080 intc_psr184_187 0x00f8
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-11 preliminary?subject to change without notice 26.6 functional description the functional description involves the areas of interrupt request s ources, priority management, and handshaking with the processor. note the intc has no spurious vector s upport. therefore, if an asserted peripheral or software settabl e interrupt request, whose pri n value in intc_psr0_3?intc_psr236_238 is higher than the pri value in intc_cpr, negates before the interrupt request to the processor for that peripheral or software settable inte rrupt request is acknowledged, the interrupt request to the proc essor still can assert or will remain asserted for that peripheral or softwa re settable interrupt request. in this case, the interrupt vector will correspond to th at peripheral or software settable interrupt request. also, the pri valu e in the intc_cpr will be updated with the corresponding pri n value in intc_psr n . furthermore, clearing the peripheral interrupt request?s enable bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. setting its enable bit or clea ring its mask bit while its flag bit is asserted has the same effect on the in tc as an interrupt event setting the flag bit. intc_psr68_71 0x0084 intc_psr188_191 0x00fc intc_psr72_75 0x0088 intc_psr192_195 0x0100 intc_psr76_79 0x008c intc_psr196_199 0x0104 intc_psr80_83 0x0090 intc_psr200_203 0x0108 intc_psr84_87 0x0094 intc_psr204_207 0x010c intc_psr88_91 0x0098 intc_psr208_211 0x0110 intc_psr92_95 0x009c intc_psr212_215 0x0114 intc_psr96_99 0x00a0 intc_psr216_219 0x0118 intc_psr100_103 0x00a4 intc_psr220_223 0x011c intc_psr104_107 0x00a8 intc_psr224_227 0x0120 intc_psr108_111 0x00ac intc_psr228_231 0x0124 intc_psr112_115 0x00b0 intc_psr232_235 0x0128 intc_psr116_119 0x00b4 intc_psr236_238 0x012c table 26-8. intc priority select register address offsets (continued) intc_psr x _ x offset address intc_psr x _ x offset address
pxd20 microcontroller reference manual, rev. 1 26-12 freescale semiconductor preliminary?subject to change without notice table 26-9. interrupt vectors irq # offset size (bytes) resource module section a (cpu section) ? ivor0 16 critical input (intc software vector mode) cpu ? ivor1 16 machine check / nmi cpu ? ivor2 16 data storage cpu ? ivor3 16 instruction storage cpu ?ivor4/ ivpr 16 external input (intc software vector mode) cpu ? ivor5 16 alignment cpu ? ivor6 16 program cpu ? ivor7 16 floating-point unavailable cpu ? ivor8 16 system call cpu ? ivor9 96 ap unavailable cpu ? ivor10 16 debug cpu ? ivor11 fixed interval timer cpu ? ivor12 watchdog timer cpu ? ivor13 data tlb error cpu ? ivor14 instruction tlb error cpu ? ivor15 debug cpu ? ivor16? ivor31 reserved ? ivor32 spe unavailable exception core ? ivor33 efp data exception core ? ivor34 efp round exception core section b (on-platform peripherals) 0 0x0000 16 software setable flag 0 software 1 0x0010 16 software setable flag 1 software 2 0x0020 16 software setable flag 2 software 3 0x0030 16 software setable flag 3 software
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-13 preliminary?subject to change without notice 4 0x0040 16 software setable flag 4 software 5 0x0050 16 software setable flag 5 software 6 0x0060 16 software setable flag 6 software 7 0x0070 16 software setable flag 7 software 8?9 0x0080? 0x0090 32 reserved 10 0x00a0 16 combined error edma 11 0x00b0 16 channel 0 edma 12 0x00c0 16 channel 1 edma 13 0x00d0 16 channel 2 edma 14 0x00e0 16 channel 3 edma 15 0x00f0 16 channel 4 edma 16 0x0100 16 channel 5 edma 17 0x0110 16 channel 6 edma 18 0x0120 16 channel 7 edma 19 0x0130 16 channel 8 edma 20 0x0140 16 channel 9 edma 21 0x0150 16 channel 10 edma 22 0x0160 16 channel 11 edma 23 0x0170 16 channel 12 edma 24 0x0180 16 channel 13 edma 25 0x0190 16 channel 14 edma 26 0x01a0 16 channel 15 edma 27 0x01b0 16 reserved 28 0x01c0 16 timeout software watchdog (swt0) 29 0x01d0 16 reserved 30 0x01e0 16 match on channel 0 stm 31 0x01f0 16 match on channel 1 stm table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 26-14 freescale semiconductor preliminary?subject to change without notice 32 0x0200 16 match on channel 2 stm 33 0x0210 16 match on channel 3 stm 34 0x0220 16 reserved 35 0x0230 16 ecc_dbd_platformflash | ecc_dbd_platformram ecsm 36 0x0240 16 ecc_sbc_platformflash | ecc_sbc_platformram ecsm 37 0x0250 16 reserved section c 38 0x0260 16 rtc real time clock (rtc) 39 0x0270 16 api autonomous periodic interrupt (api) 40 0x0280 16 reserved 41 0x0290 16 siu external irq_0 system integration unit lite (siul) 42 0x02a0 16 siu external irq_1 system integration unit lite (siul) 43 0x02b0 16 siu external irq_2 system integration unit lite (siul) 44 0x02c0 16 reserved 45 0x02d0 16 reserved 46 0x02e0 16 wakeup_irq_0 wkpu 47 0x02f0 16 wakeup_irq_1 wkpu 48 0x0300 16 wakeup_irq_2 wkpu 49 0x0310 16 wakeup_irq_3 wkpu 50 0x0320 16 reserved 51 0x0330 16 safe mode interrupt mc_me 52 0x0340 16 mode transition interrupt mc_me 53 0x0350 16 invalid mode interrupt mc_me 54 0x0360 16 invalid mode config mc_me 55 0x0370 16 reserved 56 0x0380 16 functional and destructive reset alternate event interrupt (ipi_int) mc_rgm table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-15 preliminary?subject to change without notice 57 0x0390 16 xosc counter expired (ipi_int_osc) xosc 58 0x03a0 16 reserved 59 0x03b0 16 pitimer channel 0 periodic interrupt timer (pit) 60 0x03c0 16 pitimer channel 1 periodic interrupt timer (pit) 61 0x03d0 16 pitimer channel 2 periodic interrupt timer (pit) 62 0x03e0 16 adc_eoc analog to digital converter 0 (adc0) 63 0x03f0 16 adc_er analog to digital converter 0 (adc0) 64 0x0400 16 adc_wd analog to digital converter 0 (adc0) 65 0x0410 16 flexcan_esr[err_int] flexcan 0 (can0) 66 0x0420 16 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan 0 (can0) 67 0x0430 16 reserved 68 0x0440 16 flexcan_buf_00_03 flexcan 0 (can0) 69 0x0450 16 flexcan_buf_04_07 flexcan 0 (can0) 70 0x0460 16 flexcan_buf_08_11 flexcan 0 (can0) 71 0x0470 16 flexcan_buf_12_15 flexcan 0 (can0) 72 0x0480 16 flexcan_buf_16_31 flexcan 0 (can0) 73 0x0490 16 flexcan_buf_32_63 flexcan 0 (can0) 74 0x04a0 16 dspi_sr[tfuf] dspi_sr[rfof] dspi 0 75 0x04b0 16 dspi_sr[eoqf] dspi 0 76 0x04c0 16 dspi_sr[tfff] dspi 0 77 0x04d0 16 dspi_sr[tcf] dspi 0 78 0x04e0 16 dspi_sr[rfdf] dspi 0 79 0x04f0 16 linflex_rxi linflex 0 80 0x0500 16 linflex_txi linflex 0 81 0x0510 16 linflex_err linflex 0 82 0x0520 16 reserved table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 26-16 freescale semiconductor preliminary?subject to change without notice 83 0x0530 16 reserved 84 0x0540 16 reserved 85 0x0550 16 flexcan_esr[err_int] flexcan 1 (can1) 86 0x0560 16 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan 1 (can1) 87 0x0570 16 reserved 88 0x0580 16 flexcan_buf_00_03 flexcan 1 (can1) 89 0x0590 16 flexcan_buf_04_07 flexcan 1 (can1) 90 0x05a0 16 flexcan_buf_08_11 flexcan 1 (can1) 91 0x05b0 16 flexcan_buf_12_15 flexcan 1 (can1) 92 0x05c0 16 flexcan_buf_16_31 flexcan 1 (can1) 93 0x05d0 16 flexcan_buf_32_63 flexcan 1 (can1) 94 0x05e0 16 dspi_sr[tfuf] dspi_sr[rfof] dspi 1 95 0x05f0 16 dspi_sr[eoqf] dspi 1 96 0x0600 16 dspi_sr[tfff] dspi 1 97 0x0610 16 dspi_sr[tcf] dspi 1 98 0x0620 16 dspi_sr[rfdf] dspi 1 99 0x0630 16 linflex_rxi linflex 1 100 0x0640 16 linflex_txi linflex 1 101 0x0650 16 linflex_err linflex 1 102 0x0660 16 reserved 103 0x0670 16 reserved 104 0x0680 16 reserved 105 0x0690 16 flexcan_esr[err_int] flexcan 2 (can2) 106 0x06a0 16 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan 2 (can2) 107 0x06b0 16 reserved table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-17 preliminary?subject to change without notice 108 0x06c0 16 flexcan_buf_00_03 flexcan 2 (can2) 109 0x06d0 16 flexcan_buf_04_07 flexcan 2 (can2) 110 0x06e0 16 flexcan_buf_08_11 flexcan 2 (can2) 111 0x06f0 16 flexcan_buf_12_15 flexcan 2 (can2) 112 0x0700 16 flexcan_buf_16_31 flexcan 2 (can2) 113 0x0710 16 flexcan_buf_32_63 flexcan 2 (can2) 114 0x0720 16 dspi_sr[tfuf] dspi_sr[rfof] dspi 2 115 0x0730 16 dspi_sr[eoqf] dspi 2 116 0x0740 16 dspi_sr[tfff] dspi 2 117 0x0750 16 dspi_sr[tcf] dspi 2 118 0x0760 16 dspi_sr[rfdf] dspi 2 119 0x0770 16 linflex_rxi linflex 2 120 0x0780 16 linflex_txi linflex 2 121 0x0790 16 linflex_err linflex 2 122 0x07a0 16 linflex_rxi linflex 3 123 0x07b0 16 linflex_txi linflex 3 124 0x07c0 16 linflex_err linflex 3 125 0x07d0 16 ibif inter-ic bus interface controller 0 (i2c0) 126 0x07e0 16 ibif inter-ic bus interface controller 1 (i2c1) 127 0x07f0 16 pitimer channel 3 periodic interrupt timer (pit) 128 0x0800 16 pitimer channel 4 periodic interrupt timer (pit) 129 0x0810 16 pitimer channel 5 periodic interrupt timer (pit) 130 0x0820 16 pitimer channel 6 periodic interrupt timer (pit) 131 0x0830 16 pitimer channel 7 periodic interrupt timer (pit) 132 0x0840 16 reserved 133 0x0850 16 reserved 134 0x0860 16 reserved table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 26-18 freescale semiconductor preliminary?subject to change without notice 135 0x0870 16 reserved 136 0x0880 16 reserved 137 0x0890 16 reserved 138 0x08a0 16 reserved 139 0x08b0 16 reserved 140 0x08c0 16 reserved 141 0x08d0 16 emios0_gfr [f8] enhanced modular i/o subsystem 0 (emios0) 142 0x08e0 16 emios0_gfr [f9] enhanced modular i/o subsystem 0 (emios0) 143 0x08f0 16 emios0_gfr[f 10] enhanced modular i/o subsystem 0 (emios0) 144 0x0900 16 emios0_gfr[f 11] enhanced modular i/o subsystem 0 (emios0) 145 0x0910 16 emios0_gfr[f 12] enhanced modular i/o subsystem 0 (emios0) 146 0x0920 16 emios0_gfr[f 13] enhanced modular i/o subsystem 0 (emios0) 147 0x0930 16 emios0_gfr[f 14] enhanced modular i/o subsystem 0 (emios0) 148 0x0940 16 emios0_gfr[f 15] enhanced modular i/o subsystem 0 (emios0) 149 0x0950 16 emios0_gfr[f16] en hanced modular i/o subsystem 0 (emios0) 150 0x0960 16 emios0_gfr[f17] en hanced modular i/o subsystem 0 (emios0) 151 0x0970 16 emios0_gfr[f18] en hanced modular i/o subsystem 0 (emios0) 152 0x0980 16 emios0_gfr[f19] en hanced modular i/o subsystem 0 (emios0) 153 0x0990 16 emios0_gfr[f20] en hanced modular i/o subsystem 0 (emios0) 154 0x09a0 16 emios0_gfr[f21] en hanced modular i/o subsystem 0 (emios0) table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-19 preliminary?subject to change without notice 155 0x09b0 16 emios0_gfr[f22] en hanced modular i/o subsystem 0 (emios0) 156 0x09c0 16 emios0_gfr[f23] en hanced modular i/o subsystem 0 (emios0) section d 157 0x09d0 16 emios1_gfr [f8] enhanced modular i/o subsystem 1 (emios1) 158 0x09e0 16 emios1_gfr [f9] enhanced modular i/o subsystem 1 (emios1) 159 0x09f0 16 emios1_gfr[f 10] enhanced modular i/o subsystem 1 (emios1) 160 0x0a00 16 emios1_gfr [f11] enhanced modular i/o subsystem 1 (emios1) 161 0x0a10 16 emios1_gfr[f12] en hanced modular i/o subsystem 1 (emios1) 162 0x0a20 16 emios1_gfr[f13] en hanced modular i/o subsystem 1 (emios1) 163 0x0a30 16 emios1_gfr[f 14] enhanced modular i/o subsystem 1 (emios1) 164 0x0a40 16 emios1_gfr[f 15] enhanced modular i/o subsystem 1 (emios1) 165 0x0a50 16 emios1_gfr[f 16] enhanced modular i/o subsystem 1 (emios1) 166 0x0a60 16 emios1_gfr[f 17] enhanced modular i/o subsystem 1 (emios1) 167 0x0a70 16 emios1_gfr[f 18] enhanced modular i/o subsystem 1 (emios1) 168 0x0a80 16 emios1_gfr[f 19] enhanced modular i/o subsystem 1 (emios1) 169 0x0a90 16 emios1_gfr[f 20] enhanced modular i/o subsystem 1 (emios1) 170 0x0aa0 16 emios1_gfr[f 21] enhanced modular i/o subsystem 1 (emios1) 171 0x0ab0 16 emios1_gfr[f 22] enhanced modular i/o subsystem 1 (emios1) table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 26-20 freescale semiconductor preliminary?subject to change without notice 172 0x0ac0 16 emios1_gfr[f 23] enhanced modular i/o subsystem 1 (emios1) 173 0x0ad0 16 ibif inter-ic bus interface controller 2 (i2c2) 174 0x0ae0 16 ibif inter-ic bus interface controller 3 (i2c3) 175 0x0af0 16 viu_irq video input unit (viu2) 176 0x0b00 16 reserved 177 0x0b10 16 reserved 178 0x0b20 16 reserved 179 0x0b30 16 reserved 180 0x0b40 16 fifo ov/uv dram controller 181 0x0b50 16 int dram priority manager 182 0x0b60 16 reserved 183 0x0b70 16 sgm_irg sound generator module (sgm) 184 0x0b80 16 vs_blank, ls_bf_vs, vsync display control unit (dcu3) 185 0x0b90 16 undrun display control unit (dcu3) 186 0x0ba0 16 parerr display control unit (dcu3) 187 0x0bb0 16 pdi display control unit (dcu3) 188 0x0bc0 16 vs_blank, ls_bf_vs, vsync display control unit lite (dculite) 189 0x0bd0 16 undrun display control unit lite (dculite) 190 0x0be0 16 parerr display control unit lite (dculite) 191 0x0bf0 16 pdi display control unit lite (dculite) 192 0x0c00 16 mctoi, scdetect[0:23] stepper motor controller (smc0) 193 0x0c10 16 mczi, aovi stepper stall detect 0 (ssd0) 194 0x0c20 16 mczi, aovi stepper stall detect 1 (ssd1) 195 0x0c30 16 mczi, aovi stepper stall detect 2 (ssd2) 196 0x0c40 16 mczi, aovi stepper stall detect 3 (ssd3) 197 0x0c50 16 mczi, aovi stepper stall detect 4 (ssd4) 198 0x0c60 16 mczi, aovi stepper stall detect 5 (ssd5) table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-21 preliminary?subject to change without notice 199 0x0c70 16 reserved 200 0x0c80 16 reserved 201 0x0c90 16 reserved 202 0x0ca0 16 reserved 203 0x0cb0 16 reserved 204 0x0cc0 16 reserved 205 0x0cd0 16 reserved 206 0x0ce0 16 reserved 207 0x0cf0 16 rle_int rle decoder 208 0x0d00 16 reserved 209 0x0d10 16 reserved 210 0x0d20 16 reserved 211 0x0d30 16 reserved 212 0x0d40 16 reserved 213 0x0d50 16 reserved 214 0x0d60 16 reserved 215 0x0d70 16 reserved 216 0x0d80 16 reserved 217 0x0d90 16 reserved 218 0x0da0 16 reserved 219 0x0db0 16 reserved 220 0x0dc0 16 reserved 221 0x0dd0 16 reserved 222 0x0de0 16 reserved 223 0x0df0 16 reserved 224 0x0e00 16 reserved 225 0x0e10 16 reserved table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 26-22 freescale semiconductor preliminary?subject to change without notice 26.6.1 interrupt request sources the intc has two types of interr upt requests, peripheral and softwa re configurable. these interrupt requests can assert on any clock cycle. 26.6.1.1 peripheral interrupt requests an interrupt event in a peripheral?s hardware sets a flag bit that resi des in the peripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three clocks. external interrupts are handled by the siu (see section 43.6.4, external interrupts ). 26.6.1.2 software configurable interrupt requests an interrupt request is triggered by software by writing a 1 to a set x bit in intc_sscir0_3?intc_sscir4_7 . this write sets the co rresponding flag bit, clr x , resulting in the interrupt request. the interrupt request is cleared by writing a 1 to the clr x bit. the time from the write to the set x bit to the time that th e intc starts to drive th e interrupt request to the processor is four clocks. 226 0x0e20 16 reserved 227 0x0e30 16 reserved 228 0x0e40 16 overrun quadspi 229 0x0e50 16 reserved 230 0x0e60 16 tfff quadspi 231 0x0e70 16 tcf quadspi 232 0x0e80 16 rfdf quadspi 233 0x0e90 16 cerr quadspi 234 0x0ea0 16 reserved 235 0x0eb0 16 reserved 236 0x0ec0 16 reserved 237 0x0ed0 16 reserved 238 0x0ee0 16 irq_0 gfx2d table 26-9. interrupt vectors (continued) irq # offset size (bytes) resource module
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-23 preliminary?subject to change without notice 26.6.1.3 unique vector for each interrupt request source each peripheral and software confi gurable interrupt request is assigne d a hardwired unique 9-bit vector. software configurable interrupts 0?7 are assigned vectors 0?7 respectively. the peripheral interrupt requests are assigned vectors 8 to as high as needed to in clude all the peripheral interrupt requests. the peripheral interrupt request input por ts at the boundary of the intc bl ock are assigned specific hardwired vectors within the intc. 26.6.2 priority management the asserted interrupt requests are comp ared to each other based on their pri x values set in intc_psr0_3?intc_psr236_238. the result is compared to pri in the associ ated intc_cpr. the results of those comparisons manage the priority of the isr executed by the associated processor. the associated lifo also assist s in managing that priority. 26.6.2.1 current priori ty and preemption the priority arbitrator, selector, encode r, and comparator subblocks shown in figure 26-1 compare the priority of the asserted inte rrupt requests to the current priority. if the priority of any asserted peripheral or software configurable interrupt reque st is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. al so, a unique vector for the preempting peripheral or software settable interrupt request is generated for intc interrupt acknowledge register (intc_iackr), and if in hardware vector mode, for the in terrupt vector provided to the processor. 26.6.2.1.1 priority ar bitrator subblock the priority arbitrator subblock for e ach processor compares all the prioriti es of all of the asserted interrupt requests assigned to that processor, both peripheral a nd software configurable. th e output of the priority arbitrator subblock is the highest of those priorities assigned to a gi ven processor. also, any interrupt requests which have this highest priority are output as asserted interrupt requests to the associated request selector subblock. 26.6.2.1.2 request selector subblock if only one interrupt request from the associated priority arbitrator subbloc k is asserted, then it is passed as asserted to the associ ated vector encoder subbloc k. if multiple interrupt re quests from the associated priority arbitrator subblock are asserted, only the one with the lowest vector passes as asserted to the associated vector encode r subblock. the lower vector is chosen regardless of the time order of the assertions of the peripheral or softwa re configurable interrupt requests. 26.6.2.1.3 vector encoder subblock the vector encoder subblock generate s the unique 9-bit vector for the as serted interrupt request from the request selector subblock for the associated processor.
pxd20 microcontroller reference manual, rev. 1 26-24 freescale semiconductor preliminary?subject to change without notice 26.6.2.1.4 priority co mparator subblock the priority comparator submodule compares the highe st priority output from the priority arbitrator submodule with pri in intc_c pr. if the priority comparator submodul e detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the processor. this interrupt request to the processor asserts whether this highest priority is raised above the value of pri in intc_cpr or the pri value in intc_cpr is lowered be low this highest priority. this high est priority then becomes the new priority which will be written to pri in intc_cpr when the interr upt request to the processor is acknowledged. interrupt requests whose pri n in intc_psr n are zero will not cause a preemption because their pri n will not be higher than pri in intc_cpr. 26.6.2.2 last-in first-out (lifo) the lifo stores the preempted pri values from the intc_cpr. therefore, becau se these priorities are stacked within the intc, if interrupt s need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the intc_cpr does not need to be loaded from the intc_cpr and stored onto the context stack. likewise at the end of the interrupt exce ption handler, the priority does not need to be loaded from the context stack and stored in to the intc_cpr. the pri value in the intc_cpr is pushed onto the lifo when the intc_iackr is read in softwarevector mode or the interrupt acknowledge signal from th e processor is asserted in hardware vector mode. the priority is popped into pri in the intc_cpr whenever the intc_eoir is written. although the intc supports 16 priorities, an isr execut ing with pri in the intc_cpr equal to 15 will not be preempted. therefore, the lifo supports the st acking of 15 priorities. ho wever, the lifo is only 14 entries deep. an entry for a priority of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treat ed. if the lifo is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. a priority of 0 woul d be an overwritten priority . however, the lifo will pop ?0?s if it is popped more times than it is pushed. th erefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty lifo. the lifo is not memory mapped. 26.6.3 handshaking with processor 26.6.3.1 software vect or mode handshaking this section describes handshaki ng in software vector mode. 26.6.3.1.1 acknowledging inte rrupt request to processor a timing diagram of the interrupt request and acknowledge handshaking in software vector mode and the handshake near the end of the inte rrupt exception handler, is shown in figure 26-10 . the intc examines the peripheral and software configur able interrupt requests. when it finds an asserted peripheral or software configurable interrupt request with a higher priority than pri in the associated intc_cpr, it asserts the interrupt request to the processor. the intvec field in the associated intc_iackr is updated with the preempting interrupt request?s vector when the interrupt request to the processor is asserted. the
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-25 preliminary?subject to change without notice intvec field retains that value until the next time the interrupt request to the processor is asserted. the rest of handshaking process is described in section 26.4.1.1, software vector mode . 26.6.3.1.2 end of interr upt exception handler before the interrupt exception handli ng completes, intc end-of-interrupt register (intc_eoir) must be written.when written, the associated lifo is popped so th e preempted priority is restored into pri of the intc_cpr. before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configur able interrupt request is negated. note to ensure proper operation acro ss all esys mcus, execute an mbar or msync instruction between the access to clear the flag bit and the write to the intc_eoir. when returning from the preemption, the intc does not search for the periphe ral or software settable interrupt request whose isr was pr eempted. depending on how much the isr progressed, that interrupt request may no longer even be asserted. when pri in intc_cpr is lowered to the priority of the preempted isr, the interrupt reques t for the preempted isr or any othe r asserted peripheral or software settable interrupt request at or below that priority wi ll not cause a preemption. in stead, after the restoration of the preempted context, the processor will return to the instruction address that it was to next execute before it was preempted. this next instruction is part of the preempt ed isr or the interrupt exception handler?s prolog or epilog. figure 26-10. software vector mode handshaking timing diagram 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108 0
pxd20 microcontroller reference manual, rev. 1 26-26 freescale semiconductor preliminary?subject to change without notice 26.6.3.2 hardware vector mode handshaking a timing diagram of the in terrupt request and acknow ledge handshaking in hard ware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 26-11 . as in software vector mode, the intc ex amines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than pri in intc_cpr, it as serts the interrupt request to the processor. the intvec field in the intc_i ackr is updated with the preempting peripheral or software settable interrupt request?s vector when th e interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. in addition, the value of the interrupt v ector to the processor matches the value of the intvec field in the intc_iackr. the rest of the handshaking is described in section 26.4.1.2, hardware vector mode . the handshaking near the end of the interrupt excepti on handler, that is the wri ting to the intc_eoir, is the same as in software vector mode. refer to section 26.6.3.1.2, end of interrupt exception handler. figure 26-11. hardware vector mode handshaking timing diagram 26.7 initialization/application information 26.7.1 initialization flow after exiting reset, all of the pri n fields in intc prior ity select registers (intc_psr0_3?intc_psr236_238) will be zero, and pri in intc current priority register (intc_cpr) will be 15. thes e reset values will prevent the intc from assert ing the interrupt request to the processor. the enable or mask bi ts in the peripherals are reset such that the peripheral interrupt requests 0 108 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-27 preliminary?subject to change without notice are negated. an initialization sequenc e for allowing the peripheral and so ftware settable in terrupt requests to cause an interrupt request to the proc essor is:interrupt_re quest_initialization: interrupt_request_initialization: configure vtes and hven in intc_mcr configure vtba in intc_iackr raise the pri n fields in intc_psr n set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr to zero enable processor recognition of interrupts 26.7.2 interrupt exception handler these example interrupt exception handlers use power architecture assembly code. 26.7.2.1 software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save srr0 and srr1 lis r3,intc_iackr@ha # form adjusted upper half of intc_iackr address lwz r3,intc_iackr@l(r3) # load intc_iackr, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi mtlr r3 # move intc_iackr contents into link register blrl # branch to isr; link register updated with epilog # address epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511
pxd20 microcontroller reference manual, rev. 1 26-28 freescale semiconductor preliminary?subject to change without notice isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # return to epilog 26.7.2.2 hardware vector mode this interrupt exception handler is useful with processor and system bus implementations which support a hardware vector. this example assu mes that each inte rrupt_exception_handler x only has space for four instructions, and therefore a branch to interrupt_exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue interrupt_exception_handler_continued x : code to create stack frame, save working register, and save srr0 and srr1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi bl isr x # branch to isr for interrupt with vector x epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 26.7.3 isr, rtos, and task hierarchy the rtos and all of the tasks under it s control typically execute with pri in intc current priority register (intc_cpr) having a value of 0. the rtos will execute the tasks accord ing to whatever priority scheme that it may have, but that priority scheme is independent and has a lo wer priority of execution than the priority scheme of the intc. in other words, the isrs execute above intc_cpr priority 0 and outside
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-29 preliminary?subject to change without notice the control of the rtos, the rtos executes at in tc_cpr priority 0, and while the tasks execute at different priorities under the control of the rtos , they also execute at intc_cpr priority 0. if a task shares a resource with an isr and the pcp is being used to mana ge that shared resource, then the task?s priority can be elevated in the intc_c pr while the shared resource is being accessed. an isr whose pri n in intc priority select registers (intc_psr0_3?intc_psr236_238) has a value of 0 will not caus e an interrupt request to the pr ocessor, even if its peripheral or software settable interrupt request is asserted. for a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause it to remain negated, which consequently also will not cause an interrupt request to the processor. since the isrs are outside the control of th e rtos, this isr will not r un unless called by another isr or the interrupt exception handler , perhaps after executing another isr. 26.7.4 order of execution an isr with a higher priority can pr eempt an isr with a lower priority , regardless of the unique vectors associated with each of their periphe ral or software configur able interrupt requests. however, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they assert ed. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software configurable interrupt requests asserted. the example in table 26-10 shows the order of execution of both is rs with different priorities and the same priority table 26-10. order of isr execution example step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 1 isr208 isr308 isr408 interrupt exception handler 1 rtos at priority 0 is executing. x 0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x 1 3 peripheral interrupt request 400 at priority 4 is asserts. interrupt taken. x 4 4 peripheral interrupt request 300 at priority 3 is asserts. x 4 5 peripheral interrupt request 200 at priority 3 is asserts. x 4 6 isr408 completes. interrupt exception handler writes to intc_eoir. x 1 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x 3
pxd20 microcontroller reference manual, rev. 1 26-30 freescale semiconductor preliminary?subject to change without notice 26.7.5 priority ceiling protocol 26.7.5.1 elevating priority the pri field in intc_cpr is elevated in the osek pcp to the ceili ng of all of the priorities of the isrs that share a resource. this protocol allows coherent accesses of the isrs to that shared resource. for example, isr1 has a priority of 1, isr2 has a priority of 2, and is r3 has a priority of 3. they share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr to 3, the ceiling of all of the isr priorities. after they rel ease the resource, the pri value in intc_cpr can be lowered. if they do not raise thei r priority, isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possibly co rrupting the shared resource. anot her possible failure mechanism is deadlock if the higher priority isr needs the lower pr iority isr to release the resource before it can continue, but the lower priority isr cannot release the resource until th e higher priority isr completes and execution returns to the lower priority isr. using the pcp instead of disabli ng processor recognition of all inte rrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. for ex ample, while isr3 cannot preempt isr1 while it is accessing the shared resource, all of the isrs with a priority higher than 3 can preempt isr1. 26.7.5.2 ensuring coherency a scenario can cause non-coherent accesses to the shared resource. fo r example, isr1 and isr2 are both running on the same cpu and both share a resource. is r1 has a lower priority than isr2. isr1 is 8 isr208 completes. interrupt exception handler writes to intc_eoir. x 1 9 interrupt taken. isr308 starts to execute. x 3 10 isr308 completes. interrupt exception handler writes to intc_eoir. x 1 11 isr108 completes. interrupt exception handler writes to intc_eoir. x 0 12 rtos continues execution. x 0 1 isr108 executes for peripheral interrupt request 100 beca use the first eight isrs are for software configurable interrupt requests. table 26-10. order of isr execution example (continued) step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 1 isr208 isr308 isr408 interrupt exception handler
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-31 preliminary?subject to change without notice executing and writes to the intc_cpr. the instruction fo llowing this store is a store to a value in a shared coherent data block. either immediately before or at the same time as th e first store, the intc asserts the interrupt request to the processor because the periphe ral interrupt request for isr2 has asserted. as the processor is responding to the interrupt request from the intc, and as it is aborting transactions and flushing its pipeline, it is possible that both stor es will be executed. isr2 ther eby thinks that it can access the data block coherently, but th e data block has been corrupted. osek uses the getresource and rele aseresource system services to mana ge access to a shared resource. to prevent corruption of a coherent data block, modifications to pri in intc_cpr can be made by those system services with the code sequence: disable processor recognition of interrupts pri modification enable processor recognition of interrupts 26.7.6 selecting priorities accordin g to request rates and deadlines the selection of the priorities for the isrs can be made using rate monotonic scheduling (rms) or a superset of it, deadline monotonic scheduling (dms). in rms, the is rs which have higher request rates have higher priorities. in dms, if th e deadline is before the next time th e isr is requested, then the isr is assigned a priority according to the time from the request for the isr to the deadline, not from the time of the request for the isr to the next request for it. for example, isr1 executes every 100 ? s, isr2 executes every 200 ? s, and isr3 executes every 300 ? s. isr1 has a higher priority than isr2 which has a higher priority than isr3 ; however, if isr3 has a deadline of 150 ? s, then it has a higher priority than isr2. the intc has 16 priorities, which may be less than the number of isrs. in this case, the isrs should be grouped with other isrs that have si milar deadlines. for example, a prio rity could be allocated for every time the request rate doubles. isrs wi th request rates around 1 ms would sh are a priority, is rs with request rates around 500 ? s would share a priority, isrs with request rates around 250 ? s would share a priority, etc. with this approach, a ra nge of isr reque st rates of 2 16 could be included, rega rdless of the number of isrs. reducing the number of priorities reduc es the processor?s ability to meet its deadlines. however, reducing the number of priorities can reduce the size and latency through the in terrupt controller. it also allows easier management of isrs with si milar deadlines that share a resource. they do not need to use the pcp to access the shared resource. 26.7.7 software configurab le interrupt requests the software configurable interrupt requests can be used in two ways. they can be used to schedule a lower priority portion of an isr and they may also be used by processors to interrupt othe r processors in a multiple processor system. 26.7.7.1 scheduling a lower priority portion of an isr a portion of an isr needs to be executed at the pri x value in intc_psr0_3?intc_psr236_238, which becomes the pri value in intc_cpr with the inte rrupt acknowledge. the isr, however, can have a
pxd20 microcontroller reference manual, rev. 1 26-32 freescale semiconductor preliminary?subject to change without notice portion that does not need to be executed at this higher priority. th erefore, executing the later portion that does not need to be executed at th is higher priority can prevent the ex ecution of isrs wh ich do not have a higher priority than the earlier porti on of the isr but do have a higher pr iority than what the later portion of the isr needs. this preemptive scheduling ineffi ciency reduces the processor?s ability to meet its deadlines. one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority por tion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option is fo r the isr, after co mpleting the higher priority portion, to set a set x bit in intc_sscir0_3?intc_sscir4_7. writing a 1 to set x causes a software configurable interrupt reque st. this software configurable in terrupt request will usually have a lower pri x value in the intc_psr x _ x and will not cause preemptive scheduling inefficiencies. after generating a software settable interru pt request, the higher priority isr completes. the lower priority isr is scheduled according to its priority. execution of the higher priority isr is not resumed after the completion of the lower priority isr. 26.7.7.2 scheduling an is r on another processor because the set x bits in the intc_sscir x _ x are memory mapped, processors in multiple-processor systems can schedule isrs on the other processors. one applicatio n is that one processor wants to command another processor to perform a piece of work and the initia ting processor does not need to use the results of that work. if the in itiating processor is concerned that the processor execut ing the software configurable isr has not completed the work before asking it to again execute the isr, it can check if the corresponding clr x bit in intc_sscir x _ x is asserted before again writing a 1 to the set x bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processo r to then access it. furt hermore, after the second processor has completed accessing th e block of data, the first proce ssor again wants to access it. the accesses to the block of data must be done coherently. to do this, the first processo r writes a 1 to a set x bit on the second processor. after accessing the bl ock of data, the second processor clears the corresponding clr x bit and then writes 1 to a set x bit on the first processor, in forming it that it can now access the block of data. 26.7.8 lowering priori ty within an isr a common method for avoiding preemptive scheduling inefficiencies with an isr whose work spans multiple priorities (see section 26.7.7.1, scheduling a lower priority portion of an isr) is to lower the current priority. however, the intc has a lifo whose depth is determ ined by the number of priorities. note lowering the pri value in intc_cpr within an isr to below the isr?s corresponding pri value in intc_psr0_3?intc_psr236_238 allows more preemptions than the lifo depth can support. therefore, the intc does not support lowering the current pr iority within an isr as a way to avoid preemptive scheduling inefficiencies.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 26-33 preliminary?subject to change without notice 26.7.9 negating an interrupt request outside of its isr 26.7.9.1 negating an interrupt request as a side effect of an isr some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request. for example, reading a spec ific register can clear the flag bits and their corresponding interrupt requests. this clearing as a side effect of servicing a peripheral in terrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose isr presently is executing. this negating of a periphe ral interrupt request outside of its isr can be a desired effect. 26.7.9.2 negating multiple in terrupt requests in one isr an isr can clear other flag bits besi des its own. one reason that an isr cl ears multiple flag bits is because it serviced those flag bits, and therefore the isrs for these flag bits do not need to be executed. 26.7.9.3 proper setting of in terrupt request priority whether an interrupt request negates outside its own isr due to the side effect of an isr execution or the intentional clearing a flag bit, the pr iorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. their pri x values in intc_psr0_3?intc_psr236_238 must be selected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, those flag bits can cause the interrupt reque st to the processor to assert. furthe rmore, the clearing of these other flag bits also has the same ti ming relationship to the writing to intc_sscir0_3?intc_sscir4_7 as the clearing of the flag bit that caused the present isr to be executed (see section 26.6.3.1.2, end of interrupt exception handler ) . a flag bit whose enable bit or mask bit negates its peripheral interrupt request can be clea red at any time, regardless of the periphera l interrupt request?s pri x value in intc_psr x _ x . 26.7.10 examining lifo contents in normal mode, the user does not need to know the contents of the lifo. he may not even know how deeply the lifo is nested. however, if he wants to read the contents, such as in debug mode, they are not memory mapped. the contents can be read by popping the lifo and reading the pri field in either intc_cpr. the code sequence is: pop_lifo: store to intc_eoir load intc_cpr, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when the examination is complete, the lifo can be restored using this code sequence: push_lifo: load stacked pri value and store to intc_cpr load intc_iackr if stacked pri values are not depleted, branch to push_lifo
pxd20 microcontroller reference manual, rev. 1 26-34 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-1 preliminary?subject to change without notice chapter 27 lin controller (linflexd) 27.1 introduction the linflexd (local interconnect network flexible with dma support) controller inte rfaces the lin network and supports the lin prot ocol versions 1.3, 2.0, 2.1 and j2602 in both master and slave modes. linflexd includes a lin mode that provides additional features (compa red to standard uart) to ease lin implementation, improve system robustness, minimize cpu load and allow slave node resynchronization. figure 27-1 shows the linflexd block diagram. figure 27-1. linflexd block diagram 27.2 main features the linflexd controller can operate in several modes, each of which has a distinct set of features. these distinct features are descri bed in the following sections. in addition, the linflexd c ontroller has several featur es common to all modes: ? fractional baud rate generator lin protocol handler register model / application interface buffer interface lin status baud rate filter config. message slave lin control config control status message handler master message handler id filters (1) 1 filter activation optional
pxd20 microcontroller reference manual, rev. 1 27-2 freescale semiconductor preliminary?subject to change without notice ? 3 operating modes for power saving and configuration registers lock ? initialization ?normal ?sleep ? 2 test modes ? loop back ?self test ? maskable interrupts 27.2.1 lin mode features ? supports lin protocol versions 1.3, 2.0, 2.1 and j2602 ? master mode with aut onomous message handling ? classic and enhanced checksum calculation and check ? single 8-byte buffer for transmission/reception ? extended frame mode for in -application programming purposes ? wake-up event on dominant bit detection ? true lin field state machine ? advanced lin error detection ? header, response and frame timeout ? slave mode ? autonomous header handling ? autonomous transmit/receive data handling ? lin automatic resynchronization, allowi ng operation with firc as clock source ? identifier filters for autonomous message handling in slave mode 27.2.2 uart mode features ? full-duplex communication ? selectable frame size: ? 8-bit frame ? 9-bit frame ? 16-bit frame ? 17-bit frame ? selectable parity: ? even ?odd ?0 ?1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-3 preliminary?subject to change without notice ? 4-byte buffer for reception, 4-byte buffer for transmission ? 12-bit counter for timeout management 27.3 the lin protocol the lin (local interconnect networ k) is a serial communication prot ocol. the topology of a lin network is shown in figure 27-2 . a lin network consists of: ? one master ? several slave ? the lin bus a master node contains the master ta sk as well as a slave task, all ot her nodes contain a slave task only. the master node decides when and which frame shal l be transferred on the bus. the slave task provides the data to be transported by the frame. figure 27-2. lin network topology 27.3.1 dominant and recessive logic levels the lin bus defines two l ogic levels, ?dominant? a nd ?recessive?, as follows: ? dominant: logical low level (0) ? recessive: logical high level (1) 27.3.2 lin frames a frame consists of a header provided by the master task and a response provided by the slave task, as shown in figure 27-3 . lin master node lin slave node 1 lin slave node n lin lin lin rx tx lin transceiver linflexd controller mcu lin bus application
pxd20 microcontroller reference manual, rev. 1 27-4 freescale semiconductor preliminary?subject to change without notice figure 27-3. lin frame structure 27.3.3 lin header the header consists of: ? a break field (described in section 27.3.3.1, break field ) ? a sync (described in section 27.3.3.2, sync ) ? an identifier (described in section 27.3.4.2, identifier ) the slave task associated with th e identifier provides the response. 27.3.3.1 break field the break field, shown in figure 27-4 , is used to signal the beginning of a new frame. it is always generated by the master and consists of: ? at least 13 dominant bits including the start bit ? at least one recessive bit that functions as break delimiter figure 27-4. break field 27.3.3.2 sync the sync pattern is a byte consisting of altern ating dominant and recessi ve bits as shown in figure 27-5 . it forms a data value of 0x55. header response header response master task slave task 1 slave task 2 frame slot frame header response space response start bit break delimiter
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-5 preliminary?subject to change without notice figure 27-5. sync pattern 27.3.4 response the response consists of: ? a data field (described in section 27.3.4.1, data field ) ? a checksum (described in section 27.3.4.3, checksum ) the slave task interested in the data associated with the identifier re ceives the response and verifies the checksum. 27.3.4.1 data field the structure of the data field tran smitted on the lin bus is shown in figure 27-6 . the lsb of the data is sent first and the msb last. the star t bit is encoded as a dominant bit and the stop bit is encoded as a recessive bit. figure 27-6. structure of the data field 27.3.4.2 identifier the identifier, shown in figure 27-7 , consists of two sub-fields: ? the identifier value (in bits 0?5) ? the identifier parity (in bits 6?7) the parity bits p0 and p1 are defined as follows: ? p0 = id0 xor id1 xor id2 xor id4 ? p1 = not(id1 xor id3 xor id4 xor id5) figure 27-7. identifier 27.3.4.3 checksum the checksum contains the inve rted 8-bit sum (with carry) ove r one of two possible groups: start bit stop bit start bit lsb msb stop bit byte field start bit id0 p1 stop bit id1 id2 id3 id4 id5 p0
pxd20 microcontroller reference manual, rev. 1 27-6 freescale semiconductor preliminary?subject to change without notice ? the classic checksum sums all data bytes, and is used for communication with lin 1.3 slaves. ? the enhanced checksum sums all data bytes and th e identifier, and is used for communication with lin 2.0 (or later) slaves. 27.4 linflexd and software intervention the increasing number of communicat ion peripherals embedde d on microcontrollers (for example, can, lin, spi) requires more and more cpu resources for the communicat ion management. even a 32-bit microcontroller is overloade d if its peripherals do no t provide high level featur es to autonomously handle the communication. even though the lin protocol with a maximum baud rate of 20 kbps is rela tively slow, it still generates a non-negligible load on the cpu if the lin is implem ented on a standard uart, as is usually the case. to minimize the cpu load in master mode, li nflexd handles the lin messages autonomously. in master mode, once the so ftware has triggered the header transm ission, linflexd doe s not request any software (that is, applicat ion) intervention until the next header transmission request in transmission mode or until the checksum r eception in reception mode. to minimize the cpu load in slave mode, linf lexd requires software intervention only to: ? trigger transmission or reception or data discard depending on the identifier ? write data into the buffer (tra nsmission mode) or read data fr om the buffer (reception mode) after checksum reception if filter mode is activated for sl ave mode, linflexd require s software intervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) the software uses the control, stat us and configuration registers to: ? configure lin parameters (for example, baud rate or mode) ? request transmissions ? handle receptions ? manage interrupts ? configure lin error and timeout detection ? process diagnostic information the message buffer stores transm itted or received lin frames. 27.5 summary of operating modes the linflexd controller has three operating modes: ? normal ? initialization ?sleep after a hardware reset, the linf lexd controller is in sleep m ode to reduce power consumption.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-7 preliminary?subject to change without notice the transitions between th ese modes are shown in figure 27-8 . the software instructs linflexd to enter initialization mode or sleep mode by setting lincr1[init] or lincr1 [sleep], respectively. figure 27-8. linflexd controller operating modes in addition to these controller-level operating mode s, the linflexd controller also supports several protocol-level modes: ? lin mode: ? master mode ? slave mode ? slave mode with identifier filtering ? slave mode with automatic resynchronization ? uart mode ? test modes: ? loop back mode ?self test mode these modes are discussed in de tail in subsequent sections. 27.6 controller-level operating modes 27.6.1 initialization mode the software initialization can be done while the hardware is in initiali zation mode. to enter or exit this mode, the software sets or cl ears lincr1[init], respectively. in initialization mode, all message transfers to and from the lin bus are stopped and the lin bus output (lintx) is recessive. entering initialization mode does not cha nge any of the configuration registers. to initialize the linflexd controller, the software must: sleep initialization normal s l e e p s l e e p * i n i t reset s l e e p l i n r x d o m i n a n t s l e e p * i n i t sl eep * i n i t
pxd20 microcontroller reference manual, rev. 1 27-8 freescale semiconductor preliminary?subject to change without notice ? select the desired mode (master, slave or uart) ? set up the baud rate register ? if lin slave mode with filter activation is selected, initialize the identifier list 27.6.2 normal mode after initialization is complete, the software must clear lincr1[init] to put the linflexd controller into normal mode. 27.6.3 sleep (low-power) mode to reduce power consumption, linfle xd has a low-power mode called sleep mode. in this mode, the linflexd clock is st opped. consequently, the linfle xd will not update the stat us bits, but software can still access the li nflexd registers. to enter this mode, the software must set lincr1[sleep]. linflexd can be awakened (exit sleep mode) in one of two ways: ? the software clears lincr1[sleep] ? automatic wake-up is enabled (lincr1[awum] is set) and linflexd de tects lin bus activity (that is, if a wakeup pulse of 150 ? s is detected on the lin bus) on lin bus activity detection, hardware automati cally performs the wake-up sequence by clearing lincr1[sleep] if lincr1[a wum] is set. to exit from sleep m ode if lincr1[awum] is cleared, the software must clear lincr1[sleep ] when a wake-up event occurs. 27.7 lin modes 27.7.1 master mode in master mode, the software uses the me ssage buffer to handle the lin messages. master mode is selected when lincr1[mme] is set. 27.7.1.1 lin header transmission according to the lin protocol, a ny communication on the lin bus is triggered by the master sending a header. the header is transmitted by the master task while the data is transmitted by the slave task of a node. to transmit a header with linflexd the application must set up the id entifier, the data field length and configure the message (direction and checksum type) in the bidr regist er before requesting the header transmission by set ting lincr2[htrq].
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-9 preliminary?subject to change without notice 27.7.1.2 data transmission (tr ansceiver as publisher) when the master node is publisher of the data corresponding to the identif ier sent in the header, then the slave task of the master ha s to send the data in the re sponse part of the lin frame . therefore, the software must provide the data to linflexd before requesting the header transmi ssion. the software stores the data in the message buffer bdr. according to the data field length linflexd tran smits the data and the checksum. the software uses the bi dr[ccs] bit to configure the checksu m type (classic or enhanced) for each message. the direction of the message buffer is controlled by th e bidr[dir] bit. when the software sets this bit the response is sent by linflexd (publ isher). clearing this bit configures the message buffer as subscriber. 27.7.1.3 data reception (transceiver as subscriber) to receive data from a slave node, the master sends a header with the corres ponding identifier. linflexd stores the data received from the slave in the messag e buffer and stores the message status in the linsr. 27.7.1.4 error dete ction and handling linflexd is able to detect and handle lin communicat ion errors. a code stored in the lin error status register (linesr) signals the errors to the software. table 27-1 lists the errors detected in ma ster mode and the linflexd contro ller?s response to these errors. 27.7.2 slave mode in slave mode the software uses the me ssage buffer to handle the lin messages. slave mode is selected when the lincr1[mme] is cleared. table 27-1. errors in master mode error description linflexd response to error bit error during transmission, the value read back from the bus differs from the transmitted value ? stops the transmission of the frame after the corrupted bit ? generates an interrupt if linier[beie] is set ? returns to idle state framing error a dominant state has been sampled on the stop bit of the currently received character (sync field, identifier, or data field) if encountered during reception: ? discards the current frame ? generates an interrupt if linier[feie] is set ? returns immediately to idle state checksum error the computed checksum does not match the received checksum if encountered during reception: ? discards the current frame ? generates an interrupt if linier[ceie] is set ? returns to idle state response and frame timeout refer to section 27.12.1, 8-bit timeout counter, for more details
pxd20 microcontroller reference manual, rev. 1 27-10 freescale semiconductor preliminary?subject to change without notice 27.7.2.1 data transmission (tr ansceiver as publisher) when linflexd receives the identifier, an rx interrupt is generated. the software must: ? read the received id in the bidr register ? fill the bdr registers ? specify the data field lengt h using the bidr[dfl] field ? trigger the data transmi ssion by setting lincr2[dtrq] one or several identifier filters can be configur ed for transmission by sett ing the dir bits in the corresponding ifcr registers and ac tivated by setting one or severa l bits in the ifer register. when at least one identifier filter is configured in transmission and ac tivated, and if the received id matches the filter, a specific tx interrupt is generated. typically, the software has to copy the data from ram locations to th e bdrl and bdrm registers. to copy the data to the right location, the software has to identify the data by means of the identifier. to avoid this and to ease the access to the ram locations, the linflexd controller provide s a filter match index. this index value is the number of the fi lter which matched the received identifier. the software can use the index in th e ifmi register to dir ectly access the pointer wh ich points to the right data array in the ram area and copy this data to the bdrl and bdrm registers (see figure 27-10 ). using a filter avoids the software having to configure the direction, the data field length and the checksum type in the bdir register. the so ftware fills the bdrl and bdrm registers and triggers the data transmission by set ting lincr2[dtrq]. if linflexd cannot provide enough tx identifier filters to handle all identifiers the software has to transmit data for, then a filter can be configured in mask mode (refer to section 27.7.3, slave mode with identifier filtering ) in order to manage several identifiers with one filter only. 27.7.2.2 data reception (transceiver as subscriber) when linflexd receives the identifier, an rx interrupt is generated. the software must: ? read the received id in the bidr register ? specify the data field length using the bidr[dfl] field before the reception of the stop bit of the first byte of data field when the checksum reception is comp leted, an rx interrupt is generated to allow the software to read the received data in the bdr registers. one or several identifier filters can be configured for reception by cl earing the dir bit in the corresponding ifcr registers and activated by clearing one or several b its in the ifer register. when at least one identifier filter is configured in reception and activated, and if the received id matches the filter, an rx interrupt is genera ted after the checksum reception only. typically, the software has to copy the data from the bdrl and bdrm registers to ram locations. to copy the data to the right location, the software has to identify the data by means of the identifier. to avoid
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-11 preliminary?subject to change without notice this and to ease the access to the ram locations, the linflexd controller provide s a filter match index. this index value is the number of the fi lter which matched the received identifier. the software can use the index in th e ifmi register to dir ectly access the pointer wh ich points to the right data array in the ram area and c opy this data from the bdrl and bdrm registers to the ram (see figure 27-10 ). using a filter avoids the so ftware reading the id value in the bidr register, and configuring the direction, the data field length and the checks um type in the bidr register. if linflexd cannot provide enough rx identifier filters to handle all identifiers the software has to receive the data for, then a filter can be configured in mask mode (refer to section 27.7.3, slav e mode with identifier filtering ) in order to manage several identifiers with one filter only. 27.7.2.3 data discard when linflexd receives the identifier, an rx interr upt is generated. if the re ceived identifier does not concern the node, the software must set lincr2[ddrq]. linfle xd returns to idle state. 27.7.2.4 error dete ction and handling table 27-2 lists the errors detected in sl ave mode and the linflexd contro ller?s response to these errors. table 27-2. errors in slave mode error description linflexd response to error bit error during transmission, the value read back from the bus differs from the transmitted value ? stops the transmission of the frame after the corrupted bit ? generates an interrupt if linier[beie] is set ? returns to idle state framing error a dominant state has been sampled on the stop bit of the currently received character (sync field, identifier, or data field) if encountered during reception: ? discards the current frame ? generates an interrupt if linier[feie] is set ? returns immediately to idle state checksum error the computed checksum does not match the received checksum if encountered during reception: ? discards the received frame ? generates an interrupt if linier[ceie] is set ? returns to idle state header error an error occurred during header reception (break delimiter error, inconsistent sync field, header timeout) if encountered during header reception, a break field error, an inconsistent sync field, or a timeout: ? discards the header ? generates an interrupt if linier[heie] is set ? returns to idle state
pxd20 microcontroller reference manual, rev. 1 27-12 freescale semiconductor preliminary?subject to change without notice 27.7.2.5 valid header a received header is considered as valid when it has been received corr ectly according to the lin protocol. if a valid break field and break delim iter come before the end of the cu rrent header, or at any time during a data field, the current header or data is discarded and the state m achine synchronizes on this new break. 27.7.2.6 valid message a received or transmitted message is considered as valid when the data has been received or transmitted without error according to the lin protocol. 27.7.2.7 overrun after the message buffer is full, th e next valid message reception causes an overrun and a message is lost. the linflexd controller sets linsr[bof] to si gnal the overrun condition. which message is lost depends on the configuration of the rx message buffer: ? if the buffer lock function is di sabled (lincr1[rblm] cleared), th e last message stored in the buffer is overwritten by the new incoming message. in this case, the latest message is always available to the software. ? if the buffer lock function is enabled (lincr1[rblm] set), the most recent message is discarded and the previous message is available in the buffer. 27.7.3 slave mode with identifier filtering in the lin protocol, the identifier of a message is not associated with the address of a node but related to the content of the message. consequently a transmit ter broadcasts its message to all receivers. when a slave node receives a header, it decides - depending on th e identifier value - whethe r the software needs to receive or send a res ponse. if the message does not target the node , it must be discar ded without software intervention. to fulfill this requirement, the linflexd controller provides configurable filt ers in order to request software intervention only if needed. this hardware filtering saves cpu resour ces which would otherwise be needed by software for filtering. the filtering is accomplished through the use of ifcr registers. these registers have the names ifcr0 through ifcr. this section also uses the nomenclature ifcr 2n and ifcr 2n+1 ; in this nomenclature, n is an integer, and the corresponding ifcr register is calculated using the formula in the subscript. 27.7.3.1 filter submodes usually each of the eight ifcr registers is used to fi lter one dedicated identifier, but this means that the linflexd controller could filter a maximum of eight identifiers. in order to be able to handle more identifiers, the filters can be configured to operate as masks. table 27-3 describes the two avai lable filter submodes.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-13 preliminary?subject to change without notice the bit mapping and register organization in these two submodes is shown in figure 27-9 . figure 27-9. filter configuration - register organization 27.7.3.2 identifier filter submode configuration the identifier filters are configured in the ifcr register s. to configure an identifier filter the filter must first be deactivated by clearing th e corresponding bit in the ifer[fact] field. the submode (identifier list or mask) for the corresponding if cr register is confi gured by the ifmr[ifm] field. for each filter, the ifcr register is used to configure: ? the id or mask ? the direction (tx or rx) ? the data field length ? the checksum type if no filter is active, an rx interrupt is generated on any received identifier event. table 27-3. filter submodes submode description identifier list both filter regi sters are used as identifier registers. all bits of the incoming identifier must match the bits specified in the filter register. this is the default submode for the linflexd controller. mask the identifier registers are associ ated with mask registers specifying which bits of the identifier are handled as ?must match? or as ?don?t care?. ifcr x identifier id bit mapping identifier filter re gister organization ccs dir identifier filter configuration ifcr 2n identifier identifier ifcr 2n+1 ifm = 0 identifier filter submode ifcr 2n identifier mask ifcr 2n+1 ifm = 1 identifier list submode mask submode dfl
pxd20 microcontroller reference manual, rev. 1 27-14 freescale semiconductor preliminary?subject to change without notice if at least one active filter is conf igured as tx, all received identifiers matching this filter generate a tx interrupt. if at least one active filter is conf igured as rx, all received identifiers matching this filter generate an rx interrupt. if no active filter is configured as rx, all received identi fiers not matching tx filter(s) generate an rx interrupt. further details are provided in table 27-4 and figure 27-10 . figure 27-10. identifier match index table 27-4. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector 0 0 0 - rx interrupt on all ids a (a > 0) a 0 - tx interrupt on ids matching the filters, - rx interrupt on all other ids if bf bit is set, no rx interrupt if bf bit is reset n (n = a + b) a (a > 0) b (b > 0) - tx interrupt on ids matching the tx filters, - rx interrupt on ids matching the rx filters, - all other ids discarded (no interrupt) b (b > 0) 0 b - rx interrupt on ids matching the filters, - tx interrupt on all other ids if bf bit is set, no tx interrupt if bf bit is reset ifmi message0 message1 message2 data pointers table ram @ +
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-15 preliminary?subject to change without notice 27.7.4 slave mode with automatic resynchronization automatic resynchronization must be enabled in slave mode if f ipg_clock_lin tolerance is greater than 1.5%. this feature compensates a deviation up to 14%, as specified in the lin standard. this mode is similar to sl ave mode as described in section 27.7.2, slave mode, with the addition of automatic resynchroni zation enabled by the lincr1[lase] bit. in this mode linflexd adjusts the fractional baud rate generator af ter each synch field reception. 27.7.4.1 automatic resynchronization method when automatic resynchronization is enabled, after each lin break, the time dura tion between five falling edges on rdi is sampled on as shown in figure 27-11 . then the lfdiv value (and its associated linibrr and linfbrr registers) ar e automatically updated at the end of the fifth falling edge. during lin sync field measur ement, the linflexd state m achine is stopped and no data is transferred to the data register. figure 27-11. lin sync field measurement lfdiv is an unsigned fixed point number. the mantissa is coded on 20 bi ts in the linibrr register and the fraction is coded on 4 bits in the linfbrr register. if lincr1[lase] is set, lfdiv is automatical ly updated at the end of each lin sync field. three registers are used internally to manage the auto-update of the linflexd divider (lfdiv): ? lfdiv_nom (nominal value written by soft ware at linibrr a nd linfbrr addresses) ? lfdiv_meas (results of the field synch measurement) ? lfdiv (used to genera te the local baud rate) on transition to idle, break or break delimiter state due to any error or on rece ption of a complete frame, hardware reloads lfdiv with lfdiv_nom. lin break break bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin sync field lfdiv(n) lfdiv(n+1) t br = baud rate period t br delim. t = clock period t br =16.lfdiv.t measurement = 8.t br lfdiv = tbr/(16.t)
pxd20 microcontroller reference manual, rev. 1 27-16 freescale semiconductor preliminary?subject to change without notice 27.7.4.2 deviation error on the sync field the deviation error is checke d by comparing the current baud rate (relative to the slave oscillator) with the received lin sync field (relative to the master os cillator). two checks are performed in parallel. the first check is based on a measurement between the fi rst falling edge and the last falling edge of the sync field: ? if d1 > 14.84%, lhe is set. ? if d1 < 14.06%, lhe is not set. ? if 14.06% < d1 < 14.84%, lhe can be either set or reset depending on th e dephasing between the signal on linflexd_rx pin the f ipg_clock_lin clock. the second check is based on a meas urement of time between each fa lling edge of the sync field: ? if d2 > 18.75%, lhe is set. ? if d2 < 15.62%, lhe is not set. ? if 15.62% < d2 < 18.75%, lhe can be either set or reset depending on th e dephasing between the signal on linflexd_rx pin the f ipg_clock_lin clock. note that the linflexd does not need to check if th e next edge occurs slower than expected. this is covered by the check for deviation error on the full synch byte. 27.8 test modes the linflexd controller includes two test modes, loop back mode and self test mode. they can be selected by the lbkm and sftm bits in the lincr1 register. these bits must be configured while linflexd is in initialization mode. after one of the two test modes has been se lected, linflexd must be started in normal mode. 27.8.1 loop back mode linflexd can be put in loop back mode by setting lincr1[lbkm]. in loop back mode, the linflexd treats its own transmitted messages as r eceived messages. this is illustrated in figure 27-12 . figure 27-12. linflexd in loop back mode this mode is provided for self-test functions. to be independe nt of external events , the lin core ignores the linrx signal. in this mode, the linflexd performs an internal fee dback from its tx output to its rx lintx linrx linflexd tx rx
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-17 preliminary?subject to change without notice input. the actual value of the linr x input pin is disregarded by the linflexd. the transmitted messages can be monitored on the lintx pin. 27.8.2 self test mode linflexd can be put in self te st mode by setting linc r1[lbkm] and lincr1[s ftm]. this mode can be used for a ?hot self test?, me aning the linflexd can be tested as in loop back mode but without affecting a running lin syst em connected to the lintx and linrx pins. in this mode, the linrx pin is disconnected from the li nflexd and the lintx pin is held recessive. th is is illustrated in figure 27-13 . figure 27-13. linflexd in self test mode 27.9 uart mode the main features of uart mode are presented in section 27.2.2, uart mode features . 27.9.1 data frame structure 27.9.1.1 8-bit data frame the 8-bit uart data frame is shown in figure 27-14 . the 8th bit can be a data or a parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr[pc] field. an even parity is set if the modulo-2 sum of the 7 data bits is 1. an odd parity is cleared in this case. figure 27-14. uart mode 8-bit data frame 27.9.1.2 9-bit data frame the 8-bit uart data frame is shown in figure 27-15 . the 9th bit is a parity bit. parity (even, odd, 0, or 1) can be selected by the by the uartcr[ pc] field. an even parity is set if the modulo-2 su m of the 7 data linflexd lintx linrx tx rx =1 start bit d0 d7 stop bit byte field - data bit - parity bit d1 d2 d3 d4 d5 d6
pxd20 microcontroller reference manual, rev. 1 27-18 freescale semiconductor preliminary?subject to change without notice bits is 1. an odd parity is cleared in this case. parity 0 forces a zero logical valu e. parity 1 forces a high logical value. figure 27-15. uart mode 9-bit data frame 27.9.1.3 16-bit data frame the 16-bit uart data frame is shown in figure 27-16 . the 16th bit can be a data or a parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr[pc] field. pa rity 0 forces a zero logical value. parity 1 forces a high logical value. figure 27-16. uart mode 16-bit data frame 27.9.1.4 17-bit data frame the 17-bit uart data frame is shown in figure 27-17 . the 17th bit is the parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr [pc] field. parity 0 forces a zero l ogical value. parity 1 forces a high logical value. figure 27-17. uart mode 17-bit data frame 27.9.2 buffer the 8-byte buffer is divided into two parts ? one fo r receiver and one for tran smitter ? as shown in table 27-5 . start bit d0 d7 stop bit byte field - parity bit d1 d2 d3 d4 d5 d6 d8 start bit d0 d15 stop bit byte field - data bit - parity bit d1 d2 ... ... d13 d14 start bit d0 d16 stop bit byte field - parity bit d1 d2 ... d13 d14 d15
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-19 preliminary?subject to change without notice for 16-bit frames, the lower 8 bits will be written in bdr0 and the upper 8 bits will be written in bdr1. 27.9.3 uart transmitter in order to start transmission in uart mode, th e uartcr[uart] and uartcr [txen] bits must be set. transmission starts when bdr0 (least significa nt data byte) is programmed. the number of bytes transmitted is equal to the value confi gured by the uartcr[tdfltfc] field (see table 27-18 ). the transmit buffer size is as follows: ? 4 bytes when uartcr[wl1] = 0 ? 2 half-words when uartcr[wl1] = 1 therefore, the maximum transmission that can be triggered is 4 bytes (2 half-words). after the programmed number of bytes has be en transmitted, the uartsr[dtftff] flag is set. if the uartcr[txen] field is cleared dur ing a transmission, the current tr ansmission is completed, but no further transmission can be invoked. the buffer can be configured in fifo mode (mandatory when dma tx is enabled) by setting uartcr[tfbm]. the access to the bdrl register is shown in table 27-6 . table 27-5. uart buffer structure bdr uart mode 0tx0 1tx1 2tx2 3tx3 4rx0 5rx1 6rx2 7rx3 table 27-6. bdrl access in uart mode access mode 1 word length 2 ips operation result write byte0 fifo byte ok write byte1-2-3 fifo byte ips transfer error write half-word0-1 fifo byte ips transfer error write word fifo byte ips transfer error write byte0-1-2-3 fifo half-word ips transfer error write half-word0 fifo half-word ok write half-word1 fifo half-word ips transfer error write word fifo half-word ips transfer error
pxd20 microcontroller reference manual, rev. 1 27-20 freescale semiconductor preliminary?subject to change without notice 27.9.4 uart receiver reception of a data byte is star ted as soon as the software comple tes the following tasks in order: 1. exits initialization mode 2. sets the uartcr[rxen] field 3. detects the start bit there is a dedicated data buffer for recei ved data bytes. its size is as follows: ? 4 bytes when uartcr[wl1] = 0 ? 2 half-words when uartcr[wl1] = 1 after the programmed number (rdfl bits) of bytes has been receive d, the uartsr[drfrfe] field is set. if the uartcr[rxen] field is cleared during a reception, the current recep tion is completed, but no further reception can be invoked unt il uartcr[rxen] is set again. the buffer can be configured in fifo mode (r equired when dma rx is enabled) by setting uartcr[rfbm]. the access to the bdrm register is shown in table 27-7 . read byte0-1-2-3 fifo byte/half-word ips transfer error read half-word0-1 fifo byte/half-word ips transfer error read word fifo byte/half-word ips transfer error write byte0-1-2-3 buffer byte/half-word ok write half-word0-1 buffer byte/half-word ok write word buffer byte/half-word ok read byte0-1-2-3 buffer byte/half-word ok read half-word0-1 buffer byte/half-word ok read word buffer byte/half-word ok notes: 1 as specified by uartcr[tfbm] 2 as specified by the wl1 and wl0 bi ts of the uartcr register. in uart fifo mode (uartcr[tfbm] = 1),any read operation causes an ips transfer error. table 27-7. bdrm access in uart mode access mode 1 word length 2 ips operation result read byte4 fifo byte ok read byte5-6-7 fifo byte ips transfer error read half-word2-3 fifo byte ips transfer error read word fifo byte ips transfer error table 27-6. bdrl access in uart mode (continued) access mode 1 word length 2 ips operation result
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-21 preliminary?subject to change without notice table 27-8 lists some common scenarios, controller re sponses, and suggestions when the linflexd controller is acting as a uart receiver. read byte4-5-6-7 fifo half-word ips transfer error read half-word2 fifo half-word ok read half-word3 fifo half-word ips transfer error read word fifo half-word ips transfer error write byte4-5-6-7 fifo byte/half-word ips transfer error write half-word2-3 fifo byte/half-word ips transfer error write word fifo byte/half-word ips transfer error read byte4-5-6-7 buffer byte/half-word ok read half-word2-3 buffer byte/half-word ok read word buffer byte/half-word ok write byte4-5-6-7 buffer byte/half-word ips transfer error write half-word2-3 buffer byte/half-word ips transfer error write word buffer byte/half-word ips transfer error notes: 1 as specified by uartcr[rfbm] 2 as specified by the wl1 and w l0 bits of the uartcr register table 27-8. uart receiver scenarios scenario responses and suggestions the software does not know (in advance) how many bytes will be received. do not program uartcr[rdflrfc] in advance. when this field is zero (as it is after reset), reception occurs on a byte-by-byte basis. therefore, the state machine will move to idle state after each byte is received. uartcr[rdflrfc] is programmed for a certain number of bytes received, but the actual number of bytes received is smaller. the reception will hang. in this case, the software must monitor the uartsr[to] field, and move to idle state by setting lincr1[sleep]. a stop request arrives before the reception is completed. the request is acknowledged only after the programmed number of data bytes are received. in other words, the stop request is not serviced immediately. in this case, the software must monitor the uartsr[to] field and move the state machine to idle state as appropriate. the stop request will be serviced only after this is complete. a parity error occurs during the reception of a byte. the corresponding uartsr[pe n ] field is set. no interrupt is generated. table 27-7. bdrm access in uart mode (continued) access mode 1 word length 2 ips operation result
pxd20 microcontroller reference manual, rev. 1 27-22 freescale semiconductor preliminary?subject to change without notice 27.10 memory map and register description table 27-9 shows the linflexd memory/regis ter map for the linflex_0 module. table 27-10 shows the linflexd memory/register map for linflex_1, linflex_2 and linflex_3 (t hese modules support master mode only and thus have no sl ave filter control regi sters). see the device me mory map for the base addresses. a framing error occurs during the reception of a byte. ? uartsr[fe] is set. ? if linier[feie] = 1, an interrupt is generated. this interrupt is helpful in identifying which byte has the framing error, since there is only one register bit for framing errors. a new byte has been received, but the last received frame has not been read from the buffer (uartsr[rmb] has not yet been cleared by the software) ? an overrun error will occur (uartsr[bof] will be set). ? one message will be lost (depending on the setting of lincr[rblm]). ? an interrupt is generated if linier[boie] is set. table 27-9. linflexd memory map (linflex_0 only) address offset register description location 0x00 lin control register 1 (lincr1) on page 24 0x04 lin interrupt enable register (linier) on page 27 0x08 lin status register (linsr) on page 29 0x0c lin error status register (linesr) on page 32 0x10 uart mode control register (uartcr) on page 33 0x14 uart mode status register (uartsr) on page 36 0x18 lin timeout control st atus register (lintcsr) on page 38 0x1c lin output compare register (linocr) on page 39 0x20 lin timeout control register (lintocr) on page 40 0x24 lin fractional baud rate register (linfbrr) on page 41 0x28 lin integer baud rate register (linibrr) on page 41 0x2c lin checksum field register (lincfr) on page 42 0x30 lin control register 2 (lincr2) on page 43 0x34 buffer identifier register (bidr) on page 44 0x38 buffer data register least significant (bdrl) on page 45 0x3c buffer data register most significant (bdrm) on page 46 0x40 identifier filter enable register (ifer) on page 47 0x44 identifier filter match index (ifmi) on page 47 0x48 identifier filter mode register (ifmr) on page 48 table 27-8. uart receiver scenarios (continued) scenario responses and suggestions
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-23 preliminary?subject to change without notice 0x4c?0x88 identifier filter control registers 0?15 (ifcr0?ifcr15) on page 49 0x8c global control register (gcr) on page 50 0x90 uart preset timeout register (uartpto) on page 51 0x94 uart current timeout register (uartcto) on page 52 0x98 dma tx enable register (dmatxe) on page 53 0x9c dma rx enable register (dmarxe) on page 53 table 27-10. linflexd memory map (linflex_1/linflex_2/linflex_3 only) address offset register description location 0x00 lin control register 1 (lincr1) on page 24 0x04 lin interrupt enable register (linier) on page 27 0x08 lin status register (linsr) on page 29 0x0c lin error status register (linesr) on page 32 0x10 uart mode control register (uartcr) on page 33 0x14 uart mode status register (uartsr) on page 36 0x18 lin timeout control st atus register (lintcsr) on page 38 0x1c lin output compare register (linocr) on page 39 0x20 lin timeout control register (lintocr) on page 40 0x24 lin fractional baud rate register (linfbrr) on page 41 0x28 lin integer baud rate register (linibrr) on page 41 0x2c lin checksum field register (lincfr) on page 42 0x30 lin control register 2 (lincr2) on page 43 0x34 buffer identifier register (bidr) on page 44 0x38 buffer data register least significant (bdrl) on page 45 0x3c buffer data register most significant (bdrm) on page 46 0x40 identifier filter enable register (ifer) on page 47 0x44 identifier filter match index (ifmi) on page 47 0x48 identifier filter mode register (ifmr) on page 48 0x4c global control register (gcr) on page 50 0x50 uart preset timeout register (uartpto) on page 51 0x54 uart current timeout register (uartcto) on page 52 0x58 dma tx enable register (dmatxe) on page 53 0x5c dma rx enable register (dmarxe) on page 53 table 27-9. linflexd memory map (linflex_0 only) (continued) address offset register description location
pxd20 microcontroller reference manual, rev. 1 27-24 freescale semiconductor preliminary?subject to change without notice 27.10.1 lin control register 1 (lincr1) offset:0x00 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd 1 cfd 1 lase 1 awum 1 mbl 1 bf 1 sft m 1 lbkm 1 mme 1 sbdt 1 rblm 1 sleep init w reset000000001000/1 2 0010 1 these fields are writable only in initialization mode (lincr1[init] = 1). 2 resets to 0 in slave mode and to 1 in master mode figure 27-18. lin control register 1 (lincr1) table 27-11. lincr1 field descriptions field description ccd checksum calculation disable this bit is used to disable the checksum calculation (see table 27-12 ). 0: checksum calculation is done by hardware. when th is bit is reset the lincfr register is read-only. 1: checksum calculation is disabled. when this bit is set the lincfr register is read/write. user can program this register to send a software calculated crc (provided cfd is reset). note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. cfd checksum field disable this bit is used to disable the checksum field transmission (see table 27-12 ). 0: checksum field is sent after the r equired number of data bytes is sent. 1: no checksum field is sent. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lase lin slave automatic resynchronization enable 0: automatic resynch ronization disable 1: automatic resynch ronization enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. awum automatic wake-up mode this bit controls the behavior of the linflexd hardware during sleep mode. 0: the sleep mode is exited on software request by clearing the sleep bit of the lincr register. 1: the sleep mode is exit ed automatically by ha rdware on rx dominant state detection. the sleep bit of the lincr register is cleared by hardware whenever wuf bit in linsr is set. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. mbl lin master break length these bits indicate the break length in master mode (see ta b l e 2 7 - 1 3 ). note: these bits can be written in initialization mode only. they are read-only in normal or sleep mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-25 preliminary?subject to change without notice bf bypass filter 0: no interrupt if id does not match any filter 1: an rx interrupt is generat ed on id not matching any filter notes: ? if no filter is activated, this bit is reserved. ? this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sftm self test mode this bit controls the self test mode. for more details please refer to section 27.8.2, self test mode . 0: self test mode disable 1: self test mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lbkm loop back mode this bit controls the loop back mode. for more details please refer to section 27.8.1, loop back mode . 0: loop back mode disable 1: loop back mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode mme master mode enable 0: slave mode enable 1: master mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sbdt slave mode break detection threshold 0: 11-bit break 1: 10-bit break note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. rblm receive buffer locked mode 0: receive buffer not locked on overrun. once the slave receive buffer is full the next incoming message overwrites the previous one. 1: receive buffer locked against overrun. once t he receive buffer is full the next incoming message is discarded. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sleep sleep mode request this bit is set by software to request linflexd to enter sleep mode. this bit is cleared by software to exit sleep mode or by hardware if the awum bit in lincr1 and the wuf bit in linsr are set (see table 27-14 ). init initialization request the software sets this bit to switch hardware in to initialization mode. if the sleep bit is reset, linflexd enters normal mode when clearing the init bit (see table 27-14 ). table 27-12. checksum bits configuration cfd ccd lincfr checksum sent 1 1 read/write none 1 0 read-only none 0 1 read/write programmed in lincfr by bits cf[0:7] table 27-11. lincr1 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 27-26 freescale semiconductor preliminary?subject to change without notice 0 0 read-only hardware calculated table 27-13. lin master break length selection mbl length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit table 27-14. operating mode selection sleep init operating mode 1 0 sleep (reset value) x 1 initialization 00normal table 27-12. checksum bits configuration cfd ccd lincfr checksum sent
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-27 preliminary?subject to change without notice 27.10.2 lin interrupt en able register (linier) offset: 0x04 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szie ocie beie ceie heie 0 0 feie boie lsie wui e dbfie dbeietoie drie dtie hrie w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 27-19. lin interrupt enable register (linier) table 27-15. linier field descriptions field description szie stuck at zero interrupt enable 0: no interrupt when szf bit in linesr or uartsr is set 1: interrupt generated when szf bit in linesr or uartsr is set ocie output compare interrupt enable 0: no interrupt when ocf bit in linesr or uartsr is set 1: interrupt generated when ocf bit in linesr or uartsr is set beie bit error interrupt enable 0: no interrupt when bef bit in linesr is set 1: interrupt generated when bef bit in linesr is set ceie checksum error interrupt enable 0: no interrupt on checksum error 1: interrupt generated when checksum error flag (cef) is set in linesr heie header error interrupt enable 0: no interrupt on break delimiter error, synch field error, id field error 1: interrupt generated on break delimiter error, synch field error, id field error feie framing error interrupt enable 0: no interrupt on framing error 1: interrupt generated on framing error boie buffer overrun interrupt enable 0: no interrupt on buffer overrun 1: interrupt generated on buffer overrun
pxd20 microcontroller reference manual, rev. 1 27-28 freescale semiconductor preliminary?subject to change without notice 27.10.3 lin status register (linsr) lsie lin state interrupt enable 0: no interrupt on lin state change 1: interrupt generated on lin state change this interrupt can be used for debugging purposes. it has no status flag but is reset when writing ?1111? into the lin state bits in the linsr register. wuie wake-up interrupt enable 0: no interrupt when wuf bit in linsr or uartsr is set 1: interrupt generated when wuf bit in linsr or uartsr is set dbfie data buffer full interrupt enable 0: no interrupt when buffer data register is full 1: interrupt generated when data buffer register is full dbeietoie data buffer empty interrupt enable / timeout interrupt enable 0: no interrupt when buffer data register is empty 1: interrupt generated when data buffer register is empty note: an interrupt is generated if this bit is set and one of the following is true: linflexd is in lin mode and linsr[dbef] is set linflexd is in uart mode and uartsr[to] is set drie data reception complete interrupt enable 0: no interrupt when data reception is completed 1: interrupt generated when data received flag (drf) in linsr or uartsr is set dtie data transmitted interrupt enable 0: no interrupt when data transmission is completed 1: interrupt generated when data transmitted flag (dtf) is set in linsr or uartsr register hrie header received interrupt enable 0: no interrupt when a valid lin header has been received 1: interrupt generated when a valid lin header has b een received, that is, hrf bit in linsr register is set offset: 0x08 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lins 00rmb0 rbsy rps wuf dbf f dbef drf dtf hrf ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000001000000 figure 27-20. lin status register (linsr) table 27-15. linier field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-29 preliminary?subject to change without notice table 27-16. linsr field descriptions field description lins lin state lin mode states description 0000: sleep mode linflexd is in sleep mode to save power consumption. 0001: initialization mode linflexd is in initialization mode. 0010: idle this state is entered on several events: ? sleep bit and init in lincr1 register have been cleared by software, ? a falling edge has been received on rx pin and awum bit is set, ? the previous frame reception or transmission has been completed or aborted. 0011: break in slave mode, a falling edge followed by a dom inant state has been detec ted. receiving break. note: in slave mode, in case of error new lin state can be either idle or break depending on last bit state. if last bit is dominant new lin state is break, otherwise idle. in master mode, break transmission ongoing. 0100: break delimiter in slave mode, a valid break has been detected. refer to lincr1 register for break length configuration (10-bit or 11-bit). waiting for a rising edge. in master mode, break transmission has been comp leted. break delimiter transmission is ongoing. 0101: synch field in slave mode, a valid break delimiter has been detec ted (recessive state for at least one bit time). receiving synch field. in master mode, synch field transmission is ongoing. 0110: identifier field in slave mode, a valid synch field has been received. receiving id field. in master mode, identifier transmission is ongoing. 0111: header reception/t ransmission completed in slave mode, a valid header has been received and id entifier field is available in the bidr register. in master mode, header transmission is completed. 1000: data reception/transmission response reception/transmission is ongoing. 1001: checksum data reception/transmission completed. checksum reception/transmission ongoing. in uart mode, only the following states are flagged by the lin state bits: ?init ?sleep ?idle ? data transmission/reception rmb release message buffer 0: buffer is free 1: buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. rbsy receiver busy flag 0: receiver is idle 1: reception ongoing note: in slave mode, after header reception, if dir bi t in bidr is reset and reception starts then this bit is set. in this case, user cannot set dtrq bit in lincr2. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes.
pxd20 microcontroller reference manual, rev. 1 27-30 freescale semiconductor preliminary?subject to change without notice wuf wake-up flag this bit is set by hardware and indicates to the software that linflexd has detected a falling edge on the linrx pin when ? slave is in sleep mode, ? master is in sleep mode or idle state. this bit must be cleared by software. it is reset by hardware in initializati on mode. an interrupt is generated if wuie bit in linier is set. dbff data buffer full flag this bit is set by hardware and indicates the buffer is full. it is set only when receiving extended frames (dfl > 7). this bit must be cleared by software. it is reset by hardware in initialization mode. dbef data buffer empty flag this bit is set by hardware and indicates the buffer is empty. it is set only when transmitting extended frames (dfl > 7). this bit must be cleared by software, once buffer has been filled again, in order to start transmission. this bit is reset by hardware in initialization mode. drf data reception completed flag this bit is set by hardware and indicates the data reception is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in ca se of bit error or framing error. dtf data transmission completed flag this bit is set by hardware and indicates the data transmission is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error if iobe bit is reset. hrf header reception flag this bit is set by hardware and indicates a valid header reception is completed. this bit must be cleared by software. this bit is reset by hardware in initialization mode and at end of completed or aborted frame. note: if filters are enabled, this bit is set only when identifier software filtering is required, that is to say: ? all filters are inactive and bf bit in lincr1 is set ? no match in any filter and bf bit in lincr1 is set ? tx filter match table 27-16. linsr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-31 preliminary?subject to change without notice 27.10.4 lin error status register (linesr) offset: 0x0c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf bef cef sfe f bdef idpef fef bof 0 0 0 000nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 27-21. lin error status register (linesr) table 27-17. linesr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf output compare flag 0: no output compare event occurred 1: the content of the count er has matched the content of oc1[0:7] or oc2[0:7] in linocr. if this bit is set and iot bit in lintcsr is se t, linflexd moves to idle state. if ltom bit in lintcsr register is set then ocf is reset by hardware in initialization mode. if ltom bit is reset, then ocf maintains its status whatever the mode is. bef bit error flag this bit is set by hardware and indicates to the soft ware that linflexd has detected a bit error. this error can occur during response field transmission (slave and master modes) or during header transmission (in master mode). this bit is cleared by software. cef checksum error flag this bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. this bit is cleared by software. note: this bit is never set if ccd or cfd bit in lincr1 register is set. sfef synch field error flag this bit is set by hardware and indicates that a synch field error occurred (inconsistent synch field). bdef break delimiter error flag this bit is set by hardware and indicates that the re ceived break delimiter is too short (less than one bit time).
pxd20 microcontroller reference manual, rev. 1 27-32 freescale semiconductor preliminary?subject to change without notice 27.10.5 uart mode cont rol register (uartcr) idpef identifier parity error flag this bit is set by hardware and indicates that a identifier parity error occurred. note: header interrupt is triggered when sfef or bdef or idpef bit is set and heie bit in linier is set. fef framing error flag this bit is set by hardware and indicates to the so ftware that linflexd has detected a framing error (invalid stop bit). this error can occur during reception of any data in the response field (master or slave mode) or during reception of synch field or identifier field in slave mode. bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte received is discarded. if rblm is reset then the new byte overwrites the buffer. it can be cleared by software. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. offset: 0x10 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tdfltfc 1 rdflrfc 1 rfbm tfbm 2 wl[1] 2 pc1 2 rxen txen pc0 2 pce 2 wl[0] 2 uart 2 w reset0000000000000000 1 these fields are read/write in uart buffer mode and read-only in other modes. 2 these fields are writable only in initialization mode (l incr1[init] = 1). figure 27-22. uart mode control register (uartcr) table 27-17. linesr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-33 preliminary?subject to change without notice table 27-18. uartcr field descriptions field description tdfltfc transmitter data field length / tx fifo counter this field has one of two functions depending on the mode of operation as follows: ? when linflexd is in uart buffer mode (tfb m = 0), tdfltfc defines the number of bytes to be transmitted. the field is read/write in this c onfiguration. the first bit is reserved and not implemented. the permissible values are as follows (with x representing the unimplemented first bit): 0bx00: 1 byte 0bx01: 2 bytes 0bx10: 3 bytes 0bx11: 4 bytes when the uart data length is configured as half -word (wl = 0b10 or 0b11), the only valid values for tdfltfc are 0b001 and 0b011. ? when linflexd is in uart fifo mode (tfb m = 1), tdfltfc contains the number of entries (bytes) of the tx fifo. the field is read-only in this configuration. the permissible values are as follows: 0b000: empty 0b001: 1 byte 0b010: 2 bytes 0b011: 3 bytes 0b100: 4 bytes all other values are reserved. this field is meaningful and can be programmed only when the uart bit is set. rdflrfc receiver data field length / rx fifo counter this field has one of two functions depending on the mode of operation as follows: ? when linflexd is in uart buffer mode (rfb m = 0), rdflrfc defines the number of bytes to be received. the field is read/write in this configurat ion. the first bit is reserved and not implemented. the permissible values are as follows (with x representing the unimplemented first bit): 0bx00: 1 byte 0bx01: 2 bytes 0bx10: 3 bytes 0bx11: 4 bytes when the uart data length is configured as half -word (wl = 0b10 or 0b11), the only valid values for rdflrfc are 0b001 and 0b011. ? when linflexd is in uart fifo mode (rfb m = 1), rdflrfc contains the number of entries (bytes) of the rx fifo. the field is read-only in this configuration. the permissible values are as follows: 0b000: empty 0b001: 1 byte 0b010: 2 bytes 0b011: 3 bytes 0b100: 4 bytes all other values are reserved. this field is meaningful and can be programmed only when the uart bit is set. rfbm rx fifo/buffer mode 0 rx buffer mode enabled 1 rx fifo mode enabled (mandatory in dma rx mode) this field can be programmed in initialization mode only when the uart bit is set.
pxd20 microcontroller reference manual, rev. 1 27-34 freescale semiconductor preliminary?subject to change without notice tfbm tx fifo/buffer mode 0 tx buffer mode enabled 1 tx fifo mode enabled (mandatory in dma tx mode) this field can be programmed in initialization mode only when the uart bit is set. rxen receiver enable 0: receiver disabled 1: receiver enabled this field can be programmed only when the uart bit is set. txen transmitter enable 0: transmitter disabled 1: transmitter enabled this field can be programmed only when the uart bit is set. note: transmission starts when this bit is set and when writing data0 in the bdrl register. pc parity control 00 parity sent is even 01 parity sent is odd 10 a logical 0 is always transmitted/checked as parity bit 11 a logical 1 is always transmitted/checked as parity bit this field can be programmed in initialization mode only when the uart bit is set. pce parity control enable 0: parity transmit/check disabled 1: parity transmit/check enabled this field can be programmed in initialization mode only when the uart bit is set. wl word length in uart mode 00 7 bits data + parity 01 8 bits data when pce = 0 or 8 bits data + parity when pce = 1 10 15 bits data + parity 11 16 bits data when pce = 0 or 16 bits data + parity when pce = 1 this field can be programmed in initialization mode only when the uart bit is set. uart uart mode enable 0: lin mode 1: uart mode this field can be programmed in initialization mode only. table 27-18. uartcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-35 preliminary?subject to change without notice 27.10.6 uart mode status register (uartsr) offset: 0x14 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf pe3 pe2 pe1 pe0 rmb fef bof rps wuf 0 to drfrfe dtftff nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 27-23. uart mode status register (uartsr) table 27-19. uartsr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf ocf output compare flag 0: no output compare event occurred 1: the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. an interrupt is generated if the ocie bit in linier register is set. pe3 parity error flag rx3 this bit indicates if there is a parity error in the corresponding received byte (rx3). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe2 parity error flag rx2 this bit indicates if there is a parity error in the corresponding received byte (rx2). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe1 parity error flag rx1 this bit indicates if there is a parity error in the corresponding received byte (rx1). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe0 parity error flag rx0 this bit indicates if there is a parity error in the corresponding received byte (rx0). no interrupt is generated if this error occurs. 0: no parity error 1: parity error
pxd20 microcontroller reference manual, rev. 1 27-36 freescale semiconductor preliminary?subject to change without notice rmb release message buffer 0: buffer is free 1: buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. fef framing error flag this bit is set by hardware and indicates to the so ftware that linflexd has detected a framing error (invalid stop bit). bof fifo/buffer overrun flag this bit is set by hardware when a new data byte is received and the rmb bit is not cleared in uart buffer mode. in uart fifo mode, this bit is set when there is a new byte and the rx fifo is full. in uart fifo mode, once rx fifo is full, the new received message is discarded regardless of the value of lincr1[rblm]. if lincr1[rblm] = 1, the new byte received is discarded. if lincr1[rblm] = 0, the new byte overwrites buffer. this field can be cleared by writing a 1 to it. an interrupt is generated if linier[boie] is set. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to the software that linflexd has detected a falling edge on the linrx pin in sleep mode. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt i generated if wuie bit in linier is set. to timeout the linflexd controller sets this field when a ua rt timeout occurs ? that is, when the value of uartcto becomes equal to the preset value of the timeout (uartpto register setting). this field should be cleared by software. the gcr[sr] field should be used to reset the receiver fsm to idle state in case of uart timeout for uart recept ion depending on the application both in buffer and fifo mode. an interrupt is generated when li nier[dbeietoie] is set on the error interrupt line in uart mode. drfrfe data reception complete d flag / rx fifo empty flag the linflexd controller sets this field as follows: ? in uart buffer mode (rfbm = 0), it indicates th at the num ber of bytes programmed in rdfl has been received. this field should be cleared by soft ware. an interrupt is generated if linier[drie] is set. this field is set in case of framing error, pa rity error, or overrun. th is field reflects the same value as in linesr when in initialization mode and uart bit is set. ? in uart fifo mode (rfbm = 1), it indicates that the rx fifo is empty. this field is a read-only field used internally by the dma rx interface. dtftff data transmission completed flag / tx fifo full flag the linflexd controller sets this field as follows: ? in uart buffer mode (tfbm = 0), it indicates that the data transmission is completed. this field should be cleared by software. an interrupt is gener ated if linier[dtie] is set. this field reflects the same value as in linesr when in initialization mode and uart bit is set. ? in uart fifo mode (tfbm = 1), it indicates that th e tx fifo is full. this field is a read-only field used internally by the dma tx interface. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. table 27-19. uartsr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-37 preliminary?subject to change without notice 27.10.7 lin timeout control status register (lintcsr) offset: 0x18 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0 lto o m iot toce cnt[0:7] w reset0000000000100000 1 these fields are writable only in initialization mode (l incr1[init] = 1). figure 27-24. lin timeout control status register (lintcsr) table 27-20. lintcsr field descriptions name description ltom lin timeout mode 0: lin timeout mode (header, re sponse and frame timeout detection) 1: output compare mode this bit can be set/cleared in initialization mode only. iot idle on timeout 0: lin state machine not reset to idle on timeout event 1: lin state machine reset to idle on timeout event this bit can be set/cleared in initialization mode only. toce timeout counter enable 0: timeout counter disable. ocf bit in linesr or uartsr is not set on an output compare event. 1: timeout counter enable. ocf bit is set if an output compare event occurs. toce bit is configurable by software in initialization mode. if lin state is not init and if timer is in lin timeout mode, then hardware takes control of toce bit. cnt counter value these bits indicate the lin timeout counter value.
pxd20 microcontroller reference manual, rev. 1 27-38 freescale semiconductor preliminary?subject to change without notice 27.10.8 lin output comp are register (linocr) offset: 0x1c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 roc2 1 oc1 1 ww1c 1 w1c 1 reset1111111111111111 1 if lintcsr[ltom] = 1, these fields are read-only. figure 27-25. lin output compare register (linocr) table 27-21. linocr field descriptions field description oc2 output compare 2 value these bits contain the value to be co mpared to the val ue of lintcsr[cnt]. oc1 output compare 1 value these bits contain the value to be co mpared to the val ue of lintcsr[cnt].
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-39 preliminary?subject to change without notice 27.10.9 lin timeout cont rol register (lintocr) offset: 0x20 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 rto 0 hto 3 w reset00001110000/1 1 0/1 2 1100 1 resets to 1 in slave mode and to 0 in master mode 2 resets to 0 in slave mode and to 1 in master mode 3 hto field can only be written in slave mode, lincr1[mme] = 0. figure 27-26. lin timeout control register (lintocr) table 27-22. lintocr field descriptions field description rto response timeout value this register contains the response ti meout duration (in bit time) for 1 byte. the reset value is 0xe = 14, corresponding to t response_maximum =1.4xt response_nominal hto header timeout value this register contains the header timeout duration (i n bit time). this value does not include the first 11 dominant bits of the break. the reset val ue depends on which mode linflexd is in. hto can be written only for slave mode.
pxd20 microcontroller reference manual, rev. 1 27-40 freescale semiconductor preliminary?subject to change without notice 27.10.10 lin fractional baud rate register (linfbrr) 27.10.11 lin integer baud rate register (linibrr) offset: 0x24 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_f 1 w reset0000000000000000 1 this field is writable only in in itialization mode, lincr1[init] = 1. figure 27-27. lin timeout control register (lintocr) table 27-23. linfbrr field descriptions field description div_f fraction bits of lfdiv the 4 fraction bits define the value of the fraction of the linflexd divider (lfdiv). fraction (lfdiv) = decimal value of div_f / 16. this register can be written in in itialization mode only, lincr1[init] = 1. offset: 0x28 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_m 1 w reset00000000000000000000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 27-28. lin integer ba ud rate register (linibrr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-41 preliminary?subject to change without notice 27.10.12 lin checksum field register (lincfr) table 27-24. linibrr field descriptions field description div_m lfdiv mantissa these bits define the linflexd di vider (lfdiv) mantissa value (see table 27-25 ). this register can be written in initialization mode only. table 27-25. integer baud rate selection div_m mantissa 0x0 lin clock disabled 0x1 1 ... ... 0xffffe 1048574 0xfffff 1048575 offset: 0x2c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 cf w reset0000000000000000 figure 27-29. lin checksum field register (lincfr) table 27-26. lincfr field descriptions field description cf checksum bits when lincr1[ccd] is cleared, these bits are read-only. when lincr1 [ccd] is set, these bits are read/write. see table 27-12 .
pxd20 microcontroller reference manual, rev. 1 27-42 freescale semiconductor preliminary?subject to change without notice 27.10.13 lin control register 2 (lincr2) offset: 0x30 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 iobe 1 iope 1 wur q ddr q dtr q abr q htr q 0 0 0 0 0 0 0 0 w w1c w1c w1c w1c w1c reset 0 1 0/1 2 0000000000000 1 these fields are writable only in initialization mode (lincr1[init] = 1. 2 resets to 1 in slave mode and to 0 in master mode figure 27-30. lin control register 2 (lincr2) table 27-27. lincr2 field descriptions field description iobe idle on bit error 0: bit error does not reset lin state machine 1: bit error reset lin state machine this bit can be set/cleared in init ialization mode only (lincr1[init]) = 1. iope idle on identifier parity error 0: identifier parity error does not reset lin state machine. 1: identifier parity erro r reset lin state machine. this bit can be set/cleared in init ialization mode only (lincr1[init]) = 1. wurq wake-up generation request setting this bit generates a wake-up pulse. it is reset by hardware when the wake-up character has been transmitted. the character sent is copied from data0 in bdrl buffer. note that this bit cannot be set in sleep mode. software has to exit sleep mode before requesting a wake-up. bit error is not checked when transmitting the wake-up request. ddrq data discard request set by software to stop data reception if the fram e does not concern the node. this bit is reset by hardware once linflexd has moved to idle state. in slave mode, this bit can be set only when hrf bit in linsr is set and identi fier did not match any filter. dtrq data transmission request set by software in slave mode to request the transmission of the lin data field stored in the buffer data register. this bit can be set only when hrf bit in linsr is set. cleared by hardware when the request has been completed or aborted or on an error condition. in master mode, this bit is set by hardware when dir bit in bidr is set and header transmission is completed.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-43 preliminary?subject to change without notice 27.10.14 buffer identifier register (bidr) this register contains the fields that identify a transaction and provi de other information related to it. all the fields in this regi ster must be updated when an id filter (enabled) in sl ave mode (tx or rx) matches the id received. abrq abort request set by software to abort the current transmission. cleared by hardware when the transmission has been a borted. linflexd aborts the transmission at the end of the current bit. this bit can also abort a wake-up request. it can also be used in uart mode. htrq header transmission request set by software to request the transmission of the lin header. cleared by hardware when the request has been completed or aborted. this bit has no effect in uart mode. offset: 0x34 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000000000000000 figure 27-31. buffer identifier register (bidr) table 27-28. bidr field descriptions field description dfl data field length these bits define the number of data byte s in the response part of the frame. dfl = number of data bytes - 1. normally, lin uses only dfl[0:2] to manage frames wit h a maximum of 8 bytes of data. identifier filters are compatible with dfl[0:2] and dfl[0:5] . df l[3:5] are provided to manage extended frames. dir direction this bit controls the dire ction of the data field. 0: linflexd receives the data and copy them in the bdr registers. 1: linflexd transmits the data from the bdr registers. table 27-27. lincr2 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 27-44 freescale semiconductor preliminary?subject to change without notice 27.10.15 buffer data regist er least significant (bdrl) ccs classic checksum this bit controls the type of checksum applied on the current message. 0: enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1: classic checksum covering data fields only. this is compatible with lin sp ecification 1.3 and below. id identifier identifier part of the identifier field without the identifier parity. offset: 0x38 access: user read/write 0123456789101112131415 r data3 data2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data1 data0 w reset0000000000000000 figure 27-32. buffer data register least significant (bdrl) table 27-29. bdrl field descriptions field description data3 data byte 3 data byte 3 of the data field data2 data byte 2 data byte 2 of the data field data1 data byte 1 data byte 1 of the data field data0 data byte 0 data byte 0 of the data field table 27-28. bidr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-45 preliminary?subject to change without notice 27.10.16 buffer data regist er most significant (bdrm) offset: 0x3c access: user read/write 0123456789101112131415 r data7 data6 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data5 data4 w reset0000000000000000 figure 27-33. buffer data regi ster most significant (bdrm) table 27-30. bdrm field descriptions field description data7 data byte 7 data byte 7 of the data field data6 data byte 6 data byte 6 of the data field data5 data byte 5 data byte 5 of the data field data4 data byte 4 data byte 4 of the data field
pxd20 microcontroller reference manual, rev. 1 27-46 freescale semiconductor preliminary?subject to change without notice 27.10.17 identifier filter enable register (ifer) 27.10.18 identifier filter match index (ifmi) offset: 0x40 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 fact 1 w reset0000000000000000 1 this field is writable only in init ialization mode (lincr1[init] = 1). figure 27-34. identifier filter enable register (ifer) table 27-31. ifer field descriptions field description fact filter active the software sets the bit fact[x] to activa te the filter x in identifier list mode. in identifier mask mode bits fact(2n + 1) have no ef fect on the corresponding filters as they act as masks for the identifiers 2n. these bits can be set/cleared in initialization mode only. offset: 0x44 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 0000 0000 ifmi w reset0000000000000000 figure 27-35. identifier filter match index (ifmi)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-47 preliminary?subject to change without notice 27.10.19 identifier filter mode register (ifmr) table 27-32. ifmi field descriptions field description ifmi filter match index this register contains the index corresponding to the re ceived id. it can be used to directly write or read the data in ram (refer to section 27.7.2, slave mode, for more details). when no filter matches, ifmi = 0. when filter n is matching, ifmi = n + 1. offset:0x48 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000 0 ifm w reset0000000000000000 figure 27-36. identifier filter mode register (ifmr) table 27-33. ifmr field descriptions field description ifm filter mode 0 filters 2 n and 2 n + 1 are in identifier list mode. 1 filters 2 n and 2 n + 1 are in mask mode (filter 2 n + 1 is the mask for the filter 2 n ). (see table 27-34 .) table 27-34. ifmr[ifm] configuration bit value result ifm[0] 0 filters 0 and 1 are in identifier list mode. 1 filters 0 and 1 are in mask mode (filt er 1 is the mask for the filter 0). ifm[1] 0 filters 2 and 3 are in identifier list mode. 1 filters 2 and 3 are in mask mode (filt er 3 is the mask for the filter 2). ifm[2] 0 filters 4 and 5 are in identifier list mode. 1 filters 4 and 5 are in mask mode (filt er 5 is the mask for the filter 4).
pxd20 microcontroller reference manual, rev. 1 27-48 freescale semiconductor preliminary?subject to change without notice 27.10.20 identifier filter control registers (ifcr0?ifcr15) the function of these registers is different depending on which mode the linflexd controller is in, as described in table 27-35 . ifm[3] 0 filters 6 and 7 are in identifier list mode. 1 filters 6 and 7 are in mask mode (filt er 7 is the mask for the filter 6). ifm[4] 0 filters 8 and 9 are in identifier list mode. 1 filters 8 and 9 are in mask mode (filt er 9 is the mask for the filter 8). ifm[5] 0 filters 10 and 11 are in identifier list mode. 1 filters 10 and 11 are in mask mode (filter 11 is the mask for the filter 10). ifm[6] 0 filters 12 and 13 are in identifier list mode. 1 filters 12 and 13 are in mask mode (filter 13 is the mask for the filter 12). ifm[7] 0 filters 14 and 15 are in identifier list mode. 1 filters 14 and 15 are in mask mode (filter 15 is the mask for the filter 14). table 27-35. ifcr functionality based on mode mode ifcr functionality identifier list each ifcr regi ster acts as a filter. identifier mask if a = (number of f ilters) / 2, and n = 0 to (a - 1), then ifcr[2n] acts as a filter and if cr[2n+1] acts as the mask for ifcr[2n]. offsets: 0x4c?0x88 (16 regist ers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl 1 dir 1 ccs 1 00 id 1 w reset0000000000000000 1 these fields are writable only in initialization mode (lincr1[init] = 1). figure 27-37. identifier filter control registers (ifcr0?ifcr15) table 27-34. ifmr[ifm] configuration (continued) bit value result
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-49 preliminary?subject to change without notice 27.10.21 global control register (gcr) this register can be programmed only in initialization mode. the configuration specified in this register applies in both lin and uart modes. table 27-36. ifcr field descriptions field description dfl data field length this field defines the number of data bytes in the response part of the frame. dir direction this bit controls the direction of the data field. 0: linflexd receives the data and copy them in the bdrl and bdrm registers. 1: linflexd transmits the data fr om the bdrl and bdrm registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0: enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1: classic checksum covering data fields only. this is compatible with lin sp ecification 1.3 and below. id identifier identifier part of the identifier field without the identifier parity. offset: 0x8c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000 000 tdfbm 1 rdfbm 1 tdlis 1 rdlis 1 stop 1 0 w sr 1 reset0000000000000000 1 this field is writable only in init ialization mode (lincr1[init] = 1). figure 27-38. global control register (gcr)
pxd20 microcontroller reference manual, rev. 1 27-50 freescale semiconductor preliminary?subject to change without notice 27.10.22 uart preset timeout register (uartpto) this register contains the preset timeout value in uart mode, and is used to monitor the idle state of the reception line. the timeout detection uses this register and the uartcto register described in section 27.10.23, uart current timeout register (uartcto) . table 27-37. gcr field descriptions field description tdfbm transmit data first bit msb this field controls the first bit of transmitted da ta (payload only) as msb/lsb in both uart and lin modes. 0 the first bit of transmitted data is lsb ? that is , the first bit transmitted is mapped on the lsb bit (bdr(0), bdr(8), bdr(16), bdr(24)). 1 the first bit of transmitted data is msb ? that is, the first bit transmitted is mapped on the msb bit (bdr(7), bdr(15), bdr(23), bdr(31)). rdfbm received data first bit msb this field controls the first bit of received data (payload only) as msb/lsb in both uart and lin modes. 0 the first bit of received data is lsb ? that is, t he first bit received is mapped on the lsb bit (bdr(0), bdr(8), bdr(16), bdr(24)). 1 the first bit of received data is msb ? that is, the first bit received is mapped on the msb bit (bdr(7), bdr(15), bdr(23), bdr(31)). tdlis transmit data level inversion selection this field controls the data inversion of transmitt ed data (payload only) in both uart and lin modes. 0 transmitted data is not inverted. 1 transmitted data is inverted. rdlis received data level inversion selection this field controls the data inversion of receiv ed data (payload only) in both uart and lin modes. 0 received data is not inverted. 1 received data is inverted. stop stop bit configuration this field controls the number of stop bits in tr ansmitted data in both uart and lin modes. the stop bit is configured for all the fields (delimiter, sync, id, checksum, and payload). 0 one stop bit 1 two stop bits sr soft reset if the software writes a ?1? to this field, the linfle xd controller executes a soft reset in which the fsms, fifo pointers, counters, timers, status registers, and error registers are reset but the configuration registers are unaffected. the resetting of this bit should also be done by software only (its not cleared by hardware automatically). this field always reads ?0?.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-51 preliminary?subject to change without notice 27.10.23 uart current timeout register (uartcto) this register contains the current timeout value in uart mode, and is used in conjunction with the uartpto register (see section 27.10.22, uart preset t imeout register (uartpto) ) to monitor the idle state of the reception line. uart ti meout works in both cpu and dma modes. the timeout counter: ? starts at zero and counts upward ? is clocked with the baud rate clock presca led by a hard-wired sc aling factor of 16 ? is automatically enabled when uartcr[rxen] = 1 offset: 0x90 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0 pto w reset0000111111111111 figure 27-39. uart preset timeout register (uartpto) table 27-38. uartpto field descriptions field description pto preset value of the timeout counter do not set pto = 0 (otherwise, uartsr[to] would immediately be set). offset: 0x94 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0cto w reset0000000000000000 figure 27-40. uart current timeout register (uartcto)
pxd20 microcontroller reference manual, rev. 1 27-52 freescale semiconductor preliminary?subject to change without notice 27.10.24 dma tx enable register (dmatxe) this register enables the dma tx interface. 27.10.25 dma rx enable register (dmarxe) this register enables the dma rx interface. table 27-39. uartcto field descriptions field description cto current value of the timeout counter this field is reset whenever one of the following occurs: ? a new value is written to the uartpto register ? the value of this field matches the value of uartpto[pto] ? a hard or soft reset occurs ? new incoming data is received when cto matches the value of uartpto[pto], uartsr[to] is set. offset: 0x98 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dte 15 dte 14 dte 13 dte 12 dte 11 dte 10 dte 9 dte 8 dte 7 dte6 dte 5 dte 4 dte 3 dte 2 dte 1 dte 0 w reset0000000000000000 figure 27-41. dma tx enable register (dmatxe) table 27-40. dmatxe field descriptions field description dte n dma tx channel n enable 0 dma tx channel n disabled 1 dma tx channel n enabled note: when dmatxe = 0x0, the dma tx interface fsm is forced (soft reset) into the idle state.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-53 preliminary?subject to change without notice 27.11 dma interface the linflexd dma interface offers a parametric and programmable solu tion with the following features: ? lin master node, tx mode: single dma channel ? lin master node, rx mode: single dma channel ? lin slave node, tx mode: 1 to n dma cha nnels where n = max num ber of id filters ? lin slave node, rx mode: 1 to n dma cha nnels where n = max number of id filters ? uart node, tx mode: single dma channel ? uart node, rx mode: single dma channel + timeout the linflexd controller interacts with an enhanced direct memory access (e dma) controller; see the description of that controller fo r details on its operati on and the transfer cont rol descriptors (tcds) referenced in this section. 27.11.1 master node, tx mode on a master node in tx mode, the dma interface re quires a single tx channel. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 27-43 . offset: 0x9c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dre15 dre14 dre13 dre12 dre11 dre10 dre9 dre8 dre7 dre6 dre5 dre4 dre3 dre2 dre1 dre0 w reset0000000000000000 figure 27-42. dma rx enable register (dmarxe) table 27-41. dmarxe field descriptions field description dre n dma rx channel n enable 0 dma rx channel n disabled 1 dma rx channel n enabled note: when dmarxe = 0x0, the dma rx interface fsm is forced (soft reset) into the idle state.
pxd20 microcontroller reference manual, rev. 1 27-54 freescale semiconductor preliminary?subject to change without notice figure 27-43. tcd chain memory map (master node, tx mode) the tcd chain of the dma tx channel on a master node supports: ? master to slave: transmission of the entire frame (header + data) ? slave to master: transmission of the header. the data reception is controlled by the rx channel on the master node. ? slave to slave: tran smission of the header. the register settings for the lincr2 and bidr re gisters for each class of lin frame are shown in table 27-42 .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-55 preliminary?subject to change without notice the concept fsm to control the dma tx interface is shown in figure 27-44 . the dma tx fsm will move to idle state immediately at next clock edge if dmatxe[0] = 0. table 27-42. register settings (master node, tx mode) lin frame lincr2 bidr master to slave ddrq=1 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 1 (tx) slave to master ddrq=0 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 0 (rx) slave to slave ddrq=1 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 0 (rx)
pxd20 microcontroller reference manual, rev. 1 27-56 freescale semiconductor preliminary?subject to change without notice figure 27-44. fsm to control the dma tx interface (master node) the tcd settings (word transfer) are shown in table 27-43 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfers are allowed. !dtf & !drf & (lin idle | dbef) & dma_ten & !token_dma_rx ? dma tx transfer (req/ack minor/major loop) from ram area to linflex regs set htrq to transmit the lin frame (header + [data] ) false true dma tx transfer is completed ? true !dir & !ddrq set token_dma_rx to enable the dma rx interface true (rx mode) dtf ? false true (end of frame) false true (extended frame, size > 8 bytes) dbef ? false clear dtf dbef ? clear dbef to transmit the lin frame (data for extended frame) true false enables dma tx channel request (dmaerqh, dmaerql) false (tx mode)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-57 preliminary?subject to change without notice 27.11.2 master node, rx mode on a master node in rx mode, the dma interface re quires a single rx channel. each tcd controls a single frame, except for the extended frames (multipl e tcds). the memory map associated to the tcd chain (ram area and linflexd registers) is shown in figure 27-45 . table 27-43. tcd settings (master node, tx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop nbytes[31:0] [4 + 4] + 0/4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. lincr2 + bidr + bdrl + bdrm saddr[31:0] ram address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] lincr2 address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request
pxd20 microcontroller reference manual, rev. 1 27-58 freescale semiconductor preliminary?subject to change without notice figure 27-45. tcd chain memory map (master node, rx mode) the tcd chain of the dma rx cha nnel on a master node supports slave- to-master reception of the data field. the bidr register is optionally copi ed into the ram area. this bidr fi eld (part of fifo data) contains the id of each message to allow the cpu to figure out which id was received by the linflexd dma if only the ?one dma channel? setup is used. the concept fsm to control the dma rx interface is shown in figure 27-46 . the dma rx fsm will move to idle state immediately at next clock edge if dmarxe[0]=0. linflex2 regs ram area frame (n) (slave -> master) dma transfer tcd (n) tcd (n+1) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) 1 dma rx channel (tcd single and/or linked-chain) bdrl + bdrm (4/8 bytes) tcd (n+2) bdrl + bdrm (4/8 bytes) extended frame (n+1) extended frame (n+1) linked chain
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-59 preliminary?subject to change without notice figure 27-46. fsm to control the dma rx interface (master node) the tcd settings (word transfer) are shown in table 27-44 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfer are allowed. table 27-44. tcd settings (master node, rx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop (drf | (dbff & rmb)) & token_dma_rx & dma_ren) ? dma rx transfer (req/ack minor/major loop) from linflex regs to ram area clear token_dma_rx false true clear drf dma rx transfer done ? true false clear dbff,rmb (for extended frame) false drf ? dbff & rmb ? false true (extended frame, size > 8 bytes) true enables dma rx channel request (dmaerqh, dmaerql)
pxd20 microcontroller reference manual, rev. 1 27-60 freescale semiconductor preliminary?subject to change without notice 27.11.3 slave node, tx mode on a slave node in tx mode, the dma interface requires a dma tx channel for each id filter programmed in tx mode. in case a si ngle dma tx channel is available, a single id field filter must be programmed in tx mode. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated to the tcd chai n (ram area and linflexd registers) is shown in figure 27-47 . nbytes[31:0] [4] + 4/8 = n data buffer is stuff ed with dummy bytes if the length is not word aligned. bidr + bdrl + bdrm saddr[31:0] bidr address ? soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n ? daddr[31:0] ram address ? doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no sca tter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request table 27-44. tcd settings (master node, rx mode) (continued) tcd field value description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-61 preliminary?subject to change without notice figure 27-47. tcd chain memory map (slave node, tx mode) the tcd chain of the dma tx channel on a slave node supports: ? slave to master: transmission of the data field ? slave to slave: transm ission of the data field the register settings of the lincr2, ifer , ifmr, and ifcr registers are shown in table 27-45 . the concept fsm to control the dma tx interface is shown in figure 27-48 . dma tx fsm will move to idle state if dmatxe[ x ] = 0, where x =ifmi?1. table 27-45. register settings (slave node, tx mode) lin frame lincr2 ifer ifmr ifcr slave to master or slave to slave ddrq = 0 dtrq = 0 htrq = 0 to enable an id filter (tx mode) for each dma tx channel - identifier list mode - identifier mask mode dfl = payload size id = address ccs = checksum dir = 1(tx) ram area linflex2 regs tcd (n) dma transfer tcd (n+1) frame (n) slave-> master slave ->slave bdrl + bdrm (4/8 bytes) bdrl+ bdrm (4/8 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (8 bytes) 1 dma tx channel/ filter (tcd single and/or linked chain) bdrl + bdrm (4/8 bytes) bdrl + bdrm (4/8 bytes) tcd (n+2) extended frame (n+1) extended frame (n+1) linked chain
pxd20 microcontroller reference manual, rev. 1 27-62 freescale semiconductor preliminary?subject to change without notice figure 27-48. fsm to control the dma tx interface (slave node) the tcd settings (word transfer) are shown in table 27-46 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfer are allowed. !dtf & !drf & (dbef | hrf) & (ifmi != 0) & dma_ten ? dma tx transfer (req/ack) from ram area to linflex regs (channel/filter mapping) set dtrq to transmit the lin frame (data) false true clear dtf dma tx transfer done ? false true dtf ? false true dbef ? clear dbef to transmit the lin frame (data for extended frame) true false dbef ? false true (extended frame, size > 8 bytes) enables dma tx channel/filter request (dmaerqh, dmaerql)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-63 preliminary?subject to change without notice 27.11.4 slave node, rx mode on a slave node in rx mode, th e dma interface requires a dma rx channel for each id filter programmed in rx mode. in case a single dma rx channe l is available, a single id field filter must be programmed in rx mode. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated to the tcd chai n (ram area and linflexd registers) is shown in figure 27-49 . table 27-46. tcd settings (slave node, tx mode) tcd field value description citer[14:0] 1 single iteration for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop nbytes[31:0] 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bdrl + bdrm saddr[31:0] ram address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] bdrl address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no sca tter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request
pxd20 microcontroller reference manual, rev. 1 27-64 freescale semiconductor preliminary?subject to change without notice figure 27-49. tcd chain memory map (slave node, rx mode) the tcd chain of the dma rx channel on a slave node supports: ? master to slave: recep tion of the data field. ? slave to slave: recep tion of the data field. the register setting of the lincr2, ifer , ifmr, and ifcr registers are given in table 27-47 . the concept fsm to control the dma rx interface is shown in figure 27-50 . dma rx fsm will move to idle state if dmarxe[ x ]=0 where x =ifmi?1. table 27-47. register settings (slave node, rx mode) lin frame lincr2 ifer ifmr ifcr master to slave or slave to slave ddrq = 0 dtrq = 0 htrq = 0 to enable an id filter (rx mode) for each dma rx channel - identifier list mode - identifier mask mode dfl = payload size id = address ccs = checksum dir = 0 (rx) linflex2 regs ram area dma transfer extended frame (n+1) tcd (n) tcd (n+1) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) 1 dma rx channel/ filter (tcd single and/or linked chain) bdrl + bdrm (4/8 bytes) extended frame (n+1) bdrl + bdrm (4/8 bytes) tcd (n+2) linked chain frame (n) master-> slave slave ->slave
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-65 preliminary?subject to change without notice figure 27-50. fsm to control the dma rx interface (slave node) the tcd settings (word transfer) are shown in table 27-48 . all other tcd fields = 0. tcd settings based on half-word or byte transfer are allowed. table 27-48. tcd settings (slave node, rx mode) tcd field value description citer[14:0] 1 single iterat ion for the ?major? loop biter[14:0] 1 single iteration for the ?major? loop !dtf & (drf | (dbff & rmb)) & (ifmi != 0) & dma_ren ? dma rx transfer (req/ack) from linflex regs to ram area (channel/filter mapping) false true clear drf dma rx transfer done ? false true false clear dbff,rmb (for extended frame) drf ? dbff & rmb ? false true true (extended frame, size > 8 bytes) enables dma rx channel/filter request (dmaerqh, dmaerql)
pxd20 microcontroller reference manual, rev. 1 27-66 freescale semiconductor preliminary?subject to change without notice 27.11.5 uart node, tx mode in uart tx mode, the dma inte rface requires a dma tx channel. a single tcd can control the transmission of an entire tx buffer. the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 27-51 . figure 27-51. tcd chain memory map (uart node, tx mode) the uart tx buffer must be configur ed in fifo mode in order to: ? allow the transfer of large data buffer by a single tcd nbytes[31:0] [4] + 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bidr + bdrl + bdrm saddr[31:0] bdrl address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] ram address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request table 27-48. tcd settings (slave node, rx mode) (continued) tcd field value description ram area linflex2 regs tcd (n) dma transfer (8/16 bits data format) tcd (n+1) buffer (n) buffer (n+1) bdrl (m half-words) bdrl (2 half-words fifo mode) 1 dma tx channel (tcd single and/or linked chain) bdrl (m bytes) bdrl (4 bytes fifo mode) bdrl (2 half-words fifo mode) bdrl (4 bytes fifo mode) bdrl (m half-words) bdrl (m bytes)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-67 preliminary?subject to change without notice ? adsorb the latency, following a dma request (due to the dma arbitration), to move data from the ram to the fifo ? use low priority dma channels ? support the uart baud rate (2 mb/s) without underrun events the tx fifo size is: ? 4 bytes in 8-bit data format ? 2 half-words in 16-bit data format a dma request is triggered by fifo not full (tx) status signals. the concept fsm to control the dma tx interface is shown in figure 27-52 . dma tx fsm will move to idle state if dmatxe[0] = 0.
pxd20 microcontroller reference manual, rev. 1 27-68 freescale semiconductor preliminary?subject to change without notice figure 27-52. fsm to control the dma tx interface (uart node) the tcd settings (typica l case) are shown in table 27-49 . all other tcd fields = 0. the minor loop transfers a single byte/half-word as soon a free entry is available in the tx fifo. table 27-49. tcd settings (uart node, tx mode) tcd field value description 8-bit data 16-bit data citer[14:0] m multiple iterations for the ?major? loop biter[14:0] m multiple iterations for the ?major? loop !tff & dma_ten ? dma tx transfer (req/ack) from ram area to uart tx fifo false true dma tx (minor loop) done ? false false true !tff ? true uart tx buffer (fifo mode) set txen dma tx (major loop) done ? true false enables dma tx channel request (dmaerqh, dmaerql)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-69 preliminary?subject to change without notice 27.11.6 uart node, rx mode in uart rx mode, the dma inte rface requires a dma rx channel. a single tcd can control the reception of an entire rx buffer. the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 27-53 . figure 27-53. tcd chain memory map (uart node, rx mode) nbytes[31:0] 1 2 minor loop transfer = 1 or 2 bytes saddr[31:0] ram address soff[15:0] 1 2 byte/ha lf-word increment ssize[2:0] 0 1 byte/half-word transfer slast[31:0] -m -m * 2 daddr[31:0] bdrl address daddr = bdrl + 0x3 for byte transfer daddr = bdrl + 0x2 for half-word transfer doff[15:0] 0 no increment (fifo) dsize[2:0] 0 1 byte/half-word transfer dlast_sga[31:0] 0 no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request table 27-49. tcd settings (uart node, tx mode) (continued) tcd field value description 8-bit data 16-bit data linflex2 regs ram area buffer (n) buffer (n+1) tcd (n) tcd (n+1) 1 dma rx channel (tcd single and/or linked chain) bdrm (m half-words) bdrm (m bytes) dma transfer (8/16 bits data format) bdrm (2 half-words fifo mode) bdrm (4 bytes fifo mode) bdrm (2 half-words fifo mode) bdrm (4 bytes fifo mode) bdrm (m half-words) bdrm (m bytes)
pxd20 microcontroller reference manual, rev. 1 27-70 freescale semiconductor preliminary?subject to change without notice the uart rx buffer must be configur ed in fifo mode in order to: ? allow the transfer of large data buffer by a single tcd ? adsorb the latency, following a dma request (due to the dma arbitration), to move data from the fifo to the ram ? use low priority dma channels ? support high uart baud rate (at l east 2 mb/s) without overrun events the rx fifo size is: ? 4 bytes in 8-bit data format ? 2 half-words in 16-bit data format this is sufficient because just one byte allows a reaction time of about 3.8 ? s (at 2 mbit/s), corresponding to about 450 clock cycles at 120 mhz, before the tran smission is affected. a dm a request is triggered by fifo not empty (rx) status signals. the concept fsm to control the dma rx interface is shown in figure 27-54 . dma rx fsm will move to idle state if dmarxe[0] = 0.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-71 preliminary?subject to change without notice figure 27-54. fsm to control the dma rx interface (uart node) the tcd settings (typica l case) are shown in table 27-50 . all other tcd fields = 0. the minor loop transfers a single byte/half-w ord as soon an entry is av ailable in the rx fifo. a new software reset bit is !rfe & dma_ren ? dma rx transfer (req/ack) from uart rx fifo to ram area false true dma rx (major loop) done ? false true !rfe ? true uart rx buffer (fifo mode) timeout config set rxen dma rx (minor loop) done ? true enables dma rx channel request (dmaerqh, dmaerql) false timeout restart timeout ? false set timeout flag true false
pxd20 microcontroller reference manual, rev. 1 27-72 freescale semiconductor preliminary?subject to change without notice required that allows the linflexd fsms to be reset in case this timeout state is reached or in any other case. timeout counter can be re-written by so ftware at any time to extend timeout period. 27.11.7 use cases and limitations ? in lin slave mode, the dma capability can be used only if the id filtering mode is activated. the number of id filters enabled must be equal to the number of dma channels enabled. the correspondence between channel # an d id filter is based on ifmi (i dentifier filter match index). ? in lin master mode both the dma channels (t x and rx) must be en abled in case the dma capability is required. ? in uart mode the dma capability can be used only if the uart tx/rx buffers are configured as fifos. ? dma and cpu operating modes are mutually exclusive for the data/frame transfer on a uart or lin node. once a dma transfer is finished the cpu can handle subsequent accesses. ? error management must be alwa ys executed via cpu enabling the related error interrupt sources. the dma capability does not provi de support for the error manage ment. error management means checking status bits, handling irqs a nd potentially canceling dma transfers. ? the dma programming model must be coherent wi th the tcd setting defined in this document. table 27-50. tcd settings (uart node, rx mode) tcd field value description 8 bits data 16 bits data citer[14:0] m multiple iterat ions for the ?major? loop biter[14:0] m multiple iterat ions for the ?major? loop nbytes[31:0] 1 2 minor loop transfer = 1 or 2 bytes saddr[31:0] bdrm address saddr = bdrm + 0x3 for byte transfer saddr = bdrm + 0x2 for half-word transfer soff[15:0] 0 no increment (fifo) ssize[2:0] 0 1 byte/half-word transfer slast[31:0] 0 daddr[31:0] ram address doff[15:0] 1 2 byte/half-word increment dsize[2:0] 0 1 byte/half-word transfer dlast_sga[31:0] -m -m * 2 no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-73 preliminary?subject to change without notice 27.12 functional description 27.12.1 8-bit timeout counter 27.12.1.1 lin timeout mode figure 27-55. header and response timeout 27.12.1.2 output compare mode 27.12.2 interrupts table 27-51. linflexd interrupt control interrupt event event flag bit enable control bit interrupt vector header received interrupt hrf hrie rxi 1 data transmitted interrupt dtf dtie txi data received interrupt drf drie rxi data buffer empty interrupt dbef dbeie txi data buffer full interrupt dbff dbfie rxi wake-up interrupt wupf wupie rxi lin state interrupt 2 lsf lsie rxi buffer overrun interrupt bof boie err framing error interrupt fef feie err header error interrupt hef heie err checksum error interrupt cef ceie err bit error interrupt bef beie err output compare interrupt ocf ocie err oc frame oc header oc response header response break frame oc1 oc2 response space
pxd20 microcontroller reference manual, rev. 1 27-74 freescale semiconductor preliminary?subject to change without notice figure 27-56. interrupt diagram stuck at zero interrupt szf szie err notes: 1 in slave mode, if at least one filter is configured as tx and enabled, header received interrupt vector is rxi or txi depending on the value of identifier received. 2 for debug and validation purposes. table 27-51. linflexd interrupt control (continued) interrupt event event flag bit enable control bit interrupt vector lsie states wuie wuf dbff drf hrie tx dtie dtf hrie hrf rx dbfie drie boie bof feie fef cef beie bef ceie hrf heie sfef,sdef,idpef ocie ocf szie szf error dbeie dbef toie to
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-75 preliminary?subject to change without notice 27.12.3 fractional baud rate generation the baud rates for the receiver and transmitter are both set to the sa me value as programmed in the mantissa (linibrr) and fr action (linfbrr) registers . lfdiv is an unsigned fixed point number. the 20-bit ma ntissa is coded in the linibrr register and the fraction is coded in the linfbrr register. the following examples show how to derive lf div from linibrr and li nfbrr register values: example 27-1. if linibrr = 27d and linfbrr = 12d, then mantissa (lfdiv) = 27d fraction (lfdiv) = 12/16 = 0.75d therefore lfdiv = 27.75d example 27-2. to program lfdiv = 25.62d, linfbrr = 16 * 0.62 = 9.92, nearest real number 10d = ah linibrr = mantissa(25.620d) = 25d = 19h note the baud counters are updated with the new value of the baud registers after a write to linibrr. hence the baud register value must not be changed during a transact ion. the linfbrr (contai ning the fraction bits) must be programmed before linibrr. note lfdiv must be greater than or equal to 1.5d, for example, linibrr = 1 and linfbrr = 8. therefore, the maximum possible baudrate is fperiph_set_1_clk / 24. 27.13 programming considerations this section describes the various configurat ions in which the linflexd can be used. tx/rx baud = f ipg_clock_lin (16 * lfdiv)
pxd20 microcontroller reference manual, rev. 1 27-76 freescale semiconductor preliminary?subject to change without notice 27.13.1 master node figure 27-57. programming consideration: master node, transmitter figure 27-58. programming consideration: master node, receiver figure 27-59. programming consideration: master node, transmitter, bit error figure 27-60. programming consideration: master node, receiver, checksum error header data tx checksum tx configure id dfl, data buffer set htrq txi interrupt dtf set dir = 1 header data rx checksum rx configure id, dfl set htrq rxi interrupt drf set dir = 0 and ddrq = 0 header data tx configure id dfl, data buffer set htrq dir = 1 bef set erri interrupt iobe = 1 header data tx checksum tx configure id dfl, data buffer set htrq tx interrupt dtf set dir = 1 bef set err interrupt iobe = 0 header data rx checksum rx configure id, dfl set htrq err interrupt cef set dir = 0 and ddrq = 0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-77 preliminary?subject to change without notice 27.13.2 slave node figure 27-61. programming consideration: slave node, transmitter, no filters figure 27-62. programming consideration: slave node, receiver, no filters figure 27-63. programming consideration: slave node, transmitter, no filters, bit error figure 27-64. programming consideration: slave node, receiver, no filters, checksum error figure 27-65. programming consideration: slave node, at le ast one tx filter, bf is reset, id matches filter header data tx checksum tx tx interrupt dtf set hrf set rx interrupt set dtrq configure ccs, dir, dfl, data buffers header data rx checksum rx rx interrupt drf set configure ccs, dir, dfl hrf set rx interrupt ddrq = 0 header ddrq = 1 hrf set rx interrupt header data tx err interrupt bef set hrf set rx interrupt set dtrq configure dir, dfl, data buffers iobe = 1 header data rx checksum rx err interrupt cef set ddrq = 0 configure dir, dfl hrf set rx interrupt header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (id matched) note: this configuration can be used in case the slave never receives data (for example, as with a sensor).
pxd20 microcontroller reference manual, rev. 1 27-78 freescale semiconductor preliminary?subject to change without notice figure 27-66. programming consideration: slave node, at least one rx filter, bf is reset, id matches filter figure 27-67. programming consideration: slave node, rx only, tx only, rx and tx filters, id not matching filter, bf is reset figure 27-68. programming consideration: slave node, tx filter, bf is set header data rx checksum rx rxi interrupt drf set ifmi = id matched+1 header id not matching any filter header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (id has matched) header data rx checksum rx rx interrupt drf set ddrq = 0 configure ccs, dir, dfl hrf set rx interrupt (id not matched) note: this configuration is used when: a) all tx ids are managed by filters b) the number of other filters is not enough to manage all reception ids
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-79 preliminary?subject to change without notice figure 27-69. programming consideration: slave node, rx filter, bf is set figure 27-70. programming consideration: slave node, tx filter, rx filter, bf is set header data rx checksum rx rx interrupt drf set ifmi = id matched header data rx checksum rx rx interrupt drf set hrf set rx interrupt (id not matched) configure ccs, dir, dfl (id is rx) ddrq = 0 header data tx checksum tx tx interrupt dtf set hrf set rx interrupt set dtrq configure ccs, dir, dfl, data buffers (id is tx) header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (ifmi = id matched+1) header data rx checksum rx rxi interrupt drf set ifmi = id matched+1 header data rx/tx checksum rx/tx rx/tx interrupt drf/dtf set ddrq = 0 configure ccs, dir, dfl hrf set rx interrupt (id not matched) note: this configuration is used when: a) the number of filters is not enough b) filters are used for most frequently used ids to reduce cpu usage
pxd20 microcontroller reference manual, rev. 1 27-80 freescale semiconductor preliminary?subject to change without notice 27.13.3 extended frames figure 27-71. programming consideration: extended frames 27.13.4 timeout figure 27-72. programming consideration: response timeout figure 27-73. programming consideration: frame timeout figure 27-74. programming consideration: header timeout header 8 bytes tx 8 bytes tx checksum tx tx interrupt dtf set configure dir, dfl, hrf set rx interrupt (id not matched) dbef set refill buffer reset dbef ccs dtrq =1 header 8 bytes rx 8 bytes rx checksum rx rx interrupt drf set configure dir, dfl, hrf set rx interrupt (id not matched) rmb, dbff read buffer reset rmb set ddrq = 0 ccs header rx/tx data rx oc1 t response_max ocf is set err interrupt header rx/tx data rx/tx oc2 t frame_max ocf is set err interrupt header rx oc1 t header_max ocf is set err interrupt break
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 27-81 preliminary?subject to change without notice 27.13.5 uart mode figure 27-75. programming consideration: uart mode data rx/tx dtf/drf is set tx/rx interrupt set txen/rxen write buffer for tx
pxd20 microcontroller reference manual, rev. 1 27-82 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-1 preliminary?subject to change without notice chapter 28 memory protection unit (mpu) 28.1 introduction the amba-ahb memory protection unit (mpu) pr ovides hardware access control for all memory references generated in the device . using preprogrammed region descri ptors which define memory spaces and their associated access rights, the mpu concurre ntly monitors all system bus transactions and evaluates the appropriateness of each tr ansfer. memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descript or or have insufficient rights are terminated with a protect ion error response. this module is commonly included as part of the platform. 28.1.1 overview the mpu module provides the following capabilities: ? support for 16 program-visible 128-bi t (4-word) region descriptors ? each region descriptor defi nes a modulo-32 byte space, al igned anywhere in memory ? region sizes can vary from a minimum of 32 bytes to a maximum of 4 gb ? two types of access control permissions defined in single descriptor word ? processors have separate {read, write, execute } attributes for supervisor and user accesses ? non-processor masters have {read, write} attributes ? hardware-assisted maintenance of the desc riptor valid bit minimi zes coherency issues ? alternate programming model view of the access control permissions word ? memory-mapped platform device ? interface to 4 slave ahb ports: flash controll er (instruction port), system ram controller, graphics ram (non-z160 port) , and ips peripherals bus ? connections to the ahb address phase address and attributes ? typical location is immediately ?downstream ? of the platform?s crossbar switch ? connection to the ips bus provides acc ess to the mpu?s programming model a simplified block diagram of the ahb_mpu module is shown in figure 28-1 . the ahb bus slave ports (s{0,1,2,3}_h*) are shown on the left side of the diagram, the region descriptor regi sters in the middle and the ips bus interface (ips_*) on the right side. th e evaluation macro contains the two magnitude comparators connected to the start and end address re gisters from each region descriptor (rgdn) as well as the combinational logic blocks to determine the region hit and the access protection error. for information on the details of the access evaluation macro, see section 28.3.1, access evaluation macro .
pxd20 microcontroller reference manual, rev. 1 28-2 freescale semiconductor preliminary?subject to change without notice figure 28-1. ahb_mpu block diagram ahb_mpu ips_wdata ips_addr decode mux ips bus 31 0 control rgd0 rgd1 rgd(n-1) hit_b start end error ips_rdata 31 0 hit_b start end error error_detail (edrn) error_address (earn) > > ahb_error_ap > > ahb bus slave ports address phase signals s{1,2,3}_h* s0_h* r,w,x r,w,x
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-3 preliminary?subject to change without notice 28.1.2 features the memory protection unit implemen ts a two-dimensional hardware ar ray of memory region descriptors and the crossbar slave ahb ports to continuously monitor the legality of every memory reference generated by each bus master in th e system. the feature set includes: ? support for 16 memory region descri ptors, each 128 bits in size ? specification of start and end a ddresses provide granularity for region sizes from 32 bytes to 4 gbytes ? access control definitions: 2 bus masters (proce ssor cores) support the tr aditional {r ead, write, execute} permissions with independent defini tions for supervisor and user mode accesses ? automatic hardware maintenance of the region de scriptor valid bit rem oves issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control wo rd for each descriptor provides an efficient mechanism to dynamically alter only th e access rights of a descriptor ? for overlapping region descript ors, priority is given to permission granting over access denying as this approach provides more flexibility to sy stem software. see section 28.3.2, putting it all together and ahb error terminations ? for details and section 28.6, application information ? for an example. ? support for 3 ahb slave port c onnections: flash controller, sy stem ram controller and ips peripherals bus ? mpu hardware continuously m onitors every ahb slave port access using the preprogrammed memory region descriptors ? an access protection error is det ected if a memory reference doe s not hit in any memory region or the reference is flagged as il legal in all memory regions where it does hit. in the event of an access error, the ahb reference is terminated wi th an error response and the mpu inhibits the bus cycle being sent to the targeted slave device. ? 64-bit error registers, one for each ahb slave port, capture the last faulting address, attributes and ?detail? information ? global mpu enable/disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete acces s rights during debug with the module disabled 28.1.3 modes of operation the mpu module does not support any special modes of operation. as a memory-mapped device located on the platform?s high-speed system bus, it responds based strictly on the memory addresses of the connected system buses. the ips bus is used to access the mpu?s programming model and the memory protection functions are evaluated on a reference-by-reference basis us ing the addresses from the ahb system bus port(s). power dissipation is minimized when the mp u?s global enable/disable bit is cleared (mpu_cesr[vld] = 0).
pxd20 microcontroller reference manual, rev. 1 28-4 freescale semiconductor preliminary?subject to change without notice 28.1.4 external signal description the mpu module does not include any external interf ace. the mpu?s internal in terfaces include an ips connection for accessing the programming model and multip le connections to the a ddress phase signals of the platform crossbar?s slave ah b ports. from a platform topology vi ewpoint, the mpu module appears to be directly connected ?downstrea m? from the crossbar sw itch with interfaces to the ahb slave ports. 28.2 memory map and register description the mpu module provides an ips programming model mapped to an spp-standard on-platform 16 kbyte space. the programming model is partitioned into three groups: control/status regist ers, the data structure containing the region descriptors and the alternate view of the region descriptor access control values. the programming model can onl y be referenced using 32- bit (word) accesses. atte mpted references using different access sizes, to undefined (r eserved) addresses, or with a non- supported access type (for example, a write to a read-only regi ster or a read of a write-only register ) generate an ips error termination. finally, the programming m odel allocates space for an mpu definition with 8 re gion descriptors and up to 3 ahb slave ports, like flash controller, syst em ram controller a nd ips peripherals bus. 28.2.1 memory map the mpu programming model map is shown in table 28-1 . table 28-1. mpu memory map offset address register name register description size (bits) access location 0x0000 mpu_cesr mpu control/ error status register 32 r/ partial-w on page 28-6 0x0004- 0x000f reserved 0x0010 mpu_ear0 mpu error address register, slave port 0 32 r-only on page 28-7 0x0014 mpu_edr0 mpu error detail register, slave port 0 32 r-only on page 28-7 0x0018 mpu_ear1 mpu error address register, slave port 1 32 r-only on page 28-7 0x001c mpu_edr1 mpu error detail register, slave port 1 32 r-only on page 28-7 0x0020 mpu_ear2 mpu error address register, slave port 2 32 r-only on page 28-7 0x0024 mpu_edr2 mpu error detail register, slave port 2 32 r-only on page 28-7 0x0028 mpu_ear3 mpu error address register, slave port 3 32 r-only on page 28-7 0x002c mpu_edr3 mpu error detail register, slave port 3 32 r-only on page 28-7 0x0030-0x0 3ff reserved 0x0400 mpu_rgd0 mpu region descriptor 0 128 r/w on page 28-8 0x0410 mpu_rgd1 mpu region descriptor 1 128 r/w on page 28-8
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-5 preliminary?subject to change without notice 0x0420 mpu_rgd2 mpu region descriptor 2 128 r/w on page 28-8 0x0430 mpu_rgd3 mpu region descriptor 3 128 r/w on page 28-8 0x0440 mpu_rgd4 mpu region descriptor 4 128 r/w on page 28-8 0x0450 mpu_rgd5 mpu region descriptor 5 128 r/w on page 28-8 0x0460 mpu_rgd6 mpu region descriptor 6 128 r/w on page 28-8 0x0470 mpu_rgd7 mpu region descriptor 7 128 r/w on page 28-8 0x0480 mpu_rgd8 mpu region descriptor 8 128 r/w on page 28-8 0x0490 mpu_rgd9 mpu region descriptor 9 128 r/w on page 28-8 0x04a0 mpu_rgd10 mpu region descriptor 10 128 r/w on page 28-8 0x04b0 mpu_rgd11 mpu region descriptor 11 128 r/w on page 28-8 0x04c0 mpu_rgd12 mpu region descriptor 12 128 r/w on page 28-8 0x04d0 mpu_rgd13 mpu region descriptor 13 128 r/w on page 28-8 0x04e0 mpu_rgd14 mpu region descriptor 14 128 r/w on page 28-8 0x04f0 mpu_rgd15 mpu region descriptor 15 128 r/w on page 28-8 0x0500? 0x07ff reserved 0x0800 mpu_rgdaac0 mpu rgd alternate access control 0 32 r/w on page 28-13 0x0804 mpu_rgdaac1 mpu rgd alternate access control 1 32 r/w on page 28-13 0x0808 mpu_rgdaac2 mpu rgd alternate access control 2 32 r/w on page 28-13 0x080c mpu_rgdaac3 mpu rgd alternate access control 3 32 r/w on page 28-13 0x0810 mpu_rgdaac4 mpu rgd alternate access control 4 32 r/w on page 28-13 0x0814 mpu_rgdaac5 mpu rgd alternate access control 5 32 r/w on page 28-13 0x0818 mpu_rgdaac6 mpu rgd alternate access control 6 32 r/w on page 28-13 0x081c mpu_rgdaac7 mpu rgd alternate access control 7 32 r/w on page 28-13 0x0820 mpu_rgdaac8 mpu rgd alternate access control 8 32 r/w on page 28-13 0x0824 mpu_rgdaac9 mpu rgd alternate access control 9 32 r/w on page 28-13 0x0828 mpu_rgdaac10 mpu rgd alternate access control 10 32 r/w on page 28-13 0x082c mpu_rgdaac11 mpu rgd alternate access control 11 32 r/w on page 28-13 0x0830 mpu_rgdaac12 mpu rgd alternate access control 12 32 r/w on page 28-13 0x0834 mpu_rgdaac13 mpu rgd alternate access control 13 32 r/w on page 28-13 0x0838 mpu_rgdaac14 mpu rgd alternate access control 14 32 r/w on page 28-13 table 28-1. mpu memory map (continued) offset address register name register description size (bits) access location
pxd20 microcontroller reference manual, rev. 1 28-6 freescale semiconductor preliminary?subject to change without notice 28.2.2 register description the following sections detail the individual re gisters within the mpu?s programming model. 28.2.2.1 mpu control/error st atus register (mpu_cesr) the mpu_cesr provides one byte of error status plus three bytes of configur ation information. a global mpu enable/disable bit is also included in this register. figure 28-2. mpu control/error status register (mpu_cesr) 0x083c mpu_rgdaac15 mpu rgd alternate access control 15 32 r/w on page 28-13 0x0840- 0x3fff reserved offset mpu_base + 0x000 access: read/partial write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sperr 1 0 0 0 hrl nsp nrgd 0 0 0 0 0 0 0 vl d w w1c reset 0 0 0 0 0 0 0 0 1 0 0 0 * * * * 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 table 28-2. mpu_cesr field descriptions field description sperr slave port n error, where the slave port number ma tches the bit number. each bit in this field represents a flag maintained by the mpu for signaling the pr esence of a captured error contained in the mpu_earn and mpu_edrn registers. the individual bi t is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written as a logical one. if another error is ca ptured at the exact same cycle as a write of a logica l one, this flag remains set. a ?find first one? instruction (or equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_earn/mpu_edrn registers do not contain a captured error. 1 the corresponding mpu_earn/mpu_edrn r egisters do contain a captured error. hrl hardware revision level. this 4-bit read-only field specifies the mpu?s hardware and definition revision level. it can be read by software to det ermine the functional defin ition of the module. nsp number of slave ports. this 4-bit read-only field specifies the number of slave ports [1-8] connected to the mpu. this field contains values of 0b0001 -0b1000, depending on the device configuration. the pxd20 has 4 slaves connected to the mpu. table 28-1. mpu memory map (continued) offset address register name register description size (bits) access location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-7 preliminary?subject to change without notice 28.2.2.2 mpu error address regi ster, slave port n (mpu_earn) when the mpu detects an access error on slave port n, th e 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. additional information about the faulting access is captured in the corresponding mpu_edrn re gister at the same time. note this register and the corresponding mpu_ed rn register contain the most r ecent access error; there are no hardware interlocks with the mpu_ cesr[sperr] field as the error re gisters are always loaded upon the occurrence of each pr otection violation. figure 28-3. mpu error address register, slave port n (mpu_earn) 28.2.2.3 mpu error detail register, slave port n (mpu_edrn) when the mpu detects an access error on slave port n, 32 bits of error deta il are captured in this read-only register and the corresponding bit in the mpu_cesr [sperr] field set. information on the faulting address is captured in the correspondi ng mpu_earn register at the same time. note this register and the corresponding mpu_earn register contain the most r ecent access error; there are no hardware interlocks with the mpu_cesr[sperr] field as the error regist ers are always loaded upon the occurrence of each protection violation. nrgd number of region descriptors. this 4-bit read-only field specifies the number of region descriptors implemented in the mpu. the defined encodings include: 0000 8 region descriptors 0001 12 region descriptors 0010 16 region descriptors (the number of descriptors on the pxd20) vld valid. this bit provides a global enable/disable for the mpu. 0 the mpu is disabled. 1 the mpu is enabled. while the mpu is disabled, all accesses from all bus masters are allowed. offset mpu_base + 0x010 (mpu_ear0) mpu_base + 0x018 (mpu_ear1) mpu_base + 0x020 (mpu_ear2) mpu_base + 0x028 (mpu_ear3) access: read read read read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr w reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - table 28-3. mpu_earn field descriptions field description eaddr error address. this read-only field is the refer ence address from slave port n that generated the access error. table 28-2. mpu_cesr field descriptions field description
pxd20 microcontroller reference manual, rev. 1 28-8 freescale semiconductor preliminary?subject to change without notice figure 28-4. mpu error detail register, slave port n (mpu_edrn) 28.2.2.4 mpu region desc riptor n (mpu_rgdn) each 128-bit (16 byte) region descri ptor specifies a given memory space and the access attributes associated with that space. the desc riptor definition is the very esse nce of the operation of the memory protection unit. offset mpu_base + 0x014 (mpu_edr0) mpu_base + 0x01c (mpu_edr1) mpu_base + 0x024 (mpu_edr2) mpu_base + 0x02c (mpu_edr3) access: read read read read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eacd epid emn eattr erw w reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - table 28-4. mpu_edrn field descriptions field description 0?15 eacd error access control detail. this 16-bit read-only field implements one bit per region descriptor and is an indication of the region descriptor hit logically anded with the access error indication. the mpu performs a reference-by-reference evaluation to deter mine the presence/absence of an access error. when an error is detected, the hit-qualified acce ss control vector is capt ured in this field. if the mpu_edrn register contains a captured error and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection erro r as defined by the specific set bits. if only a single eacd bit is set, then the protection error was caused by a single non-overlapping region descriptor. if two or more eacd bits are set, then the protection error was caused in an overlapping set of region descriptors. 16?23 epid error process identification. this 8-bit read-only field records the process identifier of the faulting reference. the process identifier is typically driven onl y by processor cores; for other bus masters, this field is cleared. 24?27 emn error master number. this 4-bit read-only field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error. 28?30 eattr error attributes. this 3-bit read-only field records a ttribute information about the faulting reference. the supported encodings are defined as: 0b000user mode, instruction access 0b001user mode, data access 0b010supervisor mode, instruction access 0b011supervisor mode, data access all other encodings are reserved. for non-cpu bus mast ers, the access attribute information is typically wired to supervisor, data (0b011). 31 erw error read/write. this 1-bit read-only field signals the access type (read, write) of the faulting reference. 0 read 1write
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-9 preliminary?subject to change without notice the region descriptors ar e organized sequentially in the mpu?s pr ogramming model and each of the four 32-bit words are detailed in the subsequent sections. 28.2.2.4.1 mpu region descriptor n, word 0 (mpu_rgdn.word0) the first word of the mpu region descriptor define s the 0-modulo-32 byte start address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 28.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). figure 28-5. mpu region descriptor, wo rd 0 register (mpu_rgdn.word0) 28.2.2.4.2 mpu region descriptor n, word 1 (mpu_rgdn.word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 28.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). figure 28-6. mpu region descriptor, wo rd 1 register (mpu_rgdn.word1) offset mpu_base + 0x400 + (16*n) + 0x0 (mpu_rgdn.word0) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r srtaddr 0 0 0 0 0 w reset - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0 table 28-5. mpu_rgdn.word0 field descriptions field description 0?26 srtaddr start address. this field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. offset mpu_base + 0x400 + (16*n) + 0x4 (mpu_rgdn.word1) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r endaddr 1 1 1 1 1 w reset - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 table 28-6. mpu_rgdn.word1 field descriptions field description 0?26 endaddr end address. this field defines the most significant bits of the 31-modulo-32 byte end address of the memory region. there are no hardware checks to verify that endaddr >= srtaddr; it is software?s responsibility to properly load these region descriptor fields.
pxd20 microcontroller reference manual, rev. 1 28-10 freescale semiconductor preliminary?subject to change without notice 28.2.2.4.3 mpu region descriptor n, word 2 (mpu_rgdn.word2) the third word of the mpu region de scriptor defines the access control rights of the memory region. the access control privileges are depende nt on two broad classifications of bus masters. bus masters 0-3 are typically reserved for processor cores and the corresponding access c ontrol is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as we ll as the optional inclusion of a process identification field within the definition. bus ma sters 4-7 are typically rese rved for data movement engines and their capabilities are limited to separate read and write pe rmissions. for these fields, the bus master number refers to the logical master number defined by the master ids listed in table 9-1 . for the processor privilege rights, there are three flags associated with this functi on: {read, write, execute}. in this context, these flags fo llow the traditional definition: ? read ( r ) permission refers to the ability to access th e referenced memory address using an operand (data) fetch. ?write ( w ) permission refers to the ability to update the referenced memory address using a store (data) instruction. ? execute ( x ) permission refers to the ability to read the referenced memory address using an instruction fetch. the evaluation logic defines the processor access t ype based on multiple ahb signals, as hwrite and hprot[1:0]. for non-processor data movement engi nes (bus masters 4-7), the evaluati on logic simply uses hwrite to determine if the access is a read or write. writes to this word clear the re gion descriptor?s valid bit (see section 28.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) , for more information). since it is al so expected that sy stem software may adjust only the access controls with in a region descriptor (mpu_rgdn.wo rd2) as different tasks execute, an alternate programming view of th is 32-bit entity is provided. if only the access controls are being updated, this operation should be pe rformed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descri ptor?s valid bit. figure 28-7. mpu region descriptor, wo rd 2 register (mpu_rgdn.word2) offset mpu_base + 0x400 + (16*n) + 0x8 (mpu_rgdn.word2) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 4 15 16 17 18 19 2 0 21 22 23 24 25 2 6 27 28 29 30 31 r m 7 r e m 7 w e m 6 r e m 6 w e m 5 r e m 5 w e m 4 r e m 4 w e m 3 p e m3sm m3um r w x m 2 p e m2sm m2um r w x m 1 p e m1sm m1um r w x m 0 p e m0sm m0um r w x w reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-11 preliminary?subject to change without notice table 28-7. mpu_rgdn.word2 field descriptions field description 0 m7re bus master 7 read enable. if set, this flag allows bus master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. 1 m7we bus master 7 write enable. if set, this flag allows bus master 7 to perform write operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. 2 m6re bus master 6 read enable. if set, this flag allows bus master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. 3 m6we bus master 6 write enable. if set, this flag allows bus master 6 to perform write operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. 4 m5re bus master 5 read enable. if set, this flag allows bus master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. 5 m5we bus master 5 write enable. if set, this flag allows bus master 5 to perform write operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. 6 m4re bus master 4 read enable. if set, this flag allows bus master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. 7 m4we bus master 4 write enable. if set, this flag allows bus master 4 to perform write operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. 8 m3pe bus master 3 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 9?10 m3sm bus master 3 supervisor mode access control. this 2-bit field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode 11?13 m3um bus master 3 user mode access control. this 3-bit field defines the access controls for bus master 3 when operating in user mode. the m3um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. 14 m2pe bus master 2 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 15?16 m2sm bus master 2 supervisor mode access control. this 2-bit field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode 17?19 m2um bus master 2 user mode access control. this 3-bit field defines the access controls for bus master 2 when operating in user mode. the m2um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed.
pxd20 microcontroller reference manual, rev. 1 28-12 freescale semiconductor preliminary?subject to change without notice 28.2.2.4.4 mpu region descriptor n, word 3 (mpu_rgdn.word3) the fourth word of the mpu region descriptor contains the optional process identi fier and mask, plus the region descriptor?s valid bit. since the region descriptor is a 128-bi t entity, there are potential coherency issues as this structure is being updated since multiple writes are required to update the entire descriptor. ac cordingly, the mpu hardware assists in the operation of the descri ptor valid bit to preven t incoherent region desc riptors from generating spurious access errors. in pa rticular, it is expected th at a complete update of a re gion descriptor is typically done with sequential writes to mpu_rgdn.word0, then mpu_rgdn.word1,... and finally mpu_rgdn.word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. since it is also expected that system software may ad just only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32-bit entity is provided. if only the access controls are being updated, this operation s hould be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. 20 m1pe bus master 1 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 21?22 m1sm bus master 1 supervisor mode access control. this 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode 23?25 m1um bus master 1 user mode access control. this 3-bit field defines the access controls for bus master 1 when operating in user mode. the m1um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. 26 m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 27?28 m0sm bus master 0 supervisor mode access control. this 2-bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode 29?31 m0um bus master 0 user mode access control. this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. table 28-7. mpu_rgdn.word2 field descriptions field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-13 preliminary?subject to change without notice figure 28-8. mpu region descriptor, wo rd 3 register (mpu_rgdn.word3) 28.2.2.5 mpu region descri ptor alternate access c ontrol n (mpu_rgdaacn) as noted in section 28.2.2.4.3, mpu region descript or n, word 2 (mpu_rgdn.word2) , it is expected that since system software may adjust only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32-bit entity is desired. if only the access controls are being update d, this operation should be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgdn.word2. figure 28-9. mpu rgd alternate access control n (mpu_rgdaacn) offset mpu_base + 0x400 + (16*n) + 0xc (mpu_rgdn.word3) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pid pidmask 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 vl d w reset - - - - - - - - - - - - - - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 table 28-8. mpu_rgdn.word3 field descriptions field description 0?7 pid process identifier. this 8-bit field specifies that the optional process id entifier is to be included in the determination of whether the current access hits in th e region descriptor. this field is combined with the pidmask and included in the region hit determi nation if mpu_rgdn.wor d2[mxpe] is set. 8?15 pidmask process identifier mask. this 8-bit field provides a ma sking capability so that mu ltiple process identifiers can be included as part of the region hit determi nation. if a bit in the pidmask is set, then the corresponding bit of the pid is ignored in the comparison. this field is combined with the pid and included in the region hit determination if mpu_rg dn.word2[mxpe] is set. for more information on the handling of the pid and pidmask, see section 28.3.1.1, access ev aluation ? hit determination . 31 vld valid. this bit signals the region descriptor is valid. any write to mpu_rgdn.word{0,1,2} clears this bit, while a write to mpu_rgdn.word3 sets or clears this bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid offset mpu_base + 0x800 + (4*n) (mpu_rgdaacn) access: r/w 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 4 15 16 17 18 19 2 0 21 22 23 24 25 2 6 27 28 29 30 31 r m 7 r e m 7 w e m 6 r e m 6 w e m 5 r e m 5 w e m 4 r e m 4 w e m 3 p e m3sm m3um r w x m 2 p e m2sm m2um r w x m 1 p e m1sm m1um r w x m 0 p e m0sm m0um r w x w reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
pxd20 microcontroller reference manual, rev. 1 28-14 freescale semiconductor preliminary?subject to change without notice since the mpu_rgdaacn register is simply anot her memory mapping for mpu_rgdn.word2, the field definitions shown in table 28-9 are identical to those presented in table 28-7 . table 28-9. mpu_rgdaacn field descriptions field description 0 m7re bus master 7 read enable. if set, this flag allows bu s master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. 1 m7we bus master 7 write enable. if set, this flag allows bus master 7 to perform write operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. 2 m6re bus master 6 read enable. if set, this flag allows bu s master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. 3 m6we bus master 6 write enable. if set, this flag allows bus master 6 to perform write operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. 4 m5re bus master 5 read enable. if set, this flag allows bu s master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. 5 m5we bus master 5 write enable. if set, this flag allows bus master 5 to perform write operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. 6 m4re bus master 4 read enable. if set, this flag allows bu s master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. 7 m4we bus master 4 write enable. if set, this flag allows bus master 4 to perform write operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. 8 m3pe bus master 3 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 9?10 m3sm bus master 3 supervisor mode access control. this 2-bit field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode 11?13 m3um bus master 3 user mode access control. this 3-bit field defines the access controls for bus master 3 when operating in user mode. the m3um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 14 m2pe bus master 2 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 15?16 m2sm bus master 2 supervisor mode access control. this 2-bit field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-15 preliminary?subject to change without notice 28.3 functional description in this section, the functional operati on of the mpu is detailed. in partic ular, subsequent sections discuss the operation of the access ev aluation macro as well as the handling of error-terminated ahb bus cycles. 28.3.1 access evaluation macro as previously discussed, the basic operation of th e mpu is performed in the access evaluation macro, a hardware structure replicated in the two- dimensional connection matrix. as shown in figure 28-10 , the access evaluation macro inputs the ah b system bus address phase signals (ahb_ap) and the contents of a region descriptor (rgdn) and performs two majo r functions: region hit determination (hit_b) and detection of an access prot ection violation (error). 17?19 m2um bus master 2 user mode access control. this 3-bit field defines the access controls for bus master 2 when operating in user mode. the m2um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 20 m1pe bus master 1 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 21?22 m1sm bus master 1 supervisor mode access control. this 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode 23?25 m1um bus master 1 user mode access control. this 3-bit field defines the access controls for bus master 1 when operating in user mode. the m1um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 26 m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 27?28 m0sm bus master 0 supervisor mode access control. this 2-bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode 29?31 m0um bus master 0 user mode access control. this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 28-9. mpu_rgdaacn field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 28-16 freescale semiconductor preliminary?subject to change without notice figure 28-10. mpu access evaluation macro figure 28-10 is not intended to be a schematic of th e actual access evaluation macro, but rather a generalized block diagram showing the majo r functions included in this logic block. 28.3.1.1 access evaluati on ? hit determination to evaluate the region hit determination, the mpu us es two magnitude comparators in conjunction with the contents of a region descriptor : the current access must be include d between the region's "start" and "end" addresses and simult aneously the region's valid bit must be active. recall there are no hardware checks to verify that region's "end" a ddress is greater then region's "start" address, and it is software?s respons ibility to properly load appropriate values into these fields of the region descriptor. in addition to this, the optional process identifier is examined against the region descriptor?s pid and pidmask fields. in order to generate the pid_hit i ndication: the current pid with its pidmask must be equal to the region's pid with its pidm ask. also the process identifier enab le is take into account in this comparison so that the mpu forces the pid_hit term to be asserted in the case of ahb bus master does not provide its process identifier. 28.3.1.2 access evaluation ? priv ilege violation determination while the access evaluation macro is making the region hit determinat ion, the logic is also evaluating if the current access is allowed by the permissions define d in the region descriptor . the protection violation hit_b start end error > > rgdn ahb_ap hit & error hit_b | error >= <= r,w,x
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-17 preliminary?subject to change without notice logic then evaluates the access against the effect ive permissions using the specification shown in table 28-10 . as shown in figure 28-10 , the output of the protection viol ation logic is the error signal. the access evaluation macro then uses the hit_b and error signals to form two outputs. the combined (hit_b | error) signal is used to signa l the current access is not allowed a nd (~hit_b & error) is used as the input to mpu_edrn (error detail regi ster) in the event of an error. 28.3.2 putting it all together and ahb error terminations for each ahb slave port being monitored, the mpu perf orms a reduction-and of al l the individual (hit_b | error) terms from each access eval uation macro. this expression then terminates the bus cycle with an error and reports a protecti on error for three conditions: 1. if the access does not hit in any region descriptor, a protection error is reported. 2. if the access hits in a single region descriptor and that region si gnals a protection violation, then a protection error is reported. 3. if the access hits in multiple (overlapping) regions a nd all regions signal prot ection violations, then a protection error is reported. the third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to syst em software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 28.6, application information . in event of a protection error, th e mpu requires two distinct actions: 1. intercepts the error during the ahb address pha se (first cycle out of two) and cancels the transaction before it is seen by the slave device. 2. performs the required logic func tions to force the standard 2-cy cle ahb error response to properly terminate the bus transaction and then provides the right values to the crossbar switch to commit the ahb transaction to other portions of the platform. table 28-10. protection violation definition description inputs output eff_r gd[r] eff_rgd[ w] eff_rgd[ x] protection violation? inst fetch read - - 0 yes, no x permission inst fetch read - - 1 no, access is allowed data read 0 - - yes, no r permission data read 1 - - no, access is allowed data write - 0 - yes, no w permission data write - 1 - no, access is allowed
pxd20 microcontroller reference manual, rev. 1 28-18 freescale semiconductor preliminary?subject to change without notice if instead the access is allowed, then the mpu simply pa sses all "original" ahb si gnals to the slave device. in this case, from functionality point of view, the mpu is fully transparent. 28.4 initialization information the reset state of mpu_cesr[vld] disables the enti re module. recall while th e mpu is disabled, all accesses from all bus masters are allowed. this stat e also minimizes the power dissipation of the mpu. the power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region desc riptors (mpu_rgdn) are load ed at system startup, including the setting of the mpu_rgdn.word3[vld] bi ts, before mpu_cesr[vld] is set, enabling the module. this approach allows all the loaded region de scriptors to be enabled si multaneously. recall if a memory reference does not hit in any region descriptor, the attempted access is term inated with an error. 28.5 opcode pre-fetch cycles and the execute permission the cpu pre-fetches program-c ode past the current instruction to opt imize performance. the code that is pre-fetched may never be executed or even be reach able (in the case of a branch), however the mpu module has no way of knowing this at th e time when the pre-fetch cycles occur. therefore such pre-fetches will result in an access violation if the opcode pre- fetch accesses a memory range in which the "x" execute access mode is not permitted. this must be taken into account when defining memory ranges without execute permission adjacent to memory used for program code. the best way to do this would be to leave some fill-bytes between the memory ranges in this case ? that is, do not set the upper memory boundary to the address of the last opcode but to a fo llowing address which is several words away. 28.6 application information in an operational system, interfacing wi th the mpu can generally be classified into th e following activities: 1. creation of a new memory region requires load ing the appropriate region descriptor into an available register location. when a new descriptor is loaded into a rgdn, it would typically be performed using four 32-bit wo rd writes. as discussed in section 28.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) , the hardware assists in the maintenance of the valid bit, so if this approach is foll owed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/remova l of an existing memory region is performed simply by clearing mpu_rgdn.word3[vld]. 2. if only the access rights for an existing region de scriptor need to change , a 32-bit write to the alternate version of the access control word (mpu_rgdaacn) would t ypically be performed. recall writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by de finition, no coherency issues invol ved with the update. the access rights associated with the memory region switch in stantaneously to the new value as the ips write completes.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 28-19 preliminary?subject to change without notice 3. if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the re gion descriptor: mpu_rgdn.word{0,1,3}, where the writes to word0 and word1 redefine the start and end addresses respectively and the write to word3 re-enables the region descri ptor valid bit. in many situati ons, all four words of the region descriptor would be rewritten. 4. typically, references to the mpu?s programming m odel would be restricted to supervisor mode accesses from a specific processor(s) , so a region descriptor would be specifically allocated for this purpose with attempted accesse s from other masters or while in user mode terminated with an error. 5. when the mpu detects an access error, the curren t ahb bus cycle is terminated with an error response and information on the faulting reference captured in the mpu_earn and mpu_edrn registers. the error-terminated ahb bus cycle typical ly initiates some type of error response in the originating bus master. for example, a proce ssor core may respond with a bus error exception, while a data movement bus master may respond with an error interr upt. in any event, the processor can retrieve the captured error address and detail information simply be reading the mpu_e{a,d}rn registers. information on which er ror registers contain ca ptured fault data is signaled by mpu_cesr[sperr].
pxd20 microcontroller reference manual, rev. 1 28-20 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-1 preliminary?subject to change without notice chapter 29 mode entry module (mc_me) 29.1 introduction 29.1.1 overview the mc_me controls the soc mode and mode transition sequences in all f unctional states. it also contains configuration, control and status re gisters accessible for the application. figure 29-1 depicts the mc_me block diagram.
pxd20 microcontroller reference manual, rev. 1 29-2 freescale semiconductor preliminary?subject to change without notice figure 29-1. mc_me block diagram registers platform interface cpu mc_me mc_rgm fxosc fmpll0 fmpll1 firc mc_cgm mc_pcu peripherals flash vreg device mode state machine wkpu
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-3 preliminary?subject to change without notice 29.1.2 features the mc_me includes the following features: ? control of the available modes by the me_me register ? definition of various device mode configurations by the me_ _mc registers ? control of the actual device mode by the me_mctl register ? capture of the current mode and various resource status within the conten ts of the me_gs register ? optional generation of variou s mode transi tion interrupts ? status bits for each cause of invalid mode transitions ? peripheral clock gating control ba sed on the me_run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers ? capture of current peripheral clock gated/enabled status 29.1.3 modes of operation the mc_me is based on several device modes corres ponding to different usage models of the device. each mode is configurable and ca n define a policy for energy and pr ocessing power management to fit particular system requirements. an application can easily switch fr om one mode to another depending on the current needs of the system. the operating modes controlled by the mc_me are divided into system and user modes. the system modes are modes such as reset, drun, safe, and test. these modes aim to ease the configurat ion and monitoring of the system. the user modes ar e modes such as run0?3, halt, stop, and standby which can be configured to meet the app lication requirements in terms of energy management and av ailable processing power. the mode s drun, safe, test, and run0?3 are the device software running modes. table 29-1 describes the mc_me modes. table 29-1. mc_me mode descriptions name description entry exit reset this is a chip-wide virtual mode during which the application is not ac tive. the system rema ins in this mode until all resources are available for the embedded software to take control of the device. it manages hardware initialization of chip configuration, voltage regulators, clock sources, and flash modules. system reset assertion from mc_rgm system reset deassertion from mc_rgm drun this is the entry mode for the embedded software. it provides full accessibility to the system and enables the configuration of the system at startup. it provides the unique gate to enter user modes. bam when present is executed in drun mode. system reset deassertion from mc_rgm, software request from safe, test and run0?3, wakeup request from standby system reset assertion, run0?3, test, standby via software, safe via software or hardware failure.
pxd20 microcontroller reference manual, rev. 1 29-4 freescale semiconductor preliminary?subject to change without notice 29.2 external signal description the mc_me has no connectio ns to any external pins . 29.3 memory map and register definition the mc_me contains registers for: ? mode selection and status reporting ? mode configuration ? mode transition interrupts status and mask control ? scalable number of peripheral sub-m ode selection and status reporting safe this is a chip-wide service mode which may be entered on the detection of a recoverable error. it forces the system into a pre-defined safe configuration from which the system may try to recover. hardware failure, software request from drun, test, and run0?3 system reset assertion, drun via software test this is a chip-wide service mode which is intended to provide a control environment for device software teting. software request from drun system reset assertion, drun via software run0?3 these are software running modes where most processing activity is done. these various run modes allow to enable different clock & power config urations of the system with respect to each other. software request from drun or other run0?3, interrupt event from halt, interrupt or wakeup event from stop system reset assertion, safe via software or hardware failure, other run0?3 modes, halt, stop, standby via software halt this is a reduced-activity low-power mode during which the clock to the cpu is disabled. it can be configured to switch off analog peripherals like clock sources, flash, main regulator, etc. for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event stop this is an advanced low-power mode during which the clock to the cpu is disabled. it may be configured to switch off most of the peripherals including clock sources for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event or wakeup event standby this is a reduced-leakage low-power mode during which power supply is cut off from most of the device. wakeup from this mode takes a relative ly long time, and content is lost or must be restored from backup. software request from run0?3, drun modes system reset assertion, drun on wakeup event table 29-1. mc_me mode descriptions (continued) name description entry exit
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-5 preliminary?subject to change without notice 29.3.1 memory map table 29-2. mc_me register description address name description size access location user supervisor 0xc3fd_ c000 me_gs global status word read read on page 29-15 0xc3fd_ c004 me_mctl mode control word read read/write on page 29-17 0xc3fd_ c008 me_me mode enable word read read/write on page 29-18 0xc3fd_ c00c me_is interrupt stat us word read read/write on page 29-19 0xc3fd_ c010 me_im interrupt mask word read read/write on page 29-20 0xc3fd_ c014 me_imts invalid mode transition status word read read/write on page 29-21 0xc3fd_ c018 me_dmts debug mode transition status word read read on page 29-22 0xc3fd_ c020 me_reset_mc reset mode configuration word read read on page 29-25 0xc3fd_ c024 me_test_mc test mode configuration word read read/write on page 29-25 0xc3fd_ c028 me_safe_mc safe mode configuration word read read/write on page 29-26 0xc3fd_ c02c me_drun_mc drun mode configuration word read read/write on page 29-26 0xc3fd_ c030 me_run0_mc run0 mode configuration word read read/write on page 29-27 0xc3fd_ c034 me_run1_mc run1 mode configuration word read read/write on page 29-27 0xc3fd_ c038 me_run2_mc run2 mode configuration word read read/write on page 29-27 0xc3fd_ c03c me_run3_mc run3 mode configuration word read read/write on page 29-27 0xc3fd_ c040 me_halt_mc halt mode configuration word read read/write on page 29-27 0xc3fd_ c048 me_stop_mc stop mode configuration word read read/write on page 29-28 0xc3fd_ c054 me_standby_mc standby mode configuration word read read/write on page 29-28 0xc3fd_ c060 me_ps0 peripheral status 0 word read read on page 29-30
pxd20 microcontroller reference manual, rev. 1 29-6 freescale semiconductor preliminary?subject to change without notice 0xc3fd_ c064 me_ps1 peripheral status 1 word read read on page 29-30 0xc3fd_ c068 me_ps2 peripheral status 2 word read read on page 29-31 0xc3fd_ c06c me_ps3 peripheral status 3 word read read on page 29-31 0xc3fd_ c080 me_run_pc0 run peripheral configuration 0 word read read/write on page 29-32 0xc3fd_ c084 me_run_pc1 run peripheral configuration 1 word read read/write on page 29-32 ? 0xc3fd_ c09c me_run_pc7 run peripheral configuration 7 word read read/write on page 29-32 0xc3fd_ c0a0 me_lp_pc0 low-power peripheral configuration 0 word read read/write on page 29-33 0xc3fd_ c0a4 me_lp_pc1 low-power peripheral configuration 1 word read read/write on page 29-33 ? 0xc3fd_ c0bc me_lp_pc7 low-power peripheral configuration 7 word read read/write on page 29-33 0xc3fd_ c0c4 me_pctl4 dspi0 control byte read read/write on page 29-33 0xc3fd_ c0c5 me_pctl5 dspi1 control byte read read/write on page 29-33 0xc3fd_ c0c6 me_pctl6 dspi2 control byte read read/write on page 29-33 0xc3fd_ c0c8 me_pctl8 quadspi control byte read read/write on page 29-33 0xc3fd_ c0d0 me_pctl16 flexcan0 control byte read read/write on page 29-33 0xc3fd_ c0d1 me_pctl17 flexcan1 control byte read read/write on page 29-33 0xc3fd_ c0d2 me_pctl18 flexcan2 control byte read read/write on page 29-33 0xc3fd_ c0d7 me_pctl23 dma_ch_mux control byte read read/write on page 29-33 0xc3fd_ c0df me_pctl31 bam control byte read read/write on page 29-33 table 29-2. mc_me register description (continued) address name description size access location user supervisor
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-7 preliminary?subject to change without notice 0xc3fd_ c0e0 me_pctl32 adc0 control byte read read/write on page 29-33 0xc3fd_ c0e5 me_pctl37 rle control byte read read/write on page 29-33 0xc3fd_ c0e9 me_pctl41 viu control byte read read/write on page 29-33 0xc3fd_ c0ea me_pctl42 dram controller control byte read read/write on page 29-33 0xc3fd_ c0ec me_pctl44 i2c_dma0 control byte read read/write on page 29-33 0xc3fd_ c0ed me_pctl45 i2c_dma1 control byte read read/write on page 29-33 0xc3fd_ c0ee me_pctl46 i2c_dma2 control byte read read/write on page 29-33 0xc3fd_ c0ef me_pctl47 i2c_dma3 control byte read read/write on page 29-33 0xc3fd_ c0f0 me_pctl48 linflex0 control byte read read/write on page 29-33 0xc3fd_ c0f1 me_pctl49 linflex1 control byte read read/write on page 29-33 0xc3fd_ c0f2 me_pctl50 linflex2 control byte read read/write on page 29-33 0xc3fd_ c0f3 me_pctl51 linflex3 control byte read read/write on page 29-33 0xc3fd_ c0f4 me_pctl52 gfx2d control byte read read/write on page 29-33 0xc3fd_ c0f5 me_pctl53 gxg control byte read read/write on page 29-33 0xc3fd_ c0f6 me_pctl54 dculite control byte read read/write on page 29-33 0xc3fd_ c0f7 me_pctl55 dcu3 control byte read read/write on page 29-33 0xc3fd_ c0f8 me_pctl56 gaugedriver control byte read read/write on page 29-33 0xc3fd_ c0fc me_pctl60 cansampler control byte read read/write on page 29-33 0xc3fd_ c0fe me_pctl62 sgm control byte read read/write on page 29-33 table 29-2. mc_me register description (continued) address name description size access location user supervisor
pxd20 microcontroller reference manual, rev. 1 29-8 freescale semiconductor preliminary?subject to change without notice note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error 0xc3fd_ c0ff me_pctl63 tcon control byte read read/write on page 29-33 0xc3fd_ c102 me_pctl66 cflash0 control byte read read/write on page 29-33 0xc3fd_ c104 me_pctl68 siul control byte read read/write on page 29-33 0xc3fd_ c108 me_pctl72 emios0 control byte read read/write on page 29-33 0xc3fd_ c109 me_pctl73 emios1 control byte read read/write on page 29-33 0xc3fd_ c11b me_pctl91 rtc_api control byte read read/write on page 29-33 0xc3fd_ c11c me_pctl92 pit_rti control byte read read/write on page 29-33 0xc3fd_ c128 me_pctl104 cmu0 control byte read read/write on page 29-33 table 29-3. mc_me memory map address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fd _c000 me_gs r s_current_mode s_mtrans s_dc 00 s_pdo 00 s_mvr s_fla w r0 0 0 0 0000 s_fmpll1 s_fmpll0 s_fxosc s_firc s_sysclk w table 29-2. mc_me register description (continued) address name description size access location user supervisor
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-9 preliminary?subject to change without notice 0xc3fd _c004 me_mctl r ta r g e t _ m o d e 0000000 00000 w r1 0 1 0 0101000 01111 w key 0xc3fd _c008 me_me r0 0 0 0 0000000 00000 w r0 0 standby 00 stop 0 halt run3 run2 run1 run0 drun safe test reset w 0xc3fd _c00c me_is r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c 0xc3fd _c010 me_im r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 m_iconf m_imode m_safe m_mtc w 0xc3fd _c014 me_imts r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c table 29-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 29-10 freescale semiconductor preliminary?subject to change without notice 0xc3fd _c018 me_dmts rprevious_mode 0000 mph_busy 00 pmc_prog core_dbg 00 smr w r0 vreg_csrc_sc csrc_csrc_sc firc_sc scsrc_sc sysclk_sw cflash_sc cdp_prph_0_143 00 cdp_prph_96_127 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w 0xc3fd _c01c reserved 0xc3fd _c020 me_reset_ mc r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c024 me_test_m c r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w table 29-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-11 preliminary?subject to change without notice 0xc3fd _c028 me_safe_m c r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c02c me_drun_m c r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c030 ? 0xc3fd _c03c me_run0?3 _mc r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c040 me_halt_m c r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c044 reserved table 29-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 29-12 freescale semiconductor preliminary?subject to change without notice 0xc3fd _c048 me_stop_m c r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c04c ? 0xc3fd _c050 reserved 0xc3fd _c054 me_standb y_mc r0 0 0 0 0000 pdo 00 mvron flaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd _c058 ? 0xc3fd _c05c reserved 0xc3fd _c060 me_ps0 r s_bam 0 0 0 0000 s_dma_ch_mux 00 0 0 s_flexcan2 s_flexcan1 s_flexcan0 w r0 0 0 0 000 s_quadspi 00000000 w table 29-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-13 preliminary?subject to change without notice 0xc3fd _c064 me_ps1 r s_tcon s_sgm 0 0 000 s_gaugedriver s_dcu3 s_dculite s_gxg s_gfx2d s_linflex3 s_linflex2 s_linflex1 s_linflex0 w r s_i2c_dma3 s_i2c_dma2 s_i2c_dma1 s_i2c_dma0 0 s_dram controller s_viu 000 s_rle 0000 s_adc0 w 0xc3fd _c068 me_ps2 r0 0 0 s_pit_rti s_rtc_api s_mc_pcu s_mc_rgm s_mc_cgm s_mc_me s_sscm 000000 w r0 0 0 0 00 s_emios1 s_emios0 00 s_wkpu s_siul 0 s_cflash0 00 w 0xc3fd _c06c me_ps3 r0 0 0 0 0000000 00000 w r0 0 0 0 000 s_cmu0 00000000 w 0xc3fd _c070 reserved 0xc3fd _c074 ? 0xc3fd _c07c reserved table 29-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 29-14 freescale semiconductor preliminary?subject to change without notice 29.3.2 register description unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered accor ding to big endian. for example, the me_run_pc0 register may be accessed as a word at address 0xc3fd_c080, as a half-word at address 0xc3f d_c082, or as a byte at address 0xc3fd_c083. 0xc3fd _c080 ? 0xc3fd _c09c me_run_pc 0?7 r0 0 0 0 0000000 00000 w r0 0 0 0 0000 run3 run2 run1 run0 drun safe test reset w 0xc3fd _c0a0 ? 0xc3fd _c0bc me_lp_pc0 ?7 r0 0 0 0 0000000 00000 w r0 0 standby 00 stop 0 halt 00000000 w 0xc3fd _c0c0 ? 0xc3fd _c14c me_pctl0? 143 r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w 0xc3fd _c150 ? 0xc3fd _fffc reserved table 29-3. mc_me memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-15 preliminary?subject to change without notice 29.3.2.1 global status register (me_gs) this register contains global mode status. address 0xc3fd_c000 access: user read, supervisor read, test read 0123456789101112131415 r s_current_mode s_mtrans s_dc 00 s_pdo 00 s_mvr s_fla w reset0000110000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 s_fmpll1 s_fmpll0 s_fxosc s_firc s_sysclk w reset0000000000010000 figure 29-2. global status register (me_gs) table 29-4. global status register (me_gs) field descriptions field description s_curren t_mode current device mode status 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reserved s_mtrans mode transition status 0 mode transition process is not active 1 mode transition is ongoing s_dc device current consumption status 0 device consumption is low enough to allow powering down of main voltage regulator 1 device consumption requires main voltage regul ator to remain powered regardless of mode configuration
pxd20 microcontroller reference manual, rev. 1 29-16 freescale semiconductor preliminary?subject to change without notice s_pdo output power-down status ? this bit specifies output power-down status of i/os. this bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1in safe / test modes, outputs of pads are forced to high impedance state and the pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only the pad power sequence driver is disabled, but the stat e of the output remains functional. in standby mode, the power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. wakeup li nes configuration remains unchanged s_mvr main voltage regulator status 0 main voltage regulator is not ready 1 main voltage regulator is ready for use s_fla flash memory availability status 00 flash memory is not available 01 flash memory is in power-down mode 10 flash memory is in low-power mode 11 flash memory is in normal mode and available for use s_ssclk1 secondary system clock source 1 status 0 secondary system clock source 1 is not stable 1 secondary system clock source 1 is providing a stable clock s_fmpll1 secondary frequency modulate d phase locked loop status 0 secondary frequency modulated phase locked loop is not stable 1 secondary frequency modulated phase locked loop is providing a stable clock s_fmpll0 primary frequency modulated phase locked loop status 0 primary frequency modulated phase locked loop is not stable 1 primary frequency modulated phase locked loop is providing a stable clock s_fxosc fast external crystal oscillator (4-16 mhz) status 0 fast external crystal oscillator (4-16 mhz) is not stable 1 fast external crystal oscillator (4-16 mhz) is providing a stable clock s_firc fast internal rc oscillator (16 mhz) status 0 fast internal rc oscillator (16 mhz) is not stable 1 fast internal rc oscillator (16 mhz) is providing a stable clock s_sysclk system clock switch status ? these bits specify the system clock currently used by the system. 0000 16 mhz int. rc osc. 0001 reserved 0010 reserved 0011 div. 4-16 mhz ext. xtal osc. 0100 primary pll/2 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled table 29-4. global status register (me_gs) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-17 preliminary?subject to change without notice 29.3.2.2 mode control register (me_mctl) this register is used to trigger software-controlle d mode changes. depending on the modes as enabled by me_me register bits, configurati ons corresponding to unavailable mo des are reserved and access to me_ _mc registers must respect this for successful mode requests. note byte and half-word write accesses are not allowed fo r this register as a predefined key is required to change its value. address 0xc3fd_c004 access: user read, super visor read/write, test read/write 0123456789101112131415 r ta r g e t _ m o d e 000000000000 w reset0011000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1010010100001111 w key reset1010010100001111 figure 29-3. mode control register (me_mctl) table 29-5. mode control register (me_mctl) field descriptions field description ta r g e t _ m ode target device mode ? these bits provide the target device mode to be entered by software programming. the mechanism to ente r into any mode by software requires the write operation twice: first time with key, and second time with inverted key. these bits are automatically updated by hardware while entering safe on hardware request. also, while exiting from the halt and stop modes on hardware exit events, these are updated with the appropriate run0?3 mode value. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reset (destructive) key control key ? these bits enable write access to this re gister. any write access to the register with a value different from the keys is ignored. read access will always return inverted key. key:0101101011110000 (0x5af0) inverted key:1010010100001111 (0xa50f)
pxd20 microcontroller reference manual, rev. 1 29-18 freescale semiconductor preliminary?subject to change without notice 29.3.2.3 mode enable register (me_me) this register allows a way to di sable the device modes which are not required for a given device. reset, safe, drun, and run0 m odes are always enabled. address 0xc3fd_c008 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 standby 00 stop 0 halt run3 run2 run1 run0 drun safe test reset w reset0000000000011111 figure 29-4. mode enable register (me_me) table 29-6. mode enable register (me_me) field descriptions field description standby standby mode enable 0 standby mode is disabled 1 standby mode is enabled stop stop mode enable 0 stop mode is disabled 1 stop mode is enabled halt halt mode enable 0 halt mode is disabled 1 halt mode is enabled run3 run3 mode enable 0 run3 mode is disabled 1 run3 mode is enabled run2 run2 mode enable 0 run2 mode is disabled 1 run2 mode is enabled run1 run1 mode enable 0 run1 mode is disabled 1 run1 mode is enabled run0 run0 mode enable 0 run0 mode is disabled 1 run0 mode is enabled drun drun mode enable 0 drun mode is disabled 1 drun mode is enabled safe safe mode enable 0 safe mode is disabled 1 safe mode is enabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-19 preliminary?subject to change without notice 29.3.2.4 interrupt status register (me_is) this register provides the current interrupt status. test test mode enable 0 test mode is disabled 1 test mode is enabled reset reset mode enable 0 reset mode is disabled 1 reset mode is enabled address 0xc3fd_c00c access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c reset0000000000000000 figure 29-5. interrupt status register (me_is) table 29-7. interrupt status register (me_is) field descriptions field description i_iconf_cu invalid mode configuration interrupt (clock usage) ? this bit is set during a mode transition if a clock which is required to be on by an enabled peripheral is configured to be turned off. it is cleared by writing a ?1? to this bit. 0 no invalid mode configuration (clock usage) interrupt occurred 1 invalid mode configuration (clock usage) interrupt is pending i_iconf invalid mode configuration interrupt ? this bit is set whenever a write operation to me_< mode >_mc registers with invalid mode configuration is attempted. it is cleared by writing a ?1? to this bit. 0 no invalid mode configuration interrupt occurred 1 invalid mode configuration interrupt is pending i_imode invalid mode interrupt ? this bit is set whenever an invalid mode transition is requested. it is cleared by writing a ?1? to this bit. 0 no invalid mode interrupt occurred 1 invalid mode interrupt is pending table 29-6. mode enable register (me_me) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 29-20 freescale semiconductor preliminary?subject to change without notice 29.3.2.5 interrupt mask register (me_im) this register controls whether an event generates an interrupt or not. i_safe safe mode interrupt ? this bit is set whenever the device enters safe mode on hardware requests generated in the system. it is cleared by writing a ?1? to this bit. 0 no safe mode interrupt occurred 1 saf e mode interrupt is pending i_mtc mode transition complete interrupt ? this bit is set whenever the mode transition process completes (s_mtrans transits from 1 to 0). it is cleared by writing a ?1? to this bit. this mode transition interrupt bit will not be set while entering low-power modes halt, stop, or standby. 0 no mode transition complete interrupt occurred 1 mode transition complete interrupt is pending address 0xc3fd_c010 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000 m_iconf_cu m_iconf m_imode m_safe m_mtc w reset0000000000000000 figure 29-6. interrupt mask register (me_im) table 29-8. interrupt mask register (me_im) field descriptions field description m_iconf_cu invalid mode configuration interrupt (clock usage) mask 0 invalid mode configuration (clock usage) interrupt is masked 1 invalid mode configuration (clock usage) is enabled m_iconf invalid mode configuration interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_imode invalid mode interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_safe safe mode interrupt mask 0 safe mode interrupt is masked 1 safe mode interrupt is enabled m_mtc mode transition comp lete interrupt mask 0 mode transition complete interrupt is masked 1 mode transition complete interrupt is enabled table 29-7. interrupt status register (me_is) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-21 preliminary?subject to change without notice 29.3.2.6 invalid mode transiti on status register (me_imts) this register provides the stat us bits for the possible causes of an invalid mode interrupt. address 0xc3fd_c014 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c reset0000000000000000 figure 29-7. invalid mode transition status register (me_imts) table 29-9. invalid mode transition status register (me_imts) field descriptions field description s_mti mode transition illegal status ? this bit is set whenever a new mode is requested while some other mode transition process is active (s_mtrans is ?1?). please refer to section 29.4.5, mode transition interrupts , for the exceptions to this behavior. it is cleared by writing a ?1? to this bit. 0 mode transition requested is not illegal 1 mode transition requested is illegal s_mri mode request illegal status ? this bit is set whenever the target mode requested is not a valid mode with respect to current mode. it is cleared by writing a ?1? to this bit. 0 target mode requested is not ille gal with respect to current mode 1 target mode requested is illegal with respect to current mode s_dma disabled mode access status ? this bit is set whenever the target mode requested is one of those disabled modes determined by me_me register. it is cleared by writing a ?1? to this bit. 0 target mode requested is not a disabled mode 1 target mode requested is a disabled mode s_nma non-existing mode access status ? this bit is set whenever the target mode requested is one of those non existing modes determined by me_me regist er. it is cleared by writing a ?1? to this bit. 0 target mode request ed is an existing mode 1 target mode requested is a non-existing mode s_sea safe event active status ? this bit is set whenever the device is in safe mode, safe event bit is pending and a new mode request ed other than reset/safe modes. it is cleared by writing a ?1? to this bit. 0 no new mode requested other than reset/safe while safe event is pending 1 new mode requested other than reset/safe while safe event is pending
pxd20 microcontroller reference manual, rev. 1 29-22 freescale semiconductor preliminary?subject to change without notice 29.3.2.7 debug mode transition status register (me_dmts) this register provides the status of different factors which influence mode transitions. it is used to give an indication of why a mode tran sition indicated by me_gs.s_mtra ns may be taking longer than expected. note the me_dmts register does not indi cate whether a mode transition is ongoing. therefore, some me_dmts bits may still be asserted after the mode transition has completed. address 0xc3fd_c018 access: user read, super visor read/write, test read/write 0123456789101112131415 r previous_mode 0 0 0 0 mph_busy 00 pmc_prog core_dbg 00 smr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 vreg_csrc_sc csrc_csrc_sc firc_sc scsrc_sc sysclk_sw cflash_sc cdp_prph_0_143 0000 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w reset0000000000000000 figure 29-8. debug mode transition status register (me_dmts)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-23 preliminary?subject to change without notice table 29-10. debug mode transition status register (me_dmts) field descriptions field description previous_ mode previous device mode ? these bits show the mode in which the device was prior to the latest change to the current mode. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reserved mph_busy mc_me/mc_pcu handshake busy indicator ? this bit is set if the mc_me has requested a mode change from the mc_pcu and the mc_pcu has not yet responded. it is cleared when the mc_pcu has responded. 0 handshake is not busy 1 handshake is busy pmc_prog mc_pcu mode change in progress indicator ? this bit is set if the mc_pcu is in the process of powering up or down power domains. it is cleared when all power-up/down processes have completed. 0 power-up/down transition is not in progress 1 power-up/down transition is in progress core_dbg processor is in debug mode indicator ? this bit is set while the processor is in debug mode. 0 the processor is not in debug mode 1 the processor is in debug mode smr safe mode request from mc_rgm is active indica tor ? this bit is set if a hardware safe mode request has been triggered. it is cleared when the hardware safe mode request has been cleared. 0 a safe mode request is not active 1 a safe mode request is active vreg_csr c_sc main vreg dependent clock source state change during mode transition indicator ? this bit is set when a clock source which depends on the main voltage regulator to be powered-up is requested to change its power up/down state. it is cleared when the clock source has co mpleted its state change. 0 no state change is taking place 1 a state change is taking place csrc_csr c_sc (other) clock source dependent clock source state change during mode transition indicator ? this bit is set when a clock source which depends on ano ther clock source to be powered-up is requested to change its power up/down state. it is cleared when the clock source has completed its state change. 0 no state change is taking place 1 a state change is taking place firc_sc firc state change during mode transition indicator ? this bit is set when the fast internal rc oscillator (16 mhz) is requested to change its power up/down state. it is clear ed when the fast internal rc oscillator (16 mhz) has completed its state change. 0 no state change is taking place 1 a state change is taking place
pxd20 microcontroller reference manual, rev. 1 29-24 freescale semiconductor preliminary?subject to change without notice scsrc_sc secondary clock sources state change during mode transition indicator ? this bit is set when a secondary clock source is requested to change its power up/down state. it is cleared when all secondary system clock sources have completed thei r state changes. (a ?secondary clock source? is a clock source other than firc.) 0 no state change is taking place 1 a state change is taking place sysclk_s w system clock switching pending status ? 0 no system clock source switching is pending 1 a system clock source switching is pending cflash_sc cflash state change during mode transition indicator ? this bit is set when the cflash is requested to change its power up/down state. it is cleared when the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cdp_prph _0_143 clock disable process pending status for peripherals 0?143 ? this bit is set when any peripheral has been requested to have its clock disabled. it is cleared when all the peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _96_127 clock disable process pending status for peripherals 96?127 ? this bit is set when any peripheral appearing in me_ps3 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _64_95 clock disable process pending status for peripherals 64?95 ? this bit is set when any peripheral appearing in me_ps2 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _32_63 clock disable process pending status for peripherals 32?63 ? this bit is set when any peripheral appearing in me_ps1 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _0_31 clock disable process pending status for peripherals 0?31 ? this bit is set when any peripheral appearing in me_ps0 has been requested to have it s clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral table 29-10. debug mode transition status regi ster (me_dmts) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-25 preliminary?subject to change without notice 29.3.2.8 reset mode configur ation register (me_reset_mc) this register configures system behavior during reset mode. please refer to table 29-11 for details. 29.3.2.9 test mode configuration regi ster (me_test_mc) this register configures system beha vior during test mode. please refer to table 29-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c020 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron 00 flaon w reset0000000000010011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-9. reset mode confi guration register (me_reset_mc) address 0xc3fd_c024 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000 pdo 00 mvron 00 flaon w reset0000000000010011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-10. test mode configuration register (me_test_mc)
pxd20 microcontroller reference manual, rev. 1 29-26 freescale semiconductor preliminary?subject to change without notice 29.3.2.10 safe mode configur ation register (me_safe_mc) this register configures system behavi or during safe mode. please refer to table 29-11 for details. note byte write accesses are not allowed to this register. 29.3.2.11 drun mode configuration register (me_drun_mc) this register configures system beha vior during drun mode. please refer to table 29-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c028 access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000 pdo 00 mvron 00 flaon w reset0000000010010011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-11. safe mode confi guration register (me_safe_mc) address 0xc3fd_c02c access: user read, super visor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron 00 flaon w reset0000000000010011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-12. drun mode configuration register (me_drun_mc)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-27 preliminary?subject to change without notice note the clock source and flash configur ation values are retained through standby mode. 29.3.2.12 run0?3 mode conf iguration registers (me_run0 ? 3_mc) this register configures system behavior during run 0?3 modes. please refer to table 29-11 for details. note byte write accesses are not allowed to this register. 29.3.2.13 halt mode configurat ion register (me_halt_mc) this register configures system beha vior during halt mode. please refer to table 29-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c030 - 0xc3fd_c03c access: user read, supervisor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron 00 flaon w reset0000000000010011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-13. run0?3 mode confi guration registers (me_run0?3_mc) address 0xc3fd_c040 access: user read, super visor read/write, test read/write 0123456789101112131415 r00000000pdo00 mvron 00 flaon w reset0000000000010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-14. halt mode configuration register (me_halt_mc)
pxd20 microcontroller reference manual, rev. 1 29-28 freescale semiconductor preliminary?subject to change without notice 29.3.2.14 stop mode configur ation register (me_stop_mc) this register configures system behavi or during stop mode. please refer to table 29-11 for details. note byte write accesses are not allowed to this register. 29.3.2.15 standby mode configur ation register (me_standby_mc) this register configures system behavi or during standby mode . please refer to table 29-11 for details. note byte write accesses are not allowed to this register. address 0xc3fd_c048 access: user read, super visor read/write, test read/write 0123456789101112131415 r00000000 pdo 00 mvron 00 flaon w reset0000000000010001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 29-15. stop mode configuration register (me_stop_mc) address 0xc3fd_c054 access: user read, supervisor read/write, test read/write 0123456789101112131415 r 00000000pdo00 mvron 00 flaon w reset0000000010000001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000011111 figure 29-16. standby mode confi guration register (me_standby_mc)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-29 preliminary?subject to change without notice table 29-11. mode configuration registers (me_< mode >_mc) field descriptions field description pdo i/o output power-down control ? this bit controls the output power-down of i/os. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are fo rced to high impedance state and pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only the pad power sequence driver is disabled, but the state of th e output remains functional. in standby mode, power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance. wakeup line configuration remains unchanged mvron main voltage regulator control ? this bit specifies whether main voltage regulator is switched off or not while entering this mode. 0 main voltage regulator is switched off 1 main voltage regulator is switched on flaon flash memory power-down control ? this bit specifies the operating mode of the code flash after entering this mode. 00 reserved 01 flash memory is in power-down mode 10 flash memory is in low-power mode 11 flash memory is in normal mode fmpll1on secondary frequency modulated phase locked loop control 0 secondary frequency modulated phase locked loop is switched off 1 secondary frequency modulated phase locked loop is switched on fmpll0on primary frequency modulated phase locked loop control 0 primary frequency modulated phase locked loop is switched off 1 primary frequency modulated phase locked loop is switched on fxoscon fast external crystal oscillator (4-16 mhz) control 0 fast external crystal oscillator (4-16 mhz) is switched off 1 fast external crystal oscillator (4-16 mhz) is switched on fircon fast internal rc oscillator (16 mhz) control 0 fast internal rc oscillator (16 mhz) is switched off 1 fast internal rc oscillator (16 mhz) is switched on sysclk system clock switch control ? these bits specify the system clock to be used by the system. 0000 16 mhz int. rc osc. 0001 reserved 0010 reserved 0011 div. 4-16 mhz ext. xtal osc. 0100 primary pll/2 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled in stop and test modes, reserved in all other modes
pxd20 microcontroller reference manual, rev. 1 29-30 freescale semiconductor preliminary?subject to change without notice 29.3.2.16 peripheral status register 0 (me_ps0) this register provides the status of the peripherals. please refer to table 29-12 for details. 29.3.2.17 peripheral status register 1 (me_ps1) this register provides the status of the peripherals. please refer to table 29-12 for details. address 0xc3fd_c060 access: user read, supervisor read, test read 0123456789101112131415 r s_bam 0000000 s_dma_ch_mux 0000 s_flexcan2 s_flexcan1 s_flexcan0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 s_quadspi 0 s_dspi2 s_dspi1 s_dspi0 0000 w reset0000000000000000 figure 29-17. peripheral status register 0 (me_ps0) address 0xc3fd_c064 access: user read, supervisor read, test read 0123456789101112131415 r s_tcon s_sgm 0 s_cansampler 000 s_gaugedriver s_dcu3 s_dculite s_gxg s_gfx2d s_linflex3 s_linflex2 s_linflex1 s_linflex0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_i2c_dma3 s_i2c_dma2 s_i2c_dma1 s_i2c_dma0 000000 s_rle 0000 s_adc0 w reset0000000000000000 figure 29-18. peripheral status register 1 (me_ps1)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-31 preliminary?subject to change without notice 29.3.2.18 peripheral status register 2 (me_ps2) this register provides the status of the peripherals. please refer to table 29-12 for details. 29.3.2.19 peripheral status register 3 (me_ps3) this register provides the status of the peripherals. please refer to table 29-12 for details. address 0xc3fd_c068 access: user read, supervisor read, test read 0123456789101112131415 r 000 s_pit_rti s_rtc_api s_mc_pcu s_mc_rgm s_mc_cgm s_mc_me s_sscm 000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 s_emios1 s_emios0 00 s_wkpu s_siul 0 s_cflash0 00 w reset0000000000000000 figure 29-19. peripheral status register 2 (me_ps2) address 0xc3fd_c06c access: user read, supervisor read, test read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 s_cmu0 00000000 w reset0000000000000000 figure 29-20. peripheral status register 3 (me_ps3)
pxd20 microcontroller reference manual, rev. 1 29-32 freescale semiconductor preliminary?subject to change without notice 29.3.2.20 run peripheral configuration registers (me_run_pc0 ? 7) these registers configure eight different t ypes of peripheral behavior during run modes. table 29-12. peripheral status registers 0?4 (me_ps0?4) field descriptions field description s_ peripheral status ? these bits specify the cu rrent status of the periph erals in the system. if no peripheral is mapped on a particular position (i.e., the corresponding mods bit is ?0?), the corresponding bit is always read as ?0?. 0 peripheral is frozen 1 peripheral is active address 0xc3fd_c080 - 0xc3fd_c09c access: user read, supervisor read/wr ite, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 run3 run2 run1 run0 drun safe test reset w reset0000000000000000 figure 29-21. run peripheral config uration registers (me_run_pc0?7) table 29-13. run peripheral configuration re gisters (me_run_pc0?7) field descriptions field description run3 peripheral control during run3 0 peripheral is frozen with clock gated 1 peripheral is active run2 peripheral control during run2 0 peripheral is frozen with clock gated 1 peripheral is active run1 peripheral control during run1 0 peripheral is frozen with clock gated 1 peripheral is active run0 peripheral control during run0 0 peripheral is frozen with clock gated 1 peripheral is active drun peripheral control during drun 0 peripheral is frozen with clock gated 1 peripheral is active safe peripheral control during safe 0 peripheral is frozen with clock gated 1 peripheral is active
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-33 preliminary?subject to change without notice 29.3.2.21 low-power peripheral conf iguration registers (me_lp_pc0 ? 7) these registers configure eight different types of periphera l behavior during non-run modes. 29.3.2.22 peripheral control registers (me_pctl0 ? 143) test peripheral control during test 0 peripheral is frozen with clock gated 1 peripheral is active reset peripheral control during reset 0 peripheral is frozen with clock gated 1 peripheral is active address 0xc3fd_c0a0 - 0xc3fd_c0bc access: user read, supervisor read/wr ite, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 standby 00 stop 0 halt 00000000 w reset0000000000000000 figure 29-22. low-power peripheral configuration registers (me_lp_pc0?7) table 29-14. low-power peripheral configuratio n registers (me_lp_pc0?7) field descriptions field description standby peripheral control during standby 0 peripheral is frozen with clock gated 1 peripheral is active stop peripheral control during stop 0 peripheral is frozen with clock gated 1 peripheral is active halt peripheral control during halt 0 peripheral is frozen with clock gated 1 peripheral is active address 0xc3fd_c0c0 - 0xc3fd_c14f access: user read, supervisor read/wr ite, test read/write 01234567 r 0 dbg_f lp_cfg run_cfg w reset00000000 figure 29-23. peripheral control registers (me_pctl0?143) table 29-13. run peripheral configuration register s (me_run_pc0?7) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 29-34 freescale semiconductor preliminary?subject to change without notice these registers select the conf igurations during run and non-run modes for each peripheral. 29.4 functional description 29.4.1 mode transition request the transition from one mode to another mode is normally handled by software by accessing the mode control register me_mctl. but the in case of special events, the mode transition can be automatically managed by hardware. in order to switch from one mode to another, the application should access the me_mctl register twice by writing ? the first time with the value of the key (0x5af 0) into the key bit field and the required target mode into the targ et_mode bit field, ? and the second time with the inverted value of the key (0xa50f) into the key bit field and the required target mode into the target_mode bit field. once a valid mode transition request is detected, the ta rget mode configuration in formation is loaded from the corresponding me_ _mc register. the mode transition reque st may require a number of cycles depending on the programmed configuration, and so ftware should check the s_current_mode bit field and the s_mtrans bit of the global status re gister me_gs to verify when the mode has been table 29-15. peripheral control registers (me_pctl0?143) field descriptions field description dbg_f peripheral control in debug mode ? this bit controls the state of the peripheral in debug mode 0 peripheral state depends on run_cfg/lp_cfg bits and the device mode 1 peripheral is frozen if not already frozen in device modes. note: this feature is useful to freeze the peripheral state while entering debug. for example, this may be used to prevent a reference timer from running while making a debug accesses. lp_cfg peripheral configuration select for non-run modes ? these bits associate a configuration as defined in the me_lp_pc0 ? 7 registers to the peripheral. 000 selects me_lp_pc0 configuration 001 selects me_lp_pc1 configuration 010 selects me_lp_pc2 configuration 011 selects me_lp_pc3 configuration 100 selects me_lp_pc4 configuration 101 selects me_lp_pc5 configuration 110 selects me_lp_pc6 configuration 111 selects me_lp_pc7 configuration run_cfg peripheral configuration select for run modes ? these bits associate a configuration as defined in the me_run_pc0 ? 7 registers to the peripheral. 000 selects me_run_pc0 configuration 001 selects me_run_pc1 configuration 010 selects me_run_pc2 configuration 011 selects me_run_pc3 configuration 100 selects me_run_pc4 configuration 101 selects me_run_pc5 configuration 110 selects me_run_pc6 configuration 111 selects me_run_pc7 configuration
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-35 preliminary?subject to change without notice correctly entered and the tr ansition process has complete d. for a description of vali d mode requests, please refer to section 29.4.5, mode transition interrupts . any modification of the mode configur ation register of the currently sel ected mode will not be taken into account immediately but on th e next request to enter this mode. th is means that transition requests such as run0?3 ? run0?3, drun ? drun, safe ? safe, and test ? test are considered valid mode transition requests. as soon as the mode request is accepted as valid, the s_mtrans bit is set till the status in the me_gs register matches th e configuration programmed in the respective me_ _mc register. note it is recommended that software poll the s_mtrans bit in the me_gs register after requesting a transiti on to halt, stop, or standby modes. figure 29-24. mc_me mode diagram 29.4.2 modes details 29.4.2.1 reset mode the device enters this m ode on the following events: ? from safe, drun, run0?3, or test mode wh en the target_mode bit field of the me_mctl register is written with ?0000? safe drun test reset run0 run1 halt stop system modes user modes software request non-recoverable failure run2 run3 recoverable hardware failure standby
pxd20 microcontroller reference manual, rev. 1 29-36 freescale semiconductor preliminary?subject to change without notice ? from any mode due to a system reset by the mc _rgm because of some non-recoverable hardware failure in the system (see the mc_rgm chapter for details) transition to this mode is instantaneous, and the syst em remains in this mode until the reset sequence is finished. the mode configuration information for th is mode is provided by the me_reset_mc register. this mode has a pre-defined configur ation, and the 16 mhz int. rc osc. is selected as the system clock. all power domains are made active in this mode. 29.4.2.2 drun mode the device enters this m ode on the following events: ? automatically from reset mode after completion of the reset sequence ? from run0?3, safe, or test mode when th e target_mode bit field of the me_mctl register is written with ?0011? ? from the standby mode after an external wakeup event or internal wakeup alarm (e.g., rtc/api event) as soon as any of the above events has occurred, a drun mode transi tion request is generated. the mode configuration information for this mode is provid ed by the me_drun_mc register. in this mode, the flash, all clock sources, and the system clock configuration can be contro lled by software as required. after system reset, the software execution starts with the default configurati on selecting the 16 mhz int. rc osc. as the system clock. this mode is intended to be used by software ? to initialize all registers as per the system needs ? to execute small routines in a ?ping-pong? with the standby mode when this mode is entered from standby after a wakeup event, the me_drun_mc register content is restored to its pre-standby values, a nd the mode starts in that configuration. all power domains are active when this mode is en tered due to a system reset sequence initiated by a destructive reset event. in other cases of entry, su ch as the exit from standby after a wakeup event, a functional reset event like an ex ternal reset or a software reque st from run0?3, safe, or test mode, active power domains are determin ed by the power configuration regi ster pcu_pconf2 of the mc_pcu. all power domains except power dom ains #0 and #1 are configurable in this mode (see the mc_pcu chapter for details). note software must ensure that the code executes from ram before changing to this mode if the flash configured to be in the low-power or power-down state in this mode. 29.4.2.3 safe mode the device enters this m ode on the following events: ? from drun, run0?3, or test mode when th e target_mode bit field of the me_mctl register is written with ?0010?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-37 preliminary?subject to change without notice ? from any mode except reset due to a safe mode request generated by the mc_rgm because of some potentially rec overable hardware failure in the sy stem (see the mc_rgm chapter for details) as soon as any of the above events has occurred, a safe m ode transition request is generated. the mode configuration information for this mode is provid ed by the me_safe_mc register. this mode has a pre-defined configuration, a nd the 16 mhz int. rc osc. is selected as the system cloc k. all power domains are made active in this mode. if the safe mode is requested by software while some other mode transitio n process is ongoing, the new target mode becomes the safe mode regardless of other pending requests or new requests during the mode transition. no new mode request made during a tr ansition to the safe mode will cause an invalid mode interrupt. note if software requests to change to th e safe mode and then requests to change back to the parent mode before the mode tr ansition is completed, the device?s final mode after mode tr ansition will be the safe mode. as long as a safe event is active, the system rema ins in the safe mode, and any software mode request during this time is ignored and lost. this mode is intended to be used by software ? to assess the severity of the cause of failure and then to either ? re-initialize the device via the drun mode, or ? completely reset the devi ce via the reset mode. if the outputs of the system i/os n eed to be forced to a high impeda nce state upon entering this mode, the pdo bit of the me_safe_mc register should be set. in this case , the pads? power seque nce driver cell is also disabled. the input levels remain unchanged. 29.4.2.4 test mode the device enters this m ode on the following events: ? from the drun mode when the target_mode bi t field of the me_mctl register is written with ?0001? as soon as any of the above events has occurred, a test mode transition request is generated. the mode configuration information for this mode is provided by the me_test_mc register. except for the main voltage regulator, all resource s of the system are configurable in th is mode. the system clock to the whole system can be stopped by programming th e sysclk bit field to ?1111,? a nd in this case, the only way to exit this mode is via a device reset. this mode is intended to be used by software ? to execute software test routines all power domains except power domai ns #0 and #1 are configurable in this mode. active power domains are determined by the power configurati on register pcu_pconf2 of the mc_pcu.
pxd20 microcontroller reference manual, rev. 1 29-38 freescale semiconductor preliminary?subject to change without notice note software must ensure that the code executes from ram before changing to this mode if the flash configured to be in the low-power or power-down state in this mode. 29.4.2.5 run0?3 modes the device enters one of thes e modes on the following events: ? from the drun, safe, or another run0?3 mode when th e target_mode bit field of the me_mctl register is written with ?0100?0111? ? from the halt mode due to an interrupt event ? from the stop mode due to an interrupt or wakeup event as soon as any of the above events has occurred, a run0?3 mode transition request is generated. the mode configuration information fo r these modes is provided by the me_run0?3_mc registers. in these modes, the flash, all clock sources, and the system cl ock configuration can be c ontrolled by software as required. these modes are intended to be used by software ? to execute application routines all power domains except power dom ains #0 and #1 are configurable in these modes in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. note software must ensure that the code executes from ram before changing to this mode if the flash configured to be in the low-power or power-down state in this mode. 29.4.2.6 halt mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with ?1000.? as soon as any of the above events has occurred, a halt mode transition request is generated. the mode configuration information for this mode is provid ed by me_halt_mc register. this mode is quite configurable, and the me_halt_mc re gister should be programmed acco rding to the system needs. the main voltage regulator and the flash can be put in lo w-power or power-down mode as needed. if there is a halt mode request while an interrupt request is active, the transition to halt is aborted with the resultant mode being the current mode, safe (on sa fe mode request), or drun (on reset), and an invalid mode interrupt is not generated. this mode is intended as a first-level low-power mode with ? the cpu clock frozen
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-39 preliminary?subject to change without notice ? only a few peripherals running and to be used by software ? to wait until it is requi red to do something and then to react quickly (i.e., within a few system clock cycles of an interrupt event) all power domains except power dom ains #0 and #1 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. 29.4.2.7 stop mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with ?1010.? as soon as any of the above events has occurred, a stop mode transition request is generated. the mode configuration information for this mode is provided by the me_stop_mc register. this mode is fully configurable, and the me_stop_mc register should be programmed according to the system needs. the main voltage regulator and the flash can be put in power-down mode as needed. if there is a stop mode request while any interrupt or wakeup event is active, the transi tion to stop is aborted with the resultant mode being the current mode, safe (on sa fe mode request), or drun (on reset), and an invalid mode interrupt is not generated. this can be used as an advanced low-power mode wi th the cpu clock frozen and almost all peripherals stopped. this mode is intended as an advanced low-power mode with ? the system clock frozen ? almost all peripherals stopped and to be used by software ? to wait until it is required to do something with no need to react quickly (e.g., allow for system clock source to be re-started) if the pads? power sequence driver cel l needs to be disabled while ente ring this mode, the pdo bit of the me_stop_mc register should be set. the state of the outputs is kept. this mode can be used to stop all cl ock sources and thus preserve the de vice status. when exiting the stop mode, the fast internal rc oscillator (16 mhz) clock is selected as the system clock until the target clock is available. all power domains except power dom ains #0 and #1 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu.
pxd20 microcontroller reference manual, rev. 1 29-40 freescale semiconductor preliminary?subject to change without notice 29.4.2.8 standby mode the device enters this m ode on the following events: ? from the drun or one of the run0?3 mode s when the target_mode bit field of the me_mctl register is written with ?1101.? as soon as any of the above events occur, a sta ndby mode transition request is generated. the mode configuration information for this mode is provided by the me_standby _mc register. in this mode, the power supply is turned off fo r most of the device. the only parts of the device th at are still powered during this mode are pads mapped on wakeup lines a nd power domain #0 which contains the mc_rgm, mc_pcu, wkpu, 8k ram, rtc/api, cansampler, sirc, firc, and de vice and user option bits. the firc can be optionally switched of f. this is the lowest power cons umption mode possible on the device. this mode is intended as an extreme low-power mode with ? the cpu, the flashes, and almost al l peripherals and memories powered down and to be used by software ? to wait until it is required to do something with no need to react quickly (i.e., allow for system power-up and system clock source to be re-started) the exit sequence of this mode is similar to the reset sequence. however, in addition to booting from the default location, the device can also be configured to boot fr om the backup ram (see the rgm_stdby register description in the mc_rgm chapter for detail s). in the case of booting from backup ram, it is also possible to keep the flashes disabled by writing ?01? to the cf laon and dflaon fileds in the me_drun_mc register prior to st andby entry. when booting from ba ckup ram, the core will begin executing at address 0x400 00000. a 4k mmu entry will be created commencing at this address, configured to use the vle instruction set. if there is a standby mode request while any wakeup event is active, the device mode does not change. all power domains except power dom ain #0 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. 29.4.3 mode transition process the process of mode transition follows the follow ing steps in a pre-defined manner depending on the current device mode and the requested target mode. in many cases of m ode transition, not all steps need to be executed based on the mode c ontrol information, and some steps ma y not be applicable according to the mode definition itself. 29.4.3.1 target mode request the target mode is requested by accessing the me_m ctl register with the required keys. this mode transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the process. if the request fails to satisfy these rules, it is ignored, and the ta rget_mode bit field is not updated. an optional interrupt can be generated for invali d mode requests. refer to section 29.4.5, mode transition interrupts for details.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-41 preliminary?subject to change without notice in the case of mode transitions occurring because of ha rdware events such as a reset, a safe mode request, or interrupt requests and wakeup ev ents to exit from low-power modes, the target_mode bit field of the me_mctl register is automatically updated with the appropriate target mode. the mode change process start is indicated by the setting of th e mode transition status bit s_mtrans of the me_gs register. a reset mode requested via the me_mctl register is passed to th e mc_rgm, which generates a global system reset and initiates the reset sequence. the reset mode request has the highest priority, and the mc_me is kept in the reset mode during the entire reset sequence. the safe mode request has the next highest priority after reset. it can be generated either by software via the me_mctl register from all soft ware running modes including drun , run0?3 , and test or by the mc_rgm after the detection of system hardware failures, which may occur in any mode. 29.4.3.2 target mode configuration loading on completion of the target mode request step, the target mode configuration from the me_ _mc register is loaded to start the resour ces (voltage sources, clock sources, flash, pads, etc.) co ntrol process. an overview of resource control possib ilities for each mode is shown in table 29-16 . a ? ? ? indicates that a given resource is configurable for a given mode. table 29-16. mc_me resource control overview resource mode reset test safe drun run0?3 halt stop standby firc ? ?? ? on on on on on on on on fxosc ? ???? ? off off off off off off off off fmpll0 ? ??? off off off off off off off off fmpll1 ? ??? off off off off off off off off cflash ? ???? normal normal normal normal normal low-power power- down power- down mvreg ?? on on on on on on on off pdo ?? ? off off on off off off off on
pxd20 microcontroller reference manual, rev. 1 29-42 freescale semiconductor preliminary?subject to change without notice 29.4.3.3 peripheral clocks disable on completion of the target mode request step, the mc_me requests each peripheral to enter its stop mode when: ? the peripheral is configured to be disabled via the target m ode, the peripheral configuration registers me_run_pc0?7 and me_lp_pc0?7, and the peripheral control registers me_pctl0?143 warning the mc_me does not automatically reque st peripherals to enter their stop modes if the power domains in which th ey are residing are to be turned off due to a mode change. therefore, it is software?s responsibility to ensure that those peripherals that are to be powered down are configured in the mc_me to be frozen. each peripheral acknowledges its stop mode request after clos ing its internal activity. the mc_me then disables the corresponding clock(s) to this peripheral. in the case of a safe mode transition request, the mc_me does not wait for the peripherals to acknowledge the stop requests. the safe mode cloc k gating configuration is applied immediately regardless of the status of the peripherals? stop acknowledges. please refer to section 29.4.6, peripheral clock gating for more details. each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive st ate when the device enters the safe mode. 29.4.3.4 processor low-power mode entry if, on completion of the peripheral clocks disable step, the mode transition is to the halt mode, the mc_me requests the processor to ente r its halted state. the processor acknowledges its halt state request after completing all outst anding bus transactions. if, on completion of the peripheral clocks disable step, the mode transition is to the stop or standby mode, the mc_me requests the proces sor to enter its stopped state. the processor ac knowledges its stop state request after completing al l outstanding bus transactions. 29.4.3.5 processor and syst em memory clock disable if, on completion of the processor low-power mode entry step, the mode transition is to the halt, stop, or standby mode and the processor is in its appropriate halted or stopped state, the mc_me disables the processor and system memory cloc ks to achieve further power saving. the clocks to the processor and system memory are unaffected while transi tioning between software running modes such as drun, run0?3, and safe. warning clocks to the whole device including th e processor and system memory can be disabled in test mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-43 preliminary?subject to change without notice 29.4.3.6 clock sources (main voltage regulator independent) switch-on on completion of the processor low-power mode entry , the mc_me controls all cl ock sources that affect the system clock based on the on bits of the me_ _mc and me_ _mc registers. the following system cloc k sources are switched on at this step: ? the fast internal rc oscillator (16 mhz) ? the fast external crys tal oscillator (4?16 mhz) ? the secondary fmpll note clock sources which need the main volta ge regulator to be stable are not controlled by this step. the clock sources that are required by the target mode are switched on. the duration required for the output clocks to be stable depends on the type of source, a nd all further steps of mode transition depending on one or more of these clocks waits for the stable st atus of the respective clocks . the availability status of these clocks is updated in the s_ bits of me_gs register. the clock sources which need to be switched off are unaffecte d during this process in order to not disturb the system clock which might require one of these cl ocks before switching to a different target clock. 29.4.3.7 main voltage regulator switch-on on completion of the target mode request step, if the main voltage regulator needs to be sw itched on from its off state based on the mvron bit of the me_ _mc and me__mc registers, the mc_me requests the mc_pcu to power -up the regulator and wait s for the output voltage stable status in order to update th e s_mvr bit of the me_gs register. this step is required only during the exit of the lo w-power modes halt and stop. in this step, the fast internal rc oscillator (16 mhz) is switched on regard less of the target mode c onfiguration, as the main voltage regulator requires the 16 mhz in t. rc osc. during power-up in orde r to generate the voltage status. during the standby exit sequence, the mc_pcu al one manages the power-up of the main voltage regulator, and the mc_me is kept in reset or s hut off (depending on the power domain #1 status). 29.4.3.8 flash module switch-on on completion of the main voltage regulator switch-on step, if the flash needs to be switched to normal mode from its low-power or power-down mo de based on the flaon bit field of the me_ _mc and me_ _mc registers, the mc_me requests the flash to exit from its low-power/power-down mode. when the flash available for ac cess, the s_fla bit field of the me_gs register updated to ?11? by hardware. if the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept in its low-power state and is switched on only when the main voltage regulator switch-on process has completed.
pxd20 microcontroller reference manual, rev. 1 29-44 freescale semiconductor preliminary?subject to change without notice warning it is illegal to switch the flash from low-power mode to power-down mode and from power-down mode to low- power mode. the mc_me, however, does not prevent this nor does it flag it. 29.4.3.9 clock sources (main voltag e regulator dependent) switch-on on completion of the clock sources (main voltage re gulator independent) switch-on and main voltage regulator switch-on , the mc_me controls all clock sources, whic h need the main volta ge regulator to be on, based on the on bits of the me_ _mc and me_ _mc registers. the following clock sour ces are switched on at this step: 29.4.3.10 power domain #2 switch-on on completion of the main voltage regulator switch-on step, the mc_me indica tes a mode change to the mc_pcu. the mc_pcu then determines whethe r a power-up sequence is required for power domain #2. only after the mc_pcu has executed all requi red power-ups does the mc_me complete the mode transition. 29.4.3.11 pad outputs-on on completion of the main voltage regulator switch-on step, if the pdo bit of the me_ _mc register is cleared, then ? all pad outputs are enabled to return to their previous state ? the i/o pads power sequence driver is switched on 29.4.3.12 peripheral clocks enable based on the current and target de vice modes, the peripheral c onfiguration registers me_run_pc0?7, me_lp_pc0?7, and the peripheral co ntrol registers me_pctl0?143, th e mc_me enables the clocks for selected modules as required. this step is executed only after the main voltage regulator switch-on process is completed. also, if a mode change translates to a power up of one or more pow er domains, the mc_pcu indicates the mc_me after completing the power-up sequence upon which the mc_me may assert the peripheral clock enables of the peripherals residing in those power domains. 29.4.3.13 processor and memory clock enable if the mode transition is from any of the low-power modes halt or st op to run0?3, the clocks to the processor and system memory are enab led. the process of enabling these cl ocks is executed only after the flash module switch-on process is completed.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-45 preliminary?subject to change without notice 29.4.3.14 processor low-power mode exit if the mode transition is from any of the low-power modes halt, stop, or standby to run0?3, the mc_me requests the processor to exit from its halted or stopped state. this step is executed only after the processor and memory clock enable process is completed. 29.4.3.15 system clock switching based on the sysclk bit field of the me_ _mc and me_ _mc registers, if the target and current system cl ock configurations differ, the follow ing method is implemented for clock switching. ? the target clock configuration for the 16 mh z int. rc osc. takes effect only after the s_firc bit of the me_gs register is set by hardware (i.e., the fast internal rc oscillator (16 mhz) has stabilized). ? the target clock configuration for the div. 4-16 mhz ext. xtal osc. takes effect only after the s_fxosc bit of the me_gs register is set by hardware (i.e the fast external crystal oscillator (4-16 mhz) has stabilized). ? the target clock configuration for the primary pll/2 takes effect only after the s_ fmpll0 bit of the me_gs register is set by hardware (i.e., th e primary frequency modulated phase locked loop has stabilized). ? if the clock is to be disabled, the sysclk bit field should be programmed with ?1111.? this is possible only in the stop and test modes. in the standby mode, the cl ock configuration is fixed, and the system clock is automatically forced to ?0?. the current system clock configurat ion can be observed by reading the s_sysclk bit field of the me_gs register, which is updated afte r every system clock switch ing. until the target clock is available, the system uses the previous clock configuration. system clock switchi ng starts only after ? the peripheral clocks disable process has completed in order not to change the system clock frequency before peripherals cl ose their internal activities an overview of system clock source selection possibilities for each mode is shown in table 29-17 . a ? ? ? indicates that a given clock source is selectable for a given mode. table 29-17. mc_me system clock selection overview system clock source mode reset test safe drun run0?3 halt stop standby 16 mhz int. rc osc. ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) div. 4-16 mhz ext. xtal osc. ? ????
pxd20 microcontroller reference manual, rev. 1 29-46 freescale semiconductor preliminary?subject to change without notice 29.4.3.16 power domain #2 switch-off based on the device mode and the mc_pcu?s power configuration register pcu_pconf2, the power domain #2 is controlled by the mc_pcu. if a mode change translates to a power-down of the power domain, then the mc_pcu starts the power-down sequence. the mc_pcu acknowledges th e completion of the power-down sequence with respect to the new mode, and the mc_me uses this in formation to update the mode transition status. this step is executed only after the peripheral clocks disable process has completed. 29.4.3.17 pad switch-off if the pdo bit of the me_< target mode> _mc register is ?1? then ? the outputs of the pads are forced to the high impedance state if the target mode is safe or test ? i/o pads power sequence dr iver is switched off if the target mode is one of safe, test, or stop modes in standby mode, the power sequen ce driver and all pads except the external reset and those mapped on wakeup lines are not powered and therefore high impedance. the wa keup line configuration remains unchanged. this step is executed only after the peripheral clocks disable process has completed. 29.4.3.18 clock sources switch-off based on the device mode and the on bits of the me_ _mc registers, if a given clock source is to be switched off, the mc_me requests the clock s ource to power down and updates its availability status bit s_ of the me_gs register to ?0?. the following clock sources switched off at this step: this step is executed only after the system clock switching process has completed. 29.4.3.19 flash switch-off based on the flaon bit field of the me_ _mc and me_ _mc registers, if the flash is to be put in its low-power or power-down m ode, the mc_me requests the flash to enter the primary pll/2 ? ??? system clock is disabled ? ? ?? (default) 1 disabling the system clock during test mode will require a reset in order to exit test mode table 29-17. mc_me system clock selection overview (continued) system clock source mode reset test safe drun run0?3 halt stop standby
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-47 preliminary?subject to change without notice corresponding power mode and waits for the flash to acknowledge. the exact power mode status of the flash is updated in the s_fla bit field of the me_g s register. this step is executed only when the processor and system memory clock disable process has completed. 29.4.3.20 main voltage regulator switch-off based on the mvron bit of the me_ _mc and me_ _mc registers, if the main voltage regulator is to be switched off, the mc_me requests it to power down and clears the availability status bit s_mvr of the me_gs register. this step is required only during the entry of low-power modes like halt and stop. this step is executed only after completing the following processes: ? clock sources switch-off ? flash switch-off ? the device consumption is less than the pre-defi ned threshold value (i.e., the s_dc bit of the me_gs register is ?0?). if the target mode is standby, the main voltage regulator is not switched off by the mc_me and the standby request is asserted afte r the above processes have comp leted upon which the mc_pcu takes control of the main regulator. as the mc_pcu needs the 16 mhz int. rc osc., the fast internal rc oscillator (16 mhz) remains activ e until all the standby steps are executed by the mc_pcu after which it may be switched off depending on the fi rcon bit of the me_standby_mc register. 29.4.3.21 current mode update the current mode status bit fiel d s_current_mode of the me_gs regi ster is updated with the target mode bit field target_mode of the me_mctl register when: ? all the updated status bits in the me_gs regi ster match the configuration specified in the me_ _mc register ? power sequences are done ? clock disable/enable process is finished ? processor low-power mode (halt/stop) entry and exit processes are finished software can monitor the mode transition status by reading the s_mtrans bit of the me_gs register. the mode transition latency can diff er from one mode to a nother depending on the re sources? availability before the new mode request and the target mode?s requirements. if a mode transition is taking longer to complete th an is expected, the me_dmts register can indicate which process is still in progress.
pxd20 microcontroller reference manual, rev. 1 29-48 freescale semiconductor preliminary?subject to change without notice figure 29-25. mc_me transition diagram target standby standby request ny main vreg switch-off end target mode request write me_mctl register safe mode request interrupt/wakeup event peripheral clocks disable clock sources switch-on system clock switching flash switch-on pad processor low-power processor & pad peripheral clocks enable flash switch-off s_mtrans = ?? analog on digital control analog off current mode update start s_mtrans = ?? outputs on outputs off entry processor low-power exit clock disable memory processor & clock enable memory clock sources without dependencies switch-off main vreg switch-on main vreg dependent clock sources switch-on clock sources with dependencies switch-off power domain switch-on power domain switch-off
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-49 preliminary?subject to change without notice 29.4.4 protection of mode configuration registers while programming the mode c onfiguration registers me_ _mc, the following rules must be respected. otherwise, the write opera tion is ignored and an invalid mode configuration interrupt may be generated. ? the firc must be enabled if it is to be se t as the system clock. likewise, the firc cannot be disabled whilst it is selected as the system clock. ? if the div. 4-16 mhz ext. xtal osc. clock is selected as the system clock, osc must be on. ? if the primary pll/2 clock is selected as the system clock, pll and fxosc must be on. note software must ensure that clock source s with dependencies other than those mentioned above are swithced on as needed. there is no automatic protection mechanism to check this in the mc_me. ? configuration ?00? for the fl aon bit field is reserved. ? mvreg must be on if any of the following is active: ?cflash ? system clock configurations marked as ?reserved? may not be selected. ? configuration ?1111? for the sysclk bit field is allowed only for the stop and test modes, and only in this case may all syst em clock sources be turned off. warning if the system clock is stopped duri ng test mode, the device can exit only via a system reset. 29.4.5 mode transition interrupts the mc_me provides interrupts for incorrectly c onfiguring a mode, requesting an invalid mode transition, indicating a safe mode tr ansition not due to a software re quest, and indicating when a mode transition has completed. 29.4.5.1 invalid mode configuration interrupt whenever a write operation is attempted to the me_ _mc registers violating the protection rules mentioned in the section 29.4.4, protection of mode configuration registers , the interrupt pending bit i_iconf of the me_is register is set and an interrupt request is generated if the mask bit m_iconf of me_im register is ?1?. 29.4.5.2 invalid mode transition interrupt the mode transition request is consider ed invalid under the following conditions: ? if the system is in the safe mode and the sa fe mode request from mc_r gm is active, and if the target mode requested is other than reset or safe, then this new mode request is considered to be invalid, and the s_sea bit of the me_imts register is set.
pxd20 microcontroller reference manual, rev. 1 29-50 freescale semiconductor preliminary?subject to change without notice ? if the target_mode bit field of the me_mctl re gister is written with a value different from the specified mode values (i.e., a non-existing mode), an invalid m ode transition event is generated. when such a non existing mode is requested, the s_ nma bit of the me_imts re gister is set. this condition is detected regardless of whether the proper key mechan ism is followed while writing the me_mctl register. ? if some of the device modes ar e disabled as programmed in th e me_me register, their respective configurations are considered reserved, and a ny access to the me_mctl register with those values results in an invalid mode transition reques t. when such a disabled mode is requested, the s_dma bit of the me_imts register is set. this condition is detected re gardless of whether the proper key mechanism is followed while writing the me_mctl register. ? if the target mode is not a valid mode with resp ect to the current mode, the mode request illegal status bit s_mri of the me_imts register is set. this conditi on is detected only when the proper key mechanism is followed whil e writing the me_mctl register. otherwise, the write operation is ignored. ? if further new mode requests occu r while a mode transition is in progress (the s_mtrans bit of the me_gs register is ?1?), the mode transition illegal status bi t s_mti of the me _imts register is set. this condition is detected only when th e proper key mechanism is followed while writing the me_mctl register. otherwise, the write operation is ignored. note as the causes of invalid mode transiti ons may overlap at the same time, the priority implemented for invalid m ode transition status bits of the me_imts register in the order from hi ghest to lowest is s_sea, s_nma, s_dma, s_mri, and s_mti. as an exception, the mode transition request is not considered as invalid under the following conditions: ? a new request is allowed to enter the reset or safe mode irrespective of the mode transition status. ? as the exit of halt and stop modes depends on the interrupts of the syst em which can occur at any instant, these requests to return to run0?3 modes are always valid. ? in order to avoid any unwanted lockup of the devi ce modes, software can abort a mode transition by requesting the parent mode if , for example, the mode transi tion has not completed after a software determined ?reasonable? amount of time for whatever r eason. the parent mode is the device mode before a valid mode request was made. ? self-transition requests (e.g., run0 ? run0) are not considered as invalid even when the mode transition process is active (i.e ., s_mtrans is ?1?). during the lo w-power mode exit process, if the system is not able to enter the respective ru n0?3 mode properly (i.e., all status bits of the me_gs register match with c onfiguration bits in the me_ _mc register), then software can only request the safe or res et mode. it is not possible to re quest any other mode or to go back to the low-power mode again. whenever an invalid mode request is detected, the interrupt pending bi t i_imode of the me_is register is set, and an interrupt request is generated if the mask bit m_imode of the me_im register is ?1?.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-51 preliminary?subject to change without notice 29.4.5.3 safe mode transition interrupt whenever the system enters the safe mode as a re sult of a safe mode reque st from the mc_rgm due to a hardware failure, the interrupt pending bit i_safe of the me_is register is set, and an interrupt is generated if the mask bit m_safe of me_im register is ?1?. the safe mode interrupt pending bit can be cleared only when the safe mode request is deasserted by the mc_rgm (see the mc_rgm chapte r for details on how to clear a safe mode request). if the system is already in safe mode, any ne w safe mode request by the mc_rgm also sets the interrupt pending bit i_safe. however, the safe mode interrupt pending bit is not set when the safe mode is entered by a software request (i.e., progr amming of me_mctl register). 29.4.5.4 mode transition complete interrupt whenever the system fully completes a mode tran sition (i.e., the s_mtrans bit of me_gs register transits from ?1? to ?0?), the interrupt pending bit i_ mtc of the me_is register is set, and an interrupt request is generated if the mask bi t m_mtc of the me_im register is ?1 ?. the interrupt bit i_mtc is not set when entering low-power modes halt and stop in order to avoid the same event requesting the immediate exit of these low-power modes. 29.4.6 peripheral clock gating during all device modes, each peri pheral can be associated with a particular clock gating policy determined by two groups of peri pheral configuration registers. the run peripheral configuration registers me_run_pc0?7 are chosen only during the software running modes drun, test, safe, and ru n0?3. all configurati ons are programmable by software according to the needs of the application. each configuration register contains a mode bit which determines whether or not a peripheral clock is to be gated. run configuratio n selection for each peripheral is done by the run_cfg bit field of the me_pctl0?143 registers. the low-power peripheral configur ation registers me_lp_ pc0?7 are chosen only during the low-power modes halt, stop, and standby. al l configurations are programmable by softwa re according to the needs of the application. ea ch configuration regi ster contains a mode bit whic h determines whether or not a peripheral clock is to be gate d. low-power configurati on selection for each pe ripheral is done by the lp_cfg bit field of the me_pctl0?143 registers. any modifications to the me _run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers do not affect the clock gating beha vior until a new mode tran sition request is generated. whenever the processor enters a de bug session during any mode, the foll owing occurs for each peripheral: ? the clock is gated if the dbg_f bit of the associated me_pctl0?1 43 register is set. otherwise, the peripheral clock gating stat us depends on the run_cfg a nd lp_cfg bits. any further modifications of the me_run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers during a debug session will take affect immediately without requiring any new mode request.
pxd20 microcontroller reference manual, rev. 1 29-52 freescale semiconductor preliminary?subject to change without notice 29.4.7 application example figure 29-26 shows an example application flow for requesting a mode cha nge and then waiting until the mode transition has completed.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 29-53 preliminary?subject to change without notice figure 29-26. mc_me application example flow diagram start of mode change config for target mode okay? write me__mc , me_run_pc0?7 , me_lp_pc0?7 , and me_pctl0?143 registers n y write me_mctl with target mode and key write me_mctl with target mode and inverted key start timer s_mtrans cleared? y timer expired? n y n write me_mctl with current or safe mode and key write me_mctl with current or safe mode and inverted key stop timer mode change done
pxd20 microcontroller reference manual, rev. 1 29-54 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-1 preliminary?subject to change without notice chapter 30 nexus development interface (ndi) 30.1 introduction the nexus development interface (n di) block provides real-time de velopment support capabilities for the pxd20 mcu in compliance with the ieee-i sto 5001-2003 standard. this development support is supplied for mcus without requiring external address and da ta pins for internal visibility. the ndi block is an integration of several individual nexus blocks th at are selectedt to provide the development support interface for pxd20. the ndi block interfaces to the e200z4d, and internal buses to provide devel opment support as per the ieee-isto 5001-2003 standard. the development support provided incl udes program trace, watchpoint messaging, ownership trace, watchpoi nt triggering, processor overrun c ontrol, run-time access to the mcu?s internal memory map, and acc ess to the e200z4d internal regist ers during halt, via the jtag port. 30.2 block diagram figure 30-1 shows a functional block diagram of the ndi. a simplified block diagram of the ndi illustrates th e functionality and interdependence of major blocks (see figure 30-2 ) and how the individual nexus blocks are combined to form the ndi. figure 30-1. ndi block diagram power-on tck evto mseo mdo[11:0] reset message queue program trace ownership trace watchpoint trace cpu snoop message formatter arbiter divided system clock e200z1 trace information e200z4d trace information mcko input tap controller control registers to trace blocks tdo tdi tms evti reset control
pxd20 microcontroller reference manual, rev. 1 30-2 freescale semiconductor preliminary?subject to change without notice figure 30-2. ndi implementation block diagram 30.3 features the ndi module of the pxd20 is compliant with class 3 of the ieee-isto 5001-2003 standard, with additional class 4 features available.th e following features are implemented: ? program trace via branch trace messaging (btm). branch trace me ssaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), al lowing the development tool to interpolate what transpires between the discont inuities. thus static code may be traced. ? ownership trace via ownership trace messagi ng (otm). otm facilitates ownership trace by providing visibility of which pro cess id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. ? watchpoint messaging via the auxiliary pins. ? watchpoint trigger enable of program trace messaging. ? auxiliary interface for higher data input/output. ? four message data out pins. tdo cross-bar power-on mcko evto mdo[11:0] mseo ppc reset bp/wp control once/ nexus1 ta p program/ ownership register control read/write access message fifo message transmitter nexus2+ interface auxiliary port arbitration/ muxing reset control ta p register control clock control e200z4d nexus port controller tdo muxing jtag controller tdi evti tms nexus development interface z0_tdo z0_tms z0_tdi tclk trace tdi ta p npc_tms z0_tdo z0_tms npc_tdo access auxiliary ta p npc_tdo npc_tms tdi, tclk tck
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-3 preliminary?subject to change without notice ? one message start/end out pins (mseo). ? one watchpoint event pin (evto). ? one event-in pin (evti). ? one message clock out pin (mcko). ? four pin jtag port (tdi, tdo, tms, and tck). ? registers for program trace, owners hip trace, and watc hpoint trigger. ? all features controllable and configurable via the jtag port. ? run-time access to the on-chip memory map via th e nexus read/write access protocol. this allows for enhanced download/upload capabilities. ? all features are independently configurable and controllable via the ieee 1149.1 i/o port. ? the ndi block reset is controlled with jcomp, power-on reset, and the tap state machine. all these sources are independe nt of system reset. ? support for internal censorship mode to prevent external access to flash memory contents when censorship is enabled. note if the e200z4d core has executed a wait instruction, then the nexus2+ controller clocks are gated off. while the core is in this state, it is not be possible to perform nexu s read/write operations. 30.4 modes of operation the ndi block is in reset when th e tap controller state machine is in the test-logic-reset state. the test-logic-reset state is entered on the asserti on of the power-on reset signal or through state machine transitions controlled by tms. ownership of the tap is achieved by loading the appropriate enable instruction for the de sired nexus client in the jt agc controller (jtagc) block. the npc transitions out of the reset state imme diately following negation of power-on reset. 30.4.1 nexus reset in nexus reset mode, the following actions occur: ? register values default back to their reset values. ? the message queues are marked as empty. ? the auxiliary output port pins are ne gated if the ndi controls the pads. ? the tdo output buffer is disabled if the ndi has control of the tap. ? the tdi, tms, and tck inputs are ignored. ? the ndi block indicates to the mcu that it is not using the auxiliary output port. this indication can be used to three-state the output pins or use them for another function.
pxd20 microcontroller reference manual, rev. 1 30-4 freescale semiconductor preliminary?subject to change without notice 30.4.2 operating mode in full-port mode, all availa ble mdo pins are used to transmit mess ages. all trace featur es are enabled or can be enabled by writing the conf iguration registers via the jtag port. four mdo pins are available in full-port mode. 30.4.2.1 disabled-port mode in disabled-port mode, message transmission is disa bled. any debug feature that generates messages can not be used. the primary features available are class 1 features and read/write access. 30.4.2.2 censored mode the ndi supports internal flash censorship mode by preventing the transmissi on of trace messages and nexus access to memory-mapped resources when censorship is enabled. 30.4.2.3 stop mode stop mode logic is implemented in the nexus port cont roller (npc). when a request is made to enter stop mode, the ndi block completes monitoring of any pe nding bus transaction, transm its all messages already queued, and acknowledges the stop reque st. after the acknowledgment, the sy stem clock input are shut off by the clock driver on the device. wh ile the clocks are shut off, the development tool cannot access ndi registers via the jtag port. 30.5 external signal description all the signals are available in the 416 tepb ga without any multiplexing scheme. refer to chapter 3, signal description, for details. 30.5.1 nexus signal reset states 30.6 memory map and register description the ndi block contains no memory -mapped registers. nexus register s are accessed by a development tool via the jtag port using a client-select value and a re gister index. once registers are accessed by loading the appropriate value in the rs[0:6] field of the once command register (ocmd) via the jtag port. table 30-1. ndi signal reset state name function nexus reset state pull evti event-in pin ? up evto event-out pin 0b1 ? mcko message clock out pin 0b0 ? mdo[11:0] message data out pins 0 ? mseo message start/end out pin 0b1 ?
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-5 preliminary?subject to change without notice 30.6.1 nexus debug interface registers table 30-2 shows the ndi registers by client select a nd index values. once re gister addressing is documented in chapter 24, ieee 1149.1 test access port controller (jtagc) . 30.6.2 register description this section lists the ndi registers and de scribes the registers and their bit fields. 30.6.2.1 nexus device id register (did) the npc device identifica tion register, shown in figure 30-3 , allows the part revision number, design center, part identificat ion number, and manufacturer id entity code of the device to be determined through the auxiliary output port, and serially th rough tdo. this register is read-only. table 30-2. nexus debug interface registers client select index register client-independent registers 0bxxxx 0 device id (did) 1 1 implemented in npc block. all other regist ers implemented in e200z4d nexus3 block. 0bxxxx 127 port configuration register (pcr) 1 e200z4d control/status registers 0b0000 2 e200z4d development control1 (dc1) 0b0000 3 e200z4d development control2 (dc2) 0b0000 4 e200z4d development status (ds) 0b0000 7 read/write access control/status (rwcs) 0b0000 9 read/write access address (rwa) 0b0000 10 read/write access data (rwd) 0b0000 11 e200z4d watchpoint trigger (ppc_wt)
pxd20 microcontroller reference manual, rev. 1 30-6 freescale semiconductor preliminary?subject to change without notice 30.6.2.2 port configuration register (pcr) the pcr is used to select the npc mode of ope ration, enable mcko and se lect the mcko frequency, and enable or disable mcko gating. this register should be configured as soon as the ndi is enabled. the pcr register may be re written by the debug tool s ubsequent to the enabling of the npc for low power debug support. in this case, the debug tool may set and clear the lp_dbg_en, sleep_sync, and stop_sync bits, but must preserve the original state of the remaining bits in the register. note the mode or clock division must not be modified after mcko has been enabled. changing the mode or clock division while mcko is enabled can produce unpredictable results. reg index: 0 access: user read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r part revision number 1 1 part revision number default value is 0x0 for the device?s initial mask set and changes for each mask set revision. design center part identification number w reset 0 0 0 0 ? ? ? ? ? ? ? ? ? ? ? ? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r part identification number ( continued ) manufacturer identity code 1 w reset ? ? ? ? 0 0 0 0 0 1 0 0 0 0 0 1 figure 30-3. nexus device id register (did) table 30-3. did field descriptions field description 0?3 prn part revision number. contains the revision number of the part. this field changes with each revision of the device or module. 4?9 dc design center. 10?19 pin part identification number. contains the part number of the device. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id: 0x20. 31 fixed per jtag 1149.1. always set to 1.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-7 preliminary?subject to change without notice reg index: 127 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fpm mck o _gt mck o _en mcko_div evt _en 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lp_ dbg _en 0 0 0 0 0 sle ep_ syn c sto p_s ync 0 0 0 0 0 0 0 psta t _en w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-4. port configuration register (pcr) table 30-4. pcr field descriptions field description fpm full port mode.the value of the fpm bit determines if the auxiliary output port uses the full mdo port or a reduced mdo port to transmit messages. 0 a subset of mdo pins are used to transmit messages. 1 all mdo pins are used to transmit messages. mcko_en mcko enable. this bit enables the mcko clock to run. when enabled, the frequency of mcko is determined by the mcko_div field. 0 mcko clock is driven to zero. 1 mcko clock is enabled. mcko_div mcko division factor. the value of this signal determines the frequency of mcko relative to the system clock frequency when mcko_en is assert ed. in this table, sys_ clk represents the system clock frequency. mcko_div[2:0] mcko frequency 0b000 sysclk ? 1 0b001 sysclk ? 2 0b010 reserved 0b011 sys_clk ? 4 0b100 reserved 0b101 reserved 0b110 reserved 0b111 sys_clk ? 8
pxd20 microcontroller reference manual, rev. 1 30-8 freescale semiconductor preliminary?subject to change without notice 30.6.2.3 development control register 1, 2 (dc1, dc2) the development control regi sters are used to control the basic deve lopment features of the nexus module. figure 30-5 shows development control register 1 and table 30-5 describes the register?s fields. evt_en evto/evti enable. this bit enables the evto/evti port functions. 0 evto/evti port disabled. 1 evto/evti port enabled. lp_dbg_en low power debug enable. the lp_dbg_en bit enables debug functionality to support entry and exit from low power sleep and stop modes. 0 low power debug disabled. 1 low power debug enabled. note: see also section 30.8.1, relationship betw een tck and system clock frequency. sleep_ sync sleep mode synchronization. the sleep_sync bit is used to synchroni ze the entry in to sleep mode between the device and debug tool. the device sets this bit before a pending entry into sleep mode. after reading sleep_sync as set, the debug tool then clears sleep_sync to acknowledge to the device that it may enter into sleep mode. 0 sleep mode entry acknowledge. 1 sleep mode entry pending. note: see also section 30.8.1, relationship betw een tck and system clock frequency. stop_sync stop mode synchronization. the stop_sync bit is used to synchronize th e entry into stop mode between the device and debug tool. the device sets this bit before a pending entry into stop mode. after reading stop_sync as set, the debug tool then clears stop_sync to acknowledge to the device that it may enter into stop mode. 0 stop mode entry acknowledge. 1 stop mode entry pending pstat_en processor status mode enable nexus reg: 0x0002 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r opc mck_div eoc 0 ptm wen 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovc eic tm w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-5. development control register 1 (dc1) table 30-4. pcr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-9 preliminary?subject to change without notice development control register 2 is shown in figure 30-6 and its fields are described in table 30-6 . table 30-5. dc1 field descriptions field description 0 opc 1 1 the output port mode control bit (opc) and mcko divide bits (mck_div) are shown for clarity. these functions are controlled globally by the npc port control register (pcr). these bits are writable in the pcr but have no effect. output port mode control. 0 reduced-port mode configuration (2 mdo pins). 1 full-port mode configuration (all mdo pins). 1?2 mck_div[1:0] 1 mcko clock divide ratio (see note 1). 00 mcko is 1x processor clock freq. 01 mcko is 1/2x processor clock freq. 10 mcko is 1/4x processor clock freq. 11 mcko is 1/8x processor clock freq. 3?4 eoc[1:0] evto control. 00 evto upon occurrence of watchpoints (configured in dc2). 01 evto upon entry into debug mode. 10 evto upon timestamping event. 11 reserved. 5 reserved. 6 ptm program trace method. 0 program trace uses traditional branch messages. 1 program trace uses branch history messages. 7 wen watchpoint trace enable. 0 watchpoint messaging disabled. 1 watchpoint messaging enabled. 8?23 reserved. 24?26 ovc[2:0] overrun control. 000 generate overrun messages. 001?010 reserved. 011 delay processor for btm / dtm / otm overruns. 1xx reserved. 27?28 eic[1:0] evti control. 00 evti is used for synchronization (program trace/ data trace). 01 evti is used for debug request. 1x reserved. 29?31 tm[2:0] trace mode. any or all of the tm bits may set, enabling one or more traces. 000 no trace. 1xx program trace enabled. x1x data trace enabled (not supported mode) xx1 ownership trace enabled.
pxd20 microcontroller reference manual, rev. 1 30-10 freescale semiconductor preliminary?subject to change without notice note the eoc bits in dc1 must be progr ammed to trigger evto on watchpoint occurrence for the ewc bits to have any effect. 30.6.2.4 development status register (ds) the development status register is used to report system debug status. when debug mode is entered or exited, or a cpu-defined low-power mode is entered, a debug status message is transmitted with ds[31:24]. the external tool can r ead this register at any time. nexus reg: 0x0003 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ewc 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-6. development control register 2 (dc2) table 30-6. dc2 field descriptions field description 0?7 ewc[7:0] evto watchpoint configuration. any or all of the bits in ewc may be set to configure the evto watchpoint. 00000000 no watchpoints trigger evto 1xxxxxxx watchpoint #0 (iac1 from nexus1) triggers evto. x1xxxxxx watchpoint #1 (iac2 from nexus1) triggers evto. xx1xxxxx watchpoint #2 (iac3 from nexus1) triggers evto. xxx1xxxx watchpoint #3 (iac4 from nexus1) triggers evto. xxxx1xxx watchpoint #4 (dac1 from nexus1) triggers evto. xxxxx1xx watchpoint #5 (dac2 from nexus1) triggers evto. xxxxxx1x watchpoint #6 (dcnt1 from nexus1) triggers evto. xxxxxxx1 watchpoint #7 (dcnt2 from nexus1) triggers evto. 8?31 reserved.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-11 preliminary?subject to change without notice 30.6.2.5 read/write access control/status (rwcs) the read write access contro l/status register provide s control for read/write access. read /write access provides dma-like access to memory-mapped resources on the system bus while the processor is halted or during runtime. the rwcs regist er also provides read/write access status information as shown in table 30-9 . nexus reg: 0x0004 access: user read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dbg lps lpc chk 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-7. development status register (ds) table 30-7. ds field descriptions field description 0 dbg cpu debug mode status. 0 cpu not in debug mode. 1 cpu in debug mode. 1?3 lps system low power status 000 normal (run) mode xx1 doze mode x1x nap mode 1xx sleep mode 4?5 lpc[1:0] cpu low-power mode status. 00 normal (run) mode. 01 cpu in halted state. 10 cpu in stopped state. 11 reserved. 6 chk cpu checkstop status. 0 cpu not in checkstop state. 1 cpu in checkstop state. 7?31 reserved.
pxd20 microcontroller reference manual, rev. 1 30-12 freescale semiconductor preliminary?subject to change without notice nexus reg: 0x0007 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ac rw sz map pr 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt err dv w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-8. read/write access control/status register (rwcs) table 30-8. rwcs field description field description 0 ac access control. 0 end access. 1 start access. 1 rw read/write select. 0 read access. 1 write access. 2?4 sz[2:0] word size. 000 8-bit (byte.) 001 16-bit (halfword). 010 32-bit (word). 011 64-bit (doubleword?only in burst mode). 100?111 reserved. 5?7 map[2:0] map select. 000 primary memory map. 001-111 reserved. 8?9 pr[1:0] read/write access priority. 00 lowest access priority. 01 reserved (default to lowest priority). 10 reserved (default to lowest priority). 11 highest access priority. 10?15 reserved. 16?31 cnt[13:0] access control count. number of accesses of word size sz. 30 err read/write access error. see ta bl e 3 0 - 9 . 31 dv read/write access data valid. see table 30-9 .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-13 preliminary?subject to change without notice table 30-9 details the stat us bit encodings. 30.6.2.6 read/write a ccess address (rwa) the read/write access address regist er provides the system bus address to be accessed when initiating a read or a write access. 30.6.2.7 read/write access data (rwd) the read/write access data register provides the data to/from system bus memory-mapped locations when initiating a read or a write access. table 30-9. read/write access status bit encoding read action write action err dv read access has not completed write access completed without error 0 0 read access error has occurred write access error has occurred 1 0 read access completed without error write access has not completed 0 1 not allowed not allowed 1 1 nexus reg: 0x0009 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r rwa[0-15] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rwa[16-31] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-9. read/write access address register (rwa)
pxd20 microcontroller reference manual, rev. 1 30-14 freescale semiconductor preliminary?subject to change without notice 30.6.2.8 watchpoint trigger register (wt) the watchpoint trigger regist er allows the watchpoints defined within the nexus1 logic to trigger actions. these watchpoints can control program and/or data trace enable and di sable. the wt bits can be used to produce an address-related window for triggering trace messages. table 30-10 details the watchpoint tr igger register fields. nexus reg: 0x000a access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r rwd[0-15] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rwd[16-31] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-10. read/write access data register (rwd) nexus reg: 0x000b access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r pts pte 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 30-11. watchpoint trigger register (wt)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-15 preliminary?subject to change without notice 30.7 functional description the ndi block is implemented by integrati ng the following blocks on this device: ? nexus e200z4d development interface (once and nexus3 subblocks) ? nexus port controller (npc) block ? npc_hndshk module 30.7.1 npc_hndshk module this module enables debug entry/exit across low power modes(stop, halt, standby) . the npc_hndshk supports: ? setting and clearing of the npc pcr sync bit on low-power mode entry and exit ? putting the cpu into debug mode on low-power mode exit ? generating a falling edge on the jt ag tdo pad on low-power mode exit on halt, stop, or standby mode entry, the mc_m e asserts the lp_mode_entry_req input after the clock disable process has completed and before the proc essor enters its halted or stopped state. the mode transition will then not proceed un til the lp_mode_entry_ack output has been asserted. the notification to the debugger of a low-power mode entry consists of setting the low-power mode handshake bit in the port control register (read by the debugger) via the l p_sync_in output. the debugger acknowledges that the transition into a low-power mode may proceed by clea ring the low-power mode ha ndshake bit in the port control register (written by the debugger), which re sults in the deassertion of the lp_sync_out input. table 30-10. wt field descriptions field description 0?2 pts[2:0] program trace start control. 000 trigger disabled. 001 use watchpoint #0 (iac1 from nexus1). 010 use watchpoint #1 (iac2 from nexus1). 011 use watchpoint #2 (iac3 from nexus1). 100 use watchpoint #3 (iac4 from nexus1). 101 use watchpoint #4 (dac1 from nexus1). 110 use watchpoint #5 (dac2 from nexus1). 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1). 3?5 pte[2:0] program trace end control. 000 trigger disabled. 001 use watchpoint #0 (iac1 from nexus1). 010 use watchpoint #1 (iac2 from nexus1). 011 use watchpoint #2 (iac3 from nexus1). 100 use watchpoint #3 (iac4 from nexus1). 101 use watchpoint #4 (dac1 from nexus1). 110 use watchpoint #5 (dac2 from nexus1). 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1). 12?31 reserved.
pxd20 microcontroller reference manual, rev. 1 30-16 freescale semiconductor preliminary?subject to change without notice after entry into low power mode the tdo pad become s high impedance. on exit from low power mode it is forced to 0, so for correct operation the td o pin should be pulled up while in low power modes. on halt or stop mode exit, the mc_me asserts the lp_mode_exit_req input after ensuring that the regulator and memories are in normal mode and before the processor exits its halt ed or stopped state. the mode transition will then not proc eed until the lp_mode_exit_ack output has been asserted. the mc_rgm asserts the exit_from_standby input when executing a reset sequence due to a standby exit. the reset sequence will then not complete until the lp_mode_exit_ack output has been asserted. the notification to the debugger of a low-power mode exit consists of driving the tdo pad to `0'. the debugger acknowledges that the transiti on from a low-power mode can c ontinue by setting the low-power mode sync bit in the port control register (written by debugger), which results in the assertion of the lp_sync_out input. note the debugger clock multiplexer may not guarantee glitch free switching. therefore, tck should be disabled fr om when the debugger clears the sync bit in entry_clr until the debugger se nses the falling edge of tdo in tdo_set. 30.7.2 enabling nexus clients for tap access after the conditions have been met to bring the ndi out of the reset state, the loading of a specific instruction in the jtag controller (jtagc) block is re quired to grant the ndi owne rship of the tap. each nexus client has its own jtagc instruction opcode fo r ownership of the tap, granting that client the means to read/write its registers. the jtagc inst ruction opcode for each nexus client is shown in table 30-11 . after the jtagc opcode for a client has been loaded, the client is enabled by loading its nexus-enable instruction. the nexus-enable instruct ion opcode for each nexus client is listed in table 30-12 . opcodes for all other instructions supported by nexus clients can be found in the relevant sections of this chapter. table 30-11. jtagc instruction opcodes to enable nexus clients jtagc instruction opcode description access_aux_tap_npc 10000 enables a ccess to the npc tap controller. access_aux_tap_once 10001 enables access to the e200z4d tap controller. table 30-12. nexus client jtag instructions instruction description opcode npc jtag instruction opcodes nexus_enable opcode for npc nexus enable instruction (4-bits) 0x0 bypass opcode for the npc bypass instruction (4-bits) 0xf e200z0 once jtag instruction opcodes 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-17 preliminary?subject to change without notice 30.7.3 configuring the ndi for nexus messaging the ndi is placed in disabled mode upon exit of re set. if message transmissi on via the auxiliary port is desired, a write to the port configuration register (pcr) located in the npc is then required to enable the ndi and select the mode of opera tion. asserting mcko_en in the pcr places the ndi in enabled mode and enables mcko. the frequency of mcko is selected by writing th e mcko_div field. asserting or negating the fpm bit selects full-por t or reduced-port mode, respectively. when writing to the pcr, the pcr lsb must be written to a logic zero. setting the lsb of the pcr enables factory debug mode and prevents the transmissi on of nexus messages. table 30-13 describes the ndi configuration options. 30.7.4 programmable mcko frequency mcko is an output clock to the de velopment tools used for the timi ng of mseo and mdo pin functions. mcko is derived from the system cl ock, and its frequency is determin ed by the value of the mcko_div field in the port configuration regi ster (pcr) located in the npc. po ssible operating frequencies include one-quarter and one-eighth system clock speed. figure 30-14 shows the mcko_div encodings. in this ta ble, sys_clk represents the system clock frequency. the default value selected if a reserved encoding is programmed is sys_clk ? 2 note on pxd20, the pad type used for the nexus3 signals will not support the default sysclk ? 2 and sysclk ??? setting, so the user must change the mcko frequency to be not faster than sysclk ? 4. nexus2_access opcode for e200z4d once nexus enable instruction (10-bits) 0x7c bypass opcode for the e200z4d once bypass instruction (10-bits) 0x7f 1 see the e200z4d core reference manual for a co mplete list of available once instructions. table 30-13. ndi configuration options jcomp asserted mcko_en bit of the port configuration register fpm bit of the port configuration register configuration no x x reset yes 0 x disabled yes 1 1 full-port mode yes 1 0 reduced-port mode table 30-12. nexus client jtag instructions instruction description opcode
pxd20 microcontroller reference manual, rev. 1 30-18 freescale semiconductor preliminary?subject to change without notice 30.7.5 nexus messaging most of the messages transmitted by the ndi include a src field. this field is used to identify which source generated the message. table 30-15 shows the values used for the s rc field by the different clients on the pxd20. these values are specific to the pxd20. the size of the src field in transmitted messages is 4 bits. this value is also specific to the pxd20. 30.7.6 evto sharing the npc block controls sharing of the evto output between all nexus clients that generate an evto signal. the sharing mechanism is a logical and of all incoming evto signals from nexus blocks, thereby asserting evto whenever a ny block drives its evto . when there is no active mcko, such as in disabled mode, the npc drives evto for two system clock periods. evto sharing is active as long as the ndi is not in reset. 30.7.7 debug mode control on pxd20, program breaks can be requested either by using the evti pin as a break request, or when a nexus event is triggered. 30.7.7.1 evti generated break request to use the evti pin as a debug request, the eic field in the e200z4d nexus3 development control register 1 (dc1[4:3]) must be set to c onfigure the evti input as a debug request. table 30-14. mcko_div values mcko_div[2:0] mcko frequency 0b000 sysclk ? 1 0b001 sysclk ? 2 0b010 reserved 0b011 sys_clk ? 4 0b100 reserved 0b101 reserved 0b110 reserved 0b111 sys_clk ? 8 table 30-15. src packet encodings src[3:0] pxd20 client 0b0000 e200z04d all other combinations reserved
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 30-19 preliminary?subject to change without notice 30.7.8 nexus reset control the jcomp input that is used as th e primary reset signal for the npc is also used by the npc to generate a single-bit reset signal for other nexus blocks. the si ngle bit reset signal functi ons much like the ieee 1149.1-2001 defined trst signal but has a default value of disabled (jcomp is pulled low during reset) the ieee 1149.1-2001 defines trst to be pulled up (enabled) by default. 30.8 initialization / application information 30.8.1 relationship between t ck and system clock frequency the jtag clock (tck) typically operates at a freque ncy well below the system clock frequency, as specified in the pxd20 microcontroller data sheet . in some cases, however, su ch as low power mode (if the device supports low power modes) , the system clock frequency may be lowered significantly from the normal operating range. if the system clock frequency is reduced below th e frequency of tck, it will no longer be possible to communicate with the nexus port controller port configuration register (npc_pcr). therefore, if the tool needs to update the npc_pcr low power debug enable (npc[pcr[lp_dbg_en]) or low power synchroni zation bits (npc[pcr[lp_sync], the tck clock frequency must be lowered.
pxd20 microcontroller reference manual, rev. 1 30-20 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-1 preliminary?subject to change without notice chapter 31 openvg graphics accelerator (gfx2d) 31.1 introduction the openvg graphics accelerator (gfx2d) is an embedded processor targeting the openvg 1.1 graphics api and feature set. the gfx2d has a rich, but well-chosen se t of features, with emphasis being on very high image quality and low memory bandwidth consumption. the gfx2d has a geometry engine unit for operations on pr imitives such as lines or curves specified with absolute or relative coordinates in a user specified system. it also has 2d bitmap acceleration unit for graphics operations such as bit-bloc k transfers, block fill, dithering a nd raster operations. a pipe-lined unit calculates color and alpha values for pixels from pixel coordinates and alpha according to the required gradient or texturing mode. a sepa rate anti-aliasing polygon rasterizer is connected to the 2d graphics acceleration unit for vector graphics rendering acceleration. 31.1.1 block diagram figure 31-1. gfx2d block diagram 31.1.2 features the following describes the functional features of the graphics processor. 31.1.2.1 frame buffer ? frame buffer sizes supported up-to 2048x2048 ? argb4444, rgb565, argb1555, argb5551, argb8888 frame buffer modes ? programmable argb order in fram e buffer: argb, bgra, abgr, rgba bus interface burst cache arbiter input unit slave master 2d+vg unit
pxd20 microcontroller reference manual, rev. 1 31-2 freescale semiconductor preliminary?subject to change without notice ? linear and block-based (4x4 pixels) frame buffer modes ? fast buffer clears: ? write large bursts of buffer clear data to the system memory fr om the bus interface unit without the aid of the 2d/vg rendering pipeline ? support for openvg render to image 31.1.2.2 2d bitmap graphics (separate 2d unit) ? parallel operation with the 3d pi peline, independent command input ? bitblt (surface-to-surface copy) ? format conversion from monochrome/ argb/yuv to argb during bitblt ? block fill ? internal 32-bit color precision ? source bitmap format: ? 1/4/8-bit monochrome ? argb4444, rgb565, argb1555, argb5551, argb8888 ? programmable argb order: argb, bgra, abgr, rgba ? packed yuv 4:2:2 formats (fourcc codes yu y2, uyvy, yvyu), two pixels per 32 bits of data ? 1-bit bitmap maps to foreground and background colors ? 4-bit bitmap is optionally gamma corrected to 8-bit alpha values and can be combined with foreground color to draw anti-aliased fonts ? destination bitmap format: ? argb4444, rgb565, argb1555, argb5551, argb8888, b8, a8, ab88 ? programmable argb order: argb, bgra, abgr, rgba ? supports three source bitmaps fo r separate mask/pattern/alpha bitmap support plus reading destination for rop, blend and color key operations ? supports masking source coordi nates for wrapping patterns ? supports rop4 (rop3 with separate rops for masked and unmasked pixels) logical operations ? supports inverting mask and alpha values from source ? supports destination ro tation by 0/90/180/270 degrees ? supports programmable blending with optional alpha inverse premultiply ? supports per pixel and constant alpha with optional modulation by source color alpha for openvg alpha masking ? supports color keying by source and destination co lors, with optional ignoring of alpha channel ? supports one scissor rectangle for destination coordinates ? dithering (ordered) ? color component masking ? rgb reads and writes
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-3 preliminary?subject to change without notice ? non-power of two source and dest ination bitmap sizes supported (s tride must be a multiple of 32-bits) ? bitblt with scaling implemented with the 3d re ndering pipeline, bilinear filtering with texture lookups, programmable filter ke rnels possible with the pr ogrammable pixel processor 31.1.2.3 vector graphics ? parallel operation with the 3d pi peline, independent command input ? rasterization of convex and c oncave polygons with anti-aliasing ? efficient native polygon renderi ng (no tessellation to triangles) ? non-zero and odd-even fill rules ? primitives supported: ? polygons ? openvg path primitives (except elliptical arcs ): horizontal/vertical lines, generic lines, curves, smooth curves, moveto, path closing ? curve types supported: cubic and quadratic bzier ? strokes with thickness, joints and end caps, unlimited stroke thickness ? special case handling of singularities for thick strokes ? supports paths with a maximum of 256 crossi ngs along a horizontal or a vertical line ? input coordinates: ? absolute and relative coordi nate input in floating point ? fixed-point (byte, short, int) and floa ting-point coordinate input - 0.8, 0.16, 16.16 formats ? little- and big-endian s upport separately selectable for command stream and data. ?geometry ? user to surface transform for vertices and stroke shape ? hardware curve tessellation ? adjustable accuracy for curve and round cap splitting ? openvg/svg join types: miter (with miter limit ), round, bevel ? openvg/svg cap types: butt, round, square ? pixel processing: ? programmable gradient and texturing processor ? linear and radial grad ients (with focal point) ? perspective texture mapping with filtering ? two textures supported ? srgb and pre-multiply support for textures ? 16-sample anti-aliasing ? 4x rgss aa (rotated grid super sample) ? per-pixel alpha-masking ? maximum texture size: 1024x1024 pixels
pxd20 microcontroller reference manual, rev. 1 31-4 freescale semiconductor preliminary?subject to change without notice ? vector graphics rendering system cpu load: ? display list genera tion during path creation ? co mmands and vertices are stored to an internal format/buffer, no format conversion is performed ? filling or stroking a path only requires a few re gister writes to start the operation in hardware ? display lists are transferred to the vector graphics rast erizer using dma without cpu interaction 31.2 external signal description the gfx2d does not include any external signals. 31.3 memory map and register definition this section provides a detailed description of the gf x2d external registers that are mapped to aperture. the gfx2d 16k space memory map is shown in table 31-1 . the address of each register is given as an offset to the gfx2d base address. 31.3.1 g12_commandstream table 31-1. gfx2d memory map offset register access reset value location 0x000 g12_commandstream?command stream input w 0x0000_0000 on page 31-4 0x3fc g12_mmucommandstream?mmu command stream input w 0x0000_0000 on page 31-5 0x400 g12_revision?revision r 0x0000_0000 on page 31-5 0x410 g12_sysstatus?system status r 0x0000_0000 on page 31-5 0x418 g12_irqstatus?interrupt status r/w 0x0000_0000 on page 31-6 0x438 g12_irqenable?interrupt enable r/w 0x0000_0000 on page 31-6 0x4e0 g12_irq_active_cnt?active interrupt counters r 0x0000_0000 on page 31-7 0x508 g12_clocken?clock enable r/w 0x0000_000f on page 31-7 0x510 mmu_read_addr?mmu read address w 0x0000_0000 on page 31-8 0x518 mmu_read_data?mmu read data r 0x0000_00ff on page 31-8 0x7c0 g12_fifofree?fi fo free r 0x0000_0000 on page 31-9 offset 0x000 access: user write 3130292827262524232221201918171615141312111098765432 1 0 r0 00 00 0000000000000 00000000 00 00 00 wdata reset000000000000000000000000000000 0 0 figure 31-2. command stream input (g12_commandstream)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-5 preliminary?subject to change without notice 31.3.2 g12_mmucommandstream 31.3.3 g12_revision 31.3.4 g12_sysstatus table 31-2. command stream input (g 12_commandstream) field descriptions field description 31?0 command stream data offset 0x3fc access: user write 3130292827262524232221201918171615141312111098765432 1 0 r0 00 00 0000000000000 00000000 00 00 00 wdata reset000000000000000000000000000000 0 0 figure 31-3. mmu command stream input (g12_mmucommandstream) table 31-3. mmu command stream input (g 12_mmucommandstream) field descriptions field description 31?0 mmu command stream data offset 0x400 access: user read 3130292827262524232221201918171615141312111098765432 1 0 r0 00 00 0000000000000 000000 major minor w reset000000000000000000000000000000 0 0 figure 31-4. revision (g12_revision) table 31-4. revision (g12_revision) field descriptions field description 31?8 reserved 7?4 major revision id 3?0 minor revision id offset 0x410 access: user read 3130292827262524232221201918171615141312111098765432 1 0 r0 00 00 0000000000000 000000000000 0 r w reset000000000000000000000000000000 0 0 figure 31-5. system st atus (g12_sysstatus)
pxd20 microcontroller reference manual, rev. 1 31-6 freescale semiconductor preliminary?subject to change without notice 31.3.5 g12_irqstatus 31.3.6 g12_irqenable table 31-5. system status (g 12_sysstatus) field descriptions field description 31?1 reserved 0 internal reset state offset 0x418 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0000 0 0 0 0 0 0 0 0 w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 fbc fifo g2d mh w reset00000000 0 0000000 figure 31-6. interrupt status (g12_irqstatus) table 31-6. interrupt status (g12_irqstatus) field description field description 31?4 reserved. 3 fbc done interrupt status 2 fifo full error interrupt status 1 2d idle request interrupt status 0 mh axi error / mmu page fault interrupt status offset 0x438 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0000 0 0 0 0 0 0 0 0 w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 fbc fifo g2d mh w reset00000000 0 0000000 figure 31-7. interrupt enable (g12_irqenable)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-7 preliminary?subject to change without notice 31.3.7 g12_irq_active_cnt 31.3.8 g12_clocken table 31-7. interrupt enable (g12_irqenable) field description field description 31?4 reserved. 3 fbc done interrupt enable 2 fifo full error interrupt enable 1 2d idle request interrupt enable 0 mh axi error / mmu page fault interrupt enable offset 0x4e0 access: user read 3130292827262524232221201918171615141312111098765432 1 0 r fbc error g2d mh w reset000000000000000000000000000000 0 0 figure 31-8. active interrupt counters (g12_irq_active_cnt) table 31-8. active interrupt counters (g12_irq_active_cnt) field descriptions field description 31?24 fbc done interrupt counter 23?16 fifo full error interrupt counter 15?8 2d idle request interrupt counter 7?0 mh axi error / mmu page fault interrupt counter offset 0x508 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000 0000 0 0 0 0 0 0 0 0 w reset00000000 0 0000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 reserved vg_ l1l2 g2d_ vgl3 bca che w reset00000000 0 0000111 figure 31-9. clock enable (g12_clocken)
pxd20 microcontroller reference manual, rev. 1 31-8 freescale semiconductor preliminary?subject to change without notice 31.3.9 mmu_read_addr 31.3.10 mmu_read_data table 31-9. clock enable (g12_clocken) field description field description 31?6 reserved 5?3 legacy 2 enable vg level 1 and level 2 clock 1 enable 2d and vg level 3 clock 0 enable burst cache clock offset 0x510 access: user write 3130292827262524232221201918171615141312111098765432 1 0 r0 00 00 0000000000000 00000000 00 00 00 w addr reset000000000000000000000000000000 0 0 figure 31-10. mmu read address (mmu_read_addr) table 31-10. mmu read address (mmu_read_addr) field descriptions field description 31?15 reserved 14?0 register address offset 0x518 access: user read 3130292827262524232221201918171615141312111098765432 1 0 rdata w reset000000000000000000000000000000 0 0 figure 31-11. mmu read data (mmu_read_data) table 31-11. mmu read data (mmu_read_data) field descriptions field description 31?0 register data
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-9 preliminary?subject to change without notice 31.3.11 g12_fifofree 31.4 command stream registers this section provides a detailed description of the gf x2d internal registers that are only accessible via g12_commandstream. offset 0x7c0 access: user read 3130292827262524232221201918171615141312111098765432 1 0 r000000000000000000000000000000 0 f w reset000000000000000000000000000000 0 0 figure 31-12. fifo free (g12_fifofree) table 31-12. fifo free (g12_fifofree) field descriptions field description 31?1 reserved 0 free space in input fifo
pxd20 microcontroller reference manual, rev. 1 31-10 freescale semiconductor preliminary?subject to change without notice table 31-13. command stream registers offset register access reset value section/page 0x0 g2d_base0 w 0x0000_0000 31.4.1/31-14 0x1 g2d_cfg0 31.4.2/31-14 0x2 g2d_base1 31.4.1/31-14 0x3 g2d_cfg1 31.4.2/31-14 0x4 g2d_base2 31.4.1/31-14 0x5 g2d_cfg2 31.4.2/31-14 0x6 g2d_base3 31.4.1/31-14 0x7 g2d_cfg3 31.4.2/31-14 0x8 g2d_scissorx 31.4.3/31-15 0x9 g2d_scissory 31.4.4/31-15 0xa g2d_foreground 31.4.5/31-16 0xb g2d_background 31.4.5/31-16 0xc g2d_alphablend 31.4.6/31-16 0xd g2d_rop 31.4.7/31-16 0xe g2d_config 31.4.8/31-17 0xf g2d_input 31.4.9/31-18 0x10 g2d_mask 31.4.10/31-18 0x11 g2d_blendercfg 31.4.11/31-18 0x14 g2d_blend_a0 31.4.12/31-18 0x15 g2d_blend_a1 31.4.12/31-18 0x16 g2d_blend_a2 31.4.12/31-18 0x17 g2d_blend_a3 31.4.12/31-18 0x18 g2d_blend_c0 31.4.12/31-18 0x19 g2d_blend_c1 31.4.12/31-18 0x1a g2d_blend_c2 31.4.12/31-18 0x1b g2d_blend_c3 31.4.12/31-18 0x1c g2d_blend_c4 31.4.12/31-18 0x1d g2d_blend_c5 31.4.12/31-18 0x1e g2d_blend_c6 31.4.12/31-18
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-11 preliminary?subject to change without notice 0x1f g2d_blend_c7 w 0x0000_0000 31.4.12/31-18 0x20 vgv1_vtx0 31.4.13/31-20 0x21 vgv1_vtx1 31.4.13/31-20 0x22 vgv1_tileofs 31.4.14/31-20 0x23 vgv1_fill 31.4.15/31-21 0x24 vgv1_scissorx 31.4.16/31-21 0x25 vgv1_scissory 31.4.17/31-21 0x27 vgv1_cfg1 31.4.18/31-21 0x28 vgv1_cfg2 31.4.19/31-21 0x29 vgv1_dirtybase 31.4.20/31-22 0x2a vgv1_cbase1 31.4.21/31-22 0x2b vgv1_ubase2 31.4.22/31-22 0x40 vgv2_c1x 31.4.23/31-22 0x41 vgv2_c1y 31.4.24/31-22 0x42 vgv2_c2x 31.4.25/31-23 0x43 vgv2_c2y 31.4.25/31-23 0x44 vgv2_c3x 31.4.26/31-23 0x45 vgv2_c3y 31.4.26/31-23 0x46 vgv2_c4x 31.4.27/31-23 0x47 vgv2_c4y 31.4.27/31-23 0x48 vgv2_c1xrel 31.4.28/31-23 0x49 vgv2_c1yrel 31.4.28/31-23 0x4a vgv2_c2xrel 31.4.28/31-23 0x4b vgv2_c2yrel 31.4.28/31-23 0x4c vgv2_c3xrel 31.4.28/31-23 0x4d vgv2_c3yrel 31.4.28/31-23 0x4e vgv2_c4xrel 31.4.28/31-23 0x4f vgv2_c4yrel 31.4.28/31-23 0x50 vgv2_xfxx 31.4.29/31-24 0x51 vgv2_xfyx 31.4.30/31-24 0x52 vgv2_xfxy 31.4.31/31-24 0x53 vgv2_xfyy 31.4.32/31-24 0x54 vgv2_xfxa 31.4.33/31-25 table 31-13. command stream registers (continued) offset register access reset value section/page
pxd20 microcontroller reference manual, rev. 1 31-12 freescale semiconductor preliminary?subject to change without notice 0x55 vgv2_xfya w 0x0000_0000 31.4.34/31-25 0x56 vgv2_xfstxx 31.4.35/31-25 0x57 vgv2_xfstyx 31.4.36/31-25 0x58 vgv2_xfstxy 31.4.37/31-25 0x59 vgv2_xfstyy 31.4.38/31-26 0x5a vgv2_bboxminx 31.4.39/31-26 0x5b vgv2_bboxminy 31.4.39/31-26 0x5c vgv2_bboxmaxx 31.4.40/31-26 0x5d vgv2_bboxmaxy 31.4.40/31-26 0x5e vgv2_scale 31.4.41/31-26 0x5f vgv2_bias 31.4.42/31-26 0x60 vgv2_accuracy 31.4.43/31-27 0x61 vgv2_thinradius 31.4.44/31-27 0x62 vgv2_arccos 31.4.45/31-27 0x63 vgv2_arcsin 31.4.46/31-27 0x64 vgv2_arctan 31.4.47/31-27 0x65 vgv2_radius 31.4.48/31-28 0x66 vgv2_miter 31.4.49/31-28 0x68 vgv2_clip 31.4.50/31-28 0x6e vgv2_mode 31.4.51/31-28 0x6f vgv2_action 31.4.52/31-29 0x70 vgv3_control 31.4.53/31-30 0x71 vgv3_mode 31.4.54/31-30 0x72 vgv3_writeaddr 31.4.55/31-30 0x73 vgv3_write 31.4.56/31-31 0x74 vgv3_writeifpaused 31.4.57/31-31 0x75 vgv3_nextaddr 31.4.58/31-31 0x76 vgv3_nextcmd 31.4.59/31-31 0x77 vgv3_vgbypass 31.4.60/31-32 0x78 vgv3_writes8 31.4.61/31-32 0x79 vgv3_writes16 31.4.61/31-32 0x7a vgv3_writes32 31.4.61/31-32 0x7b vgv3_writef32 31.4.61/31-32 table 31-13. command stream registers (continued) offset register access reset value section/page
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-13 preliminary?subject to change without notice 0x7c vgv3_writeraw w 0x0000_0000 31.4.61/31-32 0x7d vgv3_writedmi 31.4.62/31-32 0x7f vgv3_last 31.4.63/31-32 0x84 fbc_base 31.4.64/31-33 0x86 fbc_data 31.4.65/31-33 0x88 fbc_width 31.4.66/31-33 0x8a fbc_height 31.4.67/31-33 0x8c fbc_stride 31.4.68/31-33 0x8e fbc_start 31.4.69/31-34 0xb0 g2d_const0 31.4.70/31-34 0xb1 g2d_const1 31.4.70/31-34 0xb2 g2d_const2 31.4.70/31-34 0xb3 g2d_const3 31.4.70/31-34 0xb4 g2d_const4 31.4.70/31-34 0xb5 g2d_const5 31.4.70/31-34 0xb6 g2d_const6 31.4.70/31-34 0xb7 g2d_const7 31.4.70/31-34 0xc0 gradw_const0 31.4.71/31-34 0xc1 gradw_const1 31.4.71/31-34 0xc2 gradw_const2 31.4.71/31-34 0xc3 gradw_const3 31.4.71/31-34 0xc4 gradw_const4 31.4.71/31-34 0xc5 gradw_const5 31.4.71/31-34 0xc6 gradw_const6 31.4.71/31-34 0xc7 gradw_const7 31.4.71/31-34 0cx8 gradw_const8 31.4.71/31-34 0xc9 gradw_const9 31.4.71/31-34 0xca gradw_consta 31.4.71/31-34 0xcb gradw_constb 31.4.71/31-34 0xd0 g2d_gradient 31.4.72/31-35 0xd1 gradw_texcfg 31.4.73/31-35 0xd2 gradw_texsize 31.4.74/31-36 0xd3 gradw_texbase 31.4.75/31-36 table 31-13. command stream registers (continued) offset register access reset value section/page
pxd20 microcontroller reference manual, rev. 1 31-14 freescale semiconductor preliminary?subject to change without notice 31.4.1 g2d_base0-3 31.4.2 g2d_cfg0-3 0xd4 gradw_bordercolor w 0x0000_0000 31.4.76/31-36 0xe0 gradw_inst0 31.4.77/31-37 0xe1 gradw_inst1 31.4.77/31-37 0xe2 gradw_inst2 31.4.77/31-37 0xe3 gradw_inst3 31.4.77/31-37 0xe4 gradw_inst4 31.4.77/31-37 0xe5 gradw_inst5 31.4.77/31-37 0xe6 gradw_inst6 31.4.77/31-37 0xe7 gradw_inst7 31.4.77/31-37 0xf0 g2d_xy 31.4.78/31-37 0xf1 g2d_widthheight 31.4.79/31-37 0xf2 g2d_sxy 31.4.80/31-38 0xf3 g2d_sxy2 31.4.80/31-38 0xf4 g2d_vgspan 31.4.81/31-38 0xfe g2d_idle 31.4.82/31-38 0xff g2d_color 31.4.83/31-38 offset 0x00 (g2d_base0) 0x02 (g2d_base1) 0x04 (g2d_base3) 0x06 (g2d_base3) access: user write field reset description 31?0 0x0 base address for frame buffer offset 0x01 (g2d_cfg0) 0x03 (g2d_cfg1) 0x05 (g2d_cfg3) 0x07 (g2d_cfg3) access: user write field reset description 31?24 0x0 reserved 23 0x0 stridedesign. stride sign bit 22 0x0 swapbits. swap order of bits or nibbles in bytes table 31-13. command stream registers (continued) offset register access reset value section/page
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-15 preliminary?subject to change without notice 31.4.3 g2d_scissorx 31.4.4 g2d_scissory 21 0x0 swaprb. swap red and blue components after conversion 20 0x0 swapall. argb -> bgra swap 19 0x0 swapbytes. swap read bytes in 32-bit value before conversion 18 0x0 swapwords. swap read words in 32-bit value before conversion 17 0x0 srgb. surface is in srgb format 16 0x0 tiled 15?12 0x0 format 0x0 g2d_1 (foreground and background) 0x1 g2d_1bw (black and white) 0x2 g2d_4 0x3 g2d_8 (blue when written) 0x4 g2d_4444 0x5 g2d_1555 0x6 g2d_0565 0x7 g2d_8888 0x8 g2d_yuy2 0x9 g2d_uyvy 0xa g2d_yvyu 0xb g2d_4444_rgba 0xc g2d_5551_rgba 0xd g2d_8888_rgba 0xe g2d_a8 0xf g2d_88 (alpha and blue) 11?0 0x0 stride offset 0x08 access: user write field reset description 31?22 0x0 reserved 21?11 0x0 right 10?0 0x0 left offset 0x01 (g2d_cfg0) 0x03 (g2d_cfg1) 0x05 (g2d_cfg3) 0x07 (g2d_cfg3) access: user write field reset description
pxd20 microcontroller reference manual, rev. 1 31-16 freescale semiconductor preliminary?subject to change without notice 31.4.5 g2d_foregrou nd, g2d_background 31.4.6 g2d_alphablend 31.4.7 g2d_rop offset 0x09 access: user write field reset description 31?22 0x0 reserved 21?11 0x0 bottom 10?0 0x0 top offset 0x0a (g2d_foreground) 0x0b (g2d_background) access: user write field reset description 31?24 0x0 color in 32-bit argb format offset: 0x0c access: user write field reset description 31?16 0x0 reserved 15 0x0 masktoalpha. route mask to alpha 14 0x0 premultiplydst. premultiply destination color 13 0x0 invertmask. invert mask value 12 0x0 modulate.modulate mask to alpha 11 0x0 optimize. optimize reads based on color alpha value before rop 10 0x0 invert. invert alpha value 9 0x0 constant. use constant alpha value 8 0x0 obs_enable. obsolete: enable alpha blend, enable blender instead 7?0 0x0 alpha. constant alpha value offset: 0x0d access: user write field reset description 31?16 0x0 reserved 15?8 0x0 raster operation (rop) data type mask 7 0x0 raster operation (rop) data type dst_src_pat 6 0x0 raster operation (rop) data type src_pat
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-17 preliminary?subject to change without notice 31.4.8 g2d_config 5 0x0 raster operation (rop) data type dst_pat 4 0x0 raster operation (rop) data type src_dst 3 0x0 raster operation (rop) data type pat 2 0x0 raster operation (rop) data type src 1 0x0 raster operation (rop) data type dst 0 0x0 raster operation (rop) data type not offset: 0x0e access: user write field reset description 31?20 0x0 reserved 19 0x0 noprotect. don't use protect for destination reads 18 0x0 nolastpixel. don't draw last pixel of a line (for polylines) 17 0x0 palmlines.draw lines according to palmos rules (default wince) 16 0x0 alphatex. take only alpha from texture 0, apply color from input 15 0x0 amask. mask writes to alpha component, value 0 writes, 1 doesn't. 14 0x0 rmask. mask writes to red component, value 0 writes, 1 doesn't. 13 0x0 gmask. mask writes to green component, value 0 writes, 1 doesn't. 12 0x0 bmask. mask writes to blue co mponent, value 0 wr ites, 1 doesn't. 11 0x0 writesrgb. write srgb color 10 0x0 dither. dither the output 9 0x0 ignoreckalpha. ignore alpha in color key compare 8 0x0 obs_gamma. obsolete: gamma correct 4-bit bitmap, use srgb instead 7?6 0x0 rotate. destination rotate 5 0x0 dstck. destination color key 4 0x0 srcck. source color key 3 0x0 src3. read source 3 2 0x0 src2. read source 2 1 0x0 src1. read source 1 0 0x0 dst. read destination offset: 0x0d access: user write field reset description
pxd20 microcontroller reference manual, rev. 1 31-18 freescale semiconductor preliminary?subject to change without notice 31.4.9 g2d_input 31.4.10 g2d_mask 31.4.11 g2d_blendercfg 31.4.12 g2d_blend_a0-3, gd2_blend_c0-7 offset: 0x0f access: user write field reset description 31?6 0x0 reserved 5 0x0 linemode. draw lines instead of rectangles 4 0x0 vgmode. input is assumed to be generated by v1 and uses slightly different protocol 3 0x0 copycoord. copy destination coordinates to unsent source coordinates too 2 0x0 scoord2. source coordinate 2 in input (for pattern) 1 0x0 scoord1. source coordinate 1 in input 0 0x0 color. constant color field in input offset: 0x10 access: user write field reset description 31?24 0x0 reserved 23?12 0x0 xmask. mask for second source x coordinate 11?0 0x0 ymask. mask for se cond source y coordinate offset: 0x11 access: user write field reset description 31?9 0x0 reserved 8 0x0 nomask. don't perform mask blending 7 0x0 obs_divalpha. obsolete: take divi der from temp0 alpha instead of temp1 6 0x0 ooalpha. one over alpha: divide temp0 by temp1 after blend program (inverse premultiply) 5 0x0 enable. enable blender 4?3 0x0 alphapasses. number of alpha passes 2?0 0x0 passes. number of passes
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-19 preliminary?subject to change without notice offset 0x14 (g2d_blend_a0) 0x15 (g2d_blend_a1) 0x16 (g2d_blend_a2) 0x17 (g2d_blend_a3) 0x18 (g2d_blend_c0) 0x19 (g2d_blend_c1) 0x1a (g2d_blend_c2) 0x1b (g2d_blend_c3) 0x1c (g2d_blend_c4) 0x1d (g2d_blend_c5) 0x1e (g2d_blend_c6) 0x1f (g2d_blend_c7) access: user write field reset description 31 0x0 const_d. constant used for src d 30 0x0 const_c. constant used for src c 29 0x0 const_b. constant used for src b 28 0x0 const_a. constant used for src a 27?25 0x0 src_d. source d register. see table 31-14 . 24?22 0x0 src_c. source c register. see table 31-14 . 21?19 0x0 src_b. source b register. see table 31-14 . 18?16 0x0 src_a. source a register. see table 31-14 . 15 0x0 inv_d. invert (1-x) argument d 14 0x0 inv_c. invert (1-x) argument c 13 0x0 inv_b. invert (1-x) argument b 12 0x0 inv_a. invert (1-x) argument a 11 0x0 ar_d. alpha replicate argument d 10 0x0 ar_c. alpha replicate argument c 9 0x0 ar_b. alpha replicate argument b 8 0x0 ar_a. alpha replicate argument a 7?6 0x0 dst_c. c*d result destination register see table 31-15 . 5?4 0x0 dst_b. a*b result destination register see table 31-15 . 3?2 0x0 dst_a. a*b op c*d result destination register see table 31-15 . 1?0 0x0 operation. 0x0 g2d_blendop_add 0x1 g2d_blendop_sub 0x2 g2d_blendop_min 0x3 g2d_blendop_max
pxd20 microcontroller reference manual, rev. 1 31-20 freescale semiconductor preliminary?subject to change without notice 31.4.13 vgv1_vtx0-1 31.4.14 vgv1_tileofs table 31-14. blend source value blend source 0x0 g2d_blendsrc_zero (one with invert) 0x1 g2d_blendsrc_source (paint) 0x2 g2d_blendsrc_destination 0x3 g2d_blendsrc_image (second texture) 0x4 g2d_blendsrc_temp0 0x5 g2d_blendsrc_temp1 0x6 g2d_blendsrc_temp2 0x7 g2d_blendsrc_mask (mask value with coverage replicated to all channels) table 31-15. blend destination value blend source 0x0 g2d_blendsrc_ignore (ignore destination) 0x1 g2d_blenddst_temp0 0x2 g2d_blenddst_temp1 0x3 g2d_blenddst_temp2 offset 0x20 (vgv1_vtx0) 0x21 (vgv1_vtx1) access: user write field reset description 31?16 0x0 vertex 0(1) y coordinate (s12.4) 15?0 0x0 vertex 0(1) x coordinate (s12.4) offset: 0x22 access: user write field reset description 31?25 0x0 reserved 24 0x0 the leftmost tile 23?12 0x0 tile y offset (u12) 11?0 0x0 tile x offset (u12)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-21 preliminary?subject to change without notice 31.4.15 vgv1_fill 31.4.16 vgv1_scissorx 31.4.17 vgv1_scissory 31.4.18 vgv1_cfg1 31.4.19 vgv1_cfg2 offset: 0x23 access: user write field reset description 31?1 0x0 reserved 0 0x0 inherit. inherit the winding counters to the next tile offset: 0x24 access: user write field reset description 31?27 0x0 reserved 26?16 0x0 right. scissor right edge 15?11 0x0 padding 10?0 0x0 left. scissor left edge offset: 0x25 access: user write field reset description 31?27 0x0 reserved 26?16 0x0 bottom. scissor bottom edge 15?11 0x0 padding 10?0 0x0 top. scissor top edge offset: 0x27 access: user write field reset description 31?1 0x0 reserved 0 0x0 windrule. polygon fill rule (0=non-zero, 1=odd-even)
pxd20 microcontroller reference manual, rev. 1 31-22 freescale semiconductor preliminary?subject to change without notice 31.4.20 vgv1_dirtybase 31.4.21 vgv1_cbase1 31.4.22 vgv1_ubase2 31.4.23 vgv2_c1x 31.4.24 vgv2_c1y offset: 0x28 access: user write field reset description 31?2 0x0 reserved 1?0 0x0 aamode. 0x0 none 0x1 16x edge aa 0x2 flipquad offset: 0x29 access: user write field reset description 31?0 0x0 dirty buffer base address offset: 0x2a access: user write field reset description 31?0 0x0 compressed buffer base address offset: 0x2b access: user write field reset description 31?0 0x0 uncompressed buffer base address offset: 0x40 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 implements hline by modifying c3x keeping c3y unchanged. float 1.6.17, typical range -1e9..1e9.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-23 preliminary?subject to change without notice 31.4.25 vgv2_c2x, vgv2_c2y 31.4.26 vgv2_c3x, vgv2_c3y 31.4.27 vgv2_c4x, vgv2_c4y 31.4.28 vgv2_c(1-4)xrel, vgv2_c(1-4)yrel offset: 0x41 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 implements vline by modifying c3y keeping c3x unchanged. float 1.6.17, typical range -1e9..1e9. offset 0x42 (vgv2_c2x) 0x43 (vgv2_c2y) access: user write field reset description 31?24 0x0 reserved 23?0 0x0 first controlpoint for cubic. float 1.6.17, typical range -1e9..1e9. offset 0x44 (vgv2_c3x) 0x45 (vgv2_c3y) access: user write field reset description 31?24 0x0 reserved 23?0 0x0 second controlpoint for cubic, first controlpoint for quadratic. float 1.6.17, typical range -1e9..1e9. offset 0x46 (vgv2_c4x) 0x47 (vgv2_c4y) access: user write field reset description 31?24 0x0 reserved 23?0 0x0 end point (also moveto point). float 1.6.17, typical range -1e9..1e9.
pxd20 microcontroller reference manual, rev. 1 31-24 freescale semiconductor preliminary?subject to change without notice 31.4.29 vgv2_xfxx 31.4.30 vgv2_xfyx 31.4.31 vgv2_xfxy 31.4.32 vgv2_xfyy offset 0x48 (vgv2_c1xrel) 0x49 (vgv2_c1yrel) 0x4a (vgv2_c2xrel) 0x4b (vgv2_c2yrel) 0x4c (vgv2_c3xrel) 0x4d (vgv2_c3yrel) 0x4e (vgv2_c4xrel) 0x4f (vgv2_c4yrel) access: user write field reset description 31?24 0x0 reserved 23?0 0x0 relative to last primitive end. float 1.6.17, typical range -1e9..1e9. offset: 0x50 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 user to surface transform matrix [r0,c0] (s ee usage). float 1.6.17, typical range -100..100. offset: 0x51 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 user to surface transform matrix [r1,c0] (s ee usage). float 1.6.17, typical range -100..100. offset: 0x52 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 user to surface transform matrix [r0,c1] (s ee usage). float 1.6.17, typical range -100..100.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-25 preliminary?subject to change without notice 31.4.33 vgv2_xfxa 31.4.34 vgv2_xfya 31.4.35 vgv2_xfstxx 31.4.36 vgv2_xfstyx 31.4.37 vgv2_xfstxy offset: 0x53 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 user to surface transform matrix [r1,c1] (s ee usage). float 1.6.17, typical range -100..100. offset: 0x54 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 user to surface transform matrix [r0,c2] (s ee usage). float 1.6.17, typical range -10000..10000. offset: 0x55 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 user to surface transform matrix [r1,c2] (s ee usage). float 1.6.17, typical range -10000..10000. offset: 0x56 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 stroke matrix [r0,c0] (see usa ge). float 1.6.17, typical range -100..100. offset: 0x57 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 stroke matrix [r1,c0] (see usa ge). float 1.6.17, typical range -100..100.
pxd20 microcontroller reference manual, rev. 1 31-26 freescale semiconductor preliminary?subject to change without notice 31.4.38 vgv2_xfstyy 31.4.39 vgv2_bboxminx, vgv2_bboxminy 31.4.40 vgv2_bboxmaxx, vgv2_bboxmaxy 31.4.41 vgv2_scale 31.4.42 vgv2_bias offset: 0x58 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 stroke matrix [r0,c1] (see usa ge). float 1.6.17, typical range -100..100. offset: 0x59 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 stroke matrix [r1,c1] (see usa ge). float 1.6.17, typical range -100..100. offset 0x5a (vgv2_bboxminx) 0x5b (vgv2_bboxminy) access: user write field reset description 31?24 0x0 reserved 23?0 0x0 bounding box minimum x(y) (origo at matrix origo). float 1.6.17, typical range -10000..10000 offset 0x5c (vgv2_bboxmaxx) 0x5d (vgv2_bboxmaxy) access: user write field reset description 31?24 0x0 reserved 23?0 0x0 bounding box maximum x(y) (origo at matrix origo). float 1.6.17, typical range -10000..10000 offset: 0x5e access: user write field reset description 31?24 0x0 reserved 23?0 0x0 scale for coord=incoord*scale+bias. float 1.6.17, typical range 0..1, normally 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-27 preliminary?subject to change without notice 31.4.43 vgv2_accuracy 31.4.44 vgv2_thinradius 31.4.45 vgv2_arccos 31.4.46 vgv2_arcsin 31.4.47 vgv2_arctan offset: 0x5f access: user write field reset description 31?24 0x0 reserved 23?0 0x0 bias for coord=incoord*scale+bias. float 1.6.17, typical range -1..1, normally 0 offset: 0x60 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 accuracy goal in pixels for curve splitting. float 1.6.17, typical range 0.25..1.0. offset: 0x61 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 screen space radius limit for strokes consi dered to be thin, typical range 0..1.0, normally 0. offset: 0x62 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 round cap smoothness (cos(roundangle), see usage). float 1.6.17, typical range 0.5..1. offset: 0x63 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 round cap smoothness (sin(roundangle), see usage). float 1.6.17, typical range -0.5..0.5.
pxd20 microcontroller reference manual, rev. 1 31-28 freescale semiconductor preliminary?subject to change without notice 31.4.48 vgv2_radius 31.4.49 vgv2_miter 31.4.50 vgv2_clip 31.4.51 vgv2_mode offset: 0x64 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 round cap smoothness (tan(roundangle), see us age). float 1.6.17, ty pical range 0.1..1.0. offset: 0x65 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 stroke radius (in user space). float 1.6.17, typical range 0.1..10000. offset: 0x66 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 miter limit (given as cosine of angle, see usage). float 1.6.17, typical range 0..1. offset: 0x68 access: user write field reset description 31?24 0x0 reserved 23?0 0x0 distance of clip edge from origo. fl oat 1.6.17, typical range 10..100000, normally 1024. offset: 0x6e access: user write field reset description 31?24 0x0 reserved 23?18 0x0 exponentadd. add value to output coordinate exponent s before float_to_int conversion. nonzero val- ues here scale the output coordinates and thereby the typical ranges in float registers above are modified. 17 0x0 simpleclip. disable some clip optimizations (in case they don't work in some cases).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-29 preliminary?subject to change without notice 31.4.52 vgv2_action 16 0x0 simplestroke. disable complex stro king cases (sometimes faster but less robust). currently only dis- ables crossed segments, may be expanded in the future. 15 0x0 symmetricjoins. symmetric two sided joins 14 0x0 dropother. drop primitives on others than left sides of bounding box 13 0x0 dropleft. drop primitives left of bounding box 12 0x0 openfill. allow open fill paths 11 0x0 nodots. disable drawing of dots for zerolenth segments 10 0x0 fullsplit. always split curves up to maxsplit limit 9 0x0 strokesplit. use stroke splitting mode (s hould be enabled when stroke is enabled) 8 0x0 stroke. enable stroke mode 7?6 0x0 join. stroke join mode 0x0 miter joins (both sides extended towards intersec tion. if angle is too small (compared to stmiter register) the miter is converted into a bevel. 0x1 round joins (smoothness depends on arcsin/arccos registers) 0x2 bevel joins (ends of both sides are connected with a single line) 5?4 0x0 cap. stroke cap mode 0x0 butt caps (straight line overlappin starting point) 0x1 round caps (smoothness depends on arcsin/arccos registers) 0x2 square caps (square centered on starting point) 3?0 0x0 maxsplit. limit of number of recursive splits for curves offset: 0x6f access: user write field reset description 31?4 0x0 reserved 3?0 0x0 triggers a drawing action using current coordinates 0x0 end previous path 0x1 end previous path, c1=c4, start new open subpath 0x2 end previous path, c1=c4, start new closed subpath 0x3 line c1,c4 0x4 cubic c1,c2,c3,c4 0x5 quadratic c1,c3,c4 0x6 smooth cubic c1,c4 0x7 smooth quadratic c1,c3,c4 0x8 half lineto c4=pos, c3=normal. 0x9 moveto open + half lineto c4=pos, c3=normal. 0xa moveto closed + half lineto c4=pos, c3=normal. 0xb end previous path, c1=c4, move but do not start a subpath 0xf end previous path and block following regwrites until all lines sent offset: 0x6e access: user write field reset description
pxd20 microcontroller reference manual, rev. 1 31-30 freescale semiconductor preliminary?subject to change without notice 31.4.53 vgv3_control 31.4.54 vgv3_mode 31.4.55 vgv3_writeaddr offset: 0x70 access: user write field reset description 31?24 0x0 reserved 23?21 0x0 dmiwaitbuf. if set: pause st ream reading until the given frame buffer (one hot encoded) is free 20 0x0 v0sync. if set: pause stream reading until sync signal received from v0 19 0x0 bcflush. if set: flush burst cache (full flush). shou ld be used when the command buffer(s) added with this control write use old memory that may potentiall y be in cache. can also be used to trigger flushes when textures etc are changed. 18 0x0 write. if set: write current stream address to location given by vgv3_writeaddr (can be used for polling state) 17 0x0 abort. if set: abort stream reading immediately (should not be used in normal operation) 16 0x0 pause. if set: pause stream reading after next marked packet 15?12 0x0 dmiwaitchmask. selects dmi channels which are checked for free buffer when non-zero dmiwait- buf is given 11?0 0x0 markadd. increment mark counter by this value. mark counter tells how many undread marked packets are in the stream. stream reading continues as long as mark counter is positive (and reading is not paused). offset: 0x71 access: user write field reset description 31?5 0x0 reserved 4 0x0 dmireset. if set, reset state of dmi interface (shou ld not be needed) 30x0 dmipausetype. if set, also input regwrites are blo cked (in addition to stream reading) when v0sync or dmiwaitbuf is set in vgv3_control (normally allways set to 0) 20x0 writeflush. if set memory writes are done straight to l2 to make sure they arrive to memory as soon as possible. 1 0x0 unused 0 0x0 flipendian. flip dwords read from memory from big-endian to little-endian offset: 0x72 access: user write field reset description 31?0 0x0 address where all status writes h appen. normally a single shared address used by the driver should be sufficient, but it is also possible to change this address in the data stream.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-31 preliminary?subject to change without notice 31.4.56 vgv3_write 31.4.57 vgv3_writeifpaused 31.4.58 vgv3_nextaddr 31.4.59 vgv3_nextcmd offset: 0x73 access: user write field reset description 31?0 0x0 write this value to vgv3_writeaddr. this can be us ed to report to the cpu how far in the stream reading has progressed offset: 0x74 access: user write field reset description 31?0 0x0 write this value to vgv3_writeaddr if reading is pau sed. this should be the last register write in a packet so that pause/mark counter state has been u pdated for the packet before the write condition com- pare happens. every marked packet should probably have this conditional write so that the cpu can detect when a pause request has been completed. offset: 0x75 access: user write field reset description 31?0 0x0 address of sub-stream packet to call (see vgv3_nextcmd register) offset: 0x76 access: user write field reset description 31?28 0x0 reserved 27?16 0x0 callcount. length of sub-stream packet in call in dwords. 15 0x0 mark. if set: mark counter is decreased by one when this packet ends. if it becomes zero reading is paused. 14?12 0x0 nextcmd. action to perform after this packet. 0x0 continue reading at current address, count gives size of next packet. 0x1 jump to calladdr, count gives size of next packet. 0x2 first call a sub-stream at calladdr for callcount dwords. then perform a continue. 0x3 not supported. 0x4 not supported. 0x5 abort reading. this ends the stream. normally stream can just be paused (or automatically pauses at the end) which avoids any data being lost. 11?0 0x0 count. length of next packet in dwords.
pxd20 microcontroller reference manual, rev. 1 31-32 freescale semiconductor preliminary?subject to change without notice 31.4.60 vgv3_vgbypass 31.4.61 vgv3_writes8, vgv3_writes16, vgv3_writes32, vgv3_writef32, vgv3_writeraw 31.4.62 vgv3_writedmi 31.4.63 vgv3_last offset: 0x77 access: user write field reset description 31?1 0x0 reserved 0 0x0 when set, bypass v1 and v2, i.e. use only v3+2d (when v1+v2 cloks disabled). offset 0x78 (vgv3_writes8) 0x79 (vgv3_writes16) 0x7a (vgv3_writes32) 0x7b (vgv3_writef32) 0x7c (vgv3_writeraw) access: user write field reset description 31?27 0x0 reserved 26?24 0x0 format. lower 3 bits of address specifies the format (and each format effectively maps to a different vgv3_write register). 0x0 signed 8 bit data (4 writes per data dword) => vgv2-float 0x1 signed 16 bit data (2 writes per data dword) => vgv2-float 0x2 signed 32 bit data => vgv2-float 0x3 ieee 32-bit floating point => vgv2-float 0x4 no converson 23?20 0x0 action. if nonzero: enable action mode where this va lue is sent to vgv2_action register at end of each loop. 19?16 0x0 loop. if nonzero: enable looping mode where addr is reset after every count writes. 15?8 0x0 count. count of how many register writes to do. 7?0 0x0 addr. start register address for burst offset: 0x7d access: user write field reset description 31?7 0x0 reserved 6?4 0x0 buffer. set the frame buffer buffer as done in dmi outputs 3?0 0x0 chanmask. frame buffer 'buffer' will be displayed on masked dmi channels
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-33 preliminary?subject to change without notice 31.4.64 fbc_base 31.4.65 fbc_data 31.4.66 fbc_width 31.4.67 fbc_height 31.4.68 fbc_stride offset: 0x7f access: user write field reset description 31?1 0x0 reserved 0 0x0 just a dummy register used to check if address is in vgv3 range offset: 0x84 access: user write field reset description 31?0 0x0 fast buffer clears base address offset: 0x86 access: user write field reset description 31?0 0x0 32-bit clear value offset: 0x88 access: user write field reset description 31?11 0x0 reserved 10?0 0x0 width (internal value is value + 1) offset: 0x8a access: user write field reset description 31?11 0x0 reserved 10?0 0x0 height (internal value is value + 1)
pxd20 microcontroller reference manual, rev. 1 31-34 freescale semiconductor preliminary?subject to change without notice 31.4.69 fbc_start 31.4.70 g2d_const0-7 31.4.71 gradw_const0-b offset: 0x8c access: user write field reset description 31?11 0x0 reserved 10?0 0x0 stride (internal value is value + 1) offset: 0x8e access: user write field reset description 31?1 0x0 reserved 0 0x0 dummy. just write anything offset 0xb0 (g2d_const0) 0xb1 (g2d_const1) 0xb2 (g2d_const2) 0xb3 (g2d_const3) 0xb4 (g2d_const4) 0xb5 (g2d_const5) 0xb6 (g2d_const6) 0xb7 (g2d_const7) access: user write field reset description 31?0 0x0 blender constant in 32-bit argb format offset 0xc0 (gradw_const0) 0xc1 (gradw_const1) 0xc2 (gradw_const2) 0xc3 (gradw_const3) 0xc4 (gradw_const4) 0xc5 (gradw_const5) 0xc6 (gradw_const6) 0xc7 (gradw_const7) 0xc8 (gradw_const8) 0xc9 (gradw_const9) 0xca (gradw_consta) 0xcb (gradw_constb) access: user write field reset description 31?16 0x0 reserved 15?0 0x0 constant value in 1.5.10 floating point
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-35 preliminary?subject to change without notice 31.4.72 g2d_gradient 31.4.73 gradw_texcfg offset: 0xd0 access: user write field reset description 31?9 0x0 reserved 8 0x0 sel. select register window for gradient and texture unit 7 0x0 enable2.enable second texture 6 0x0 enable. enable gradient and texturing operation 5?3 0x0 instructions2. number of instructions for pass 2 - 1 2?0 0x0 instructions. number of instructions for pass 1 - 1 offset: 0xd1 access: user write field reset description 31?30 0x0 reserved 29 0x0 swapbits. swap order of bits or nibbles in bytes 28 0x0 tex2d. 2d texture 27 0x0 swaprb. swap red and blue components after conversion 26 0x0 swapall. argb -> bgra swap 25 0x0 swapbytes. swap read bytes in 32-bit value before conversion 24 0x0 swapwords. swap read words in 32-bit value before conversion 23 0x0 premultiply. premulti ply colors with alpha 22 0x0 srgb. texture is in srgb format 21 0x0 bilin. 20?19 0x0 wrapv. 0x0 clamp 0x1 repeat 0x2 mirror 0x3 border 18?17 0x0 wrapu. 0x0 clamp 0x1 repeat 0x2 mirror 0x3 border 16 0x0 tiled.
pxd20 microcontroller reference manual, rev. 1 31-36 freescale semiconductor preliminary?subject to change without notice 31.4.74 gradw_texsize 31.4.75 gradw_texbase 31.4.76 gradw_bordercolor 15?12 0x0 format 0x0 g2d_1 (foreground and background) 0x1 g2d_1bw (black and white) 0x2 g2d_4 0x3 g2d_8 (blue when written) 0x4 g2d_4444 0x5 g2d_1555 0x6 g2d_0565 0x7 g2d_8888 0x8 g2d_yuy2 0x9 g2d_uyvy 0xa g2d_yvyu 0xb g2d_4444_rgba 0xc g2d_5551_rgba 0xd g2d_8888_rgba 0xe g2d_a8 0xf g2d_88 (alpha and blue) 11?0 0x0 stride. offset: 0xd2 access: user write field reset description 31?22 0x0 reserved 21?11 0x0 texture height 10?0 0x0 texture width offset: 0xd3 access: user write field reset description 31?0 0x0 texture base address offset: 0xd4 access: user write field reset description 31?0 0x0 texture border color in 32-bit argb format offset: 0xd1 access: user write field reset description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-37 preliminary?subject to change without notice 31.4.77 gradw_inst0-7 31.4.78 g2d_xy 31.4.79 g2d_widthheight offset 0xe0 (gradw_inst0) 0xe1 (gradw_inst1) 0xe2 (gradw_inst2) 0xe3 (gradw_inst3) 0xe4 (gradw_inst4) 0xe5 (gradw_inst5) 0xe6 (gradw_inst6) 0xe7 (gradw_inst7) access: user write field reset description 31 0x0 reserved 30?29 0x0 opcode. 0x0 dot 0x1 rcp 0x2 sqrtmul 0x3 sqrtadd 28?25 0x0 destination, 0xxx = temp, 100x = output 24?20 0x0 source a, 1xxxx = constant, 00xxx = temp, 0100x = output 19?15 0x0 source b, 1xxxx = constant, 00xxx = temp, 0100x = output 14?10 0x0 source c, 1xxxx = constant, 00xxx = temp, 0100x = output 9?5 0x0 source d, 1xxxx = constant, 00xxx = temp, 0100x = output 4?0 0x0 source e, 1xxxx = constant, 00xxx = temp, 0100x = output offset: 0xf0 access: user write field reset description 31?28 0x0 reserved 27?16 0x0 primitve x 15?12 0x0 padding 11?0 0x0 primitive y offset: 0xf1 access: user write field reset description 31?28 0x0 reserved 27?16 0x0 primitve width
pxd20 microcontroller reference manual, rev. 1 31-38 freescale semiconductor preliminary?subject to change without notice 31.4.80 g2d_sxy, g2d_sxy2 31.4.81 g2d_vgspan 31.4.82 g2d_idle 31.4.83 g2d_color 15?12 0x0 padding 11?0 0x0 primitive height offset 0xf2 (g2d_sxy) 0xf3 (g2d_sxy2) access: user write field reset description 31?27 0x0 reserved 26?16 0x0 primitve source x 15?11 0x0 padding 10?0 0x0 primitive source y offset: 0xf4 access: user write field reset description 31?20 0x0 reserved 19?16 0x0 coverage value 15?12 0x0 padding 11?0 0x0 span width offset: 0xfe access: user write field reset description 31?3 0x0 reserved 2 0x0 send signal to v3 after flush 1 0x0 flush burst cache 0 0x0 send irq after flush offset: 0xf1 access: user write field reset description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-39 preliminary?subject to change without notice 31.5 mmu command stream registers this section provides a detailed description of the gf x2d internal registers that are only accessible via g12_mmucommandstream. offset: 0xff access: user write field reset description 31?0 0x0 color in 32-bit argb format table 31-16. mmu command stream registers offset register access reset value section/page 0x040 mh_mmu_config?mmu configuration r/w 0x0000_0000 31.5.1/31-40 0x041 mh_mmu_va_range?mmu virtual base address and range r/w 0x0000_0000 31.5.2/31-40 0x042 mh_mmu_pt_base?mmu page table base address r/w 0x0000_0000 31.5.3/31-40 0x043 mh_mmu_page_fault?mmu page fault r 0x0000_0000 31.5.4/31-41 0x044 mh_mmu_tran_error?mmu transaction error address r/w 0x0000_0000 31.5.5/31-41 0x045 mh_mmu_invalidate?mmu invalidate w 0x0000_0000 31.5.6/31-41 0x046 mh_mmu_mpu_base?mpu base address r/w 0x0000_0000 31.5.7/31-42 0x047 mh_mmu_mpu_end?mpu end address r/w 0x0000_0000 31.5.8/31-42 0xa40 mh_arbiter_config?arbiter configuration r/w 0x07c8_6590 31.5.9/31-42 0xa41 mh_clnt_axi_id_reuse?client axi ids r/w 0x0000_1243 31.5.10/31-43 0xa42 mh_interrupt_mask?interrupt mask r/w 0x0000_0000 31.5.11/31-44 0xa43 mh_interrupt_status?in terrupt status r/w 0x0000_0000 31.5.12/31-44 0xa44 mh_interrupt_clear?interrupt clear w 0x0000_0000 31.5.13/31-44 0xa45 mh_axi_error?axi read/write error status r 0x0000_0000 31.5.14/31-44 0xa46 mh_perfcounter0_select?performance counter 0 select r/w 0x0000_00ff 31.5.15/31-45 0xa47 mh_perfcounter0_config?performance counter 0 config r/w 0x0000_0000 31.5.16/31-45 0xa48 mh_perfcounter0_low?performance counter 0 lower 32 bits r 0x0000_0000 31.5.17/31-45 0xa49 mh_perfcounter0_hi?performance counter 0 upper 16 bits r 0x0000_0000 31.5.18/31-46 0xa4a mh_perfcounter1_select?performance counter 1 select r/w 0x0000_00ff 31.5.19/31-46 0xa4b mh_perfcounter1_config?performance counter 1 config r/w 0x0000_0000 31.5.20/31-46 0xa4c mh_perfcounter1_low?performance counter 1 lower 32 bits r 0x0000_0000 31.5.21/31-46 0xa4d mh_perfcounter1_hi?performance counter 1 upper 16 bits r 0x0000_0000 31.5.22/31-46 0xa4e mh_debug_ctrl?debug control r/w 0x0000_0000 31.5.23/31-46 0xa4f mh_debug_data?debug data r 0x0000_0000 31.5.24/31-47 0xa50 mh_axi_halt_control?axi halt control r/w 0x0000_0000 31.5.25/31-47
pxd20 microcontroller reference manual, rev. 1 31-40 freescale semiconductor preliminary?subject to change without notice 31.5.1 mh_mmu_config 31.5.2 mh_mmu_va_range 31.5.3 mh_mmu_pt_base offset: 0x040 access: user read/write field reset description 31?26 0x0 reserved 25?24 0x0 specifies paw client behavior for mmu lookups. see table 31-17 . 23?22 0x0 specifies tcr client behavior for mmu lookups. see table 31-17 . 21?20 0x0 specifies vgtr1 client behavior for mmu lookups. see ta b l e 3 1 - 1 7 . 19?18 0x0 specifies vgtr0 client behavior for mmu lookups. see ta b l e 3 1 - 1 7 . 17?16 0x0 specifies cpr4 client behavior for mmu lookups. see table 31-17 . 15?14 0x0 specifies cpr3 client behavior for mmu lookups. see table 31-17 . 13?12 0x0 specifies cpr2 client behavior for mmu lookups. see table 31-17 . 11?10 0x0 specifies cpr1 client behavior for mmu lookups. see table 31-17 . 9?8 0x0 specifies cpr0 client behavior for mmu lookups. see table 31-17 . 7?6 0x0 specifies cpw client behavior for mmu lookups. see table 31-17 . 5?4 0x0 specifies rbw client behavior for mmu lookups. see table 31-17 . 3?2 0x0 padding 1 0x0 split_mode_enable. reserves 8 translation buffer entries for use by the tc client 0 0x0 mmu_enable. enables mmu; if disabled all mmu checks are bypassed and pa = va table 31-17. mmu behavior value description 0x0 never translate, pa = va 0x1 translate if va is in va range, otherwise pa = va 0x2 only translate if va is in va range, else page fault offset: 0x041 access: user read/write field reset description 31?12 0x0 virtual base address (va_base[31:12]) aligned to a 4kb page boundary (va_base[11:0]=0). 11?0 0x0 number of 64 kb regions mapped, up to 256mb
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-41 preliminary?subject to change without notice 31.5.4 mh_mmu_page_fault 31.5.5 mh_mmu_tran_error 31.5.6 mh_mmu_invalidate offset: 0x042 access: user read/write field reset description 31?12 0x0 page table base address (pt_base[31:12]) aligned to a 4kb page boundary (pt_base[11:0]=0). 11?0 0x0 alignment, zeroed. offset: 0x043 access: user read field reset description 31?12 0x0 va[31:12] of lookup that caused the page fault 11 0x0 page table entry not valid for write operation 10 0x0 page table entry not valid for read operation 9 0x0 client va not in va range 8 0x0 client pa not in mpu range 7 0x0 padding bit 6?4 0x0 axi id of lookup that caused the page fault 3?2 0x0 reports programmed client behavior bits at the time of page fault. see table 31-17 . 1 0x0 operation type, 0 = read, 1 = write 0 0x0 page fault occured offset: 0x044 access: user read/write field reset description 31?5 0x0 address location (tran_error[31:5]) used for dummy reads or writes in the event of a page fault, aligned on a 32-bit boundary (tran_error[4:0]=0). 14?0 0x0 alignment, zeroed.
pxd20 microcontroller reference manual, rev. 1 31-42 freescale semiconductor preliminary?subject to change without notice 31.5.7 mh_mmu_mpu_base 31.5.8 mh_mmu_mpu_end 31.5.9 mh_arbiter_config offset: 0x045 access: user read/write field reset description 31?2 0x0 reserved 10x0 invalidate_all. if split_mode_enable is set, clears all non-tc tag valid bits; else clears all tag valid bits. read: 0 invalidate not in progress. 1 invalidate in progress, awaiting spte fetch to complete. write: 0 no effect, only cleared by hardware 1 initiate invalidate process. 00x0 invalidate_tc. if split_mode_enable is set, clea rs all tc tag valid bits; else does nothing. read: 0 invalidate not in progress. 1 invalidate in progress, awaiting spte fetch to complete. write: 0 no effect, only cleared by hardware 1 initiate invalidate process. offset: 0x046 access: user read/write field reset description 31?12 0x0 memory protection unit base address (mpu_base[31:12]) aligned to a 4kb page boundary (mpu_base[11:0]=0). 11?0 0x0 alignment, zeroed. offset: 0x047 access: user read/write field reset description 31?12 0x0 memory protection unit end address (mpu _end[31:12]) aligned to a 4kb page boundary (mpu_end[11:0]=0). 11?0 0x0 alignment, zeroed. offset: 0xa40 access: user read/write field reset description 31?27 0x0 reserved. 26 0x1 pa_clnt_enable. enables pa client requests
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-43 preliminary?subject to change without notice 31.5.10 mh_clnt_axi_id_reuse 25 0x1 rb_clnt_enable. enables rb client requests 24 0x1 tc_clnt_enable. enables tc client requests 23 0x1 vgt_clnt_enable. enables vgt client requests 22 0x1 cp_clnt_enable. enables cp client requests 21?16 0x8 when in_flight_limit_enable is enabled, specif ies the maximum number of outstanding requests allowed by mh (0 = no limit) 15 0x0 in_flight_limit_enable. enable s limit of outstanding requests 14 0x1 tc_arb_hold_enable. holds arbiter for 4 cycles when tc wins arbitration, same page and bank requests exist and tcd is full 13 0x1 tc_reorder_enable. enables tc reordering queue. requires l1_arb_ enable to be set also 12?10 0x1 sdram page size--rbc or brc formats assumed for sdram configuration 000 0.5 kb 001 1 kb 010 2 kb 011 4 kb 100 8 (4) kb 101 16 (4) kb 9 0x0 l2_arb_control. selects algorithm for level 2 arbitration 0 least recently used client 1 fixed priority: [cp->pa->vgt->tc->rb] 8 0x1 l1_arb_hold_enable. selects behav ior when arbiter is back pressured 0 forces re-arbitration. 1 holds arbiter on current winner. 7 0x1 l1_arb_enable. enables level 1 arbitration for same page and bank addresses 6 0x0 same_page_granularity. specifies granularity of same_page_limit 0granularity = 2 1 granularity = 16 5?0 0x10 when l1_arb_enable is enabled, specifies the number of same page requests allowed before re-arbi- tration: for same_page_granularity = 0: same page requests = [same_page_limit x 2] + 1 for same_page_granularity = 1: same page requests = [same_page_limit x 16] + 1 (0 = no limit) offset: 0xa41 access: user read/write field reset description 31?15 0x0 reserved 14?12 0x1 paw_id. pa write client axi id 11 0x0 padding bit 10?8 0x2 mmur_id. mmu read client axi id offset: 0xa40 access: user read/write field reset description
pxd20 microcontroller reference manual, rev. 1 31-44 freescale semiconductor preliminary?subject to change without notice 31.5.11 mh_interrupt_mask 31.5.12 mh_interrupt_status 31.5.13 mh_interrupt_clear 31.5.14 mh_axi_error 7 0x0 padding bit 6?4 0x4 rbw_id. rb write client axi id 3 0x0 padding bit 2?0 0x3 cpw_id. cp write sub-client axi id offset: 0xa42 access: user read/write field reset description 31?3 0x0 reserved 2 0x0 enables mmu page fault interrupt 1 0x0 enables axi write error interrupt 0 0x0 enables axi read error interrupt offset: 0xa43 access: user read/write field reset description 31?3 0x0 reserved 2 0x0 mmu page fault interrupt status 1 0x0 axi write error interrupt status 0 0x0 axi read error interrupt status offset: 0xa44 access: user read/write field reset description 31?3 0x0 reserved 2 0x0 clears mmu page fault interrupt 1 0x0 clears axi write error interrupt 0 0x0 clears axi read error interrupt offset: 0xa41 access: user read/write field reset description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-45 preliminary?subject to change without notice 31.5.15 mh_perfcounter0_select 31.5.16 mh_perfcounter0_config 31.5.17 mh_perfcounter0_low offset: 0x045 access: user read field reset description 31?8 0x0 reserved. 7 0x0 axi_write_error. axi write error 6?4 0x0 axi_write_id. axi id of write error: cpw = mh_clnt_axi_id_reuse.cpw_id rbw = mh_clnt_axi_id_reuse.rbw_id paw = mh_clnt_axi_id_reuse.paw_id 3 0x0 axi_read_error. axi read error 2?0 0x0 axi_read_id. axi id of read error: 000 cpr0 001 cpr1 010 cpr2 011 cpr3 100 cpr4 101 vgtr0 110 vgtr1 111 tcr mmur = mh_clnt_axi_i d_reuse.mmur_id offset: 0xa46 access: user read/write field reset description 31?8 0x0 reserved 7?0 0xff counter select. see table 31-18 . offset: 0xa47 access: user read/write field reset description 31?8 0x0 reserved 7?0 0x0 n value used in nth access and n entry measurements only. offset: 0xa48 access: user read field reset description 31?0 0x0 lower 32 bits of performance count
pxd20 microcontroller reference manual, rev. 1 31-46 freescale semiconductor preliminary?subject to change without notice 31.5.18 mh_perfcounter0_hi 31.5.19 mh_perfcounter1_select 31.5.20 mh_perfcounter1_config 31.5.21 mh_perfcounter1_low 31.5.22 mh_perfcounter1_hi 31.5.23 mh_debug_ctrl offset: 0xa49 access: user read field reset description 31?16 0x0 reserved 15?0 0x0 upper 16 bits of performance count offset: 0xa4a access: user read/write field reset description 31?8 0x0 reserved 7?0 0xff counter select. see table 31-18 . offset: 0xa4b access: user read/write field reset description 31?8 0x0 reserved 7?0 0x0 n value used in nth access and n entry measurements only. offset: 0xa4c access: user read field reset description 31?0 0x0 lower 32 bits of performance count offset: 0xa4d access: user read field reset description 31?16 0x0 reserved 15?0 0x0 upper 16 bits of performance count
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-47 preliminary?subject to change without notice 31.5.24 mh_debug_data 31.5.25 mh_axi_halt_control offset: 0xa4e access: user read/write field reset description 31?6 0x0 reserved 5?0 0x0 debug data index offset: 0xa4f access: user read field reset description 31?0 0x0 debug data offset: 0xa50 access: user read/write field reset description 31?1 0x0 reserved 0 0x0 axi_halt. read: 0 axi halt not acknowledged. 1 axi halt acknowledged. write: 0 no effect. cleared by reset. must wait for axi halt acknowledgment before initiating reset. 1 initiate axi halt request.
pxd20 microcontroller reference manual, rev. 1 31-48 freescale semiconductor preliminary?subject to change without notice 31.5.26 performance counters table 31-18. performance counters select value counter name 0x00 cp_r0_requests 0x01 cp_r1_requests 0x02 cp_r2_requests 0x03 cp_r3_requests 0x04 cp_r4_requests 0x05 cp_total_read_requests 0x06 cp_w_16b_requests 0x07 cp_w_32b_requests 0x08 cp_total_write_requests 0x09 cp_total_requests 0x0a cp_data_bytes_written 0x0b cp_write_clean_responses 0x0c cp_r0_read_bursts_received 0x0d cp_r1_read_bursts_received 0x0e cp_r2_read_bursts_received 0x0f cp_r3_read_bursts_received 0x10 cp_r4_read_bursts_received 0x11 cp_total_read_bursts_received 0x12 cp_r0_data_beats_read 0x13 cp_r1_data_beats_read 0x14 cp_r2_data_beats_read 0x15 cp_r3_data_beats_read 0x16 cp_r4_data_beats_read 0x17 cp_total_data_beats_read 0x18 vgt_r0_requests 0x19 vgt_r1_requests 0x1a vgt_total_requests 0x1b vgt_r0_read_bursts_received 0x1c vgt_r1_read_bursts_received 0x1d vgt_total_read_bursts_received 0x1e vgt_r0_data_beats_read 0x1f vgt_r1_data_beats_read 0x20 vgt_total_data_beats_read 0x21 tc_16b_requests 0x22 tc_32b_requests 0x23 tc_total_requests 0x24 tc_roq_requests 0x25 tc_info_sent 0x26 tc_read_bursts_received 0x27 tc_data_beats_read
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-49 preliminary?subject to change without notice 0x28 tcd_bursts_read 0x29 rb_requests 0x2a rb_data_bytes_written 0x2b rb_write_clean_responses 0x2c pa_requests 0x2d pa_data_bytes_written 0x2e pa_write_clean_responses 0x2f?0x36 axi_read_requests_id_0-7 0x37 axi_total_read_requests 0x38?0x3f axi_read_request_data_beats_id_0-7 0x40 axi_total_read_request_data_beats 0x41?0x48 axi_write_requests_id_0-7 0x49 axi_total_write_requests 0x4a?0x51 axi_total_requests_id_0-7 0x52 axi_total_requests 0x53?0x5a axi_read_channel_bursts_id_0-7 0x5b axi_read_channel_total_bursts 0x5c?0x63 axi_read_channel_data_beats_read_id_0-7 0x64 axi_read_channel_total_data_beats_read 0x65?0x6c axi_write_channel_bursts_id_0-7 0x6d axi_write_channel_total_bursts 0x6e?0x75 axi_write_channel_data_bytes_written_id_0-7 0x76 axi_write_channel_total_data_bytes_written 0x77?0x7e axi_write_response_channel_responses_id_0-7 0x7f axi_write_response_channel_total_responses 0x80 total_mmu_misses 0x81 mmu_read_misses 0x82 mmu_write_misses 0x83 total_mmu_hits 0x84 mmu_read_hits 0x85 mmu_write_hits 0x86 split_mode_tc_hits 0x87 split_mode_tc_misses 0x88 split_mode_non_tc_hits 0x89 split_mode_non_tc_misses 0x8a stall_awaiting_tlb_miss_fetch 0x8b mmu_tlb_miss_read_bursts_received 0x8c mmu_tlb_miss_data_beats_read 0x8d cp_cycles_held_off 0x8e vgt_cycles_held_off 0x8f tc_cycles_held_off table 31-18. performance counters (continued) select value counter name
pxd20 microcontroller reference manual, rev. 1 31-50 freescale semiconductor preliminary?subject to change without notice 0x90 tc_roq_cycles_held_off 0x91 tc_cycles_held_off_tcd_full 0x92 rb_cycles_held_off 0x93 pa_cycles_held_off 0x94 total_cycles_any_clnt_held_off 0x95 tlb_miss_cycles_held_off 0x96 axi_read_request_held_off 0x97 axi_write_request_held_off 0x98 axi_request_held_off 0x99 axi_request_held_off_inflight_limit 0x9a axi_write_data_held_off 0x9b cp_same_page_bank_requests 0x9c vgt_same_page_bank_requests 0x9d tc_same_page_bank_requests 0x9e tc_arb_hold_same_page_bank_requests 0x9f rb_same_page_bank_requests 0xa0 total_same_page_bank_requests 0xa1 cp_same_page_bank_requests_killed_fairness_limit 0xa2 vgt_same_page_bank_requests_killed_fairness_limit 0xa3 tc_same_page_bank_requests_killed_fairness_limit 0xa4 rb_same_page_bank_requests_killed_fairness_limit 0xa5 total_same_page_bank_killed_fairness_limit 0xa6 total_mh_read_requests 0xa7 total_mh_write_requests 0xa8 total_mh_requests 0xa9 mh_busy 0xaa cp_nth_access_same_page_bank_sequence 0xab vgt_nth_access_same_page_bank_sequence 0xac tc_nth_access_same_page_bank_sequence 0xad rb_nth_access_same_page_bank_sequence 0xae tc_roq_n_valid_entries 0xaf arq_n_entries 0xb0 wdb_n_entries 0xb1 mh_read_latency_start 0xb2 mh_read_latency_post 0xb3 mc_total_read_requests 0xb4 elapsed_clk_cycles 0xff none (defaut value, not counting) table 31-18. performance counters (continued) select value counter name
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-51 preliminary?subject to change without notice 31.6 functional description figure 31-1 shows the gfx2d top level block diagram. 31.6.1 bus interface the bus interface has a 32-bit ahb sl ave port and a 64-bit axi master port. 31.6.2 input unit this unit handles the command stream input through the slave inte rface, status register reads, and external interrupt generation with programmabl e interrupt handler. it connects to the slave por t of the bus interface unit where the cpu can feed in commands to the graphics processor. 31.6.3 arbiter the arbiter sits between the rendering core and the bus interface, handling pr ioritized arbitration of memory reads and writes. 31.6.4 burst cache the burst cache handles the main memory traffic for the rendering pipeline. it is composed of 256-bit blocks. the burst cache intr insically works with pixel groups and caches re cently used pixels. it also stops pixels proceeding in the pixel pipeline, if the same memory lo cation already has a pending write coming from the pixel pipeline. this pr otection is done separately for the various 2d and vg buffers. 31.6.5 2d+vg unit this unit handles all 2d-bitmap relate d operations. it has a rectangle rast erizer, which generates the source and destination x and y coor dinates. the rasterizer can also operate in right-to-left and/or bottom-to-top direction. raster operation (rop) is supported between the source, pattern/mask a nd destination data. the data is then written to the destination bitmap. separate rops can be used for ma sked and unmasked pixels (rop4). the color can also be alpha blended with the destination with either pe r pixel or constant alpha value. this unit also contains a vector graphics rasterizer, which is capable of raster izing anti-aliased complex polygons. 31.6.6 2d+vg unit level architecture figure 31-13 shows the architecture of the 2d+vg unit.
pxd20 microcontroller reference manual, rev. 1 31-52 freescale semiconductor preliminary?subject to change without notice figure 31-13. 2d+vg architecture 31.6.6.1 command handler the purpose of the command handler is to read co mmand streams from memory and send them onwards to the vector graphics geometry engi ne and other units. these streams can be used like display lists in 3d graphics. the unit supports three da ta streams from which register addr esses and data can be read in various formats. multiple streams can also be used to implement subroutin es in the display list. in addition the unit has a stream marker mechanis m that can be used to extend an already executing command list and to report progress status back to the cpu through memory writes. fina lly the unit can perform conditional register writes base on feedback information from the geometry engi ne. this can be used to perform bounding box tests and hardware based tiling. 31.6.6.2 geometry engine the vector graphics geom etry engine performs geometry operati ons on primitives. input primitives can be lines or curves (cubic/quadratic) specified with ab solute or relative coordinates in a user specified coordinate system. curves are first sp lit into line segments according to a given accuracy goal. after this the resulting line path can optionally be converted into a thick stroke with possi bly rounded joins and caps. 2d unit vector graphics vector graphics rasterizer geometry engine gradient / texturing spans with alpha, state writes pixel color and alpha pixel coordinates and alpha texture fetches color reads and writes command stream fetch, vector data command handler memory arbiter vector commands, state writes edges, state writes memory bus accesses state writes from cpu or geometry engine
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 31-53 preliminary?subject to change without notice the geometry engine can also pe rform bounding box tests where results ar e relayed back to the command handler. 31.6.6.3 rasterizer the vector graphics rasterizer handles rasterizing arbitrary ve ctor graphic shapes to spans for the 2d unit. 31.6.6.4 2d unit the 2d unit performs block based 2d operations like fills and blits. it also manages drawing spans from the vector graphics rasterizer whic h are internally handled as one pixe l height rectangles. if required, it also pipes the pixels through the gradient and texturing unit. 31.6.6.5 gradient and texturing unit the gradient and texturing unit calculates color and al pha values for pixels fr om pixel coordinates and alpha according to the required gradie nt or texturing mode. internally th e unit is a very simple cpu with at maximum 8 instructions per pi xel and a flexible alu to perfor m all necessary operations like dot products, square root and di vision. the texturing part ha ndles fetching textures fr om memory and filtering them.
pxd20 microcontroller reference manual, rev. 1 31-54 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 32-1 preliminary?subject to change without notice chapter 32 periodic interrupt timer (pit) 32.1 introduction the pit is an array of timers that can be used to raise interrupts and trigger dma channels. this device has one pit module with eight timer channels (pit channels 0 through 7). these are connected to the trigger input 0 through 7 of the dma_mux. figure 32-1 shows the pit block diagram. figure 32-1. pit block diagram the main features of this block are: ? timers can generate dma trigger pulses ? timers can generate interrupts ? all interrupts are maskable ? independent timeout periods for each timer 32.2 signal description the pit module has no external pins. timer 7 timer 0 . . . pit registers peripheral interrupts peripheral pit . . . triggers bus bus clock
pxd20 microcontroller reference manual, rev. 1 32-2 freescale semiconductor preliminary?subject to change without notice 32.3 memory map and register description this section provides a detailed description of all registers accessi ble in the pit module. 32.3.1 memory map table 32-1 gives an overview on all pit registers. note register address = base address + a ddress offset, where the base address is defined at the mcu level and the a ddress offset is defined at the module level. reserved registers will read as 0, writes will have no effect. 32.3.2 register descriptions this section describes in address order all the pit registers and their individual bits. table 32-1. pit memory map address offset use location 0x000 pit module control register on page 32-3 0x004?0x0fc reserved 0x100?0x10c timer channel 0 see table 32-2 0x110?0x11c timer channel 1 0x120?0x12c timer channel 2 0x130?0x13c timer channel 3 0x140?0x14c timer channel 4 0x150?0x15c timer channel 5 0x160?0x16c timer channel 6 0x170?0x17c timer channel 7 0x0180?0x1fc reserved table 32-2. timer channel n address offset use location channel + 0x00 timer load value register on page 32-3 channel + 0x04 current timer value register on page 32-4 channel + 0x08 timer control register on page 32-5 channel + 0x0c timer flag register on page 32-6
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 32-3 preliminary?subject to change without notice 32.3.2.1 pit module control register (pitmcr) this register controls whether the timer clocks s hould be enabled and whether the timers should run in debug mode. table 32-3. pitmcr field descriptions 32.3.2.2 timer load value register (ldval) these registers select the timeout period for the timer interrupts. offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000 0 0 0 0 0 mdis frz w reset0000000000000010 figure 32-2. pit module co ntrol registers (pitmcr) field description mdis module disable. this is used to disable the module clock. this bit should be enabled before any other setup is done. 0 clock for pit timers is enabled 1 clock for pit timers is disabled (default) frz freeze. allows the timers to be stopped when the device enters debug mode. 0 = timers continue to run in debug mode. 1 = timers are stopped in debug mode.
pxd20 microcontroller reference manual, rev. 1 32-4 freescale semiconductor preliminary?subject to change without notice 32.3.2.3 current timer value register (cval) these registers indicate th e current timer position. offset channel_base + 0x00 access: read/write 0123456789101112131415 r tsv31 tsv30 tsv29 tsv28 tsv27 tsv26 tsv25 tsv24 t sv23 tsv22 tsv21 tsv20 tsv19 tsv18 tsv17 tsv16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv15 tsv14 tsv13 tsv12 tsv11 tsv10 tsv9 tsv8 tsv7 tsv6 tsv5 tsv4 tsv3 tsv2 tsv1 tsv0 w reset0000000000000000 figure 32-3. timer load value register (ldval) table 32-4. ldval field descriptions field description tsv n time start value bits. these bits set the timer start value. the timer will count down until it reaches 0, then it will generate an interrupt and load this register value again. writing a new value to this register will not restart the timer, instead the value will be loaded once the timer expires. to abort the current cycle and start a timer peri od with the new value, the timer must be disabl ed and enabled again (see figure 32-8 ).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 32-5 preliminary?subject to change without notice 32.3.2.4 timer contro l register (tctrl) these register contain the control bits for each timer. offset channel_base + 0x04 access: read/write 0123456789101112131415 r tvl31 tvl30 tvl29 tvl28 tvl27 tvl26 tvl25 tvl24 tvl23 tvl22 tvl21 tvl20 tvl19 tvl18 tvl17 tvl16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl15 tvl14 tvl13 tvl12 tvl11 tvl10 tvl9 tvl8 tvl7 tvl6 tvl5 tvl4 tvl3 tvl2 tvl1 tvl0 w reset0000000000000000 figure 32-4. current timer value register (cval) table 32-5. cval field descriptions field description tvl n current timer value. these bits represent the cu rrent timer value. note that the timer uses a downcounter. note: the timer values will be frozen in debug mode if the frz bit is set in the pit module control register (see figure 32-2 )
pxd20 microcontroller reference manual, rev. 1 32-6 freescale semiconductor preliminary?subject to change without notice 32.3.2.5 timer flag register (tflg) these registers hold the pit interrupt flags. offset channel_base + 0x08 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000000 tie ten w reset0000000000000000 figure 32-5. timer control register (tctrl) table 32-6. tctrl field descriptions field description tie timer interrupt enable bit. 0 interrupt requests from timer x are disabled 1 interrupt will be requested whenever tif is set when an interrupt is pending (tif set), enabling the interrupt will immediately cause an interrupt event. to avoid this, the associated tif flag must be cleared first. ten timer enable bit. 0 timer will be disabled 1 timer will be active
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 32-7 preliminary?subject to change without notice 32.4 functional description 32.4.1 general this section gives detailed informat ion on the internal operati on of the module. each timer can be used to generate trigger pulses as well as to generate inte rrupts, each interrupt will be available on a separate interrupt line. 32.4.1.1 timers the timers generate triggers at periodic intervals, wh en enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will gene rate a trigger pulse, and set the interrupt flag. all interrupts can be enabled or masked (by setting th e tie bits in the tctrl re gisters). a new interrupt can be generated only after th e previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. offset channel_base + 0x0c access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000tif w w1c reset0000000000000000 figure 32-6. timer flag register (tflg) table 32-7. tflg field descriptions field description tif time interrupt flag. tif is set to 1 at the end of the timer period.this flag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1), tif causes an interrupt request. 0 time-out has not yet occurred 1 time-out has occurred
pxd20 microcontroller reference manual, rev. 1 32-8 freescale semiconductor preliminary?subject to change without notice the counter period can be restarte d, by first disabling, then enabling the timer with the ten bit (see figure 32-7 ). the counter period of a runni ng timer can be modified, by first disabli ng the timer, settin g a new load value and then enabling the timer again (see figure 32-8 ). it is also possible to change th e counter period without restarting the timer by wr iting the ldval register with the new load value. this value will then be loaded after the next trigger event (see figure 32-9 ). figure 32-7. stopping and starting a timer figure 32-8. modifying running timer period figure 32-9. dynamically setting a new load value 32.4.1.2 debug mode in debug mode the timers will be frozen - this is intended to aid software development, allowing the developer to halt the proces sor, investigate the current state of th e system (e.g. the timer values) and then continue the operation. 32.4.2 interrupts all of the timers support interrupt ge neration. refer to the mcu specificat ions for related vector addresses and priorities. p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 32-9 preliminary?subject to change without notice timer interrupts can be disa bled by setting the tie bits to zero. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that tif bit. 32.5 initialization and application information 32.5.1 example configuration in the example configuration: ? the pit clock has a frequency of 50 mhz ? timer 1 shall create an interrupt every 5.12 ms ? timer 3 shall create a trigger event every 30 ms first the pit module needs to be activated by writin g a 0 to the mdis bit in the pitctrl register. the 50 mhz clock frequency equates to a clock period of 20 ns . timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger would be calculated as (period / clock period) -1. this means that ldval1 with 0003e7f f hex and ldval3 with 0016e35f hex. the interrupt for timer 1 is enabled by setting tie in the tctrl1 register. the ti mer is started by writing a 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore ti mer 3 is started by writi ng a 1 to bit ten in the tctrl3 register, bit tie stays at 0. the following example code matches the described setup: // turn on pit pit_ctrl = 0x00; // rti pit_rti_ldval = 0x004c4b3f; // setup rti for 5000000 cycles pit_rti_tctrl = pit_tie; // let rti generate interrupts pit_rti_tctrl |= pit_ten; // start rti // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 pit_ldval3 = 0x0016e35f; // setup timer 3for 1500000 cycles pit_tctrl3 = ten; // start timer 3
pxd20 microcontroller reference manual, rev. 1 32-10 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 33-1 preliminary?subject to change without notice chapter 33 peripheral bridge (pbridge) 33.1 introduction the pbridge is the interface between the system bus and on-chip peripherals. it has a hard-wired configuration and cannot be re-configured in software. 33.1.1 overview pxd20 devices have one pbridge, which provides an interface between the system bus and all lower bandwidth peripherals. accesses that fall within the address space of th e pbridge are decoded to provide individual module selects for periphera l devices on the slave bus interface. 33.1.2 features the following list summarizes th e key features of the pbridge. ? supports the slave interface signals. this in terface is only meant for slave peripherals. ? supports 32-bit slave peripherals. (byte, halfwo rd, and word reads and writes are supported to each.) 33.2 functional description the pbridge serves as an interface between a system bus and the peripheral (slave) bus. it functions as a protocol translator. acces ses that fall within the address space of the pbridge are decoded to provide individual module selects for periphera l devices on the slave bus interface. 33.2.1 access support aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals. peripheral registers must not be misaligned, although no explicit chec king is performe d by the pbridge. note data accesses that cross a 32 -bit boundary are not supported. 33.2.1.1 peripheral write buffering buffered writes are not supported by the pxd20 pbridge. 33.2.1.2 read cycles two-clock read accesses are possibl e with the pbridge when the reque sted access size is 32-bits or smaller, and is not misali gned across a 32-bit boundary.
pxd20 microcontroller reference manual, rev. 1 33-2 freescale semiconductor preliminary?subject to change without notice 33.2.1.3 write cycles three-clock write accesses are possibl e with the pbridge when the requested access size is 32-bits or smaller. misaligned writes that cr oss a 32-bit boundary are not supported. 33.2.2 general operation slave peripherals are modules that contain readable/wri table control and status re gisters. the system bus master reads and writes these re gisters through the pbridge. the p bridge generates module enables, the module address, transfer attribut es, byte enables, and writ e data as inputs to th e slave peripherals. the pbridge captures read data from the slave interface and dr ives it on the system bus. the pbridge occupies a 64 mb portion of the address space. the register maps of the slave peripherals are located on 16-kb boundaries. each slave peripheral is allocated one 16-kb block of the memory map, and is activated by one of the module enables from the pbridge. the pbridge is responsible for indicat ing to slave peripherals if an acces s is in supervisor or user mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 34-1 preliminary?subject to change without notice chapter 34 power control unit (mc_pcu) 34.1 introduction 34.1.1 overview the power control unit (mc_pcu) is used to reduc e the overall soc power consumption. power can be saved by disconnecting parts of the soc from the pow er supply via a power switc hing device. the soc is grouped into multiple parts ha ving this capability which are called ?power domains.? when a power domain is disconnected from the supply, the power consumpt ion is reduced to zero in that domain. any status information of such a power dom ain is lost. when re-conne cting a power domain to the supply voltage, the domai n draws an increased curr ent until the power domain reaches its operational voltage. power domains are controlled on a device mode basi s. for each mode, software can configure whether a power domain is connected to the supply voltage (power-up state) or disconnected (power-down state). maximum power saving is reache d by entering the standby mode. on each mode change request, the mc_pcu evalua tes the power domain settings in the power domain configuration registers and initia tes a power-down or a power-up sequence for each individual power domain. the power-up/down sequences are handled by fini te state machines to ensure a smooth and safe transition from one power state to the other. exiting the standby mode can only be done via a system wakeup event as all power domains other than power domain #0 are in the power-down state. in addition, the mc_pcu acts as a bridge for mapping the vreg pe ripheral to the mc_pcu address space. figure 34-1 depicts the mc_pcu block diagram.
pxd20 microcontroller reference manual, rev. 1 34-2 freescale semiconductor preliminary?subject to change without notice figure 34-1. mc_pcu block diagram 34.1.2 features the mc_pcu includes the following features: ? support for 3 power domains ? support for device modes reset, drun, safe, test, run0?3, halt, stop, and standby (for further mode details , please see the mc_me chapter) ? power states updating on each mode change and on system wakeup ? a handshake mechanism for power state changes thus guarant eeing operable voltage ? maps the vreg registers to the mc_pcu address space 34.2 external signal description the mc_pcu has no connections to any external pins . mc_me firc vreg wkpu power domains power domain state machines registers platform interface mc_pcu mapped module interface mapped peripheral cpu
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 34-3 preliminary?subject to change without notice 34.3 memory map and register definition 34.3.1 memory map note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 34-1. mc_pcu register description address name description size access location user supervisor 0xc3fe_8000 pcu_pconf0 power domain #0 configuration word read read on page 34-5 0xc3fe_8004 pcu_pconf1 power domain #1 configuration word read read on page 34-6 0xc3fe_8008 pcu_pconf2 power domain #2 configuration word read read/write on page 34-7 0xc3fe_8040 pcu_pstat power domain status register word read read on page 34-7 table 34-2. mc_pcu memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe _8000 pcu_pconf0 r0000000000000000 w r0 0 stby 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _8004 pcu_pconf1 r0000000000000000 w r0 0 stby 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _8008 pcu_pconf2 r0000000000000000 w r0 0 stby 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w
pxd20 microcontroller reference manual, rev. 1 34-4 freescale semiconductor preliminary?subject to change without notice 34.3.2 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the pd0 field of the pcu_pstat register may be accessed as a word at address 0xc3fe_8040, as a half-word at address 0xc3fe_8042, or as a byte at address 0xc3fe_8043. 0xc3fe _800c ? 0xc3fe _803c reserved 0xc3fe _8040 pcu_pstat r0000000000000000 w r pd2 pd1 pd0 w 0x044 ? 0x07c reserved 0xc3fe _8080 ? 0xc3fe _80fc vreg registers 0xc3fe _8100 ? 0xc3fe _bffc reserved table 34-2. mc_pcu memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 34-5 preliminary?subject to change without notice 34.3.2.1 power domain #0 configuration register (pcu_pconf0) this register defines for power dom ain #0 whether it is on or off in each device mode. as power domain #0 is the always-on power domain (and includes the mc _pcu), none of its bits are programmable. this register is available for completeness reasons. address 0xc3fe_8000 access: user read, supervisor read, test read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 stby 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0010010111111111 figure 34-2. power domain #0 conf iguration register (pcu_pconf0) table 34-3. power domain configur ation register field descriptions field description rst power domain control during reset mode 0 power domain off 1 power domain on test power domain control during test mode 0 power domain off 1 power domain on safe power domain control during safe mode 0 power domain off 1 power domain on drun power domain control during drun mode 0 power domain off 1 power domain on run0 power domain control during run0 mode 0 power domain off 1 power domain on run1 power domain control during run1 mode 0 power domain off 1 power domain on run2 power domain control during run2 mode 0 power domain off 1 power domain on run3 power domain control during run3 mode 0 power domain off 1 power domain on
pxd20 microcontroller reference manual, rev. 1 34-6 freescale semiconductor preliminary?subject to change without notice 34.3.2.2 power domain #1 configuration register (pcu_pconf1) this register defines for power domain #1 whether it is on or off in each device mode. the bit field description is the same as in table 34-3 . as the platform, clock generati on, and mode control reside in power domain #1, this power domai n is only powered down during the standby mode. therefore, none of the bits is programmable. this regist er is available for completeness reasons. the difference between pc u_pconf0 and pcu_pconf1 is the reset value of the stby bit: during the standby mode, power domain #1 is disconnected from the power supply, and therefore pcu_pconf1.stby is always ?0?. power domain #0 is always on, and th erefore pcu_pconf0.stby is ?1?. for further details about st andby mode, please refer to section 34.4.4.2, standby mode transition . halt power domain control during halt mode 0 power domain off 1 power domain on stop power domain control during stop mode 0 power domain off 1 power domain on stby power domain control during standby mode 0 power domain off 1 power domain on address 0xc3fe_8004 access: user read, supervisor read, test read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 stby 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 34-3. power domain #1 conf iguration register (pcu_pconf1) table 34-3. power domain configuration register field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 34-7 preliminary?subject to change without notice 34.3.2.3 power domain #2 configuration register (pcu_pconf2) this register defines for power domain #2 whether it is on or off in each device mode. the bit field description is the same as in table 34-3 . 34.3.2.4 power domain status register (pcu_pstat) this register reflects the power stat us of all available power domains. address 0xc3fe_8008 access: user read, super visor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 stby 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 34-4. power domain #2 conf iguration register (pcu_pconf2) address 0xc3fe_8040 access: user read, supervisor read, test read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pd2 pd1 pd0 w reset0000000000000111 figure 34-5. power domain status register (pcu_pstat) table 34-4. power domain status register (pcu_pstat) field descriptions field description pd n power status for power domain # n 0 power domain is inoperable 1 power domain is operable
pxd20 microcontroller reference manual, rev. 1 34-8 freescale semiconductor preliminary?subject to change without notice 34.4 functional description 34.4.1 general the mc_pcu controls all available power domai ns on a device mode basis. the pcu_pconf n registers specify during which system/user modes a power domain is powered up. the power state for each individual power domain is reflected by the bits in the pcu_pstat register. on a mode change, the mc_pcu ev aluates which power domai n(s) must change pow er state. the power state is controlled by a st ate machine (fsm) for each individual power domain (see figure 34-1 ) which ensures a clean and safe state transition. 34.4.2 reset / power-on reset after any reset, the soc will tran sition to the reset mode during which all power domains are powered up (see the mc_me chapter). once the reset sequenc e has been completed, the drun mode is entered and software can begin th e mc_pcu configuration. 34.4.3 mc_pcu configuration per default, all power domains are powered in all modes other than st andby. software can change the configuration for each power domain on a mode basis by programming the pcu_pconf n registers. each power domain which is powered down is held in a reset state. read/write accesses to peripherals in those power domains will re sult in a transfer error. 34.4.4 mode transitions on a mode change requested by the mc_me, the mc _pcu evaluates the power configurations for all power domains. it compares th e settings in the pcu_pcon fn registers for the new mode with the settings for the current mode. if the configuration for a pow er domain differs between the modes, a power state change request is generated. these requests are handled by a finite stat e machine to ensu re a smooth and safe transition from one power state to another. 34.4.4.1 drun, safe, test, run0?3, halt, and stop mode transition the drun, safe, test, run0?3, halt, and stop modes allow an increased power saving. the level of power saving is software-controll able via the settings in the pcu_pconf n registers for power domain #2 onwards. the settings fo r power domains #0 and #1 can not be changed. therefore, power domains #0 and #1 remain connected to the power supply for all modes beside standby. figure 34-6 shows an example for a mode tr ansition from run0 to halt a nd back, which will result in power domain #2 being powered down during the hal t mode. in this case, pcu_pconf2.halt is programmed to be ?0?.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 34-9 preliminary?subject to change without notice when the mc_pcu receives the mode change request to halt mode, it starts its power-down phase. during the power-down phase, clocks are disabled and the reset is asse rted resulting in a loss of all information for this power domain. then the power domain is disconnected fr om the power supply (power-down state). figure 34-6. mc_pcu events during power sequences (non-standby mode) when the mc_pcu receives a mode change request to run0, it starts its power-up phase if pcu_pconf2.run0 is ?1?. the power domain is re-c onnected to the power supply, and the voltage in power domain #2 will increas e slowly. once the voltage of power domain #2 is within an operable range, its clocks are enabled, and its resets are deasserted (power-up state). note it is possible that, due to a mode ch ange, power-up is requested before a power domain completed its power-dow n sequence. in this case, the information in that power domain is lost. 34.4.4.2 standby mode transition standby offers the maximum power saving. the level of pow er saving is software -controllable via the settings in the pcu_pconf n registers for power domai n #2 onwards. power dom ain #0 stays connected to the power supply while power dom ain #1 is disconnected from the power supply. amongst others power domain #1 contains the platform and the mc_me. therefore this mode differs from all other user/system modes. once standby is entered it can onl y be left via a syst em wakeup. on exiting the standby mode, all power domains are powered up accord ing to the settings in the pcu_pconfn registers, and the drun mode is entered. in drun mode, at least power domains #0 and #1 are powered. figure 34-7 shows an example for a mode transition fr om run0 to standby to drun. all power domains which have pcu_pconfn.s tby cleared will enter power-dow n phase. in this example only power domain #1 will be disa bled during standby mode. new mode power-down run0 voltage in pstat.pd2 halt run0 notes: not drawn to scale; pconf2 .run0 = 1; pconf2.halt = 0 current mode power-up phase power domain #2 run0 halt run0 requested by me power-down state power-up state phase
pxd20 microcontroller reference manual, rev. 1 34-10 freescale semiconductor preliminary?subject to change without notice when the mc_pcu receives th e mode change request to standby mode it starts the power down phase for power domain #1. during the power dow n phase, clocks are disabled and reset is asserted resulting in a loss of all information for this power domain. then the power domain is disc onnected from the power supply (power-down state). figure 34-7. mc_pcu events during power sequences ( standby mode) when the mc_pcu receives a syst em wakeup request, it starts the power-up phase. the power domain is re-connected to the power supply and the voltage in power domain #1 will increase slowly. once the voltage is in an operable range, cl ocks are enabled and the reset is be deasserted (power-up state). note it is possible that due to a wakeup re quest, power-up is requested before a power domain completed its power-dow n sequence. in this case, the information in that power domain is lost. 34.4.4.3 power saving for me mories during standby mode all memories which are not powered down during standby mode automatica lly enter a power saving state. no software configuration is required to enable this power savi ng state. while a memory is residing in this state an increased power saving is achieved. data in the memories is retained. 34.5 initialization information to initialize the mc_pcu, the registers pcu_pconf2? should be programmed. after programming is done, those registers should no longer be changed. new mode power-down run0 voltage in pstat.pd1 standby notes: not drawn to scale; pconf1.run0 = 1; pconf1.stby = 0 current mode power-up phase power domain #1 run0 standby drun requested by me power-down state power-up state power-up state phase mode set due to reset being asserted to power domain #1 wakeup request
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 34-11 preliminary?subject to change without notice 34.6 application information 34.6.1 standby mode considerations standby offers maximum power saving possibility. but power is only saved during the time a power domain is disconnected from the suppl y. increased power is required wh en a power domain is re-connected to the power supply. additional powe r is required during restoring the in formation (e.g., in the platform). care should be taken that the time during which the soc is operating in standby mode is significantly longer than the required time for restoring the information.
pxd20 microcontroller reference manual, rev. 1 34-12 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-1 preliminary?subject to change without notice chapter 35 quad serial peripheral interface (quadspi) 35.1 introduction figure 35-1 is a block diagram of the quad serial peripheral interface (quadspi) module.
pxd20 microcontroller reference manual, rev. 1 35-2 freescale semiconductor preliminary?subject to change without notice figure 35-1. quadspi block diagram ahb bus ips bus/ipd bus read read_done ahb_serve fetch received (addr, size, type) (data) ahb_control qspi_ic_sfm ahbcommand (inst, addr, size) ready rdata ipcommand (inst, addr, size) ready rdata ctrl_vector ready wdata qspi_if system clock domain sclk clock domain quadspi bus flash a ipacc ahbacc wdata rdata qspi_if_core qspi_if_sclk cmd txdata ready tx_acc rxdata ready rx_acc events rx buffer tx buffer sfar icr address register instruct. register command_build & buffer control define rd_data (addr, cmd) wr_data (data) (data) ahb buffer ip_ctrl (addr, size) (data) ip_control sckfa pcsfa iofa[3:0] dma and interrupt control command processing clock domain crosser cmd txdata ready tx_acc rxdata ready rx_acc events quadspi bus flash b sckfb pcsfb iofb[3:0]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-3 preliminary?subject to change without notice 35.1.1 overview the quadspi block acts as an interface to spi serial flash devices. refer to section 35.1.3, quadspi modes of operation , for a description of the different modes. 35.1.2 features the quadspi supports the following features: ? compatible with winbond and spansion as vendors of spi seri al flash devices. ? single, dual and quad mode of operation. ? supports both 24- a nd 32-bit addresses. ? two identical serial flash devices can be c onnected and accessed in parallel for data read operations, forming one (virtual) flash memory with doubled readout bandwidth. ? dma support to read rx buffer data via amba ahb bus (64 bit wi dth interface) or ip registers space (32 bit access). ? inner loop size of dma a ccess can be configured. ? in total 14 interrupt condi tions are mapped to 5 different interrupt lines (see table 35-2 ) ? memory mapped read access to connected flash devices. ? supports flash devices of up to 128 mb in size ? appropriate command sequence for flash read triggered automatically by read access ? automatic divide by 2 of the se rial flash device clock for co mmands not supporting the full frequency range. additionally, the module supp orts a stop mode for power-saving pur poses. this is independent from any low power modes on the external quadspi memory device. 35.1.3 quadspi modes of operation 35.1.3.1 normal mode in this mode one or two external serial flash memo ry device can be accessed. further details about this mode of operation can be found in chapter section 35.5.3, normal mode . 35.1.3.2 module disable mode the module disable mode is used for power management of the devi ce containing the quadspi module, it is controlled by signals external to the quad spi. the clock to the non-memory mapped logic in the quadspi can be stopped while in the module disable mode. see section 35.5.4.2, modul e disable mode . 35.1.3.3 stop mode the stop mode is also used for power management. when a request is made to enter stop mode, the quadspi block completes the action currently processed. then the request is acknowledged.
pxd20 microcontroller reference manual, rev. 1 35-4 freescale semiconductor preliminary?subject to change without notice 35.2 external signal description 35.2.1 overview table 35-1 lists the signals of the external signals bel onging to the quadspi module in conjunction with the different modes of operation: 35.2.2 detailed signal description the following paragraphs describe th e function of the signals given in table 35-1 in more detail. only the modes relevant to the specific signal are mentioned according to table 35-1 . 35.2.2.1 pcsfa - periphera l chip select flash a this signal is the chip select for the serial flash device a. 35.2.2.2 pcsfb - peripheral chip select flash b this signal is the chip select for the serial flash device b. 35.2.2.3 sckfa ? serial clock flash a this signal is the serial clock out put to the serial flash device a. 35.2.2.4 sckfb ? serial clock flash b this signal is the serial clock out put to the serial flash device b. 35.2.2.5 iofa[3:0] - data io flash a these signals are the data i/o lines to/f rom the serial flash device a. refer to section 35.2.3, driving of external signals , for details about the signal drive and timing behavior. note that the signal pins of the serial flash device may change their function according to the sfm command executed, leaving them as control inputs when single and dual instructions ar e executed. the quadspi module drives these signals high during the execution of si ngle and dual instructions. table 35-1. signal properties signal name function direction pcsfa peripheral chip select flash a output pcsfb peripheral chip select flash b output sckfa serial clock flash a output sckfb serial clock flash b output iofa[3:0] serial i/o flash a bidir iofb[3:0] serial i/o flash b bidir
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-5 preliminary?subject to change without notice 35.2.2.6 iofa[3:0] - data io flash b these signals are the data i/o lines to/f rom the serial flash device b. refer to section 35.2.3, driving of external signals , for details about the signal drive and timing behavior. note that the signal pins of the serial flash device may change their function according to the sfm command executed, leaving them as control inputs when single and dual instructions ar e executed. the quadspi module drives these signals high during the execution of si ngle and dual instructions. 35.2.3 driving of external signals the different phases of serial fl ash access scheme are shown in figure 35-2 below:
pxd20 microcontroller reference manual, rev. 1 35-6 freescale semiconductor preliminary?subject to change without notice figure 35-2. serial flash access scheme the different phases and the i/o driving characterist ics of the quadspi module are characterized in the following way: ? idle: serial flash device not selected. no interaction with the se rial flash device. all iofx signals driven. ? instruction: serial flash device selected. the instructi on is sent to the seri al flash device. all iofx signals are driven. sckfx pcsfx idle instruction address mode dummy data idle iofx[0] single instructions iofx[3:2] driven high all the time driven all the time, values taken according to phase iofx[1:0] dual instructions iofx[3:2] driven high all the time driven for tx instr. only iofx[3:0] quad instructions driven for tx instr. only not driven not driven
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-7 preliminary?subject to change without notice ? address: serial flash address is sent to the device. all iofx signals are driven. note that this phase is not applicable for all sfm commands. ? mode: mode bytes are sent to the se rial flash device. all iofx signa ls are driven. note that this phase is not applicable for all sfm commands. ? dummy: dummy clocks are provided to th e serial flash device. refer to figure 35-2 for the iofx signals driven. the actual data lines required fo r the sfm command executed are not driven for data read commands. note that this phase is not applicable for all sfm commands. ?data: serial flash data are sent to or receiv ed from the serial flash device. refer to figure 35-2 for the iofx signals driven. the actual data lines required for the sfm command executed are not driven for data read commands. note that this phase is not applicable for all sfm commands. the pcsfx and sckfx signals are driven permanently throughout all the phases. in individual flash mode this applies to the selected flash device. in parallel fl ash mode this applies to both serial flash devices simultaneously. 35.3 interrupt signals the interrupt request lines of th e quadspi module are mapped to th e internal flags according to table 35-2 below: table 35-2. assignment of interrupt request lines irq/dma line qspi_sfmfr flag interrupt description ipi_int_tfff tbff tx buffer fill ipi_int_tcf tff ip command transaction finished ipi_int_rfdf rbdf rx buffer drain ipi_int_overrun buffer overflow/underrun error logical or from: rbof rx buffer overrun tbuf tx buffer underrun abof ahb buffer overflow
pxd20 microcontroller reference manual, rev. 1 35-8 freescale semiconductor preliminary?subject to change without notice 35.4 memory map and register definition 35.4.1 memory map table 35-3 shows the quadspi memory map. ipi_int_cerr serial flash command error logical or from: ipaef ip access while ahb busy error ipief ip command could not be triggered error ipgef ip access while ahb grant error abcef ahb command error abmef ahb mode error iuef ip command usage error icef ip command error imef ip command mode error table 35-3. quadspi memory map address register name location qspi_base+0x000 module configur ation register (qspi_mcr) on page 35-11 qspi_base+0x004 laten cy configuration register (qspi_lcr) on page 35-12 qspi_base+0x004 - qspi_base+0x0fc reserved qspi_base+0x100 serial flash address register (qspi_sfar) on page 35-13 qspi_base+0x104 instruction code register (qspi_icr) on page 35-14 qspi_base+0x108 sampling register (qspi_smpr) on page 35-15 qspi_base+0x10c rx buffer st atus register (qspi_rbsr) on page 35-16 qspi_base+0x110 rx buffer c ontrol register (qspi_rbct) on page 35-17 qspi_base+0x114 ? qspi_base+0x14c reserved qspi_base+0x150 tx buffer st atus register (qspi_tbsr) on page 35-17 qspi_base+0x154 tx buffer da ta register (qspi_tbdr) on page 35-18 qspi_base+0x158 amba contro l register (qspi_acr) on page 35-19 qspi_base+0x15c s tatus register (qspi_sfmsr) on page 35-20 table 35-2. assignment of interrupt request lines (continued) irq/dma line qspi_sfmfr flag interrupt description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-9 preliminary?subject to change without notice 35.4.2 serial flash address assignment in table 35-4 below it is noted how the different access mode s are related to the address specified for the next sfm command. note that this address assignment is valid for ip commands as well as ahb command. for ip commands it is the value to be programmed into the qspi _sfar register, for ahb commands it is the address accessed via the ahb bus. note any read access to non-implemented addresses will provide undefined results. the address space availabl e for each single flash de vice in 24-bit addressing mode is limited to 3 byt es corresponding to 16 mb a ddress space. in 32-bit addressing mode this is extended to 4bytes, allowing the maximum of 128 mb to be addressed. it is within the responsibility of the user not to exceed beyond the physically availabl e addresses of the serial flash attached to the quadspi module. parallel flash mode is valid only for commands related to data read from the serial flash. any ip command other than data read in parallel flash mode will result in the assertion of the qspi_sfmfr[iuef] flag and any ahb command other than data read in parallel flash mode will result in the assertion of the qspi _sfmfr[abcef] flag, see table 35-43 and table 35-47 for the related commands. qspi_base+0x160 flag regi ster (qspi_sfmfr) on page 35-21 qspi_base+0x164 interrupt and dm a request select and enable register (qspi_sfmrser) on page 35-23 qspi_base+0x168 ? qspi_base+0x1fc reserved qspi_base+0x200 ? qspi_base+0x27c rx buffer data registers 0?31 (qspi_rbdr0?qspi_rbdr31) on page 35-25 table 35-4. serial flash address assignment address access mode 0x7000_0000 ... 0x77ff_ffff (128 mb) individual flash mode - flash a only 0x7800_0000 ... 0x7fff_ffff (128 mb) individual flash mode - flash b only 0x8000_0000 ... 0x8fff_ffff (256 mb) parallel flash mode - flash a and b in parallel table 35-3. quadspi memory map (continued) address register name location
pxd20 microcontroller reference manual, rev. 1 35-10 freescale semiconductor preliminary?subject to change without notice in the individual flash modes the 3 add ress bytes available for the flash address are determined by sfadr[8: 31] as given in the table above. in parallel flash mode bot h flashes are read with the same starting address of 3 bytes in size. this address is derived from sf adr[7:30] as given in the table above. the lsb of the sfadr field is used to select the appropriate bits of both flash devices to combine the byte corresponding to the selected address. 35.4.3 amba bus register memory map 35.4.4 register descriptions 35.4.4.1 registe r write access this section describes the write access restri ction terms that apply to all registers. 35.4.4.1.1 register wr ite access restriction for each register bit and register fi eld, the write access conditions are sp ecified in the detailed register description. a description of the wr ite access conditions is given in table 35-6 . if, for a specific register table 35-5. quadspi amba bus memory map address register name memory mapped serial flash data - individual flash mode on flash a 0x7000_0000 ... 0x77ff_ffff (128 mb) memory mapped serial flash data - individual flash mode on flash a refer to section 35.4.5.2, memory mapped serial flash data - individual flash mode on flash a , for details and to table 35-28 and table 35-32 for information about the byte ordering. memory mapped serial flash data - individual flash mode on flash b 0x7800_0000 ... 0x7fff_ffff (128 mb) memory mapped serial flash data - individual flash mode on flash b refer to section 35.4.5.3, memory mapped serial flash data - individual flash mode on flash b , for details and to table 35-28 and table 35-32 for information about the byte ordering. memory mapped serial flash data - parallel flash mode 0x8000_0000 ... 0x8fff_ffff (256 mb) memory mapped serial flash data - parallel flash mode refer to section 35.4.5.4, memory mapped serial flash data - parallel flash mode , for details and to table 35-31 and table 35-32 for information about the byte ordering. ahb rx data buffer (q spi_ardb0 to qspi_ardb31) 0x9000_0000 ...(128*4 byte) 0x9000_01ff ahb rx data buffer (qspi_ardb0 to qspi_ardb31) address 0x9000_0000 is qspi_ardb0. refer to table 35-28 and table 35-30 for information about the byte ordering.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-11 preliminary?subject to change without notice bit or field, none of the given write access conditions is fulfilled, any writ e attempt to this register bit or field is ignored without any not ification. the values of the bi ts or fields are not changed. the condition term [a or b] indicates that the register or field can be written to if at least one of the conditions is fulfilled. 35.4.4.1.2 register write access requirements all registers can be accessed with 8-bit, 16-bit and 32- bit wide operations. for some of the registers, at least a 16/32-bit wide write access is required to ensure correct operation. this write access requirement is stated in the detailed register description for each register affected 35.4.4.2 module configurat ion register (qspi_mcr) the qspi_mcr holds configuration data associated with quadspi operation. caution the upper 16 bits of this regi ster are writable in disa bled mode. be sure that these are always kept at th e reset value indicated in figure 35-3 . table 35-6. register write access restrictions condition description anytime no write access restriction. disabled mode write access only if the module is in module disable mode . normal mode write access only if the module is in normal mode . address: qspi_base + 0x000 write: bits 0-15 disabled mode all other fields: anytime 0123456789101112131415 r 0000000000001111 w reset0000000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r d_rsvd mdis 0000000 vmid 000 w clr_txf clr_rxf ext_add reset0 100000000000000 figure 35-3. module configuration register (qspi_mcr)
pxd20 microcontroller reference manual, rev. 1 35-12 freescale semiconductor preliminary?subject to change without notice 35.4.4.3 latency configurat ion register (qspi_lcr) the latency configuration register is used to inse rt a variable number of dum my cycles during command execution. the dummy cycle inserti on is dependent on memory vendor (refer to vendor?s memory specification guide), frequency of se rial flash clock (sck) and type of command (refer to qspi latency support, table 35-9 ). table 35-7. qspi_mcr field descriptions field description d_rsvd reserved bit. this bit is writable but should be kept as value 0. mdis module disable. the mdis bit allows the clock to the non-memory mapped logic in the quadspi to be stopped, putting the quad spi in a software controlled power-saving state. see section 35.5.4.2, module disable mode , for more information. 0 enable quadspi clocks. 1 allow external logic to disable quadspi clocks. clr_txf clear tx fifo/buffer. in validate the tx buffer content. 0 no action 1 read and write pointers of the rx buffer are re set to 0. qspi_tbsr[trctr] is reset to 0. clr_rxf clear rx fifo. invalidate the rx buffer. 0 no action 1 read and write pointers of the rx buffer are reset to 0. qspi_rbsr[rdbfl] is reset to 0. vmid vmid ? vendor model id. this field applies to flash a and flash b. 0000 reserved 0001 winbond 0010 spansion 0011 macronix 0100 numonyx others reserved ext_add 1 1 this bit is set to enable the qspi for 32-bit addressing mode. the respective external serial flash memory should also be independently enabled for accepting 32-bit addresses. extended memory address modes. 0 default mode, 24-bit addressing. 1 32-bit addressing.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-13 preliminary?subject to change without notice 35.4.4.4 serial flash addr ess register (qspi_sfar) the serial flash address regi ster contains the address for the next ip command. bi ts 23 to 0 (bits 26 to 0 when mcr.ext_add = 1) are used fo r the addressing of the flash device itself. additional bits are used to specify the access mode of the next ip command. refer to table 35-4 for the mapping between the access mode and the qspi_sfar content and to section 35.5.3, normal mode , for details about the command triggering and command execution. address: qspi_base + 0x004 write: anytime 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 ndc w reset0000000000001000 figure 35-4. latency configuration register (qspi_lcr) table 35-8. qspi_lcr field descriptions field description ndc 1 1 refer to data sheet of memory vendors. number of dummy cycles to be inserted during command execution. 0x00 no dummy cycle 0x01 1 dummy cycle 0x02 2 dummy cycles 0x03 3 dummy cycles 0x04 4 dummy cycles .... 0x3e 62 dummy cycles 0x3f 63 dummy cycles table 35-9. qspi latency support memory vendor supported commands winbond none spansion 0b, 3b, 6b, bb, eb macronix all numonyx all
pxd20 microcontroller reference manual, rev. 1 35-14 freescale semiconductor preliminary?subject to change without notice refer to table 35-11 below for the address assignment re lated to the different access modes. 35.4.4.5 instruction code register (qspi_icr) the instruction code register consis ts of the generic instruction code (ic) and an additional parameter section (ico). this co ntains additional options to parameterize the command as shown in table 35-41 . if the ic field is written successfully a new command to the external serial flash de vice is started with that instruction code if this code is supported by the module (see section 35.8, serial flash devices ). address: qspi_base + 0x100 write: qspi_sfmsr[ip_acc] = 0 0123456789101112131415 r sfadr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sfadr w reset0000000000000000 figure 35-5. serial flash address register (qspi_sfar) table 35-10. qspi_sfar field descriptions field description sfadr serial flash address, register content is used as byte address for all following ip commands. table 35-11. sfadr address assignment sfadr serial flash byte address - related to the first buffer entry 1 1 the address specified in the sfadr field determines th e byte appearing at qspi_rbdr0[0:7]. subsequent bytes appear according to the byte ordering given above. serial flash device 0x7000_0000 0x00_0000 - 0x00_0003 flash a refer to section 35.5.3.4.1, byte ordering in individual flash mode ... ... 0x77ff_fffc 0x7fff_f ffc - 0x7fff_ffff 0x7800_0000 0x0000_0000 - 0x0000_0003 flash b refer to section 35.5.3.4.1, byte ordering in individual flash mode ... ... 0x7fff_fffc 0x7fff_fffc - 0x7fff_ffff 0x8000_0000 0x0000_0000 - 0x00_0001 flash b refer to section 35.5.3.4.2, byte ordering in parallel flash mode ... ... 0x8fff_ffff 0x8fff_f ffe - 0x8fff_ffff
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-15 preliminary?subject to change without notice refer to section 35.5.3.1, issuing sfm commands , for further details about the triggering of ip commands. 35.4.4.6 sampling re gister (qspi_smpr) the sampling register allows configur ation of the scheme how the incomi ng data from an external serial flash device are sampled in the quadspi module. address: qspi_base + 0x104 write: ico: qspi_sfmsr[ip_acc] = 0 ic: qspi_sfmsr[ip_acc] = 0 and qspi_sfmsr[ahb_acc] = 0 0123456789101112131415 r ico w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ico ic w reset0000000000000000 figure 35-6. instruction code register (qspi_icr) table 35-12. qspi_icr field descriptions field description ico instruction code options, additional parameters fo r the ic instruction described below. meaning of the individual bits vary for each instruction code and vendor, detailed description in table 35-41 . ic write access: instruction code of the sfm command to be executed next. read access: instruction code of the la st sfm command succe ssfully written. upon writing this byte a new command sequence is started to the external serial flash device. address: qspi_base + 0x108 write: disabled mode 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fsdly fsphs 00 hsdly hsphs hsena w reset0000000000000000 figure 35-7. sampling register (qspi_smpr)
pxd20 microcontroller reference manual, rev. 1 35-16 freescale semiconductor preliminary?subject to change without notice 35.4.4.7 rx buffer status register (qspi_rbsr) this register contains information related to the receive data buffer. table 35-13. qspi_smpr field descriptions field description fsdly full speed delay selection. select the delay w.r .t. the reference edge for the sample point valid for full speed commands: 0: one clock cycle delay 1: two clock cycles delay fsphs full speed phase selection. select the edge of the sampling clock valid for full speed commands: 0: select sampling at non-inverted clock 1: select sampling at inverted clock hsdly half speed delay selection. only relevant when hsena bit is set . select the delay w.r.t. the reference edge for the sample point valid for half speed commands: 0: one clock cycle delay 1: two clock cycles delay hsphs half speed phase selection. only relevant when hsena bit is set . select the edge of the sampling clock valid for half speed commands: 0: select sampling at non-inverted clock 1: select sampling at inverted clock hsena half speed serial flash clock enable: this bit enables the divide by 2 of the clock to the external serial flash device for specific commands. refer to section 35.8.5, serial flash clock frequency limitations , for details. 0: disable divide by 2 of serial flash clock for half speed commands 1: enable divide by 2 of serial flash clock for half speed commands address: qspi_base + 0x10c 0123456789101112131415 r rdctr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00 rdbfl 00000000 w reset0000000000000000 figure 35-8. rx buffer status register (qspi_rbsr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-17 preliminary?subject to change without notice 35.4.4.8 rx buffer contro l register (qspi_rbct) this register contains control data related to the receive data buffer. 35.4.4.9 tx buffer status register (qspi_tbsr) this register contains information re lated to the transmit data buffer. table 35-14. qspi_rbsr field descriptions field description rdctr read counter, indicates how many entries of 4 byte have been removed from the rx buffer. it is incremented by the number (qspi_rbct[ wmrk] + 1) on rx buffer pop event. for further details please refer to section 35.4.5.5, ahb rx data bu ffer (qspi_ardb0 to qspi_ardb31) , and section 35.5.3.3.2, data tr ansfer from the quadspi module internal buffers . rdbfl rx buffer fill level, indicates how many entries of 4 bytes are still available in the rx buffer. address: qspi_base + 0x110 write: qspi_sfmsr[ip_acc] = 0 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 rxbrd 000 wmrk w reset0000000000000000 figure 35-9. rx buffer control register (qspi_rbct) table 35-15. qspi_rbct field descriptions field description rxbrd rx buffer readout: this bit specifies the access scheme for the rx buffer readout. 0 rx buffer content is read using the ahb bus registers qspi_ardb0 to qspi_ardb31. for details refer to section 35.6.3, exclusive access to serial flash for ahb commands . 1 rx buffer content is read using the ip bus registers qspi_rbdr0 to qspi_rbdr31. wmrk rx buffer watermark: this field determines when the readout action of the rx buffer is triggered. when the number of valid entries in the rx buffer exceeds the number given by the wmrk field the qspi_sfmfr[rxwe] flag is asserted. for details refer to section 35.6.7, dma usage .
pxd20 microcontroller reference manual, rev. 1 35-18 freescale semiconductor preliminary?subject to change without notice 35.4.4.10 tx buffer data register (qspi_tbdr) the qspi_tbdr register provides access to the circular tx buffer. this buffer provides the data written into it as write data for the page programming commands to the serial flash device. refer to table 35-28 for the byte ordering scheme. address: qspi_base + 0x150 0123456789101112131415 r trctr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 trbfl 00000000 w reset0000000000000000 figure 35-10. tx buffer status register (qspi_tbsr) table 35-16. qspi_tbsr field descriptions field description trctr transmit counter. this field indicates how many entries of 4 bytes have been written into the tx buffer by host accesses. it is reset to 0 when a 1 is written into the qspi_m cr[clr_txf] bit. it is incremented on each write access to the qspi_tbdr register when another word has been pushed onto the tx buffer. when it is not cleared the trctr field wraps around to 0. refer to section 35.4.4.10, tx buffer data register (qspi_tbdr) , for details. trbfl tx buffer fill level. the trbfl field contains the number of entries of 4 bytes each available in the tx buffer for the quadspi module to transmit to the serial flash device. address: qspi_base + 0x154 write: qspi_sfmsr[txfull] = 0 32-bit write access required 0123456789101112131415 r txdata[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata[15:0] w reset0000000000000000 figure 35-11. tx buffer (qspi_tbdr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-19 preliminary?subject to change without notice 35.4.4.11 amba control register (qspi_acr) the qspi_acr register defines th e command that is used for following ahb commands. the read commands allowed are given in 35.8, serial flash devices . the execution of the command itself is triggered by an ahb read to the address range assi gned to the memory mapped serial flash data. for further details refer to section 35.6.4, command arbitration . table 35-17. qspi_tbdr field descriptions field description txdata tx data on write access the data are written into the next available entry of the tx buffer and the qpsi_tbsr[trbfl] field is updated accordingly. on read access the last data written are read. address: qspi_base + 0x158 write: anytime 0123456789101112131415 r00000000 armb w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r arsz 000 aric w reset0000100000000011 figure 35-12. amba control register (qspi_acr) table 35-18. qspi_acr field descriptions field description armb amba read mode byte. instruction code option for aric for continuous mode. refer to table 35-41 m7-m0 and section 35.6.6, cont inuous mode commands . arsz amba read size. specifies the number of bytes which are read from the external serial flash device into the ahb buffer for any starting address not found in the ahb buffer. the total number of bytes to be read by the resulting ahb command is the value in arsz * 8. individual flash mode : legal values for arsz are in the range from 1 to 16, resulting in 8 up to 128 bytes read from the (single) external serial flash devices. parallel flash mode : legal values for arsz are in the range from 1 to 16, resulting in 8 up to 128 bytes read from both external serial flash device s. note that the actual nu mber of bytes read from each flash device is half the total number of bytes. an attempt to write 0 is ignored, instead the reset value is programmed into this field. aric amba read instruction code. selects the read command to be used for any read access to the external serial flash device. the reset value of the aric field is the read_data command with a size of 4 bytes.
pxd20 microcontroller reference manual, rev. 1 35-20 freescale semiconductor preliminary?subject to change without notice 35.4.4.12 status register (qspi_sfmsr) the qspi_sfmsr register provides all available status information about sfm command execution and arbitration, the rx buffer and tx buffer and the ahb buffer. address: qspi_base + 0x15c 0123456789101112131415 r 0000 txfull 00 txne rxdma 000 rxfull 00 rxwe w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 ahbfull 00 ahbne 0 ahbtrn ahbgnt cntmdfb cntmdfa ahb_acc ip_acc busy w reset0000000000000000 figure 35-13. status register (qspi_sfmsr) table 35-19. qspi_sfmsr field descriptions field description tx buffer related status information txfull tx buffer full: asserted when no more data can be stored. txne tx buffer not empty: asserted when tx buffer contains data. rx buffer related status information rxdma rx buffer dma: asserted when rx buffer read out via dma is active. rxfull rx buffer full: asserted when the rx buffer is full, i.e. that qspi_rbsr[rdbfl] field is equal to 32. rxwe rx buffer watermark exceeded: asserted when the number of valid entries in the rx buffer exceeds the number given in the qspi_rbct[wmrk] field. ahb buffer and ahb access related status information ahbfull ahb buffer full: asserted when ahb buffer is full. ahbne ahb buffer not empty: assert ed when ahb buffer contains data. ahbtrn ahb access transaction pending: asserted when there is a pending request on the ahb interface. refer to the amba specification for details. ahbgnt ahb command priority granted: asserted when another module has been granted priority of ahb commands against ip commands. for details refer to section 35.6.4, command arbitration . sfm command related status information
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-21 preliminary?subject to change without notice 35.4.4.13 flag register (qspi_sfmfr) the qspi_sfmfr register provide s all available flags about sfm command execution and arbitration which may serve as source for the gene ration of interrupt service requests. note that the error flags in this register do not relate directly to the execution of the transaction in the se rial flash device itself but only to the behavior and conditions visible in the quadspi module. cntmdfb continuos mode bit flash b: this bit is updated when a sfm command is triggered. 0 the sfm command triggered does not belong to the subset of continuous mode commands. 1 the sfm command triggered does belong to the subset of continuous mode commands. refer to section 35.6.6, continuous mode commands , for details. cntmdfa continuos mode bit flash a: this bit is updated when a sfm command is triggered. 0 the sfm command triggered does not belong to the subset of continuous mode commands. 1 the sfm command triggered does belong to the subset of continuous mode commands. refer to section 35.6.6, continuous mode commands , for details. ahb_acc ahb access: asserted when the transaction currently executed was initiated by ahb bus. ip_acc ip access: asserted when transaction cu rrently executed was initiated by ip bus. busy module busy: asserted when module is currently busy handling a transaction to an external flash device. address: qspi_base + 0x 160 write: enabled mode 0123456789101112131415 r 0000 tbff tbuf 00000000 rbof rbdf w w1c w1c w1c w1c reset0000100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 abcef abmef abof iuef icef imef 0 ipaef ipief 0 ipgef 0 00 tff w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 35-14. flag register (qspi_sfmfr) table 35-20. qspi_sfmfr field descriptions field description tx buffer related flags tbff tx buffer fill flag: set when th e tx buffer is not full. refer to section 35.5.3.6, tx buffer operation , for details. table 35-19. qspi_sfmsr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 35-22 freescale semiconductor preliminary?subject to change without notice tbuf tx buffer underrun flag: set when fsm qspi_if tried to pull data although tx buffer was empty. the ip command leading to the tx buffer underrun is continued (data sent to the serial flash device are undefined). the application must clear the tx buff er in response to this event by writing a a into the qspi_mcr[clr_txf] bit. rx buffer related flags rbof rx buffer overflow flag: set when not all the dat a read from the serial flash device could be pushed into the rx buffer. the ip command leading to this condition is contin ued until the number of bytes according to the qspi_ic[ico] field has been read from the serial flash device. the content of the rx buffer is not changed. rbdf rx buffer drain flag: will be set if th e qspi_sfmsr[rxwe] status bit is asserted. writing 1 into this bit triggers one of the following actions: ? if the rx buffer is has up to qspi_rbc t[wmrk] valid entries the flag is cleared. ? if the rx buffer has more than qspi_rbct[wmrk] valid entries and the qspi_sfmrser[rbdde] bit is not set (flag driven mode) a rx buffer pop event is triggered. the flag remains set if the rx buffer contains more than qspi_rbct[wmrk] valid entries after the rx buffer pop event is finished. the flag is cleared if the rx buffer contains le ss than or equal to qspi_rbct[wmrk] valid entries after the rx buffer pop event is finished. refer to section 35.5.3.5.2, receive buffer drain interrupt or dma request , for details. ahb command and ahb buffer related flags abcef ahb command error flag: set when the execution of an ahb command is started with an invalid ahb command programmed into the qspi_acr[aric] field 1 . no communication with the serial flash devi ce is initiated by the quadspi module. the ahb bus request which triggered this command is answered with an error response. abmef ahb command mode error flag: set when the execution of a valid ahb command is started and one of the following condition occurs: ? mode bit collision 2 is detected ? mode bit error 3 is detected. no communication with the serial flash devi ce is initiated by the quadspi module. the ahb bus request which triggered this command is answered with an error response. abof ahb buffer overflow flag: set when the module attempted to push data onto the ahb buffer that exceeded the size of the ahb buffer. this conditio n can occur only if the qspi_acr[arsz] field is programmed incorrectly. the ahb command leading to this condition is contin ued until the number of entries according to the qspi_acr[arsz] field has been read from the serial flash device. the content of the ahb buffer is not changed. ip command related flags iuef ip command usage error flag: set when in parallel flash mode the execution of an ip command is started and the qspi_icr[ic] field does not contain a dat a read command. refer to table 35-43 and table 35-47 for the related commands. no communication with the serial flash devi ce is initiated by the quadspi module. icef ip command error flag: set when the execution of an ip command is star ted and the qspi_icr[ic] field contains an invalid command. no communication with the serial flash devi ce is initiated by the quadspi module. table 35-20. qspi_sfmfr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-23 preliminary?subject to change without notice additional details about the error flags cont ained in that register can be found in table 35-35 . 35.4.4.14 interrupt and dma request select and enable register (qspi_sfmrser) the qspi_sfmrser register provides enables and se lectors for the interrupts in the quadspi module. imef ip command mode error flag: set when the execut ion of a valid ip command is started and one of the following condition occurs: ? mode bit collision 2 is detected ? mode bit error 3 is detected. no communication with the serial flash devi ce is initiated by the quadspi module. command arbitration and execution related flags ipaef ip command trigger during ahb access error flag. set when the following condition occurs: ? a write access occurs to the qspi_icr[ic] field and the qspi_s fmfr[ahb_acc] bit is set. any command leading to the assertion of the ipaef flag is ignored ipief ip command trigger could not be executed error flag. set when the qspi_sfmsr[ip_acc] bit is set and any of the following conditions occurs: ? write access to the qspi _icr register. any command leading to the assertion of the ipief flag is ignored ? write access to the qspi_sfar register. ? write access to the qspi_rbct register. ipgef ip command trigger during ahb grant error flag: set when the following condition occurs: ? a write access occurs to the qspi_icr[ic] fi eld and the qspi_sfmsr[ahbgnt] bit is set. any command leading to the assertion of the ipgef flag is ignored tff ip command transaction finished flag: set when the quadspi module has finished a running ip command. if an error occurred the re lated error flags are valid at th e latest in the same clock cycle when the tff flag is asserted. 1 invalid ahb command means that the qspi_acr[aric] fiel d is programmed to a command not reflecting data read. refer to table 35-43 and table 35-47 for the related commands. 2 refer to section 35.6.6, continuous mode commands , for the description of a mode bit collision. 3 when two serial flash devices are accessed simultaneously in parallel flash mode both of the related continuous mode bits qspi_sfmsr[cntmdfa] and qspi_sfmsr[cntmdfb] must match with the command. if this is not the case a mode bit error is detected. table 35-20. qspi_sfmfr field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 35-24 freescale semiconductor preliminary?subject to change without notice address: qspi_base + 0x164 write: anytime 0123456789101112131415 r0000 tbfie tbuie 0000 rbdde 000 rboie rbdie w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 abceie abmeie aboie iueie iceie imeie 0 ipaeie ipieie 0 ipgeie 0 00 tfie w reset0000000000000000 figure 35-15. interrupt and dma request select and enable register (qspi_sfmrser) table 35-21. qspi_sfmrser field descriptions field description tbfie tx buffer fill interrupt enable tbuie tx buffer underrun interrupt enable rbdde rx buffer drain dma enable: enables generation of dma requests for rx buffer drain. when this bit is set dma requests via the ipd_req_rfdf line are generated as long as the qspi_sfmsr[rxwe] st atus bit is set. 0 no dma request will be generated 1 dma request will be generated rboie rx buffer overflow interrupt enable rbdie rx buffer drain interrupt enable: enables gener ation of irq requests for rx buffer drain. when this bit is set the ipi_int_rfdf line is asserted as long as the qspi_sfmsr[rbdf] flag is set. 0 no rbdf interrupt will be generated 1 rbdf interrupt will be generated abceie ahb command erro r interrupt enable abmeie ahb mode error interrupt enable aboie ahb buffer overflow interrupt enable iueie ip command usage error interrupt enable iceie ip command error interrupt enable imeie ip command mode error interrupt enable ipaeie ip command trigger during ahb access error interrupt enable ipieie ip command trigger during ip access error interrupt enable ipgeie ip command trigger during ahb grant error interrupt enable tfie transaction finis hed interrupt enable
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-25 preliminary?subject to change without notice note each flag of the qspi_sfmfr register enabled as source for an interrupt prevents the quadspi module from en tering stop mode or module disable mode when this flag is set. refer to section 35.5.4, power saving features , for details. 35.4.4.15 rx buffer data registers 0?31 (qspi_rbdr0?qspi_rbdr31) the qspi_rbdr registers provide access to the individual entries in the rx buffer. refer to table 35-28 for the byte ordering scheme. qspi_rbdr0 corresponds to the actual position of the read pointer with in the rx buffer. the number of valid entries available depends on the number of valid buffer entries available in the rx buffer. example 1, rx buffer filled completely with 32 words : in this case the address range for valid read access extends from qspi_rbd r0 to qspi_rbdr31. example 2, rx buffer filled with 5 valid words : rx buffer fill level qspi_rbsr[rdbfl] is 5. in this case an access to qspi_rbdr4 pr ovides the last valid entry. any access beyond the range of valid rx buffer entries pr ovides undefined results. address: qspi_base + 0x200 (qspi_rbdr0) ... qspi_base + 0x27c (qspi_rbdr31) 0123456789101112131415 r rxdata[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxdata[15:0] w reset0000000000000000 figure 35-16. rx buffer data regi sters 0?31 (qspi_rbdr0?qspi_rbdr31) table 35-22. qspi_rbdr field descriptions field description rxdata rx data. the rxdata field contains the data associated with the related rx buffer entry. data format and byte ordering is given in section 35.5.3.4, byte orderi ng of serial flash read data .
pxd20 microcontroller reference manual, rev. 1 35-26 freescale semiconductor preliminary?subject to change without notice 35.4.5 ahb bus register memory map descriptions this chapter contains definitions of registers in the amba address space. 35.4.5.1 ahb bus access considerations it has to be noted that all logic in the quadspi m odule implementing the ahb bus access is related to read the content of an external serial flash device. ther efore the following restrictions apply to the quadspi module w.r.t. accesses to the ahb bus: ? any write access is answered with the er ror condition according to the amba ahb specification. no write occurs. ? any ahb command resulting in the assert ion of the qspi_sfmfr[abcef] or the qspi_sfmfr[abmef] flags is answered wi th the error condition according to the amba_ahb specification. the resu lting ahb command is ignored. ? ahb bus access types fully s upported are nonseq and busy. ? ahb access type seq is treated in the same way like nonseq. refer to the amba ahb specification for further details. 35.4.5.2 memory mapped serial flash data - individua l flash mode on flash a starting with address 0x7000_0000 the content of the first external se rial flash devices is mapped into the address space of the device containing the quadspi module. serial flash address byte address 0x0 corresponds to bus addr ess 0x7000_0000 with increasi ng order. refer to table 35-23 below for the address mapping. the byte ordering for 32 bit access is given in table 35-28 and for 64 bit read access the byte ordering is given in table 35-32 . the available address range depends from the size of the external se rial flash device. any access beyond the size of the external serial flash provides undefined results. for details concerning th e read process refer to section 35.5.3.3, flash read . 35.4.5.3 memory mapped serial flash data - individua l flash mode on flash b starting with address 0x7800_0000 the content of the first external se rial flash devices is mapped into the address space of the device containing the quadspi module. serial flash address byte address 0x0 corresponds to bus addr ess 0x7800_0000 with increasi ng order. refer to table 35-24 below for the address table 35-23. memory mapped individual flash mode - flash a address scheme memory mapped address 32 bit access memory mapped address 64 bit access serial flash byte address 0x7000_0000 0x7000_0000 0x000_0000 - 0x000_0003 0x7000_0004 0x000_0004 - 0x000_0007 ... ... ... 0x77ff_fff8 0x77ff_fff8 0x7ff_fff8 - 0x7ff_fffb 0x77ff_fffc 0x7ff_fffc - 0x7ff_ffff
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-27 preliminary?subject to change without notice mapping. the byte ordering for 32 bit access is given in table 35-28 and for 64 bit read access the byte ordering is given in table 35-32 . the available address range depends from the size of the external se rial flash device. any access beyond the size of the external serial flash provides undefined results. for details concerning th e read process refer to section 35.5.3.3, flash read . 35.4.5.4 memory mapped serial fl ash data - parallel flash mode starting with address 0x8000_0000 the content of both (identical) extern al serial flash devices is mapped into the address space of the device containing the quadspi module. serial fl ash address byte address 0x0 of both flash devices co rresponds to bus address read from bus address 0x8000_0000 provide s bits [7:4] of both serial fl ash devices and read from bus address 0x8000_0001 provides bits [3:0] of both flash devices. refer to table 35-25 below for the address mapping. the byte ordering for 32 bit access is given in table 35-30 and for 64 bit read access the byte ordering is given in table 35-32 . table 35-24. memory mapped individual flash mode - flash b address scheme memory mapped address 32 bit access memory mapped address 64 bit access serial flash byte address 0x07800_0000 0x7800_0000 0x000_0000 - 0x000_0003 0x07800_0004 0x000_0004 - 0x000_0007 ... ... ... 0x07fff_fff8 0x7fff_fff8 0x7ff_fff8 - 0x7ff_fffb 0x07fff_fffc 0x7ff_fffc - 0x7ff_ffff table 35-25. memory mapped parallel flash mode address scheme memory mapped address 32 bit access memory mapped address 64 bit access serial flash a byte address serial flash b byte address 0x8000_0000 0x8000_0000 0x000_0000 - 0x000_0001 0x000_0000 - 0x000_0001 0x8000_0004 0x000_0002 - 0x000_0003 0x000_0002 - 0x000_0003 0x8000_0008 0x8000_0008 0x000_0004 - 0x000_0005 0x000_0004 - 0x000_0005 0x8000_000c 0x000_0006 - 0x000_0007 0x000_0006 - 0x000_0007 ... ... ... ...
pxd20 microcontroller reference manual, rev. 1 35-28 freescale semiconductor preliminary?subject to change without notice the usable space depends from the size of the external seri al flash devices. any access beyond the size of the external serial flash provides undefined results. for details concerning th e read process refer to section 35.5.3.3, flash read . 35.4.5.5 ahb rx data buffer (qspi_ardb0 to qspi_ardb31) the ahb rx data buffer register 0 to 31 can be us ed to read the buffer cont ent of the rx buffer from successive addresses. qspi_ardb0 corresponds to the rx buffer re gister entry corresponding to the current value of the read po inter with increasing order. the increment of the read pointer depends from th e access scheme (dma or flag-driven). refer to section 35.5.3.3.2, data transfer from th e quadspi module internal buffers , topic rx buffer, data read via register interface and ahb read for the description of successive acc esses to the rx buffer content. refer also to section 35.5.3.4, byte ordering of serial flash read data , for the byte ordering scheme. 0x8fff_fff8 0x8fff_fff8 0x7ff_fffc - 0x7ff_fffd 0x7ff_fffc - 0x7ff_fffd 0x8fff_fffc 0x7ff_fffe - 0x7ff_ffff 0x7ff_fffe - 0x7ff_ffff address: 0x9000_0000 for qspi_ardb0 0x9000_007c for qspi_ardb31 0123456789101112131415 r arxd[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rarxd[15:0] w reset0000000000000000 figure 35-17. ahb rx data buff er (qspi_ardb0 to qspi_ardb31) table 35-26. qspi_ardb field descriptions field description arxd amba provided rx buffer data. byte order (endianess) is identical to the rx buffer data registers. table 35-25. memory mapped parallel flash mode address scheme (continued) memory mapped address 32 bit access memory mapped address 64 bit access serial flash a byte address serial flash b byte address
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-29 preliminary?subject to change without notice valid address range accessible in the qspi_ardbn range depends on th e number of valid buffer entries available in the rx buffer. ? example 1, rx buffer filled completely with 32 words : in this case the addres s range for valid read access extends from qspi _ardb0 to qspi_ardb31. ? example 2, rx buffer filled with 5 valid words, rx buffer fill level qspi_rbsr[rdbfl] is 5. in this case an access to qspi_ard b4 provides the last valid entry. 35.5 functional description 35.5.1 serial flash access schemes the quad serial peripheral interface (quadspi) block ac ts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. depe nding from the serial flash devices attached to the quadspi module the fo llowing access schemes are possible: note if two flash devices are accessed in pa rallel flash mode they are accessed with identical control signals. speci al alignment on per-flash basis is not possible. it is within the responsibility of the applic ation to ensure that the identical signals are applicab le to both flash devices. in parallel flash mode both external se rial flash devices appear logically as one single memory doubled in size w. r.t. one individual flash device. if two different flash devices are at tached they can be operated only in individual flash mode. in the parallel flash mode only da ta read commands are supported. any other ip command will result in an error condition signal led by the assertion of the qspi_sfmfr[iuef] flag and any other ahb command will result in the assertion of the qspi_sfmfr[abcef] flag. in the individual flash mode all supported commands are available. unless explicitly noted all the following descri ptions relate to the individual flash mode. table 35-27. access schemes for serial flash data access access scheme one flash device on port a one flash device on port b two identical flash devices connected on port a and port b individual flash mode: access to flash a yes n/a yes individual flash mode: access to flash b n/a yes yes parallel flash mode: read fr om flash a and flash b n/a n/a yes
pxd20 microcontroller reference manual, rev. 1 35-30 freescale semiconductor preliminary?subject to change without notice 35.5.2 modes of operation refer to section 35.1.3, quadspi modes of operation for an overview over the possible operational modes of the quadspi block. ? normal mode can be used for write or read accesses to an external serial flash device. ? serial flash write: data can be programmed into the flash of th e serial flash device. refer to section 35.5.3.2, flash programming , for further details. ? serial flash read: read the contents of the seri al flash device. two sepa rate read channels are available via rx buffer and ahb buffer, see section 35.5.3.3, flash read . ? stop mode: the mode is used fo r power management. when a request is made to enter stop mode, the quadspi block acknowledges th e request and completes the sf m command in progress, then the system clocks to the quadspi block may be shut off, see section 35.5.4.1, stop mode . ? module disable mode: the mode is used for power management. the clock to the non-memory mapped logic in the quadspi can be stopped whil e in module disable m ode.the module enters the mode by setting qspi_mcr[mdis] or when a request is asserted by an external controller. see section 35.5.4.2, module disable mode , for more details. 35.5.3 normal mode this mode is used to allow communication with an exte rnal serial flash device. compared to the standard spi protocol, this communication method uses up to 4 bidirectional data li nes operating at high data rates. the communication to the external seri al flash device consists of an instruction code and optional address, mode, dummy and data transfers. all operations to the external serial flash device may use only instruction codes listed in section 35.8, serial flash devices . 35.5.3.1 issuing sfm commands each access to the external device follows the same sequence: 1. the user must provide the required componen ts of a sfm command to the quadspi module. 2. from these components the complete transaction is built. the transaction starts and the status bit qspi_sfmsr[busy] is set. 3. communication with the external serial flash de vice is started and the transaction is executed. 4. when the transaction is finished (all transmit- and receive operations with the external serial flash device are finished) the status bit qspi_sfmsr[bus y] is reset. in case of an ip command the qspi_sfmfr[tff] flag is asserted. further details are given in below in section 35.5.3.2, flash programming , and section 35.5.3.3, flash read . note that there are 2 diffe rent ways to trigger the processing of sfm commands in the quadspi module. 35.5.3.1.1 ip commands for ip commands the required components need to be written into the following registers:
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-31 preliminary?subject to change without notice ? read address of the serial flash into qspi_sfar, refer to section 35.4.4.4, serial flash address register (qspi_sfar) ,. for ip commands not related to speci fic addresses the ba se address of the related flash need to be programmed. ? instruction code options belonging to the ip command into the qspi_icr[ico] field. ? instruction code belonging to the ip command into the qspi_icr[ic] field. note that the write into the qspi_icr[ic] field must be the last step of th e sequence. it is possible to combine both fields of the qspi_i cr into one single write. refer to section 35.4.4.5, instruction code register (qspi_icr) , for details. note that there are some conditions were no ip command is executed af ter writing the qspi_icr[ic] field and the write operation itself is ignored. they are described in section 35.6.4, command arbitration . 35.5.3.1.2 ahb commands note that the required components of the ahb commands are located in different registers w.r.t. the ip commands. they need to be written into the qspi_acr register like described in section 35.4.4.11, amba control register (qspi_acr) . the ahb command itself is triggered by a read acces s of the host into the memory mapped serial flash data, like described in section 35.4.5.2, memory mapped serial fl ash data - individual flash mode on flash a . again the possible error c onditions are described in section 35.6.4, command arbitration . 35.5.3.2 flash programming in all cases the memory sector to be written needs to be erased first. the pr ogramming sequence itself is then initiated in the following way: 1. check that the tx buffer is em pty. if the qspi_sfmsr[txne] bit is set the tx buffer must be cleared by writing 1 into the qspi_mcr[clr_txf] bit. 2. program the address related to the command in the qspi_sfar register. optionally one can clear the qspi_tbsr[trctr] field by writ ing 1 into qspi_mcr[clr_txf]. 3. provide initial data for the program command into the circular buffer via re gister tx buffer data register (qspi_tbdr). at least one word of data must be written into the tx buffer. 4. program the required instruction code options (i.e . size of data) into the qspi_icr[ico] register. 5. trigger the ip command to program the serial flash devi ce by writing the instruction code into the qspi_icr[ic] register. 6. depending from the amount of data required step 3 must be repeated until all the required data have been written into the qspi_tbd r register. at any time the q spi_tbdr[trctr] field can be read to check how many words have been written actually into the tx buffer. steps 4 and 5 may be executed together. upon writing the qspi_icr[i c] field (refer to step 5) the quadspi module will start to execute the command by transferring instruction c ode, address and then data to the external device. the data are fetched from the tx buffer. it consists of 15 entries wi th 32-bit and is organized as a circular fifo, whose
pxd20 microcontroller reference manual, rev. 1 35-32 freescale semiconductor preliminary?subject to change without notice read pointer is incremented after e ach fetch. when all data are transmitted, the quadspi module will return from ?busy? to ?idle?. however, this is not true for the external device since the internal programming is still ongoing. it is up to the user to monitor the relevant status informat ion available from the serial flash device and to ensure that the pr ogramming is finished properly. 35.5.3.3 flash read host access to the data stored in the external serial flash device is done in two st eps: first the data must be read into the internal buffers and in the second st ep these internal buffers can be read by the host. 35.5.3.3.1 reading seri al flash data into the quadspi module read access to the external serial flash de vice can be triggered in two different ways: ? ip command read : for reading flash data into the rx buffer the user must provide the required components of the relate d sfm command, including the select ion of the flash device and the access mode, to the qspi_sfar and the qspi_i cr registers. all avai lable read commands supported by the external se rial flash are possible. optionally it is possible to clear the rx buffer pointer prior to triggering the ip command by writing a 1 into the qspi_mcr[clr_rxf] bit. from these inputs the complete transaction is bui lt when the qspi_icr[ic] field is written. the transaction related to the read access starts and the requested number of bytes is fetched from the external serial flash device into the rx buffer. si nce the read access is tr iggered by an ip command the ip_acc status bit is set driving in turn th e busy bit (both are located in the qspi_sfmsr). the communication with the external serial flas h is stopped when the specified number of bytes has been read (successful co mpletion of the transaction). ? ahb command read : for reading flash data into the ahb buffer the user must setup a read access to the address range were the external serial flash devices ar e mapped to by programming the qspi_acr register with the requested data not alre ady available in the ahb buffer . flash device selection and access mode ar e determined by the address acces sed in the ahb address space associated to the quad spi module, refer to section 35.4.5.2, memory mapped serial flash data - individual flash mode on flash a , section 35.4.5.3, memory mapped serial flash data - individual flash mode on flash b , and section 35.4.5.4, memory mapped serial flash data - parallel flash mode . on each ahb read access to the memory mapped area the valid data in the ahb buffer are checked against the address requested in the act ual read. when the ahb read request can?t be served from the content of the ahb buffer the co mplete transaction to access the external serial flash device is built from the qspi_acr regist er contents and started. the requested number of buffer entries defined in the qspi _acr[arsz] field is then fetched from the ex ternal serial flash device into the internal ahb buffer. since the read access is triggered via the ahb bus the qspi_sfmsr[ahb_acc] status bit is set driving in turn the qspi_sfmsr[busy] bit until the transaction is finished. the co mmunication with the external se rial flash is stopped when the specified number of en tries has been filled. basically the ahb buffer behaves similar to a cac he memory with a size of one single line.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-33 preliminary?subject to change without notice 35.5.3.3.2 data transfer from the quadspi module internal buffers the data read out from the external serial flash de vice by the quadspi module are stored in the internal buffers. depending from the buffer to which the data from the external serial flas h has been loaded there are several different ways to access these data in the internal buffers. refer to figure 35-1 for details about the two available buffers, the rx buffer a nd the ahb buffer, in the quadspi module: ? the rx buffer is implemented as fifo of depth 32 entries of 4 bytes. its content is accessible in two different address areas both re ferring to the identical data. ? in the ips address space in the area a ssociated to qspi_rbd r0 to qspi_rbdr31. ? in the ahb address space in the area associated to qspi _ardb0 to qspi_ardb31. two successive entries are accessed with one single 64 bit ahb read operation. rx buffer operation can be su mmarized as follows: the qspi _rbct[wmrk] field determines at which fill level the rxwe bit is asserted and how many entries are remo ved from the rx buffer on each buffer pop operation. so the qspi_sfm sr[rxwe] bit indicates that the configured number of data entries is availa ble in the rx buffer and the q spi_rbsr[rdbfl] field indicates how many valid entries are available in total. note that the first entry (qspi_rbdr0 or qspi_ardb0) always corresponds to the first valid entry in the rx buffer. further details can be found in section 35.4.4.15, rx buffer data registers 0?31 (qspi_rbdr0?qspi_rbdr31) , and in section 35.4.5.5, ahb rx data buffer (qspi_ardb0 to qspi_ardb31) . ? flag-based data read of the rx buffer is done by polling the qspi _sfmfr[rxwe] bit. when it is asserted the valid entries can be read either via the ips address space (qspi_rbdrn) or the ahb address space (qspi_ardbn). a buffer pop operation must be triggered by the application by writing a 1 into the qspi_sfmfr[rbdf] bit. ? dma controlled data read of the rx buffer is done by using the dma capabilities of the quadspi and the device containing the quadspi m odule. the application mu st ensure that the dma controller of the related device is program med appropriately like it is described in section 35.6.7, dma usage . dma controlled read out is triggered fu lly automatically by the assertion of the qspi_sfmfr[rxwe] bit. the related buffer pop operation is also handled completely inside the quadspi module. like in the case above accessing the rx buffer content either on qspi_rbdrn or qspi_ardbn rela ted addresses is equivalent. ? ahb buffer data read vi a memory mapped access : this kind of access is done by reading one of the addresses assigne d to the external serial flash de vice(s) within the range given in table 35-5 under the condition that the data reque sted are already present in the ahb buffer or it is currently read from the serial flash device . if this is not the case a memory mapped read of the ahb buffer is triggered like descri bed above). as long as the requested da ta are already available in the ahb buffer they are provided to the host. the host can re ad the available data out of the ahb buffer in any order. if the address requested by the current read is the one currently fetched by the quadspi module from the serial flash the execution of the curr ent command remains running with the ahb read access stalled. as soon as the da ta from the requested address have been read by the quadspi module the ahb read access is serv ed. so it?s possible to run seque ntial read from the ahb buffer
pxd20 microcontroller reference manual, rev. 1 35-34 freescale semiconductor preliminary?subject to change without notice at arbitrary speed without the need to monitor a ny information about the av ailability of the data. nevertheless this access scheme stalls the ahb bus for the time required to read the data from the serial flash device. as long as the host restricts its accesses to the da ta already in the buffer and the data currently fetched from the serial flash it is possible to run the host read from the ahb buffer in parallel to the serial flash read into the ahb buffer. 35.5.3.4 byte ordering of serial flash read data in this paragraph the byte ordering of the serial fl ash data is given. the basic scheme is that the first byte read out of the serial flash device - which is a ddressed by the qspi_sfar[sfadr] field - corresponds to bit position qspi_rbdr0[0:7] register for ip command read. in cont rast to that for ahb command read the bytes are always posi tioned according to the byte ordering of the ahb bus. 35.5.3.4.1 byte ordering in individual flash mode table 35-28 below gives the byte ordering scheme how the byte oriented data space of the serial flash device is mapped into one single 32 bi t entry of the rx buffer or the ah b buffer. the table is valid within the following context: ? flash a or flash b in individual flash mode ? all ahb data read commands with access size of 32 bit note for ip commands the read size can be given in number of bytes. if this number is not a multiple of 4 the last buffer entry is not completely filled with the missing higher numbere d bytes at undefined values. for ahb command read starting from an address not aligned to 32 bi t boundaries the requested bytes are given at the appropriate positions according to th e amba ahb specification. 35.5.3.4.2 byte ordering in parallel flash mode in parallel flash mode each byte is co mbined out of 2 half bytes which ar e read in parallel from the two serial flash devices. table 35-29 below shows how the flas h content is separated into the half bytes and table 35-30 shows how the half bytes are assembled to the content of the qspi_rbdr0 register. table 35-28. byte ordering in individual flash mode serial flash byte numbering 0123 buffer entry bit position [31:0] (32 bit data width) [7:0] [15:8] [23:16] [31:24]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-35 preliminary?subject to change without notice the table entry naming reflects the half byt e positioning in the serial flash devices: ? h0 means flash a , h0 means flash b . ?fa 0 means half byte in high position , fao means half byte in low position . ?fah <0> means physical byte address 0 in the serial flash device, fal<1 > means physical byte address 1 in the serial flash device. note for ip commands the read size can be given in number of bytes. if this number is not a multiple of 4 the last buffer entry is not completely filled with the missing higher numbere d bytes at undefined values. table 35-29. serial flash device half byte ordering serial flash device byte # flash a bit position flash b bit position [7:4] [3:0] [7:4] [3:0] 0 fah0 fal0 fbh0 fbl0 1 fah1 fal1 fbh1 fbl1 2 fah2 fal2 fbh2 fbl2 3 fah3 fal3 fbh3 fbl3 4 fah4 fal4 fbh4 fbl4 5 fah5 fal5 fbh5 fbl5 6 fah6 fal6 fbh6 fbl6 7 fah7 fal7 fbh7 fbl7 8 fah8 fal8 fbh8 fbl8 table 35-30. byte ordering in parallel flash mode - rx buffer qspi_sfar[sfadr] set to 0x000_0000 qspi_rbdr0 qspi_ardb0 fah0 fbh0 fal0 fbl0 fah1 fbh1 fal1 fbl1 qspi_rbdr1 qspi_ardb1 fah2 fbh2 fal2 fbl2 fah3 fbh3 fal3 fbl3 qspi_sfar[sfadr] set to 0x000_0001 qspi_rbdr0 qspi_ardb0 fah1 fbh1 fal1 fbl1 fah2 fbh2 fal2 fbl2 qspi_rbdr1 qspi_ardb1 fah3 fbh3 fal3 fbl3 fah4 fbh4 fal4 fbl4
pxd20 microcontroller reference manual, rev. 1 35-36 freescale semiconductor preliminary?subject to change without notice note for ahb command read starting from an address not aligned to 32 bit boundaries or ahb access size smaller than 32 bit the requested bytes are given at the appropriate positi ons according to the amba ahb specification. 35.5.3.4.3 buffer entry ordering for 64 bit read access for read access via the ahb interface 64 bit access is possible. each 64 bit access reads 2 32 bit entries simultaneously. the ordering of these 32 bit en tries within the 64 bit word is given in table 35-32 below: 35.5.3.5 normal mode inte rrupt and dma requests the quadspi module has 10 different flags that can onl y generate interrupt requests and one flag that can generate interrupt as well as dma requests. table 35-34 lists the eight conditions . note that the flags mentioned in the table relate to the flag register (qspi_sfmfr). table 35-31. byte ordering in parallel flash mode - ahb buffer ahb address 0x8000_0000 (32 bit access) fah0 fbh0 fal0 fbl0 fah1 fbh1 fal1 fbl1 ahb address 0x8000_0004 (32 bit access) fah2 fbh2 fal2 fbl2 fah3 fbh3 fal3 fbl3 table 35-32. 64 bit read access buffer entry ordering ahb read data bit position [63:0] [31:0] [63:32] buffer entry # even (0, 2, 4, ...) odd (1, 3, 5, ...) table 35-33. if sclk input and output signals signal i/o width comment new_command i 1 request for new transaction to external serial flash ctrl_vector i 90 parameters for new transaction cont_mode i 1 indicates if the external serial flash device is in continous mode ?1? = yes sfm_samp_params i 5 controls delay and phase when to sample data sent from serial flash cutil_rdy o 1 state machine ready to accept a new command rdata_valid o 1 newly read data word is available rdata o 33 32 bit rdata + indicator bit for real rdata tx_underrun o 1 transaction had to be terminated prematurely due to insufficient tx data rx_overrun o 1 transaction had to be terminated prematurely due to rx buffer overflow cont_mode_sent o 1 control byte for continous mode has been sent tr_complete o 1 transaction complete
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-37 preliminary?subject to change without notice each condition has a flag bit in the qspi_sfmfr a nd a request enable bit in the qspi_sfmrser. the rx buffer drain flag (rbd f) has separate enable bits for gene rating irq and dma requests. note that not each single flag is represen ted by an individual irq line. 35.5.3.5.1 transmit buff er fill interrupt request the transmit buffer fill irq indica tes that the tx buffer can accept new data. it is asserted if the qspi_sfmfr[tbff] flag is assert ed and if the corresponding enable bit (qspi_sfmrser[tbfie]) is set. refer to section 35.5.3.6, tx buffer operation , for details about the assertion of the qspi_sfmfr[tbff] flag. 35.5.3.5.2 receive buffer dr ain interrupt or dma request the receive buffer drain irq derive d from the qspi_sfmfr[rbdf] flag indicates that the rx buffer of the quadspi module has data available from the serial flash device to be read by the host. it remains set as long as the qspi_rbsr[rxwe] bit is set. the qspi_sfmrser[rbdie] bit en ables the related irq. aside from the irq it is possibl e to handle rx buffer drain by dm a. if the qspi_sfmrser[rbdde] bit is set each write of the module into the rx buff er triggers a dma request. the application must set the environment appropriately (e.g. the dm a controller) for the dma transfers. 35.5.3.5.3 buffer overflow/ underrun interrupt request the buffer overflow/underrun irq is a combinati on of the following flags (all located in the qspi_spifr register with the related enab le bits in the qspi_spirser register): table 35-34. interrupt and dma request conditions condition flag (qspi_spisr) dma tx buffer fill tbff tx buffer underrun tbuf rx buffer drain rbdf x rx buffer overflow rbof ahb buffer overflow abof ahb command error abcef ahb command mode error abmef ip command usage error iuef ip command error icef ip command mode error imef ip command trigger during ahb access error ipaef ip command trigger could not be executed error ipief ip access during ahb grant error ipgef ip command related transaction finished tff
pxd20 microcontroller reference manual, rev. 1 35-38 freescale semiconductor preliminary?subject to change without notice ? tbuf - tx buffer underrun, enabled by tbu_ie ? rbof - rx buffer overflow, enabled by rbo_ie ? abof - ahb buffer overflow, enabled by abo_ie the transmit buffer underrun indicates that an under run condition in the tx buff er has occurred. it is generated when the tx buffer is empty, a tran sfer to the serial flash is initiated and the qspi_spirser[tfuf_ie] bit is set. the receive buffer overflow indicates that an overf low condition in the rx buffer has occurred. it is generated when the rx buffer is full, an additional read transfer attempts to write into the rx buffer and the qspi_sfmrser[rbo_ie] bit is set. the ahb buffer overflow indicates that an overflow condition in the ahb buffer has occurred. it is generated when the ahb buffer is fu ll, an additional read transfer atte mpts to write into the ahb buffer and the qspi_sfmrser[abo_ie] bit is set. the data from the transfers that generated the individual overflow conditions are ignored. 35.5.3.5.4 serial flash comm and error interrupt request the ipaef, ipief, ipgef, abcef, abmef, iuef, icef and imef flags in the qspi_sfmsr and the related interrupt enable bits in the qspi_sfmrser determine the assertion of the interrupt line. 35.5.3.5.5 transaction fi nished interrupt request the ip command transaction finish ed irq indicates the completion of the current ip command. it is masked by the qspi_sfmsr[tf_ie] bit. 35.5.3.6 tx buffer operation the tx buffer provides the data used for page programming. for prope r operation it is re quired to provide at least one entry in the tx buffer prior to starting the execution of the page programming command. the application must ensure that the required number of da ta bytes is written into the tx buffer fast enough as long as the command is executed wi thout a tx buffer overflow or underrun. the quadspi module sets the qspi_sfmfr[tbff] flag initially and subsequent ly as long as the tx buffer can accept more data to be written into. when the quadspi module tries to pull data out of an empty tx buffer the tx buffer underrun is signalled by the qspi_sfmfr[tbuf] flag. the current ip command leading to the underrun condition is continued until the specified number of bytes has been sent to the serial flash device. when the sfm command has been finished the qspi _sfmfr[tbff] flag is asserted. the tx buffer overflow isn?t signalled explicitly, bu t the tx buffer fill level can be monitored by the qspi_tbsr[trbfl] field. refer to section 35.4.4.9, tx buffer stat us register (qspi_tbsr) , and section 35.4.4.13, flag register (qspi_sfmfr) , for details about the tx buffer related registers and to section 35.5.3.5.1, transmit buffer fill interrupt request , for details about the usage of the associated interrupt.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-39 preliminary?subject to change without notice 35.5.4 power saving features the quadspi supports three power-saving strategies: ? stop mode ? module disable mode - clock ga ting of non-memory mapped logic ? clock gating of slave bus signals and clock to memory-mapped logic like all power saving features th e stop mode requires logic external to the quadspi module for power management and clock gating control. figure 35-18 shows an example on how the quadspi power saving features can be used: figure 35-18. power saving mode concept of quadspi module 35.5.4.1 stop mode the quadspi has a dedicated low pow er mode managed by the mode entr y module. when the mode entry module requests the quadspi module to enter low power mode, the quadspi block waits until the following conditions are met before completing the mode transition: ? qspi_sfmsr[busy] = 0 and ? qspi_sfmsr[ahbtrn] = 0 and ? qspi_rbsr[rdbfl] = 0 and ? qspi_sfmsr[rxdma] = 0 ? none of the flags in the qspi_sfmfr register enabled as interrupts is set system clock ipg_clk ipg_stop ipg_enable_clk d q ips_module_en ips_addr, ips_byte_en, ips_rwb, ips_wdata ipg_stop_ack power management ipg_clk_s forced to 0 block non-memory mapped area memory mapped area quadspi power saving logic d_rsvd mdis & & & & & & &
pxd20 microcontroller reference manual, rev. 1 35-40 freescale semiconductor preliminary?subject to change without notice the conditions given above ensure that there is no sfm command currently exec uted, all the data read into the rx buffer from the serial flash have been fetched by the application. it is also ensured that no current ahb access, no active dma nor any enabled interrupt is pending note that it is not visible to the application whether the module ha s already negated the ipg_enable_clk. while the clocks are shut off, the quadspi memory-mapped logic is not accessible. certain read or write operations have a different effect wh en the quadspi is in the stop mode . in the stop mode not all of the status and flag bits of the quadspi module are updated and writing to them will have no effect. interrupt and dma request signals cannot be cleared while in the stop mode. note that there is a time where it is illegal to issue a new sfm command. this time starts, due to the internal processing pipeline, 2 clock cycles prior to raising the request to go into stop mode. this time ends with leaving the stop mode. 35.5.4.2 module disable mode module disable mode is a block-specific mode that the quadspi can enter to save power. there are two possibilities to request ente ring the module disable mode: ? host software can initiate the module disable mode by writing a ?1? to the mdis bit in the qspi_mcr. ? the module disable mode can al so be initiated by hardware. a power management block can initiate module disable mode by asserting the ipg_doze signal while the doze bit in the qspi_mcr is asserted. when a request is encountered to enter the module disable mode the quadspi negates ipg_enable_clk when it is ready to enter the module disable mode. the condition to enter the module disable mode is reached when: ? qspi_sfmsr[busy] = 0 and ? qspi_sfmsr[ahbtrn] = 0 and ? qspi_rbsr[rdbfl] = 0 ? qspi_sfmsr[rxdma] = 0 ? none of the flags in the qspi_sfmfr register enabled as interrupts is set the conditions given above ensure that there is no sfm command currently exec uted, all the data read into the rx buffer from the serial flash have been fetched by the application. it is also ensured that no current ahb access, no active dma nor any enabled interrupt is pending note that it is not visible to the application whether the module ha s already negated the ipg_enable_clk. if implemented, the ipg_enable_cl k signal can stop the clock to th e non-memory mapped logic. when ipg_enable_clk is negated and the ipg_clk is stopped th e quadspi is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different effect when the quadspi is in the module disable mode . in the module disable mo de not all of the stat us and flag bits of the quadspi module are updated and writing to them will have no effect. interrupt and dma request signals cannot be cleared whil e in the module disable mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-41 preliminary?subject to change without notice note that there is a time where it is illegal to issue a new sfm command. this time starts, due to the internal processing pipeline, 2 clock cycles prior to raising the reques t to enter the module disable mode. this time ends with leaving the module disable mode. 35.5.4.3 leaving power saving modes in the stop mode and the module disable mode the cl ocks to the quadspi module are switched off by external circuitry. note that after the quadspi modul e has left these power savi ng modes and has returned to normal mode the execution of the first sfm command is defe rred until the clock to drive that part of the module related to the serial flash device is availa ble. depending from the point in time when the first sfm command is triggered the actual execution of that command will star t with a slight delay w.r.t. the re-enabling of the clock signal. 35.5.4.4 slave bus signal gating the quadspi?s module enable signal is used to gate slave bus signals such as address, byte enable, read/write and data. this prevents toggling slave bus signals from propagat ing through parts of the quadspi?s combinational logic and consuming power unless it is a quadspi access. the module enable signal can also be used to gate the cl ock (ipg_clk_s) to the memory-mapped logic. 35.6 initialization/application information 35.6.1 power up and reset note that the serial flash devices connected to the quadspi module may require special voltage characteristics of their input s during power up or reset. it is within the responsibil ity of the application to ensure this. 35.6.2 available status/flag information this paragraph gives an overview over the different status and flag informat ion available and their interdependencies for different use cases. related registers are qspi_sfmsr and qspi_sfmfr. refer to the related descriptions how to set up the quadspi module appropriately. 35.6.2.1 ip commands refer to section 35.4.4.5, instruction code register (qspi_icr) , for additional details not explicitly covered in this paragraph. 35.6.2.1.1 ip commands - normal operation writing the qspi_icr[ic] field triggers the execution of a new ip command. given that this is a legal command the qspi_sfmsr[ipacc] a nd the qspi_sfmsr[busy] bits are asserted simultaneously immediately after the execution is started. when the instruction on the serial flash device has been finished these bits are de-asserted and the qspi_sfmfr[tff] flag is set.
pxd20 microcontroller reference manual, rev. 1 35-42 freescale semiconductor preliminary?subject to change without notice 35.6.2.1.2 ip commands - error situations refer to table 35-35 below. 35.6.2.2 ahb commands refer to section 35.5.3.3.1, reading serial flas h data into the quadspi module , for additional details not explicitly covered in this paragraph. 35.6.2.2.1 ahb commands - normal operation memory mapped read access to a serial flash address not covered in the ahb buffer triggers the execution of an ahb command. given that this is a le gal command the qspi_sfmsr[ahbacc] and the qspi_sfmsr[busy] bits are asserted simultaneous ly immediately after th e execution is started. when the instruction on the serial flash device has been finished these bits are de-asserted. 35.6.2.2.2 ip commands - error situations refer to table 35-35 below. 35.6.2.3 overview of error flags table 35-35 below gives an overview of the different er ror flags in the qspi_sfmfr register and additional error-related details.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-43 preliminary?subject to change without notice note that only the buffer related errors are related to a transaction on the external serial fl ash. all the other errors do not trigger an actual transaction. 35.6.2.4 ip bus and ahb ac cess command collisions there are two flags related to this topic, th e qspi_sfmfr[ipaef] and qspi_sfmfr[ipief]. see section 35.5.3.3.1, reading serial flash data into the quadspi module , for a description of the flags itself and to section 35.6.4, command arbitration , for details about possible command collisions. table 35-35. overview of qspi_sfmfr error flags error category error flag in qspi_sfmfr command execution on serial flash device tff behavior description command arbitration errors ipief no -> tff not asserted in conjunction with that command attempt to trigger ip command not be executed. ? ip command already running, write attempt to qspi_ic register. ? ip command running, attempt to write qspi_sfar register. ? ip command running, attempt to write qspi_rbct register. ipaef ? ahb command already running, another ip command could not be executed. ? ahb command already running, write attempt to qspi_icr[ic] field. ipgef ? exclusive access to the serial flash granted for ahb commands, write attempt to qspi_icr[ic] field. ahb command errors abcef no -> tff not asserted in conjunction with that command ? ahb command error abmef ? ahb command mode error 1 1 refer to section 35.6.6, continuous mode commands , for the description of a mode bit collision ip command errors iuef ? ip command usage error icef ? ip command error imef ? ip command mode error 1 buffer related errors rbof yes -> tff is asserted on completion ? rx buffer overrun tbuf ? tx buffer underrun
pxd20 microcontroller reference manual, rev. 1 35-44 freescale semiconductor preliminary?subject to change without notice 35.6.3 exclusive access to serial flash for ahb commands it is possible that severa l masters need to access th e serial flash device conne cted to the quadspi module separately, one master by triggeri ng ip commands and reading the rx buffer and the other masters by triggering ahb commands. to avoid command collisi ons resulting in excessive latencies the quadspi module implements a request-handshake mechanism be tween the master trigge ring ahb commands and the quadspi module allowing this specif ic master to request exclusive acc ess to the serial flash device for ahb commands. if this exclusive access is granted th e execution of ip commands is blocked. this resolves command collisions and excessive ti mes where the ahb interface may be blocked. if this capability is used in the device there is addi tional status and flag inform ation available related to this mechanism. the qspi_sfmsr[ahbgnt] bit reflec ts the module-internal state that the exclusive access mentioned above is granted, a ny attempt to trigger an ip comma nd is rejected and results in the assertion of the qspi_sfmfr[ip gef] flag. refer to the descriptions of the related bit and flag for details. it is within the responsibility of the application to set up the master using this mechanism appropriately, if used incorrectly no ip comma nds at all can be triggered. two different cases can be distinguished: 35.6.3.1 rx buffer read via qspi_ardb registers in this case all masters share the ahb bus for rx buffer as well as for ahb buffer read. in this case the access to the ahb interface by the ma ster triggering ahb commands must be deferred until any pending ip command has been finished and the rx buffer readout has been finished as well. this is the conservative use case, corres ponding to the reset value 0 of the qspi_rbct[rxbrd] bit. in this case the qspi_sfmsr[ahbgnt] bit is assert ed not earlier than any running ip command has been finished (qspi_sfmsr[ip_acc] is 0), the rx buffer has been read out completely (qspi_rbsr[rdbfl] equal to 0) and no dma read is pending (qspi_sfmsr[rxdma] equal to 0. 35.6.3.2 rx buffer read via qspi_rdbr registers this is the preferred use case. it is not possibl e that a pending ahb bus access triggered by an ahb command stalls the ahb bus and blocks the rx buffer readout since the rx buffer is read via the ip bus based registers qspi_r bdr0 to qspi_rbdr31. for this case it is recommended to pr ogram the qspi_rbct[r xbrd] bit to 1. the qspi_sfmsr[ahbgnt] bit is assert ed immediately after any running ip command has been finished (qspi_sfmsr[ip_acc] is 0), allowing the master triggeri ng ahb commands to trigger ahb commands as soon as possible wit hout the need to wait for the rx buffer readout to be finished. 35.6.4 command arbitration in case of overlapping commands the arbitration scheme is described in the following paragraphs under the assumption that the priority mechanism described in section 35.6.3, exclusive ac cess to serial flash for ahb commands , is not used:
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-45 preliminary?subject to change without notice ? during the execution of an ip command the r unning ip command can?t be terminated by issuing another ip command or ahb comm and. the qspi_sfmfr[ipief] flag is asserted when the host tries to write into the qspi_icr register. when the host triggers an ahb command (refer to section 35.5.3.3.1, reading serial flash data into the quadspi module , for details) this command is stalled until the currently r unning ip command is finished. ? during the execution of an ahb command the running ahb command can?t be terminated by issuing an ip command. the comm and is ignored and the qspi_sfm fr[ipaef] flag is asserted. refer to section 35.4.4.13, flag register (qspi_sfmfr) , for the description of these flags. when another ahb command is triggered th e address of the memo ry mapped access is considered. if the requested address is curren tly read from the serial flash device the running command is continued. if this is not the case the currently running command is terminated and another ahb command related to the re quested address is executed. refer to section 35.5.3.3.1, reading serial flash data into the quadspi module , for further details. in case of coinciding commands th e ip command is triggered and the ahb command is stalled until the ip command has been finished (qspi_ sfmsr[ip_acc] has been deasserted). the ip commands ignored in case of command coll ision will not result in the assertion of the qspi_sfmfr[tff] flag. 35.6.5 flash device selection regardless of the sfm command (ip or ahb) the access mode is selected by specifying the 32 bit address value for the following sfm command. for ip commands the access mode is selected with the address programmed into the qspi_sfar register. refer to section 35.4.4.4, serial flash address register (qspi_sfar) , for details. for ahb commands the access mode is determined by the memory mapped address which is accessed refer to section 35.4.3, amba bus register memory map , for details. 35.6.6 continuous mode commands in the command set of the serial flash devices there are commands which use a sp ecial access mode of the attached serial flash device. once this mode is enable d in the serial flash devi ce there are only certain sfm commands allowed until this mode is explicitly disabled. refer to the se rial flash device specification for further details. note that it is an error if a sfm command tri ggered does not correspond to the related status bits qspi_sfmsr[cntmdfa/b]. in this case a mode bi t collision is detected associated with the qspi_sfmfr[imef] or the qspi_sfmfr[abmef ] flag, depending from the sfm command triggered. 35.6.7 dma usage for the complete description of the dma module refer to the related chapter. in this paragraph only the details specific to the dma usage rela ted to the quadspi module are given.
pxd20 microcontroller reference manual, rev. 1 35-46 freescale semiconductor preliminary?subject to change without notice 35.6.7.1 dma usage in normal mode 35.6.7.1.1 bandwidth considerations careful consideration of the throughput rate of the entire chain (serial flash -> ahb bus/ip bus -> dma controller) involved in the read data process is essential fo r proper operation. such an alysis must take into account not only the datarate provided by the serial fl ash but also the datarate of the ahb bus and the performance of the dma controller in reading data from the rx buffer. two figures must match for proper ope ration, that means that the data rate provided by the serial flash device must not exceed the average rx buffer readout data ra te. otherwise, the longe r this state persists, a rx buffer overflow will result. ahb bus side: the total number of bus cycles for each dma minor loop completion is added from the following components: ? overhead for each minor loop, gi ven by dma controller: 10 cycles ? overhead due to clock domain crossing: 2 cycles ? number of bus clock cycles requi red for 8 bytes (64 bit read si ze): 2 cycles (rea d/write sequence of dma controller) note that the size of th e minor loop is determined by the size of the qspi_rbct[wmrk ] field, therefore the overhead given above distributes among (qspi_r bct[wmrk] + 1)/2 read accesses of 64 bit each. table 35-36 below gives some exampl es for typical use cases: serial flash device side: the number of serial flash clock cycles can be determined in the following way: ? number of serial flash clock cy cles required to read 4 bytes, corresponding to one rx buffer entry (setup of command and address not considered): 4 cycles for quad m ode instructions in parallel table 35-36. access duration examples - bus clock side qspi_rbct[wmrk] setting # of bytes per dma loop 1 1 ?dma loop? means one minor loop completion whic h is equivalent to one major loop iteration # of bus clock cycles for dma minor loop time duration of dma minor loop for 120 mhz bus clock frequency 0 4 12+2=14 ~117ns 1 8 12+2=14 ~117ns 3 16 12+4=16 ~133ns 7 32 12+8=20 ~167ns 11 48 12 + 12 = 24 ~200 ns
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-47 preliminary?subject to change without notice flash mode, 8 cycles for quad mode instructi ons in individual flash mode, 16/32 cycles for dual/single instructions. ? overhead due to clock domain crossing: 1 cycle table 35-37 below lists the number of cl ock cycles required to read the data from serial flash corresponding to the different setti ng of the qspi_rbct[wmrk] field: from the examples given in table 35-36 and table 35-37 above it can be seen that, dependent from the relationship between the frequencies of the bus clock and the serial flash clock, ther e are settings possible where the serial flash provides the r ead data faster than the ahb bus can read out the rx buffer. in the tables above it is the case of reading the serial flas h in parallel flash mode with quad instructions and qspi_rbct[wmrk] set to 0. in this case the rx buff er is filled over time, to avoid the rx buffer overrun the ip command used to read from fl ash need to specify th e data size small enough. note also that side effects like load from other masters on the ahb bus are not considered. 35.7 byte ordering - endianess the internal byte orientation of the quadspi module is big endian (be). this means that the high order bits of the associated data vectors are a ssociated with low order address positions. the byte ordering is according to the following example: 35.7.1 programming flash data cpu write instructions to the qspi_tbdr register like (1) write qspi_tbdr -> 0x 01 _ 02 _ 03 _ 04 (2) write qspi_tbdr -> 0x 05 _ 06 _ 07 _ 08 table 35-37. access duration examples - serial flash clock side qspi_rbc t[wmrk] setting # of bytes per dma loop 1 1 ?dma loop? means one minor loop completion which is equivalent to one major loop iteration # of sckfx cycles for 48 mhz sckfx time duration of serial flash data readout for 48 mhz sckfx frequency ifm 2 single 2 individual flash mode ifm dual ifm quad pfm 3 quad 3 parallel flash mode ifm single ifm dual ifm quad pfm quad 0 4 33 17 9 5 ~688 ns ~354 ns ~188 ns ~104 ns 1 8 65 33 17 9 ~1.354 ? s ~688 ns ~354 ns ~188 ns 3 16 129 65 33 17 ~2.688 ? s ~1.354 ? s ~688 ns ~354 ns 7 32 257 129 65 33 ~5.354 ? s ~2.688 ? s ~1.354 ? s ~688 ns 11 48 385 193 97 49 ~8.021 ? s ~4.021 ? s ~2.021 ? s ~1.021 ? s
pxd20 microcontroller reference manual, rev. 1 35-48 freescale semiconductor preliminary?subject to change without notice result in the following content of the tx buffer: programming the tx buffer into the external serial fl ash device results in the fo llowing byte order to be sent to the serial flash: 01 ... 02 ... 03 ... 04 ... 05 ... 06 ... 07 ... 08 35.7.2 reading flash data into the rx buffer reading the content from the same a ddress provides the following sequence of bytes, identical to the write case: 01 ... 02 ... 03 ... 04 ... 05 ... 06 ... 07 ... 08 this results in the rx buffer filled with: 35.7.2.1 readout of the rx buffer via qspi_rbdrn the rx buffer content appears at cpu read access via the ip skyblue interface in the following order: (1) read qspi_rbdr0 <- 0x 01 _ 02 _ 03 _ 04 (2) read qspi_rbdr1 <- 0x 05 _ 06 _ 07 _ 08 35.7.2.2 readout of the rx buffer via ardbn the rx buffer content appears at read access on the amba ahb interface at the quadspi module boundary: (1a):32bitaccess:readqspi_ardb0<-0x 01 _ 02 _ 03 _ 04 (2a):32bitaccess:readqspi_ardb1<-0x 05 _ 06 _ 07 _ 08 (1b/2b): 64 bit access: read qspi_ardb0 <- 0x 01 _ 02 _ 03 _ 04 _ 05 _ 06 _ 07 _ 08 table 0-2 example of quadspi tx buffer tx buffer entry content 0 32?h 01 _ 02_ 03 _ 04 1 32?h 05 _ 06_ 07 _ 08 table 35-38. resulting rx buffer content rx buffer entry content 0 32?h 01 _ 02_ 03 _ 04 1 32?h 05 _ 06_ 07 _ 08
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-49 preliminary?subject to change without notice 35.7.3 reading flash data into the ahb buffer reading the content from the same a ddress as it was written to provid es the following sequence of bytes, identical to the write case: 01 ... 02 ... 03 ... 04 ... 05 ... 06 ... 07 ... 08 this results in the ahb buffer filled with: 35.7.3.1 readout of th e ahb buffer via memory mapped read the ahb buffer content appears at read access on the amba ahb interface at the quadspi module boundary: (1a):32bitreadaccess:<-0x 01 _ 02 _ 03 _ 04 (2a): 32 bit read access: <- 0x 05 _ 06 _ 07 _ 08 (1/2): 64 bit read access: <- 0x 01 _ 02 _ 03 _ 04 _ 05 _ 06 _ 07 _ 08 35.8 serial flash devices currently flash memory devices with serial flash bus are developed by several vendors. most standard commands currently have the same in struction code for all vendors, so me commands are however unique for one vendor. the currently supported list of instruction codes and the required instruction code options are provided in this chapter. 35.8.1 supported instructio n codes in winbond devices table 35-39. resulting ahb buffer content ahb buffer entry content 0 64?h 01 _ 02_ 03 _ 04 _ 05 _ 06_ 07 _ 08 table 35-40. winbond instruction codes command instructio n code required input data / parameters output data options qspi_icr[ico] address [qspi_sfar] data [tx buffer] status / data [rx buffer] write enable 06h write disable 04h read status reg1 05h size s7 - s0 read status reg2 35h size s15 - s8 write status reg 01h size s15 - s0 page program 02h size a23 - a0 size * (d7 - d0) 1
pxd20 microcontroller reference manual, rev. 1 35-50 freescale semiconductor preliminary?subject to change without notice the qspi_mcr[ico] field is mapped to the different command options belonging to the complete sfm command which is then sent to the serial flash. th is is shown in detail in the following tables. table 35-41 quad page program 32h size a23 - a0 size * (d7 - d0) 32k block erase 52h a23 - a0 64k block erase d8h a23 - a0 sector erase 20h a23 - a0 chip erase c7h/60h erase suspend 75h erase resume 7ah power down b9h high performance mode a3h read data 03h 2 size a23 - a0 size * (d7 - d0) 1 fast read 0bh size a23 - a0 size * (d7 - d0) fast read dual output 3bh size a23 - a0 size * (d7 - d0) fast read dual i/o bbh m7 - m0, size a23 - a0 size * (d7 - d0) fast read quad output 6bh size a23 - a0 size * (d7 - d0) fast read quad i/o ebh m7 - m0, size a23 - a0 size * (d7 - d0) octal word read quad i/o e3h m7 - m0, size a23 - a0 size * (d7 - d0) (continuos read) mode bit reset ffh (ffh), size release power down/highperf.mode (optional): read device id abh (opt.): read size (opt.): id7 - id0 read manufacturer/device id 90h size a23 - a0 = 0h/1h manid7 - manid0 devid7 - dev0 read unique id 4bh size uniqid63 - uniqid 0 read jedec id 9fh size manid7 - manid0, memid7 - mem0, capid7 - capid0 1 denotes that size-times one byte is transferred on the se rial flash data bus. total number of bytes must be pro- vided in the tx buffer or can be read from the rx buffer 2 according to winbond documentation this command only supports a maximum clock speed of 50 mhz. if the serial flash is operated at a higher clock frequency, the clock frequency for this command must be decreased. refer to section 35.8.5, serial flash clock frequency limitations , for details. table 35-40. winbond instruction codes (continued) command instructio n code required input data / parameters output data options qspi_icr[ico] address [qspi_sfar] data [tx buffer] status / data [rx buffer]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-51 preliminary?subject to change without notice shows the commands usable in all flash access modes, table 35-42 the commands specific to the individual flash modes and table 35-43 the commands specific to the parallel flash mode. all size information is given in number of bytes. note that the mapping reflects the bits which are actually sent to the single serial flash device selected in the individua l flash mode or which are sent to each of the two serial flash devices in the parallel flash mode. table 35-41. ico field on winbond devices - all flash access modes instruction code qspi_icr[ico] 01234567891011121314151617181920212223 01h size 02h size (bytes to be written) 05h size 32h size (bytes to be written) 35h size 03h individual flash access: refer to table 35-42 parallel flash access: refer to table 35-43 0bh 3bh bbh 6bh e3h ebh abh read 1 1 ?read? bit controls if 8 sclk clocks are added to read the device id, equivalent to size = 1 (1byte to read) in any case 24 dummy bits are transmitted after the instruction code to allow reading. 90h size 4bh size (bytes) 9fh size ffh size 2 2 to reset continuous read mode while in dual i/o operations, set size to 1. to reset the continuous read mode while in quad i/o operations set size to 0. table 35-42. ico field on winbond devices - individual flash modes instruction code qspi_icr[ico] 01234567891011121314151617181920212223 03h size (bytes to be read) 0bh size (bytes to be read)
pxd20 microcontroller reference manual, rev. 1 35-52 freescale semiconductor preliminary?subject to change without notice in the parallel flash mode the qs pi_icr[ico] field is no longer relate d to the size read from each individual flash device. instead the size to be read is related to the (virtual) combined flash memory. therefore the amount of data that is read from each single flash device is half th e amount of data specified in the qspi_icr[ico] field. 35.8.2 instruction codes in spansion devices 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh size (bytes to be read) e3h size (bytes to be read) m7 - m0 ebh size (bytes to be read) m7 - m0 table 35-43. ico field on winbond devices - parallel flash mode instruction code qspi_icr[ico] 01234567891011121314151617181920212223 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh size (bytes to be read) e3h size (bytes to be read) m7 - m0 ebh size (bytes to be read) m7 - m0 table 35-44. spansion instruction codes command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer] write enable 06h write disable 04h read status reg 05h size s7 - s0 [8] read config reg 35h size s15 - s8 [8] table 35-42. ico field on winbond devices - individual flash modes instruction code qspi_icr[ico] 01234567891011121314151617181920212223
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-53 preliminary?subject to change without notice write reg 01h size s15 - s0 reset erase and prog fail flag 30h size s15 - s0 page program 02h size a23 - a0 size * (d7 - d0) 2 quad page program 32h size a23 - a0 size * (d7 - d0) 16kbit = 4kb sector erase 20h a23 - a0 32kbit = 8kb block erase 40h a23 - a0 64kb block erase d8h a23 - a0 bulk erase c7h / 60h deep power down b9h read data 03h 3 size a23 - a0 size * (d7 - d0) 1 fast read 0bh size a23 - a0 size * (d7 - d0) dual output read 3bh size a23 - a0 size * (d7 - d0) quad output read 6bh size a23 - a0 size * (d7 - d0) dual i/o high performance read bbh m7 - m0, size a23 - a0 size * (d7 - d0) quad i/o high performance read ebh m7 - m0, size a23 - a0 size * (d7 - d0) read manufacturer/device id 90h size a23 - a0 [24] = 0h / 1h manid7 - manid0, devid7 - dev0 read jedec id 9fh size manid7 - manid0, memid7 - memid0, capid7 - capid0 multi i/o performance mode a3h release power down/highperf.mode optional: read electronic signature abh (opt.): read size (opt.): sig79 - sig0 read status register 07h s7 - s0 (8) autoboot register read 14h s31 - s0 (32) autoboot register write 15h s31 - s0 (32) bank address register read 16h s7 - s0 (8) bank address register write 17h s7 - s0 (8) asp read 2bh s15 - s0 (16) asp program 2fh s15 - s0 (16) program suspend 85h table 35-44. spansion instruction codes (continued) command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer]
pxd20 microcontroller reference manual, rev. 1 35-54 freescale semiconductor preliminary?subject to change without notice the qspi_mcr[ico] field is mapped to the different command options belonging to the complete sfm command which is then sent to the serial flash. th is is shown in detail in the following tables. table 35-45 shows the commands usable in all flash access modes, table 35-46 the commands specific to the individual flash modes, and table 35-47 the commands specific to the parallel flash mode. all size information is given in number of bytes. note that the mapping reflects the bits which are actually sent to the single serial flash device selected in the individua l flash mode or which are sent to each of the two serial flash devices in the parallel flash mode. program resume 8ah write ppb lock register a6h s7 - s0 (8) read ppb lock register a7h s7 - s0 (8) dyb read e0h a31 - a0 s7 - s0 (8) dyb write e1h a31 - a0 s7 - s0 (8) ppb read e2h a31 - a0 s7 - s0 (8) ppb write e3h a31 - a0 s7 - s0 (8) ppb erase e4h password read e7h s63 - s0 (64) password program e8h s63 - s0 (64) password unlock e9h s63 - s0 (64) software reset f0h 1 the address bits are decided by the mode serial flash is work ing. for 32-bit extended address the bits used are a26 - a0, and for default 24-bit address mode the bits used are a23 - a0. 2 denotes that size-times one byte is transferred on the serial flash data bus. total number of bytes must be provided in the tx buffer or can be read from the rx buffer. 3 according to spansion documentation this command only supports a maximum clock speed of 40 mhz. table 35-45. ico field on spansion devices - all flash access modes instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 01h size 02h size (bytes to be written) 05h size 32h size (bytes to be written) 35h size table 35-44. spansion instruction codes (continued) command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-55 preliminary?subject to change without notice 03h individual flash access: refer to ta b l e 3 5 - 4 6 parallel flash access: refer to table 35-47 0bh 3bh bbh 6bh ebh 90h size 9fh size abh read 1 07h size 14h size 15h size 16h size 17h size 2bh size 2fh size a6h size a7h size e0h size e1h size e2h size e3h size e7h size e8h size e9h size 1 ?read? bit controls if up to 80 clocks are added to read the el ectronic signature, equivalent to size = 10 (10bytes to read). i n any case 24 dummy bits are transmitted after the instruction code to allow reading. table 35-45. ico field on spansion devices - all flash access modes (continued) instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
pxd20 microcontroller reference manual, rev. 1 35-56 freescale semiconductor preliminary?subject to change without notice since both serial flash devi ces are treated logical ly as one single device doubled in size the amount of data that must be read from each singl e flash device is half th e amount of data specifie d in the qspi_icr[ico] field. 35.8.3 instruction codes in macronix devices table 35-46. ico field on spansion devices - individual flash mode instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh size (bytes to be read) ebh size (bytes to be read) m7 - m0 table 35-47. ico field on spansion devices - parallel flash mode instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh x size (bytes to be read) ebh size (bytes to be read) m7 - m0 table 35-48. macronix instruction codes command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer] write enable 06h write disable 04h read status reg 05h size s7 - s0 [8] write reg 01h size s15 - s0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-57 preliminary?subject to change without notice read erase and prog fail flag 30h size s15 - s0 page program 02h size a23 - a0 size * (d7 - d0) 2 4kb sector erase 20h a23 - a0 block erase 52h / d8h a23 - a0 chip erase c7h / 60h deep power down b9h read data 03h size a23 - a0 size * (d7 - d0) 1 fast read 0bh size a23 - a0 size * (d7 - d0) dual read mode sequence 3bh size a23 - a0 size * (d7 - d0) quad read mode 6bh size a23 - a0 size * (d7 - d0) dual i/o high performance read bbh m7 - m0, size a23 - a0 size * (d7 - d0) quad i/o high performance read ebh m7 - m0, size a23 - a0 size * (d7 - d0) read electronix manufacturer and device id 90h / dfh / efh size a23 - a0[24] = 0h / 1h manid7 - manid0, memid7 - memid0, capid7 - capid0 read jedec id 9fh size manid7 - manid0, memid7 - memid0, capid7 - capid0 high performance enable mode a3h read electronic signature abh (opt): read size (opt.): sig79 - sig0 read security register 2bh s7 - s0 [8] write security register 2fh s7 - s0 [8] exit 4-byte mode e9h clear sr fail flag 30h single block lock protection 36h a23 - a0 quad page program 38h a23 - a0 size * (d7 - d0) single block unlock protection 39h a23 - a0 read block protection lock status 3ch a23 - a0 read dmc 5ah a23 - a0 size * (d7 - d0) write protection selection 68h enable so to output ry/by 70h table 35-48. macronix instruction codes (continued) command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer]
pxd20 microcontroller reference manual, rev. 1 35-58 freescale semiconductor preliminary?subject to change without notice the qspi_mcr[ico] field is mapped to the different command options belonging to the complete sfm command which is then sent to the serial flash. th is is shown in detail in the following tables. table 35-49 shows the commands usable in all flash access modes, table 35-50 the commands specific to the individual flash modes, and table 35-51 the commands specific to the parallel flash mode. all size information is given in number of bytes. note that the mapping reflects the bits which are actually sent to the single serial flash device selected in the individua l flash mode or which are sent to each of the two serial flash devices in the parallel flash mode. gang block lock 7eh disable so to output ry/by 80h gang block unlock 98h continuous mode adh a23 - a0 s15 - s0 [16] enter secured otp b1h enter 4byte mode b7h exit secured otp c1h 1 the address bits are decided by the mode serial flash is work ing. for 32-bit extended address the bits used are a26 - a0, and for default 24-bit address mode the bits used are a23 - a0. 2 denotes that ?size?- times one byte is transferred on the serial flash data bus. total number of bytes must be provided in the tx buffer or can be read from the rx buffer. table 35-49. ico field on macronix devices - all flash access modes instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 01h size 02h size (bytes to be written) 05h size 32h size (bytes to be written) 35h size 03h individual flash access: refer to ta b l e 3 5 - 5 0 parallel flash access: refer to table 35-51 0bh 3bh bbh 6bh ebh table 35-48. macronix instruction codes (continued) command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-59 preliminary?subject to change without notice since both serial flas h devices are treated logicall y as one single device doubled in size, the amount of data that must be read from each singl e flash device is half th e amount of data specifie d in the qspi_icr[ico] field. 90h size 9fh size abh read 1 07h size 2bh size 2fh size 38h size (bytes to be written) 3ch size 5ah size adh size 1 ?read? bit controls if up to 80 clocks are added to read the el ectronic signature, equivalent to size = 10 (10bytes to read). i n any case 24 dummy bits are transmitted after the instruction code to allow reading. table 35-50. ico field on macronix devices - individual flash mode instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh size (bytes to be read) ebh size (bytes to be read) m7 - m0 table 35-51. ico field on macronix devices - parallel flash mode instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) table 35-49. ico field on macronix devices - all flash access modes instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
pxd20 microcontroller reference manual, rev. 1 35-60 freescale semiconductor preliminary?subject to change without notice 35.8.4 instruction codes in numonyx devices bbh size (bytes to be read) m7 - m0 6bh x size (bytes to be read) ebh size (bytes to be read) m7 - m0 table 35-52. numonyx instruction codes command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer] write enable 06h write disable 04h read status register 05h size s7 - s0 [8] write status register 01h size s15 - s0 page program 02h size a23 - a0 size * (d7 - d0) 2 sub sector erase 20h a23 - a0 block erase d8h a23 - a0 bulk erase c7h read data 03h size a23 - a0 size * (d7 - d0) 1 fast read 0bh size a23 - a0 size * (d7 - d0) dual read mode sequence 3bh size a23 - a0 size * (d7 - d0) quad read mode 6bh size a23 - a0 size * (d7 - d0) dual i/o high performance read bbh m7 - m0, size a23 - a0 size * (d7 - d0) quad i/o high performance read ebh m7 - m0, size a23 - a0 size * (d7 - d0) read jedec id 9fh size manid7 - manid0, memid7 - memid0, capid7 - capid0 exit extended address mode e9h read flag status register 70h s7 - s0 [8] write nv configuration register b1h s15 - s0 [16] table 35-51. ico field on macronix devices - parallel flash mode (continued) instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-61 preliminary?subject to change without notice the qspi_mcr[ico] field is mapped to the different command options belonging to the complete sfm command which is then sent to the serial flash. th is is shown in detail in the following tables. table 35-53 shows the commands usable in all flash access modes, table 35-54 the commands specific to the individual flash modes, and table 35-55 the commands specific to the parallel flash mode. all size read nv configuration register b5h s15 - s0 [16] enter extended address mode b7h quad command page program 12h a23 - a0 size * (d7 - d0) quad input extended fast program 32h a23 - a0 size * (d7 - d0) otp program 42h a23 - a0 size * (d7 - d0) read otp 4bh a23 - a0 size * (d7 - d0) clear status flag register 50h write volatile enhanced configuration 61h s7 - s0 [8] read volatile enhanced configuration 65h s7 - s0 [8] erase suspend 75h erase resume 7ah write volatile configuration register 81h s7 - s0 [8] read volatile configuration register 85h s7 - s0 [8] dual input fast program a2h size * (d7 - d0) multiple i/o read identification afh s23 - s0 [24] quad output fast read bch a31-a0 size * (d7 - d0) write extended address register c5h s7 - s0 [8] read extended address register c8h s7 - s0 [8] dual input extended fash program d2h a23 - a0 size * (d7 - d0) write to lock register e5h a23 - a0 s7 - s0 [8] 1 the address bits are decided by the mode serial flash is work ing. for 32-bit extended address the bits used are a26 - a0, and for default 24-bit address mode the bits used are a23 - a0. 2 denotes that ?size?- times one byte is transferred on the serial flash data bus. total number of bytes must be provided in the tx buffer or can be read from the rx buffer. table 35-52. numonyx instruction codes (continued) command instruction code required input data / parameters output data options qspi_icr[ico] address [qspi_sfad] 1 data [tx buffer] status / data [rx buffer]
pxd20 microcontroller reference manual, rev. 1 35-62 freescale semiconductor preliminary?subject to change without notice information is given in number of bytes. note that the mapping reflects the bits which are actually sent to the single serial flash device selected in the individua l flash mode or which are sent to each of the two serial flash devices in the parallel flash mode. since both serial flas h devices are treated logicall y as one single device doubled in size, the amount of data that must be read from each singl e flash device is half th e amount of data specifie d in the qspi_icr[ico] field. table 35-53. ico field on numonyx devices - all flash access modes instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 01h size 02h size (bytes to be written) 05h size 32h size (bytes to be written) 35h size 03h individual flash access: refer to ta b l e 3 5 - 5 4 parallel flash access: refer to table 35-55 0bh 3bh bbh 6bh ebh 90h size 9fh size abh read 1 1 ?read? bit controls if up to 80 clocks are added to read the el ectronic signature, equivalent to size = 10 (10bytes to read). i n any case 24 dummy bits are transmitted after the instruction code to allow reading. table 35-54. ico field on numonyx devices - individual flash mode instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh size (bytes to be read) ebh size (bytes to be read) m7 - m0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-63 preliminary?subject to change without notice 35.8.5 serial flash clock frequency limitations certain commands of the winbond serial flash devices are limited in the frequenc y applied to the serial flash device on command execution. to allow for hi gher clock speeds for the remaining commands the serial flash device clock can be divided by 2 (hal f speed) when executing such a command limited in frequency by setting the qspi_s mpr[hsena] bit. refer to table 35-40 for the commands affected. 35.9 internal sampling of serial flash input data depending from the actual implemen tation there is a delay between the internal clocking in the quadspi module and the external serial flash device. this means that the incoming data from the serial flash appear this delay later in time at the quadspi sampling logic w.r.t. internal re ference clock. refer to figure 35-19 for an overview of this scheme. figure 35-19. serial flash sampling clock overview table 35-55. ico field on numonyx devices - parallel flash mode instruction code qspi_icr[ico] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh x size (bytes to be read) ebh size (bytes to be read) m7 - m0 quadspi sck - serial flash clock sampling clock gen serial flash data out clock si_io[0:3] - serial flash data 1 2 3 4 5
pxd20 microcontroller reference manual, rev. 1 35-64 freescale semiconductor preliminary?subject to change without notice note the arrival of the serial flash data in the sampling stage of the quadspi module are given in fig figure 35-20 below. note that the amount of the total delay t del,total is very specific to the characteristics of the actual implementation. note also that the serial flash devi ce clock sck is inverted w.r.t. the quadspi internal reference clock. figure 35-20. serial flash sampling clock timing the rising edge of the internal refere nce clock is taken as timing referen ce for the data output of the serial flash. after a time of t del,total the data arrive at the internal sampling stage of the quadspi module. according to figure 35-19 the following parts of the delay chain contribute to t del,total : 1. output delay of the serial flash clock out put of the device containing the quadspi module 2. wire delay of applicat ion/pcb from the device containing th e quadspi module to the external serial flash device 3. clock to data out delay of the external seri al flash device, including input and output delays 4. wire delay of applicati on/pcb from the external serial flash device to the devi ce containing the quadspi module 5. input delay belonging to the data in input the possible points in time for th e sampling of the incoming data ar e denoted as n/1, i/1, n/2 and i/2 above. the sampling point relevant for the internal sampling is configured in the qspi_smpr register, refer to section 35.4.4.6, sampling register (qspi_smpr) , for details. note that the falling edges of the reference clock are not actually use d, instead the inverted clock is us ed for sampling at these positions. internal ref clock serial flash data internal reference for serial flash data sampling t del,total n/1 n/2 i/1 i/2 possible sampling points sck - serial flash clock
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 35-65 preliminary?subject to change without notice table 35-56 below gives an overview of th e available configura tions for the commands running at regular (full) speed: depending from the actual delay a nd the serial flash clock frequency the appropriate sampling point can be chosen. the following remarks should be consid ered when selecting the appropriate setting: ? theoretically there should be 2 se ttings possible to capture the corr ect data since the serial flash output is valid for 1 clock cycle, disregarding rise and fall times a nd timing uncertainties. ? depending from the timing uncertainties it may tu rn out in actual applications that only one possible sample positions remains. this is subject to care ful consideration depending from the actual implementation. ? the delay t del,total is an absolute size to shift the point in time when the serial flash date get valid at the quadspi input. ? for decreasing frequency of the se rial flash clock the distance betw een the edges increases. so for large differences in the frequency the required setting may change. ? for commands running at half of the regular serial flash clock (qspi_smpr[hsena] bit set) the sampling point must be figured separately to allo w for the compensation of the absolute shift in time w.r.t. the sample-relative setting in the qspi_spmpr register. table 35-56. sampling configuration sampling point description delay [fsdly] [hsdly] phase [fsphs] [hsphs] qspi_smpr for full speed setting 1 1 x is not considered here n/1 sampling with non-inverted clock, 1 sample delay 0 0 0x0000000x i/1 sampling with inverted clock, 1 sample delay 0 1 0x0000002x n/2 sampling with non-inverted clock, 2 samples delay 1 0 0x0000004x i/2 sampling with inverted clock, 2 samples delay 1 1 0x0000006x
pxd20 microcontroller reference manual, rev. 1 35-66 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 36-1 preliminary?subject to change without notice chapter 36 real-time clock (rtc/api) 36.1 overview the rtc is a free running counter used for time k eeping applications. the rt c may be configured to generate an interrupt at a predefin ed interval independent of the mode of operation (run mode or low power mode). if in a low power mode when the rtc interval is reached, the rtc will first generate a wakeup and then assert the interrupt request. the rtc also supports an autonomous periodic interrupt (api) function used to generate a period ic wakeup request to exit a low power mode or an interrupt request. 36.2 features features of the rtc include: ? 4 selectable counter clock sources ? 4?16 mhz fxosc (osca) ? 128 khz sirc ? 32 khz sxosc (oscb) ? 16 mhz firc ? optional 512 prescaler and optional 32 prescaler ? 32-bit counter ? supports times up to 1.5 mont hs with 1 ms resolution ? runs in all modes of operation ? reset when disabled by software and by por ? 12-bit compare value to support interrupt intervals of 1s up to greater than 1 hr with 1s resolution ? rtc compare value changeable while counter is running ? rtc status and control re gister are reset only by por ? autonomous periodic interrupt (api) ? 10-bit compare value to support wa keup intervals of 1.0 ms to 1 s ? compare value changeable while counter is running ? configurable interrupt for rtc ma tch, api match, and rtc rollover ? configurable wakeup event for rtc match, api match, and rtc rollover
pxd20 microcontroller reference manual, rev. 1 36-2 freescale semiconductor preliminary?subject to change without notice figure 36-1. rtc/api block diagram 0 12 clksel[0:1] 3 128 khz sirc 16 mhz firc 32 khz == cnten rtccnt rtcval 10:21 rtcf rtcie rtc interrupt offset reg == 22:31 api wakeup + load 22:31 apival apien reset reset 32-bit counter sync sync rtc wakeup apif apiie api sync interrupt rovrf sync 4-16 mhz div512 div32 div32en div512en rtcie rovren osca oscb
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 36-3 preliminary?subject to change without notice figure 36-2. clock gating for rtc clocks 36.3 device-specific information for this device: ? fxosc, sxosc, firc, and sirc clocks are provided as counter clocks for the rtc. default clock on reset is sirc divided by 4. ? the rtc will be reset on dest ructive reset, with the excep tion of software watchdog reset. ? the rtc provides a configurable divider by 512 to be optionally used when firc source is selected. 36.4 modes of operation 36.4.1 functional mode there are two functional modes of operation for th e rtc: normal operation and low power mode. in normal operation, all rtc registers can read or writte n and the input isolation is disabled. the rtc/api 32-bit counter cell c.g. en 128 khz sirc (cnten & clksel== 2???b0 cell en 32 khz oscb (cnten & clksel== 2???b0 cell en 16 mhz firc (cnten & clksel== 2???b1 cell c.g. en 4-16 mhz osca (cnten & clksel== 2???b1 c.g. c.g. 0 12 clksel[0:1] 3 cell c.g. en 1 0 div 512 cell c.g. en 1 0 div 32 div512en div32en cnten
pxd20 microcontroller reference manual, rev. 1 36-4 freescale semiconductor preliminary?subject to change without notice and associated interrupts ar e optionally enabled. in low power mode, the bus in terface is disabled and the input isolation is enabled. the rtc/api is enabled if enabled prior to entry into low power mode. 36.4.2 debug mode on entering into the debug mode th e rtc counter freezes on the last valid count if the rtcc[frzen] is set. on exit from debug mode counter continues from the frozen value. 36.5 memory map and register descriptions 36.5.1 rtc supervisor control register (rtcsupv) the rtcsupv register contains the supv bit which de termines whether other re gisters are accessible in supervisor mode or user mode. note rtcsupv register is accessible only in supervisor mode. 36.5.2 rtc control register (rtcc) the rtcc register contains: table 36-1. memory map address offset register location 0x0 rtc supervisor control register (rtcsupv) on page 36-4 0x4 rtc control register (rtcc) on page 36-4 0x8 rtc status register (rtcs) on page 36-6 0xc rtc counter register (rtccnt) on page 36-7 offset: rtc_base + 0x0000 0 1 2 34567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 r sup v w por 1 0 0 00000000000000000000000000000 figure 36-3. rtc supervisor control register (rtcsupv) table 36-2. rtcsupv regist er bit/field descriptions field description 0 supv rtc supervisor bit 0 all registers are accessible in both user as well as supervisor mode. 1 all other registers are accessi ble in supervisor mode only.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 36-5 preliminary?subject to change without notice ? rtc counter enable ? rtc interrupt enable ? rtc clock source select ? rtc compare value ?api enable ? api interrupt enable ? api compare value offset rtc_base + 0x0004 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cnt en rtci e frz en rovr en rtcval[ w por0 0 0 0 0 00000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r api en apiie clksel div51 2en div3 2en apival w por0 0 0 0 0 00000000000 figure 36-4. rtc control register (rtcc) table 36-3. rtcc field descriptions field description cnten counter enable the cnten bit enables the rtc counter. making cnten bit 1?b0 has the effect of asynchronously resetting (synchronous reset negat ion) all the rtc logic. this allows for the rtc configuration and clock source selection to be updated without causing synchronization issues. 1 counter enabled 0 counter disabled rtcie rtc interrupt enable the rtcie bit enables interr upts requests to the system if rtcf is asserted. 1 rtc interrupts enabled 0 rtc interrupts disabled frzen freeze enable bit the counter freezes on entering the debug mode (as the ipg_debug is detected active) on the last valid count value if the frzen bit is set. af ter coming of the debug mode counter starts from the frozen value. 0 counter does not freeze in debug mode. 1 counter freezes in debug mode.
pxd20 microcontroller reference manual, rev. 1 36-6 freescale semiconductor preliminary?subject to change without notice 36.5.3 rtc status register (rtcs) the rtcs register contains: ? rtc interrupt flag rovren counter roll over interrupt enable the rovren bit enables interrupt requests when the rtc has rolled over from 0xffff_ffff to 0x0000_0000. the rtcie bit must also be set in or der to generate an interrupt from a counter rollover. 1 rtc rollover interrupt enabled 0 rtc rollover interrupt disabled rtcval rtc compare value the rtcval bits are compared to bits 10:21 of the rtc counter and if match sets rtcf. rtcval may only be updated when cnten is 0. note: rtcval should not be set to 0. apien autonomous periodic interrupt enable the apien bit enables the autonomous periodic interrupt function. 1 api enabled 0 api disabled apiie api interrupt enable the apiie bit enables interrupts requests to the system if apif is asserted. 1 api interrupts enabled 0 api interrupts disabled clksel clock select the clksel bits select the clock source for the rtc. clksel may only be updated when cnten is 0. the user should ensure that oscill ator is enabled before selecting it as a clock source for rtc. 00 sxosc_clk_divided 01 sirc_divided 10 irc_fast_divided 11 fxosc_clk_divided div512en divide by 512 enable the div512en bit enables the 512 clock divi der. div512en may only be updated when cnten is 0. 0 divide by 512 is disabled. 1 divide by 512 is enabled. div32en divide by 32 enable the div32en bit enables the 32 clock divider. div32en may only be updated when cnten is 0. 0 divide by 32 is disabled. 1 divide by 32 is enabled. apival api compare value the apival bits are compared to an offset val ue based on bits 22:31 of the rtc counter and if match asserts an interrupt/wakeup request. apival may only be updated when apien is 0 or api function is undefined. note: api functionality starts only when apival is non-zero. the first api interrupt takes two more cycles because of synchroni zation of apival to the rtc clock. after that interrupts are periodic in nature. the minimum supported value of apival is 4. table 36-3. rtcc field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 36-7 preliminary?subject to change without notice ? api interrupt flag ? rollovr flag 36.5.4 rtc counter register (rtccnt) the rtccnt register contains the current value of the rtc counter. offset rtc_base + 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 rtc f 00 0000000 0 000 w w1c por000 0 000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 api f 0 0 rovr f 000 0 000000 w w1c w1c por000 0 000000000000 figure 36-5. rtc status register (rtcs) table 36-4. rtcs field descriptions field description rtcf rtc interrupt flag the rtcf bit indicates that the rtc counter has reached the counter value matching rtcval. rtcf is cleared by writing a 1 to rtcf. writing a 0 to rtcf has no effect. 1 rtc interrupt 0 no rtc interrupt note: rtcf is not set if rtcval is 12'b0. apif api interrupt flag the apif bit indicates that the rtc counter has r eached the counter value matching api offset value. apif is cleared by writing a 1 to apif. writing a 0 to apif has no effect. 1 api interrupt 0 no api interrupt note: the periodic interrupt comes after apival[0:9] + 1?b1 rtc counts rovrf counter roll over interrupt flag the rovrf bit indicates that the rtc has rolled over from 0xffff_ffff to 0x0000_0000. rovrf is cleared by writing a 1 to rovrf. 1 rtc has rolled over. 0 rtc has not rolled over.
pxd20 microcontroller reference manual, rev. 1 36-8 freescale semiconductor preliminary?subject to change without notice 36.6 rtc functional description the rtc consists of a 32-bit free running counter enabled with the rtcc[cnten] bit (cnten when negated asynchronously resets the c ounter and synchronously enables the counter when enabled). the value of the counter may be read via the rtccnt regi ster. note that due to the clock synchronization, the rtccnt value may actually represen t a previous counter value. the di fference between the counter and the read value depends on ratio of counter clock and ipg_c lk. maximum possible di fference between the two is 6 count values. the clock source to the counter is selected with the rtcc[clksel] fi eld, which gives four options for clocking the rtc/api. the four cl ock sources are assumed to be two 16 mhz sour ces, one 32 khz source and one 128 khz source. the output of the clock m ux can be optionally divi ded by combination of 512 and 32 to give a 1 ms rtc/api count period for different clock sources . note that the rtcc[cnten] bit must be disabled when the rt c/api clock source is switched. when the counter value for counte r bits 10:21 match the 12-bit value in the rtcc[rtcval] field, then the rtcs[rtcf] interrupt flag bit is set (after proper clock synchronization). if the rtcc[rtcie] interrupt enable bit is set, then the rtc interrupt request is generate d. the rtc supports interrupt requests in the range of 1s to 40 96s (> 1 hr.) with a 1s resolution. the rtcc[rtcval ] field may only be updated when the rtcc[cnten] bit is cleared to disable the c ounter. if there is a match while in low power mode then the rtc will first generate a wakeup request to force a wakeup to r un mode, then the rtcf flag will be set. a rollover interrupt can be generated when the rtc transitions from a count of 0xffff_ffff to 0x0000_0000. the rollover flag is enabled by setting the rtcc[rovren] bit. an interrupt request is generated for an rtc counter rollover when both the rtcc[rovren] and rt cc[rtcie] bits are set. all the flags and counter values ar e synchronized with ipg_clk. it is assumed that ipg_clk frequency is always more than or equal to the rtc_clk used to run the counter. offset: rtc_base + 0x000c 012345678910111213141516171819202122232425262728293031 r rtccnt[0:31] w por00000000000000000000000000000000 figure 36-6. rtc counter register (rtccnt) table 36-5. rtccnt field descriptions field description rtccnt rtc counter value due to the clock synchronization, the rtccnt val ue may actually represent a previous counter value.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 36-9 preliminary?subject to change without notice 36.7 api functional description setting rtcc[apien] bit enables the autonomous in terrupt function. the 10-bit rtcc[apival] field selects the time interval for trigge ring an interrupt and/or wakeup ev ent. since the rtc is a free running counter, the apival is added to the current count to calculate an offset. when the counter reaches (offset count + 1), a interrupt and/or wakeup request is generated. then the offset value is recalculated and again retriggers a new request when the new value is reached. apival may onl y be updated when apien is disabled. when a compare is reached, the rtcs[api f] interrupt flag bit is set (after proper clock synchronization). if the rt cc[apiie] interrupt enable bit is set, then the api interrupt request is generated. if there is a match while in low power mode, then the api wi ll first generate a wakeup request to force a wakeup into normal operation, then the apif flag will be set.
pxd20 microcontroller reference manual, rev. 1 36-10 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-11 preliminary?subject to change without notice chapter 37 reset generation module (mc_rgm) 37.1 introduction 37.1.1 overview the reset generation module (mc_rgm) centralizes the different rese t sources and manages the reset sequence of the device. it provides a register interface and the reset sequencer . the different registers are available to monitor and control the device reset seque nce. the reset sequencer is a state machine which controls the different phases (phase0, phase1, ph ase2, phase3, and idle) of the reset sequence and control the reset signals generated in the system. figure 37-1 depicts the mc_rgm block diagram.
pxd20 microcontroller reference manual, rev. 1 37-12 freescale semiconductor preliminary?subject to change without notice figure 37-1. mc_rgmblock diagram 37.1.2 features the mc_rgm contains the functiona lity for the following features: ? ?destructive? resets management ? ?functional? resets management ? signalling of reset events after each reset sequence (reset status flags) ? conversion of reset events to safe mode or inte rrupt request events (for further mode details, please see chapter 29, mode entry module (mc_me) ) pad[22:21] reset registers platform interface cpu mc_rgm mc_me power-on 1.2v low-voltage detected (power domain #0) 1.2v low-voltage detected (power domain #1) software watchdog timer 2.7v low-voltage detected jtag initiated reset cpu reset software reset checkstop reset fmpll0 fail fxosc frequency lower than reference cmu0 clock frequency higher/lower than reference 4.5v low-voltage detected code or data flash fatal error functional reset filter boot mode capture destructive reset filter reset state machine sscm peripherals mc_cgm
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-13 preliminary?subject to change without notice ? short reset sequence configuration ? bidirectional reset be havior configuration ? selection of alternate boot via th e backup ram on standby mode exit (for further mode details, please see chapter 29, mode entry module (mc_me) ) ? boot mode capture on reset deassertion 37.1.3 modes of operation the different reset sources are organized into two families: ?destructive? and ?functional?. ? a ?destructive? reset source is associated with an event related to a critical?usually hardware?error or dysfunction. when a ?destructive? reset event occu rs, the full reset sequence is applied to the device starting from phase0. this resets the full device ensuring a safe start-up state for both digital and analog m odules. ?destructive? resets are ? power-on reset ? 1.2v low-voltage detected (power domain #0) ? 1.2v low-voltage detected (power domain #1) ? software watchdog timer ? 2.7v low-voltage detected ? a ?functional? reset source is associated with an event related to a less-critical - usually non-hardware - error or dysfunction. when a ?func tional? reset event occurs, a partial reset sequence is applied to th e device starting from phas e1. in this case, most digital modules are reset normally, while analog modules or specific di gital modules? (e.g. debug modules, flash modules) state is preserved. ?functional? resets are ? external reset ? jtag initiated reset ?cpu reset ? software reset ? checkstop reset ? fmpll0 fail ? fxosc frequency lower than reference ? cmu0 clock frequency higher/lower than reference ? 4.5v low-voltage detected ? fmpll1 fail fatal error when a reset is triggered, the mc_rgm state mach ine is activated and proceeds through the different phases (i.e. phase n states). each phase is associated with a particular device reset being provided to the system. a phase is completed when all corresponding phase completion ga tes from either the system or internal to the mc_rgm are acknowledged. the device re set associated with the phase is then released, and the state machine proceeds to the next phase up to entering the idle phase. du ring this entire process, the mc_me state machine is held in reset mode. only at the end of the reset sequence, when the idle phase is reached, does the mc_me enter the drun mode.
pxd20 microcontroller reference manual, rev. 1 37-14 freescale semiconductor preliminary?subject to change without notice alternatively, it is possibl e for software to configure some reset source events to be converted from a reset to either a safe mode request issued to the mc _me or to an interrupt issued to the cpu (see section 37.3.1.4, destructive event reset disable register (rgm_derd) , and section 37.3.1.6, destructive event alternate request register (rgm_dear) , for ?destructive? resets and section 37.3.1.3, functional event rese t disable register (rgm_ferd) , and section 37.3.1.5, functional event alternate re quest register (rgm_fear) , for ?functional? resets). 37.2 external signal description the mc_rgm interfaces to the bidirectional re set pin reset and the boot mode pins pad[22:21]. 37.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 37-1. mc_rgm register description address name description location 0xc3fe_4000 rgm_fes functional event status on page 37-17 0xc3fe_4002 rgm_des destructive event status on page 37-18 0xc3fe_4004 rgm_ferd functional event reset disable on page 37-19 0xc3fe_4006 rgm_derd destructive event reset disable on page 37-21 0xc3fe_4010 rgm_fear functional event alternate request on page 37-22 0xc3fe_4012 rgm_dear destructive event alternate request on page 37-23 0xc3fe_4018 rgm_fess functional event short sequence on page 37-24 0xc3fe_401a rgm_stdby standby reset sequence on page 37-25 0xc3fe_401c rgm_fbre functional bidirectional reset enable on page 37-26
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-15 preliminary?subject to change without notice table 37-2. mc_rgm memory map address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_4000 rgm_fes / rgm_des r f_exr f_fmpll1 f_lvd45 f_cmu0_fhl f_cmu0_olr f_fmpll0 f_soft f_core f_jtag ww1c r f_por f_lvd27 f_swt f_lvd12_pd1 f_lvd12_pd0 ww1c 0xc3fe_4004 rgm_ferd / rgm_derd r d_exr d_fmpll1 d_lvd45 d_cmu0_fhl d_cmu0_olr d_fmpll0 d_soft d_core d_jtag w r0 d_lvd27 d_swt d_lvd12_pd1 d_lvd12_pd0 w 0xc3fe_4008 ? 0xc3fe_400c reserved 0xc3fe_4010 rgm_fear / rgm_dear r ar_exr ar_fmpll1 ar_lvd45 ar_cmu0_fhl ar_cmu0_olr ar_fmpll0 ar_soft ar_core ar_jtag w r0 ar_lvd27 ar_swt ar_lvd12_pd1 ar_lvd12_pd0 w 0xc3fe_4014 reserved w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
pxd20 microcontroller reference manual, rev. 1 37-16 freescale semiconductor preliminary?subject to change without notice 37.3.1 register descriptions unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for ex ample, the rgm_stdby regi ster may be accessed as a word at address 0xc3fe_4018, as a half-word at address 0xc3fe_401a, or as a byte at address 0xc3fe_401b. 0xc3fe_4018 rgm_fess / rgm_stdby r ss_exr ss_flash ss_lvd45 ss_cmu0_fhl ss_cmu0_olr ss_fmpll0 ss_soft ss_core ss_jtag w r00000000 boot_from_bkp_ram 0000000 w 0xc3fe_401c rgm_fbre r be_exr be_lvd45 be_cmu0_fhl be_cmu0_olr be_fmpll0 be_soft be_core be_jtag w 0xc3fe_4020 ? 0xc3fe_7ffc reserved table 37-2. mc_rgm memory map (continued) address name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-17 preliminary?subject to change without notice 37.3.1.1 functional event status register (rgm_fes) this register contains the st atus of the last asserted f unctional reset sources . it can be accessed in read/write on either supervisor mode or test mode . register bits are cleared on write ?1?. address 0xc3fe_4000 access: supervisor read/write 0123456789101112131415 r f_exr f_fmpll1 f_lvd45 f_cmu0_fhl f_cmu0_olr f_fmpll0 0 f_soft f_core f_jtag ww1c por0000000000000000 figure 37-2. functional event status register (rgm_fes) table 37-3. functional event status register (rgm_fes) field descriptions field description f_exr flag for external reset 0 no external reset event has occurred since either the last clear or the last de structive reset assertion 1 an external reset event has occurred f_flash flag for code or data flash fatal error 0 no code or data flash fatal error event has occurred si nce either the last clear or the last destructive reset assertion 1 a code or data flash fatal error event has occurred f_lvd45 flag for 4.5v low-voltage detected 0 no 4.5v low-voltage detected event has occurred since ei ther the last clear or th e last destructive reset assertion 1 a 4.5v low-voltage detected event has occurred f_cmu0_fh l flag for cmu0 clock frequency higher/lower than reference 0 no cmu0 clock frequency higher/lower than reference ev ent has occurred since either the last clear or the last destructive reset assertion 1 a cmu0 clock frequency higher/lower than reference event has occurred f_cmu0_ol r flag for fxosc frequency lower than reference 0 no fxosc frequency lower than reference event has o ccurred since either the last clear or the last destructive reset assertion 1 a fxosc frequency lower than reference event has occurred f_fmpll0 flag for fmpll0 fail 0 no fmpll0 fail event has occurred since either the last clear or the last destructive reset assertion 1 a fmpll0 fail event has occurred f_soft flag for software reset 0 no software reset event has occurred since either the last clear or the last destructive reset assertion 1 a software reset event has occurred w1c w1c w1c w1c w1c w1c w1c w1c
pxd20 microcontroller reference manual, rev. 1 37-18 freescale semiconductor preliminary?subject to change without notice 37.3.1.2 destructive event st atus register (rgm_des) this register contains the status of the last asserted destructive re set sources. it can be accessed in read/write on either supervisor mode or test mode. register bits ar e cleared on write ?1?. f_core flag for cpu reset 0 no cpu reset event has occurred since either the la st clear or the last de structive reset assertion 1 a cpu reset event has occurred f_jtag flag for jtag initiated reset 0 no jtag initiated reset event has occurred since either the last clear or the last destructive reset assertion 1 a jtag initiated reset event has occurred address 0xc3fe_4002 access: supervisor read/write 0123456789101112131415 r f_por f_lvd27 f_swt f_lvd12_pd1 f_lvd12_pd0 ww1c por1000000000000000 figure 37-3. destructive event status register (rgm_des) table 37-4. destructive event status register (rgm_des) field descriptions field description f_por flag for power-on reset 0 no power-on event has occurred since the last clear (due to either a software clear or a low-voltage detection) 1 a power-on event has occurred f_lvd27 flag for 2.7v low-voltage detected 0 no 2.7v low-voltage detected event has occurred since either the last clear or the last power-on reset assertion 1 a 2.7v low-voltage detected event has occurred f_swt flag for software watchdog timer 0 no software watchdog timer event has occurred since eit her the last clear or the last power-on reset assertion 1 a software watchdog timer event has occurred f_lvd12_p d1 flag for 1.2v low-voltage de tected (power domain #1) 0 no 1.2v low-voltage detected (power domain #1) event has occurred since either the last clear or the last power-on reset assertion 1 a 1.2v low-voltage detected (power domain #1) event has occurred f_lvd12_p d0 flag for 1.2v low-voltage de tected (power domain #0) 0 no 1.2v low-voltage detected (power domain #0) event has occurred since either the last clear or the last power-on reset assertion 1 a 1.2v low-voltage detected (power domain #0) event has occurred table 37-3. functional event status regist er (rgm_fes) field descriptions (continued) field description w1c w1c w1c w1c
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-19 preliminary?subject to change without notice note the f_por flag is automatically clear ed on a 1.2v low-voltage detected (power domain #0 or #1) or a 2.7v low-voltage detected (vreg). this means that if the power-up sequence is not monotonic (i.e the voltage rises and then drops enough to tr igger a low-voltage detection), the f_por flag may not be set but instead the f_lvd12_pd0, f_lvd12_pd1, or f_lvd27_vreg flag is set on exiting the reset sequence. therefore, if the f_por, f_lvd12_pd0, f_lvd12_pd1, or f_lvd27_vreg flags are set on reset exit, software should interpret the reset cause as power-on. note in contrast to all other reset sources, the 1.2v low- voltage detected (power domain #0) event is captured on its deas sertion. therefore, the status bit f_lvd12_pd0 is also asserted on the reset?s deassertion. in case an alternate event is selecte d, the safe mode or interr upt request are similarly asserted on the reset?s deassertion. 37.3.1.3 functional event reset disable register (rgm_ferd) this register provides dedicated bits to disable functional reset source s.when a functional reset source is disabled, the associated functional ev ent will trigger either a safe mode request or an interrupt request (see section 37.3.1.5, functional event altern ate request register (rgm_fear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. each byte can be written only on ce after power-on reset. address 0xc3fe_4004 access: supervisor read/write 0123456789101112131415 r d_exr d_fmpll1 d_lvd45 d_cmu0_fhl d_cmu0_olr d_fmpll0 0 d_soft d_core d_jtag w por0000000000000000 figure 37-4. functional event reset disable register (rgm_ferd)
pxd20 microcontroller reference manual, rev. 1 37-20 freescale semiconductor preliminary?subject to change without notice table 37-5. functional event reset disable register (rgm_ferd) field descriptions field description d_exr disable external reset 0 an external reset event triggers a reset sequence 1 an external reset event generates a safe mode request d_fmpll1 disable fmpll1 fa il fatal error 0 an fmpll1 fail fatal error event triggers a reset sequence 1 an fmpll1 fail fatal error event generates either a safe mode or an interrupt request depending on the value of rgm_fear[ar_fmpll1] d_lvd45 disable 4.5v low-voltage detected 0 a 4.5v low-voltage detected event triggers a reset sequence 1 a 4.5v low-voltage detected event generates eit her a safe mode or an interrupt request depending on the value of rgm_fear.ar_lvd45 d_cmu0_f hl disable cmu0 clock frequency higher/lower than reference 0 a cmu0 clock frequency higher/lower than reference event triggers a reset sequence 1 a cmu0 clock frequency higher/lower than reference event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu0_fhl d_cmu0_o lr disable fxosc frequency lower than reference 0 a fxosc frequency lower than reference event triggers a reset sequence 1 a fxosc frequency lower than reference event gener ates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu0_olr d_fmpll0 disable fmpll0 fail 0 a fmpll0 fail event triggers a reset sequence 1 a fmpll0 fail event generates either a safe m ode or an interrupt request depending on the value of rgm_fear.ar_fmpll0 d_soft disable software reset 0 a software reset event triggers a reset sequence 1 a software reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_soft d_core disable cpu reset 0 a cpu reset event triggers a reset sequence 1 a cpu reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_core d_jtag disable jtag initiated reset 0 a jtag initiated reset event triggers a reset sequence 1 a jtag initiated reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_jtag
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-21 preliminary?subject to change without notice 37.3.1.4 destructive event reset disable register (rgm_derd) this register provides dedicated bits to disable particular destructiv e reset sources. when a destructive reset source is disabled, the associated destructive ev ent will trigger either a safe mode request or an interrupt request (see section 37.3.1.6, destructive event altern ate request regi ster (rgm_dear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in r ead only in user mode. each byte can be writte n only once after power-on reset. address 0xc3fe_4006 access: supervisor read 0123456789101112131415 r 0 d_lvd27 d_swt d_lvd12_pd1 d_lvd12_pd0 w por0000000000000000 figure 37-5. destructive event reset disable register (rgm_derd) table 37-6. destructive event reset disable register (rgm_derd) field descriptions field description d_lvd27 disable 2.7v low-voltage detected 0 a 2.7v low-voltage detected event triggers a reset sequence 1 a 2.7v low-voltage detected event generates eit her a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd27 d_swt disable software watchdog timer 0 a software watchdog timer event triggers a reset sequence 1 a software watchdog timer event generates either a safe mode or an interrupt request depending on the value of rgm_dear.ep d_lvd12_p d1 disable 1.2v low-voltage detected (power domain #1) 0 a 1.2v low-voltage detected (power domain #1) event triggers a reset sequence 1 a 1.2v low-voltage detec ted (power domain #1) event generates ei ther a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd12_pd1 d_lvd12_p d0 disable 1.2v low-voltage detected (power domain #0) 0 a 1.2v low-voltage detected (power domain #0) event triggers a reset sequence 1 a 1.2v low-voltage detec ted (power domain #0) event generates ei ther a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd12_pd0
pxd20 microcontroller reference manual, rev. 1 37-22 freescale semiconductor preliminary?subject to change without notice 37.3.1.5 functional event alternat e request register (rgm_fear) this register defines an alternat e request to be generated when a reset on a functional event has been disabled. the alternate reque st can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read /write in either supervisor mode or test mode. it can be accessed in read only in user mode. address 0xc3fe_4010 access: supervisor read/write 0123456789101112131415 r ar_exr ar_fmpll1 ar_lvd45 ar_cmu0_fhl ar_cmu0_olr ar_fmpll0 ar_soft ar_core ar_jtag w por0000000000000000 figure 37-6. functional event altern ate request register (rgm_fear) table 37-7. functional event alternate request register (rgm_fear) field descriptions field description ar_exr alternate request for external reset 0 generate a safe mode request on an external reset event if the reset is disabled 1 generate an interrupt request on an external reset event if the reset is disabled ar_fmpll1 alternate request for fm pll1 fail fatal error 0 generate a safe mode request on an fmpll1 fail fatal error event if the reset is disabled 1 generate an interrupt request on an fmpll1 fail fatal error event if the reset is disabled ar_lvd45 alternate request for 4.5v low-voltage detected 0 generate a safe mode request on a 4.5v low-volt age detected event if the reset is disabled 1 generate an interrupt request on a 4.5v low-voltage detected event if the reset is disabled ar_cmu0_f hl alternate request for cmu0 clock frequency higher/lower than reference 0 generate a safe mode request on a cmu0 clock frequency higher/lower than reference event if the reset is disabled 1 generate an interrupt request on a cmu0 clock frequen cy higher/lower than reference event if the reset is disabled ar_cmu0_ olr alternate request for fxosc frequency lower than reference 0 generate a safe mode request on a fxosc frequency lower than reference event if the reset is disabled 1 generate an interrupt request on a fxosc frequency lower than reference event if the reset is disabled note: for the case when rgm_ferd[d_cmu0_olr] = 1 & rgm_fear[ar_cmu0_olr] = 1 a rgm interrupt will not be generated for a fxosc failure when the system clock = fxosc as there will be no system clock to execute the interrupt service routin e. however, the interrupt service routine will be executed if the fxosc recovers at some point. the recommended use case for this feature is when the system clock = firc or fmpll. ar_fmpll0 alternate request for fmpll0 fail 0 generate a safe mode request on a fmpll0 fail event if the reset is disabled 1 generate an interrupt request on a fmpll0 fail event if the reset is disabled ar_soft alternate request for software reset 0 generate a safe mode request on a software reset event if the reset is disabled 1 generate an interrupt request on a software reset event if the reset is disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-23 preliminary?subject to change without notice 37.3.1.6 destructive ev ent alternate request register (rgm_dear) this register defines an alternate request to be generated when a re set on a destructive event has been disabled. the alternate reque st can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read /write in either supervisor mode or test mode. it can be accessed in read only in user mode. ar_core alternate request for cpu reset 0 generate a safe mode request on a cpu reset event if the reset is disabled 1 generate an interrupt request on a cpu reset event if the reset is disabled ar_jtag alternate request for jtag initiated reset 0 generate a safe mode request on a jtag initiated reset event if the reset is disabled 1 generate an interrupt request on a jtag initiated reset event if the reset is disabled 0123456789101112131415 r 0 ar_lvd27 ar_swt ar_lvd12_pd1 ar_lvd12_pd0 w por0000000000000000 figure 37-7. destructive event alternate request register (rgm_dear) table 37-8. destructive event alternate request register (rgm_dear) field descriptions field description ar_lvd27 alternate request for 2.7v low-voltage detected 0 generate a safe mode request on a 2.7v low-volt age detected event if the reset is disabled 1 generate an interrupt request on a 2.7v low-voltage detected event if the reset is disabled ar_swt alternate request for so ftware watchdog timer 0 generate a safe mode request on a software watchdog timer event if the reset is disabled 1 generate an interrupt request on a software watchdog timer event if the reset is disabled ar_lvd12_ pd1 alternate request for 1.2v low-voltage detected (power domain #1) 0 generate a safe mode request on a 1.2v low-voltage detected (power domain #1) event if the reset is disabled 1 generate an interrupt request on a 1.2v low-voltage de tected (power domain #1) event if the reset is disabled ar_lvd12_ pd0 alternate request for 1.2v low-voltage detected (power domain #0) 0 generate a safe mode request on a 1.2v low-voltage detected (power domain #0) event if the reset is disabled 1 generate an interrupt request on a 1.2v low-voltage de tected (power domain #0) event if the reset is disabled table 37-7. functional event alternate request re gister (rgm_fear) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 37-24 freescale semiconductor preliminary?subject to change without notice 37.3.1.7 functional event short sequence register (rgm_fess) this register define s which reset sequence will be done when a functional reset sequen ce is triggered.the functional reset sequence can either start from phase1 or from phase3, skipping phase1 and phase2. note this could be useful for fast reset seque nce, for example to skip flash reset. however, short sequence resets should not be used when in a mode with flash configured to power-down state. in this case a full phase1 reset is required in order to power up the flas h - therefore fess should be set to 0x0. note if any functional event is defined to perform a short reset sequence then it will not also assert the exte rnal reset pin even if that option is selected in the rgm_fbre register. short reset sequen ces can be useful to allow a fast reset sequence, for example to skip flash reset. it can be accessed in read/write in ei ther supervisor mode or test mode. it can be accessed in read in user mode. address 0xc3fe_4018 access: supervisor read/write 0123456789101112131415 r ss_exr ss_flash ss_lvd45 ss_cmu0_fhl ss_cmu0_olr ss_fmpll0 0 ss_soft ss_core ss_jtag w por0000000000000000 figure 37-8. functi onal event short sequence register (rgm_fess) table 37-9. functional event short sequence register (rgm_fess) field descriptions field description ss_exr short sequence for external reset 0 the reset sequence triggered by an external reset event will start from phase1 1 the reset sequence triggered by an external reset event will start from phase3, skipping phase1 and phase2 ss_flash short sequence for code or data flash fatal error 0 the reset sequence triggered by a code or data flash fatal error event will start from phase1 1 the reset sequence triggered by a code or data flash fatal error event will start from phase3, skipping phase1 and phase2 ss_lvd45 short sequence for 4.5v low-voltage detected 0 the reset sequence triggered by a 4.5v low-voltage detected event will start from phase1 1 the reset sequence triggered by a 4.5v low-voltage detected event will start from phase3, skipping phase1 and phase2
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-25 preliminary?subject to change without notice 37.3.1.8 standby reset sequence register (rgm_stdby) this register defines reset sequence to be applied on standby mode exit. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. ss_cmu0_f hl short sequence for cmu0 clock frequency higher/lower than reference 0 the reset sequence triggered by a cmu0 clock freque ncy higher/lower than reference event will start from phase1 1 the reset sequence triggered by a cmu0 clock freque ncy higher/lower than reference event will start from phase3, skipping phase1 and phase2 ss_cmu0_ olr short sequence for fxosc frequency lower than reference 0 the reset sequence triggered by a fxosc frequency lower than reference event will start from phase1 1 the reset sequence triggered by a fxosc frequency lower than reference event will start from phase3, skipping phase1 and phase2 ss_fmpll0 short sequence for fmpll0 fail 0 the reset sequence triggered by a fmpll0 fail event will start from phase1 1 the reset sequence triggered by a fmpll0 fail event will start from phase3, skipping phase1 and phase2 ss_soft short sequence for software reset 0 the reset sequence triggered by a software reset event will start from phase1 1 the reset sequence triggered by a software reset event will start from phase3, skipping phase1 and phase2 ss_core short sequence for cpu reset 0 the reset sequence triggered by a cpu reset event will start from phase1 1 the reset sequence triggered by a cpu reset event will start from phase3, skipping phase1 and phase2 ss_jtag short sequence for jtag initiated reset 0 the reset sequence triggered by a jtag initiated reset event will start from phase1 1 the reset sequence triggered by a jtag initiat ed reset event will start from phase3, skipping phase1 and phase2 address 0xc3fe_401a access: supervisor read/write 0123456789101112131415 r 00000000 boot_from_bkp_ram 0000000 w reset0000000000000000 figure 37-9. standby reset sequence register (rgm_stdby) table 37-9. functional event short sequence regi ster (rgm_fess) field de scriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 37-26 freescale semiconductor preliminary?subject to change without notice note this register is reset on any enabled ?destructive? or ?functional? reset event. 37.3.1.9 functional bidirectional r eset enable register (rgm_fbre) this register enables the ge neration of an external rese t on functional reset. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read in user mode. table 37-10. standby reset sequence regi ster (rgm_stdby) field descriptions field description boot_ from_ bkp_ram boot from backup ram indicator ? this bit indicates whether the system will boot from backup ram or flash out of standby exit. 0 boot from flash on standby exit 1 boot from backup ram on standby exit address 0xc3fe_401c access: supervisor read/write 0123456789101112131415 r be_exr 0 be_lvd45 be_cmu0_fhl be_cmu0_olr be_fmpll0 0 be_soft be_core be_jtag w por0000000000000000 figure 37-10. functional bidirectional reset enable register (rgm_fbre) table 37-11. functional bidirectional reset en able register (rgm_fbre) field descriptions field description be_exr bidirectional reset enable for external reset 0 reset is asserted on an external re set event if the reset is enabled 1 reset is not asserted on an external reset event be_lvd45 bidirectional reset enable fo r 4.5v low-voltage detected 0 reset is asserted on a 4.5v low-volta ge detected event if the reset is enabled 1 reset is not asserted on a 4.5v low-voltage detected event be_cmu0_f hl bidirectional reset enable for cmu0 cloc k frequency higher/lower than reference 0 reset is asserted on a cmu0 clock frequency higher/l ower than reference event if the reset is enabled 1 reset is not asserted on a cmu0 clock frequency higher/lower than reference event be_cmu0_ olr bidirectional reset enable for fxosc frequency lower than reference 0 reset is asserted on a fxosc frequency lower than reference event if the reset is enabled 1 reset is not asserted on a fxosc frequency lower than reference event be_fmpll0 bidirectional reset enable for fmpll0 fail 0 reset is asserted on a fmpll0 fa il event if the reset is enabled 1 reset is not asserted on a fmpll0 fail event
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-27 preliminary?subject to change without notice 37.4 functional description 37.4.1 reset state machine the main role of mc_rgm is the ge neration of the reset se quence which ensures that the correct parts of the device are reset based on the reset source event. this is summarized in table 37-12 . note jtag logic has its own independent rese t control and is not controlled by the mc_rgm in any way. the reset sequence is comprised of five phases managed by a state machin e, which ensures that all phases are correctly processed thr ough waiting for a minimum dur ation and until al l processes that need to occur during that phase have been completed before proceeding to the next phase. the state machine used to produce the reset sequence is shown in figure 37-11 . be_core bidirectional reset enable for cpu reset 0 reset is asserted on a cpu reset event if the re set is enabled 1 reset is not asserted on a cpu reset event be_jtag bidirectional reset enable for jtag initiated reset 0 reset is asserted on a jtag initiated reset event if the reset is enabled 1 reset is not asserted on a jtag initiated reset event table 37-12. mc_rgm reset implications source what gets reset external reset assertion boot mode capture power-on reset all yes yes ?destructive? resets all except mc_rgm and rtc/api yes yes external reset all (unless an alternate request is enabled) except mc_rgm, rtc/api and nexus/tap yes yes ?functional? resets all (unless an alternate request is enabled) except mc_rgm, rtc/api and nexus/tap programmable 1 1 the assertion of the external reset is controlled via the rgm_fbre register programmable 2 2 the boot mode is captured if the external reset is asserted shortened ?functional? resets 3 3 the short sequence is enabled via the rgm_fess register all except mc_rgm, rtc/api, nexus/tap, cflash, and sscm programmable 1 programmable 2 table 37-11. functional bidirectional reset enable register (rgm_fbre) field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 37-28 freescale semiconductor preliminary?subject to change without notice x figure 37-11. mc_rgm state machine 37.4.1.1 phase0 phase this phase is entered immediately from any phase on a power-on or enab led ?destructive? reset event. the reset state machine exits phase0 and enters phase1 on verification of the following: phase0 phase1 phase2 phase3 idle duration ? 3 fast internal rc oscillator (16mhz) clock cycles firc stable, vreg voltage okay done duration ? 350 fast internal rc oscillator (16mhz) clock cycles duration ???? fast internal rc oscill ator (16mhz) clock cycles code and data flash initialization done duration ?? 40 ? fast internal rc oscillator (16mhz) clock cycles code and data flash initialization done fast internal rc oscillator (16mhz) clock is running power-up has completed power-on or enabled ?destructive? reset enabled non-shortened external or ?functional? reset 1 enabled shortened external or ?functional? reset code and data flash initialization done reset released
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-29 preliminary?subject to change without notice ? power-up has completed ? fast internal rc oscillator (16mhz) clock is running ? all enabled ?destructive? re sets have been processed ? all processes that need to be done in phase0 are completed ? firc stable, vreg voltage okay ? a minimum of 3 fast internal rc oscillator (16mhz) clock cycles have elapsed since power-up completion and the last enabled ?destructive? reset event 37.4.1.2 phase1 phase this phase is entered either on exit from phase0 or immediately from phase2, phase3, or idle on a non-masked external or ?functional? re set event if it has not been confi gured to trigger a ?short? sequence. the reset state machine exits phase1 and ente rs phase2 on verificat ion of the following: ? all enabled, non-shortened ?functiona l? resets have been processed ? a minimum of 350 fast intern al rc oscillator (16mhz) clock cycles have elapsed since the last enabled external or non-shorte ned ?functional? reset event 37.4.1.3 phase2 phase this phase is entered on exit from phase1. the rese t state machine exits phase2 and enters phase3 on verification of the following: ? all processes that need to be done in phase2 are completed ? code and data flash initialization ? a minimum of 8 fast internal rc oscillator (16mhz ) clock cycles have elapsed since entering phase2 37.4.1.4 phase3 phase this phase is a entered either on exit from phase2 or immediately from idle on an enabled, shortened ?functional? reset event. the reset state machine ex its phase3 and enters idle on verification of the following: ? all processes that need to be done in phase3 are completed ? code and data flash initialization ? a minimum of 40 fast internal rc oscillator (16mhz) clock cycles have elapsed since the last enabled, shortened ?functional? reset event 37.4.1.5 idle pha se this is the final phase and is entered on exit from phase3. when this phase is reached, the mc_rgm releases control of the system to the platform and waits for new reset events that can trigger a reset sequence.
pxd20 microcontroller reference manual, rev. 1 37-30 freescale semiconductor preliminary?subject to change without notice 37.4.2 destructive resets a ?destructive? reset indicates that an event has occu rred after which critical re gister or memory content can no longer be guaranteed. the status flag associated with a give n ?destructive? reset event (rgm_des.f_ bit) is set when the ?destructive? re set is asserted and the power-on reset is not asserted. it is possible for multiple status bits to be set simultaneously , and it is software?s responsibility to determine which reset source is the most critical for the application. the ?destructive? reset can be optionall y disabled by writing bit rgm_derd.d_ pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-31 preliminary?subject to change without notice ? an external reset event ? a ?functional? reset event configured via the rg m_fbre register to assert the external reset in this case, the external reset is asserted until the end of phase3. 37.4.4 functional resets a ?functional? reset indicates that an event has occurr ed after which it can be guaranteed that critical register and memory content is still intact. the status flag associated with a gi ven ?functional? reset event (rgm_fes.f_ bit) is set when the ?functional? reset is asse rted and the power-on reset is not a sserted. it is possible for multiple status bits to be set simultaneously , and it is software?s responsibility to determine which reset source is the most critical for the application. the ?functional? reset can be optionally disabled by software writing bit rgm_ferd.d_ . note the rgm_ferd register can be wr itten only once between two power-on reset events. an enabled functional reset will nor mally trigger a reset sequence star ting from the beginning of phase1. nevertheless, the rgm_fess register enables the furt her configuring of the re set sequence triggered by a functional reset. when rgm_fess.ss_ is set, the associated ?functional? reset will trigger a reset sequence starting di rectly from the beginning of phas e3, skipping phase1 and phase2. this can be useful especially in case a f unctional reset should not reset the flash module. 37.4.5 standby entry sequence standby mode can be entered only when the mc_rgm is in idle. on standby entry, the mc_rgm moves to phase1. the minimum duration c ounter in phase1 does not start until standby mode is exited. on entry to phase1 due to stand by mode entry, the rese ts for all power domains except power domain #0 are asserted. du ring this time, reset is not assert ed as the external reset can act as a wakeup for the device. there is an option to keep the fl ash inaccessible and in low-power m ode on standby exit by configuring the drun mode before standby entry so that the fl ash is in power-down or low-power mode. if the flash is to be inaccessible, the phase2 and phase3 states do not wait for the flash to complete initialization before exiting, and the reset to the flash remains asserted. see the mc_me chapter for detail s on the standby and drun modes. 37.4.6 alternate event generation the mc_rgm provides alternative events to be genera ted on reset source asserti on. when a reset source is asserted, the mc_rgm normally enters the reset seque nce. alternatively, it is possible for each reset
pxd20 microcontroller reference manual, rev. 1 37-32 freescale semiconductor preliminary?subject to change without notice source event (except the power-on reset event) to be converted from a rese t to either a safe mode request issued to the mc_me or to an interrupt request issued to the cpu. alternate event selection for a given reset source is made via the rgm_f/derd and rgm_f/dear registers as shown in table 37-13 . the alternate event is cleared by deas serting the source of the request (i .e. at the reset source that caused the alternate request) and also clearing the appropriate rgm_f/des status bit. note alternate requests (safe m ode as well as interrupt requests) are generated asynchronously. note if a masked ?destructive? reset event which is configured to generate a safe mode/interrupt request occurs during phase0, it is ignored, and the mc_rgm will not send any safe mode /interrupt request to the mc_me. the same is true for masked ?functional? reset events during phase1. 37.4.7 boot mode capturing the mc_rgm provides samp ling of the boot mode pad[22:21] for use by the system to determine the boot mode. this sampling is done five fast internal rc osci llator (16mhz) clock cycles before the rising edge of reset . the result of the sampling is then provided to the system. for each bit, a value of ?1? is produced only if each of the oldest th ree of the five samples have the valu e ?1?, otherwise a value of ?0? is produced. note in order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode valu e to the device at least five fast internal rc oscillator (16mhz) clock periods before the external reset deassertion crosses the v ih threshold. note reset can be low as a consequence of the internal reset generation. this will force re-sampling of the boot mode pins. table 37-13. mc_rgm alternate event selection rgm_f/derd bit value rgm_f/dear bit value generated event 0 x reset 1 0 safe mode request 1 1 interrupt request
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 37-33 preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 37-34 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-1 preliminary?subject to change without notice chapter 38 run-length encoding decoder (rle_dec) 38.1 introduction the rle_dec module is used to decode data that has been compressed using a run length encoding (rle) scheme. it has input and outpu txs fifo buffers directly connect ed to the crossbar switch and requires the cpu or dma to push in the encoded data and then extract the decoded result. the module configuration is optimized for dec oding data stored in a two-dimensi onal image format but can also be used to extract data stored as a linear array. figure 38-1. rle_dec block diagram 38.1.1 overview figure 38-1 is a block diagram of the run-length en coding decoder (rle_dec) module. the module has two independent interfaces that are memory mapped into the device: ? crossbar switch interface for moving data into and out of the module ahb ctrl rle_dec ahb bus fsm t x f i f o r x f i f o regif dma fifo fill levels rx and tx fifo thresholds pixel width busy status busy status write interface write interface read interface read interface crossbar switch ip bus
pxd20 microcontroller reference manual, rev. 1 38-2 freescale semiconductor preliminary?subject to change without notice ? ip bus interface for configuring the module the crossbar interface appears in th e device memory map as two fifos. writes to the rx fifo will cause the rle_dec to begin decoding ope rations. the rle_decs finite st ate machine (fsm) removes data from the rx fifo, decodes it and pl aces the output into the tx fifo. th e decoded data appears in the tx fifo and is removed from th is fifo after it is read by a crossbar master such as the cpu or edma. the dma operations require the use of two different dma channels. the module is configured and its status monitored using registers on the ip bus that appear as locations in the module register memory area. this configuration includes information on the size of the image (or data set) and the size of the individual pixels (or data elements) in the image. the rle_dec uses this information to determine when an operation is comple te for this reason the rle_dec will typically be reconfigured for each operation si nce the size of each compre ssed image will be different. the module can raise interrupts to indicate errors and when an operation is complete. 38.1.2 features the rle_dec supports the following features: ? lossless decompression ? pixel formats supported: 8bpp, 16bpp, 24bpp and 32bpp (programmable) ? ahb mapped rx fifo (8x8 bytes deep) with dma support. ? ahb mapped tx fifo (8x8 bytes deep) with dma support. ? programmable fill levels of read and write buffers fo r initiating burst transfers. ? partial image decode feature, wherein only a portion of the decoded image is given as output. (see section 38.5.3, image coor dinates? example, for details). ? support for stop mode for power-saving purposes 38.1.3 rle_dec modes of operation 38.1.3.1 normal mode in this mode, the rle_dec block performs the normal ?run length en coding? decode operation. further details about this mode of ope ration can be found in chapter 38.5.5, normal mode . 38.1.3.2 module disable mode the module disable mode is used for power management of the devi ce containing the rle_dec module, it is controlled by signals external to the rle_de c. the clock to the non-memory mapped logic in the rle_dec can be stopped while in the module disable mode. see chapter 38.5.6.1, module disable mode .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-3 preliminary?subject to change without notice 38.1.3.3 stop mode stop mode is used for power management by the syst em mode management. when a request is made to enter stop mode, the rle_dec block completes the action currently processe d. then the request is acknowledged. 38.2 external signal description rle_dec has no external signals. 38.3 interrupt and dma request signals the interrupt and dma request lines of the rle_de c module are mapped to the internal flags in the dec_rle_isr register. 38.4 memory map and register definition 38.4.1 memory map table 38-1 shows the rle_dec memory map. 38.4.2 amba bus register memory map table 38-2 shows the rx and tx fifos of rle_dec ma pped to crossbar switch (ahb) interface. table 38-1. rle_dec memory map address offset register location 0x00 module configuration register (rle_dec_mcr) on page 38-4 0x04 image configuration register (rle_dec_icr) on page 38-5 0x08 compressed image size register (rle_dec_cisr) on page 38-6 0x0c decompressed image coordinates register (rle_dec_dicr) on page 38-6 0x10 status register (rle_dec_sr) on page 38-7 0x14 interrupt request status register (rle_dec_isr) on page 38-7 0x18 interrupt request enable register (rle_dec_rier) on page 38-8 0x1c start pixel coordinate register of image (rle_dec_spcr) on page 38-9 0x20 end pixel coordinate register of image (rle_dec_epcr) on page 38-10
pxd20 microcontroller reference manual, rev. 1 38-4 freescale semiconductor preliminary?subject to change without notice 38.4.3 register descriptions 38.4.3.1 module configurati on register (rle_dec_mcr) the rle_dec_mcr holds conf iguration data associated with rle_ dec operation. this register can be accessed with 8-bit, 16-bit and 32-bit wide operations. table 38-2. rle_dec amba bus memory map address register name 0x9000_4000 to 0x9000_403f rx fifo address range:- the ahb master can read from and write into these addresses (for debug purposes only). the fifo operation is performed only when the access is made to the below mentioned memory mapped area for rx fifo. 0x9000_4040 to 0x9000_407f tx fifo address range:- the ahb master can read from and write into these addresses (for debug purposes only). the fifo operation is performed only when the access is made to the below mentioned memory mapped area for tx fifo. 0x9000_4080 to 0x9000_40bf memory mapped area for rx fifo. ahb can only write into this address. a write into this address range results in a write to the rx fifo wherever the write pointer points. if rx fi fo is full, ahb write request will result in hready low, unless space is there for the write operation. (please note: the write(burst or single write) should start from address 0x9000_4080 only.) 0x9000_40c0 to 0x9000_40ff memory mapped area for tx fifo. ahb can only read from this address. a read from this address range results in a read from the top of the tx fifo. if tx fifo is em pty, ahb read request will result in hready low, unless some data is available for reading. (please note: the read(burst or single read) should start from address 0x9000_40c0 only.) address: rle_dec_base + 0x000 write:anytime 0123456789101112131415 r rx_fifo_threshold tx_fifo_threshold w reset0010000000100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000 txffen 0 mdis w reset0000000000000001 figure 38-2. module configurat ion register (rle_dec_mcr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-5 preliminary?subject to change without notice 38.4.3.2 image configuration register (rle_dec_icr) the rle_dec_icr holds configurati on data associated with configur ation of image parameters. this register can be accessed with 8-bit, 16-bit and 32-bit wide operations. table 38-3. rle_dec_mcr field descriptions field description rx_fifo_t hreshold rx fifo threshold: this field determines how much space should be available for writing into the rx buffer until the write action is triggered (through dm a). when the number of bytes of available space in rx fifo exceeds the number given by this field the rle_dec_fr[rffr] flag is asserted. tx_fifo_th reshold tx fifo threshold: this field determines how many entries must be read into the tx fifo until the readout action is triggered. when the number of valid entries in the tx fifo exceeds the number given by this field the rle_dec_fr[tfdr] flag is asserted. txffen tx fifo flush enable. this bit configures th e operation of the rle decoder in the case when the image decoding is complete and the data remaining in the tx fifo is below the value of tx_fifo_threshold. 0 trigger the dma action only when txfi fo has more data than tx_fifo_threshold. 1 trigger the dma action until the tx fifo is empty even if it is less than tx_fifo_threshold. mdis module disable. the mdis bit allows the clock to the non-memory mapped logic in the rle_dec to be stopped, putting the rle_dec in a software controlled power-saving state. see section 38.5.6.1, module disable mode , for more information. 0 enable rle_dec clocks. 1 allow external logic to disable rle_dec clocks. address: rle_dec_base + 0x004 write:anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 00000 0 000000000 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 0 0 0 0 0 0 0 0 0 0 width w reset0 00000 0 000000000 figure 38-3. image configurat ion register (rle_dec_icr) table 38-4. rle_dec_ icr field descriptions field description width 00 -- pixel width is 08-bits; 01 -- pixel width is 16-bits; 10 -- pixel width is 24-bits; 11 -- pixel width is 32-bits.
pxd20 microcontroller reference manual, rev. 1 38-6 freescale semiconductor preliminary?subject to change without notice 38.4.3.3 compressed image size register (rle_dec_cisr) the rle_dec_cisr holds the size of the compressed image. this register can be accessed with 8-bit, 16-bit and 32-bit wide operations. 38.4.3.4 decompressed image coordi nates register (rle_dec_dicr) the rle_dec_dicr holds the final coordinates of the decompressed image. decompression is done until this pixel reach ed. please refer to section 38.5.3, image coor dinates? example . this register can be accessed with 8-bit, 16-bit and 32-bit wide operations. address: rle_dec_base + 0x008 write:anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r0 00000 0 000000000 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r size w reset0 00000 0 000000000 figure 38-4. compressed image size register (rle_dec_cisr) table 38-5. rle_dec_cisr field descriptions field description size this is the byte-size of compressed image, that w ill be given as an input to the rle_dec. this should be programmed before the module is enabled using mdis. address: rle_dec_base + 0x00c write:anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r x w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y w reset0 00000 0 000000000 figure 38-5. decompressed image coordinates register (rle_dec_dicr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-7 preliminary?subject to change without notice 38.4.3.5 status register (rle_dec_sr) the rle_dec_sr register provide s the status information about the tx fifo and rx fifo. 38.4.3.6 interrupt request status register (rle_dec_isr) the rle_dec_isr register is the interrupt status register for rle decoder. the interrupts are asserted upon associated events. they ar e deasserted upon write to this register. table 38-6. rle_dec_di cr field descriptions field description x this is the x coordinate of the final pixel of the decompressed image, that will be given as the output of the rle decoder. this should be programmed be fore the module is enabled using mdis. this field has a minimum value of 1. y this is the y coordinate of the final pixel of the decompressed image, that will be given as the output of the rle decoder. this should be programmed be fore the module is enabled using mdis. this field has a minimum value of 1. address: rle_dec_base + 0x0010 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxfree txfill w reset0100000000000000 figure 38-6. status register (rle_dec_sr) table 38-7. rle_dec_sr field descriptions field description rxfree this status gives the amount of free spac e in bytes, available in rx fifo to write. txfill this status gives the amount of data in bytes, available in tx fifo to read.
pxd20 microcontroller reference manual, rev. 1 38-8 freescale semiconductor preliminary?subject to change without notice 38.4.3.7 interrupt request enable register (rle_dec_rier) the rle_dec_rier register provides enables for the interrupts in the rle_dec module. address: rle_dec_base + 0x0014 reset upon write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 rxdif txdif rxuif txuif rxfif txfif rxeif txeif w w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 38-7. interrupt request status register (rle_dec_isr) table 38-8. rle_dec_isr field descriptions field description rxdif rx image done. is asserted when the amount of received data has equalled the programmed ?compressed image size register? txdif tx image done. is asserted when coordinates of decompressed image cross end pixel coordinates which are defined in ?end pixel coordinate register? rxuif rx fifo has space. asserted when rx fifo has more space than rx fifo threshold. (dma request for input data.) txuif tx fifo has data. asserted when tx fifo has more data than tx fifo threshold. (dma request for output data.) rxfif rx fifo full: asserted when rx fifo has no mo re space left for data and a write was attempted on it. txfif tx fifo full: asserted when tx fifo has no more space left for data and a write was attempted on it. rxeif rx fifo empty: asserted when rx fifo has no data and a read was attempted from it. txeif tx fifo empty: asserted when tx fifo has no data and a read was attempted from it.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-9 preliminary?subject to change without notice 38.4.3.8 start pixel coordinate register of image (rle_dec_spcr) the rle_dec_spcr holds the start c oordinates of the decompressed image. this register can be accessed with 8-bit, 16-bit and 32-bit wide operations. address: rle_dec_base + 0x0018 write: anytime 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 rxdie txdie rxuie txuie rxfie txfie rxeie txeie w reset0000000000000000 figure 38-8. interrupt request enable register (rle_dec_rier) table 38-9. rle_dec_rier field descriptions field description rxdie interrupt enable for rx image done interrupt txdie interrupt enable for tx image done interrupt rxuie interrupt enable for rx fifo has space interrupt txuie interrupt enable for tx fifo has data interrupt rxfie interrupt enable for rx fifo full interrupt txfie interrupt enable for tx fifo full interrupt rxeie interrupt enable for rx fifo empty interrupt txeie interrupt enable for tx fifo empty interrupt
pxd20 microcontroller reference manual, rev. 1 38-10 freescale semiconductor preliminary?subject to change without notice 38.4.3.9 end pixel coordinate re gister of image (rle_dec_epcr) the rle_dec_spcr holds the end coordinates of the decompressed image of interest. see section 38.5.3, image coordinates? example . this register can be accesse d with 8-bit, 16-bit and 32-bit wide operations. address: rle_dec_base + 0x001c write:anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r x w reset0 00000 0 000000001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y w reset0 00000 0 000000001 figure 38-9. start pixel coordinate register of image (rle_dec_spcr) table 38-10. rle_dec_spcr field descriptions field description x this is the x coordinate of the first pixel of the decompressed image, that will be given as the output of the rle decoder. see section 38.5.3, image coordinates? example . this should be programmed before the module is enabled using mdis. this field has a minimum value of 1. y this is the y coordinate of the final pixel of the decompressed image, that will be given as the output of the rle decoder. see section 38.5.3, image coordinates? example . this should be programmed before the module is enabled using mdis. this field has a minimum value of 1. address: rle_dec_base + 0x0020 write:anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r x w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y w reset0 00000 0 000000000 figure 38-10. end pixel coordinate register of image (rle_dec_epcr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-11 preliminary?subject to change without notice 38.4.4 crossbar switch memory map descriptions 38.4.4.1 rx fifo address range the size of the rx fifo is 8-bytes x 8-bytes . the rx fifo address range is 0x9000_4000 to 0x9000_4038. a crossbar switch can read from and write into these addresses (for debug purposes only). the fifo operation is performed only when the access is made to the below mentioned memory mapped area for rx fifo. 38.4.4.2 tx fifo address range the size of the tx fifo is 8-bytes x 8-bytes . the tx fifo addre ss range is 0x9000_4040 to 0x9000_4078. a crossbar switch can read from and write into these addresses (for debug purposes only). the fifo operation is performed only when the access is made to the below mentioned memory mapped area for tx fifo. 38.4.4.3 memory mapped rx fifo the contents of the rx fifo ar e mapped to 0x9000_4080. writin g rle compressed data into the rx fifo increments the write-pointer based on the size of the written data. the rle decode process can be automated by using the edma. each time the free space of rx fifo exceeds a certain level (programmabl e), a (rx fifo) dma request is a sserted. when enabled the edma can be used to write rle compressed data into the rx fifo. a read request to rx fifo results in an error. 38.4.4.4 memory mapped tx fifo the contents of the tx fifo are mapped to 0x9000_40c0. the rle_dec module writes decompressed data into the tx fifo. the rle decode process can be automated by using th e edma. each time the contents of the tx fifo exceeds a certain fill-level (progr ammable), a (tx fifo) dma request is asserted. when enabled the edma can be used to read the decompressed data from the tx fifo. table 38-11. rle_dec_epcr field descriptions field description x this is the x coordinate of the last pixel of the decompressed image of interset, that will be given as the output of the rle decoder. see section 38.5.3, image coordinates? example . this should be programmed before the module is enabled using mdis. this field has a minimum value of 1. y this is the y coordinate of the last pixel of the decompressed image of interset, that will be given as the output of the rle decoder. see section 38.5.3, image coordinates? example . this should be programmed before the module is enabled using mdis. this field has a minimum value of 1.
pxd20 microcontroller reference manual, rev. 1 38-12 freescale semiconductor preliminary?subject to change without notice a write request to tx fifo results in an error. 38.5 functional description 38.5.1 rle encoding format the expected encoding is as follows: ? the first data byte in the encoded image is a command byte (cmd[7:0]) ? the ms bit (cmd[7]) i ndicates if the following bytes are raw or compress ed pixels. one pixel can be 8-bit, 16-bit, 24-bit or 32-bit wide, depending on th e pixel_width configuration. ? the remaining 7 command bits (cmd[6:0]), specif y the number of raw or co mpressed pixels that follow the command byte. the count is offset by 1 such that value of 0 means one pixel follows. ? for compressed pixels (cmd[7] = 1), only one pixel follows the command byte. this pixel is repeated count+1 times. a new command fo llows after cmd+(1*{pix el width}) pixels. ? for raw pixels (cmd[7] = 0), count+1 number of pixels follow the command byte and these are passed to the tx fifo as is. ? if there is more data to decode then a new command follows after cmd+({count+1}*{pixel width}) bytes. this encoding continue s until the whole image is decoded 38.5.2 rle decoding process the recommended process to decode the data is as follows: ? the rle_dec module is disabled by default (mdis=1). ? before enabling the device, program the comp ressed image size register (rle_dec_cisr) and decompressed image size register (rle_dec_dicr) for the image. the decoder expects to read compressed-image-size amount of bytes from th e rx fifo and expects to decode and write decompressed-image-size amount of bytes into the tx fifo. ? when less than the full image is to be decoded then configure the start pixe l coordinates register (rle_dec_spcr) and the end pixel coor dinates register (rle_dec_epcr). ? configure the width of the pixels in the image (rle_dec_icr). ? enable the rle_dec dma rx and tx channels in the dmamux module and connect these to channels in the edma. configure the selected edma channels such that the compressed image is written into the rx fifo an the decomp ressed image is copy from the tx fifo. ? enable the rle_dec by setting mdis=0. ? when the decoding is complete th e txdif flag is set (rle_dec_isr register). this indicates that the rle process is complete but depending on the size of the image and the value of the rle_dec_mcr[txffen] bit there ma y be some decoded pixels that have not been copied from the tx fifo because its threshold has not been reached. ? if the txffen bit is not set to automatically flus h the tx fifo then trigger an edma transfer under software control until the tx fifo is empty (txfill=0 in rle_dec_sr register).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 38-13 preliminary?subject to change without notice ? set mdis=1 to disable the module. the module needs to be disabled at the end of image decompression and enabled again only after the parameters of the new image have been programmed. 38.5.3 image coordinates? example figure 38-11 shows the definition of the coordinates used in rle_dec to define the decompressed image. let the decompressed image be of si ze 10-pixels x 10-pixels. th e start coordinate is the coordinate at the top-left corner, (1,1), i.e. x=1 and y=1. the last coordi nate is bottom-right coordi nate, (10,10) in this case. so, we see that the image size can be described by th e bottom-right coordinate of the image. this pixel coordinate is described in the register ?decompressed image c oordinate register.? if only a part of the complete image is to be given as output, then ?start pixel coordinate register? and ?end pixel coordinate register? s hould be programmed appropriately. fo r example, in the figure shown below, if the gray area is the imag e of interest and it is only require d to output only that part of the decompressed image, then the ?start pixel coordinate register? should be programmed as (x=3, y=4) and ?end pixel coordinate register? shou ld be programmed as (x=7, y=7). if however, the complete decompressed image is to be output, then the ?start pi xel coordinate register? should be programmed as (x=1, y=1) and ?end pixel coordinate register? s hould be programmed as (x=10, y=10), i.e. equal to ?decompr essed image coordinate register.? 38.5.4 modes of operation the possible operational modes of the rle_dec block are: ? normal mode: this is used for normal rle decomp ression of data received from ahb interface. the module enters this mode by deasserting rle_dec_mcr[mdis]. ? stop mode: the mode used by th e system when changing modes if the rle is no longer required. when the system requests stop mode, the rle_dec block completes the execution of the current command and acknowledges the request. the system then removes clocks to the rle_dec block. (1,1) (2,1) (3,1) (4,1) (5,1) (6,1) (7,1) (8,1) (9,1) (10,1) (1,2) (1,3) (1,4) (3,4) (1,5) (1,6) (1,7) (7,7) (1,8) (1,9) (1,10) (10,10) figure 38-11. decompressed 10x10 pixel image
pxd20 microcontroller reference manual, rev. 1 38-14 freescale semiconductor preliminary?subject to change without notice ? module disable mode: the mode is used for power management. the clock to the non-memory mapped logic in the rle_dec ca n be stopped while in module di sable mode.the module enters the mode by setting rle_dec_mcr[mdis]. 38.5.5 normal mode in normal mode, decompression of data is performed using rle scheme. the module enters this mode by deasserting rle_dec_mcr[mdis]. whenever the rx fifo has some data, the state m achine is triggered. the de coding operation starts according to the rle decoding scheme described above. whenever tx fifo is not full and rx fifo has got data to transmit, the decoding is done. after completing the decode of one image, the normal mode should be exited. for decoding the data of next image, the re-entry to norm al mode should be done only after th e new image parameters have been programmed. 38.5.6 power-saving features the rle_dec supports two power-saving strategies: ? stop mode ? module disable mode 38.5.6.1 module disable mode the rle_dec block is in module disable mode by defa ult. it is exited to no rmal-mode by de-asserting the mdis bit in rle_dec_mcr register. host software can initiate the modul e disable mode by writing a ?1? to the mdis bit. when a request is encountered to enter the module disable mode the rl e_dec negates clock-enable when it is ready to enter the module disable mode. if implemented, the clock-enable signal can stop the clock to the non-memory mapped logic. when clock-enable is negated, the rle_dec is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different effect when the rle_dec is in the module disable mode. dma request signa ls cannot be cleared while in the module disable mode. note that issuing a new ahb request is illegal in no rmal mode during the time starting with raising the request to enter module disable mode and e nding with leaving the module disable mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-1 preliminary?subject to change without notice chapter 39 sound generator module (sgm) 39.1 introduction the sgm is a 4-channel sound generator supporti ng autonomous audio note generation, mono linear pcm data playback, mixing, and amplitude control. output data from the sgm mixer in the form of stereo 16-bit pcm samples can be fed to an external audio dac using its i2s interface or to an internal pwm for output to an external lpf. 39.2 features the sgm provides the following features: ? four independent audio channels with dedicate d fifo buffers ? four channel audio mixer featuri ng left and right channel outputs ? individual channel volume control ? volume resolution 8 bits (256 volume settings) ? input data formats supported : 8, 12, 14 and 16 bit ? mono 16-bit pwm output to drive external lpf and speaker/buzzer. ? i2s interface ? choice of operating clocks to allow fl exible selection of audio sample rates ? module disable for power savi ng when sgm is not in use the sgm channels support two modes of operation: ? direct digital synthesis (dds) mode ? fifo acts as a memory buffer cont aining waveform samples (wavetable) ? programmable sample rate ? configurable asr envelope with 8-bit volume control ? linear increment (attack) and decremen t (release) with programmable amplitude ? exponential increment (attack) and decrement (release) with programmable amplitude ? programmable sustain time ? programmable number of note pulses 1 to 65536 with unlimit ed repetition option ? automatic inter-note time control ? sound start/stop function to start or stop sound generation immediately ? buffered configuration registers ? wave mode ? input fifo for each channel to buffer in coming wave file audio sample stream. ? dma request associated with each channel. ? programmable fifo watermark
pxd20 microcontroller reference manual, rev. 1 39-2 freescale semiconductor preliminary?subject to change without notice ? automatic wave duration control ? automatic dead-time control ? repeat mode with progr ammable repeat number ? ability for each channel to operate in wave mode or dds mode independently of other channels ? synchronisation option for multiple channels in wave mode interrupts are supported as follows: ? dds mode: ? at the end of autonomous increment/decrement ? at the end of programmed sequence of note pulses ? on reaching configurable amplitude leve l during autonomous increment/decrement ? wave mode: ? fifo full / empty / watermark 39.3 device-specific configuration the i2s and pwm outputs are multiple xed together on this device, and the active output is determined by the sgmctl[pwme] bit. see chapter 3, signal description, for details for pin assignments.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-3 preliminary?subject to change without notice 39.4 block diagram a block diagram of the sgm module is shown in figure 39-1 . figure 39-1. high level block diagram of sgm vol-0 mixer-l pwm pre-scalers sgm bus clock vol-1 vol-2 vol-3 i2s master sgm module dma req 0-3 fifo-1 fifo-0 fifo-2 fifo-3 dds0/sfc0 ch0 ch1 ch2 ch3 resample pwm resample-0 resample-1 resample-2 resample-3 clock select ips interface resmp_clk ch3_clk ch2_clk ch1_clk ch0_clk pwm_clk mixer-r left channel right channel channel selector channel selector channel volume input buffer dds1/sfc1 dds2/sfc2 dds3/sfc3 registers buffer i2s configuration/status fifo i2s 34bit x 8 signals pwmoa pwmo sck fs do mclk sgm bus clock x 2 control
pxd20 microcontroller reference manual, rev. 1 39-4 freescale semiconductor preliminary?subject to change without notice 39.5 external signal description 39.6 memory map and register definition this section describes the sgm me mory map and register definition. 39.6.1 memory map the sgm module contains a set of control and status registers loca ted between sgm register base + 0x0000 and 0x00fc (tbd). table 39-1. sgm external interface signals signal description i/o type voltag e range width pwm external signals pwmo either pwm block sample rate clock or composite signal that can be filtered, amplified and fed to a buzzer or loudspeaker (sgmctl.os = 1). o logic [0,vdd] 1 pwmoa pwm block pwm signal output signal. o logic [0,vdd] 1 i2s external signals sck clock out (audio data driven on this clock) o logic [0,vdd] 1 do audio serial data out o logic [0,vdd] 1 fs frame sync o logic [0,vdd] 1 mclk mclk (auxiliary clock) output enable o logic [0,vdd] 1 table 39-2. sgm memory map address register width access location $base+0x0000 sgmctl 32 read/write on page 39-6 $base+0x0004 sgmcfg 32 read/write on page 39-8 $base+0x0008 clkrsp 32 read/write on page 39-11 $base+0x000c clkch3 32 read/write on page 39-12 $base+0x0010 ddsch3 32 read/write on page 39-12 $base+0x0014 ecrach3 32 read/write on page 39-13 $base+0x0018 ecrrch3 32 read/write on page 39-14 $base+0x001c ecrsch3 32 read/write on page 39-15 $base+0x0020 ntch3 32 read/write on page 39-16 $base+0x0024 tpcch3 32 read/write on page 39-16 $base+0x0028 ptcch3 32 read/write on page 39-17
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-5 preliminary?subject to change without notice $base+0x002c dtcch3 32 read/write on page 39-18 $base+0x0030 rncch3 32 read/write on page 39-18 $base+0x0034 clkch2 32 read/write on page 39-12 $base+0x0038 ddsch2 32 read/write on page 39-12 $base+0x003c ecrach2 32 read/write on page 39-13 $base+0x0040 ecrrch2 32 read/write on page 39-14 $base+0x0044 ecrsch2 32 read/write on page 39-15 $base+0x0048 ntch2 32 read/write on page 39-16 $base+0x004c tpcch2 32 read/write on page 39-16 $base+0x0050 ptcch2 32 read/write on page 39-17 $base+0x0054 dtcch2 32 read/write on page 39-18 $base+0x0058 rncch2 32 read/write on page 39-18 $base+0x005c clkch1 32 read/write on page 39-12 $base+0x0060 ddsch1 32 read/write on page 39-12 $base+0x0064 ecrach1 32 read/write on page 39-13 $base+0x0068 ecrrch1 32 read/write on page 39-14 $base+0x006c ecrsch1 32 read/write on page 39-15 $base+0x0070 ntch1 32 read/write on page 39-16 $base+0x0074 tpcch1 32 read/write on page 39-16 $base+0x0078 ptcch1 32 read/write on page 39-17 $base+0x007c dtcch1 32 read/write on page 39-18 $base+0x0080 rncch1 32 read/write on page 39-18 $base+0x0084 clkch0 32 read/write on page 39-12 $base+0x0088 ddsch0 32 read/write on page 39-12 $base+0x008c ecrach0 32 read/write on page 39-13 $base+0x0090 ecrrch0 32 read/write on page 39-14 $base+0x0094 ecrsch0 32 read/write on page 39-15 $base+0x0098 ntch0 32 read/write on page 39-16 $base+0x009c tpcch0 32 read/write on page 39-16 $base+0x00a0 ptcch0 32 read/write on page 39-17 $base+0x00a4 dtcch0 32 read/write on page 39-18 $base+0x00a8 rncch0 32 read/write on page 39-18 $base+0x00ac vcrwav 32 read/write on page 39-19 table 39-2. sgm memory map (continued) address register width access location
pxd20 microcontroller reference manual, rev. 1 39-6 freescale semiconductor preliminary?subject to change without notice 39.6.2 register descriptions 39.6.2.1 sgm control register (sgmctl) the sgmctl register controls the function of sgm. $base+0x00b0 sgmtocr 32 read/write on page 39-20 $base+0x00b4 mixcr 32 read/write on page 39-20 $base+0x00b8 clkpwm 32 read/write on page 39-21 $base+0x00bc pwmcr 32 read/write on page 39-22 $base+0x00c0 dfifo1 32 write on page 39-22 $base+0x00c4 dfifo2 32 write on page 39-23 $base+0x00c8 fifowm 32 read/write on page 39-24 $base+0x00cc fifor p 32 read/write on page 39-24 $base+0x00d0 fifowp 32 read/write on page 39-25 $base+0x00d4 sgmst 32 read on page 39-25 $base+0x00d8 sgmicfd 32 read/write on page 39-27 $base+0x00dc sgmic 32 read/write on page 39-29 $base+0x00e0 sgmisfd 32 read/write on page 39-31 $base+0x00e4 sgmis 32 read/write on page 39-32 $base+0x00e8 i2sen 32 read/write on page 39-34 $base+0x00ec i2sctl 32 read/write on page 39-35 $base+0x00f0 i2sdfc 32 read/write on page 39-36 $base+0x00f4 i2sprs 32 read/write on page 39-38 $base+0x00f8 i2sintc 32 read/write on page 39-38 $base+0x00fc i2sst 32 read/write on page 39-39 table 39-2. sgm memory map (continued) address register width access location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-7 preliminary?subject to change without notice sgm register base + 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r sog ch3 sog ch2 sog ch1 sog ch0 0000 mdis 0000000 w reset0000000010000000 1514131211109876543210 r mod ch3 mod ch2 mod ch1 mod ch0 0000 toe wav clks 000 pwm e pwm chs os w reset0000000001000000 figure 39-2. sgm control register (sgmctl) table 39-3. sgmctl register description field description 31 sogch3 start of generation of channel 3. control the start/stop of the channel 3. 0 stop the channel sound generation. 1 start the channel sound generation. 30 sogch2 start of generation of channel 2. control the start/stop of the channel 2. 0 stop the channel sound generation. 1 start the channel sound generation. 29 sogch1 start of generation of channel 1. control the start/stop of the channel 1. 0 stop the channel sound generation. 1 start the channel sound generation. 28 sogch0 start of generation of channel 0. control the start/stop of the channel 0. 0 stop the channel sound generation. 1 start the channel sound generation. 27-24 reserved. 23 mdis module disable. force the sgm into a power-down mode by disabling the module clock. 0 clock input switched on. 1 clock input switched off. force sgm enter low-power. note: to enable the sgm, this bit needs to be cleared before configuring other registers of sgm. 22-16 reserved. 15 modch3 channel 3 mode selection. 0 wave mode 1 dds mode 14 modch2 channel 2 mode selection. 0 wave mode 1 dds mode 13 modch1 channel 1 mode selection. 0 wave mode 1 dds mode 12 modch0 channel 0 mode selection. 0 wave mode 1 dds mode
pxd20 microcontroller reference manual, rev. 1 39-8 freescale semiconductor preliminary?subject to change without notice 39.6.2.2 sgm configuration register (sgmcfg) the sgmcfg register determin es the configuration of sgm. 11-8 reserved. 7 toe time out enable. 0 disable timeout 1 enable timeout 6 wavclks wave mode clock selection. select the resample clock as channel clock for all wave mode channels. 0 use the individual channel clock. 1 select the resample clock as channel clock for all channels which are in wave mode 5-3 reserved. 2 pwme pwm output select. select the pwm or i2s output. 0 select the i2s output 1 select the pwm output. 1 pwmchs pwm channe l select. select the data source for pwm duty cycle. 0 select the output data of mi xer left as the duty cycle of pwm 1 select the output data of mixe r right as the duty cycle of pwm 0 os sgm output selection. control separate or mixed ?frequency? and ?volume? outputs for pwm. 0 separate outputs. 1 mixed outputs sgm register base + 0x0004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r at k f ch3 at k f ch2 at k f ch1 at k f ch0 relf ch3 relf ch2 relf ch1 relf ch0 nop ech3 nop ech2 nop ech1 nop ech0 tpce ch3 tpce ch2 tpce ch1 tpce ch0 w reset0000000000000000 1514131211109876543210 r rpte ch3 rpte ch2 rpte ch1 rpte ch0 0000 sfch3 sfch2 sfch1 sfch0 w reset0000000000000000 figure 39-3. sgm configuration register (sgmcfg) table 39-3. sgmctl register description (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-9 preliminary?subject to change without notice table 39-4. sgmcfg register description field description 31 at k f c h 3 envelope attack style for channel 3. this bit controls the type of interp olation used in the attack phase for channel 3 in dds mode. 0 linear interpolation 1 exponential interpolation 30 at k f c h 2 envelope attack style for channel 2. this bit controls the type of interp olation used in the attack phase for channel 2 in dds mode. 0 linear interpolation 1 exponential interpolation 29 at k f c h 1 envelope attack style for channel 1. this bit controls the type of interp olation used in the attack phase for channel 1 in dds mode. 0 linear interpolation 1 exponential interpolation 28 at k f c h 0 envelope attack style for channel 0. this bit controls the type of interp olation used in the attack phase for channel 0 in dds mode. 0 linear interpolation 1 exponential interpolation 27 relfch3 envelope release style for channel 3. this bit controls the type of interpolation used in the release phase for channel 3 in dds mode. 0 linear interpolation 1 exponential interpolation 26 relfch2 envelope release style for channel 2. this bit controls the type of interpolation used in the release phase for channel 2 in dds mode. 0 linear interpolation 1 exponential interpolation 25 relfch1 envelope release style for channel 1. this bit controls the type of interpolation used in the release phase for channel 1 in dds mode. 0 linear interpolation 1 exponential interpolation 24 relfch0 envelope release style for channel 0. this bit controls the type of interpolation used in the release for channel 0 in dds mode. 0 linear interpolation 1 exponential interpolation 23 nopech3 envelope no-output phase enable for channel 3. in dds mode this bit contro ls the inter-note no-output phase. 0 disable the no-output phase for channel 3 in dds mode. 1 enable the no-output phase for channel 3 in dds mode. 22 nopech2 envelope no-output phase enable for envelope for channel 2. in dds mode this bit controls the inter-note no-output phase. 0 disable the no-output phase for channel 2 in dds mode. 1 enable the no-output phase for channel 2 in dds mode. 21 nopech1 envelope no-output phase enable for envelope for channel 1. in dds mode this bit controls the inter-note no-output phase. 0 disable the no-output phase for channel 1 in dds mode. 1 enable the no-output phase for channel 1 in dds mode. 20 nopech0 envelope no-output phase enable for envelope for channel 0. in dds mode this bit controls the inter-note no-output phase. 0 disable the no-output phase for channel 0 in dds mode. 1 enable the no-output phase for channel 0 in dds mode.
pxd20 microcontroller reference manual, rev. 1 39-10 freescale semiconductor preliminary?subject to change without notice 19 tpcech3 target note pulse counter enable for channel 3. in dds mode this bit controls the note pulses counter. 0 disable the pulse counter for channel 3 in dds mode. 1 enable the pulse counter for channel 3 in dds mode. 18 tpcech2 target note pulse counter enable for channel 2. in dds mode this bit controls the note pulse counter. 0 disable the pulse counter for channel 2 in dds mode. 1 enable the pulse counter for channel 2 in dds mode. 17 tpcech1 target note pulse counter enable for channel 1. in dds mode this bit controls the note pulse counter. 0 disable the pulse counter for channel 1 in dds mode. 1 enable the pulse counter for channel 1 in dds mode. 16 tpcech0 target note pulse counter enable for channel 0. in dds mode this bit controls the note pulse counter. 0 disable the note pulse counter for channel 0 in dds mode. 1 enable the note pulse counter for channel 0 in dds mode. 15 rptech3 repeat mode enable for channel 3. in wave mode, this bit controls the playback mode for channel 3. 0 disable repeat mode for channel 3 in wave mode. 1 enable repeat mode for channel 3 in wave mode. 14 rptech2 repeat mode enable for channel 2. in wave mode, this bit controls the playback mode for channel 2. 0 disable repeat mode for channel 2 in wave mode. 1 enable repeat mode for channel 2 in wave mode. 13 rptech1 repeat mode enable for channel 1. in wave mode, this bit controls the playback mode for channel 1. 0 disable repeat mode for channel 1 in wave mode. 1 enable repeat mode for channel 1 in wave mode. 12 rptech0 repeat mode enable for channel 0. in wave mode, this bit controls the playback mode for channel 0. 0 disable repeat mode for channel 0 in wave mode. 1 enable repeat mode for channel 0 in wave mode. 11-8 reserved . 7-6 sfch3 sample format for channel 3. defines the pcm data format for channel 3. 00 16-bit 01 14-bit 10 12-bit 11 8-bit 5-4 sfch2 sample format for channel 2. defines the pcm data format for channel 2. 00 16-bit 01 14-bit 10 12-bit 11 8-bit 3-2 sfch1 sample format for channel 1. defines the pcm data format for channel 1. 00 16-bit 01 14-bit 10 12-bit 11 8-bit 1-0 sfch0 sample format for channel 0. defines the pcm data format for channel 0. 00 16-bit 01 14-bit 10 12-bit 11 8-bit field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-11 preliminary?subject to change without notice 39.6.2.3 clock configuration re gister for resampler (clkrsp) the clkrsp register controls the resampling clock. table 39-5. clkrsp register description table 39-6. clock source selection table 39-7. prescaler range sgm register base + 0x0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r clks 00000000000 prsr w reset0000000000000000 1514131211109876543210 r prsm w reset0000000000000001 figure 39-4. clock configuration register for resampler (clkrsp) field description 31-30 clks clock source selection resampler. see ta b l e 3 9 - 6 for details. 29-24 reserved. 18-16 prsr prescaler range of resampler. these three bits determine the range of the prescaler clock, as shown in ta b l e 3 9 - 7 15-0 prsm prescaler modulus select. these 16 bits control the prescale mo dulus counter in the clock generator. the clock divide ratio is (prsm+1). a value of 0 disables the generated clock. clks[1:0] selected clock source 0x00 ips clock 0x01 sample clock 1 0x02 sample clock 2 0x03 system clock prsr[2] prsr[1] prsr[0] prescaled clock 0 0 0 source clock 0 0 1 source clock / 2 0 1 0 source clock / 4 0 1 1 source clock / 8 1 0 0 source clock / 16 1 0 1 source clock / 32 1 1 0 source clock / 64
pxd20 microcontroller reference manual, rev. 1 39-12 freescale semiconductor preliminary?subject to change without notice note: the channel configuration register s are described for channel 3 - clkch3(offset 0x000c) to rncch3 (off set 0x0030). the registers for the other three channels are identical exce pt that they have the offsets shown below: for channel 2, clkch2(offset 0x0034) to rncch2(offset 0x0058). for channel 1, clkch1(offset 0x005c) to rncch1(offset 0x0080). for channel 0, clkch0(offset 0x084) to rncch0(offset 0x00a8). 39.6.2.4 clock configuration register for channel 3 (clkch3) the clkch3 register contro ls the clock for channel 3. table 39-8. clkch3 register description 39.6.2.5 dds configuration regi ster for channel 3 (ddsch3) ddsch3 contains the accumulator incr ement value for channel 3 dds mode. 1 1 1 source clock / 128 sgm register base + 0x000c (channel 3) sgm register base + 0x0034 (channel 2) sgm register base + 0x005c (channel 1) sgm register base + 0x0084 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r clks 00000000000 prsr w reset0000000000000000 1514131211109876543210 r prsm w reset0000000000000001 figure 39-5. clock configuration register for channel 3 (clkch3) field description 31-30 clks clock source selection of channel 3. see ta b l e 3 9 - 6 for details. 29-24 reserved. 18-16 prsr prescaler range of channel 3. these three bits determine the range of the prescaler clock, as shown in ta b l e 3 9 - 7 15-0 prsm prescaler modulus select. these 16 bits control the prescale mo dulus counter in the clock generator. the clock divide ratio is (prsm+1). a value of 0 disables the generated clock.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-13 preliminary?subject to change without notice table 39-9. ddsch3 register description 39.6.2.6 envelope configuration regist er of attack phase for channel 3 (ecrach3) the ecrach3 register controls the envelope shape for the attack phase of channel 3. sgm register base + 0x0010 (channel 3) sgm register base + 0x0038 (channel 2) sgm register base + 0x0060 (channel 1) sgm register base + 0x0088 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r ddsf w reset0000000000000001 1514131211109876543210 r0000000000000000 w reset0000000000000000 figure 39-6. dds configuration register for channel 3 (ddsch3) field description 31-16 ddsf accumulator increment value for dds channel 3. ddsf is added to the wavetable memory pointer every clock cycle. it therefore controls the frequency of the sound. if ddsf is set to all 0?s, no sound will generated. 15-0 reserved. sgm register base + 0x0014 (channel 3) sgm register base + 0x003c (channel 2) sgm register base + 0x0064 (channel 1) sgm register base + 0x008c (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r atkt atksl w reset1111111100000001 1514131211109876543210 r at k s c w reset0000000100000000 figure 39-7. envelope configuration register of attack phase for channel 3 (ecrach3)
pxd20 microcontroller reference manual, rev. 1 39-14 freescale semiconductor preliminary?subject to change without notice table 39-10. ecrach3 register description the duration of the entire attack phase can be calculated with the method below: ? the duration of one step: d step = t chanel clock *(atksc +1) ? the total number of steps fo r linear interpolation: n step = ceil(atkt/atksl) - 1 ? the total number of steps fo r exponential interpolation: n step = ceil(log((atkt+1),2))-1 ? the entire duration of the attack phase : d atk = d step * n step ? the minimum attack phase occurs when atksl = 0xff and atksc = 0 note the function ceil(x) returns the smallest integer no less than x. the function log(x,2) returns the binary logarithm of x. 39.6.2.7 envelope configuration regist er of release phase for channel 3 (ecrrch3) the ecrrch3 register controls the envelope shape for the release phase of channel 3. field description 31-24 at k t target volume of attack phase. these bits control the final amplitude of the attack phase. 23-16 atksl attack step size. these bits control the step he ight of the volume increment for the envelope if linear interpolation is selected. for each step, atksl is added to the existing amplitude. 15-0 at k s c attack step duration count. these bits control the duration of an amplitude increment step for the asr envelope. the duration counter is clocked by the cha nnel clock. when the value of the step counter reaches atksc+1 the next step will be taken. sgm register base + 0x0018 (channel 3) sgm register base + 0x0040 (channel 2) sgm register base + 0x0068 (channel 1) sgm register base + 0x0090 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r relt relsl w reset0000100000000001 1514131211109876543210 r relsc w reset0000000100000000 figure 39-8. envelope configuration register of release phase for channel 3 (ecrrch3)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-15 preliminary?subject to change without notice table 39-11. ecrrch3 register description the duration of the entire release phase can be calculated with the method below: ? the duration of one step: d step = t chanel clock *(relsc +1) ? the total number of steps fo r linear interpolation: n step = ceil((atkt-relt)/relsl) ? the total number of steps fo r exponential interpolation: n step =ceil(log((atkt/relt),2)) ? the entire duration of release phase : d rel = d step * n step 39.6.2.8 envelope configuration regist er of sustain ti ming for channel 3 (ecrsch3) ersch3 controls the timing of the e nvelope sustain phase of channel 3. table 39-12. ecrsch3 re gister description field description 31-24 relt target volume of release phase. these bits control the final amplitude of the release phase . 23-16 relsl release step length. these bits control the step height of the vo lume decrement for the envelope if linear interpolation is selected. for each step, rels l is subtracted from the existing amplitude.. 15-0 relsc release step duration count. these bits control the duration of an amplitude decrement step for the asr envelope. the duration counter is clocked by the cha nnel clock. when the value of the step counter reaches relsc+1 the next step will be taken. sgm register base + 0x001c (channel 3) sgm register base + 0x0044 (channel 2) sgm register base + 0x006c (channel 1) sgm register base + 0x0094 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 sust w reset0000000000000000 1514131211109876543210 r sust w reset1000000000000000 figure 39-9. envelope timing conf iguration register of sustain timing for channel 3 (ecrsch3) field description 31-24 reserved. 23-0 sust sustain timing. these bits control the timing of sustai n phase of the envelope for channel 3.
pxd20 microcontroller reference manual, rev. 1 39-16 freescale semiconductor preliminary?subject to change without notice the duration of the sustain phase can be calculated with the method below: ? the entire duration of the sustain phase : d sust = t chanel clock *(sust +1) so the entire duration of one note is : d note = d atk + d rel + d sust 39.6.2.9 inter-note no-output pha se timing for channel 3 (ntch3) ntch3 controls the timing of inter- note no-output phase of channel 3. table 39-13. ntch3 register description the duration of the no-output phase can be calculated with the method below: ? the entire duration of attack phase : d nop = t chanel clock *(nopt +1) 39.6.2.10 target note pulse count for channel 3 (tpcch3) tpcch3 controls the target note pulse number for channel 3 in dds mode. sgm register base + 0x0020 (channel 3) sgm register base + 0x0048 (channel 2) sgm register base + 0x0070 (channel 1) sgm register base + 0x0098 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 nopt w reset0000000000000000 1514131211109876543210 r nopt w reset1000000000000000 figure 39-10. inter-note no-output phase timing for channel 3 (ntch3) field description 31-24 reserved. 23-0 nopt no-output timing. these bits control the timing of no-output phase of the channel 3.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-17 preliminary?subject to change without notice table 39-14. tpcch3 register description 39.6.2.11 playback timing configurat ion register for channel 3(ptcch3) ptcch3 controls the length of pla yback for channel 3 in wave mode. sgm register base + 0x0024 (channel 3) sgm register base + 0x004c (channel 2) sgm register base + 0x0074 (channel 1) sgm register base + 0x009c (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r tpc w reset0000000010000000 figure 39-11. target note pulse number for channel 3 (tpcch3) field description 31-16 reserved . 14-0 tpc target note pulse count. these bits control the number of note pulses in dds mode for channel 3. when the pulses number reaches tpc channel 3 ent ers the idle state. if the tpc is set to 0, the note generation will be endless until the sgmtcl.sogch3 de-asserts. sgm register base + 0x0028 (channel 3) sgm register base + 0x0050 (channel 2) sgm register base + 0x0078 (channel 1) sgm register base + 0x00a0 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 playbt w reset0000000000000000 1514131211109876543210 r playbt w reset1000000000000000 figure 39-12. playback timing configuration register for channel 3(ptcch3)
pxd20 microcontroller reference manual, rev. 1 39-18 freescale semiconductor preliminary?subject to change without notice table 39-15. pbtcch3 register description 39.6.2.12 dead time c onfiguration register for channel 3(dtcch3) dtcch3 controls the timing of th e deadtime between wave repetitio ns for channel 3 in wave mode. table 39-16. dtcch3 register description 39.6.2.13 repeat number configuration register for channel 3(rncch3) rncch3 controls the repetition number for channel 3 in wave mode. field description 22-0 playbt playback time. these bits control the length of playback for channel 3 in wave mode. the channel fetches and plays this number of sample s for each wave repetition. sgm register base + 0x002c (channel 3) sgm register base + 0x0054 (channel 2) sgm register base + 0x007c (channel 1) sgm register base + 0x00a4 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000 deadt w reset0000000000000000 1514131211109876543210 r deadt w reset1000000000000000 figure 39-13. dead time configuration register for channel 3(dtcch3) field description 22-0 deadt dead time. these bits control the timing of deadtime for channel 3 in wave mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-19 preliminary?subject to change without notice table 39-17. rptn register description 39.6.2.14 volume control regi ster for wave mode (vcrwav) vcrwav controls the volume of all 4 channels in wave mode. sgm register base + 0x0030 (channel 3) sgm register base + 0x0058 (channel 2) sgm register base + 0x0080 (channel 1) sgm register base + 0x00a8 (channel 0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r000000 rptn w reset0000000010000000 figure 39-14. repeat number configur ation register fo r channel 3(rncch3) field description 9-0 rptn repeat number. these bits control the number of repetitions fo r channel 3 in wave mode when the repeat mode is selected. setting rptn to 0 causes the wave to repeat endlessly. sgm register base + 0x00ac 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r volch3 volch2 w reset1111111111111111 1514131211109876543210 r volch1 volch0 w reset1111111111111111 figure 39-15. volume control register for wave mode (vcrwav)
pxd20 microcontroller reference manual, rev. 1 39-20 freescale semiconductor preliminary?subject to change without notice table 39-18. vcrwav register description 39.6.2.15 sgm timeout count register (sgmtocr) sgmtocr controls the sound playback timeout. table 39-19. sgmtocr register description 39.6.2.16 mixer configuration register (mixcr) mixcr controls the channel selection for the left mixer and right mixer. field description 31-24 volch3 volume control for channel 3 in wave mode. 23-16 volch2 volume control for channel 2 in wave mode. 16-8 volch1 volume control for channel 1 in wave mode. 7-0 volch0 volume control for channel 0 in wave mode. sgm register base + 0x00b0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r timeout w reset1000000000000000 1514131211109876543210 r timeout w reset0000000000000000 figure 39-16. sgm timeout count register (sgmtocr) field description 31-0 timtout timeout timing count. these bits control the time out timing when the sgm is playing a sound.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-21 preliminary?subject to change without notice table 39-20. mixcr register description 39.6.2.17 clock configuration register for pwm (clkpwm) the clkpwm register determines the pwm clock. table 39-21. clkpwm register description sgm register base + 0x00b4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r000000000000 chsl w reset0000000000001111 1514131211109876543210 r000000000000 chsr w reset0000000000001111 figure 39-17. mixer configuration register (mixcr) field description 19-16 chsl channel select for left mixer. ? chsl[3]=0 : channel 3 is not selected for left mixer ? chsl[3]=1 : channel 3 is selected for the left mixer 3-0 chsr channel select for right mixer. ? chsr[3]=0 : channel 3 is not selected for the right mixer ? chsr[3]=1 : channel 3 is selected for the right mixer sgm register base + 0x00b8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r clks 00 00000000 prsr w reset0000000000000000 1514131211109876543210 r prsm w reset0000000000000001 figure 39-18. clock configuration register for pwm (clkpwm) field description 31-30 clks clock source selection resampler. see ta b l e 3 9 - 6 for details. 29-24 reserved.
pxd20 microcontroller reference manual, rev. 1 39-22 freescale semiconductor preliminary?subject to change without notice 39.6.2.18 pwm configuration register (pwmcr) pwmcr controls the pwm fr equency and ton frequency. table 39-22. mixcr register description 39.6.2.19 data fifo register 1(dfifo1) dfifo1 provides the data fifo in terface for channel 3 and channel 2. 18-16 prsr prescaler range of resampler. these three bits determine the range of the prescaler clock, as shown in ta b l e 3 9 - 7 15-0 prsm prescaler modulus select. these 16 bits control the prescale mo dulus counter in the clock generator. the clock divide ratio is (prsm+1). a value of 0 disables the generated clock. sgm register base + 0x00bc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r pwmf w reset1000000000000000 1514131211109876543210 r tonf w reset1000000000000000 figure 39-19. pwm configur ation register (pwmcr) field description 31-16 pwmf pwm frequency. these bits control the pwm frequency and also define the maximum amplitude (100% duty cycle) od the pwm. a 100% duty cycle (con tinually high) will be generated if the value of the mixed data is higher than pwmf 15-0 tonf ton frequency. these bits determine the pwm duty cycle change frequency. the divider is clocked by pwm_clk. the divide ratio is 2xtonfxpwmf. field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-23 preliminary?subject to change without notice table 39-23. data fifo register 1 39.6.2.20 data fifo register 2(dfifo2) dfifo2 provides the data fifo in terface for channel 1 and channel 0. table 39-24. data fifo register 2 sgm register base + 0x00c0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w fifoch3 reset0000000000000000 1514131211109876543210 r w fifoch2 reset0000000000000000 figure 39-20. pwm configur ation register (pwmcr) field description 31-16 fifoch3 data fifo for channel 3. writes to this register will be stored in the fifo and increment the fifo write pointer. 15-0 fifoch2 data fifo for channel 2. writes to this register will be stored in the fifo and increment the fifo write pointer. sgm register base + 0x00c4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r w fifoch1 reset0000000000000000 1514131211109876543210 r w fifoch0 reset0000000000000000 figure 39-21. data fifo register (dfifo2) field description 31-16 fifoch1 data fifo for channel 1. writes to this register will be stored in the fifo and increment the fifo write pointer. 15-0 fifoch0 data fifo for channel 0. writes to this register will be stored in the fifo and increment the fifo write pointer.
pxd20 microcontroller reference manual, rev. 1 39-24 freescale semiconductor preliminary?subject to change without notice 39.6.2.21 fifo watermark (fifowm) the fifowm register configures the watermark of the fifos. table 39-25. fifo watermark register 2 39.6.2.22 fifo read pointer (fiforp) the fiforp register contains the current fifo read pointers. any write to frpchx will clear/flush the fifo of the channel, including the read/write pointer and all the fifo flags. any 32-bit write to the fiforp will clear/flush the enti re datapath/pipeline of the sgm. sgm register base + 0x00c8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r wmch3 wmch2 w reset1000000010000000 1514131211109876543210 r wmch1 wmch0 w reset1000000010000000 figure 39-22. fifo watermark register (fifowm) field description 31-24 wmch3 fifo watermark for channel 3. 23-16 wmch2 fifo watermark for channel 2. 16-8 wmch1 fifo watermark for channel 1. 7-0 wmch0 fifo watermark for channel 0. sgm register base + 0x00cc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r frpch3 frpch2 w reset0000000000000000 1514131211109876543210 r frpch1 frpch0 w reset0000000000000000 figure 39-23. fifo read pointer (fiforp)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-25 preliminary?subject to change without notice table 39-26. fifo read pointer 39.6.2.23 fifo write pointer (fifowp) the fifowp contains the current fi fo write pointers. any write to fwpchx will clear/flush the fifo and datapath of this channel, incl uding the read/write pointer and all th e fifo flags. any 32-bit write to the fifowp will clear/flush the entire datapath/pipeline of the sgm. table 39-27. fifo write pointer 39.6.2.24 sgm status register (sgmst) the sgmst register indicates the cu rrent operating status of the sgm. field description 31-24 frpch3 fifo read pointer for channel 3. any write to this byte will clear/flush the fifo of channel 3. 23-16 frpch2 fifo read pointer for channel 2. any write to this byte will clear/flush the fifo of channel 2. 16-8 frpch1 fifo read pointer for channel 1. any write to this byte will clear/flush the fifo of channel 1. 7-0 frpch0 fifo read pointer for channel 0. any write to this byte will clear/flush the fifo of channel 0. sgm register base + 0x00d0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r fwpch3 fwpch2 w reset0000000000000000 1514131211109876543210 r fwpch1 fwpch0 w reset0000000000000000 figure 39-24. fifo write pointer (fifowp) field description 31-24 fwpch3 fifo write pointer for channel 3. any write to this byte will clear/flush the fifo of channel 3. 23-16 fwpch2 fifo write pointer for channel 2. any write to this byte will clear/flush the fifo of channel 2. 16-8 fwpch1 fifo write pointer for channel 1. any write to this byte will clear/flush the fifo of channel 1. 7-0 fwpch0 fifo write pointer for channel 0. any write to this byte will clear/flush the fifo of channel 0.
pxd20 microcontroller reference manual, rev. 1 39-26 freescale semiconductor preliminary?subject to change without notice table 39-28. fifo write pointer sgm register base + 0x00d4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0000 flsc h3 statch3 0000 flsc h2 statch2 w reset0000000000000000 1514131211109876543210 r 0000 flsc h1 statch1 0000 flsc h0 statch0 w reset0000000000000000 figure 39-25. fifo write pointer (fifowp) field description 27 flsch3 fifo and datapath of channel 3 is being flushed. 0: fifo and datapath of channel 3 is ready 1: fifo and datapath of channel 3 is being flushed if and only if the fifo and datapath of channel 3 is re ady(flsch3=0), is it allowed to fill the fifo and start sound generation on channel 3 (set sgmctl.sogch3). ot herwise it will lead to unpredictable consequences. 26-24 statch3 operation status of channel 3. these bits indicate the current state of channel 3. see table 39-40 and table 39-41 for details of these states. 000: idle 001: playb 010: deadt 011: attk 100: sust 101: rels 110: nopt 111: n/a if and only the operation status is idle (statch3=000), is it allowed to start sound generation on channel 3 (set sgmctl.sogch3). otherwise it will l ead to unpredictable consequences. 19 flsch2 fifo and datapath of channel 2 is being flushed. 0: fifo and datapath of channel 2 is ready 1: fifo and datapath of channel 2 is being flushed if and only if the fifo and datapath of channel 2 is re ady(flsch2=0), is it allowed to fill the fifo and start sound generation on channel 2(set sgmctl.sogch2). otherwise it will lead to unpredictable consequences.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-27 preliminary?subject to change without notice 39.6.2.25 sgm interrupt control regi ster for fifo and dma (sgmicfd) the sgmicfd register enables and controls th e fifo interrupt and dma request functions. 18-16 statch2 operation status of channel 2. these bits indicate the current state of channel 2. see table 39-40 and table 39-41 for details of these states. 000: idle 001: playb 010: deadt 011: attk 100: sust 101: rels 110: nopt 111: n/a if and only if the operation status is idle (statch2=0 00), is it allowed to start sound generation on channel 2 (set sgmctl.sogch2). othe rwise it will lead to unpredictable consequences. 11 flsch1 fifo and datapath of channel 1 is being flushed. 0: fifo and datapath of channel 1 is ready 1: fifo and datapath of channel 1 is being flushed if and only if the fifo and datapath of channel 1 is re ady(flsch1=0), is it allowed to fill the fifo and start sound generation on channel 1(set sgmctl.sogch1). otherwise it will lead to unpredictable consequences. 10-8 statch1 operation status of channel 1. these bits indicate the current state of channel 1. see table 39-40 and table 39-41 for details of these states. 000: idle 001: playb 010: deadt 011: attk 100: sust 101: rels 110: nopt 111: n/a if and only if the operation status is idle (statch1=0 00), is it allowed to start sound generation on channel 1 (set sgmctl.sogch1). othe rwise it will lead to unpredictable consequences. 3 flsch0 fifo and datapath of channel 0 is being flushed. 0: fifo and datapath of channel 0 is ready 1: fifo and datapath of channel 0 is being flushed if and only if the fifo and datapath of channel 0 is re ady(flsch0=0), is it allowed to fill the fifo and start sound generation on channel 0 (set sgmctl.sogch0). ot herwise it will lead to unpredictable consequences. 2-0 statch0 operation status of channel 0. these bits indicate the current state of channel 0. see table 39-40 and table 39-41 for details of these states. 000: idle 001: playb 010: deadt 011: attk 100: sust 101: rels 110: nopt 111: n/a if and only if the operation status is idle (statch0=0 00), is it allowed to start sound generation on channel 0 (set sgmctl.sogch0). othe rwise it will lead to unpredictable consequences. field description
pxd20 microcontroller reference manual, rev. 1 39-28 freescale semiconductor preliminary?subject to change without notice table 39-29. sgm interrupt control register for dma and fifo sgm register base + 0x00d8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r flde ch3 flde ch2 flde ch1 flde ch0 0000 flie ch3 flie ch2 flie ch1 flie ch0 0000 w reset0000000000000000 1514131211109876543210 r ffie ch3 ffie ch2 ffie ch1 ffie ch0 feie ch3 feie ch2 feie ch1 feie ch0 foie ch3 foie ch2 foie ch1 foie ch0 fuie ch3 fuie ch2 fuie ch1 fuie ch0 w reset0000000000000000 figure 39-26. sgm interrupt control register for dma and fifo (sgmicdf) field description 31 fldech3 fifo level dma request enable for channel 3. enables a dma service request when the fifo level is below the watermark of channel 3. 30 fldech2 fifo level dma request enable for channel 2. enables a dma service request when the fifo level is below the watermark of channel 2. 29 fldech1 fifo level dma request enable for channel 1. enables a dma service request when the fifo level is below the watermark of channel 1. 28 fldech0 fifo level dma request enable for channel 0. enables a dma service request when the fifo level is below the watermark of channel 0. 27-24 reserved. 23 fliech3 fifo level interrupt request enable for channel 3. enables an interrupt request when the fifo level is below the watermark of channel 3. 22 fliech2 fifo level interrupt request enable for channel 2. enables the interrupt request when the fifo level is below the watermark of channel 2. 21 fliech1 fifo level interrupt request enable for channel 1. enables the interrupt request when the fifo level is below the watermark of channel 1. 20 fliech0 fifo level interrupt request enable for channel 0. enables the interrupt request when the fifo level is below the watermark of channel 0. 19-16 reserve d. 15 ffiech3 fifo full interrupt enable for channel 3. 14 ffiech2 fifo full interrupt enable for channel 2. 13 ffiech1 fifo full interrupt enable for channel 1. 12 ffiech0 fifo full interrupt enable for channel 0. 11 feiech3 fifo empty interrupt enable for channel 3.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-29 preliminary?subject to change without notice 39.6.2.26 sgm interrupt control register (sgmic) the sgmic register enables and controls the in terrupts associated with each sound channel. 10 feiech2 fifo empty interrupt enable for channel 2. 9 feiech1 fifo empty interrupt enable for channel 1. 8 feiech0 fifo empty interrupt enable for channel 0. 7 foiech3 fifo overflow interrupt enable for channel 3. 6 foiech2 fifo overflow interrupt enable for channel 2. 5 foiech1 fifo overflow interrupt enable for channel 1. 4 foiech0 fifo overflow interrupt enable for channel 0. 3 fuiech3 fifo underflow interrupt enable for channel 3. 2 fuiech2 fifo underflow interrupt enable for channel 2. 1 fuiech1 fifo underflow interrupt enable for channel 1. 0 fuiech0 fifo underflow interrupt enable for channel 0. sgm register base + 0x00dc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r toie 0000000 pdie ch3 pdie ch2 pdie ch1 pdie ch0 rdie ch3 rdie ch2 rdie ch1 rdie ch0 w reset0000000000000000 1514131211109876543210 r eori ech3 eori ech2 eori ech1 eori ech0 eoai ech3 eoai ech2 eoai ech1 eoai ech0 eoni ech3 eoni ech2 eoni ech1 eoni ech0 pcie ch3 pcie ch2 pcie ch1 pcie ch0 w reset0000000000000000 figure 39-27. sgm interrupt control register (sgmic) field description
pxd20 microcontroller reference manual, rev. 1 39-30 freescale semiconductor preliminary?subject to change without notice table 39-30. sgm interrupt control register field description 31 toie timeout interrupt enable for sgm. 30-24 reserved. 23 pdiech3 playback duration interrupt enable for channel 3 in wave mode. 22 pdiech2 playback duration interrupt enable for channel 2 in wave mode. 21 pdiech1 playback duration interrupt enable for channel 1 in wave mode. 20 pdiech0 playback duration interrupt enable for channel 0 in wave mode. 19 rdiech3 repeat duration interrupt enable for channel 3 in wave mode. 18 rdiech2 repeat duration interrupt enable for channel 2 in wave mode. 17 rdiech1 repeat duration interrupt enable for channel 1 in wave mode. 16 rdiech0 repeat duration interrupt enable for channel 0 in wave mode. 15 eoriech3 enable the interrupt of reaching the end of release phase in dds mode for channel 3. 14 eoriech2 enable the interrupt of reaching the end of release phase in dds mode for channel 2. 13 eoriech1 enable the interrupt of reaching the end of release phase in dds mode for channel 1. 12 eoriech0 enable the interrupt of reaching the end of release phase in dds mode for channel 0. 11 eoaiech3 enable the interrupt of reaching the end of attack phase in dds mode for channel 3. 10 eoaiech2 enable the interrupt of reaching the end of attack phase in dds mode for channel 2. 9 eoaiech1 enable the interrupt of reaching the end of attack phase in dds mode for channel 1. 8 eoaiech0 enable the interrupt of reaching the end of attack phase in dds mode for channel 0. 7 eoniech3 enable the interrupt at the end of inter-note no-output phase for channel 3 in dds mode. 6 eoniech2 enable the interrupt at the end of inter-note no-output phase for channel 2 in dds mode. 5 eoniech1 enable the interrupt at the end of inter-note no-output phase for channel 1 in dds mode.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-31 preliminary?subject to change without notice 39.6.2.27 sgm interrupt status regi ster for fifo and dma (sgmisfd) the sgmisfd register contains the dm a and fifo interrupt status of sgm. table 39-31. sgm interrupt status register for fifo and dma 4 eoniech0 enable the interrupt at the end of inter-not e no-output phase for channel 0 in dds mode. 3 pciech3 enable the interrupt when reaching the target number of note pulses count for channel 3 in dds mode. 2 pciech2 enable the interrupt when reaching the target number of note pulses count for channel 2 in dds mode. 1 pciech1 enable the interrupt when reaching the target number of note pulses count for channel 1 in dds mode. 0 pciech0 enable the interrupt when reaching the target number of note pulses count for channel 0 in dds mode. sgm register base + 0x00e0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 00000000 flfc h3 flfc h2 flfc h1 flfc h0 0000 w reset0000000011110000 1514131211109876543210 rfffc h3 fffc h2 fffc h1 fffc h0 fefc h3 fefc h2 fefc h1 fefc h0 fofc h3 fofc h2 fofc h1 fofc h0 fufc h3 fufc h2 fufc h1 fufc h0 w reset0000111100000000 figure 39-28. sgm interrupt status register for fifo and dma(sgmisfd) field description 31-24 reserved. 23 flfch3 fifo programmable level flag for channel 3. note the dma clears this flag when servicing a dma request 22 flfch2 fifo programmable level flag for channel 2. note the dma clears this flag when servicing a dma request 21 flfch1 fifo programmable level flag for channel 1. note the dma clears this flag when servicing a dma request 20 flfch0 fifo programmable level flag for channel 0. note the dma clears this flag when servicing a dma request 19-16 reserved. field description
pxd20 microcontroller reference manual, rev. 1 39-32 freescale semiconductor preliminary?subject to change without notice 39.6.2.28 sgm interrupt status register (sgmis) the sgmis register contains the status of the interrupts associated wi th each sound channel. 15 fffch3 fifo full flag for channel 3. 14 fffch3 fifo full flag for channel 2. 13 fffch3 fifo full flag for channel 1. 12 fffch3 fifo full flag for channel 0. 11 fefch3 fifo empty flag for channel 3. 10 fefch2 fifo empty flag for channel 2. 9 fefch1 fifo empty flag for channel 1. 8 fefch0 fifo empty flag for channel 0. 7 fofch3 fifo overflow flag for channel 3. 6 fofch2 fifo overflow flag for channel 2. 5 fofch1 fifo overflow flag for channel 1. 4 fofch0 fifo overflow flag for channel 0. 3 fufch3 fifo underflow flag for channel 3. 2 fufch2 fifo underflow flag for channel 2. 1 fufch1 fifo underflow flag for channel 1. 4 fufch0 fifo underflow flag for channel 0. field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-33 preliminary?subject to change without notice table 39-32. sgm interrupt status register sgm register base + 0x00e4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tof0000000 pdfc h3 pdfc h2 pdfc h1 pdfc h0 rdfc h3 rdfc h2 rdfc h1 rdfc h0 ww1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 1514131211109876543210 reor fch3 eor fch2 eor fch1 eor fch0 eoaf ch3 eoaf ch2 eoaf ch1 eoaf ch0 eon fch3 eon fch2 eon fch1 eon fch0 pcfc h3 pcfc h2 pcfc h1 pcfc h0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 39-29. sgm interrupt status register (sgmis) field description 31 tof timeout flag. 30-24 reserved. 23 pdfch3 playback duration over status for channel 3 in wave mode. 22 pdfch2 playback duration over status for channel 2 in wave mode. 21 pdfch1 playback duration over status for channel 1 in wave mode. 20 pdfch0 playback duration over status for channel 0 in wave mode. 19 rdfch3 repeat duration over flag for channel 3 in wave mode. 18 rdfch2 repeat duration over flag for channel 2 in wave mode. 17 rdfch1 repeat duration over flag for channel 1 in wave mode. 16 rdfch0 repeat duration over flag for channel 0 in wave mode. 15 eorfch3 flag of reaching the end of at release phase in dds mode for channel 3. 14 eorfch2 flag of reaching the end of at release phase in dds mode for channel 2. 13 eorfch1 flag of reaching the end of at release phase in dds mode for channel 1. 12 eorfch0 flag of reaching the end of at release phase in dds mode for channel 0.
pxd20 microcontroller reference manual, rev. 1 39-34 freescale semiconductor preliminary?subject to change without notice 39.6.2.29 i2s enable register (i2sen) the i2sen register enables the i2s operations 11 eoafch3 flag of reaching the end of at attack phase in dds mode for channel 3. 10 eoafch2 flag of reaching the end of at attack phase in dds mode for channel 2. 9 eoafch1 flag of reaching the end of at attack phase in dds mode for channel 1. 8 eoafch0 flag of reaching the end of at attack phase in dds mode for channel 0. 7 eonfch3 flag of reaching the end of the inter-note no-output phase for channel 3 in dds mode. 6 eonfch2 flag of reaching the end of the inter-note no-output phase for channel 2 in dds mode. 5 eonfch1 flag of reaching the end of the inter-note no-output phase for channel 1 in dds mode. 4 eonfch0 flag of reaching the end of the inter-note no-output phase for channel 0 in dds mode. 3 pcfch3 flag of reaching the target number of note pulses count for channel 3 in dds mode. 2 pcfch2 flag of reaching the target number of note pulses count for channel 2 in dds mode. 1 pcfch1 flag of reaching the target number of note pulses count for channel 1 in dds mode. 0 pcfch0 flag of reaching the target number of note pulses count for channel 0 in dds mode. sgm register base + 0x00e8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r00000000000 srst 000 ien w reset0000000000000000 figure 39-30. i2s enable register (i2sen) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-35 preliminary?subject to change without notice table 39-33. i2s enable register 39.6.2.30 i2s control register (i2sctl) the i2sctl register controls i2s operations table 39-34. i2s control register field description 31-5 reserved. 4 srst i2s module soft reset. writing 1 to this bit soft resets the module logic. memory mapped registers are not be affected. 0: normal function 1: soft reset asserted 3-1 reserved. 0 ien i2s enable. 0: i2s interface disabled 1: 2s interface enabled sgm register base + 0x00ec 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0000000000000000 w reset0000000000000000 1514131211109876543210 r fifoth 0000 ace n acse l chs el 0 pm 00 psyn c pol w reset0000000000000000 figure 39-31. i2s control register (i2sctl) field description 31-15 reserved. 15-14 fifoth i2s fifo threshold level. after accumulating the number of data specified by this number, the i2s starts sending data out ofthe interface. 00: threshold is 1, start as soon as data is received from sgm 01: threshold is 2, start after 2 data units are received from sgm 10: threshold is 3, start after 3 data units are received from sgm 11: threshold is 4, start after 4 data units are received from sgm 13-10 reserved. 9 acen auxiliary clock (mclk). 0 auxiliary clock disabled. 1 auxiliary clock enabled. 8 acsel auxiliary clock (mclk) selection. 0: auxiliary clock is 256 times the sampling clock 1: auxiliary clock is 512 times the sampling clock
pxd20 microcontroller reference manual, rev. 1 39-36 freescale semiconductor preliminary?subject to change without notice 39.6.2.31 i2s output data format control register (i2sdfc) the i2sdfc register controls the i2s output data format. table 39-35. i2s output data format control register 7 chsel channel selection for mono pcm mode. 0: left mixer data will be selected for i2s 1: right mixer data will be selected for i2s 6 reserved. 5-4 pm protocol mode. 00: philips protocol mode (stereo) 01: msb justify mode (stereo) 10: lsb justify mode (stereo) 11: pcm mode (mono) 3-2 reserved. 1 psync active edge of frame sync 0: frame sync is active high 1: frame sync is active low 0 pol clock polarity control for data transfer 0: data & frame sync clocked on rising edge 1: data & frame sync clocked on falling edge sgm register base + 0x00f0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r00000000000 fsl w reset0000000000000000 1514131211109876543210 r000 msbf 0 bso 00 odf 000 idf w reset0000000000000000 figure 39-32. i2s output data format control register (i2sdfc) field description 31-21 reserved. 20-16 fsl frame sync length. these bits specify the frame sync length for pcm mode. the actual number of frame synch length fsl+1, so the default value is 1. 15-13 reserved. field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-37 preliminary?subject to change without notice 12 msbf msb first. this bit represents what data is to be sent first as out put on i2s interface. for formats where bit stuffing is applicable, this option will be applied only after the bit stuffing is already done 0: send most significant bit out first 1: send least significant bit out first 9-8 bso bit stuffing option. this option is only used when the output data format is bigger than the input data format. in this case additional data is stuffed to the outgoing data. 000: append 0?s after least significant bit (lsb) 001: append most mignificant byte s (msb) after lsb i.e repeat data 010: prepend sign bit - most significant bit (msb) before msb 011: prepend 0?s before msb others: reserved note: these bits have different implications for different protocol modes (pm). table 39-36 shows the details. 7-6 reserved. 5-4 odf output data format 00: 16 bits per channel 01: 32 bits per channel 10: 24 bits per channel 11: reserved 3-1 reserved. 0 idf input data format i. e bits per channel 0: 16 bit per channel 1: reserved table 39-36. output protocol mode (formats) supported by i2s protocol mode interpretation philips mode data is always most significant bit justified. 000 : append 0?s after least significant bit (lsb) 001 : append most significant bytes (msb) after lsb i.e repeat data 010 : prepend sign bit - most significant bit (msb) before msb 011 : prepend 0?s before msb others : reserved msb justify mode data is always most significant bit justified. 000 : append 0?s after least significant bit (lsb) 001 : append most significant bytes (msb) after lsb i.e repeat data others : reserved lsb justify mode data is always least significant bit justified. 000 : append 0?s after least significant bit (lsb) note: reserved for lsb justified mode 001 : append most significant bytes (msb) after lsb i.e repeat data note: reserved for lsb justified mode 010 : prepend sign bit - most significant bit (msb) before msb 011 : prepend 0?s before msb 100 : prepend appropriate most significant by tes (msb) before msb i.e repeat data others : reserved field description
pxd20 microcontroller reference manual, rev. 1 39-38 freescale semiconductor preliminary?subject to change without notice 39.6.2.32 i2s clock prescal er register (i2sprs) the i2sprs register controls the cl ock prescaler values that govern the bit and auxiliary clock frequencies. table 39-37. i2s clock prescaler register 39.6.2.33 i2s interrupt control register (i2sintc) the i2sintc register controls the interrupts of i2s interface. pcm mode data is always most significant bit justified. 000 : append 0?s after least significant bit (lsb) 001 : append most significant bytes (msb) after lsb i.e repeat data 010 : prepend sign bit - most significant bit (msb) before msb 011 : prepend 0?s before msb 100 : prepend appropriate most significant by tes(msb) before msb i.e repeat data others : reserved sgm register base + 0x00f4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r acpsclr w reset0000000000000000 1514131211109876543210 r i2spsclr w reset0000000000000000 figure 39-33. i2s clock prescaler register (i2sprs) field description [31:16] acpsclr auxiliary clock pre-scaler. this value needs to be synchronised with the sgm prescaler value and the prescaler value programmed for on i2spsclr after accounting for data stuffing and data repetition on the left and right channels. 15-0 i2spsclr i2s clock pre-scaler. these bits specify the divide factor for the system cl ock to achieve the bit clock. this value should be synchronised with the prescaler values programmed for sgm after accounting for data stuffing and data repetition on the left and right channels. table 39-36. output protocol mode (formats) supported by i2s (continued) protocol mode interpretation
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-39 preliminary?subject to change without notice table 39-38. i2s enable register 39.6.2.34 i2s status register (i2sst) the i2sints register shows the status of the i2s interface. sgm register base + 0x00f8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tsfe n 00000 fofe fufe 00000 cple n 00 w reset0000000000000000 1514131211109876543210 r0000000000000000 w reset0000000000000000 figure 39-34. i2s interrupt control register (i2sintc) field description 31 tsfen i2s transfer error interrupt enable. 31-26 reserved. 25 fofe i2s fifo overflow enable. 24 fufe i2s fifo underflow enable. 18 cplen i2s complete interrupt enable. 15-0 reserved. sgm register base + 0x00fc 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rtsfe00000foffuf00000cpl00 ww1c w1c reset0000000000000000 1514131211109876543210 r00000000 fifost 000bsy w reset0000000000000000 figure 39-35. i2s status register (i2sst)
pxd20 microcontroller reference manual, rev. 1 39-40 freescale semiconductor preliminary?subject to change without notice 39.7 functional description the sound generator module creates sound by clocki ng pcm sound samples out of up to four sound source channels, mixing these together and sending the output to either a mono pwm output or to a stereo i2s interface. the sound channels can operate in one of two modes depending on whether a wavetable (dds mode) or complete pcm str eam (wave) is required. dds mode includes a volume envelope that shapes the playback of the wavetable. the volume in wave mode is determined by the volume set in the mixer for that channel. 39.7.1 wave mode in wave mode, the pcm data is stored in memory ex ternal to the sgm (for ex ample ram or flash). each sample is fetched using the edma th en fed to the sgm which promotes it to 16 bits per sample using its sample format converter (sfc). samples should be in two?s comple ment signed format. the channel fifo is used to buffer the incoming data and then deliver the samples at the required clock rate to the mixer. as a sample is fetched from the fifo and played by the channel its location in the fifo will be replaced by a newer incoming sample. there are two options for playback: ? single shot mode. in this mode the channel ?plays? the entire s ource wave once. the duration of the playback is controlled by the pl ayback timing configuration register ( section 39.6.2.11, playback timing configuration re gister for channel 3(ptcch3) ) which determines the number table 39-39. i2sst field descriptions field description 31 tsfe i2s transfer error. if the i2s fifo is empty but the i2s requests dat a then transfer error interrupt will be raised. 31-26 reserved. 25 fof i2s fifo overflow. interrupt indicating the fifo overflow. th e i2s soft reset can clear this flag. 24 fuf i2s fifo underflow. interrupt indicating the fifo underflow. t he i2s soft reset ca n clear this flag. 18 cpl i2s complete interrupt indicating all data is transferred after receiving end of sequence from the sgm. 15-8 reserved. 7-4 fifost fifo status. this field specifies the amount of data currently residing in the i2s fifo. cleared on soft reset, or when the i2s fifo gets emptied. 3-1 reserved. 0 bsy i2s busy. the i2s interface is busy. cleared on soft re set or when module completes outputing data.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-41 preliminary?subject to change without notice of samples in the source wave. see figure ? for a simple example wher e the source wave consists of 5 samples. figure 39-36. single shot mode playback ? repeat mode. in this mode the channel ?plays? th e entire source wave then waits for a deadtime ( section 39.6.2.12, dead time configurati on register for channel 3(dtcch3) ) during which it produces samples of value 0 then ?plays? the entire wave again. the number of repeats is programmable in the rep eat number register ( section 39.6.2.13, repeat number configuration register for channel 3(rncch3) ). in the last iteration, the dead time duration is removed and the repeat finishes at the end of playback durati on. endless repetition can be produced by setting the repeat number to all 0. see figure for an example where the five sa mple source wave is repeated three times. figure 39-37. repeat mode playback the input fifo (256 ? 16 bit) for each channel is used to buffe r the incoming pcm audio sample stream. see figure 39-38 . the status of the fifo such as overflow and underflow is reported in the fifo and dma status register ( section 39.6.2.27, sgm interrupt status re gister for fifo and dma (sgmisfd) ) which can also raise interrupts if required. configure the in terrupt requirements us ing the fifo and dma interrupt control register ( section 39.6.2.25, sgm interrupt contro l register for fifo and dma (sgmicfd) ). note for correct operation the edma tran sfer descriptor must match the playback length of the wave. s0 s1 s2 s3 s4 channel clock sample output s0 s1s2s3 s4 s0s1 s2 s3 s4 s0 s1 s2 s3 s4 0x0000 0x0000 playback=5 playback=5 playback=5 deadtime=3 deadtime=3 repeat number=3
pxd20 microcontroller reference manual, rev. 1 39-42 freescale semiconductor preliminary?subject to change without notice figure 39-38. pcm sample flow for wave mode 39.7.1.1 state machine of sgm channel in wave mode the sgm manages the operation of th e channel using a state machine. the current state of the machine for each channel is found in the sgmst register. see figure and table 39-40 for details of the state machine operation. figure 39-39. wave mode state machine - by function table 39-40. wave mode state machine source state destination state transfer condition description idle/stop playb a if sog is asserted, samples will fetched from fifo and the playback starts. wave 0 wave 1 wave 2 memory system (ram, flash) fifo0 mixer fifo1 fifo2 fifo3 ch0 ch1 ch2 ch3 edma transfer edma tcdx start address edma transfer edma tcdy start address the sgm makes a dma request to the associated channel when the fifo falls below the watermark level playb idle/stop deadt a b d c e
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-43 preliminary?subject to change without notice 39.7.2 dds mode in dds mode the sound is not genera ted by playing back a full wave str eam, instead it is synthesized from a wavetable. this section expl ains the operation of dds mode. 39.7.2.1 dds concept a sound can be described by 3 different attributes: pitch, volume and timbre. ? the pitch depends on the frequency of the wave. ? the volume depends on the amplitude of the wave. ? the timbre depends on the shape of the wave. in ge neral, each instrument ha s its individual timbre, e.g. piano, guitar, violin, drum, voice. direct digital synthesis reli es on the fact that the timbre of a s ound does not vary greatly for relatively large changes in frequency and so a single table cont aining samples that represen t the timbre of the sound may be played back at different fr equencies rather than having to stor e individual waves for each required pitch. the characteristic envelope of the sound may change as the pitch changes. for example higher pitched sounds may have a faster at tack and shorter sustain than lowe r pitches. dds mode accounts for this difference by allowing the user to configure the volume envelope for the wavetable independently of the samples in the table. the envelope has three phases: ? attack: the volume is increasing from 0 or the previous final volume value ? sustain: the volume remains constant ? release: the volume is d ecreasing to a final value each phase is configurable for duration and for the ph ases where the volume is ch anging the type of change and rate of change is controllable. playb idle/stop b if sog is deasserted, the playback will be stopped immediately. alternatively, when the playback ends and no-repeat mode is selected, the playback will be stopped. playb deadt c if repeat mode is selected then when playback ends at the end of the current repeat, the sgm will enter the deadtime phase and give samples of 0x0000. deadt playb d if repeat mode is selected then when the deadtime phase ends and the channel has not reached the target numb er of repeats then another playback will begin. deadt idle e if sog is deasserted, the deadtime will be stopped immediately. alternatively, when the deadtime ends and the channel reaches the target number of repeat then the playback will stop. table 39-40. wave mode state machine (continued)
pxd20 microcontroller reference manual, rev. 1 39-44 freescale semiconductor preliminary?subject to change without notice 39.7.2.2 wavetable initialization in dds mode , the wavetable needs to be loaded into the ch annel fifo by the system (typically the edma or cpu). the fifo then works as a local memory buffer which the dds uses to synthesize the sound. unlike wave mode the samples remain in memory until the wavetable is replaced. 39.7.2.3 generating the tone it is unlikely that a complete tone of suitable durat ion may be contained in the wavetable, therefore each tone is generated by playing the samp les in the wavetable c ontinually until the end of the volume envelope is reached. the rate at which the samples are fed from the wavetable depends on the clock for the channel and the increment size for the wavetable address counter ( section 39.6.2.5, dds configuration register for channel 3 (ddsch3) ) and clock for each channel. the incr ement size affects the sequence of the samples as well as the rate at which new samples are selected from the wavetabl e so it generally remains fixed for a given tone. the pitch of the tone is ther efore typically changed by increasing or decreasing the clock to the channel. since the channel clock also af fects the envelope timing it is usual to change the envelope parameters when ch anging the pitch of the tone. the duration of each tone is determined by the volum e envelope. the attack pha se controls the maximum amplitude of the sound, the sustain pha se determines how long it stays at that amplitude and the release phase controls the final amplitude of the sound. the attack and re lease phases are both programmable for length through the rate at which they change the am plitude and how much cha nge is made at a time. for the attack phase the atta ck configuration register ( section 39.6.2.6, envelope configuration register of attack phase for channel 3 (ecrach3) ) and the sgm confi guration register ( section 39.6.2.2, sgm configuration re gister (sgmcfg) ) control the behavior. the attack may use linear or exponential interpolation as configured in sg mcfg. for linear mode the channel clock increments a counter that causes an increase in amplitude of ecrachn.atksl when it re aches a value of ecrachn.atksc. when the output reaches the amplitude specified by ecrachn.atkt the attack phase is over. for exponential mode the step size is c ontrolled by the atkt bitfield su ch that each step increases in magnitude in an exponential fashion. in the sustain phase the duration is simply determin ed by the number of channe l clock ticks specified by the sust bitfiled of the sust ain configuration register ( section 39.6.2.8, envelope c onfiguration register of sustain timing for channel 3 (ecrsch3) ). for the release phase the att ack configuration register ( section 39.6.2.7, envelope c onfiguration register of release phase for channel 3 (ecrrch3) ) and the sgm configuration register ( section 39.6.2.2, sgm configuration re gister (sgmcfg) ) control the behavior. the release may use linear or exponential interpolation as configured in sg mcfg. for linear mode the channel clock increments a counter that causes a decrease in amplitude of ecrrchn.relsl when it reac hes a value of ecrrchn.relsc. when the output reaches the amplitude specified by ecrrchn.relt the release phase is over. for exponential mode the step size is c ontrolled by the relt bitfield such that each step decreases in magnitude in an exponential fashion. see figure and figure
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-45 preliminary?subject to change without notice figure 39-40. asr envelope figure 39-41. asr envelope with linear attack and exponential release the channel allows repetition of the volume envelope ( section 39.6.2.10, target note pulse count for channel 3 (tpcch3) ) and the insertion of a delay betw een repetitions of the wavetable ( section 39.6.2.9, inter-note no-output phase timing for channel 3 (ntch3) ). volume time duration attack release max_volume target final volume sustain
pxd20 microcontroller reference manual, rev. 1 39-46 freescale semiconductor preliminary?subject to change without notice figure gives an example of the dds mode in action. figure 39-42. dds mode for one channel 39.7.2.4 updating the configuration buffers in dds mode, the configuration registers for dds mode, sgmcfg (upper word), ddsch3/2/1/0, ecrach3/2/1/0, ecrrch3/2/1/0, ec rsch3/2/1/0, ntch3/2/1/0, tpcch3/2/1/0, are equipped with hardware buffers. if sound generation hasn?t started, the buffer values w ill be updated from the conf iguration registers every ips clock cycle. when a note is being generated, the values of the c onfiguration registers are copied to the buffers when the following sequence is detected: 1. configure the 1st note before starting the generation. 1. setting the start of generati on bit (sogchx bit in sgmctl). 2. buffers are updated at next ips clock. 3. synchronous reload occurs : ? at the end of release phase if the no-output phase insertion is disabled. ? at the end of no-output phase, if the no-output phase insertion is enabled. up to the next reload, configura tion registers and buffers can hold di fferent values. the following figure shows an example (not to scale). no-output-time volume time duration inter-note tone(n) tone(0) tone(1)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-47 preliminary?subject to change without notice figure 39-43. updating the dds configuration buffer 39.7.2.5 state machine of sgm channel in dds mode the sgm manages the operation of th e channel using a state machine. the current state of the machine for each channel is found in the sgmst register. see figure and table 39-41 for details of the state machine operation. figure 39-44. dds-mode state machine - by function table 39-41. dds mode state machine source state destination state transfer condition description idle/stop attk a if the sog is asserted, the asr envelope will enter the attack phase. attk sust rels nopt idle/stop b a c d e f g h i j
pxd20 microcontroller reference manual, rev. 1 39-48 freescale semiconductor preliminary?subject to change without notice 39.7.3 sgm architecture the sgm consists of a clock conf iguration logic, ips interface, four identical sound channels, a re-sampling block, mixer with volume control, pw m output and i2s interface. refer to for a block diagram of the sgm. the followi ng sections discuss each in turn. 39.7.4 sgm clocking the sgm uses the following clocks: source clocks: ? system clock ? sgm module clock (maximum fre quency half the system clock) attk idle/stop b the generation of the sound can be stopped by deasserting the sog anytime. attk sust c if the asr envelope reach the target volume of attack phase, sustain phase will be entered. sust idle/stop d the generation of the sound can be stopped by deasserting the sog anytime. sust rels e when the target sustain timing is reached, the release phase will be entered. rels idle/stop f the generation of the sound can be stopped by deasserting the sog anytime.or if the no-output phase is disabled, the note pulse count is enabled and the target note pulse number is reached, the idle phase will be entered. rels nop g if the asr envelope reach the target volume of release phase and the no-output phase is enabled, the no-output phase will be entered. rels attk h if the asr envelope reach the target volume of release phase and the no-output phase is disabled, the no-output phase will be entered. nopt idle/stop i the generation of the sound can be stopped by deasserting the sog anytime. or when the target note pulse number is reached (if the target note pulse count is enabled), the generation ends. nopt attk j when the target no -output timing is reached, the attack phase will be entered if the target note pulse number isn?t reached or disabled. table 39-41. dds mode state machine (continued) source state destination state transfer condition description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-49 preliminary?subject to change without notice generated clocks: ? resampling clock -- used to resample the data from all the 4 channels with the same expected sample rate. note in wave mode, the pcm data from 4 ch annels should have the same sample rates. use the sgmctl[wavclks] bit to select the resample clock as the channel clock of all wave -mode channels. in dds m ode, the reference clock for each dds can be different. before mixing the channels together, they should be re-sampled by the expected sample rate. ? ch0_clk - used to clock the channel 0. ? ch1_clk - used to clock the channel 1. ? ch2_clk - used to clock the channel 2. ? ch3_clk - used to clock the channel 3. ? pwm_clk - used to clock the pwm block. ? ton_clk - used to clock the rate of change of mixer output with pwm. 39.7.5 channel controller there are four channels available in the sgm. each channel consists of: ? a dds controller with an asr envelope controller ? a sample format converter (sfc) ? volume control logic 39.7.5.1 dds controller the dds controller produces dds (w avetable synthesis) using an accumulator, the channel fifo and a volume control managed by th e envelop controller. see figure 39-45. dds architecture in sgm
pxd20 microcontroller reference manual, rev. 1 39-50 freescale semiconductor preliminary?subject to change without notice the 16-bit accumulator is incremente d by the channel clock and generates the address to read the samples from the fifo. only the upper 8 bits are used to se lect the address to the fi fo. the ddsf value provides the increment of the 16-bit accumulator and so can be used to determine both the frequency of change of sample as well as the sequence of samples: ? a value of 0x0100 will output sequential samples from the wavetable at a rate of one per dds clock cycle ? a value of 0x0200 will output ev ery second sample from the waveta ble at a rate of one per dds clock cycle ? a value of 0x0001 will output sequential samples from the wavetable at a rate of one every 256 dds clock cycles ? a value of 0x00c0 will output the sequence samp le 0, sample 1, sample 2, sample 3, sample 3, sample 4, sample 5, sample 6, sample 7, sa mple 7 and so on at the dds clock rate since only the upper 8 bits of the accumulator are used to addre ss the wavetable, the sample rate is: the repetition frequency of the wavetable contents is given by: fwave = fddsclk/ddsf eqn. 39-1 39.7.5.2 asr envelope controller the sgm provides a simple, configur able asr envelope, which is a simplified adsr envelope. see figure . the envelope controller controls the volume of each sample output fr om the dds controller. 39.7.5.3 sample format converter in wave mode, linear mono pcm data coded in 8-bit, 12-bit and 16-bit are supported. the sample format converter (sfc) converts data coded in 8 or 12 bit into 16-bit linear pcm data (represented by two?s complement). 39.7.5.4 volume control the volume controller is used to adjust the volu me of the sound. for each ch annel, the volume can be controlled individually. a fixed-point multiplier is applied to each channel to compute the required sample value for the resampler and mixer. f ddsout f ddsclk 2 16 -------------- - ddsf ? =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-51 preliminary?subject to change without notice for wave mode the volume is directly controlled by the volume control re gister for each channel. for dds mode, the volume is controlled by the asr envelope controller. figure 39-46. volume controller for one channel 39.7.6 re-sampling block the re-sampling block is used to unify the sample ra tes for all channels before entering the mixers. for dds mode, different sample clocks can be used for each channel and the re-sampling clock can be used to choose the current sample value on each channel as its output. for wave mode, the algorithm for src(sample rate conversion) would be very complicated with linear /cubic interpolation and therefore all wave mode channels mu st share a sample clock. 39.7.7 mixer the mixers are used to mix the data from the four channels together and generate the pcm outputs for the external audio dac and/or pwm (as the duty). two mixers, right mixe r and left mixer, are provided to generate the pcm data for 2 output channels: channel-r and channel-l. each mixer can be configured to mix any 1 to 4 of all 4 input channels togeth er. consider, for example, channel-0 and channel-1 in wave m ode and channel-2 and channel-3 in dds mode. the left mixer can be configured to mix channel-0 and ch annel-3 together while the right mixer can be configured to mix channel-1and channel-2 together. the mixer implements an arithmetic add for all the 4 input data (represented by 2' s complement) and a division with the rule below: if 1 channel is selected, division by 1; if 2 channels are selected, division by 2; if 3channels are selected, division by 4;
pxd20 microcontroller reference manual, rev. 1 39-52 freescale semiconductor preliminary?subject to change without notice if 4 channels are selected, division by 4; 39.7.8 i2s interface it is possible to select either pwm or i2s options for the output of the mixed sample data. the output option chosen does not affect the hardware or process for creating the mixed sound. this section describes the i2s block. 39.7.8.1 features the i2s interface has the following features: ? synchronous master mode support only ? output sample support ? 16-bit per channel ? 32-bit per channel ? 16-bit encapsulated in 32-bit ? same data can be repeated on the both left and right channels ? supported protocol modes ? philips (stereo) ? i2s msb justify (stereo) ? i2s lsb justify ? pcm (mono) ? for pcm mode ? only 16-bit input a udio data is supported ? output data supported format is 16-bit or 16-bit extended 32-bit ? programmable frame sync width of 1 to up to 13-bit clocks i.e. support for long and short frame synchro ? for extended bit formats, following data repetition options are supported ? append sign bits (for lsb justified modes) ? repeat msbits (for msb justified modes) ? stuff 0's (all extended modes) ? stuff 1's (all extended modes) ? additional clock output port support with programmable frequency of ? 256 frame clock ? 512 frame clock ? programmable polarity for clock, da ta and frame synchronisation signals ? 16-bit pre-scaler to support different sck clock frequency ? 8 word deep (32-bit wide) fifo for buffering audio data output data ? programmable fifo thresholds to start i2s data transfer
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-53 preliminary?subject to change without notice ? fifo underrun and transfer complete interrupts 39.7.8.2 clock choices when no dedicated clock sources are provided for the sample rate of 44.1/22.05/11.025 khz and 48/24/8khz on this device, the solution below is used to minimize the sample rate variation. ? sgm prescalers will be programmed in such a way, that its sampling frequenc y is always slightly higher than i2s ? once enabled, i2s will keep asking for data fr om sgm. i2s maintains the actual sample rate control, so its prescaler should be accurately programmed ? an underrun (i2s needing data, but sgm not ab le to process that fast) will never happen 39.7.8.3 i2s block diagram figure 39-47. i2s block diagram 39.7.8.4 supported protocol modes this section describes the i2s mode s supported by the interface. configur ation of the protocol modes are done using the control and output data format registers ( section 39.6.2.30, i2s control register (i2sctl) and section 39.6.2.31, i2s output data form at control register (i2sdfc) ). sgm ips logic i2s bus sgm logic sgm clocking logic side band signal i2s master interface i2s master logic i2s clock prescaler configuration signals for i2s system clk i2s fifo
pxd20 microcontroller reference manual, rev. 1 39-54 freescale semiconductor preliminary?subject to change without notice 39.7.8.4.1 philips mode figure 39-48. philips mode 16/32-bit figure 39-49. philips mode 24-bit sck fs do msb transmission reception may be 16-bit, 32-bit lsb msb channel left channel right sck fs do transmission reception 8-bit remaining channel left 32-bit channel right msb lsb 0 forced 24-bit data
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-55 preliminary?subject to change without notice figure 39-50. philips mode 16-bit extended to 32-bit 39.7.8.4.2 msb justify mode figure 39-51. 16/32 bit sck fs do transmission reception 16-bit remaining channel left 32-bit channel right msb lsb 0 forced 16-bit data sck fs do msb transmission reception may be 16-bit, 32-bit lsb msb channel left channel right
pxd20 microcontroller reference manual, rev. 1 39-56 freescale semiconductor preliminary?subject to change without notice figure 39-52. 24-bit extended to 32-bit figure 39-53. 16-bit extended to 32-bit sck fs do transmission reception 8-bit remaining channel left 32-bit channel right msb lsb 0 forced 24-bit data sck fs do transmission reception 16-bit remaining channel left 32-bit channel right msb lsb 0 forced 16-bit data
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-57 preliminary?subject to change without notice 39.7.8.4.3 lsb justify mode figure 39-54. 16/32bit figure 39-55. 24-bit extended to 32-bit sck fs do msb transmission reception may be 16-bit, 32-bit lsb msb channel left channel right sck fs do transmission reception 8-bit remaining channel left 32-bit channel right 0 forced 24-bit data lsb lsb
pxd20 microcontroller reference manual, rev. 1 39-58 freescale semiconductor preliminary?subject to change without notice figure 39-56. 16-bit extended to 32-bit sck fs do transmission reception 16-bit remaining channel left 32-bit channel right 0 forced 16-bit data lsb lsb
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-59 preliminary?subject to change without notice 39.7.8.4.4 pcm mode figure 39-57. 16-bit extended to 32-bit figure 39-58. 32-bit sck fs short frame do msb 16bit lsb msb fs long frame upto 13-bit sck do msb lsb 16-bit data fs short frame fs long frame upto 13-bit
pxd20 microcontroller reference manual, rev. 1 39-60 freescale semiconductor preliminary?subject to change without notice 39.7.9 pwm output as an alternative to the i2s interface it is possible to have the output of one of the mixer channels act as the source of the duty cycle of a pwm. the duty cycle of the pwm ch anges with each output sample and the output signal can be filtered and in tegrated to provide a low cost dac. figure 39-59. pwm block the pwm output is designed to provide a simple digital output that can be filtered to reproduce the analog output of either one of the mixe r channels. reproducing the highest quality sound is not possible for the pwm due to the very high pwm frequencies that would be required. therefore fo r most applications the pwm is limited to a lower quality sound output. when the pwm output is enabled the i2s is disabled. the mixed data values from either the left mixer or the right mixer are used as the count of the duty cycle of the pwm (pwmchs bit in section 39.6.2.2, sgm configurat ion register (sgmcfg) ). the total length of the pwm count is defined by the pwmcr[ pwmf] field and the frequency of the pwm is defined by the pwm clock ( section 39.6.2.18, pwm configurat ion register (pwmcr) ). a 100% duty cycle (continually high) wi ll be generated if the value of the mixed data is higher than the pwmf count. the amplitude of the filtered output is determined by the duty cycle of the pwm. the frequency of the output is decide d by the channel sample rate. the pwm frequency is generate d by pwmf and the pwm clock. it can be calculated as: the duty cycle of pwm signal is calculated as follows: ? if [mixer_out] > [pwmf]: duty cycle =100% ?if 0 ? [mixer_out] ? [pwmf]: duty cycle = [mixer_out] / ([pwmf]+1) m u x mixer left channel mixer right channel pwm counter ton clock generator pwm channel select pwm_clk pwmoa pwmo 0 1 sgmctl.os ton_clk pwmcr.pwmf pwmcr.tonf pwm_out & composite_out f pwm f pwmclk pwmf ?? 1 + ?? ------------------------------------- =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-61 preliminary?subject to change without notice figure 39-60. generation of the pwm composite output signal 39.8 interrupts and dma all of the sgm interrupt sources ar e anded together into a single inte rrupt vector. there are interrupt sources related to the operation of each channel, the fifo and dma status and the i2s interface. the channel interrupts and dma are as configured and recorded in the sgm interrupt registers ( section 39.6.2.26, sgm interrupt control register (sgmic) and section 39.6.2.28, sgm interrupt status register (sgmis) ). enable the dma for wave mode channels using the sgmicdf[fldechn] bits. the status flags sgmisdf[flfchn] indicate that a dm a request has been made. note th at the dma will clear this bit when it acknowledges the request. there is a general timeout flag to indicate expiration of ti meout counter. the counter is enabled using the sgmctl[toe] bit and the interr upt control flag sgmic[toie]. interrupt sources when channels are in wave mode: ? playback duration over (end of each playback cycle) ? repeat duration over interrupt sources when channels are in dds mode: ? end of release phase ? end of attack phase ? end of inter-note no-output phase ? end of pulse count the fifo and dma interrupts are c onfigured and recorded in the dm a and fifo interrupt registers ( section 39.6.2.25, sgm interrupt control regi ster for fifo and dma (sgmicfd) and section 39.6.2.27, sgm interrupt status regi ster for fifo and dma (sgmisfd) )
pxd20 microcontroller reference manual, rev. 1 39-62 freescale semiconductor preliminary?subject to change without notice the fifo interrupts are as follows: ? fifo programmable level flag ( note that this flag is automa tically cleared by an active dma) ? fifo full flag ? fifo empy flag ? fifo underflow flag ? fifo overflow flag 39.9 initialization and application information this section provides some use cases to give some basic direction to a user on how to initialize and configure the sgm module. 39.9.1 wave mode use cases the typical use cases fo r this function are: ? speech (single shot mode) ? alarm sound (repeat mode) 39.9.1.1 speech 39.9.1.1.1 description the application requires to playback a pcm wave wh ich can have a duration up to 10s (5s typical). the quality can go up to 48khz (22khz t ypical) sampling rate and the samp les can be up to 16-bit (12-bit typical). according to these requirements, a mono linear pcm file of about 1mbyte (about 170kbyte typical) need to be stored in the system a nd the sgm will have to fetch each of the 480,000 samples (110,000 typical) stored in the wave and send them out to the sp eaker/amplifier at the sampling frequency rate. 39.9.1.1.2 sgm functionality the only information the sgm needs to know are ? the number of samples ? the sample data width ? the sampling rate the number of samples and the sampling data width w ill be used by the channel to issue all the dma requests and fill the input fifo. the fifo control is transparent to the user. th e number of samples, the sampling data width and the sampling rate will be us ed by the mixer to consume the data in the fifo. the user will have to program the dma tcd to fetch the data from the address of the wave in the system memory and enable the dma channel.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-63 preliminary?subject to change without notice 39.9.1.2 alarm sound 39.9.1.2.1 description the application will playback a repeti tive sound with a blank period in between. the duration of a single sound can go up to 5s (typical 2.5s ), the duration of the bl ank period should be the same, sampling rate and sample width are identical to the voice test case. the duration of the repetition can be or not progr ammable in number of cycles (1 cycle being the sound+the blanking time). as an example, we can imagine an indicator noise. 39.9.1.2.2 sgm functionality the user programs the sgm sample rate, the sample widt h and the number of sa mples for the sound and the duration of the deadtime. the user also programs the sgm to have it as free running (repeating until the user will stop it) or with a limited duration (repeat number). the user will program inside the dma the address of the sound in the system memory and enable the channel. table 39-42. work flow for alarm sound in wav mode cpu (main) cpu(isr) sgm 0. clear the sgmctl.mdis to enable sgm 1. configure the dma descriptor to move the pcm data from memory to fifo 2. check the sgmst. if the fifo of current channel is ready(flschx=0 ), configure the fifo watermark. then enable the dma request dma controller will move the pcm data from memory to sgm fifo 3. configure the sgm ? clocking/ wave mode ? enable the repeat mode, configure the repeat number and sample format ? *enable the playback duration interrupt and repeat duration interrupt (optional) ? check the fifo status. if the fifo is not empty, enable the sgmctl.sogchx start the sound playback generate the 1st repeat dma transfer completion isr: configure the dma descriptor of moving the next part pcm data from memory to fifo. ...... ...... *at the end of 1st playback duration, sgm will raise the interrupt of playback duration. (optional) deadtime ...
pxd20 microcontroller reference manual, rev. 1 39-64 freescale semiconductor preliminary?subject to change without notice 39.9.2 dds mode use cases sgm can also generate the sound with a wavetable. the frequency, amplitude a nd the shape of the notes are configurable. the typical use cases fo r this function are: ? polyphonic sound ? polyphonic alarm sound generate the 2nd repeat ... ... repeat number is reached. *sgm will rise the repeat duration interrupt .(optional) sgm clear the sgmctl.sogchx. to stop the current playback or deadtime: 4. clear the sgmctl.sogchx. 5. check the sgmst. wait until the operation status is idle(statchx=3'b000) 6. disable the dma request. 7. write 0/1 to fifo read/write pointer of this channel. clear the fifo and flush the datapath. 8. check the sgmst. wa it until the fifo of current channel is ready(flschx=0). 9. configure the dma descriptor of move pcm data from memory to fifo for wav another playback-deadt sequence 10. enable the dma request. dma controller will move the pcm data from memory to sgm fifo ... 11. configure the sgm (interrupt, clocking ...) 12. check the fifo status. if the fifo is not empty, set the sgmctl.sogchx to enable the playback-deadt sequence ... ... table 39-42. work flow for alarm sound in wav mode (continued) cpu (main) cpu(isr) sgm
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-65 preliminary?subject to change without notice 39.9.2.1 polyphonic sound 39.9.2.1.1 description in this use case the application gene rates sequences of notes on each ch annel. when mixed, these generate a polyphonic sound. for every i ndividual note, the duration is define d by the configurable asr envelope. 39.9.2.1.2 sgm functionality the sgm needs to be configured with the following information: ? wavetable ? asr envelope ? frequencies of every individual notes, which are de fined by the timing configuration of the channel to generate a sequence of notes us ing a single channel, enable the in terrupt on reaching the configurable target volume level of the release phase. the frequency of each note should be configured by software. all 4 channels can be configured simultaneously or in some sequence. when all 4 channels are mixed a polyphonic sound is generated. the figures below shows an exam ple of generating/mixi ng polyphonic sound. and tabl e 1-6 shows a work flow of generating a sequen ce of notes by one channel. figure 39-61. channel 0 figure 39-62. channel 1 1 st note 2 nd note 3 rd note 4 th note 5 th note 1 st note 2 nd note 3 rd note 4 th note 5 th note 6 th note 7 th note 8 th note 9 th note
pxd20 microcontroller reference manual, rev. 1 39-66 freescale semiconductor preliminary?subject to change without notice figure 39-63. channel 2 figure 39-64. channel 3 figure 39-65. mixed polyphonic sound table 39-43. work flow of generating a sequence of notes by one channel cpu (main) cpu(isr) sgm 0. clear the sgmctl.mdis to enable sgm 1. configure the dma descriptor of move the wavetable from memory to fifo 2. check the sgmst. if the fifo of current channel is ready(flschx=0 ), configure the fifo watermark. then enable the dma request dma controller will move the pcm data from memory to sgm fifo 1 st note 2 nd note 3 rd note 4 th note 5 th note 6 th note 7 th note 8 th note 1 st note 2 nd note 3 rd note 4 th note 5 th note 6 th note
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-67 preliminary?subject to change without notice 3. configure the sgm ? clocking/ dds mode ? asr envelope ? enable the interrupt when reaching the configurable volume leve l at release/no-output phase ? configure the ddsf (frequency) of 1st note for this channel ? check the sgmst. wait until the operation status is idle(statchx=3'b000). ? check the fifo status. if the fifo is full, enable the sgmctl.sogchx ? configure the ddsf (frequency) and/or other configurations (envelope...) of 2nd note for this channel all dds-configuration are buffered start the sound generation by dds. generate the 1st note ...... sgm isr: configure the ddsf (frequency) and/or other configurations ( envelope...) of the 3nd note for this channel when reaching the target volume at end of release/no-output phase of the 1st pulse (note), raise the interrupt and synchronously reload the buffered configurations of the 2nd note. generate the 2nd note ...... sgm isr: configure the ddsf (frequency) and/or other configurations ( envelope...) of the 4nd note for this channel when reaching the target volume at release/no-output phase of the 2nd pulse (note), raise the interrupt and synchronously reload the buffered configurations of the 3rd note. ...... ...... ... to stop the current dds generation: 4. clear the sgmctl.sogchx. 5. check the sgmst. wait until the operation status is idle(statchx=3'b000) * 6. disable the dma request. (optional) *7. write 0/1 to fifo read/write pointer of this channel. clear the fifo and flush the datapath. *8. check the sgmst. wait until the fifo of current channel is ready(flschx=0). *9. configure the dma descriptor of move another wavetable from memory to fifo *10. set the watermark. enable the dma request. * dma controller will move the pcm data from memory to sgm fifo (optional) ... table 39-43. work flow of generating a sequence of notes by one channel (continued)
pxd20 microcontroller reference manual, rev. 1 39-68 freescale semiconductor preliminary?subject to change without notice note: * if user want to use the same wavetable for generat ing another note sequence, step 6-10 can be skipped. 39.9.2.2 polyph onic alarm sound 39.9.2.2.1 description in this use case the application generates a repe titive polyphonic sound with a blank period in-between. the duration of a single s ound and the inter-note no-output time can be controlled by the asr envelope. the duration of the repetition can be pr ogrammed in the number of the note pulses. 39.9.2.2.2 sgm functionality a typical/simple example could be: ? every channel generates one note periodically. four channels generate four different notes. ? cpu only needs to configure the sgm once. ? all four channels can be configured simultaneously or in some sequence. ? the number of the note pulses are progra mmable to control the entire duration. the figures below show an simple example of polyphonic alarm sound. figure 39-66. channel 0 figure 39-67. channel 1 11. configure the sgm (interrupt, clocking ...) 12. check the fifo status. if the fifo is full, set the sgmctl.sogchx to enable another dds generation of another note sequence. ... ... table 39-43. work flow of generating a sequence of notes by one channel (continued)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 39-69 preliminary?subject to change without notice figure 39-68. channel 2 figure 39-69. channel 3 figure 39-70. mixed polyphonic alarm sound
pxd20 microcontroller reference manual, rev. 1 39-70 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 40-1 preliminary?subject to change without notice chapter 40 static ram (sram) 40.1 introduction this device includes a 64 kb sram module. the main features of the sram module are: ? 64-bit ram organization with ecc ? available for data and program storage ? 64-bit ecc with single-bit corre ction, double-bit detection on a 32- bit boundary for data integrity ? supports byte (8-bit), half word (16-bit), word ( 32-bit) and long word (64- bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses ? separate internal power domains applied ram block ? standby modes to retain c ontents during low power mode ? the device can boot from the ram for fast rec overy from low power mode without the need to wait for the flash memory to be available ? option available to set the sr am access to one wait state. 40.1.1 modes of operation there are two main sram operating modes: normal mode and standby mode. these modes are briefly described in this section. 40.1.1.1 normal (f unctional) mode normal mode allows for reads and wr ites of the sram memory arrays. 40.1.1.2 standby mode standby mode preserves the contents of all or a the portion of the memory during low-power standby mode. 40.2 external signal description there are no external signals associated with the sram. 40.3 memory map and registers there are no control or status registers directly as sociated with the sram module, although error-correcting code (ecc) regist ers are provided in the error corr ection status module (ecsm). see chapter 19, error correction status module (ecsm), for more information.
pxd20 microcontroller reference manual, rev. 1 40-2 freescale semiconductor preliminary?subject to change without notice 40.4 functional description ecc checks are performed during the read portion of an sram ecc read/wri te (r/w) operation, and ecc calculations are performed dur ing the write portion of a read/w rite (r/w) operation. because the ecc bits can contain random data after the device is powered on, you must initialize the sram by executing 64-bit write instructions to the entire sram . for more information, refer to section 40.8, initialization and application information. 40.5 sram ecc mechanism the sram ecc detects the following condi tions and produces the following results: ? detects and corrects all 1-bit errors ? detects and flags all 2-bit erro rs as non-correctable errors ? detects 72-bit reads (64-bit data bus plus the 8-bit ecc) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag the intent of this is to detect al l odd-bit failures, all two-bit failures , some three-bit failures, and some multi-bit failures, with regard to iec 61508-7 a.5.6. note the sram does not detect all errors greater than 2 bits. internal sram write operations are pe rformed on the following byte boundaries: ? 1 byte (0:7 bits) ? 2 bytes (0:15 bits) ? 4 bytes or 1 word (0:31 bits) ? 8 bytes or 2 words (0:63 bits) if the entire 64 data bits are written to sram, no re ad operation is performed and the ecc is calculated across the 64-bit data bus. the 8-bit ecc is appe nded to the data segment and written to sram. if the write operation is less than the entire 64-bit data width (1-, 2-, or 4- byte segment), the following occurs: 1. the ecc mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or flagging errors. 2. the write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data bus. 3. the ecc is then calculated on the resulti ng 64 bits formed in the previous step. 4. the 8-bit ecc result is appended to the 64 bits from the data bus, and th e 72-bit value is then written to sram. 40.5.1 access timing the system bus is a two-stage pipe lined bus, which makes the timing of any access dependent on the access during the previous clock. additionally, the ecsm_mudcr register optionally forces a minimum of one
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 40-3 preliminary?subject to change without notice wait state for every access; refer to chapter 19, error correction status module (ecsm) , for more information. table 40-1 lists the various combinations of read and write operations to sram and the number of wait states used for each operation. th e table columns contain the following information: current operation lists the type of sram operation executing currently previous operation lists the valid types of sram operations that can precede the current sram operation (valid operation dur ing the preceding clock) wait states lists the number of wait states (bus clocks) the operation requires which depends on the combination of the cu rrent and previous operation table 40-1. number of wait states required for sram operations current operation previous operatio n number of wait states required 1 read operation read idle 1 pipelined read burst read 64-bit write 2 8-, 16-, or 32-bit write 0 (read from the same address) 1 (read from a different address) pipelined read read 0 burst read idle 1,0,0,0 pipelined read burst read 64-bit write 2,0,0,0 8-, 16-, or 32-bit write 0,0,0,0 (read from the same address) 1,0,0,0 (read from a different address)
pxd20 microcontroller reference manual, rev. 1 40-4 freescale semiconductor preliminary?subject to change without notice 40.5.2 reset effects on sram accesses an asynchronous functional reset will possibly corrupt ram if it assert s during a read or write operation to sram. the completion of that access depends on the cycle at which the reset occurs. data read from or written to sram before the reset event occurred is retained, a nd no other address locations are accessed or changed. in case of no access ongoing when reset oc curs, the ram corruption does not happen. instead synchronous reset (s w reset) should be used in a controll ed function (without ram accesses) in case initialization procedure is needed without ram initialization. after any destructive reset, the c ontents of ram are not guaranteed. 40.6 dma requests there are no dma requests associated with the system sram. 40.7 interrupt requests there are no interrupt requests a ssociated with the system sram, except for the ecc reporting through the ecsm. write operation 8-, 16-, or 32-bit write idle 1 read pipelined 8-, 16-, or 32-bit write 2 64-bit write 8-, 16-, or 32-bit write 0 (write to the same address) pipelined 8-, 16-, or 32-bit write 8-, 16-, or 32-bit write 0 64-bit write idle 0 64-bit write read 64-bit burst write idle 0,0,0,0 64-bit write read 1 the ecsm_mudcr[sram_add_one_ws] bit forces a minimum access of 1 cycle when enabled. table 40-1. number of wait states required for sram operations (continued) current operation previous operatio n number of wait states required 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 40-5 preliminary?subject to change without notice 40.8 initialization and application information to use the sram, the ecc must check all bits that require initialization after power on. use a 64-bit cache-inhibited write to each sram location to initia lize the sram array as part of the application initialization code. all writes must specify an even number of regist ers performed on 64-bit word-aligned boundaries. if the write is not the entire 64 bits (e.g., 8, 16, or 32 bits), a read / modify / write operation is generated that checks the ecc value upon the read. see section 40.5, sram ecc mechanism . note you must initialize sram, even if th e application does not use ecc reporting. 40.8.1 example code to initialize sram correctly, use a store multiple word ( stmw) instruction to implem ent 64-bit writes to all sram locations. the stmw instruction concatenates two 32-bit registers to implem ent a single 64-bit write. to ensure the writes are 64-bits, specify an even number of registers and write on 64-bit word-aligned boundaries. the following example code illustrates the use of the stmw instruction to initialize the sram ecc bits. example 40-1. initializing sram ecc bits init_ram: lis r11,0x4000 # base address of the sram, 64-bit word aligned ori r11,r11,0 # not needed for this address but could be for others li r12,640 # loop counter to get all of sram; # 80k/4 bytes/32 gprs = 640 mtctr r12 init_ram_loop: stmw r0,0(r11) # write all 32 gprs to sram addi r11,r11,128 # inc the ram ptr; 32 gprs * 4 bytes = 128 bdnz init_ram_loop # loop for 80k of sram
pxd20 microcontroller reference manual, rev. 1 40-6 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-1 preliminary?subject to change without notice chapter 41 stepper motor controller (smc) 41.1 introduction the smc block is a pwm motor controll er suitable for driving small ste pper and air core motors used in instrumentation applications. the m odule can also be used for other mo tor control or pwm applications that match the frequency, resolution and output driv e capabilities of the module. the smc has 12 pwm channels associated with two pins each (24 pins in total). 41.1.1 features the smc includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with select able pwm dithering function ? left, right, or center aligned pwm ? short-circuit detection in each pwm channel with programmable time-out 41.1.2 modes of operation 41.1.2.1 functional modes 41.1.2.1.1 dither function dither function can be selected or deselected by setting or clearing the mcctl0 [dith] bit. this bit influences all pwm channels. for details, please refer to section 41.4.1.3.5, dither bit (mcctl0[dith]) . 41.1.2.2 pwm channel configuration modes the 12 pwm channels can operate in three functional modes. those mode s are, with some restrictions, selectable for each ch annel independently. 41.1.2.2.1 dual full h-bridge mode this mode is suitable to dr ive a stepper motor or a 360 o air gauge instrument. for details, please refer to section 41.4.1.1.1, dual full h-bridge mode . in this mode two adjacent pwm channels are combined, and two pwm channels drive four pins. 41.1.2.2.2 full h-bridge mode this mode is suitable to drive a ny load requiring a pwm signal in a h- bridge configurati on using two pins. for details please refer to section 41.4.1.1.2, full h-bridge mode .
pxd20 microcontroller reference manual, rev. 1 41-2 freescale semiconductor preliminary?subject to change without notice 41.1.2.2.3 half h-bridge mode this mode is suitable to drive a 90 o instrument driven by one pin. for details, please refer to section 41.4.1.1.3, half h-bridge mode . 41.1.2.3 pwm alignment modes each pwm channel can operate indepe ndently in three differ ent alignment modes. fo r details, please refer to section 41.4.1.3.1, pwm alignment modes . 41.1.2.4 low-power modes the behavior of the smc when it is disabled by the mode entry module is programmable. for details, please see section 41.4.5, operation in smc stop mode .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-3 preliminary?subject to change without notice 41.1.3 block diagram figure 41-1. smc block diagram period register mcper 11-bit timer/counter duty register mcdc0 comparator m0c0m m0c0p duty register mcdc1 comparator m0c1m m0c1p duty register mcdc2 comparator m1c0m m1c0p duty register mcdc3 comparator m1c1m m1c1p duty register mcdc4 comparator m2c0m m2c0p duty register mcdc5 comparator m2c1m m2c1p duty register mcdc6 comparator m3c0m m3c0p duty register mcdc7 comparator m3c1m m3c1p control registers mcctl0[dith] 11 pwm channel pair pwm channel duty register mcdc8 comparator m4c0m m4c0p duty register mcdc9 comparator m4c1m m4c1p duty register mcdc10 comparator m5c0m m5c0p duty register mcdc11 comparator m5c1m m5c1p
pxd20 microcontroller reference manual, rev. 1 41-4 freescale semiconductor preliminary?subject to change without notice 41.2 external signal description the smc is associated with 24 pins. table 41-1 lists the relationship betw een the pwm channels, signal pins, pwm channel pairs (motor numbers), coils and node s they are supposed to dr ive if all channels are set to dual full h-br idge configuration. 41.2.1 m0c0m/m0c0p/m0c1m/m0c1p ? pwm output pins for motor 0 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive cu rrent flow through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state (for details refer to section 41.4.1, modes of operation ). table 41-1. pwm channel and pin assignment pin name pwm channel pwm channel pair 1 1 a pwm channel pair always consists of pwm channel x and pwm channel x+1 (x = 2 ? n). the term ?pwm channel pair? is equivalent to the term ?motor.? for example, channel pair 0 is equivalent to motor 0. coil node m0c0m 0 0 0 minus m0c0p plus m0c1m 1 1 minus m0c1p plus m1c0m 2 1 0 minus m1c0p plus m1c1m 3 1 minus m1c1p plus m2c0m 4 2 0 minus m2c0p plus m2c1m 5 1 minus m2c1p plus m3c0m 6 3 0 minus m3c0p plus m3c1m 7 1 minus m3c1p plus m4c0m 8 4 0 minus m4c0p plus m4c1m 9 1 minus m4c1p plus m5c0m 10 5 0 minus m5c0p plus m5c1m 11 1 minus m5c1p plus
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-5 preliminary?subject to change without notice 41.2.2 m1c0m/m1c0p/m1c1m/m1c1p ? pwm output pins for motor 1 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive cu rrent flow through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state (for details refer to section 41.4.1, modes of operation ). 41.2.3 m2c0m/m2c0p/m2c1m/m2c1p ? pwm output pins for motor 2 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive cu rrent flow through coil 0 when m2c0p is driven to a logic high state. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state (for details refer to section 41.4.1, modes of operation ). 41.2.4 m3c0m/m3c0p/m3c1m/m3c1p ? pwm output pins for motor 3 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive cu rrent flow through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state (for details refer to section 41.4.1, modes of operation ). 41.2.5 m4c0m/m4c0p/m4c1m/m4c1p ? pwm output pins for motor 4 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive cu rrent flow through coil 0 when m4c0p is driven to a logic high state. pwm output on m4c1m results in a positive current flow through coil 1 when m4c1p is driven to a logic high state (for details refer to section 41.4.1, modes of operation ). 41.2.6 m5c0m/m5c0p/m5c1m/m5c1p ? pwm output pins for motor 5 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive cu rrent flow through coil 0 when m5c0p is driven to a logic high state. pwm output on m5c1m results in a positive current flow through coil 1 when m5c1p is driven to a logic high state (for details refer to section 41.4.1, modes of operation ). 41.3 memory map and register definition this section provides a detailed description of all registers of the 10-bit 12-channel smc module. 41.3.1 module memory map table 41-2 shows the memory map of the 10-bit 12-channel smc module. access type can be ? rw: read and write
pxd20 microcontroller reference manual, rev. 1 41-6 freescale semiconductor preliminary?subject to change without notice ? data access type is 8,16 or 32 bit. it is recommende d to access the various register using the access types shown in table 41-2 for consistent write operations. table 41-2. smc ? memory map address offset use recommende d access type location 0x00 motor controller control register 0 (mcctl0) rw, 8 bit on page 41-8 0x01 motor controller control register 1 (mcctl1) rw, 8 bit on page 41-9 0x02 motor controller period register (mcper) rw, 16 bit on page 41-10 0x04 reserved ? 0x05 reserved ? 0x06 reserved ? 0x07 reserved ? 0x08 reserved ? 0x09 reserved ? 0x0a reserved ? 0x0b reserved ? 0x0c reserved ? 0x0d reserved ? 0x0e reserved ? 0x0f reserved ? 0x10 motor controller channel control register 0 (mccc0) rw, 8 bit on page 41-10 0x11 motor controller channel control register 1 (mccc1) rw, 8 bit on page 41-10 0x12 motor controller channel control register 2 (mccc2) rw, 8 bit on page 41-10 0x13 motor controller channel control register 3 (mccc3) rw, 8 bit on page 41-10 0x14 motor controller channel control register 4 (mccc4) rw, 8 bit on page 41-10 0x15 motor controller channel control register 5 (mccc5) rw, 8 bit on page 41-10 0x16 motor controller channel control register 6 (mccc6) rw, 8 bit on page 41-10 0x17 motor controller channel control register 7 (mccc7) rw, 8 bit on page 41-10 0x18 motor controller channel control register 8 (mccc8) rw, 8 bit on page 41-10 0x19 motor controller channel control register 9 (mccc9) rw, 8 bit on page 41-10 0x1a motor controller channel control register 10 (mccc10) rw, 8 bit on page 41-10 0x1b motor controller channel control register 11 (mccc11) rw, 8 bit on page 41-10 0x1c reserved - 0x1d reserved - 0x1e reserved - 0x1f reserved - 0x20 motor controller duty cycle register 0 (mcdc0) rw, 16 bit on page 41-11 0x22 motor controller duty cycle register 1 (mcdc1) rw, 16 bit on page 41-11 0x24 motor controller duty cycle register 2 (mcdc2) rw, 16 bit on page 41-11 0x26 motor controller duty cycle register 3 (mcdc3) rw, 16 bit on page 41-11 0x28 motor controller duty cycle register 4 (mcdc4) rw, 16 bit on page 41-11 0x2a motor controller duty cycle register 5 (mcdc5) rw, 16 bit on page 41-11 0x2c motor controller duty cycle register 6 (mcdc6) rw, 16 bit on page 41-11 0x2e motor controller duty cycle register 7 (mcdc7) rw, 16 bit on page 41-11
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-7 preliminary?subject to change without notice 41.3.2 register description this section provides detailed descriptions of all registers in ascending address order. table 41-3 provides a key for the register figur es and register tables. 0x30 motor controller duty cycle register 8 (mcdc8) rw, 16 bit on page 41-11 0x32 motor controller duty cycle register 9 (mcdc9) rw, 16 bit on page 41-11 0x34 motor controller duty cycle register 10 (mcdc10) rw, 16 bit on page 41-11 0x36 motor controller duty cycle register 11 (mcdc11) rw, 16 bit on page 41-11 0x38 reserved - 0x39 reserved - 0x3a reserved - 0x3b reserved - 0x3c reserved - 0x3d reserved - 0x3e reserved - 0x3f reserved - 0x40 short-circuit detector time-out register (mcsdto) rw, 8 bit on page 41-13 0x41 reserved - 0x42 reserved - 0x43 reserved - 0x44 short-circuit detector enable register 0 (mcsde0) rw, 8 bit on page 41-13 0x45 short-circuit detector enable register 1 (mcsde1) rw, 8 bit on page 41-14 0x46 short-circuit detector enable register 2 (mcsde2) rw, 8 bit on page 41-14 0x47 reserved - 0x48 short-circuit detector interrupt enable register 0 (mcsdien0) rw, 8 bit on page 41-15 0x49 short-circuit detector interrupt enable register 1 (mcsdien1) rw, 8 bit on page 41-15 0x4a short-circuit detector interrupt enable register 2 (mcsdien2) rw, 8 bit on page 41-16 0x4b reserved - 0x4c short-circuit detector interrupt register 0 (mcsdi0) r/mw, 8 bit on page 41-16 0x4d short-circuit detector interrupt register 1 (mcsdi1) r/mw, 8 bit on page 41-17 0x4e short-circuit detector interrupt register 2 (mcsdi2) r/mw, 8 bit on page 41-17 0x4f reserved - table 41-3. register access conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its pres ence in the read or write row indicate s that it can be read or written. register field types table 41-2. smc ? memory map (continued) address offset use recommende d access type location
pxd20 microcontroller reference manual, rev. 1 41-8 freescale semiconductor preliminary?subject to change without notice 41.3.2.1 motor controller control register 0 (mcctl0) this register controls the ope rating mode of the smc module. . rwm a read/write bit that may be modified by hardware in some fashion other than by a reset. w1c write one to clear. a flag bit that can be read, is cleared by writing a one, writing 0 has no effect. reset value 0 resets to zero. 1 resets to one. offset module base + 0x0000 0 1 2 3 4 5 6 7 r0 mcpre 0 0 dith 0 mctoif w w1c reset 0 0 0 0 0 0 0 0 figure 41-2. motor controller control register 0 (mcctl0) table 41-4. mcctl0 field descriptions field description mcpre motor controller prescaler select ? mcpre determines the prescaler value that sets the motor controller timer counter clock frequency (f tc ). the clock source for the prescaler is the peripheral bus clock (f bus ) as shown in figure 41-32 . writes to mcpre will not affect the timer counter clock frequency f tc until the start of the next pwm period. 00 f tc = f bus 01 f tc = f bus /2 10 f tc = f bus /4 11 f tc = f bus /8 dith motor control/driver di ther feature enable (refer to section 41.4.1.3.5, dither bit (mcctl0[dith]) ) 0 dither feature is disabled. 1 dither feature is enabled. mctoif motor controller timer coun ter overflow interrupt flag ? this bit is set when a motor controller timer counter overflow occurs. the bit is cleared by writing a 1 to the bit. 0 a motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared. 1 a motor controller timer co unter overflow has occurred. table 41-3. register access conventions (continued) convention description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-9 preliminary?subject to change without notice 41.3.2.2 motor controller control register 1 (mcctl1) this register controls the behavior of the analog se ction of the smc as well as the interrupt enables. offset module base + 0x0001 0 1 2 3 4 5 6 7 r recirc 0 0 0 0 0 0 mctoie w reset 0 0 0 0 0 0 0 0 figure 41-3. motor controller control register 1 (mcctl1) table 41-5. mcctl1 field descriptions field description recirc recirculation in (dual) full h-bridge mode (refer to section 41.4.1.3.3, recirculation bit (mcctl1[recirc]) ) ? recirc only affects the outputs in (dual) full h-bridge modes. in half h-bridge mode, the pwm output is always active low. recirc = 1 will also invert the effect of the mcdcx [sign] bits (refer to section 41.4.1.3.2, si gn bit (mcdcx[sign]) ) in (dual) full h-bridge modes. recirc must be changed only while no pwm channel is operating in (dual) full h-bridge mode; otherwise, erroneous output pattern may occur. 0 recirculation on the high side transistors. acti ve state for pwm output is logic low, the static channel will output logic high. 1 recirculation on the low side transistors. active state for pwm output is logic high, the static channel will output logic low. mctoie motor controller timer counte r overflow interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the motor controller timer counter overflow interrupt flag ( mcctl0 [mctoif]) is set.
pxd20 microcontroller reference manual, rev. 1 41-10 freescale semiconductor preliminary?subject to change without notice 41.3.2.3 motor controller period register (mcper) setting per to 0 will shut off all pwm channels as if mcccx [mcam] is set to 0 in all channel control registers after the next period timer counter overflow. in this case, the mo tor controller releases all pins. note programming per to 1 and setting the mcctl0 [dith] bit will be managed as if per is programmed to 0. all pwm channels will be shut off after the next period ti mer counter overflow. 41.3.2.4 motor controller channe l control register (mccc0..11) each pwm channel has one associat ed control register to control output delay, pwm alignment, and output mode. the number of each re gister refers directly the pwm channel it controls. the relation between channels, pin names and register names is shown in table 41-19 . offset module base + 0x0002, 0x0003 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 per w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 41-4. motor controller period register (mcper) table 41-6. mcper field descriptions field description per pwm period ? per defines the number of motor controller timer counter clocks a pwm period lasts. the motor controller timer counter is clocked with the frequency f tc . if dither mode is enabled ( mcctl0 [dith] = 1, refer to section 41.4.1.3.5, dith er bit (mcctl0[dith]) ), per[0] is ignored and reads as a 0. in this case per = 2 * mcdcx [duty[10:1]]. offset module base + 0x0010 . . . 0x001b 0 1 2 3 4 5 6 7 r mcom mcam 0 0 cd w reset 0 0 0 0 0 0 0 0 figure 41-5. motor controller channel control register (mccc0..11)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-11 preliminary?subject to change without notice note the smc will release the pins after the next pwm timer counter overflow without accommodating any channel de lay if a single channel has been disabled or if the period re gister has been cleared or all channels have been disabled. program one or more inac tive pwm frames (duty cycle = 0) before writing a configurat ion that disables a single channel or the entire smc. 41.3.2.5 motor controller duty cycle register (mcdc0..11) each duty cycle register sets the sign and duty functionality for the respective pwm channel. the number of each register refires directly the pwm channel it controls. the re lation between channels, pin names and register names is shown in table 41-19 . table 41-7. mcccx field descriptions field description mcom output mode ? mcom controls the pwm channel?s output mode. 00 half h-bridge mode, pwm on pin mncxm, pin mncxp is released 01 half h-bridge mode, pwm on pin mncxp, pin mncxm is released 10 full h-bridge mode 11 dual full h-bridge mode mcam pwm channel a lignment mode ? mcam controls the pwm channel?s pwm alignment mode and operation. mcam and mcom are double buffered. the values used for the generation of the output waveform will be copied to the working registers either at once (if all pwm channels are disabled or mcper [per] is set to 0) or if a timer counter overflow occurs. reads of the register return the most recent written value, which are not necessarily the currently active values. 00 channel disabled 01 left aligned 10 right aligned 11 center aligned cd pwm channel delay ? each pwm channel can be individually delayed by a programmable number of pwm timer counter clocks. the delay will be n/f tc . 00 zero pwm clocks channel delay 01 one pwm clock channel delay 10 two pwm clocks channel delay 11 three pwm clocks channel delay offset module base + 0x0020 . . . 0x0037 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r sign [4] sign[3:0] duty w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 41-6. motor cont roller duty cycle register (mcdc0..11)
pxd20 microcontroller reference manual, rev. 1 41-12 freescale semiconductor preliminary?subject to change without notice to prevent the output from incons istent signals, the duty cycle re gisters are double buffered. the smc module will use working registers to generate the out put signals. the working re gisters are copied from the bus accessible registers at the following conditions: ? mcper [per] is set to 0 (all channels are disabled in this case) ? mcccx [mcam] of the respective channel is set to 0 (channel is disabled) ? a pwm timer counter overflow occurs while in half h-bridge or full h-bridge mode ? a pwm channel pair is configured to work in dual full h-bridge mode and a pwm timer counter overflow occurs after the odd 1 duty cycle register of the ch annel pair has been written. in this way, the output of the pwm will always be either the old pwm waveform or the new pwm waveform, not some variation in between. reads of this register return the mo st recent value wr itten. reads do not necessarily return the value of the currently active sign, duty cycle, and dither fu nctionality due to the double buffering scheme. table 41-8. mcdcx field descriptions field description sign[4] sign bit ? the sign[4] bit is used to define which out put will drive the pwm signal in (dual) full-h-bridge modes. the sign[4] bit has no effect in half-bridge modes. see section 41.4.1.3.2, sign bit (mcdcx[sign]) and ta b l e 4 1 - 2 0 for detailed information about the impact of mcctl1 [recirc] and sign[4] bit on the pwm output. sign[3:0] sign bit extension ? replicates the sign[4] bit towards t he duty field to make the whole register a signed representation for the duty cycle length. duty duty cycle length ? duty defines the number of motor controller timer counter clocks the corresponding output is driven low ( mcctl1 [recirc] = 0) or is driven high ( mcctl1 [recirc] = 1). setting all bits to 0 will give a static high output in case of mcctl1 [recirc] = 0; otherwise, a static low output. values greater than or equal to the conten ts of the period register will generate a static low output in case of mcctl1 [recirc] = 0, or a static high output if mcctl1 [recirc] = 1. 1. odd duty cycle register: mcdcx +1, x = 2 ? n
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-13 preliminary?subject to change without notice 41.3.2.6 short-circuit detector time-out register (mcsdto) 41.3.2.7 short-circuit detector enable register 0 (mcsde0) offset module base + 0x0040 0 1 2 3 5 7 r tout w reset 0 0 0 0 0 0 0 0 figure 41-7. short-circuit detector time-out register (mcsdto) table 41-9. mcsdto field descriptions field description tout time-out ? the value tout is an unsigned 8-bit number . this value is used as load value for the short-circuit detection counters. this value is applied to all 24 short-circuit detection blocks. due to synchronization and sampling, tout must always be larger than 2 (see also section 41.4.6, short-circuit detection ). offset module base + 0x0044 0 1 2 3 4 5 6 7 r sden w reset 0 0 0 0 0 0 0 0 figure 41-8. short-circuit detector enable register 0 (mcsde0) table 41-10. mcsde0 field description field description sden short-circuit detector enable ? each short-circuit detector can be enabled or disabled according to the mapping described in ta b l e 4 1 - 2 3 . the short-circuit detector of a given pin is enabled if the related enable bit is set to 1.
pxd20 microcontroller reference manual, rev. 1 41-14 freescale semiconductor preliminary?subject to change without notice 41.3.2.8 short-circuit detector enable register 1 (mcsde1) 41.3.2.9 short-circuit detector enable register 2 (mcsde2) offset module base + 0x0045 0 1 2 3 4 5 6 7 r sden w reset 0 0 0 0 0 0 0 0 figure 41-9. short-circuit detector enable register 1 (mcsde1) table 41-11. mcsde1 field description field description sden short-circuit detector enable ? each short-circuit detector can be enabled or disabled according to the mapping described in ta b l e 4 1 - 2 3 . the short-circuit detector of a given pin is enabled if the related enable bit is set to 1. offset module base + 0x0046 0 1 2 3 4 5 6 7 r sden w reset 0 0 0 0 0 0 0 0 figure 41-10. short-circuit detector enable register 2 (mcsde2) table 41-12. mcsde2 field description field description sden short-circuit detector enable ? each short-circuit detector can be enabled or disabled according to the mapping described in ta b l e 4 1 - 2 3 . the short-circuit detector of a given pin is enabled if the related enable bit is set to 1.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-15 preliminary?subject to change without notice 41.3.2.10 short-circuit detector inte rrupt enable register 0 (mcsdien0) 41.3.2.11 short-circuit detector inte rrupt enable register 1 (mcsdien1) offset module base + 0x0048 0 1 2 3 4 5 6 7 r sdie w reset 0 0 0 0 0 0 0 0 figure 41-11. short-circuit detector interrupt enable register 0 (mcsdien0) table 41-13. mcsdien0 field descriptions field description sdie short-circuit detect or interrupt enable ? the interrupt of each short-circuit detector can individually be enabled or disabled according to the mapping described in table 41-23 . the short-circuit detector interrupt of a given pin is enab led if the related interrupt enable bit is set to 1. offset module base + 0x0049 0 1 2 3 4 5 6 7 r sdie w reset 0 0 0 0 0 0 0 0 figure 41-12. short-circuit detector interrupt enable register 1 (mcsdien1) table 41-14. mcsdien1 field descriptions field description sdie short-circuit detect or interrupt enable ? the interrupt of each short-circuit detector can individually be enabled or disabled according to the mapping described in table 41-23 . the short-circuit detector interrupt of a given pin is enab led if the related interrupt enable bit is set to 1.
pxd20 microcontroller reference manual, rev. 1 41-16 freescale semiconductor preliminary?subject to change without notice 41.3.2.12 short-circuit detector inte rrupt enable register 2 (mcsdien2) 41.3.2.13 short-circuit detector interrupt register 0 (mcsdi0) offset module base + 0x004a 0 1 2 3 4 5 6 7 r sdie w reset 0 0 0 0 0 0 0 0 figure 41-13. short-circuit detector interrupt enable register 2 (mcsdien2) table 41-15. mcsdien2 field descriptions field description sdie short-circuit detect or interrupt enable ? the interrupt of each short-circuit detector can individually be enabled or disabled according to the mapping described in table 41-23 . the short-circuit detector interrupt of a given pin is enab led if the related interrupt enable bit is set to 1. offset module base + 0x004c 0 1 2 3 4 5 6 7 rsdif w rwm rwm rwm rwm rwm rwm rwm rwm reset 0 0 0 0 0 0 0 0 figure 41-14. short-circuit detector interrupt register 0 (mcsdi0) table 41-16. mcsdi0 field descriptions field description sdif short-circuit detector interrupt flag ? in case of a detected shor t-circuit, the corresponding bit according to the mapping in table 41-23 is set in the short-circuit detector interrupt register. if this specific interrupt is also ena bled in the interrupt enable register mcsdien0 , than this event will rise an external interrupt.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-17 preliminary?subject to change without notice 41.3.2.14 short-circuit detector interrupt register 1 (mcsdi1) 41.3.2.15 short-circuit detector interrupt register 2 (mcsdi2) offset module base + 0x004d 0 1 2 3 4 5 6 7 rsdif w rwm rwm rwm rwm rwm rwm rwm rwm reset 0 0 0 0 0 0 0 0 figure 41-15. short-circuit detector interrupt register 1 (mcsdi1) table 41-17. mcsdi1 field descriptions field description sdif short-circuit detector interrupt flag ? in case of a detected shor t-circuit, the corresponding bit according to the mapping in table 41-23 is set in the short-circuit detector interrupt register. if this specific interrupt is also ena bled in the interrupt enable register mcsdien1 , than this event will rise an external interrupt. offset module base + 0x004e 0 1 2 3 4 5 6 7 rsdif w rwm rwm rwm rwm rwm rwm rwm rwm reset 0 0 0 0 0 0 0 0 figure 41-16. short-circuit detector interrupt register 2 (mcsdi2) table 41-18. mcsdi2 field descriptions field descriptions sdif short-circuit detector interrupt flag ? in case of a detected shor t-circuit, the corresponding bit according to the mapping in table 41-23 is set in the short-circuit detector interrupt register. if this specific interrupt is also ena bled in the interrupt enable register mcsdien2 , than this event will rise an external interrupt.
pxd20 microcontroller reference manual, rev. 1 41-18 freescale semiconductor preliminary?subject to change without notice 41.4 functional description 41.4.1 modes of operation 41.4.1.1 pwm output modes the smc is configured between three output modes. ? dual full h-bridge mode can be used to control either a stepper motor or a 360 ? air core instrument. in this case two pwm channels are combined. ? in full h-bridge mode, each pwm channel is updated independently. ? in half h-bridge mode, one pin of the pwm ch annel can generate a pwm signal to control a 90 ? air core instrument (or other load requiring a pwm signal) and the other pin is unused. the mode of operation for pwm channel x is determined by th e output mode bits mcccx [mcom]. after a reset occurs, each pwm channel will be disabled, the corresponding pins are released. each pwm channel consists of tw o pins. one output pin will genera te a pwm signal. the other will operate as logic high or low output dependi ng on the state of the recirculation bit mcctl1 [recirc] (refer to section 41.4.1.3.3, recirculatio n bit (mcctl1[recirc]) ), while in (dual) full h-bridge mode, or will be released, whil e in half h-bridge mode. the state of the sign bit mcdcx [sign[4]] in the duty cycle register determines the pin where the pwm signal is driven in full h-bri dge mode. while in half h-bridge mode, the state of the released pin is dete rmined by other modules asso ciated with this pin. associated with each pwm cha nnel pair n are two pwm channels, x and x + 1, where x = 2 * n and n (0,1,2... 5) is the pwm channel pair number. duty cycl e register x controls the sign of the pwm signal (which pin drives the pwm signal) and the duty cy cle of the pwm signal for smc channel x. the pins associated with pwm channel x are mnc0p and mnc0m. similarly, duty cycle register x + 1 controls the sign of the pwm signal and the duty cycle of the pwm signal for channel x + 1. the pins associated with pwm channel x + 1 are mnc1p and mnc1m. this is summarized in table 41-19 . table 41-19. corresponding registers and pin names for each pwm channel pair pwm channel pair number pwm channel control register duty cycle register channel number pin names n mcccx mcdcx pwm channel x, x = 2 ? n mnc0m mnc0p mcccx +1 mcdcx +1 pwm channel x+1, x = 2 ? n mnc1m mnc1p 0 mccc0 mcdc0 pwm channel 0 m0c0m m0c0p mccc1 mcdc1 pwm channel 1 m0c1m m0c1p
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-19 preliminary?subject to change without notice 41.4.1.1.1 dual full h-bridge mode pwm channel pairs x and x + 1 operate in dual full h-bridge mode if both channels are enabled ( mcccx [mcam]=0x1, 0x2, or 0x3) and the output mode bits mcccx [mcom] in both pwm channel control registers are set to 0x3. a typical configuration in dual fu ll h-bridge mode is shown in figure 41-17 . pwm channel x drives the pwm output signal on either mnc0p or mnc0m. if mnc0p drives the pwm signal, mnc0m will be output either high or low depending on the mcctl1 [recirc] bit. if mnc0m drives the pwm signal, mnc0p will be an output high or low. pwm channel x + 1 drives the pwm output signal on either mnc1p or mnc1m. if mnc1p drives the pw m signal, mnc1m will be an output high or low. if mnc1m drives the pwm signal, mnc1p will be an out put high or low. this results in motor recirculation currents on the high side drivers ( mcctl1 [recirc] = 0) while the pwm signal is at a logic high level, or motor recirculation currents on the low side drivers ( mcctl1 [recirc] = 1) while the pwm signal is at a logic low level. the pin driving the pwm signal is determined by the sign bit mcdcx [sign[4]] for the corresponding channel and the state of the mcctl1 [recirc] bit. the value of the pwm duty cycle is determined by the value of the duty cycle bits mcdcx [duty] for the corresponding channel. 1 mccc2 mcdc2 pwm channel 2 m1c0m m1c0p mccc3 mcdc3 pwm channel 3 m1c1m m1c1p 2 mccc4 mcdc4 pwm channel 4 m2c0m m2c0p mccc5 mcdc5 pwm channel 5 m2c1m m2c1p 3 mccc6 mcdc6 pwm channel 6 m3c0m m3c0p mccc7 mcdc7 pwm channel 7 m3c1m m3c1p 4 mccc8 mcdc8 pwm channel 8 m4c0m m4c0p mccc9 mcdc9 pwm channel 9 m4c1m m4c1p 5 mccc10 mcdc10 pwm channel 10 m5c0m m5c0p mccc11 mcdc11 pwm channel 11 m5c1m m5c1p table 41-19. corresponding registers and pin names for each pwm channel pair (continued) pwm channel pair number pwm channel control register duty cycle register channel number pin names
pxd20 microcontroller reference manual, rev. 1 41-20 freescale semiconductor preliminary?subject to change without notice figure 41-17. typical dual full h-bridge mode configuration 16-bit write accesses to the duty cycle registers ar e allowed, 8-bit write accesse s can lead to unpredictable duty cycles. the following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent pwm output: 1. write to duty cycle register x 2. write to duty cycle register x + 1 at the next timer counter overflow, the duty cycle re gisters will be copied to the working duty cycle registers. sequential writes to the duty cycle register x will result in the previous data being overwritten. 41.4.1.1.2 full h-bridge mode in full h-bridge mode ( mcccx [mcom]=0x2), the pwm channels x and x + 1 operate independently. the duty cycle working registers are updated wh enever a timer counter overflow occurs. 41.4.1.1.3 half h-bridge mode in half h-bridge mode ( mcccx [mcom] = 0x0 or 0x1), the pwm channels x and x + 1 operate independently. in this mode, each pwm channel can be configured such that one pin is released and the other pin is a pwm output. figure 41-18 shows a typical configurati on in half h-bridge mode. the two pins associated with each channel are sw itchable between released mode and pwm output dependent upon the state of the output mode bits mcccx [mcom]. see register description in section 41.3.2.4, motor controller channel control register (mccc0..11) . in half h-bridge mode, the state of the mcdcx [sign[4]] bit has no effect. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m motor n, coil 0 motor n, coil 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-21 preliminary?subject to change without notice figure 41-18. typical quad half h-bridge mode configuration 41.4.1.2 relationship between pwm mode and pwm channel enable the pair of smc channels cannot be placed into dua l full h-bridge mode unles s both smc channels have been enabled ( mcccx [mcam] not equal to 0) and dual full h- bridge mode is selected for both pwm channels ( mcccx [mcom] = 0x3). if only one channe l is set to dual full h-bri dge mode, this channel will operate in full h-bridge m ode, the other as programmed. 41.4.1.3 relationship between sign , duty, dither, recirc, period, and pwm mode functions 41.4.1.3.1 pwm alignment modes each pwm channel can be programmed individually to three different alignment modes. the alignment mode is determined by the mcccx [mcam] bits in the corresponding channel control register. left aligned ( mcccx [mcam] = 0x1): the output wi ll start active (low if mcctl1 [recirc] = 0 or high if mcctl1 [recirc] = 1) and will turn inactive (high if mcctl1 [recirc] = 0 or low if mcctl1 [recirc] = 1) after the number of counts spec ified by the corresponding duty cycle register. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m released pwm output v ssm v ddm v ssm v ddm released pwm output
pxd20 microcontroller reference manual, rev. 1 41-22 freescale semiconductor preliminary?subject to change without notice figure 41-19. left aligned right aligned ( mcccx [mcam] = 0x2): the output wi ll start inactive (high if mcctl1 [recirc] = 0 and low if mcctl1 [recirc] = 1) and will turn act ive after the number of counts spec ified by the difference of the contents of period register and the corresponding duty cycle register. figure 41-20. right aligned center aligned ( mcccx [mcam] = 0x3): even periods will be out put left aligned, odd periods will be output right aligned. pwm ope ration starts with the even period af ter the channel has been enabled. pwm operation in center aligned mode might start with the od d period if the channel has not been disabled before changing the alignment mode to center aligned. 0 15 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 mcctl0[dith] = 0, mcccx[mcam] = 0x1, mcdcx[duty] = 15, mcper[per] = 100, mcctl1[recirc] = 0 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 85 99 99 mcctl0[dith] = 0, mcccx[ mcam] = 0x2, mcdcx[duty] = 15, mcper[per] = 100, mcctl1[recirc] = 0
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-23 preliminary?subject to change without notice figure 41-21. center aligned 41.4.1.3.2 sign bit ( mcdcx [sign]) assuming mcctl1 [recirc] = 0 (the active state of the pwm signal is low), when the mcdcx [sign[4]] bit for the corresponding channel is cleared, mnc0p (if the pwm channel number is even, n = 0, 1, 2...5, see table 41-19 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2...5 see table 41-19 ), outputs a logic high while in (dual) full h-br idge mode. in half h-br idge mode the state of the mcdcx [sign[4]] bit has no effect. the pwm output signal is generated on mnc0m (if the pwm channel number is even, n = 0, 1, 2...5, see table 41-19 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2...5). assuming mcctl1 [recirc] = 0 (the active state of the pwm signal is low), when the mcdcx [sign[4]] bit for the corresponding channel is set, mnc0m (if th e pwm channel number is even, n = 0, 1, 2...5, see table 41-19 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2...5, see table 41-19 ), outputs a logic high while in (dual) full h-br idge mode. in half h-br idge mode the state of the mcdcx [sign[4]] bit has no effect. the pwm output signal is generated on mnc0p (if the pwm channel number is even, n = 0, 1, 2...5, see table 41-19 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2...5). setting mcctl1 [recirc] = 1 will also i nvert the effect of the mcdcx [sign[4]] bit such that while mcdcx [sign[4]] = 0, mnc0p or mnc1p will generate the pwm signal and mnc0m or mnc1m will be a static low output. while mcdcx [sign[4]] = 1, mnc0m or mnc1m w ill generate the pwm signal and mnc0p or mnc1p will be a static low output. in this case the active state of th e pwm signal will be high. see table 41-20 for detailed information about the impact of mcdcx [sign[4]] and mcctl1 [recirc] bit on the pwm output. table 41-20. impact of mcctl1 [recirc] and mcdcx [sign[4]] bit on the pwm output output mode mcctl1 [recirc] mcdcx [sign[4]] mncym mncyp (dual) full h-bridge 0 0 pwm 1 1 (dual) full h-bridge 0 1 1 pwm 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 mcctl0[dith] = 0, mcccx[mcam ] = 0x3, mcdcx[duty] = 15, mcper[per] = 100, mcctl1[recirc] = 0
pxd20 microcontroller reference manual, rev. 1 41-24 freescale semiconductor preliminary?subject to change without notice 41.4.1.3.3 recirculation bit ( mcctl1 [recirc]) the mcctl1 [recirc] bit controls the flow of the r ecirculation current of the load. setting mcctl1 [recirc] = 0 will cause recirc ulation current to fl ow through the high side transistors, and mcctl1 [recirc] = 1 will cause the recirculation current to flow through the low side transistors. the mcctl1 [recirc] bit is only active in ( dual) full h-bridge modes. effectively, mcctl1 [recirc] = 0 will cause a static high out put on the output terminal not driven by the pwm, mcctl1 [recirc] = 1 will cause a st atic low output on the output terminals not driven by the pwm. to achieve the same current direction, the mcdcx [sign[4]] bit behavior is inverted if mcctl1 [recirc] = 1. figure 41-22 , figure 41-23 , figure 41-24 , and figure 41-25 illustrate the effect of the mcctl1 [recirc] bit in (dual) full h-bridge modes. mcctl1 [recirc] bit must be changed onl y while no pwm channel is operat ed in (dual) full h-bridge mode. (dual) full h-bridge 1 0 0 pwm 2 (dual) full h-bridge 1 1 pwm 0 half h-bridge: pwm on mncym don?t care don?t care pwm ? 3 half h-bridge: pwm on mncyp don?t care don?t care ? pwm 1 pwm : the pwm signal is low active. e.g., the waveform starts with 0 in left aligned mode. output m generates the pwm signal. output p is static high. 2 pwm: the pwm signal is high active. e.g., the waveform st arts with 1 in left aligned mode. output p generates the pwm signal. output m is static low. 3 the state of the output transistors is not controlled by the smc. table 41-20. impact of mcctl1 [recirc] and mcdcx [sign[4]] bit on the pwm output (continued) output mode mcctl1 [recirc] mcdcx [sign[4]] mncym mncyp
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-25 preliminary?subject to change without notice figure 41-22. pwm active phase, mcctl1 [recirc] = 0, mcdcx [sign[4]] = 0 figure 41-23. pwm passive phase, mcctl1 [recirc] = 0, mcdcx [sign[4]] = 0 v ddm v ssm mnc0p mnc0m static 0 pwm 1 pwm 1 static 0 v ddm v ssm mnc0p mnc0m static 0 pwm 0 static 0 pwm 0
pxd20 microcontroller reference manual, rev. 1 41-26 freescale semiconductor preliminary?subject to change without notice figure 41-24. pwm active phase, mcctl1 [recirc] = 1, mcdcx [sign[4]] = 0 figure 41-25. pwm passive phase, mcctl1 [recirc] = 1, mcdcx [sign[4]] = 0 41.4.1.3.4 relationship between mcctl1 [recirc] bit, mcdcx [sign[4]] bit, mcccx [mcom] bits, pwm state, and output transistors please refer to figure 41-26 for the output tran sistor assignment. v ssm mnc0p mnc0m v ddm static 1 static 1 pwm 0 pwm 0 v ddm v ssm mnc0p mnc0m static 1 static 1 pwm 1 pwm 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-27 preliminary?subject to change without notice figure 41-26. output transistor assignment table 41-21 illustrates the state of the out put transistors in diff erent states of the smc module. ??? means that the state of the output transist or is not controlled by the smc. table 41-21. state of output transistors in various modes mode mcccx [mcom] pwm duty 1 1 when in (dual) full mode and recirc=0, the pwm is 0 when the duty cycle is active and 1 when it is passive. when recirc = 1, the opposite is true. mcctl1 [recirc] mcdcx [sign[4]] t1 t2 t3 t4 mnc ym mnc yp off don?t care ? don?t care don?t care ? ? ? ? ? ? half h-bridge 0x0 active don?t care don?t care ? ? off on 0 ? half h-bridge 0x0 passive don?t care don?t care ? ? on off 1 ? half h-bridge 0x1 active don?t care don?t care off on ? ? ? 0 half h-bridge 0x1 passive don?t care don?t care on off ? ? ? 1 (dual) full 0x2 or 0x3 active 0 0 on off off on 0 1 (dual) full 0x2 or 0x3 passive 0 0 on off on off 1 1 (dual) full 0x2 or 0x3 active 0 1 off on on off 1 0 (dual) full 0x2 or 0x3 passive 0 1 on off on off 1 1 (dual) full 0x2 or 0x3 active 1 0 on off off on 0 1 (dual) full 0x2 or 0x3 passive 1 0 off on off on 0 0 (dual) full 0x2 or 0x3 active 1 1 off on on off 1 0 (dual) full 0x2 or 0x3 passive 1 1 off on off on 0 0 v ddm v ssm mncyp mncym t1 t2 t3 t4
pxd20 microcontroller reference manual, rev. 1 41-28 freescale semiconductor preliminary?subject to change without notice 41.4.1.3.5 dither bit ( mcctl0 [dith]) the purpose of the dither mode is to increase the minimum length of output pulses without decreasing the pwm resolution, in order to limit the pulse distortion in troduced by the slew rate control of the outputs. if dither mode is selected the output pattern will repeat after tw o timer counter overflows. for the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. to achieve the same output frame frequency, the presca ler of the smc module has to be set to twice the division rate if dither mode is sele cted; e.g., with the same prescaler di vision rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. the mcctl0 [dith] bit enables or disables the dither function. mcctl0 [dith] = 0: dither function is disabled. when mcctl0 [dith] is cleared and assumin g left aligned operation and mcctl1 [recirc] = 0, the pwm output will start at a logic lo w level at the beginning of the pw m period (motor controller timer counter = 0x000). the pwm output re mains low until the motor contro ller timer counter matches the 11-bit pwm duty cycle value mcdcx [duty]. when a match (output co mpare between motor controller timer counter and mcdcx [duty]) occurs, the pwm output will t oggle to a logic high level and will remain at a logic high leve l until the motor controller timer counter overflows (r eaches the contents of mcper [per] ? 1). after the motor controller timer c ounter resets to 0x000, the pwm output will return to a logic low level. this completes one pwm period. the pwm period repeats every mcper [per] counts of the motor controller timer counter. if mcdcx [duty] >= mcper [per], the output will be static low. if mcdcx [duty] = 0, the output will be continuously at a logic high level. the relationship between the motor controll er timer counter clock, motor controller timer counter value, and pwm output while mcctl0 [dith] = 0 is shown in figure 41-27 . figure 41-27. pwm output: mcctl0 [dith] = 0, mcccx [mcam] = 0x1, mcdcx [duty] = 100, mcper [per] = 200, mcctl1 [recirc] = 0 mcctl0 [dith] = 1: dither function is enabled please note if mcctl0 [dith] = 1, the bit mcper [per[0]] will be internally forced to 0 and read always as 0. when mcctl0 [dith] is set and assuming left aligned operation and mcctl1 [recirc] = 0, the pwm output will start at a logic low le vel at the beginning of the pwm peri od (when the motor controller timer counter = 0). the pwm output remain s low until the motor controller timer counter matches the 10-bit 0100 0 100 0 pwm output 1 period 200 counts 200 counts 1 period motor controller timer counter clock motor controller timer counter 199 199
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-29 preliminary?subject to change without notice pwm duty cycle value mcdcx [duty]. when a match (output compar e between motor controller timer counter and mcdcx [duty]) occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reach es the value defined by mcper [per[10:1]] ? 1). after the motor controller time r counter resets to 0x000, the pwm output will return to a logic low level. this completes the first half of the pwm pe riod. during the second half of the pwm period, the pwm output will remain at a logic low level until either the motor controller timer counter matches the 10-bit pwm duty cycle value mcdcx [duty] if mcdcx [duty[0]]= 0, or the motor controller timer counter matches the 10-bit pwm duty cycle value + 1 (the value of mcdcx [duty[10:1]] is incremented by 1 and is compared with the motor controller timer counter value) if mcdcx [duty[0]] = 1 for the corresponding channel. when a match occurs, the pwm output will toggle to a logic high level and will remain at a logi c high level until the motor controller timer counter overflows (reaches th e value defined by mcper [per[10:1]] ? 1). af ter the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this process will repeat every numbe r of counts of the moto r controller timer count er defined by the period register contents ( mcper [per]). if the output is neither set to 0% nor to 100% there will be four edges on the pwm output per pwm period in this case. th erefore, the pwm output compare function will alternate between mcdcx [duty] and mcdcx [duty] + 1 every half pwm period if mcdcx [duty[0]] for the corresponding channel is se t to 1. the relationship between the motor controller timer counter clock (f tc ), motor controller timer counter va lue, and left ali gned pwm output if mcctl0 [dith] = 1 is shown in figure 41-28 and figure 41-29 . figure 41-30 and figure 41-31 show right aligned and center aligned pwm operation re spectively, with dither feature enabled and mcdcx [duty[0]] = 1. please note: in the following examples, the mcper [per] value, which is, if mcctl0 [dith] = 1, always an even number. note the mcctl0 [dith] bit must be changed only if the smc is disabled (all channels disabled or peri od register cleared) to a void erroneous waveforms. figure 41-28. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x1, mcdcx [duty] = 31, mcper [per] = 200, mcctl1 [recirc] = 0 0 15 pwm output 16 0 100 counts motor controller timer counter motor controller timer counter clock 0 16 1 period 100 counts 15 99 99
pxd20 microcontroller reference manual, rev. 1 41-30 freescale semiconductor preliminary?subject to change without notice figure 41-29. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x1, mcdcx [duty] = 30, mcper [per] = 200, mcctl1 [recirc] = 0 . figure 41-30. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x2, mcdcx [duty] = 31, mcper [per] = 200, mcctl1 [recirc] = 0 figure 41-31. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x3, mcdcx [duty] = 31, mcper [per] = 200, mcctl1 [recirc] = 0 pwm output 1 period 100 counts motor controller timer counter motor controller timer counter clock 100 counts 015 16 0 0 16 15 99 99 0 84 pwm output 85 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 85 100 counts 84 99 99 0 84 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 100 counts 15 99 99
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-31 preliminary?subject to change without notice 41.4.2 pwm duty cycle the pwm duty cycle for the smc cha nnel x can be determined by dividi ng the decimal representation of the bits mcdcx [duty] by the decimal representation of the bits mcper [per] and multiplying the result by 100% as shown in equation 41-1 . eqn. 41-1 note x = pwm channel number = 0, 1, 2, 3 ... 11. this equa tion is only valid if mcdcx [duty] <= mcper [per] and mcper [per] is not equal to 0. whenever mcdcx [duty] >= mcper [per], a constant low level ( mcctl1 [recirc] = 0) or high level ( mcctl1 [recirc] = 1) wi ll be output. 41.4.3 motor controller counter clock source figure 41-32 shows how the pwm motor controller tim er counter clock source is selected. figure 41-32. motor controller counter clock selection the peripheral bus clock is the source for the motor controller counter prescaler. the motor controller counter clock rate, f tc , is set by selecting the appropriate prescaler value. the prescaler is selected with the mcctl0 [mcpre] bits. the smc channel frequency of operation can be calculated using equation 41-2 if mcctl0 [dith] = 0. eqn. 41-2 the smc channel frequency of ope ration can be cal culated using equation 41-3 if mcctl0 [dith] = 1. eqn. 41-3 effective pwm channel x % duty cycle duty mcper ------------ --------- 100% ? = 1 ???? 1/4 1/8 motor controller timer counter prescaler motor controller timer counter clock prescaler select mppre0, mppre1 11-bit motor controller timer counter peripheral bus clock f bus clock generator clk clocks and reset generator module motor controller timer counter clock f tc motor channel frequency (hz) f tc mcper m ? ----------------- -------------- = motor channel frequency (hz) f tc mcper m 2 ? ? -------------------- ------------------ =
pxd20 microcontroller reference manual, rev. 1 41-32 freescale semiconductor preliminary?subject to change without notice note both equations ar e only valid if mcper [per] is not equal to 0. m = 1 for left or right aligned mode, m = 2 for center aligned mode. table 41-22 shows examples of the smc channel frequenc ies that can be generated based on different peripheral bus clock frequencie s and the prescaler value. note due to the selectable slew rate contro l of the outputs, cl ipping may occur on short output pulses. 41.4.4 output switching delay in order to prevent large peak curr ent draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level tr ansitions on the smc outputs. the timing delay, t d , is determined by the mcccx [cd] bits in the corresponding channel control register and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. note a pwm channel gets disabled at the next timer counter overflow without notice of the switching delay. 41.4.5 operation in smc stop mode all module clocks are stoppe d and the associated port pins are set to their inactive state, which is defined by the state of the mcctl1 [recirc] bit. the smc modul e registers stay the same as they were prior to entering stop mode. therefore, after exiting from stop mode, the associat ed port pins will resume to the same functionality they had prior to entering stop mode. 41.4.6 short-circuit detection each pwm pin is equipped with a s hort-circuit detection f unction. hence, 24 instances (4 for each pwm module) of the short-ci rcuit detector exist. table 41-22. smc channel frequencies (hz), mcper [per] = 256, mcctl0 [dith] = 0, mcccx [mcam] = 0x2, 0x1 prescaler peripheral bus clock frequency 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz 1 62500 39063 31250 19531 15625 1/2 31250 19531 15625 9766 7813 1/4 15625 9766 7813 4883 3906 1/8 7813 4883 3906 2441 1953
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-33 preliminary?subject to change without notice each single short-circuit detector is a timer, meas uring the time during which th e signals pwm and fb are not equal (see figure 41-33 ). if this time is greater than or equal to the ti me represented by mcsdto [tout], then a short- circuit is assumed. to enable the short-circuit detector on a pin, ensure that the pin?s input buffer is enabled in the corresponding pad configuration register in the siu module. table 41-23. cross-reference pwm signal to short-circuit detector register bits short- circuit detector index sd pwm channel pin name related sd enable bit (see 41.3.2.7) related sd int enable bit (see 41.3.2.10) related sd int bit (see 41.3.2.13) 23 10 m5c0m mcsde2[sden[7]] mcsdien2[sdie[7]] mcsdi2[sdif[7]] 22 8 m4c0m mcsde2[sden[6]] mcsdien2[sdie[6]] mcsdi2[sdif[6]] 21 6 m3c0m mcsde2[sden[5]] mcsdien2[sdie[5]] mcsdi2[sdif[5]] 20 4 m2c0m mcsde2[sden[4]] mcsdien2[sdie[4]] mcsdi2[sdif[4]] 19 2 m1c0m mcsde2[sden[3]] mcsdien2[sdie[3]] mcsdi2[sdif[3]] 18 0 m0c0m mcsde2[sden[2]] mcsdien2[sdie[2]] mcsdi2[sdif[2]] 17 11 m5c1m mcsde2[sden[1]] mcsdien2[sdie[1]] mcsdi2[sdif[1]] 16 9 m4c1m mcsde2[sden[0]] mcsdien2[sdie[0]] mcsdi2[sdif[0]] 15 7 m3c1m mcsde1[sden[7]] mcsdien1[sdie[7]] mcsdi1[sdif[7]] 14 5 m2c1m mcsde1[sden[6]] mcsdien1[sdie[6]] mcsdi1[sdif[6]] 13 3 m1c1m mcsde1[sden[5]] mcsdien1[sdie[5]] mcsdi1[sdif[5]] 12 1 m0c1m mcsde1[sden[4]] mcsdien1[sdie[4]] mcsdi1[sdif[4]] 11 10 m5c0p mcsde1[sden[3]] mcsdien1[sdie[3]] mcsdi1[sdif[3]] 10 8 m4c0p mcsde1[sden[2]] mcsdien1[sdie[2]] mcsdi1[sdif[2]] 9 6 m3c0p mcsde1[sden[1]] mcsdien1[sdie[1]] mcsdi1[sdif[1]] 8 4 m2c0p mcsde1[sden[0]] mcsdien1[sdie[0]] mcsdi1[sdif[0]] 7 2 m1c0p mcsde0[sden[7]] mcsdien0[sdie[7]] mcsdi0[sdif[7]] 6 0 m0c0p mcsde0[sden[6]] mcsdien0[sdie[6]] mcsdi0[sdif[6]] 5 11 m5c1p mcsde0[sden[5]] mcsdien0[sdie[5]] mcsdi0[sdif[5]] 4 9 m4c1p mcsde0[sden[4]] mcsdien0[sdie[4]] mcsdi0[sdif[4]] 3 7 m3c1p mcsde0[sden[3]] mcsdien0[sdie[3]] mcsdi0[sdif[3]] 2 5 m2c1p mcsde0[sden[2]] mcsdien0[sdie[2]] mcsdi0[sdif[2]] 1 3 m1c1p mcsde0[sden[1]] mcsdien0[sdie[1]] mcsdi0[sdif[1]] 0 1 m0c1p mcsde0[sden[0]] mcsdien0[sdie[0]] mcsdi0[sdif[0]]
pxd20 microcontroller reference manual, rev. 1 41-34 freescale semiconductor preliminary?subject to change without notice figure 41-33. short-circuit detector overview pwm generator pwm fb timer tout mcsden[sden[sd]] mcsdin[sdif[sd]] motor pin i dff dff and synchronizer
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-35 preliminary?subject to change without notice figure 41-34. example for mcsdto [tout] = 4 ? hence, if pwm != fb, the timer starts counting if the short-circuit detector is enabled at least one clock cycle before (see mcsde0 , mcsde1 or mcsde2 ) ? if pwm == fb, the timer stops and is reset to the time-out value mcsdto [tout] in order to be ready for the next transaction ? if pwm != fb and the timer state is larger or equal mcsdto [tout], than ? one of the interrupt flags mcsdi0 [sdif], mcsde1 [sdif] or mcsdi2 [sdif] is set in order to flag a short-circuit. ? the interrupt flag is cleared by writing one, by reset or by disabling the short-circuit detector ? the timer is stopped and reloaded with the time-out value mcsdto [tout] in order to be ready for the next transaction ? if a short-circuit det ector is disabled ( mcsden [sden[ sd ]] == 0), the related short-circuit detector counter is halted and preloaded with the register value of mcsdto [tout]. the related bit in mcsdin [sdif[ sd ]] of this specific short-ci rcuit detector is set to 0. this means that, if all short-circuit detectors ar e disabled, all bits of mcsdin stay at 0. no interrupt from the detector can be generated independently of the interrupt mask in mcsdienn . ? in case of low power-modes, the state of the short-ci rcuit detector is frozen. after exit of the low power mode, the short-circ uit detector will resume operation from the previous state. if the short-circuit detector s hould restart with define d state (counter value = mcsdto [tout], than the related detector shall be disabled and enabled again. this will reload the counter with the mcsdto [tout] value and restart th e short-circuit detector. pwm fb_sample 4 2 1 04 counter mcsdin[sdif[sd ]] interrupt flag clk t_sample :sample and synchronization delay t_diff :delay between fb at pin and the internal pwm signal pwm :signal from motor controller fb at pin :this is the signal directly after the input driver of the pad s ignal fb_sample :pad signal after sampling and synchronization t_sample 3 fb at pin 4 t_diff
pxd20 microcontroller reference manual, rev. 1 41-36 freescale semiconductor preliminary?subject to change without notice the maximum time span which the timer can cover depends on the cloc k frequency f of the main clock. the maximum delay d covered by the counter is d = mcsdto [tout]* f. due to sampling and syn- chronization of the feedback signal, the value of mcsdto [tout] must always be larger than 2. the two synchronizer stages imply also, that a a short-circuit with a duration of less than or equal to 2 clock cycles cannot be detected. two special cases shall be highlighted: ? static short-circuit to ground and pwm signal = 1 see figure 41-35 : in this case, the enable of the short-circuit detector starts the sampli ng process and the interrupt bit is set mcsdto [tout]+1 cycles after enabling the short-circuit detector ? static short-circuit to vd d and pwm signal = 0 see figure 41-36 : in this case. the enable of the short-circuit detector starts the sampli ng process and the interrupt bit is set mcsdto [tout]+3 cycles after enabling the short-ci rcuit detector due to the sync hronizer which has been cleared during disable of the sh ort-circuit detector figure 41-35. static short-circuit, pwm signal always at 1 and fb always at 0, mcsdto [tout]=3 pwm=1 fb_sample=0 3 2 1 00 counter mcsdin[sdif[sd ]] interrupt flag clk t_sample :sample and synchronization delay t_diff :delay between fb at pin and the internal pwm signal pwm :signal from motor controller fb at pin :this is the signal directly after the input driver of the pad s ignal fb_sample :pad signal after sampling and synchronization 3 fb at pin=0 3 en
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 41-37 preliminary?subject to change without notice figure 41-36. static short-circuit, pwm signal always at 0 and fb always at 1, mcsdto [tout]=3 note the short-circuit detection block doe s not disable a port in case of a short-circuit. it is task of the micr ocontroller to manage the event of a short-circuit. 41.5 reset the smc is reset by system reset. al l associated ports are released, al l registers of the smc module will switch to their reset state as defined in section 41.3.2, register description . 41.6 interrupts the smc has one interrupt output which is the bitwis e or function of 25 individual interrupt request sources: ? one time counter overflow interrupt: an interrupt will be requested when the mcctl1 [mctoie] bit in is set and the running pwm frame is finished. the interrupt is cleared by either setting the mcctl1 [mctoie] bit to 0 or to write a one to the mcctl0 [mctoif] bit ? 24 interrupts for the short-circuit detection, one for each pwm pin: whenever a short-circuit is detected on one pwm pin and the s hort-circuit detector enable bit mcsden [sden[ sd ]] is set, than the related interrupt flag mcsdin [sdif[ sd ]] is set according to the mapping shown in table 41-23 . the interrupt flag in mcsdin [sdif[ sd ]] will also rise an external interrupt if the pwm=0 fb_sample=1 3 3 2 10 counter mcsdin[sdif[sd ]] interrupt flag clk t_sample :sample and synchronization delay t_diff :delay between fb at pin and the internal pwm signal pwm :signal from motor controller fb at pin :this is the signal directly after the input driver of the pad s ignal fb_sample :pad signal after sampling and synchronization 3 fb at pin=1 en due to synchronizer
pxd20 microcontroller reference manual, rev. 1 41-38 freescale semiconductor preliminary?subject to change without notice interrupt enable bit mcsdienn [sdie[ sd ]] is set. to clear the interrupt flag, either write a one into the related bit position mcsdin [sdif[ sd ]] or disable the related shor t-circuit detect or by writing zero to mcsden [sden[ sd ]]. if the short-circuit detector is enabled and a static short-circuit exists, then the mcsdin [sdif[ sd ]] flag will be asserted direct ly after clearing it, because the short-circuit detector is still enab led and will detect the short-circuit again. to avoid this behavior, disable the short-circuit detector channe l after detection of the short-circuit. figure 41-37. smc interrupt generation mcsdi0 mcsdi1 mcsdi2 mctoif mcsdie0 mcsdie1 mcsdie2 mctoie 25 bits 25 bits bitwise and or of all input bits 25 bits interrupt request to host
pxd20 microcontroller reference manual, rev. 1 42-1 chapter 42 stepper stall detect (ssd) 42.1 introduction 42.1.1 overview the ssd block connects to one stepper motor (sm) with two coils. it can be used to monitor the movement of the sm to detect that the attached gauge poi nter has reached the stal l position of the scale. basis of the movement detection is to drive one of the coil s and to integrate the back emf (electromotive force) induced in the other coil. this back emf is present only if the sm is rotating. therefore, if the integral of the back emf exceeds a certain threshold, th e sm is still rotating; othe rwise it can be regarded as being stalled. the ssd block shares the pins connected to the sm coils together with the motor controller block responsible for driving the sm in the main applicat ion (e.g. moving the gauge pointer to a certain position of the scale).
pxd20 microcontroller reference manual, rev. 1 42-2 figure 42-1.ssd overall block diagram the names of the sub blocks given in the diagra m above relate to the descriptions given in section 42.4.1, main building blocks of the ssd : ? ?analog block? relates to section 42.4.1.1, analog block . ? ?analog wrapper and port control? relates to section 42.4.1.2, analog wrapper + port control . analog block digital block sine cosine to/from stepper motor pads bis control analog wrapper + port control ?? - output ?? - fdbk register if ?? - output port control ips if port control offset cancellation down counter integration accumulator bis control ?? - fdbk
pxd20 microcontroller reference manual, rev. 1 42-3 ? ?register interface? relates to section 42.4.1.3, register interface . ? ?bis (blanking-integration sequen ce) control logic? relates to section 42.4.1.4, bis control . 42.1.2 features the most important features of the ssd block are listed below: ? programmable full step states according to 2 coil stepper motors (4 states). ? programmable integration polarity ? integration accumulator of 16 bits with programmable clock divider. ? programmable down c ounter (16 bit timer). ? 64 mhz bus clock: finest resolution in time down to 125 ns, maximum length of blanking or integration phase for this case is ~8.2 ms. ? 64 mhz bus clock: maximum length of blanking or integration phase is 1.05 s, resolution in time reduced to 16 ? s for this case. ? automatic sequence of blanki ng followed by integration (bis) triggered by the user. ? full flexibility over blanking a nd integration phase of the bis: ? separate down counter initializati on values and divider factors. ? separate interrupt flags and interrupt enable bits ? separate coil drive enable bits. ? polarity switching to cancel dc offset erro rs programmable. the down counter value for the integration phase can be divided by 2, 4 or 8 to switch the polarity durin g the integration phase. additionally the offset cancellation can be switched off completely. ? seamless changeover into or from ssd (stepper stall detect) mode: the coil control signals outside of the bis are fully programmable. 42.1.3 modes of operation this section describes the different modes of operation of the ssd block. 42.1.3.1 disabled mode in this mode the ssd block is disabl ed. none of the sm coils is driven nor one of th e coils sensed. this is the case if the rtze bit in the control register is cleared. 42.1.3.2 normal mode in this mode the ssd block needs exclusive control over the sm coils. this must be ensured on at the device level. setting the rtze bit in the control register is not sufficient since the ssd does not provide a global port enable signal. refer to section 42.4, functional description , for more details.
pxd20 microcontroller reference manual, rev. 1 42-4 42.1.3.3 power down modes when the ssd is disabled by the mode entry module, the analog block and the sy stem clocks driving the ssd blocks are disabled. 42.2 external signal description each of the four analog i/os of the ssd block is us ed either as the output of a half-bridge sourcing or sinking the current of the sm coil dr iven currently or - in case of acting as an input - the back emf of the non-driven coil with respect to an internally-generated refere nce voltage is supplied to the ?? -modulator of the analog block. the si gnal properties are given in table 42-1 . 42.3 memory map and register definition this section provides a detailed description of the re gisters of the ssd block. no te that all registers are 16 bits in width. there is no access on byte level. 42.3.1 memory map table 42-2 lists the registers of the ssd block. table 42-1. signal properties name port coil coil node i/o reset cosp cosp cosine plus analog i/o z cosm cosm minus analog i/o z sinp sinp sine plus analog i/o z sinm sinm minu sanalog i/oz table 42-2. block memory map offset register name (long) register name (short) access 1 1 note that r/w registers may contain some read-only or write-only bits. location 0x00 ssd control and status register control r/w on page 42-5 0x02 ssd interrupt flag and enable register irq r/w on page 42-7 0x04 ssd integrator accumulator register itgacc r on page 42-8 0x06 ssd down counter count register dcnt r on page 42-8 0x08 ssd blanking counter load register blncntld r/w on page 42-9 0x0a ssd integration counter load register itgcntld r/w on page 42-9 0x0c ssd prescaler register prescale r/w on page 42-10 0x0e reserved 2 2 read access provides 0x0000. no write allowed. n/a ?
pxd20 microcontroller reference manual, rev. 1 42-5 42.3.2 register summary figure 42-2 and table 42-3 below illustrate the different acce ss modes of some register bits. table 42-3 provides a key for regist er figures and tables. 42.3.3 register descriptions this section describes the individual bits of all the ssd registers. note that the details of the functional description linked to these bits is given in section 42.4, functional description . 42.3.3.1 ssd control and status register (control) figure 42-3 below describes the fields of th e main control (control) register: always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 42-2. key to register fields table 42-3. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect. register content is updated in hardware. w write only. if no read value is given any read access will provide undefined results. refer to description of individual bits for additional effects of read. r/w standard read/write bit. only software can change the bit?s value (other than a hardware reset). w1c write one to clear. a status bit that ca n be read, and is cleared by writing a one. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal.
pxd20 microcontroller reference manual, rev. 1 42-6 the function of the control register bits is shown in table 42-4 . offse t 0x00 access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 step rcir itgdir blndcl itgdcl rtze 0blnst itgst 0 0 0 sdcpu d_rsv d w trig reset0 0 0 0 0 0 0 0 0 0 0 000 0 0 figure 42-3. ssd control and status register (control) table 42-4. control register field description field description 15 trig - trigger blanking -> integration sequence (bis). 1 sequence of blanking -> integration is triggered. 0 no effect. 14-13 step - full step state. these bi ts determine which coil is driven for sm movement,. refer to table 42-11 for details of the step states. 00 select0 ? angle (east pole) state for the electromagnetic field in the sm. 01 select90 ? angle (north pole) state for the electromagnetic field in the sm. 10 select180 ? angle (west pole) state for the electromagnetic field in the sm. 11 select270 ? angle (south pole) state for the electromagnetic field in the sm. 12 rcir - blanking polarity for coil recirculation. refer to section 42.4, functional description, for details of the recirculation mode. 1 coil recirculation via low side transistors (vssm, analog gnd). 0 coil recirculation via high side transistors (vddm, analog supply voltage). 11 itgdir - direction (polarity) of integration. refer to section 42.4.1.4.3, dc offset cancellation , for details 10 blndcl - drive coil during blanking. 1 during the bis blanking phase the other coil is actually driven by the ssd block (genuine use case). 0 during the bis blanking phase the other coils is no t driven by the ssd. the sm will not move during blanking. 9 itgdcl - drive coil during integration and outside of any bis. 1 during the bis integration phase and outside of any bis the other coil is actually driven by the ssd block (genuine use case). outside of any bis the same coil is driven. 0 during the bis integration phase the other coils is not driven by the ssd. outside of any bis no coil is driven. the sm will not move during integration (not useful for ssd). 8 rtze - return to zero enable. this is in fact the enable bit of the ssd logic to take over control of the sm coils 1 . 1 control of the sm coils by the ssd block is enabled. 0 control of the sm coils by the ssd block is disabled. 6 blnst - blanking status. refer to section 42.1.3.2, normal mode , for details. 1 the ssd block is currently in the blanking phase of an ongoing bis. 0 the ssd block is not in the blanking phase of an ongoing bis. 5 itgst - integration status. refer to section 42.1.3.2, normal mode , for details. 1 the ssd block is currently in the integration phase of an ongoing bis. 0 the ssd block is not in the integration phase of an ongoing bis.
pxd20 microcontroller reference manual, rev. 1 42-7 42.3.3.2 interrupt enable and flag register (irq) figure 42-4 below describes the fields of the inte rrupt enable and flag (irq) register: the function of the irq register bits is shown in table 42-5 . 1 sdcpu - ?? -modulator power up. setting this bit enables the analog block of the ssd and enables the clocking of the port control logic of the digital part. 1 analog block of the ssd is enabled. 0 analog block of the ssd is not enabled. 0 d_rsvd - reserved bit.. this bit is writable but should be kept as value 0. 1 the application must switch off any other blocks possibly interfering with port control of the ssd block. offse t 0x02 access: user read/write 1514131211109876543210 r blnif itgif 00000 acov if blni e itgie 00 0 0 0 acov ie w w1c w1c w1c reset0000000000000000 figure 42-4. ssd interrupt flag and enable register (irq) table 42-5. irq register field description field description 15 blnif - blanking expired interrupt flag. 1 this flag is set when the bis blanking phase has expired. 0 no such event. 14 itgif - integration expired interrupt flag. 1 this flag is set when the bis integration phase has expired. 0 no such event. 8 acovif - accumulator overflow interrupt flag. 1 this flag is set when during the bis integration phase the integration logic attempted either to increment the itgacc register abov e 0x7fff or to decrement it below 0x8000. 0 no such event. 7 blnie - blanking expired interrupt enable. 1 a module interrupt will occur if the blnif bit is set. 0 the blnif flag will not trigger an interrupt on the ips_int output. table 42-4. control register field description (continued) field description
pxd20 microcontroller reference manual, rev. 1 42-8 42.3.3.3 integration accumulator register (itgacc) figure 42-5 below describes the fields of the inte gration accumulator (itgacc) register: the function of the itgacc register bits is shown in table 42-6 . 42.3.3.4 down counter register (dcnt) figure 42-6 below describes the fields of th e down counter (dcnt) register: the function of the dcnt register bits is shown in table 42-7 . 6 itgie - integration expired interrupt enable. 1 a module interrupt will occur if the itgif bit is set. 0 the itgif flag will not trigger an interrupt on the ips_int output. 0 acovie - accumulator interrupt enable. 1 a module interrupt will occur if the acovif bit is set. 0 the acovif flag will not trigger an interrupt on the ips_int output. offset 0x04 access: user read/write 1514131211109876543210 ritgacc w reset0000000000000000 figure 42-5. ssd integration accumulator register (itgacc) table 42-6. itgacc register field description field description 15-0 itgacc - integration accumulator readout value. this 2?s complement register represents the accumulator register of the back emf integrator of the ssd block. refer to the functional description of the integrator for further details. offset 0x06 access: user read/write 1514131211109876543210 r dcnt w reset0000000000000000 figure 42-6. ssd down counter register (dcnt) table 42-5. irq register field description (continued) field description
pxd20 microcontroller reference manual, rev. 1 42-9 42.3.3.5 blanking counter load register (blncntld) figure 42-7 below describes the fields of the bl anking counter load (blncntld) register: the function of the blncntld register bits is shown in table 42-8 . 42.3.3.6 integration counter load register (itgcntld) figure 42-8 below describes the fields of the inte gration counter load (itgcntld) register: the function of the itgcntld register bits is shown in table 42-9 . table 42-7. dcnt regist er field description field description 15-0 dcnt - down counter value. this register represents the actual value of the down counter in unsigned format. refer to the functional description of the integrator for further details. offset 0x08 access: user read/write 1514131211109876543210 r blncntld w reset0000000000000000 figure 42-7. ssd blan king counter load re gister (blncntld) table 42-8. blncntld register field description field description 15-0 blncntld - blanking count load value. this register is programmed with the number of down counter periods belonging to the blanking phase of the followi ng biss. number format is unsigned. refer to the functional description of the integrator for further details. programming all 0?s into the blncntld register bits disables blanking completely. offset 0x0a access: user read/write 1514131211109876543210 r itgcntld w reset0000000000000000 figure 42-8. ssd integration count er load register (itgcntld)
pxd20 microcontroller reference manual, rev. 1 42-10 42.3.3.7 ssd prescale and di vider register (prescale) figure 42-9 below describes the fields of the prescale and divider factor (prescale) register: the function of the prescale re gister bits is shown in table 42-10 below: table 42-9. itgcntld register field description field description 15-0 itgcntld - integration count load value. this regi ster is programmed with the number of down counter periods belonging to the integration phase of the foll owing biss. number format is unsigned. refer to the functional description of the integrator for further details. programming all 0?s into the itgcntld register bits disables integration completely. offset 0x0c access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r blndiv 0 itgdiv 00 offcnc 0 acdiv w reset0000000000000000 figure 42-9. ssd prescale and divider factor register (prescale) table 42-10. prescale register field description field description 14-12 blndiv - blanking counter clock divider select. t he frequency for updating the down counter in the blanking phase of the next biss is derived from the bus clock according to the formula = / (8 * 2 blndiv ) according to this formula the divider factors are: 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 10-8 itgdiv - integration counter clock divider select. the frequency for updating the down counter in the integration phase of the next biss is derive d from the bus clock according to the formula = / (8 * 2 itgdiv ) according to this formula the divider factors are: 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024
pxd20 microcontroller reference manual, rev. 1 42-11 42.4 functional description for all the descriptions given here it is assumed that the ssd block has gained exclusive control of the sm coils and the analog block is enabled appropriately. 42.4.1 main building blocks of the ssd the functional description given in th is chapter deals with the main f unctional blocks. it concentrates on the description of the implem ented functionality. refer to figure 42-1 for details. 42.4.1.1 analog block an overview of the analog block of the ssd block is given in figure 42-10 below. additionally the most important sub blocks of the digital part which are connected to the an alog blocks are shown in order to clarify the joint operation of the analog block and the digital part. 5-4 offcnc - offset cancellation polarity flip select. refer to section 42.4.1.4.3, dc offset cancellation . for details of the offset cancellation mechanism. the offcnc bits set the pr eset value of the internal counter which determines the polarity flips during the integration phase. the preset value is derived from the itgcntld register value with the following divider factor: 00 0: selected polarity remains unchanged for all the time of the integration phase. 01 2: 1st polarity switch (and possibly a succeedin g one) occurs after [itgcntld div 2] dcnt ticks. 10 4: 1st polarity switch and succeeding one s occur after [itgcntld div 4] dcnt ticks. 11 8: 1st polarity switch and succeeding one s occur after [itgcntld div 8] dcnt ticks. if the itgcntld register value cannot be divided by the required factor an additi onal polarity flip occurs with a duration corresponding to the bits shifted out. 2-0 acdiv - accumulator sample clock divider select. the accumulator sample clock is derived from the bus clock according to the formula =/(8*2 acdiv ) according to this formula the divider factors are: 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 the first itgacc register update occurs when (8 * 2 acdiv ) bus clocks have expired after the itgst bit has been set by the ssd block. table 42-10. prescale register field description (continued) field description
pxd20 microcontroller reference manual, rev. 1 42-12 figure 42-10. ssd block di agram, analog block main part of the analog block is the ?? -modulator. it is oper ational during the bis integration phase only (step 5 in section 42.4.2.2, details of the ssd measurement ). the clock to update the feedback path is derived from the bus clock using the acdiv setting. the 1-bit output value provided to the digital part is used to increment or decrement the itgacc register. sine coil cosine coil bus vddm cosp cosm t1 t2 t3 vssm vddm t4 vssm s1 s3 s2 s4 vddm sinp sinm t5 t6 t7 vssm vddm t8 vssm s5 s7 s6 s8 offset cancellation vddm vssm r2 r2 r1 c1 + ? + ? down counter load register sigma-delta modulator + ref. voltage generation p a d p a d p a d p a d integrator reference dac integration accumulator down counter prescaler accumulator prescaler dff ssd_1mot analog block clock signals bis control separate for blanking and integration shaded down counter blocks: + ? down counter obe to pads clock
pxd20 microcontroller reference manual, rev. 1 42-13 for the correct movement of the sm the sine and cosi ne coil connections to v ddm and vdds need to be set properly, depending from the a ngular position. this is achieved by enabling and disabling of the pad transistors t1 to t8. these pad transistors are not part of the ssd block, onl y the obe (output buffer enable) signals for the pads are provided. for the switch characteristics refer to section 42.4.1.2.1, transistor condition states . aside from the pad transistors the switches s1 to s8 determine which coil provides the back emf to the integrator in which polarity w.r.t. the reference vol tage. the switches are impl emented in the analog block of the ssd (denoted by shading them in the same manner like the analog block). the ?? -modulator is enabled by setting the sdcpu bit in the control register. to compensate for switching effects of the analog circui try the user must take into account sufficient start up time, described in section 42.5.1, analog block startup time , prior to starting the bis. 42.4.1.2 analog wrapper + port control this sub block controls the outputs to the coils and the inputs to the analog block. refer to figure 42-10 for details. the most relevant bits of the control regi ster belonging to that functional block are: ? step bits: these 2 bit v ector has two functions. one function is to determine which coil is driven and whic h coil is connected to the ?? -modulator. additionally the direction of the current flow is selected with these bits. for cloc kwise direction of the sm movement the value must be decremented and for counter-clo ckwise movement it must be incremented when advancing from one step setting to the next. ? blndcl: this bit is the enable of the supply vo ltage to be routed to the coil driven in the appropriate step setting during the blanking phase of an ongoing bis. ? itgdcl: this bit is the enable of the supply vol tage to be routed to the coil driven in the appropriate step setting during the integrat ion phase of an ongoing bis. additionally it determines the coil drive se tting outside of any bis. ? itgdir: this bit is rele vant only in the integrati on phase. together with th e step bits the polarity of the integration is determined by enabling or di sabling the appropriate an alog switches. refer to section 42.4.1.4.3, dc offset cancellation . these control bits are translated into the appropriate switching sche me of the pad transistors and the ?? -modulator switches describe d below. note that it must be ensure d at the device level that the ssd block has exclusive control over the analog pads connected to the sm coils. additionally it is a preconditi on that the rtze bit in the control register is set. 42.4.1.2.1 transistor condition states the pad transistors t1 to t8 are responsible for connecting the sm coils to the analog supply voltages vddm and vdds. table 42-11 below shows the pad tr ansistor condition states implemented in the analog block. in the table the columns have the following meaning: ? step denotes the setting of the corr esponding bits in the control register. ? itgst reflects the status indicat or of the bis integration phase.
pxd20 microcontroller reference manual, rev. 1 42-14 ? ?resulting dcoil? is the (bis state depe ndent) resulting coil drive setting. see table 42-12 for how this setting is derived from the value of the control register. ? rcir denotes the setting of the corr esponding bit in the control register. table 42-12 below shows the logic dependency of the resulting coil drive from the internal state of the ssd block and from the setting of the different coil control bits in the control register: table 42-11. transistor condition states 1 1 ?x? means ?don?t care? step itgst resulting dcoil rcirt1t2t3t4t5t6t7t8 remarks xx 1 0 x off off off off off off off off integration with no drive 00 0 0 0 off off off off on off on off blanking withno drive (rcir bit determines supply voltage for recirculation) 00 0 0 1 off off off off off on off on 01 0 0 0 on off on off off off off off 01 0 0 1 off on off on off off off off 10 0 0 0 off off off off on off on off 10 0 0 1 off off off off off on off on 11 0 0 0 on off on off off off off off 11 0 0 1 off on off on off off off off 00 0 1 0 on off off on on off on off cosine coil driven p->m 00 0 1 1 on off off on off on off on 00 1 1 x on off off on off off off off 01 0 1 0 on off on off on off off on sine coil driven p->m 01 0 1 1 off on off on on off off on 01 1 1 x off off off off on off off on 10 0 1 0 off on on off on off on off cosine coil driven m->p 10 0 1 1 off on on off off on off on 10 1 1 x off on on off off off off off 11 0 1 0 on off on off off on on off sine coil driven m->p 11 0 1 1 off on off on off on on off 11 1 1 x off off off off off on on off
pxd20 microcontroller reference manual, rev. 1 42-15 42.4.1.2.2 switch condition states the analog switches s1 to s8 are used to select the appropriate source and polar ity of the non-driven coil into the ?? -modulator for integration during the integrat ion phase of an ongoing bis. outside of the integration phase none of the switches is enabled. refer to table 42-13 below for details. note the value given in the column ?integration polarity? in table 42-13 is linked to the itgdir bit in the control register in the way described in section 42.4.1.4.3, dc offset cancellation , below. 42.4.1.3 register interface the register interface processes the ips accesses from the device level. access size is 32 bits, the ssd block supports 16- and 32-bit accesses. any write access on byte-level is ignored. table 42-12. generation of the ?resulting dcoil? blnst blndcl itgst itgdcl resulting dcoil remarks 0 x 0 0 0 no running bis itgdcl determines result 11 1 0 0 x 0 running bis in blanking phase blndcl determines result 11 0 x 1 0 0 running bis in integration phase itgdcl determines result 11 table 42-13. switch condition states itgst step (register bit) integration polarity (input to analog block) s1 s2 s3 s4 s5 s6 s7 s8 0 xx x open open open open open open open open 1 00 0 open open open open close open open close 1 00 1 open open open open open close close open 1 01 0 open close close open open open open open 1 01 1 close open open close open open open open 1 10 0 open open open open open close close open 1 10 1 open open open open close open open close 1 11 0 close open open close open open open open 1 11 1 open close close open open open open open
pxd20 microcontroller reference manual, rev. 1 42-16 all reserved registers provide 0x0000 on read. write access is not allowed. 42.4.1.4 bis control once triggered the sequence control logic walks through a single individua l bis. in the normal application one bis corresponds to a single step (90 ? movement of the sm). in detail the bis is implemented in the ssd block in the following way: ? each bis starts with setting the trig bit. ending a running bis manually is only possibly by clearing the rtze bit. ? if the blncntld register is set to a valu e other than 0x0000 the dcnt is loaded with (blncntld - 1) and is started using the blndiv bit setting for the clock divider. the blnst is set. the blanking phase of the bis is executed, the bl ndcl bit is used to determine whether one of the coils is driven during the blanking phase. if the appropriate number of dow n counter periods (equal to th e blncntld register value) expires the blnif is set, the interrupt is triggered according to the blnie bit and the blnst bit is cleared. ? if the itgcntld register is set to a valu e other than 0x0000 the dcnt is loaded with (itgcntld - 1) and is started usi ng the itgdiv bit setting for the clock divider. the itgst is set and the itgacc register is initialized with 0x0000. the integration phase of the bis is executed, the it gdcl bit is used to de termine whether one of the coils is driven during the integration phase. the ?? -modulator of the anal og block is functional and the itgacc register is updated. during the integration phase the polarity is switched according to the offcnc bits. if the appropriate number of down counter periods (equal to the itgc ntld register value) expires the itgif is set, the interrupt is triggered accord ing to the itgie bit and the itgst bit is cleared. the state of the ongoing bis can be m onitored by the following status bits: ? the blnst bit is set during the blanking phase exclusively. ? the itgst bit is set during the integration phase exclusively. when it is set, the bis control enables the ?? -modulator in the analog block together with the integrati on circuitry. as long as the integration phase is active the it gacc register content is modified depending from the output of the ?? -modulator. in the normal use case the end of the bis is the end of the integration phase. i ndependent from the time required by the software to detect and act upon the end of the bis the itgacc register is not changed after the end of th e integration phase. the sequence control logic itself ma kes use of the following sub blocks: 42.4.1.4.1 down counter the down counter is basically a timer with the divider factor (blndiv or itgdiv) and length (blncntld or itgcntld) determined by the current state of the bis. additionally to defining the
pxd20 microcontroller reference manual, rev. 1 42-17 length of the integration phase the itgcntld sett ing determines the dcnt value to switch the integration polarity for dc offset cancella tion depending from the offcnc bit setting. when the down counter re aches 0x0000 and the associat ed divider period has expi red the appropriate flag is set and the corresponding in terrupt is triggered dependi ng from the interrupt enable bit. note that polling the dcnt register for 0x0000 is misleading since the dcnt ti me out is reached at the end of the divider period belonging to the value of 0x0000. refer to section 42.6.3, watching intern al states of the ssd . table 42-14 below shows details how the blndiv/i tgdiv and blncntld/itgcntld settings determine the length and granularit y of the blanking and in tegration phase dependi ng from the bus clock frequency. 42.4.1.4.2 integration accumulator this is the fundamental sub block of the ssd, it is responsible for collecting the result of the back emf integration from the ?? -modulator located in the analog block. the only time when the value of the accumulator can change is during the integration phase of a bis. in terms of signal processing the itgacc register is the counterpart of the ?? -modulator in the analog block, working as the ?? -demodulator: depending from the acdiv bits in the prescale register the output of the analog block is samp led periodically and the content of the accumulator incremented or decremented. therefore the itgacc register in fact counts the ?imbalance? between 1 and 0 output samples from the analog block. the value of the itgacc register can change only during the integration phase of an ongoing bis. before the first update the content is initia lized to 0x0000 and starting from that it is incremented or decremented according to the ?? -modulator output. number format is two?s complement, if an overflo w (attempt to increment itgacc register value of 0x7fff) or an underflow (attempt to decrement it gacc register value of 0x8000) the acovif bit indicates the over-/underflow condition, the ssd interrupt is triggered if the acovie bit is set and the itgacc register values is not changed. for the rest of the integration phase of the current bis the itgacc register value does not change. reaching the accumulator end values without an over-/underflow condition does not prevent the itga cc register from incr ementing 0x8000 (-32768) or decrementing 0x7fff (+32767). table 42-15 below shows details how the acdiv setting determines the ?? -demodulator sampling clock w.r.t. the bus clock. the recomme nded setting for the sampling is a resulting clock between 500 khz and 2 mhz. therefore the acdiv values for sampling cloc k values in this recomm ended range are given: table 42-14. blanking and integration phase length vs. bus clock 1 1 numbers rounded appropriately bus clock 40 mhz 64 mhz 80 mhz blndiv/itgdiv 0 7 0 7 0 7 timing granularity 0.2 ? s 25.6 ? s0.125 ? s16 ? s0.1 ? s12.8 ? s max. length of bln/itg 13.107 m s 1.678 s 8.192 ms 1.049 s 6.554 ms 0.839 s
pxd20 microcontroller reference manual, rev. 1 42-18 42.4.1.4.3 dc offset cancellation due to deviations from th e mid point of the analog s upply voltages and other effect s in the hardware of the analog blocks a dc offset may be introduced into the output of the ?? -modulator. as a consequence of such a dc offset the value obtained in the integrat ion accumulator would depend from the ?direction? of the integration (e.g. accumulator increment for positive back emf in clockwise movement). the dc offset cancellation implemented in the ssd block can eliminate (or at least re duce) the influence of such a dc offset: when active the dc offset cancellation reverts tw o internal settings in the ssd block during the integration phase of the current bis: ? the input into the analog block controlling the integration polarity which sets the switch condition state (third column in table 42-13 ): initial value (when the integration starts at step 5 in section 42.4.2.2, details of the ssd measurement ) is the bit value given in the itgdi r register in the control register. ? the output of the ?? -modulator being applied to the integration accumulator (itgacc register): initially it is applied without cha nge to the integration accumulator. as a result the switch conditions in the analog circui try change the direction of the voltage representing the back emf measured by the ?? -modulator. but the change directi on of the itgacc register is maintained because the interpretation of the ?? -modulator output is reverted, too. the offset cancellation is implemen ted as an additional counter runni ng during the integration phase with the same clock setting like the dc nt register. the preset value for this counter is derived from the itgcntld register by shifting right by 0, 1, 2 or 3 bits, depending from the offcnc bit setting. clearing all the offcnc bits obvious ly disables the offset cancellation completely. note that increasing the number of flips improves the offset cancellation becaus e the different polarities are distributed equally over the complete integration phase (if itgcntld can be divided by the appropriate number). refer to figure 42-11 for more details. table 42-15. itgacc update clock vs. bus clock - recommended settings 1 1 numbers rounded appropriately bus clock 40 mhz 64 mhz 80 mhz acdiv 3?b010 3?b011 3?b 011 3?b100 3?b011 3?b100 divider factor 32 64 64 128 64 128 sampling frequency 1.25 mhz 625 khz 1.00 mhz 500 khz 1.25 mhz 625 khz update interval 0.8 ? s1.6 ? s1.00 ? s2.00 ? s0.8 ? s1.6 ? s
pxd20 microcontroller reference manual, rev. 1 42-19 figure 42-11. offset cancellation polarity distribution if the shift process shifts out ls bits from the itgcntld register (non-integer di vide) the number shifted out creates an additional polarity flip which lasts the appropriate number of dcnt update periods. 42.4.2 stepper stall detection measurement this part of the functional descript ion deals with the main intended use case of the ssd block, this is the detection of the scale end boundaries of the gauge pointer moved by the sm which, in turn, is driven by the ssd block. for details of th e related sub blocks refer to section 42.4.1, main building blocks of the ssd . 42.4.2.1 overview of the ssd measurement the generic flow of ssd measurement is given in figure 42-12 below, the numbers de noted at each step belong to the detailed explanations given in section 42.4.2.2, details of the ssd measurement . the two phases of the bis are executed in sequence: 1. blanking phase: since the non-driven coil used fo r measurement was driven in the previous step switching transients are induced when changing from the driven into the non-driven state. therefore both pins of the non-driven coil are connected to one of the analog supply voltages vddm or vssm (depending from the rcir bit) to allow recirculation of these transient currents. 2. integration phase: this is the actual meas urement where the itgacc register is changed according to the results of the ?? -modulator of the analog block. time of integration phase offcnc = 2???b offcnc = 2???b offcnc = 2???b offcnc = 2???b initial polarity setting reverted polarity setting sample down counter for itgcntld = 0x1fff 0x1fff 0x0x000 0x1bff 0x17ff 0x13ff 0x0fff 0x0bff 0x07ff 0x03ff
pxd20 microcontroller reference manual, rev. 1 42-20 figure 42-12. generic ssd flow 42.4.2.2 details of the ssd measurement this section describes in detail the steps introduced in figure 42-12 . note that it describes only the measurement process. the decision whether the stall position has been reached or another sm step is required must be made by the controlling cpu dependi ng from the measurement result. all control bits are assumed to have their (inact ive) reset values prior to ente ring the ssd measurement flow. the following paragraphs relate to one complete bis including the (optiona l) blanking phase followed by the integration phase: 1. start of measurement start of measurement 1 initialize ssd 2 start blanking 3 start integration 5 end of measurement 9 end of blanking? 4 end of integration? 6 yes no yes no stop integration 7 read integration result 8 bis executed automatically
pxd20 microcontroller reference manual, rev. 1 42-21 for proper usage of the ssd block it must have exclusive control over the coils belonging to the sm whose stall position must be de tected. this must be ensured at the device level. following this the ssd must be enabled by setting the rtze bit in the control register, this bit must be left asserted for the complete ssd flow. it is at this point in time that application-dependent control setti ngs are set which remain constant over the complete ssd flow. these settings cons ist of the integrate direction of the itgacc register, which is set by the itgdir bit and the di rection to advance the s tep setting (increment or decrement influence clockwise or counter-clo ckwise movement of the sm). additionally the prescale and the irq re gister must be programmed (it is not recommended to change the content of the prescale re gister during a running bis). 2. initialize ssd at this point the step bits are set according to the angular position of the sm for the current position. after programming the step bits the analog block can be enabled by setting the sdcpu bit. 3. start blanking this step starts with setting the trig bit together with the step bits initializing the complete bis for the next step. depending from th e direction of the rotation the pr evious step setting is either decremented or incremented, wrapping from 2?b11 to 2?b00 or vice versa. if the blndcl bit is set this step marks the start of the sm movement , during blanking both pins of the non-driven coil are connected either to vddm or vssm for reci rculation, depending from the rcir bit. the bus clock is divided accordingly to the blndiv bits to decrement the dcnt. th e blnst bit is set to allow the user to monitor the status. 4. end of blanking? the end of the blanking phase is automaticall y detected. if the dc nt reaches 0x0000 and the complete blanking time is expired the blnif flag is set and the inte rrupt triggered according to the blnie bit. the blnst bit is cleared. 5. start integration after the end of the blanking phase the ssd bloc k continues automaticall y with the integration phase: the itgcntld register is used to initialize the dcnt and is decrem ented according to the itgdiv bits setting. the driving coils is powered according to the itgdcl bit. during the integration phase the polarity flip for offset cancel lation is triggered according to the offcnc bits. the itgst bit is set to allow th e user to monitor the status. 6. end of integration? the down counter is monitored in the same way like in step 4. the itgif flag is set and the interrupt is triggered according to the itgie bit. the itgst bit is cleared. 7. stop integration on the expiration of the current bis the integration is stopped, the ?? -modulator is disabled, the itgacc register is frozen. note that the current to the coil dr iven by the ssd block continues according to the itgdcl and the step setting. 8. read integration result
pxd20 microcontroller reference manual, rev. 1 42-22 now the result of the back emf integration over the time set with the blncntld register value can be read from the itgacc register. 9. end of measurement depending from the result of the measurement th e ssd block now can be disabled by clearing the rtze bit or another m easurement can be started. any additi onal measurement should start from step 2. 42.4.3 additional modes of operation there are several addi tional modes how the ssd block can operate with the sm co ils. they are aside from the main use case. 42.4.3.1 blanking with no drive during blanking of one coil (refer to step 3 in section 42.4.2, stepper stall detection measurement ) the user can disable the drive of the ot her coil by not setting the blndcl bi t. since the sm has moved in the integration phase of the previous bis this means th at the sm movement is interrupted during blanking. this mode is not useful for ssd. 42.4.3.2 integration with no drive if the itgdcl bit is switched off the driving coil of the sm is not powered during the integration phase, the sm will not move. only the ?? -modulator output is integrated wi th the reference voltage setting belonging to that step. this mode makes no sense fo r stall detection, but it can be used for certain measurements of the analog sub blocks. 42.5 initialization information 42.5.1 analog block startup time no specific initialization af ter a hard reset or after leaving one of the power dow n modes is necessary, but the user should allow a suff icient startup time of th e analog block after hard re set or enabling of the ssd block to compensate switching transients. the st artup time specified for the analog block is 20 ? s. 42.5.2 analog block polarity switching time if the offset cancellation is used the polarity of the back emf measurem ent in the analog block is reverted during the integration phase. no te that the time for the ?? -modulator to achieve a stable output depends strongly from the external circuitry, e.g. coil inductance, parasitic capacitance of the leads. as an initial estimation for typical applications a ti me of maximum 10 ? s should be taken into account by the user.
pxd20 microcontroller reference manual, rev. 1 42-23 42.5.3 ssd startup the ssd block takes care of smooth tr ansitions between the different step s to avoid current glitches when the coil driven by the block (sine or cosine) changes. single-cycle glitches in the coil drive current at startup of the ssd flow can be avoided in the following way: ? program the step bits reflecting the current posi tion of the sm prior to the ssd flow with the sdcpu bit still cleared. ? after programming the step bits enable the analog block by setting the sdcpu bit. 42.6 application information this is additional information intended for use by the customer. 42.6.1 current flow examples figure 42-13 below shows the current flow for a co mplete sequence of the step bits for counter-clockwise movement in cluding the recirc ulation time: figure 42-13. full step sequence for counter-clockwise movement different examples of the current flow in the sm coil s for different settings of the control bits are given in figure 42-14 to figure 42-17 below: figure 42-14 below shows the recirculation at the beginning of step = 0. the co sine coil is driven in the direction p -> m and the sine coil is recirculated against vddm. 0 1 2 3 0 imax + _ imax 0 imax + _ imax sine coil current cosine coil current recirculation
pxd20 microcontroller reference manual, rev. 1 42-24 figure 42-14. current flow for blan king (step = 0, blndcl = 1, rcir = 0) in figure 42-15 below the recirculation at the beginning of the next bis for step = 1 with changed setting of the rcir bit is shown. the sine coil is driven again in p -> m direction and the cosine coil is recirculated against vssm. figure 42-15. current flow for blan king (step = 1, blndcl = 1, rcir = 1) in figure 42-16 below it is shown that for the next step (s tep = 2) the cosine coil is driven in reverse direction with respect to step = 0 (m -> p direction). because it is the integration phase of the bis, the sine coil is isolated from the analog suppl y voltages. instead, it is connected to the ?? -modulator (not shown). vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm
pxd20 microcontroller reference manual, rev. 1 42-25 figure 42-16. current flow for integration (step = 2, itgdcl = 1) figure 42-17 below shows that the sine coil is driven fo r step = 3 in reverse direction with respect to step = 1 (m -> p direction). again the other coil (cos ine) is isolated from the analog supply voltages because it is the integration phase of the current bis. figure 42-17. current flow for integration (step = 3, itgdcl = 1) 42.6.2 setting of the prescale register 42.6.2.1 timing resolution considerations set the acdiv bits to the lowest di vision factor possible, resulting in the highest possible clock frequency for the integration accumulator. this will give the most precise result. vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm
pxd20 microcontroller reference manual, rev. 1 42-26 setting the blndiv or itgdiv bi ts will influence the resoluti on of the down counter in the corresponding phase of the bis (fine resolution required for blanking) as well as the available (absolute) time interval that can be covered by the length of the dcnt register (must be l ong enough to cover almost one sm step movement for integrati on). due to the different prescaler se ttings for blanking and integration no compromise is necessary between fine resolution for bla nking and long time for in tegration when using high bus frequencies. it is recommended to select the setting with the best timing resolution for the blanking phase for the blndiv bit setting (lowest value). most likely a di fferent value must be chosen for the itgdiv bit setting, neverthele ss the lowest possible value should be chosen, too. note that in normal operation it shoul d not occur that the acovif bit in the irq register reads out to be set during the integration. if this happens the bit indicates that either an ove rflow or an underflow occurred in the itgacc register. the result should be discar ded because the setup of the ssd block was wrong for the current ssd attempt. 42.6.2.2 offset cancellation considerations note that the polarity switching for of fset cancellation like depicted in figure 42-11 is controlled by the dcnt register update which is update d depending from the itgdiv setti ngs. all the divider settings are powers of 2, so the distance in time between two dcnt regi ster updates is always an integer multiple or divider of the itgacc regi ster update, depending which divider f actor is greater than the other one. if the offset cancellation is used the measurement pol arity in the analog block is reverted at least once during the integration phase . as a consequence the ?? -modulator needs some time after each polarity flip to achieve a stable output. an estim ation for that time is given in section 42.5.2, analog block polarity switching time . if the itgacc register is updated before the ?? -modulator output is stable at least one count is incorrect. since the next polarit y flip takes place in the opposite direction this incorrect count will be compensated for by the following polarity flip. therefore it may be useful to add a small number of dcnt register updates to the integration phase to have an even num ber of polarity flips in the offset cancellation. another mean to improve accuracy is to adjust the dcnt register updates where the polarity switches occur with respect to the follo wing itgacc register update to al low enough settling time for the ?? -modulator output. 42.6.3 watching internal states of the ssd for some applications it might be required by the applicat ion to know the current state of an ongoing bis. it is recommended to do that by reading the blnst and the itgst bits of the control register. if necessary the dcnt register value may be read to know how far the dcnt register period has expired. do not poll the dcnt register value for 0x0000 to find out the end of the blanking or integration phase. aside from generating more cpu load than required th is introduces an inaccuracy. not earlier than the dcnt register divider period belonging to the 0x0000 value has expired th e complete blanking or integration phase has been processed.
pxd20 microcontroller reference manual, rev. 1 42-27 it should be kept in mind that the recommended way of operati on is to enable the appropriate interrupt flag instead of polling the ssd registers. 42.6.4 stepper motor transition considerations 42.6.4.1 ssd phase-in and phase-out prior to starting the ssd flow the sm gauge is usually moved in the proxi mity of the expected stall position using another sm driver module. to change the driving source of the sm without visible interruption to the ssd block it is essential for the user to replicate the coil drive setting valid at the end of the sm drive into the ssd control register. given that the transfer of the port control from the previous sm driver module to the ssd block can be done sufficiently fast the sm will not move but will start at a know position with the ssd flow. the same applies to the end of the ssd flow when the sm control is transferred to another module. it is essential for the application in this use case that the coil drive setting at th e end of the ssd flow is replicated in this other module. basically the seamless hand over of the sm coils to another block can be handled by appropriately programming the step bits and the itgdcl bit in th e control register prior to pass pad control to the ssd block. this ensures that one of the sm coil s is driven and the sm retains its position when the ssd block gets pad control. vice versa the step and itgdcl setting at the end of the last bis where the gauge stall was detected allow the user to replicate this specific coil driv e setting to the module taking over pad control from the ssd block. for more details refer to specific application notes describing the us age of the ssd block. 42.6.4.2 changing of ssd internal states depending from the applicat ion it may be required to lock the sm into the current angular position to prevent occasional movement prior to the next step. this is especially useful after the integration phase of a bis. to achieve this the internal logic of the ss d block does the following af ter the integration phase has expired: ? the coil drive setting of the in tegration phase is held active: th e itgdcl bit determines the coil drive; the coil and coil directi on is determined by the step bits. ? the undriven coil is set (back to) r ecirculation like in the blanking phase. this leaves both coils in a well-defined state, nevert heless the user should keep this time outside of the bis as short as possible to avoid visible interruptions of th e gauge movement. when changing to the next step within the ssd flow it should be noted that the update of the step bits should coincide (done in the same write to the control re gister) like the trigger of the bis by writing 1 into the trig bit. this ensures seamless changeover fr om one step to the next as well as immediate start of the bis when the coil driven has changed.
pxd20 microcontroller reference manual, rev. 1 42-28 42.6.5 legacy modes - separate blanking and integration phase despite the automatic bis it is still possible to us e the ssd block in a way similar to the old design. separate blanking and integration ph ases can be obtained very easily by setting the down counter preload value for the undesired phase to 0x0000. when the corr esponding bis is executed this phase is simply skipped. note that in this case the blnif bit will be importa nt for the user because its assertion marks the end of the blanking phase. to ease the programming of separa te blncntld and itgcntld regi ster values on-the-fly the two adjacent registers are placed into one single 32-bit access. therefore the user who wants to implement programmed-control switching betw een blanking and integration need s only one single 32-bit register write (to switch the down counter pr eload values) prior to the executi on of the blanking or integration phase.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-1 preliminary?subject to change without notice chapter 43 system integration unit lite (siul) 43.1 introduction this chapter describes the system in tegration unit lite (siul), which is used for the management of the pads and their configuration. it controls the multiplexi ng of the alternate functions used on all pads as well as being responsible for the management of the external interrupts to the device. 43.2 overview the system integration unit lite (siul) contro ls the mcu pad configuration, ports, general-purpose input and output (gpio) signals and external interrupts with trigger event configuration. figure 43-1 is a block diagram of the siul and its interfaces to other system components. the module provides the capability to configure, read, and wr ite to the device?s ge neral-purpose i/o pads that can be configured as either inputs or outputs. ? when a pad is configured as an input, the state of the pad (logic high or low) is obtained by reading an associated data input (g pdi or pgpdi) register. ? when a pad is configured as an output, the value dr iven onto the pad is determined by writing to an associated data output (gpdo, pg pdo or mpgdo) register. enabling the input buffers when a pad is configured as an output allows the actual state of the pad to be read. ? to enable monitoring of an output pad value, the pa d can be configured as both output and input so the actual pad value can be read back a nd compared with the expected value.
pxd20 microcontroller reference manual, rev. 1 43-2 freescale semiconductor preliminary?subject to change without notice figure 43-1. system integration unit lite block diagram 1 up to 128 pins in the 176-pin package; up to 150 pins in the 208-pin package; up to 177 pins on the 416-pin package 43.3 features the system integration unit lite supports these distinctive features: ?gpio ? gpio function on up to 185 unique i/o pins ? dedicated input and output re gisters for each gpio pin ? external interrupts ? 3 system interrupt vectors for up to 24 interrupt sources ? 16 programmable digi tal glitch filters ? independent interrupt mask ips bus data pad input io interrupt interrupt controller ips master - configuration - glitch filter pad config (iomuxc) pad cfg (pcrs) gpio functionality 185 1 185 1 185 1 24 4 mux pads 185 1 siul module interrupt functionality
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-3 preliminary?subject to change without notice ? edge detection ? system configuration ? pad configuration control ? special function control ? ddr pad configuration ? rsds pad configuration ? nexus pad configuration 43.4 external signal description most device pads support multiple device functions. pad configuration registers are provided to enable selection between gpio and other signals. these other si gnals, also referred to as alternate functions, are typically peripheral functions. gpio pads are grouped in ?ports,? with each port containing up to 16 pads. with appropriate configuration, all pins in a port can be read or written to in parallel with a single r/w access. note in order to use gpio port functionalit y, all pads in the port must be configured as gpio rather than as alternate functions. 43.4.1 detailed signal descriptions 43.4.1.1 general-purpose i/o pins (gpio[0:184]) the gpio pins provide general-purpose input a nd output function. the gpio pins are generally multiplexed with other i/o pin functions. each gpio input and output is separately cont rolled by an input (gpdi n_n ) or output (gpdo n_n ) register. 43.4.1.2 external interrupt request input pins (eirq[0:23]) 1 the eirq[0:23] are connected to the siu inputs. rising or falling edge events are enabled by setting the corresponding bits in the siu_ireer or the siu_ifeer register. table 43-1 lists the external interr upt pins used by the siul. 1. eirq[0:15] in the 176-pin package; eirq[0:18] in t he 208-pin package; eirq[0:23] in the 416-pin package
pxd20 microcontroller reference manual, rev. 1 43-4 freescale semiconductor preliminary?subject to change without notice 43.4.1.3 special functi on output pins configuration (pcr[185:281]) pcr registers exist for the special function pads. these typi cally have much more limited functionality than the gpio pads. 43.5 memory map and register description this section provides a detailed description of all registers accessible in the siul module. table 43-1. siul external interrupt mapping external irq flag pcr port package 176 208 416 irq_0 eif[0] pcr[0] pa[0] x x x eif[1] pcr[1] pa[1] x x x eif[2] pcr[8] pa[8] x x x eif[3] pcr[9] pa[9] x x x eif[4] pcr[16] pb[0] x x x eif[5] pcr[18] pb[2] x x x eif[6] pcr[27] pb[11] x x x eif[7] pcr[29] pb[13] x x x irq_1 eif[8] pcr[71] pf[1] x x x eif[9] pcr[79] pf[9] x x x eif[10] pcr[86] pg[0] x x x eif[11] pcr[87] pg[1] x x x eif[12] pcr[98] pg[12] x x x eif[13] pcr[129] pk[8] x x eif[14] pcr[131] pk[10] x x x eif[15] pcr[132] pk[11] x x x irq_2 eif[16] pcr[134] pl[1] x x eif[17] pcr[136] pl[3] x x eif[18] pcr[151] pm[4] x x eif[19] pcr[158] pm[11] x eif[20] pcr[162] pn[1] x eif[21] pcr[164] pn[3] x eif[22] pcr[172] pn[11] x eif[23] pcr[180] pp[3] x
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-5 preliminary?subject to change without notice 43.5.1 siu memory map table 43-2 gives an overview on the siul registers implemented. table 43-2. siul memory map address name description size (bits) location base (0xc3f9_0000) ? reserved ? base + 0x0004 midr1 mcu id register #1 32 on page 43-7 base + 0x0008 midr2 mcu id register #2 32 on page 43-8 base + (0x000c - 0x0013) ? reserved ? base + 0x0014 isr interrupt status flag register 32 on page 43-8 base + 0x0018 irer interrupt request enable register 32 on page 43-9 base + (0x001c - 0x0027) ? reserved ? base + 0x0028 ireer interrupt rising edge event enable 32 on page 43-9 base + 0x002c ifeer interrupt falling-edge event enable 32 on page 43-10 base + 0x0030 ifer ifer interr upt filter enable register 32 on page 43-11 base + (0x0034 - 0x003f) ? reserved ? base + 0x0040 - base + 0x01b1 pcr0?pcr184 1 pad configuration registers 0?184 16 on page 43-11 base + 0x01b2? base + 0x0272 pcr185?pcr281 pad configuration registers 185?281 (used for non-gpio and special functions) 16 on page 43-13 base + (0x0274?0x04ff) ? reserved ? base + 0x0500 - base + 0x052b psmi0_3? psmi50_53 pad selection for multiplexed inputs 32 on page 43-15 base + (0x052c?0x05ff) ? reserved ? base + 0x0600 - base + 0x06b8 gpdo0_3 - gpdo184_187 1 gpio pad data output register 32 on page 43-19 base + (0x06bc?0x07ff) ? reserved ? base + 0x0800 - base + 0x08b8 gpdi0_3 - gpdi184_187 1 gpio pad data input register 32 on page 43-20 base + (0x08bc?0x0bff) ? reserved ? base + 0x0c00 - base + 0x0c14 pgpdo0 - pgpdo5 parallel gpio pad data out register 32 on page 43-21 base + (0x0c18?0x0c3f) ? reserved ? base + 0x0c40 - base + 0x0c54 pgpdi0 - pgpdi5 parallel gpio pad data in register 32 on page 43-22 base + (0x0c58?0x0c7f) ? reserved ?
pxd20 microcontroller reference manual, rev. 1 43-6 freescale semiconductor preliminary?subject to change without notice note a transfer error will be issued when tr ying to access reserved register space. 43.5.2 register protection the individual registers of system integration unit lite are protected from accidental writes. the following registers are protected: ?irer ( interrupt request enable register ) ? ireer ( interrupt rising-edge event enable register ) ? ifeer ( interrupt falling-edge event enable register ) ?ifer ( interrupt filter enable register ), entire porta, portb[ 0:3] and portc[2:15] ? psmi[n] ( pad selection for multiplexed inputs ) ? ifmc[n] ( interrupt filter maximum counter ) ?ifpc ( interrupt filter clock prescaler ) ?pcr[n] ( pad configuration registers ) refer to appendix a, registers under protection, for details. 43.5.3 register description this section describes in a ddress order all the siul regi sters. each description incl udes a standard register diagram. details of register bit a nd field function follow the register diagrams, in bit or der. the numbering convention of register is msb=0, however the numbering of intern al field is lsb=0, e.g. partnum[5] = midr1[10]. base + 0x0c80 - base + 0x0cac mpgpdo0 - mpgpdo11 masked parallel gpio pad data out register 32 on page 43-23 base + (0x0cb0?0x0fff) ? reserved ? base + 0x1000 - base + 0x105c ifmc0 - ifmc23 1 interrupt filter maximum counter register 32 on page 43-24 base + (0x1060?0x107c) ? reserved ? base + 0x1080 ifcp interrupt filter clock prescaler register 32 on page 43-25 base + (0x1084 - 0x3fff) ? reserved ? 1 not all port pins are available in all packages. table 43-2. siul memory map (continued) address name description size (bits) location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-7 preliminary?subject to change without notice figure 43-2. key to register fields 43.5.3.1 mcu id register #1 (midr1) this register holds identificati on information about the device. always 1 always 0 r/w bit read - bit write - write 1 bit self - 0 n/a reads 1 reads 0 bit only bit only bit bit to clear w1c clear bit bit address: base + 0x0004 access: none 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r partnum[15:0] w reset 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r csp pkg[4:0] major_mask[3:0] minor_mask[3:0] w reset 0 1 0 0 or 1 depending on package 0 0 0 0 0 1 0 0 0 0 figure 43-3. mcu id register #1 (midr1) table 43-3. midr1 field descriptions field description pa rt n u m [15:0] mcu part number device part number of the mcu. 0101_0110_0100_0101: device with 2 mb flash memory for the full part number this field needs to be combined with midr2.partnum[0:7] csp always reads back 0 pkg[4:0] package settings can be read by software to determine the package type that is used for the particular device: 0b10001: 176-pin qfp 0b10101: 208-pin qfp 0b10100: 416-pin bga major_mask[3:0] major mask revision counter starting at 0x0. incremented eac h time when there is a resynthesis. minor_mask[3:0] minor mask revision counter starting at 0x0. incremente d each time a mask change is done.
pxd20 microcontroller reference manual, rev. 1 43-8 freescale semiconductor preliminary?subject to change without notice 43.5.3.2 mcu id register #2 (midr2) field description same as ss cm mcu id register #2 (see section 44.2.2, register description ). 43.5.3.3 interrupt status flag register (isr) this register holds the external interrupt flags. address: base + 0x0008 access: none 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rsf flash_size_1[3:0] flash_size_2[3:0] 0000000 w reset 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r partnum[23:16] 100ee 0001 w reset 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 figure 43-4. mcu id register #2 (midr2) table 43-4. midr2 field descriptions field description sf manufacturer 0: freescale semiconductor 1: reserved flash_size_1 coarse granularity for flash memory size needs to be added to the memory size indicated by flash_size_2 to calculate the actual memory size. 0b0111: 2 mb flash_size_2 fine granularity for flash memory size needs to be added to the memory size indicated by flash_size_1 to calculate the actual memory size. 0b0000: 0 x (flash_size_1 / 8) 0b0010: 2 x (flash_size_1 / 8) 0b0100: 4 x (flash_size_1 / 8) partnum ascii character in mcu part number 0x53: character ?s? (this device) ee data flash present 0: no data flash is present 1: data flash is present
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-9 preliminary?subject to change without notice 43.5.3.4 interrupt request enable register (irer) this register is used to enable the external interrupt messaging to the interrupt controller. 43.5.3.5 interrupt rising-edge event enable register (ireer) this register is used to enable rising-edge triggered events to be enabled on the corresponding external interrupt pads. address: base + 0x0014 access: user read/write (write 1 to clear) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eif 1 1 {eif[19], eif[15:14], eif[12:0]} in the 176-pin package; eif[18:0] in the 208-pin package; eif[23:20, 18:0] in the 416-pin package w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-5. interrupt status flag register (isr) table 43-5. isr field descriptions field description eif[x] external interrupt status flag x this flag can be cleared only by writing a 1. writin g a 0 has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 0: no interrupt event has occurred on the pad 1: an interrupt event as defined by ireer[x] and ifeer[x] has occurred address: base + 0x0018 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ire 1 1 {ire[19], ire[15:14], ire[12:0]} in th e 176-pin package; ire[18:0] in the 208- pin package; ire[23:20, 18:0] in the 416-pin package w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-6. interrupt request enable register (irer) table 43-6. irer field descriptions field description ire[x] external interr upt request enable x 1: a set eif[x] bit causes an interrupt request 0: interrupt requests from the corresponding eif[x] bit are disabled
pxd20 microcontroller reference manual, rev. 1 43-10 freescale semiconductor preliminary?subject to change without notice 43.5.3.6 interrupt falling-edge ev ent enable register (ifeer) this register is used to enable falling-edge trigge red events to be enabled on the corresponding external interrupt pads. note if both the iree and ifee bit is cleared for the same interrupt source, the interrupt status flag for the corres ponding external interr upt will never be set. address: base + 0x0028 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r iree 1 1 {iree[19], iree[15:14], iree[12:0]} in the 176-pin package ; iree[18:0] in the 208-pin package; iree[23:20, 18:0] in the 416-pin package w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-7. interrupt rising-edge event enable register (ireer) table 43-7. ireer field descriptions field description iree[x] enable rising-edge events to cause the eif[x] bit to be set. 1: rising-edge event is enabled 0: rising-edge event is disabled address: base + 0x002c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifee 1 1 {ifee[19], ifee[15:14], ifee[12:0]} in the 176-pin package; ifee[18:0] in the 208-pin package; ifee[23:20, 18:0] in the 416-pin package w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-8. interrupt falling-edge event enable register (ifeer) table 43-8. ifeer field descriptions field description ifee[x] enable falling-edge events to cause the eif[x] bit to be set. 1: falling-edge event is enabled 0: falling-edge event is disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-11 preliminary?subject to change without notice 43.5.3.7 interrupt filter enable register (ifer) this register is used to enable a digital filt er counter on the corresponding exte rnal interrupt pads to filter out glitches on the inputs. 43.5.3.8 pad configuration registers (pcr0?pcr184) the pad configuration regist ers allow configuration of the static electrical and functional characteristics associated with i/o pads. each pcr cont rols the characteristics of a single pad. note 16/32-bit access supported in addition to the bit map above, the following table 43-11 describes the pcr register depending on the pad type. the bits in shaded fields are not implemented for the particul ar i/o type. the pa field selecting address: base + 0x0030 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ife 1 1 ife[15:0] in the 176-pin package; ife[18:0] in t he 208-pin package; ife[23:0] in the 416-pin package w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-9. interrupt filter enable register (ifer) table 43-9. ifer field descriptions field description ife[x] enable digital glitch filter on the interrupt pad input. 1: filter is enabled 0: filter is disabled address: base + 0x0040 (pcr0)(185 registers) base + 0x0042 (pcr1) ... base + 0x01b0 (pcr184) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smc apc pa[1:0] obe ibe ode src[1:0] wpe wps w reset 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 reset value shown is for the most of the pcrs, however, some pcrs are initialized to different values dependent on the requirements of the device. see chapter 3, signal description, for the reset configurations of each pcr on this device. figure 43-10. pad configuration registers (pcrx)
pxd20 microcontroller reference manual, rev. 1 43-12 freescale semiconductor preliminary?subject to change without notice the number of alternate functions may or may not be present depending on th e number of alternate functions actually mapped on the pad. figure 43-11. pad configuration register (pcr) for the different pad types in pxd20 pad type 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 pad with slew rate control (f,m, and s) smc apc pa[1:0] obe ibe ode src[1:0] wpe wps pad with reduced slew rate control (smd) smc apc pa[1:0] obe ibe ode src [1] wpe wps pad with gpio and analog functionality (j) smc apc pa[1:0] obe ibe ode src[1:0] wpe wps table 43-10. pcrx field descriptions field description smc safe mode control this bit supports the overriding of the automatic de activation of the output buffer of the associated pad upon entering safe mode of the soc. 1: in soc safe mode, the output buffer remains functional. 0: in soc safe mode, the output bu ffer of the pad is disabled. apc analog pad control this bit enables the usage of the pad as analog input. 1: analog input path switch can be enabled by the adc. 0: analog input path from the pad is gated and can not be used. pa[1:0] pad output assignment this field is used to select the function to driv e the output of a multiplexed pad. note that for non-gpio functions the output buffer is automa tically enabled when the function is selected. 00: alternative mode 0: gpio. 01: alternative mode 1: see chapter 3, signal description 10: alternative mode 2: see chapter 3, signal description 11: alternative mode 3: see chapter 3, signal description note: number of bit depending of the number of actual alternate function. please refer to datasheet obe output buffer enable this bit enables the output buffer of the pad when the pad is in gpio mode. 1: output buffer of the pad is enabled when pa = 00. 0: output buffer of the pad is disabled when pa = 00. ibe input buffer enable this bit enables the input buffer of the pad. 1: input buffer of the pad is enabled. 0: input buffer of the pad is disabled.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-13 preliminary?subject to change without notice 43.5.3.9 pad configuration registers (pcr185?pcr281) the non-gpio and special functions pins have de dicated pad configurati on registers that allow configuration of the electrical characteristics associated with the pads. each pcr controls the characteristics of a single pad. ode open drain output enable this bit controls output driver configuration for th e pads connected to this signal. either open drain or push/pull driver configurations can be sele cted. this feature applie s to output pads only. 1: open drain enable signal is asserted for the pad. 0: open drain enable signal is negated for the pad. src[1:0] slew rate control this field controls the slew rate control output si gnals from the siul. the output signals are driven to the value of this field. the actual slew rates are defined by the implementation of the pad devices for a given soc. note: for low-power modes, keeping these bits asserted may result in more leakage. it is recommended to not drive these bits during low-power modes. wpe weak pull up/down enable this bit controls whether the weak pull up/d own devices are enabled/disabled for the pad connected to this signal. 1: weak pull device enabled for the pad. 0: weak pull device disabled for the pad. wps weak pull up/down select this bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 1: weak pull-up selected 0: weak pull-down selected figure 43-12. pad configuration regist er (pcr) definition for pcr185?281 pad type 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 nexus smc obe ibe ode src[1:0] wpe wps ddr smc ode src[2:0] wpe wps rsds smc ode src[1:0] wpe wps table 43-10. pcrx field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 43-14 freescale semiconductor preliminary?subject to change without notice it is important to configur e the slew rate control corr ectly for the ddr pads. see table 43-12 for appropriate configuration values. table 43-11. pcr185?281 field descriptions field description smc safe mode control this bit supports the overriding of the automatic de activation of the output buffer of the associated pad upon entering safe mode of the soc. 1: in soc safe mode, the output buffer remains functional. 0: in soc safe mode, the output bu ffer of the pad is disabled. obe output buffer enable this bit enables the output buffer of the pad in case the pad is in gpio mode. 1: output buffer of the pad is enabled when pa = 00. 0: output buffer of the pad is disabled when pa = 00. ibe input buffer enable this bit enables the input buffer of the pad. 1: input buffer of the pad is enabled. 0: input buffer of the pad is disabled. ode open drain output enable this bit controls output driver configuration for th e pads connected to this signal. either open drain or push/pull driver configurations can be sele cted. this feature applie s to output pads only. 1: open drain enable signal is asserted for the pad. 0: open drain enable signal is negated for the pad. src slew rate control this field controls the slew rate control output si gnals from the siul. the output signals are driven to the value of this field. the actual slew rates are defined by the implementation of the pad devices for a given soc. note: for low-power modes, keeping these bits asserted may result in more leakage. it is recommended to not drive these bits during low-power modes. wpe weak pull up/down enable this bit controls whether the weak pull up/d own devices are enabled/disabled for the pad connected to this signal. 1: weak pull device enabled for the pad. 0: weak pull device disabled for the pad. wps weak pull up/down select this bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 1: weak pull-up selected 0: weak pull-down selected table 43-12. pcr202-268 slew rate settings src2 src1 src0 mode 1 1 1 3.3 v sdr 1 1 0 1.8 v ddr2 full strength 101 n/a 100 n/a
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-15 preliminary?subject to change without notice 43.5.3.10 pad selection for multiplexe d inputs registers (psmi0_3?psmi50_53) the psmi registers control selection of the source pa d for input signals to on-chip modules. each psmi register applies to a single input signal. configure the psmi register s to select the pad on which the external input signal is connected. in order to multiplex different pads to the same peripheral input, the siul provides a register that controls the selection between th e different sources. 0 1 1 2.5 v ddr1 0 1 0 1.8 v ddr2 half strength 0 0 1 1.8 v low-power ddr full speed 0 0 0 1.8 v low power ddr half speed address: base + 0x0500 - 0x0534 (54 registers) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 padsel0 0 0 0 0 padsel1 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 padsel2 0 0 0 0 padsel3 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-13. pad selection for multiplexed inputs register (psmi0_3) table 43-13. psmi0_3 field descriptions field description padsel0 - 3, padsel4 - 7, ... padsel40 - 43 pad selection bits each padsel field selects the pad currently used for a certain input function. see table 43-14 . table 43-12. pcr202-268 slew rate settings (continued) src2 src1 src0 mode
pxd20 microcontroller reference manual, rev. 1 43-16 freescale semiconductor preliminary?subject to change without notice table 43-14. peripheral input pin selection psmi register siul address offset peripheral input mapping of input pin to peripheral input 1 psmi[0] 0x500 canrx_0 0:pcr[17] 1:pcr[135] psmi[1] 0x501 canrx_1 0:pcr[26] 1:pcr[133] psmi[2] 0x502 canrx_2 0:pcr[150] 1:pcr[157] 2:pcr[179] psmi[3] 0x503 pdi_pclk 0:pcr[119] 1:pcr[142] 2:pcr[156] psmi[4] 0x504 viu[0]_pdi8 0:pcr[123] 1:pcr[163] psmi[5] 0x505 viu[1]_pdi9 0:pcr[124] 1:pcr[164] psmi[6] 0x506 viu[2] _pdi10 0:pcr[125] 1:pcr[171] psmi[7] 0x507 viu[3] _pdi11 0:pcr[126] 1:pcr[172] psmi[8] 0x508 viu[4] _pdi12 0:pcr[127] 1:pcr[179] psmi[9] 0x509 viu[5] _pdi13 0:pcr[118] 1:pcr[137] 2:pcr[152] psmi[10] 0x50a viu[6] _pdi14 0:pcr[120] 1:pcr[138] 2:pcr[153] psmi[11] 0x50b viu[7] _pdi15 0:pcr[104] 1:pcr[122] 2:pcr[139] psmi[12] 0x50c viu[8] _pdi16 0:pcr[75] 1:pcr[140] 2:pcr[154] psmi[13] 0x50d viu[9] _pdi17 0:pcr[76] 1:pcr[141] 2:pcr[155] psmi[14] 0x50e pdi_de 0:pcr[98] 1:pcr[108] 2:pcr[180] psmi[15] 0x50f dspi1_ss 0:pcr[43] 1:pcr[98]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-17 preliminary?subject to change without notice psmi[16] 0x510 emios0[8] 0:pcr[50] 1:pcr[106] 2:pcr[156] psmi[17] 0x511 emios0[9] 0:pcr[49] 1:pcr[55] 2:pcr[107] psmi[18] 0x512 emios0[10] 0:pcr[56] 1:pcr[116] psmi[19] 0x513 emios0[11] 0:pcr[57] 1:pcr[115] 2:pcr[181] psmi[20] 0x514 emios0[12] 0:pcr[58] 1:pcr[114] psmi[21] 0x515 emios0[13] 0:pcr[59] 1:pcr[113] 2:pcr[182] psmi[22] 0x516 emios0[14] 0:pcr[60] 1:pcr[112] psmi[23] 0x517 emios0[15] 0:pcr[61] 1:pcr[111] 2:pcr[183] psmi[24] 0x518 emios0[16] 0:pcr[51] 1:pcr[110] 2:pcr[157] psmi[25] 0x519 emios0[17] 0:pcr[1] 1:pcr[113] 2:pcr[173] psmi[26] 0x51a emios0[18] 0:pcr[0] 1:pcr[112] 2:pcr[174] psmi[27] 0x51b emios0[19] 0:pcr[9] 1:pcr[111] 2:pcr[175] psmi[28] 0x51c emios0[20] 0:pcr[8] 1:pcr[110] 2:pcr[176] psmi[29] 0x51d emios0[21] 0:pcr[86] 1:pcr[109] 2:pcr[177] psmi[30] 0x51e emios0[22] 0:pcr[87] 1:pcr[108] 2:pcr[178] table 43-14. peripheral input pin selection (continued) psmi register siul address offset peripheral input mapping of input pin to peripheral input 1
pxd20 microcontroller reference manual, rev. 1 43-18 freescale semiconductor preliminary?subject to change without notice psmi[31] 0x51f emios0[23] 0:pcr[52] 1:pcr[109] 2:pcr[158] psmi[32] 0x520 emios1[8] 0:pcr[46] 1:pcr[104] 2:pcr[118] psmi[33] 0x521 emios1[9] 0:pcr[106] 1:pcr[120] 2:pcr[127] psmi[34] 0x522 emios1[10] 0:pcr[28] 1:pcr[123] 2:pcr[143] psmi[35] 0x523 emios1[11] 0:pcr[29] 1:pcr[124] 2:pcr[144] psmi[36] 0x524 emios1[12] 0:pcr[125] 1:pcr[131] 2:pcr[145] psmi[37] 0x525 emios1[13] 0:pcr[126] 1:pcr[132] 2:pcr[146] psmi[38] 0x526 emios1[14] 0:pcr[74] 1:pcr[107] 2:pcr[122] psmi[39] 0x527 emios1[15] 0:pcr[75] 1:pcr[77] 2:pcr[116] psmi[40] 0x528 emios1[16] 0:pcr[47] 1:pcr[76] 2:pcr[154] psmi[41] 0x529 emios1[17] 0:pcr[115] 1:pcr[119] 2:pcr[149] psmi[42] 0x52a emios1[18] 0:pcr[25] 1:pcr[121] 2:pcr[139] psmi[43] 0x52b emios1[19] 0:pcr[24] 1:pcr[70] 2:pcr[140] psmi[44] 0x52c emios1[20] 0:pcr[23] 1:pcr[71] 2:pcr[141] table 43-14. peripheral input pin selection (continued) psmi register siul address offset peripheral input mapping of input pin to peripheral input 1
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-19 preliminary?subject to change without notice 43.5.3.11 gpio pad data output registers (gpdo0_3 - gpdo184) these registers can be used to set or clear a single gpio pa d with byte access. the gpio pad data output re gisters are a group of 185 one- byte registers used to set or clear the logic value on their associated pads. each word contains four registers. the word beginning at base + 0x0600 contains gpdo0 - gpdo3, the word beginning at base + 0x0604 contains gpdo3 - gpdo07, and so on. psmi[45] 0x52d emios1[21] 0:pcr[73] 1:pcr[103] 2:pcr[142] psmi[46] 0x52e emios1[22] 0:pcr[114] 1:pcr[135] 2:pcr[152] psmi[47] 0x52f emios1[23] 0:pcr[48] 1:pcr[136] 2:pcr[153] 3:pcr[155] psmi[48] 0x530 i2c_scl_1 0:pcr[1] 1:pcr[77] 2:pcr[132] psmi[49] 0x531 i2c_sda_1 0:pcr[0] 1:pcr[74] 2:pcr[131] psmi[50] 0x532 lin1_rxd 0:pcr[28] 1:pcr[78] psmi[51] 0x533 lin2_rxd 0:pcr[128] 1:pcr[157] 2:pcr[163] psmi[52] 0x534 lin3_rxd 0:pcr[150] 1:pcr[171] psmi[53] 0x535 evti 0:pcr[80] 1:evti 1 connecting a peripheral input to a pad requires assigning both the psmi value for the peripheral input and the pad assignment in the siu_ pcr register for that signal. table 43-14. peripheral input pin selection (continued) psmi register siul address offset peripheral input mapping of input pin to peripheral input 1
pxd20 microcontroller reference manual, rev. 1 43-20 freescale semiconductor preliminary?subject to change without notice 43.5.3.12 gpio pad data input registers (gpdi0_3?gpdi184) these registers can be used to read the gpio pad data with a byte access. the gpio pad data input re gisters are a group of 185 one- byte registers used to set or clear the logic value on their associated pads. each word contains four registers. the word beginning at base + 0x0600 contains gpdi0 - gpdi3, the word beginning at base + 0x0604 contains gpdi3 - gpdi07, and so on. address: base + 0x0600 - 0x06b8 (4 7 registers) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 pdo [0] 0 0 0 0 0 0 0 pdo [1] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 pdo [2] 0 0 0 0 0 0 0 pdo [3] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-14. port gpio pad data output register 0 - 3 (gpdo0_3) table 43-15. gpdo0_3 field descriptions field description pdo[x] pad data out this bit stores the data to be driven out on the ex ternal gpio pad controlled by this register. 1: logic high value is driven on the corresponding gpio pad when the pad is configured as an output 0: logic low value is driven on the corresponding gpio pad when the pad is configured as an output
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-21 preliminary?subject to change without notice 43.5.3.13 parallel gpio pad data out registers (pgpdo0?pgpdo5) the input/output ports are construc ted such that they contain 16 gpio pins, for example porta[0..15]. parallel port registers for input (p gpdi) and output (pgpdo) are provided to allow a comp lete port to be written or read in one operation, depende nt on the individual pad configuration. writing a parallel pgpdo register di rectly sets the associated gpdo regi ster bits. there is also a masked parallel port output register allo wing the user to determine which pins within a port are written. while very convenient and fast, this approach does ha ve implications regarding current consumption for the device power segment containing the port gpio pads . toggling several gpio pins simultaneously can significantly increase current consumption. warning caution must be taken to avoid ex ceeding maximum current thresholds when toggling multiple gpio pins si multaneously. please refer to data sheet. address: base + 0x0800 - 0x08b8 (47 registers) access: user read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 pdi [0] 0 0 0 0 0 0 0 pdi [1] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 pdi [2] 0 0 0 0 0 0 0 pdi [3] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-15. port gpio pad data input register 0 - 3 (gpdi0_3) table 43-16. gpdo0_3 field descriptions field description pdi[x] pad data in this bit stores the value of the external gpio pad associated with this register. 1: the value of the data in signal for the corresponding gpio pad is logic high 0: the value of the data in signal for the corresponding gpio pad is logic low
pxd20 microcontroller reference manual, rev. 1 43-22 freescale semiconductor preliminary?subject to change without notice note it is important to note the bit orderi ng of the ports in the parallel port registers. the most significant bit of the parallel port register corresponds to the least significant pin in the port. 43.5.3.14 parallel gpio pad data in register (pgpdi0?pgpdi5) the siu_pgpdi registers are simila r in operation to the pgpdo regist ers, described in the previous section ( section 43.5.3.13, parallel gpio pad da ta out register s (pgpdo0?pgpdo5) ) but they are used to read port pins simultaneously. note the port pins to be read need to be c onfigured as inputs but even if a single pin within a port has ibe set, then you can still read that pin using the parallel port register. however, this do es mean you need to be very careful. reads of pgpdi registers are equi valent to reading the corresponding gpdi registers but significantly faster since as many as two ports can be read si multaneously with a single 32-bit read operation. address: base + 0x0c00 - 0x0c14 (6 registers) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ppdo[x][0:15] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ppdo[x][16:31] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-16. parallel gpio pad data out register (pgpdo0) table 43-17. pgpdo0_5 field descriptions field description ppdo[x] parallel pad data out write or read the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bit-wise gpio pad data output registers (g pdo0_3 - gpdo184). the x and bit index define which ppdo register bit is equivalent to which pdo register bit according to the equation ppdo[x][y] = pdo[(x*32)+y] where x is the pgpdo register number (0..5) and y is the bit number within that register (0..31).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-23 preliminary?subject to change without notice note it is important to note the bit orderi ng of the ports in the parallel port registers. the most significant bit of the parallel port register corresponds to the least significant pin in the port. 43.5.3.15 masked parallel gpio pad data out regi ster (mpgpdo0?mpgpdo11) the mpgpdo registers are similar in ope ration to the pgpdo ports described in section 43.5.3.13, parallel gpio pad data ou t registers (pgpdo0?pgpdo5), but with two significant differences: ? the mpgpdo registers support masked port-wide changes to the data out on the pads of the respective port. masking effectively allows selectiv e bitwise writes to the full 16-bit port. ? each 32-bit mpgpdo register is associated to only one port. note the mpgpdo registers may only be acc essed with 32-bit writes. 8-bit or 16-bit writes will not modify any bits in the register and wi ll cause a transfer error response by the module. read accesses return ?0?. address: base + 0x0c40 - 0x0c54 (6 registers) access: user read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ppdi[x][0:15] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ppdi[x][16:31] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-17. parallel gpio pad data in register (pgpdi0) table 43-18. pgpdi0_5 field descriptions field description ppdi[x] parallel pad data in read the current pad value. accesses to this register location are coherent with accesses to the bit-wise gpio pad data input registers (gpdi0_3?gpdi184). the x and bit index define which ppdi register bit is equivalent to which pdi register bit according to the equation: ppdi[x][y] = pdi[(x*32)+y] where x is the pgpdi register num ber (0..5) and y is the bit number within that register (0..31).
pxd20 microcontroller reference manual, rev. 1 43-24 freescale semiconductor preliminary?subject to change without notice note it is important to note the bit orderi ng of the ports in the parallel port registers. the most significant bit of the parallel port register corresponds to the least significant pin in the port. warning toggling several ios at the same time can significantly increase the current in a pad group. caution must be take n to avoid exceeding maximum current thresholds. please refer to data sheet. 43.5.3.16 interrupt filter maximum counter registers (ifmc0?ifmc23) these registers are used to confi gure the filter counter associated with each digita l glitch filter. note for the pad transition to trigger an interr upt it must be stea dy for at least the filter period. address: base + 0x0c80 - 0x0ca8 (1 2 registers) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w mask[x][0:15] reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w mppdo[x][0:15] reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-18. masked parallel gpio pad data out register (mpgpdo0) table 43-19. mpgpdo0_3 field descriptions field description mask[x][0:15] mask field each bit corresponds to one data bit in the mp pdo[x] register at the same bit location. 1: the associated bit value in the mppdo[x] field is written 0: the associated bit value in the mppdo[x] field is ignored mppdo[x][0:15] masked parallel pad data out write the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bit-wise gpio pad data output registers (g pdo0_3 - gpdo184). the x and bit index define which mppdo register bit is equivalent to which pdo register bit according to the following equation: mppdo[x][y] = pdo[(x*16)+y]
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-25 preliminary?subject to change without notice 43.5.3.17 interrupt filter cloc k prescaler register (ifcpr) this register is used to configure a clock prescaler which is used to select the clock for all digital filter counters in the siul. address: base + 0x1000 - 0x105c (24 registers) access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 maxcntx[3:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-19. interrupt filter maximum counter registers (ifmc0 - ifmc15) table 43-20. ifmc field descriptions field description maxcntx [3:0] maximum interrupt filter counter setting. filter period = t(irc) ? ifcp ? maxcntx + n ? t(irc) ? ifcp where n is a synchronisation uncertainty between -1 and 3 maxcntx can be 3 to 15. maxcnt < 3 causes the filter to be bypassed. t(irc): basic filter clock period: 62.5 ns (f = 16 mhz) address: base + 0x1080 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 ifcp[3:0] w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 43-20. interrupt filter clock prescaler register (ifcpr)
pxd20 microcontroller reference manual, rev. 1 43-26 freescale semiconductor preliminary?subject to change without notice 43.6 functional description 43.6.1 general this section provides a functional descripti on of the system integration unit lite. 43.6.2 pad control the siul controls the configurat ion and electrical characteristic of the device pads. it provides a consistent interface for all pads, both on a by-port a nd a by-bit basis. the pad configuration registers (pcr n , see section 43.5.3.8, pad configurat ion registers (pcr0?pcr184) ) allow software control of the static electrical char acteristics of external pins with a single write. these are used to configure the following pad features: ? open drain output enable ? slew rate control ? pull control ? pad assignment ? control of analog path switches ? safe mode behavi or configuration 43.6.3 general purpose input and output pads (gpio) the siul allows each pad to be c onfigured as either a ge neral purpose input out put pad (gpio), and as one or more alternate functions (i nput or output), the function of wh ich is normally determined by the peripheral that will use the pad. the siul manages 185 gpio pads organized as ports th at can be accessed for da ta reads and writes as 32-bit, 16-bit or 8-bit. as shown in figure 43-21 , all port accesses are identical with each read or write being performed only at a different location to access a different port width. table 43-21. ifcpr field descriptions field description ifpc [3:0] interrupt filter clock prescaler setting prescaled filter clock peri od = t(irc) x (ifcp + 1) t(irc): basic filter clock period: 62.5 ns (f = 16 mhz) ifcp can be 0 to 15
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 43-27 preliminary?subject to change without notice figure 43-21. data port example arrangement showing configuration for different port width accesses this implementation requires that the registers are arranged in such a wa y as to support this range of port widths without having to split reads or writes into multiple accesses. the siul has separate data input (gpdi n_n , see section 43.5.3.12, gpio pad data input registers (gpdi0_3?gpdi184) ) and data output (gpdo n_n , see section 43.5.3.11, gpio pad data output registers (gpdo0_3 - gpdo184) ) registers for all pads, allowing the po ssibility of reading back an input or output value of a pad directly. this supports the ability to validate what is present on the pad rather than simply confirming the value that wa s written to the data register by accessing the data input registers. data output registers allow an output pad to be driv en high or low (with the op tion of push-pull or open drain drive). input registers are read-onl y and reflect the respective pad value. when the pad is configured to use one of its alternat e functions, the data input va lue reflect the respective value of the pad. if a write operation is performed to the data output regi ster for a pad configured as an alternate function (non gpio), this wr ite will not be reflected by the pad value until reconfigured to gpio. the allocation of what i nput function is connected to the pin is defined by the psmi registers (pcr n , see section 43.5.3.8, pad configurati on registers (pcr0?pcr184) ). 43.6.4 external interrupts the siul supports 24 external interrupts, eirq0?eir q23. the mapping of these interrupts to external pins is summarized in table 43-1 and described in full detail in chapter 3, signal description . the siul supports three interrupt v ectors to the interrupt controller. each vector interrupt has eight external interrupts combined together with the presence of flag generating an interrupt for that vector if enabled. all of the external interrupt pads within a si ngle group have equal priority. refer to figure 43-22 for an overview of the exte rnal interrupt implementation. 31 23 siu base+ 0x0000 15 7 0 siu base+ 15 7 0 siu base+ 15 7 0 siu base+ 70 0x0003 siu base+ 70 0x0002 siu base+ 70 0x0001 siu base+ 70 0x0000 0x0002 0x0000 32-bit port 16-bit port 16-bit port 8-bit port 8-bit port 8-bit port 8-bit port
pxd20 microcontroller reference manual, rev. 1 43-28 freescale semiconductor preliminary?subject to change without notice figure 43-22. external interrupt pad diagram 1 bit count is [0:15] in the 176-pin package, [0:18] in the 208-pin package, and [0:23] in the 416-pin package. 43.6.4.1 external interrupt management each interrupt can be enabled or disabled independently. this can be performed using the interrupt request enable register (irer - section 43.5.3.4, interrupt request enable register (irer) ). a pad defined as an external in terrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges bei ng active. a setting of having both e dge events disabled is reserved and should not be configured. extern al interrupts require that the asso ciated input buffer for the pad is enabled (pcr[ibe]=1). the active eirq edge is controlled through the configuration of the registers ireer and ifeer. each external interrupt supports an individual flag which is held in the flag register (isr - section 43.5.3.3, interrupt status flag register (isr) ). this register is a clear -by-write-1 register type, preventing inadvertent overwriting of other flags in the same register. 43.7 pin muxing for pin muxing, please refer to chapter 3, signal description, of this document. interrupt controller int vectors eif[15:8] 1 eif[7:0] ire[23:0] 1 pads iree[23:0] 1 interrupt edge enable ifee[23:0] 1 falling rising edge detection glitch filter ife[23:0] 1 maxcount[x] irq glitch filter enable glitch filter counter_n ifcp[3:0] glitch filter prescaler interrupt enable or or irq_15_08 1 irq_07_00 eif[23:16] 1 or irq_23_16
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 44-1 preliminary?subject to change without notice chapter 44 system status and configuration module (sscm) 44.1 introduction 44.1.1 overview the system status and configurat ion module (sscm), pictured in figure 44-1 , provides central soc functionality. on devices with a se parate standby power domain, the system status block is part of that domain. figure 44-1. system status and configuration module block diagram 44.1.2 features the sscm includes these distinctive features: ? system configuration and status ? memory sizes/status ? device mode and security status ? determine boot vector ? search code flash for bootable sector ? device identification inform ation (mcu id registers) bus system status and configuration module interface password comparator revid hardmacro core logic system status peripheral interface bus debug port
pxd20 microcontroller reference manual, rev. 1 44-2 freescale semiconductor preliminary?subject to change without notice ? debug status port enable and selection ? bus and peripheral abort enable/disable 44.1.3 modes of operation the sscm operates identically in all system modes. 44.2 memory map and register description this section provides a detailed description of all memory-mapped registers in the sscm. 44.2.1 memory map table 44-1 shows the memory map for the sscm. note that all addresses are offsets; the absolute address may be calculated by adding the specified offset to the base address of the sscm. all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be al igned to 32-bit boundaries. as an example, the status register is accessible by a 16-bit read/ write to address ?base + 0x0002?, but performing a 16-bit access to ?base + 0x0003? is illegal. 44.2.2 register description the following memory-mapped register s are available in the sscm. those bits that are shaded out are reserved for future use. to optimize future compat ibility, these bits should be masked out during any read/write operations to avoid c onflict with future revisions. 44.2.2.1 system status register (status) the system status register is a read-only register that reflects the current state of the system. table 44-1. sscm memory map address register location base + 0x0000 system status (status) on page 44-2 base + 0x0002 system memory configuration (memconfig) on page 44-3 base + 0x0004 reserved base + 0x0006 error configuration (error) on page 44-4 base + 0x0008 debug status port (debugport) on page 44-5 base + 0x000a reserved base + 0x000c password comparison register high word on page 44-6 base + 0x0010 password comparison register low word on page 44-6
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 44-3 preliminary?subject to change without notice 44.2.2.2 system memory configuration register the system memory configur ation register is a read-o nly register that reflects the memory configuration of the system. address: base + 0x0000 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 nxen pub sec 0 bmode 0 0 0 0 0 w reset: 000000000/10/10/10 0000 = reserved figure 44-2. status (status) register table 44-2. status allowed register accesses 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bi t addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed not allowed table 44-3. status field descriptions field description nxen nexus enabled. pub public serial access status. this bit indicates wh ether serial boot mode with public password is allowed. 1 serial boot mode with public password is allowed 0 serial boot mode with private flash password is allowed, provided the key hasn?t been swallowed sec security status. this bit reflects t he current security state of the flash. 1 the flash is secured 0 the flash is not secured bmode device boot mode. 000 reserved for flexray boot serial boot loader 001 legacy bootstrap via can 010 legacy bootstrap via uart 011 single chip 100 - 111 reserved this field is only updated during reset.
pxd20 microcontroller reference manual, rev. 1 44-4 freescale semiconductor preliminary?subject to change without notice 44.2.2.3 error configuration the error configuration register is a read-write register that controls the error handling of the system. address : base + 0x0002 access: read only 0123456789101112131415 r ivld dvld w reset: xxxxxxxxxx1xxxx1 = reserved figure 44-3. system memory configuration (memconfig) register table 44-4. memconfig field descriptions field description 10 ivld instruction flash valid. this bit i dentifies whether or not the on-chip in struction flash is accessible in the system memory map. the flash may not be accessible due to security limitations, or because there is no flash in the system. 1 instruction flash is accessible 0 instruction flash is not accessible 15 dvld data flash valid. this bit identifie s whether or not the on-chip data fl ash is visible in the system memory map. the flash may not be accessible due to security limitations, or because there is no flash in the system. 1 data flash is visible 0 data flash is not visible table 44-5. memconfig allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed (also reads status register) write not allowed not allowed not allowed
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 44-5 preliminary?subject to change without notice 44.2.2.4 debug status port register the debug status port register is used to (optionally) provide debug data on a set of pins. address : base + 0x0006 access: read/write 0123456789101112131415 r 00000000000000paerae w reset: 0000000000000000 = reserved figure 44-4. error configur ation (error) register table 44-6. error field descriptions field description 14 pa e peripheral bus abort enable. this bit enables bus aborts on any access to a peripheral slot that is not used on the device. this feature is intended to ai d in debugging when developing application code. 1 illegal accesses to non-existing peripherals pr oduce a prefetch or data abort exception 0 illegal accesses to non-existing peripherals do no t produce a prefetch or data abort exception 15 rae register bus abort enable. this bit enables bus aborts on illegal accesses to off-platform peripherals. illegal accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to peripherals produce a prefetch or data abort exception 0 illegal accesses to peripherals do not produce a prefetch or data abort exception transfers to peripheral bus resources may be aborted even before they reach the peripheral bus (i.e. at the aips level). in this case, the per_abort and reg_abort register bits will have no effect on the abort. table 44-7. error allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed write allowed allowed not allowed address: base + 0x0008 access: read/write 0123456789101112131415 r 0000000000000debug_mode[2:0]] w reset: 0000000000000000 = reserved for future use figure 44-5. debug status port (debugport) register
pxd20 microcontroller reference manual, rev. 1 44-6 freescale semiconductor preliminary?subject to change without notice 44.2.2.5 password comparison registers these registers allow to unsecure the de vice, if the correct password is known. table 44-8. debugport field descriptions field description 13-15 debug _mode [0:2] debug status port mode. this field selects the alte rnate debug functionality for the debug status port 000 no alternate functionality selected 001 mode 1 selected 010 mode 2 selected 011 mode 3 selected 100 mode 4 selected 101 mode 5 selected 110 mode 6 selected 111 mode 7 selected table 44-9 describes the functionality of the debug status port in each mode. table 44-9. debug status port modes pin 1 1 all signals are active high, unless otherwise noted mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 status[0] status[8] memconfig[0] memconfig[8] reserved reserved reserved 1 status[1] status[9] memconfig[1] memconfig[9] reserved reserved reserved 2 status[2] status[10] memconfig[2] memconfig[10] reserved reserved reserved 3 status[3] status[11] memconfig[3] memconfig[11] reserved reserved reserved 4 status[4] status[12] memconfig[4] memconfig[12] reserved reserved reserved 5 status[5] status[13] memconfig[5] memconfig[13] reserved reserved reserved 6 status[6] status[14] memconfig[6] memconfig[14] reserved reserved reserved 7 status[7] status[15] memconfig[7] memconfig[15] reserved reserved reserved table 44-10. debugport allowed register accesses 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bi t addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed not allowed write allowed allowed not allowed
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 44-7 preliminary?subject to change without notice address: 0x000c access: read/write 0123456789101112131415 r 0000000000000000 w pwd_hi[0:15] reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w pwd_hi[16:31] reset 0000000000000000 figure 44-6. password comparison register high word (pwcmph) address: 0x0010 access: read/write 0123456789101112131415 r 0000000000000000 w pwd_lo[0:15] reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w pwd_lo[16:31] reset 0000000000000000 figure 44-7. password comparison register low word (pwcmpl) table 44-11. password comparison register field descriptions field description 0-31 pwd_hi [0:31] upper 32 bits of the password 0-31 pwd_lo [0:31] lower 32 bits of the password
pxd20 microcontroller reference manual, rev. 1 44-8 freescale semiconductor preliminary?subject to change without notice in order to unsecure the device, the password needs to be written as follows: first the upper word to the pwcmph register, then the lower word to the pwcmpl register. the sscm compares the password and if the password is correct, unlocks the device. 44.3 functional description the primary purpose of the sscm is to provide information about the cu rrent state and configuration of the system that may be useful fo r configuring application software and for debug of the system. for convenience the description of the boot vector selection is contained in chapter 6, boot assist module (bam). this allows all of the reset behavi or to be described in a single place. 44.4 initialization/application information 44.4.1 reset the reset state of each indivi dual bit is shown within the section 44.2.2, register description . table 44-12. pwcmph/l allowed register accesses 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bi t addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed allowed
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 45-1 chapter 45 system timer module (stm) 45.1 introduction 45.1.1 overview the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 45.1.2 features the stm has the following features: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 45.1.3 modes of operation the stm supports two device modes of operation: nor mal and debug. when the st m is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the stm_cr register. if the frz bi t is set, the counter is stopped in debug mode, otherwise it continues to run. 45.2 external signal description the stm does not have any external interface signals. 45.3 memory map and register definition the stm programming model has fourt een 32-bit registers. the stm regi sters can only be accessed using 32-bit (word) accesses. attempted refe rences using a different size or to a reserved address generates a bus error termination. 45.3.1 memory map the stm memory map is shown in table 45-1 .
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 45-2 45.3.2 register descriptions the following sections detail the individua l registers within the stm programming model. figure 45-1 shows the conventions used in the register figures. 45.3.2.1 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, free ze control and timer enable bits. table 45-1. stm memory map address offset register location 0x0000 stm control register (stm_cr) on page 45-2 0x0004 stm counter value (stm_cnt) on page 45-3 0x0008 reserved 0x000c reserved 0x0010 stm channel 0 control register (stm_ccr0) on page 45-4 0x0014 stm channel 0 interrupt register (stm_cir0) on page 45-4 0x0018 stm channel 0 compare register (stm_cmp0) on page 45-5 0x001c reserved 0x0020 stm channel 1 control register (stm_ccr1) on page 45-4 0x0024 stm channel 1 interrupt register (stm_cir1) on page 45-4 0x0028 stm channel 1 compare register (stm_cmp1) on page 45-5 0x002c reserved 0x0030 stm channel 2 control register (stm_ccr2) on page 45-4 0x0034 stm channel 2 interrupt register (stm_cir2) on page 45-4 0x0038 stm channel 2 compare register (stm_cmp2) on page 45-5 0x003c reserved 0x0040 stm channel 3 control register (stm_ccr3) on page 45-4 0x0044 stm channel 3 interrupt register (stm_cir3) on page 45-4 0x0048 stm channel 3 compare register (stm_cmp3) on page 45-5 0x004c - 0x3fff reserved always reads 1 1always reads 0 0r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0n/a bit w1c bit figure 45-1. key to register fields
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 45-3 45.3.2.2 stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. offset: 0x000 access: read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 00 00 frz ten w reset0000000000000000 figure 45-2. stm control register (stm_cr) table 45-2. stm_cr field descriptions field description 16:23 cps counter prescaler. selects the clock divide value for the prescaler (1 - 256). 0x00 divide system clock by 1 0x01 divide system clock by 2 ... 0xff divide system clock by 256 30 frz freeze. allows the timer counter to be stopped when the device enters debug mode. 0 stm counter continues to run in debug mode. 1 stm counter is stopped in debug mode. 31 ten timer counter enabled. 0 counter is disabled. 1 counter is enabled. offset: 0x004 access: read/write 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 figure 45-3. stm count register (stm_cnt) table 45-3. stm_cnt field descriptions field description 0:31 cnt timer count value used as the time base for all cha nnels. when enabled, the counter increments at the rate of the system clock divi ded by the prescale value.
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 45-4 45.3.2.3 stm channel cont rol register (stm_ccr n ) the stm channel control register (stm_ccr n ) has the enable bit for channel n of the timer. 45.3.2.4 stm channel interrupt register (stm_cir n ) the stm channel interr upt register (stm_cir n ) has the interrupt flag for channel n of the timer. offset: 0x10+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 figure 45-4. stm channel control register (stm_ccr n ) table 45-4. stm_ccr n field descriptions field description 31 cen channel enable. 0 the channel is disabled. 1 the channel is enabled. offset: 0x14+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000cif w w1c reset0000000000000 0 00 figure 45-5. stm channel interrupt register (stm_cir n )
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 45-5 45.3.2.5 stm channel comp are register (stm_cmp n ) the stm channel compar e register (stm_cmp n ) holds the compare value for channel n. 45.4 functional description the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal m ode the counter continuously increments. when enabled in debug mode the coun ter operation is controlled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherw ise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. e ach channel includes a channel control register (stm_ccr n ), a channel interrupt register (stm_cir n ) and a channel compare register (stm_cmp n ). the channel is enabled by setting the stm_ccr n [cen] bit. when enabled, the channel will set the stm_cir n [cif] bit and generate an inte rrupt request when the channel compare register matches the timer counter. the interrupt request is cleared by writing a 1 to the stm_cir n [cif] bit. a write of 0 to the stm_cir n [cif] bit has no effect. note the stm counter does not advance wh en the system clock is stopped. table 45-5. stm_cir n field descriptions field description 31 cif channel interrupt flag 0 no interrupt request. 1 interrupt request due to a match on the channel. offset: 0x18+0x10*n access: read/write 012345678910111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 figure 45-6. stm channel compare register (stm_cmp n ) table 45-6. stm_cmp n field descriptions field description 0:31 cmp compare value for channel n. if the stm_ccr n [cen] bit is set and the stm_cmp n register matches the stm_cnt register, a channel interrupt request is generated and the stm_cir n [cif] bit is set.
pxd20 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 45-6
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-1 preliminary?subject to change without notice chapter 46 timing controller (tcon) 46.1 introduction the timing controller module (tcon) provides an alternative interface for the dcu3 that provides rgb data and timing signals for ?raw? tft panels wh ich have no embedded tcon. the tcon drives the panel via a rsds (reduced sw ing differential signalling) interface (refer to rsds tm ?intra-panel? interface specification, revisi on 1.0, national semiconductor). the tc on and associated rsds i/o module enable direct drive of the row and column drivers of display panels enabling emulation of tcon ics used in display panels. figure 46-1 shows a typical applicat ion diagram of the tcon. figure 46-1. application diagram of the tcon 46.1.1 features ? flexible timing generation unit s upporting 12 timing signal channels ? conforms to rsds tm ?intra-panel? interface specificati on, revision 1.0 (na tional semiconductor) ? flexible mapping of rgb data to rsds channels ? support bit mapping or 8-bit or 6-bit color depth ? output data signal transition minimiz ation through data inversion control ? blanking of rgb data during inactive period (driven to all ?0? or all ?1?) ? flexible rsds output setup/hol d time control in granulatir y of 1/2 system clock cycle rsds cd 1 m rsds cd 1 m rsds cd 1 m rsds rd a1 an rsds rd a1 an gate clock out enable rsds cd 1 m rsds i/o tcon gray scale reference start pulse/tcon_out[x] start pulse/tcon_out[x] line transfer signal tcon_out[x] gray scale voltage reference bus /9 + clk rsds bus tcon_out[x] tft lcd panel inversion control tcon_out[11] hsync_in vsync_in data_en_in data_in 24
pxd20 microcontroller reference manual, rev. 1 46-2 freescale semiconductor preliminary?subject to change without notice 46.1.2 modes of operation the tcon has 3 operation modes: ? bypass mode: the input signals are passed through, and the tcon shall be turned off ? ttl mode: the tcon is functional, driving pa rallel rgb output in non-rsds mode, and the tcon timing signals ? rsds mode: the tcon is functional, driv ing the rsds interface and timing signals 46.2 external signal descriptions the tcon has the following external signals: 46.3 memory map and register definition 46.3.1 memory map figure 46-2 shows the register memory map of the tcon. table 46-1. tcon external signals signal description i/o reset data_out[25:0] 1 1 these signals output through the rsds i/o interface pixel data and clock out, can be configured to be single-ended ttl output or rsds differential output o0 tcon_out[11:0] 12 tcon timing signals o 0 rsds_mode 2 2 this signal goes to the rsds i/o only rsds/ttl format directive o 0 table 46-2. tcon memory map address offset register access location 0x0000 (tcon_ctrl1) ? tcon control1 register r/w on page 46-6 0x0004 (tcon_bmc) ? bit map control register r/w on page 46-8 0x0008-0x0014 (tcon_comp0-tcon_comp3) - comparator 0/1/2/3 configure register r/w on page 46-8 0x0018-0x0024 (tcon_comp0_msk - tcon_conp3_msk) - comparator 0/1/2/3 compare value mask register r/w on page 46-10 0x0028-0x003c (tcon_pulse0 - tcon_pulse5) - pulse 0/1/2/3/4/5 configure register r/w on page 46-11 0x0040-0x0054 (tcon_pulse0_msk - tcon_pulse5_msk) - pulse 0/1/2/3/4/5 compare value mask register r/w on page 46-12 0x0058-0x008c (tcon_smx0 - tcon_smx13) - smx0 - smx13 function control register r/w on page 46-13
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-3 preliminary?subject to change without notice 46.3.2 register summary 0x0090 (tcon_omux_low) - tcon output mux control low r/w on page 46-15 0x0094 (tcon_omux_high) - tcon output mux control high r/w on page 46-16 0x0098-0x00cc (tcon_lut0 - tcon_lut13) - tcon look up table 0 - 13 r/w on page 46-18 0x00d0-0x0100 (tcon_data0_dly - tcon_data12_dly) - rsds i/o 0 - 12 control r/w on page 46-19 0x0104 (tcon_ctrl2) -- tcon control2 register r/w on page 46-21 table 46-3. tcon register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14131211109876543210 tcon_ctrl1 0x0000 r tcon_en 0 tcon_bypass data_inv_en tcon11_inv tcon10_inv tcon9_inv tcon8_inv tcon7_inv tcon6_inv tcon5_inv tcon4_inv tcon3_inv tcon2_inv tcon1_inv tcon0_inv w r init_delay v_ref_sel h_ref_sel vlen hsync_inv vsync_inv color_depth rgb_padding_en rgb_padding rsds_mode w tcon_bmc 0x0004 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 0 0 0 0 0 0 clk_pos color_ order bit_order bit_swap w tcon_compx (0x0008-0x0014 ) r func _sel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 0 0 0 0 comp_value w table 46-2. tcon memory map (continued) address offset register access location
pxd20 microcontroller reference manual, rev. 1 46-4 freescale semiconductor preliminary?subject to change without notice tcon_compx_ mask (0x0018-0x0024 ) r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r 0 0 0 0 mask w tcon_pulsex (0x0028-0x003c ) r func_sel 0 0 set w r comparat or_sel 0 0 reset w tcon_pulsex _msk (0x0040-0x0054 ) r 0 0 0 0 set_mask w r 0 0 0 0 reset_mask w tcon_smxx (0x0058-0x008c ) r index3_sel index2_sel index1_sel index0_sel 0 0 0 0 w r 0 0 0 0 0 0 y_sel x_sel w tcon_omux_ low 0x0090 r0 0 tcon5 tcon4 tcon3 w r tcon 3[4:0] tcon2 tcon1 tcon0 w tcon_omux_ high 0x0094 r0 0 tcon11 tcon10 tcon9 w r tcon 9[4:0] tcon8 tcon7 tcon6 w tcon_lutx (0x0098-0x00c c) r lut[31:16] w r lut[15:0] w table 46-3. tcon register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14131211109876543210
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-5 preliminary?subject to change without notice 46.3.3 register descriptions this section contains the detailed descriptions of tcon registers. tcon_datax_ dly (0x00d0-0x0100 ) r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w r pol 0 0 osufine2 osufine1 osucrse2 osucrse1 osdfine skewopt w tcon_ctrl2 0x0104 r 0 0 0 0 0 0 0 clk_offset w r 0 0 0 0 0 0 0 0 div_ratio w table 46-3. tcon register summary (continued) name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14131211109876543210
pxd20 microcontroller reference manual, rev. 1 46-6 freescale semiconductor preliminary?subject to change without notice 46.3.3.1 control register 1 (tcon_ctrl1) figure 46-2. tcon_ctrl1 register offset 0x000 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r tcon_en 0 tcon_bypass data_inv_en tcon11_inv tcon10_inv tcon9_inv tcon8_inv tcon7_inv tcon6_inv tcon5_inv tcon4_inv tcon3_inv tcon2_inv tcon1_inv tcon0_inv w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r init_delay[2:0] v_ref_sel[2:0] h_ref_sel[1:0] vlen[1:0] hsync_inv vsync_inv color_depth rgb_padding_en rgb_padding rsds_mode w reset0000000000001100 table 46-4. tcon_ctrl1 field descriptions field description tcon_en 1: enable tcon. 0: disable tcon. tcon_bypass 1: bypass tcon, both data and timing signals will pass through the tcon unmodified. see section 46.4.1.3, bypass mode , for pin mapping in that mode. 0: not bypass tcon. state of the tcon is decided by tcon_en. hsync_inv 1: hsync_in signal is active low 0: hsync_in signal is active high vsync_inv 1: vsync_in signal is active low 0: vsync_in signal is active high tcon11_inv - tcon0_inv tconx output inversion control 0: do not invert tconx 1: invert output tconx init_delay initialization delay, set the number of frames before the tcon starts to output timing signals.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-7 preliminary?subject to change without notice v_ref_sel v_ref selector, see section 46.4.2.3, toggle generator , for use of v_ref signal. 0: select tcon_pulse0 output as v_ref 1: select tcon_pulse1 output as v_ref 2: select tcon_pulse2 output as v_ref 3: select tcon_pulse3 output as v_ref 4: select tcon_pulse4 output as v_ref 5: select tcon_pulse5 output as v_ref 6: select tcon_pulse0 output as v_ref, while reset vt gl_counter and vtgl[3] to 0 at rising edge of v_ref. 7: select tcon_pulse0 output as v_ref, while set vtgl _counter to 1 and reset vtgl[3] to 0 at rising edge of v_ref. note: pulse generated must be vertical based for the toggle generator. h_ref_sel h_ref selector, see section 46.4.2.3, toggle generator , for use of h_ref signal. 0: select tcon_comp0 output as h_ref. 1: select tcon_comp1 output as h_ref. 2: select tcon_comp2 output as h_ref. 3: select tcon_comp3 output as h_ref. vlen maximum counter value for vtgl_counter in the toggle generator. see section 46.4.2.3, toggle generator , for detailed functionality of this field. data_inv_en 1: enable output data inversion the input pixel (n) is compared with pixel (n-1). if more than half of the rgb data bits toggle, the pixel (n) output will be inverted and the tcon_out[11] flags this data inversion to the gray scale reference. tcon_out[11] =1 -> data_out is inve rted, tcou_out[11] =0 -> data_out is not inverted. intention of this feature is for board level emi reduction 0: disable output data inversion color_depth color depth of each color component 1: 8 bits 0: 6 bits, the 2 lsb?s are set to 2?b0 rgb_padding_en rgb data padding enable 1: enable padding during blanking 0: disable padding during blanking rgb_padding rgb data driven during blanking. 1: all ?1? 0: all ?0? rsds_mode 1: rsds mode, output rsds bit mapping 0: ttl mode, output ttl bit mapping table 46-4. tcon_ctrl1 field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 46-8 freescale semiconductor preliminary?subject to change without notice 46.3.3.2 bit mapping control (tcon_bmc) 46.3.3.3 tcon_comp0 - tcon_comp3 offset 0x0004 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r 0 0 0 0 0 0 clk_pos color_order bit_order bit_swap w reset0000000000000000 figure 46-3. tcon_bmc register table 46-5. tcon_bmc register field descriptions field description clk_pos clock position selection, output pixel clock can be assigned to any data_out pins. for rsds mode, see table 46-31 for detailed mapping relationship. for ttl mode, see table 46-32 for detailed mapping relationship. color_order color component order configuration bits. 000: rgb 001: brg 010: gbr 011: rbg 100: grb 101: bgr other values:are reserved.for use bit_order 0: msb 7 down to lsb 0 for every color component 1: lsb 0 upto msb 7, for every color component. (inverted order) bit_swap 0: no swap 1: swap odd and even bits for every color component: bit 6 and 7, 4 and 5, 2 and 3, 0 and 1 are swapped. this is needed for rsds channel order inversion
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-9 preliminary?subject to change without notice offset 0x0008 - 0x0014 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r func_sel 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r 0 0 0 0 comp_value w reset0000111111111111 figure 46-4. tcon_compx register table 46-6. tcon_compx re gister field descriptions field description func_sel on which direction the comparatio n is based, vertical or horizontal 0: compare on horizontal direction 1: compare on vertical direction comp_value comparison value. func_sel=0 -> a one-pixel clock cycle high pulse is generated when h_count = comp_value + 2; func_sel=1 -> a one-line wide high pulse is generated when v_count = comp_value. see section 46.4.2.1, comparator , for detailed explanation
pxd20 microcontroller reference manual, rev. 1 46-10 freescale semiconductor preliminary?subject to change without notice 46.3.3.4 tcon_comp0_msk - tcon_comp3_msk offset 0x0018 - 0x0024 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r 0 0 0 0 mask w reset0000111111111111 figure 46-5. tcon_compx_msk register table 46-7. tcon_compx_msk register field descriptions field description mask comparison value mask: mask[x] = 1: in clude bit x in co mparator matching mask[x] = 0 ignore bit x in comparator matching
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-11 preliminary?subject to change without notice 46.3.3.5 tcon_pulse0 - tcon_pulse5 offset 0x0028 - 0x003c access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r func_sel 0 0 set w reset0000111111111111 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r comparat or_sel 0 0 reset w reset0000111111111111 figure 46-6. tcon_pulsex register table 46-8. tcon_pulsex register field descriptions field description func_sel select the type of pulse, horizontal/vertical/or mix 00: set/reset value both for horizontal compare 01: set/reset value both for vertical compare, signal transition point determined by comparator_sel 10: set/reset value both for vertical compare, signal transitions at the beginning of the line which is matched. 11: set value for horizontal compare, reset value for vertical compare. si gnal transiti on point for reset determined by comparator_sel. comparator_ sel when func_sel is set to 01, 1 of the 4 comparator outputs is selected to define the horizontal change point for both set/reset. when func_sel is set to 11, 1 of the 4 comparator outputs is selected to define the horizontal c hange point for reset. 00: select comparator0 01: select comparator1 10: select comparator2 11: select comparator3 note: when func_sel set to 01 or 11, user should program the corresponding comparator for horizontal compare to ensure the timing signal is generated as expected. set set point compare value note: there will be a two pixel clock cycle delay betw een the internal pixel counter and the output pixel data in horizontal directi on, user should take this two cycle delay into account when programming this field. see section 46.4.2.2, pulse generator , for detailed explanation. reset reset point compare value note: there will be a two pixel clock cycle?s delay between the internal pixel count an d the output pixel data in horizontal direction, user should take this two cycle delay into account when programming this field. see section 46.4.2.2, pulse generator , for detailed explanation.
pxd20 microcontroller reference manual, rev. 1 46-12 freescale semiconductor preliminary?subject to change without notice 46.3.3.6 tcon_pulse0_msk - tcon_pulse5_msk offset 0x0040 - 0x0054 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 set_mask w reset0000111111111111 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r 0 0 0 0 reset_mask w reset0000111111111111 figure 46-7. tcon_pulsex_msk register table 46-9. tcon_pulsex_msk register field descriptions field description set_mask set point compare mask value set_mask[x] = 1: include x postion in pulse generator set value comparison set_mask[x] = 0, ignore x position in pulse generator set value comparison reset_mask reset point compare mask value reset_mask[x] = 1, include x position in pulse generator re set value comparison reset_mask[x] = 0, ignore x position in pulse generator reset value comparison.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-13 preliminary?subject to change without notice 46.3.3.7 tcon_smx0 - tcon_smx13 figure 46-8. tcon_smxx register offset 0x0058 - 0x008c access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r index3_sel index2_sel index1_sel index0_sel 0 0 0 0 w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r 0 0 0 0 0 0 y_sel x_sel w reset0000000000000000 table 46-10. tcon_smxx field descriptions field description index3_sel smxx lut index3 selection. {index3,index2,index1,index0} will be used as address to lut to generate timing signal.} 0: index3 = 0; 1: index3 = x; 2: index3 = y; 3: index3 = x&y; 4: index3 = x|y; 5: index3 = x^y; 6: index3 = !(x&y)) 7: reserved for use index2_sel smxx lut index2 selecti on. same functionality as index3_sel
pxd20 microcontroller reference manual, rev. 1 46-14 freescale semiconductor preliminary?subject to change without notice index1_sel smxx lut index1 selecti on. same functionality as index3_sel index0_sel smxx lut index0 selecti on. same functionality as index3_sel y_sel smxx logic input y selection. 00: const0 01: const1 02: pulse0 03: pulse1 04: pulse2 05: pulse3 06: pulse4 07: pulse5 08: vtgl[0] 09: vtgl[1] 0a: vtgl[2] 0b: vtgl[3] 0c: smx0 0d: smx1 0e: smx2 0f: smx3 10: smx4 11: smx5 12: smx6 13: smx7 14: smx8 15: smx9 16: smx10 17: smx11 18: comp0 19: comp1 1a: comp2 1b: comp3 1c~1f: reserved x_sel smx logic input a selection, the same selection logic is implemented here as in y_sel. table 46-10. tcon_smxx field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-15 preliminary?subject to change without notice 46.3.3.8 tcon_omux_low figure 46-9. tcon_omux_low register offset 0x0090 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r0 0 tcon5 tcon4 tcon3 w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r tcon3 tcon2 tcon1 tcon0 w reset0000000000000000 table 46-11. tcon_omux_low field descriptions field description tcon0 output selection for tcon pin0 00: const0 01: const1 02: pulse0 03: pulse1 04: pulse2 05: pulse3 06: pulse4 07: pulse5 08: vtgl[0] 09: vtgl[1] 0a: vtgl[2] 0b: vtgl[3] 0c: smx6 0d: smx7 0e: smx8 0f: smx9 10: smx10 11: smx11 12: smx12 13: smx13 14 - 1f: reserved, default to const0 tcon1 output selection for tcon pin1, refer to field tcon0 for detailed functional description
pxd20 microcontroller reference manual, rev. 1 46-16 freescale semiconductor preliminary?subject to change without notice 46.3.3.9 tcon_omux_high figure 46-10. tcon_omux_high register tcon2 output selection for tcon pin2, refer to field tcon0 for detailed functional description tcon3 output selection for tcon pin3, refer to field tcon0 for detailed functional description tcon4 output selection for tcon pin4, refer to field tcon0 for detailed functional description tcon5 output selection for tcon pin5, refer to field tcon0 for detailed functional description offset 0x0094 access: user read/write 0123456789101112131415 r0 0 tcon11[4:0] tcon10[4:0] tcon9[4:0] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcon9[4:0] tcon8[4:0] tcon7[4:0] tcon6[4:0] w reset0000000000000000 table 46-11. tcon_omux_low field descriptions (continued) field description
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-17 preliminary?subject to change without notice table 46-12. tcon_omux_high field descriptions field description tcon6[4:0] output selection for tcon pin6 00: const0 01: const1 02: pulse0 03: pulse1 04: pulse2 05: pulse3 06: pulse4 07: pulse5 08: vtgl[0] 09: vtgl[1] 0a: vtgl[2] 0b: vtgl[3] 0c: smx6 0d: smx7 0e: smx8 0f: smx9 10: smx10 11: smx11 12: smx12 13: smx13 14 - 1f: reserved tcon7[4:0] output selection for tcon pin7, refer to field tcon6 for detailed functional description tcon8[4:0] output selection for tcon pin8, refer to field tcon6 for detailed functional description tcon9[4:0] output selection for tcon pin9, refer to field tcon6 for detailed functional description tcon10[4:0] output selection for tcon pin10, refer to field tcon6 for detailed functional description tcon11[4:0] output selection for tcon pin11, refer to field tcon6 for detailed functional description
pxd20 microcontroller reference manual, rev. 1 46-18 freescale semiconductor preliminary?subject to change without notice 46.3.3.10 tcon_lut0 - tcon_lut13 offset 0x0098 - 0x00cc access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r lut[31:16] w reset1111111111111111 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r lut[15:0] w reset0000000001011100 figure 46-11. tcon_lutx register table 46-13. tcon_lutx register field descriptions field description lut[31:0] look up table for smxx. smxx(n) = tcon_lutx[{index3,index2,index1,index0,smxx(n-1)}], see table 46-10 for construction of index3 to index0.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-19 preliminary?subject to change without notice 46.3.3.11 tcon_data0_dly - tcon_data12_dly offset 0x00d0 - 0x0100 access: user read/write power architecture 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 00000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 15 14 13 12 11 10 9 8 76543210 r pol 0 0 osufine 2 osufin e1 osucrse 2 osucrse1 osdfine skewopt w reset 0 0 0 0 0 0 0 0 00000001 figure 46-12. tcon_datax_dly register table 46-14. tcon_datax_dly field descriptions 1 1 bits 13,14,16-31 can be written and read back although these bits do not affect the functi onality of the tcon module. field description pol control signal for choosing polarity if same data is to be transmitted or opposite data polarity is to be transmitted osufine2 2 2 see table 46-16 for details of how these bits affect the fi ne adjustment of the rsds output voltage swing. control signal for increasing the voltage value.(fine adjustment) osufine1 2 control signal for increasing the voltage value.(fine adjustment) osucrse2 3 3 see ta b l e 4 6 - 1 5 for details of how these bits affect the coar se adjustment of the rs ds output voltage swing. control signal for increasing the voltage va lue to higher order.(coarse adjustment) osucrse1 3 control signal for increasing the voltage value.(coarse adjustment) osdfine 2 control signal for decreasing the voltage value.(fine adjustment) skewopt 4 4 see ta b l e 4 6 - 1 7 for details of how these bits affect the absolute skew of the channel timing. 8 programmable bits to control skew
pxd20 microcontroller reference manual, rev. 1 46-20 freescale semiconductor preliminary?subject to change without notice table 46-15. rsds option bits to increase/decrease the output swing (coarse adjustment) s. no osucrse2 osucrse1 voltage of the driver differential voltage across pad_p and pad_n 1 0 0 normal default 2 0 1 increased increase swing by 60mv 3 1 0 increased increase swing by 100mv 4 1 1 increased increase swing by 160mv table 46-16. rsds option bits to increase/decrease the output swing (fine adjustment) s. no osdfine osucrse1 osucrse2 voltage of the driver differential voltage across pad_p and pad_n 1 0 0 0 normal default 2 0 0 1 increased increase swing by 25mv 3 0 1 0 increased increase swing by 15mv 4 0 1 1 increased increase swing by 40mv 5 1 0 0 decreased decrease swing by 30mv 6 1 0 1 decreased decrease swing by 5mv 7 1 1 0 decreased decrease swing by 15mv 8 1 1 1 increased increase swing by 10mv table 46-17. rsds option bits to increase the skew ipp_skew _opt7 ipp_skew _opt6 ipp_skew_ opt5 ipp_skew _opt4 ipp_skew_ opt3 ipp_skew _opt2 ipp_skew _opt1 ipp_skew_ opt0 output skew (psec) 00000000 n.a. 00000001 52 00000010 117 00000100 171 00001000 211 00010000 255 00100000 299 01000000 346 1.2v 0v 0v 0v 0v 0v 0v 0v 391
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-21 preliminary?subject to change without notice 46.3.3.12 tcon_ctrl2 1.2v 1.2v 1.2v 1.2v 1. 2v 1.2v 1.2v 1.2v 44 notes: (1) we have 256 different skew numbers for various combinations of these 8 programmable bits, in this table only few are listed . please refer extended table for all the skew numbers. (2) all these skew numbers are at typical corners (3) default value for the 8 skew option are all ?1?. (4) if all zero combination is applied, transmitter will not go to powerdown, instead we shall see a fixed dc transmitter outpu t irrespective of input data. this state is n.a. offset 0x0104 access: user read/write power architecture 0123456789101112131415 conventional 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 0 0 0 0 0 0 0 clk_offset[8:0] w reset0000000000000000 power architecture 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 conventional 1514131211109876543210 r 0 0 0 0 0 0 0 0 div_ratio[7:0] w reset0000000000000010 figure 46-13. tcon_ctrl2 register table 46-18. tcon_ctrl2 register field descriptions field description div_ratio[7:0] tcon pixel clock divide ration. when div_ratio set to n, pix_clk will be ipg_clk divided by n+1. clk_offset[8:0] output pixel clock offset value in half ipg_clk cycle unit. please refer to section 46.4.5, clock/data skew adjustment , for use of this field. the valid range of thif field is to 0 to 2n-1 in ttl mode and 0 to n-1 in rsds mode, where n=(div_ratio+1). table 46-17. rsds option bits to increase the skew (continued) ipp_skew _opt7 ipp_skew _opt6 ipp_skew_ opt5 ipp_skew _opt4 ipp_skew_ opt3 ipp_skew _opt2 ipp_skew _opt1 ipp_skew_ opt0 output skew (psec) 00000000 n.a. 00000001 52 00000010 117 00000100 171
pxd20 microcontroller reference manual, rev. 1 46-22 freescale semiconductor preliminary?subject to change without notice 46.4 functional description the major functions of the tcon are to generate timin g signals needed to drive the external row drivers and column drivers, and map the rgb data bits to the outputs according to the rsds tm standard. it accepts rgb data, and horizontal/v ertical synchronization signals from the display controller unit module, maintains two internal counters (x_count, a nd y_count), and uses these to generate the timing signals. in order to support as many type of panels aspossible, the ti ming generation unit has been designed to be flexible and can be configured freel y to generate complicat ed timing signals. see section 46.4.2, timing signal generator , for details about the ti ming signal generation unit. the tcon has three operation modes including rs ds mode, ttl mode, and bypass mode. in bypass mode the input signals are passed through the tcon unchanged, a nd in the other two modes the tcon performs signal (the rgb data and pixel clock) bi t mapping. for details of the operation modes see section 46.4.1, modes of operation , and for the signal bit mapping see section 46.4.4, bit mapping control (bmc) . the tcon also has a data inversion control featur e which can be used to minimize transitions on the output data bus. for details see section 46.4.3, data inversion control . 46.4.1 modes of operation 46.4.1.1 rsds mode the rsds mode is the typical ope ration mode of the tcon. in rs ds mode, the tcon maps the rgb data bits and the pixel cl ock according to the rsds tm ?intra-panel? interface specification, revision 1.0 (national semiconductor). for details see section 46.4.4.2, bit mapping in rsds mode . in rsds mode, the tcon drives the rsds interface, where the rgb data and the pixel clock (25 signals for 8-bit color depth, and 19 signals for 6-bit color de pth) are transfered via 13 or 10 rsds differential pairs, each differential pa ir carries two signals. so da ta is driven on both rising a nd falling edge of the pixel clock. the tcon timing signals are tran sfered via single ended ttl interface. in rsds mode, the tcon places th e rsds i/o in rsds output mode. to ease board design, the pixel clock can be assi gned to any one of the differential pairs. see section 46.4.4.4, clock mapping in rsds mode . to enable the rsds mode, set tcon_ctrl1[rsds_mode]=?1?, tcon_ctrl1[tcon_bypass]=?0?, and tcon_ctr l1[tcon_en]=?1?. for the tcon_ctrl1 register see section 46.3.3.1, control register 1 (tcon_ctrl1) . 46.4.1.2 ttl mode in ttl mode the tcon drives the rgb data, pixe l clock, and the tcon timing signals all via ttl interface. in this mode simpler signal bit mapping is performed, see section 46.4.4.1, bit mapping in ttl mode . it is also possible to assign the pixel clock to any one of the 25 output pins in ttl mode, see section 46.4.4.5, clock mapping in ttl mode .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-23 preliminary?subject to change without notice to enable ttl mode, set tcon_ctrl1[rsds_m ode]=?0?, tcon_ctrl1 [tcon_bypass]=?0?, and tcon_ctrl1[tcon_en]=?1?. 46.4.1.3 bypass mode for applications where the tcon is not in use, a bypass mode is provided in which the input signals for the display controller are passe d through the tcon unchanged. see table 46-19 about how the input signals are assigned to the tcon output. to put the tcon in bypass mode , set tcon_ctrl1[tcon_en]=0. and tcon_ctrl1[tcon_bypass]=1. 46.4.2 timing signal generator the timing signal generator (tsg) is the tcon timing signal generation unit. it accepts the hsync/vsync signals from the input parallel display interface, and ma intains two counters ( hcount , vcount ) based on that. all the timing signals ar e generated based on these two counters. for every line the hcount counts the current pixel number, from 1 to the number of pixels per line (the full line, including inactive period). it restarts from 1 with the hsync signal rising edge. similarly the vcount counts from 1 with the vsync signal rising edge (first line), increments by ?1? at the end of each line, till the last line in a frame (including inactive lines). the timing signal generator is composed of 4 comparators ( section 46.4.2.1, comparator ), 6 pulse generators ( section 46.4.2.2, pulse generator ), 1 toggle generator ( section 46.4.2.3, toggle generator ), and a signal mixer or synthesizer ( section 46.4.2.4, signa l mixer (smx) ). see the following sections for detailed descriptions. 46.4.2.1 comparator there are 4 comparators in the tcon, each can be configured to compare hcount or vcount with the value specified in a tcon_compx register (see section 46.3.3.3, tcon_comp0 - tcon_comp3 ). if desired the user can mask some bits from co mparing by setting the corresponding bits in both tcon_compx_msk (see section 46.3.3.4, tcon_comp0_msk - tcon_comp3_msk ) and table 46-19. input/output signal mapping in bypass mode input output data_in[23:0] data_out[25:2] pix_clk data_out[1] dcu_tag tcon_out[0] hsync_in tcon_out[1] vsync_in tcon_out[2] data_en_in tcon_out[3]
pxd20 microcontroller reference manual, rev. 1 46-24 freescale semiconductor preliminary?subject to change without notice tcon_compx register to ?0.? an one cycle (pixel cl ock cycle, or line cycle) pulse will be generated when the compare result is match, and the comparison logic is shown below: compare_out = (tcon_compx.comp_value == (tcon_compx_msk .mask & hcount )) eqn. 46-1 or compare_out = (tcon_compx.comp_value == (tcon_compx_msk.mask & vcount )) eqn. 46-2 tcon_compx.func_sel determines whether equation 46-1 or equation 46-2 is used (i.e. comparison is done on horizontal or vertical direction). 46.4.2.2 pulse generator there are 6 pulse generators in the tcon which can be used to generate pulses which have a set point and a reset point, and the pulse length is discretional. the set and reset point is determined by tcon_pulsex.[set] and tc on_pulsex.[reset] (see section 46.3.3.5, tcon_pulse0 - tcon_pulse5 ), to which the hcount or vcount value will be compared. if desired the user can mask some bits from comparing by setting the corr esponding bits in both tcon_pulsex_msk and tcon_pulsex register to 0. th e equations used to find the set/clear point are similar to equation 46-1 or equation 46-2 . tcon_pulsex.[func_sel] controls the t ype of the pulse, a.k.a. whether the set/reset point comparison is performed on horizot nal direction (compare with hcount ) or vertical direction (compare with vount ). and when vertical comparison is selected (i e. func_sel = 01 or 11), 1 of the 4 comparator outputs (must be a horizontal pulse) can be selected to further dete rmine the signal transition point on horizontal direction. or when func_sel = 10, the si gnal transition will happe n immediately when the vertical compare matches (ie. at the beginning of the line). when needed tcon_pulsex.[comparator_sel] selects 1 of th e 4 comparator outputs as the horizontal reference. 46.4.2.3 toggle generator there?s 1 toggle generator in the tcon which can be used to generate si gnals which toggles line to line, or frame to frame, or signal which toggles line to line but polarity ch anges from frame to frame. the toggle generator accepts the 4 comparator outputs (tcon_comp[0:3]) and the 6 pulses (tcon_pulse[0-5]), and generates 4 toggle signals ( vtgl[0-3] ) based on that. the toggle generator uses a counter (vtgl_counter) and a t flip-flop to generate the 4 toggle signals. the vtgl_counter takes 1 of the 4 co mparator outputs as the clock ( h_ref ), and 1 of the 6 pulses as the enable signal ( v_ref ). the h_ref/v_ref selection is controlled via tcon_ctrl1.h_ref_sel (see section 46.3.3.1, control register 1 (tcon_ctrl1) ) and tcon_ctrl1.v_ref_sel. tcon_ctrl1.vlen sets the maximun counter value. the vtgl_counter in crements at the rising edge of h_ref when v_ref is high, and it falls back to ?0? when the counter value exceeds vlen. and then the vtgl[0-2] are generated by decoding the counter value ( equation 46-3 to equation 46-5 ). vtgl[0] = (vtgl_counter == 0) eqn. 46-3 vtgl[1] = (vtgl_counter == 1) eqn. 46-4
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-25 preliminary?subject to change without notice vtgl[2] = (vtgl_counter == 2) eqn. 46-5 the h_ref_sel and v_ref_sel shal l be programmed so that the h_ref is a horizontal pulse (one pixel clock cycle pulse per line) and the v_ref is a vertical pulse (pulse last s for 1 line or several lines). figure 46-20 shows the relationship between vle n, vtgl_counter sequence and vtgl[2:0]. a t flip-flop is used to generate vtgl [3]. t flip-flop is a type of flip-f lop whose output t oggles (inverts) at the rising edge of the clock input when the enable signal input is high. the t flip-flop in the toggle generator is clocked by h_ref , and the enable signal ( en ) is the bit-and of vtgl[0] and v_ref . by programming the vlen, and control the pulse lengt h of v_ref, the vtgl[3] can be used to generate toggle signals whose polarity ch anges from fram e to frame. see table 46-21 for some programming examples. table 46-20. vtgl[0-2] sequence input output vtgl_ counter sequence vlen vtgl 012345678 0 0 111111111 1 000000000 2 000000000 1 0 101010101 1 010101010 2 000000000 2 0 100100100 1 010010010 2 001001001 table 46-21. vtgl[3] programming examples vtgl[3] v_ref pulse length vlen toggles every line, polarity inverts frame to frame, steady during vertical blanking (2 frame sequence) odd (eg. number of active lines + 1) 0 toggles every other line, polarity inverts frame to frame, steady during vertical blanking (2 frame sequence) odd*2 (eg. number of active lines) 1 toggles every 3rd line, polarity inverts frame to frame, steady during vertical blanking (2 frame sequence) odd*3 (eg. number of active lines + 3) 2 toggles every other line, walking pattern (4 frame sequence) odd (eg. number of active lines + 1) 1
pxd20 microcontroller reference manual, rev. 1 46-26 freescale semiconductor preliminary?subject to change without notice .to make it easier to understand, table 46-22 shows an simpler example wher e the number of active lines is 6. 46.4.2.4 signal mixer (smx) to generate more complicated timing signals, ther e are 14 signal mixer/synthe sizer (smx) modules in the tcon which can be used to perform logic operations between ev ery two signals. each smx module takes 2 signal inputs (x and y) , and generates 1 smxx output. the x and y input of each smx modul e can be selected from any two of the 28 signals (4 comparator outputs, 6 pulses, 4 toggle generator outputs, constant 0 or 1, and 12 feedback signals smx0~11). the x/y signal selection is configurabled via tcon_smxx.x_sel and tcon_smxx.y_sel (see section 46.3.3.7, tcon_smx0 - tcon_smx13 ). 12 of the smxx output (s mx0~11) can be feedback to the smxx input again in order to generate even more complicated signals (combining information of more than 2 signals), the smx module is composed of several logic operation units (and, or , xor or nand), and a look-up-table (lut). the lut takes 4 inputs, including the current lut out put value and a 4-bit inde x (index[3:0]), the lut output is the next cycle smx output. function perf ormed by the lut is determined by the values programmed into tcon_lutx (see section 46.3.3.10, tcon_lut0 - tcon_lut13 ). by default the value of tcon_lutx is 32?hffff_005c and the de fault truth table of the lut is shown in table 46-23 where smxx(n-1) is the current smxx state and smxx(n) is the next cycle smxx va lue. with this setting the lut emulates the function of a set/reset/toggle/data flip-fl op, where index3 to index0 are the set/reset/toggle enable/data inputs, ?set? has the hi ghest priority. the user can also reprogram the table 46-22. ctgl[3] signal example a vlen frame active line number v_ref pulse length 012345678 0 0 0101010 7 1 1010101 7 1 0 011001 6 1 100110 6 2 0 011100011 9 1 100011100 9 1 0 0110011 7 1 0011001 7 2 1001100 7 3 1100110 7
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-27 preliminary?subject to change without notice tcon_lutx registers so that the lu t performs different operations (e.g. change the priority order of the set/reset/toggle enable/data signals). the index[3:0] input of the lut is generated by the logic opera tion units. each bit of it is a logic operation of x, y, 0 or 1. the logic operations perform ed are selected by tcon_smxx.index0-3_sel (see section 46.3.3.7, tcon_smx0 - tcon_smx13 ). 46.4.2.5 output crossbar mux the output crossbar mux is used to select 12 from the ge nerated 20 timing signals as the 12 tcon timing signal outputs. the 20 timing signals in clude: 6 pulses, 4 toggle generator outputs (vtgl[0:3]), constant ?0? and ?1,? and 8 of the 14 smxs out put (smx6~13). tcon_ omux_high (see section 46.3.3.8, tcon_omux_low ) and tcon_omux_low (see section 46.3.3.9, tcon_omux_high ) determines which 12 timing signals are selected as the output. 46.4.3 data inversion control the data inversion co ntrol is adopted to minimize data transitio n on the data bus, in order to reduce emi on board level. the idea is to invert the data output when more than half of the data bits changed compare to the previous data output, and use a signal (tcon_out[11]) to indicate to the external gray scale reference circuit that the data is inverted. the user can enable the data inverse control by setting tcon_ctrl1.d ata_inv_en to ?1? (see section 46.3.3.1, control register 1 (tcon_ctrl1) ), in that case, tcon_out[11] will indicate the data inversion so it can?t be used as ti ming signal output. but it can if the da ta inversion control is disabled. 46.4.4 bit mapping control (bmc) the bit mapping control (bmc) modul e is adopted to remap the color component order, color bit order and output clock position for both rsds and ttl mode. figure 46-14 shows the diagram of the bit mapping control module. table 46-23. default tcon lut truth table index3 index2 index1 index0 smxx(n-1) smxx(n) 1x 1 1 don?t care xxx1 01xxx0 001x01 001x10 0001x1 0000x0
pxd20 microcontroller reference manual, rev. 1 46-28 freescale semiconductor preliminary?subject to change without notice figure 46-14. bit mapping control 46.4.4.1 bit mapp ing in ttl mode see table 46-24 for default bit mapping in 8-bit color mode. see table 46-25 for default bit mapping in 6-bit color mode. beside the default bit mapping, it?s possibl e to swap the rgb color component order (tcon_bmc.color_order) and the lsb/ms g bit order in each color component (tcon_bmc.bit_order), see section 46.3.3.2, bit mapping control (tcon_bmc) . 46.4.4.2 bit mapping in rsds mode see table 46-26 for default bit mapping in 8-bit color mode. table 46-24. ttl mode bit mapping, 8-bit color data signal rising of pix_clk remapped rgb[23:16] {r7,r6,r5,r4,r3,r2,r1,r0} remapped rgb[15:8] {g7,g 6,g5,g4,g3,g2,g1,g0} remapped rgb[7:0] {b7,b6 ,b5,b4,b3,b2,b1,b0} table 46-25. ttl mode bit mapping, 6-bit color data signal rising of pix_clk remapped rgb[23:16] {r7,r6,r5,r4,r3,r2,2?b0} remapped rgb[15:8] {g7 ,g6,g5,g4,g3,g2,2?b0} remapped rgb[7:0] {b7,b6,b5,b4,b3,b2,2?b0} table 46-26. rsds mode bit mapping, 8-bit color data signal rising of pix_clk falling of pix_clk remapped rgb[23] r6 r7 remapped rgb[22] r4 r5 remapped rgb[21] r2 r3 remapped rgb[23:0] bit mapping rgb[23:0] pixel_clk clock mapping data_out
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-29 preliminary?subject to change without notice see table 46-27 for default bit mapping in 6-bit color mode. beside the default bit mapping, it?s possibl e to swap the rgb color component order (tcon_bmc.color_order), the lsb/msg bit order in each color component remapped rgb[20] r0 r1 remapped rgb[19:16] 0 0 remapped rgb[15] g6 g7 remapped rgb[14] g4 g5 remapped rgb[13] g2 g3 remapped rgb[12] g0 g1 remapped rgb[11:8] 0 0 remapped rgb[7] b6 b7 remapped rgb[6] b4 b5 remapped rgb[5] b2 b3 remapped rgb[4] b0 b1 remapped rgb[3:0] 0 0 table 46-27. rsds mode bit mapping, 6-bit color data signal rising of pix_clk falling of pix_clk remapped rgb[23] r6 r7 remapped rgb[22] r4 r5 remapped rgb[21] r2 r3 remapped rgb[20:16] 0 0 remapped rgb[15] g6 g7 remapped rgb[14] g4 g5 remapped rgb[13] g2 g3 remapped rgb[12:8] 0 0 remapped rgb[7] b6 b7 remapped rgb[6] b4 b5 remapped rgb[5] b2 b3 remapped rgb[4:0] 0 0 table 46-26. rsds mode bit mapping, 8-bit color (continued) data signal rising of pix_clk falling of pix_clk
pxd20 microcontroller reference manual, rev. 1 46-30 freescale semiconductor preliminary?subject to change without notice (tcon_bmc.bit_order), and the 2 bits transfered during rising and falling pixel clock cycle (tcon_bmc.bit_swap). see section 46.3.3.2, bit mapping control (tcon_bmc) . 46.4.4.3 bit mapping examples a. rsds mode, below settings will remap the bit order as in table 46-28 tcon_ctrl1.op_mode = 1; //rsds mode tcon_ctrl1.color_depth = 1; //8bit per color tcon_bmc.color_order = 3?b000; //color order rgb tcon_bmc.bmc.bit_order = 1; //0 up to 7msb tcon_bmc.bmc.bit_swap = 0; //no odd/even bit order swap b. rsds mode, below settings will remap the bit order as in table 46-29 tcon_ctrl1.data_mode = 1; //rsds mode tcon_ctrl1.color_depth = 0; //6 bit per color tcon_bmc.color_order = 3?b101; //color order bgr tcon_bmc.bmc.bit_order = 0; //msb 7 down to 0 tcon_bmc.bmc.bit_swap = 1; //swap odd and even bit table 46-28. bit mapping example a data signal rising of pix_clk falling of pix_clk remapped rgb[23] r0 r1 remapped rgb[22] r2 r3 remapped rgb[21] r4 r5 remapped rgb[20] r6 r7 remapped rgb [19:16] 0 0 remapped rgb[15] g0 g1 remapped rgb[14] g2 g3 remapped rgb[13] g4 g5 remapped rgb[12] g6 g7 remapped rgb [11:8] 0 0 remapped rgb[7] b0 b1 remapped rgb[6] b2 b3 remapped rgb[5] b4 b5 remapped rgb[4] b6 b7 remapped rgb [3:0] 0 0 table 46-29. bit mapping example b data signal rising of pix_clk falling of pix_clk remapped rgb[23] b7 b6
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-31 preliminary?subject to change without notice c. ttl mode, below settings will remap the bit order as in table 46-30 tcon_ctrl1.data_mode = 0; //ttl mode tcon_bmc.color_order = 3?b000; //color order rgb tcon_bmc.bit_order = 1; //0 up to msb7 tcon_ctrl1.color_depth = 1; //6bit per color; 46.4.4.4 clock mapping in rsds mode to aid board design, it has been made possible to assign the pixel clock output to any of the 13 rsds differential pairs, configured via tcon_bmc.clk_pos (see section 46.3.3.2, bit mapping control (tcon_bmc) ). the flexible clock mapping in rsds mode is shown in table 46-31 . remapped rgb[22] b5 b4 remapped rgb[21] b3 b2 remapped rgb [20:16] 0 0 remapped rgb[15] g7 g6 remapped rgb[14] g5 g4 remapped rgb[13] g3 g2 remapped rgb [12:8] 0 0 remapped rgb[7] r7 r6 remapped rgb[6] r5 r4 remapped rgb[5] r3 r2 remapped rgb [4:0] 0 0 table 46-30. bit mapping example c rsds 8-bits rising of pix_clk remapped rgb[23:16] {r2,r3,r4,r5,r6,r7,2?b0} remapped rgb[15:8] {g2,g3,g4,g5,g6,g7,2?b0} remapped rgb[7:0] {b2,b3,b4,b5,b6,b7,2?b0} table 46-31. clock mapping in rsds mode data_ out clk_pos[4:0] 0123456789101112 0/1 clk 1 ~4/4 2/3 ~4/4 2 clk ~5/5 table 46-29. bit mapping example b (continued) data signal rising of pix_clk falling of pix_clk
pxd20 microcontroller reference manual, rev. 1 46-32 freescale semiconductor preliminary?subject to change without notice 46.4.4.5 clock mapping in ttl mode similar to rsds mode, it?s also possible to assign th e pixel clock output to any bit of the data_out[1:25] in ttl mode, configured via tcon_bmc.clk_pos (see section 46.3.3.2, bit mapping control (tcon_bmc) ). see table 46-32 for details. 4/5 ~5/5 clk ~6/6 6/7 ~6/6 clk ~7/7 8/9 ~7/7 clk ~12/12 10/11 ~12/12 clk ~13/13 12/13 ~13/13 clk ~14/14 14/15 ~14/14 clk ~15/15 16/17 ~15/15 clk ~20/20 18/19 ~20/20 clk ~21/21 20/21 ~21/21 clk ~22/22 22/23 ~22/22 clk ~23/ 23 24/25 ~23/23 clk 1 clk stands for differential clock signal pair: clk_out_b/clk_out 2 ~n/n stands for differential data sign al pair: ~remapped r gb[n]/remapped rgb[n] table 46-32. clock mapping in ttl mode d a t a _ o u t clk_pos[4:0] 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 0 const0 1c 1 0 20 2 c1 31c 2 table 46-31. clock mapping in rsds mode (continued) data_ out clk_pos[4:0] 0123456789101112
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-33 preliminary?subject to change without notice 42c 3 53c 4 64c 5 75c 6 86c 7 97c 8 1 0 8c 9 1 1 9c 10 1 2 10 c 11 1 3 11 c 12 1 4 12 c 13 1 5 13 c 14 1 6 14 c 15 1 7 15 c 16 1 8 16 c 17 1 9 17 c 18 2 0 18 c 19 2 1 19 c 20 2 2 20 c 21 table 46-32. clock mapping in ttl mode (continued) d a t a _ o u t clk_pos[4:0] 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
pxd20 microcontroller reference manual, rev. 1 46-34 freescale semiconductor preliminary?subject to change without notice 46.4.5 clock/data skew adjustment in order to fulfill different setup/hold timing re quirements on the output inte rface, it has been made possible to adjust the signa l skew between the pixel clock output and the data output (including rgb data and timing signals). the output pixel cl ock can be flexibly shif ted compared to the da ta signals. it can be shifted over the whole pixel clock pe riod, in granularity of half pixel clock source cycle (the clock from which the pixel clock is derived/divided). tcon_ctrl2.div_ratio (see section 46.3.3.12, tcon_ctrl2 ) configures the pixel clock divide ratio, and tcon_ctrl2.clk_offset c onfigures the offset between th e internal pixel clock and the output pixel clock.. 46.5 rsds interface description 46.5.1 introduction rsds (reduced swing differential signaling) is an intra panel interface bus stan dard. it is a sub-lvds system, as its application is with a subsystem, the signal swing is furt her reduced from lvds to further lower power. as compared to lvds, the rsds scheme uses a 2:1 serialization sc heme, resulting in a less complex and low power architecture. this interface operates at a maximum frequency of 80 mhz. apart from rsds_tx pad there is another cell called rsds_ref which is to pr ovide current and voltage biases to the transmitter cell. 2 3 21 c 22 2 4 22 c 2 3 2 5 23 c 1 clock 2 n stand for remapped rgb[n] table 46-32. clock mapping in ttl mode (continued) d a t a _ o u t clk_pos[4:0] 0123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-35 preliminary?subject to change without notice figure 46-15. rsds interface 46.5.2 features main features of rsds tr ansmitter are as follows ? common mode voltage between 0.5 v to 1.5 v ? supports data rates upto 120 mbps ? output impedence of 100 ? differential ? programmable voltage swing ? programmable option for controlling data polarity ? programmable skew control 46.5.3 data path signals 46.5.3.1 pad_p this is the ?positive? i/o signa l connected bond pad for the rsds output pad. the voltage supported by the pad is defined by the vref_rsds and vss associated with the cell. ipp_obe rsds_tx vref_rsds iref_rsds pad_n pad_p ipp_curr_dwn rsds_ref_en ipp_curr_up ipp_do ipp_skew_opt ipp_data_polarity rsds_ref
pxd20 microcontroller reference manual, rev. 1 46-36 freescale semiconductor preliminary?subject to change without notice 46.5.3.2 pad_n this is the ?negative? i/o signal connected bond pa d for the rsds output pad. the voltage supported by the pad is defined by the vref_rsds and vss associated with the cell. 46.5.4 cell description 46.5.4.1 rsds_ref - rsds reference cell this pad cell provides the current reference bias that is mirrored to set the output current for the rsds driver. this pad also provides a vo ltage reference that is used in the rsds driver common-mode feedback circuit. 46.5.4.2 rsds_tx - rsds transmitter cell this pad cell drives the differenti al pads, pad_p and pad_n with a spec ified offset volta ge (common mode voltage) and differential vol tage swing. this is done in current mode, i.e. curren t is sourced at pad_p and sinked at pad_n (and vice-vers a) depending on whether the data to be transmitted is high (or low). below is the illustrative diagram for the same. internally, it has h-bridge kind of out put stage with one current source and one current sink. there are four switches which steer the current into the load connected between pad_p and pad_n. this happens by controlling the switches in such a way that at one time, a set of two diagonal switches is on when incoming data is high, and the othe r set of two diagonal switches is on when data is low. thus, same amount of curr ent flows through load in opposite direction depending on the data value.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-37 preliminary?subject to change without notice figure 46-16. illustrative diagram of rsds driver 46.5.5 functionality and modes of operation: table 46-33. modes of operation modes description conditions normal (asynch) data transmission (asynchronous) rsds_ref_en = ipp_obe =1.2, normal (asynch positive edge) data transmission (asynchronous), with positive data polarity. rsds_ref_en = ipp_obe =1.2, ipp_data_polarity =0v normal (asynch, negative edge) data transmission (asynchronous), with negative data polarity. rsds_ref_en = ipp_obe =1.2, ipp_data_polarity = 1.2v power down (ref) rsds_ref is in power down. rsds_ref_en = 0 power down (driver) rsds_tx is in power down/disable. ipp_obe = 0 table 46-34. logic table for outputs ipg_powseq_dr_off rsds_ref_ en ipp_obe ipp_do pad_p pad_n 1x xxzz 00 xxxx 01 0 xzz
pxd20 microcontroller reference manual, rev. 1 46-38 freescale semiconductor preliminary?subject to change without notice 46.5.6 general some pad timing diagrams are included below. 46.5.7 timing diagrams figure 46-17. rise/fall transition 01 1 001 01 1 110 table 46-34. logic table for outputs (continued) ipg_powseq_dr_off rsds_ref_ en ipp_obe ipp_do pad_p pad_n rise time time fall 80% 20% 80% 20% crossover point differential data lines pad_p pad_n pad_p pad_n (tr) (tf)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 46-39 preliminary?subject to change without notice figure 46-18. enable time figure 46-19. rise & fall transition time for differential output signal (pad_p - pad_n) differential pad_p pad_n enable time ipp_obe outputs valid outputs (tdz) crossover point vo s
pxd20 microcontroller reference manual, rev. 1 46-40 freescale semiconductor preliminary?subject to change without notice 46.6 initialization/application information 46.6.1 tcon initialization the procedure to bring up the tcon out of reset state and start data and timing signal generation: 1. program tcon_compx and tcon_compx_msk registers to configure the comparator. 2. program tcon_pulsex and tcon_pulsex_msk re gisters to configure the pulse generator. 3. program tcon_smxx and tcon_lu tx registers if necessary. 4. program tcon_bmc (see section 46.3.3.2, bit mapping control (tcon_bmc) ) register to configure the bit mapping control. 5. program the tcon_ctrl1 (see section 46.3.3.1, control register 1 (tcon_ctrl1) ) register to configure the operation mode of tcon and enab le tcon (it?s recommended to do this in two steps, and set tcon_en in the second).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-1 preliminary?subject to change without notice chapter 47 video input unit (viu2) 47.1 introduction the viu2 is an enhanced version of the original vi deo-in (viu) block, with ne w features added including down-scaling, brightness and contrast adjustment, and yuv 4:2:2 output. figure 47-1 shows a block diagram of the viu2. figure 47-1. viu2 block diagram 47.1.1 features ? support from qvga to xvga 8-bit/10-bit itu656 video input 1 ? up to 1/8 video down-scaling ? support different scaling ratio on hor izontal and vertical direction ? brightness/contrast adjust ? yuv to rgb 888/565 conversion ? simple de-interlace function (weaving) for interlaced/or ps eudo interlaced video input ? internal dma engine for transfering data from fifo to system memory 47.2 memory map and register definition 47.2.1 memory map 1. when down scaling and/or b/c adjust is enabled, the two lsb?s of the 10-bit input are ignored. table 47-1. viu2 memory map address offset register access location 0x00 status and configuration register (scr) rw on page 47-5 0x04 luminance coefficients for red, green and blue matrix (luma_comp) rw on page 47-7 data[9:0] pixclock yuv2rgb registers irq ipm bus ips bus 4 ips_clk domain 1 5 dma engine synch ronizer ipg_clk domain fifo(256x64bit) pa d pa d hscale vscale b/c adjust 3 itu decoder 2 output formatter 6 7
pxd20 microcontroller reference manual, rev. 1 47-2 freescale semiconductor preliminary?subject to change without notice 47.2.2 register summary table 47-2 shows the viu2 register summary table. 0x08 chroma coefficients for red matrix (chroma_red) rw on page 47-8 0x0c chroma coefficients for green matrix (chroma_green) rw on page 47-9 0x10 chroma coefficients for blue matrix (chroma_blue) rw on page 47-9 0x14 base address of every field/fram e of picture in memory (dma_addr) rw on page 47-10 0x18 horizontal dma increment (dma_inc) rw on page 47-10 0x1c input video pixel and line count (invsz) rw on page 47-11 0x20 high ipm request priority alarm (hpalrm) rw on page 47-12 0x24 programable alpha value (alpha) rw on page 47-12 0x28 down scaling factor at horizonal direction (hfactor) rw on page 47-13 0x2c down scaling factor at vertical direction (vfactor) rw on page 47-13 0x30 down scaling destination pixel and line count (vid_size) rw on page 47-14 0x34 b/c adjust look-up-table current address (lut_addr) rw on page 47-14 0x38 b/c adjust look-up-table data entry (lut_data) rw on page 47-15 table 47-2. viu2 register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210 0x00 scr r mo de3 2bit ro und _on dit her _on fiel d_n o dm a_a ct sca ler _en rgb _en bc_ en mo de4 44 err or_ irq dm a_e nd_ irq vst art _ir q hsy nc_ irq vsy nc_ irq fiel d_i rq w w1c w1c w1c w1c w1c w1c r ecc _en err or_ en dm a_e nd_ en vst art _en hsy nc_ en vsy nc_ en fiel d_e n error_code format_ctrl sof t_r ese t w ox04 luma_comp r y_red[9:0] y_green[9:5] w r y_green[4:0] y_blue[9:0] w table 47-1. viu2 memory map (continued) address offset register access location
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-3 preliminary?subject to change without notice ox08 chroma_red r cr_red[10:0] w r cb_red[11:0] w ox0c chroma_gree n r cr_green[10:0] w r cb_green[11:0] w ox10 chroma_blue r cr_blue[10:0] w r cb_blue[11:0] w 0x14 dma_addr r addr[31:16] w r addr[15:3] w 0x18 dma_inc r w r inc w 0x1c invsz r linec w r pixelc w 0x20 hpalrm r w r alarm w 0x24 alpha r w r alpha[7:0] w table 47-2. viu2 register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210
pxd20 microcontroller reference manual, rev. 1 47-4 freescale semiconductor preliminary?subject to change without notice 0x28 hfactor r w r factor w 0x2c vfactor r w r factor w 0x30 vid_size r linec w r pixelc w 0x34 lut_addr r w r addr w 0x38 lut_data r data[31:16] w r data[15:0] w table 47-2. viu2 register summary name 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1514131211109876543210
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-5 preliminary?subject to change without notice 47.2.3 register descriptions 47.2.3.1 scr offset 0x00 access: user read/write 0123456 7 r mode32bit round_on dither_on field_no dma_act scaler_e n rgb_en bc_en w reset0000001 0 8 9 10 11 12 13 14 15 r mode444 error_ir q dma_end_i rq vstart_ir q hsync_irq vsync_irq field_irq w w1c w1c w1c w1c w1c w1c reset1000000 0 16 17 18 19 20 21 22 23 r ecc_en error_en dma_end_ en vstart_en hsync_en vsync_en field_en w reset0000000 0 24 25 26 27 28 29 30 31 r error_code format_ctrl soft_reset w reset0000000 0 = unimplemented or reserved figure 47-2. scr register
pxd20 microcontroller reference manual, rev. 1 47-6 freescale semiconductor preliminary?subject to change without notice table 47-3. scr fields field description soft_reset writing 1 to this bit generates an internal reset to all components except registers in viu2 block. this bit should be set by software when an error interrupt is detected, and it needs to be cleared by software to release the software reset. format_ctrl output pixel data format control. see below or refer to figure 47-20 for detailed definition. here 32-bit means mode32bit is set and 16-bit means mode32bit is cleared. rgb mode means rgb_en is set and yuv mode means rgb_en is cleared. c means u or v. dummy means ?don?t care? data. 16-bit rgb mode: 3'b000: {r[7:3], g[7:2], b[7:3]}; 3'b001: {g[4:2], b[7:2] , r[7:3], g[7:5]}; 32-bit rgb mode: 3'b000: {alpha, r, g, b}; 3'b001: {alpha, b, g, r}; 3'b010: {r, g, b, alpha}; 3'b011: {b, g, r, alpha}; 16-bit yuv mode: 3'b000: {c,y}; 3'b001: {y,c}; 32-bit yuv mode: 3'b000: {dummy, y, u, v}; 3'b001: {dummy, y, v, u}; 3'b010: {dummy, u, v, y}; 3'b011: {dummy, v, u, y}; 3'b100: {y, u, v, dummy}; 3'b101: {y, v, u, dummy}; 3'b110: {u, v, y, dummy}; 3'b111: {v, u, y, dummy}; error_code error code. signals e rrors that triggered error irq. 0000 : no error 0001 : dma arm command given during vertical active, dma_act does not accept the value on ips bus. 0010 : dma arm command given during vertical blanking when dma_act is set. 0100 : line too long 0101 : too many lines in a field/frame 0110 : line too short 0111 : not enough lines in a field/frame 1000 : fifo overflow 1001 : fifo underflow 1010 : one bit ecc error 1011 : two or more bits ecc error others: reserved field_en interrupt enable bit for field_irq. vsync_en interrupt enable bit for vsync_irq. hsync_en interrupt enable bit for hsync_irq. vstart_en interrupt enable bit for vstart_irq. dma_end_en interrupt enable bit for dma_end_irq. error_en interrupt enable bit for error_irq.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-7 preliminary?subject to change without notice 47.2.3.2 luma_comp ecc_en enable bit for ecc error reporting. viu will also trigger interrupt upon detecting one or more errors.. field_irq interrupt status bit. write ?1? to clear field_irq. vsync_irq interrupt status bit. write ?1? to clear vsync_irq. hsync_irq interrupt status bit. write ?1? to clear hsync_irq. vstart_irq interrupt status bit. write ?1? to clear vstart_irq. dma_end_irq interrupt status bit. write ?1? to clear dma_end_irq. error_irq interrupt status bit. write ?1? to clear error_irq. mode444 yuv 4:4:4 mode enable bit. when it?s set itu dec oder sends out yuv 4:4:4 form at data, otherwise yuv 4:2:2 is sent by default. it shall be cleared when down scaling is enabled because the down-scaler works on yuv 4:2:2 format. bc_en bright/contrast adjust enable. rgb_en yuv to rgb conversion enable. scaler_en down scaling enable. dma_act dma transfer of current field/frame is busy (write by software, cleared at end of transfer). when dma_act is cleared, input video data is ignored and not put into fifo. field_no field number, extracted from itu-656 stream. dither_on dithering is on. used when vi deo data is stored in buffer as rgb 565 format and round_on is not set. round_on round is on. used when video data is stored in buffer as rgb565 format. mode32bit select 32-bit or 16-bit output. 0 : 16-bit rgb or yuv 4:2:2 output 1: 32-bit rgb or yuv 4:4:4 output. dither_on and round_on are ignored if output is 32-bit rgb. offset 0x04 access: user read/write 0123456789101112131415 r y_red[9:0] y_green[9:5] w reset10010101 00010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y_green[4:0] y_blue[9:0] w reset10100010 01010100 = unimplemented or reserved figure 47-3. luma_comp register table 47-3. scr fields field description
pxd20 microcontroller reference manual, rev. 1 47-8 freescale semiconductor preliminary?subject to change without notice the rgb pixel value is computed using following formulae: eqn. 47-1 eqn. 47-2 eqn. 47-3 the multiplications with y_red, y _green, and y_blue are unsigned mult iplications. the multiplications with cr_red, cb_red, cr_gr een, cb_green, cr_blue, and cb_blue ar e signed multiplications. the addition is saturated to prevent overflow. 47.2.3.3 chroma_red table 47-4. luma_comp fields field description y_red[9:0] luminance coefficient for red matrix. y_green[9:0] luminance coefficient for green matrix. y_blue[9:0] luminance coefficient for blue matrix. offset 0x08 access: user read/write 0123456789101112131415 r cr_red[10:0] w reset00000011 00110001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cb_red[11:0] w reset00000000 00000000 = unimplemented or reserved figure 47-4. chroma_red register table 47-5. chroma_red fields field description cr_red[10:0] cr coefficient for red matrix. cb_red[11:0] cb coefficient for red matrix. red y16 ? ?? yred ? 512 ------------------------------------ - cr 128 ? ?? crred 512 ----------------------------------------- cb 128 ? ?? cbred 512 ------------------------------------------- ++ = green y16 ? ?? ygreen ? 512 -------------------------------------------- - cr 128 ? ?? crgreen 512 ----------------------------------------------- - cb 128 ? ?? cbgreen 512 ------------------------------------------------- - ++ = blue y16 ? ?? yblue ? 512 --------------------------------------- - cr 128 ? ?? crblue 512 -------------------------------------------- cb 128 ? ?? cbblue 512 ---------------------------------------------- ++ =
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-9 preliminary?subject to change without notice 47.2.3.4 chroma_green 47.2.3.5 chroma_blue offset 0x0c access: user read/write 0123456789101112131415 r cr_green[10:0] w reset00000110 01100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cb_green[11:0] w reset00001111 00111000 = unimplemented or reserved figure 47-5. chrom a_green register table 47-6. green_chrom a_coefficients fields field description cr_green[10:0] cr coefficient for green matrix. cb_green[11:0] cb coefficient for green matrix. offset 0x10 access: user read/write 0123456789101112131415 r cr_blue[10:0] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cb_blue[11:0] w reset00000100 00001001 = unimplemented or reserved figure 47-6. chroma_blue register table 47-7. chroma_blue fields field description cr_blue[10:0] cr coefficient for blue matrix. cb_blue[11:0] cb coefficient for blue matrix.
pxd20 microcontroller reference manual, rev. 1 47-10 freescale semiconductor preliminary?subject to change without notice 47.2.3.6 dma_addr 47.2.3.7 dma_inc offset 0x14 access: user read/write 0123456789101112131415 r addr[31:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr[15:3] w reset00000000 00000000 = unimplemented or reserved figure 47-7. dma_addr register table 47-8. dma_addr fields field description dma_address[31:3] base address of every field of pict ure in memory used by dma. rewrite only after receiving dma done interrup t and before arming dma. the lowest 3 bits of dma_address cannot be set. it is always 3?b0. see section 47.4.2/47-24 for more details. offset 0x18 access: user read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inc w reset00000000 00000000 = unimplemented or reserved figure 47-8. dma_increment register
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-11 preliminary?subject to change without notice 47.2.3.8 invsz table 47-9. dma_inc fields field description inc value of this field should be zero or memory size that one active line occupies in memory. it will be added to the memory mapped rounded address at the end of every line. see section 47.3.9/47-21 . memory size of one active line depends on line pixel number. it is ? pixel_count[15:2] + |pixe l_count[1:0] when mode32bit=0; ? pixel_count[15:1] + pixe l_count[0] when mode32bit=1; it shall only be configured when dma is inactive, during vertical blanking. see section 47.4.2/47-24 for more details. offset 0x1c access: user read/write 0123456789101112131415 r linec w reset00000000 11110000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pixelc w reset00000010 11010000 = unimplemented or reserved figure 47-9. invsz register table 47-10. invsz fields field description linec expected number of active lines in each input video field/frame. it shall only be configured when dma is non-active, during vertical blanking. see section 47.4.2/47-24 for more details. if more lines are found during data receive part, a too many lines error interrupt is generated when error_irq is set. redundant lines are discarded. if less lines are found during data receive part, a not enough lines error interrupt is generated when error_irq is set. pixelc expected number of active pixels in each inpu t video line, it shall be integer multiply of 4. it shall only be configured when dma is non-active, during vertical blanking. see section 47.4.2/47-24 for more details. if more pixels are found during data receive part, a line too long error interrupt is generated when error_irq isset. redundant pixels are discarded. if less pixels are found during data receive part, a line too short error interrupt is generated when error_irq is set.
pxd20 microcontroller reference manual, rev. 1 47-12 freescale semiconductor preliminary?subject to change without notice 47.2.3.9 hpalrm 47.2.3.10 alpha offset 0x20 access: user read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r alarm w reset00000000 10010000 = unimplemented or reserved figure 47-10. hpalrm register table 47-11. hpalrm fields field description alarm high priority alarm threshold. when fifo_fill is higher than this value, high priority bus request will be asserted. offset 0x24 read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r alpha[7:0] w reset00000000 11111111 = unimplemented or reserved figure 47-11. alpha register table 47-12. alpha fields field description alpha[7:0] alpha value used for picture blending. this r egister is configured during vertical blanking and used from the next video field.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-13 preliminary?subject to change without notice 47.2.3.11 hfactor 47.2.3.12 vfactor offset 0x28 access: user read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r factor w reset00000001 00000000 = unimplemented or reserved figure 47-12. factor_h register table 47-13. factor_h fields field description factor down scaling factor at horizonal direction. factor[10:8] is used as integer part of the factor. factor[7:0] is used as fractional part of the factor. offset 0x2c access: user read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r factor_v w reset00000001 00000000 = unimplemented or reserved figure 47-13. vfactor register table 47-14. vfactor fields field description factor down scaling factor at vertical direction. factor[10:8] is used as integer part of the factor. factor[7:0] is used as fractional part of the factor.
pxd20 microcontroller reference manual, rev. 1 47-14 freescale semiconductor preliminary?subject to change without notice 47.2.3.13 vid_size 47.2.3.14 lut_addr offset 0x30 access: user read/write 0123456789101112131415 r linec w reset00000000 11110000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pixelc w reset00000010 11010000 = unimplemented or reserved figure 47-14. vid_size register table 47-15. vid_size fields field description linec expected number of lines in each output video frame after down scaling. pixelc expected number of pixels in each output video line after down scaling. it shall be multiply of 2 in 32-bit output mode, and multiply of 4 in 16-bit output mode. offset 0x34 access: user read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr w reset00000000 00000000 = unimplemented or reserved figure 47-15. lut_addr register table 47-16. lut_addr fields field description addr current address pointer of the b/c adjust look-up- table. value of this register increments (by 4) automatically at the end of each lut_data write ope ration. this function allows fast update to the whole look-up-table, to the table of one color component, or even to any random field of the table. note: lut_addr reflects correct address only when clock of b/c adjust block is valid.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-15 preliminary?subject to change without notice 47.2.3.15 lut_data 47.3 functional description the viu2 accepts itu-r bt.656 compatible video st ream on its parallel interface, decodes it and optionally performs processes like down-scaling, brightness and contrast adjust, yuv to rgb conversion, and de-interlace (weaving), and then st ores the result video stream to the system memory which can then be displayed by a display c ontroller, or post processed. functions of the viu2 are designed in a way that they can be flexibly enabled or disable by software. but there are a few limitations as listed below: ? the down-scaler works on yuv 4:2: 2 format, so to enable the dow n-scaler itu decoder shall be configured in yuv 4:2:2 mode. ? to use the down-scaler, progressive video input shall be used for display quality?s sake, and the de-interlace shall be disabled. 47.3.1 itu656 the itu-r bt.656-4 recommendation de scribes the means of interconnec ting digital tele vision equipment operating on the 525-line or 625-line standards and combines with th e 4:2:2 encoding parameters as defined in the itu-r bt.601 recommendation. the data stream structure on itu- r bt.656-4 interface is shown in figure 47-17 . there are two timing reference signals, one at th e beginning of each video da ta block (start of active video, sav) and one at the end of each video data bloc k (end of active video, eav). offset 0x38 access: user read/write 0123456789101112131415 r data[31:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data[15:0] w reset00000000 00000000 = unimplemented or reserved figure 47-16. lut_data register table 47-17. lut_data fields field description data b/c adjust look-up-table data entry. data in this re gister is actually written/read to/from the address pointed by the current lut_addr value in the table. note: data reflects correct data value only when clock of b/c adjust block is valid.
pxd20 microcontroller reference manual, rev. 1 47-16 freescale semiconductor preliminary?subject to change without notice figure 47-17. interface data stream of itu-r bt.656-4 each timing reference signal consists of a four-w ord sequence in the following format: ff 00 00 xy. values are expressed in hexadecimal notation. value ff and 00 are reserved to be used in the timing reference signals. the first three words are a fixed preamble. the f ourth word contains information defining field 2 identification, the state of field blanking, and the stat e of line blanking. the assi gnment of bits within the timing reference signal is shown in table 47-18 . in above table, bits p0, p1, p2, p3 ha ve states dependent on the states of the bits f, v and h. at th e receiver side this arrangement pe rmits one-bit errors to be corrected and two-bit errors to be detected. note that when used in progressive video mode (instead of interlaced mode), where frames are transfered versus odd and even fields, the f bit can be either ignored or considered as indication of frames. refer to the itu-r bt.656-4 recommendation for more details. table 47-18. video timing reference codes data bit number first word (ff) second word (00) third word (00) fourth word (xy) 9(msb) 1 0 0 1 8100f(0: field 1, 1: field 2) 710 0 v(0: elsewhere, 1: field blanking) 610 0 h(0: in sav, 1: in eav) 510 0 p3 410 0 p2 310 0 p1 210 0 p0 110 0 0 010 0 0 cb359 y718 cr359 y719 eav sav cb0 y0 cr0 y1 timing reference signals
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-17 preliminary?subject to change without notice 47.3.2 input synchronizer the synchronizer block (1) captures itu656 protocol signals from the interfac e, and synchronizes them to the ipg_clk domain. 47.3.3 itu decoder the itu decoder block (2) detects the itu656 timing reference signal (consists of a four-word sequence in the following format: ff-00-00-xy) and extrac ts hsync, vsync, field number signals and video data from the itu data stream. the format of active pixel data from the itu stream is yuv 4:2:2. the decoder block can directly send out this yuv 4:2:2 data, or interpolat e it to yuv 4:4:4 format and send out. this is determined by the mo de444 field in the scr register ( 47.2.3.1/47-5 ). this bit shall not be set if the down-scaler is enabled, because the down-scaler works on yu v 4:2:2 data format. 47.3.4 down scaling the down-scaler block (3) performs down-scaling to the incoming video stream. it?s able to scale down the input video stream by a frac tional scaling ratio up to 1/8. the down-scaler block can be enabled/disabled by softwa re via the scaler_en bit in the scr re gister. to use the down-scaler video data extracted from it u decoder shall be in yuv 4:2:2 format. the down-scaler uses a bi-linear filt er with simple linear interpolation between th e two nearest neighbors, on both horizontal and vertical direction. scaling is fi rstly done on the horizonal di rection (called xscale), and then the vertical direction (called yscale). different scaling factors are supported on horizonal direction and vert ical direction. assuming the scaling factors are (factor _h, factor_v), in theory for every pixel (x, y) of the scaled picture the coordinates of the corresponding pixel in th e incoming picture (x1, y1) can be calculated by multiplying the coordinates with the scaling fact ors, say (x1 = x * factor_h, y1 = y * factor_v). now because the scaling fa ctors can be fractions, the coordinates (x1, y1) are not integer anymore, they are fractional values. the scalers use the integer part of (x1, y1) to find the two neighboring pixels from the incoming picture as input to the fi lters, and the fractional part to derive the weighting factors for interpolation. the scaling factors, (factor_h, factor _v), are both 11 bit with the lower 8 bit as the factional part and the highest 3 bit the integer part. it?s capable of scaling the input picture by up to 8, in steps of 1/256. it?s by 8 if the factor is programmed as all zeros. instead of using multipliers to calcu late (x1, y1), two 20-bit phase accumu lator is used to step through the source pixels/or lines, where the lowe r 8 bit is the fractional part. for ev ery output pixel/or line the phase adder is added to the accumulator. with the 12 bit integer part of the accumulator, up to 4096 source pixels/or lines can be supported. so for each target pixel, the curre nt accumulator position is used to de termine how the pixel is going to be produced. as an example, accumulator value 0x123.3a means the step positi on is between pixel[0x123] and pixel[0x124], and the output pi xel will be calculated by (pixel [0x124] * (0x100 - 0x3a) + pixel[0x123] * 0x3a) >> 8. the same concept is used for horizontal and vertical scaling.
pxd20 microcontroller reference manual, rev. 1 47-18 freescale semiconductor preliminary?subject to change without notice because ot the vertical scaling, a line buffer is used for each color component to store the data from horizontal scaling, it stores one line of data. size of the line buffer dete rmines the maximum video output size after scaling the scaling factors are pr ogrammed via the hfactor ( 47.2.3.11/47-13 ) and vfactor ( 47.2.3.12/47-13 ) registers. and video size after scaling is programmed via the vid_size register ( 47.2.3.13/47-14 ). three scalers are instantiated in the dow n-scaler block, one for each component. note the scaled pixel count per line shall be integer multiply of 2 in 32-bit output mode, or 4 in 16-bit output mode. the us er shall divide the input pixel count by the horizontal scaling fa ctor and truncate the result to multiply of 2 or 4. note to achieve good display quality, progressi ve video input shall be used if down-scaling is needed. 47.3.5 brightness and contrast adjust the b/c adjust block (4) performs brightness and contra st adjustment to the input video stream via three internal look-up-tables, one table per color component. each table c ontains 256 8-bit entries, it maps every incoming pixel to the value of one of it?s entries according to the original value of the pixel. the component is then replaced by the value in the tabl e. if the incoming stream contains 10 bits per component, then only the 8 most signi ficant bits are mapped to the look-up table. th is feature allows the user to adjust brightness and/or contrast of the in coming picture according to th ree arbitrary adjustment curves, one adjustment curve per color component. to use this feature, the b/c adjust look-up-table shal l be programmed in software in the following format.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-19 preliminary?subject to change without notice figure 47-18. b/c adjust look-up-table format two registers are provided to program th e look-up-table, they are lut_addr ( 47.2.3.14/47-14 ) and lut_data ( 47.2.3.15/47-15 ). lut_addr is the current address pointer, which always points to the current table offset to be programmed. it can be set by software, a nd it increases (by 4) automatically when each word is written to th e table, and it falls back to 0x000 if the current va lue is 0x2fc and the last word is written to the table. lut_data is the table data entr y, data written to this register will be stored into the table, to the address pointed to by lut_addr. this register shall only be written by 4-byte word. with combination of these two registers user can program the b/c look-up-tabl e conveniently, either program the whole table, or reprogram the table for one color comp onent only, or even change one single arbitrary word in the table. the b/c adjust can be enabled/disa bled by software via the bc_en bi t in the status_config register ( 47.2.3.1/47-5 ). 47.3.6 yuv to rgb conversion the yuv2rgb block (5) is used to convert yuv (4:2:2 or 4:4:4) to rgb (888 or 565). the coefficients of the yuv to rgb conversion matrix are programmed via four registers ( 47.2.3.2/47-7 , 47.2.3.3/47-8 , 47.2.3.4/47-9 , 47.2.3.5/47-9 ). when the input is yuv 4:2:2, it?s interpolated to yuv 4:4:4 first. 47.3.7 round and dither in rgb565 output mode, when pixel data is converted from rgb888 to rgb565 the image is anamorphic more or less, because of losing colo r information conveyed by the least si gnificant two or three bits of the original color components, which are dropped. vi u2 block provides two simple algorithms, round and dither, to compensate this color information loss. table 47-19. color component bc lut offset local address [1:0] 00 01 10 11 y 0x000 bc0 y bc1 y bc2 y bc3 y ...... 0x0fc bc252 y bc253 y bc254 y bc255 y u 0x100 bc0 u bc1 u bc2 u bc3 u ...... 0x1fc bc252 u bc253 u bc254 u bc255 u v 0x200 bc0 v bc1 v bc2 v bc3 v ...... 0x2fc bc252 v bc253 v bc254 v bc255 v
pxd20 microcontroller reference manual, rev. 1 47-20 freescale semiconductor preliminary?subject to change without notice 47.3.7.1 round in round mode, viu2 will round in 1 to lsb if the decimal fraction is bigge r than 0.5 and ignore the smaller fraction when round_on is se t in the status_config register ( 47.2.3.1/47-5 ). 47.3.7.2 dither dither is a little more complex but better than round for recovering image. it?s a statistical compensation algorithm. it doesn?t render all pixels with the same grey or color leve l, but some with the lower one, and some with a color level of 1 lsb more. the selec tion of adding one lsb or not depends on the position of the pixel on the screen. figure 47-19 shows the implementation of dither in the viu2 block. figure 47-19. dither implementation the number above the pixel position in the diagram is the compensation value for th is pixel. when pixels have a value of 0.25, they are rendered 0 in 75 ? of the pixels and 1 in 25 ? of pixels. this averages to 0.25. similarly, pixel values of 0.5, 0.75, and 1.0 are rendered 50 ? , 75 ? and 100 ? of the pixels as 1. for human eyes, this rendering result of dither makes the holistc image smoothe r and closer to the original one. 47.3.8 output formatter the output formatter block (6) accepts yuv or rg b data from the yuv2rgb block, arranges them in expected format, and then sends it to the dma engine. the format_ctrl field in status_config register controls how the viu2 st ores data to system memory, see figure 47-20 for details. figure 47-20. viu2 output data stream format pixel format format_ ctrl 1 local address [2:0] 000 001 010 011 100 101 110 111 rgb 565 000 r0[7:3], g0[7:2], b0[7:3] r1[7:3], g1[7:2], b1[7:3] r2[7:3], g2[7:2], b2[7:3] r3[7:3], g3[7:2], b3[7:3] 001 2 g0[4:2], b0[7:3], r0[7:3], g0[7:5] g1[4:2], b1[7:3], r1[7:3], g1[7:5] g2[4:2], b2[7:3], r2[7:3], g2[7:5] g3[4:2], b3[7:3], r3[7:3], g3[7:5] rgb 8888 000 a0 r0 g0 b0 a1 r1 g1 b1 001 a0 b0 g0 r0 a1 b1 g1 r1 010 r0 g0 b0 a0 r1 g1 b1 a1 011 b0 g0 r0 a0 b1 g1 r1 a1 0 0.25 0.5 0.75 0 0.5 0.25 0.75 0 0.5 0 0.5 0.25 0.75 0.25 0.75 line0 line1 line2 line3
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-21 preliminary?subject to change without notice 47.3.9 dma and de-interlace the dma engine block (7) functions as the fifo controller and dma engi ne. it stores the data from the output formatter block into a fifo and then writes them to syst em memory via the ipm interface. viu2 block has an embeded dma. when video data leaves the output formatter and is placed into a 256 64 bit fifo, it waits for transferin g to memory by this internal dma. after doing some necessary regist er configuration, such as coeffi cients, invsz and dma_addr, user can activate dma by setting the dma_act of the stat us and configuration register. but note that dma_act can be configured only during vertical bla nking since viu2 block won? t transfer a fragment of video field to memory. if it?s co nfigured during field active time, dm a transfer can not be started and an error interrupt will be asserted. the viu2 block asserts a transfer request when data in fifo is enough for one transfer. normally one transfer conveys 32 bytes from fifo to memory. while at the end of a li ne, all remaining da ta of this line is transfered, though it may not be 32 bytes. viu2 also provides a simple way to de-interlace for interlaced/or pseudo interlaced video image. it is implemented by setting dma_ad dr and dma_inc registers. figure 47-21 shows the implementation of de-interlace. value of dma_inc is added to the rounded address at the end of every active li ne. so, when dma_inc is zero, pixel data is stored in memory line by line, meaning de-interlace is off, as shown in figur e (1) and (2) ; otherwise when dma_inc equals to one-line memory mapped pixel size, and dma_a ddr(2) = dma_addr(1) + dma_inc, odd field and even field will be merged into one fr ame in memory, as shown in figure (3). yuv 4:2:2 000 u0 y0 v0 y1 u2 y2 v2 y3 001 y0 u0 y1 v0 y2 u2 y3 v2 yuv 4:4:4 000 dummy y0 u0 v0 dummy y1 u1 v1 001 dummy y0 v0 u0 dummy y1 v1 u1 010 dummy u0 v0 y0 dummy u1 v1 y1 011 dummy v0 u0 y0 dummy v1 u1 y1 100 y0 u0 v0 dummy y1 u1 v1 dummy 101 y0 v0 u0 dummy y1 v1 u1 dummy 110 u0 v0 y0 dummy u1 v1 y1 dummy 111 v0 u0 y0 dummy v1 u1 y1 dummy 1 all values not shown in the table shall be considered as reserved and shall not be used. 2 this format is basically intended for da ta communication with any little-endian peri pheral in the system, assuming big-endian system memory is used. figure 47-20. viu2 output data stream format pixel format format_ ctrl 1 local address [2:0] 000 001 010 011 100 101 110 111
pxd20 microcontroller reference manual, rev. 1 47-22 freescale semiconductor preliminary?subject to change without notice here dma_addr(1) means base addr ess of field 1, and dma_addr(2) means base address of field 2. memory mapped line size means memory size that occupied by one active line pixels. it depends on pixel number of one line and video data format (rgb888 or rgb565). see register description in section 47.2.3.7/47-10 . figure 47-21. implemen tation of de-interlace 47.3.10 error case normally, user should provide a st andard and totally itu-compatible video stream to viu2 block. however, it?s difficult to avoid unexpected errors al l the time. viu2 can mana ge error cases like ecc error, line too long, line too shor t, too many lines, or not enough li ne in a field, even fifo overflow. ? ecc error: itu stream provides 4-bit error corr ecting code p[3:0] in its sav and eav. it is decoded in viu2 to use correct fi eld number, horizonal sync and vert ical sync bits. it can correct one bit error and find two bits error. when ecc error is found, an in terrupt is asserted. ? line too long error: when pixels of active line is longer than pixelc , a line too long error interrupt is asserted and re dundant pixels are discarded. ? too many lines error: when active lines of a fi eld are bigger than linec, a too many lines error interrupt is asserted and redundant lines is discarded. ? line too short error: when pixels of active line is less than pixelc, a line too short error interrupt is asserted. ? not enough line error: when active lines of a fi eld is less than linec, a not enough line error interrupt is asserted. ? fifo overflow error: if system bus is blocked for a long time, vide o data is stored in fifo and makes fifo overflow. when fifo is overflow, an interrupt is asserted, and the coming data is discarded until fifo works normally again. current field is jumble d. however, viu2 recovers to work at the next field if bus is unblocked at that time. ? fifo underflow: when fifo is read when it?s em pty, a fifo underflow erro r interrupt is asserted. normally, this error shouldn?t occur. viu2 can manage above error cases to a certain extent . however, when it doesn?t recover to work, user should write the soft_reset bit of the status a nd configuration register to reset viu2 block. dma_addr(1) dma_addr(2) field 1 field 2 (1) (2) line 1 line 2 line 3 line n line 1 line 2 line 3 line n dma_addr(1) (3) line 1 line 2 line 3 line n field 1 field 1 field 1 field 1 field 2 field 2 field 2 line 1 line 2 line n dma_addr(2)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 47-23 preliminary?subject to change without notice 47.4 initialization/application information 47.4.1 initialization information when viu2 block comes out of rese t, software should implement the fo llowing steps to start this block. 1. program status_config register ( 47.2.3.1/47-5 ) to set the viu2 to desired operation mode ? to enable yuv 4:2:2 to 4:4:4 interpolat ion in itu decoder, set the mode444 bit 1 ? to enable down-scaler, set the scaler_en bit ? to enable b/c adjust, set the bc_en bit ? to enable rgb565 output mode, set rgb_en bit and clear mode32bit bit. optionally set dither_on or round_on bit to enable dither or round 2 ? to enable argb8888 output mode, set rgb_en and mode32bit bit ? to enable yuv output mode, clear rgb_en bit 2. set the format_ctrl field so that viu2 output s data in correct form at. configure the input video size via the invsz register ( 47.2.3.8/47-11 ). 3. if want to use rgb out put, configure yuv to rgb conversion coefficients ( 47.2.3.2/47-7 , 47.2.3.3/47-8 , 47.2.3.4/47-9 , 47.2.3.5/47-9 ) or use the default values after reset. 4. if want to use the down scaling func tion, program the down scaling factors ( 47.2.3.11/47-13 , 47.2.3.12/47-13 ), and destination video size after scaling ( 47.2.3.13/47-14 ). 5. if want to use the b/c adjust function, program the b/c adjust look-up-table via the lut_data ( 47.2.3.15/47-15 ) and lut_addr ( 47.2.3.14/47-14 ) registers. 6. configure the hpalrm ( 47.2.3.9/47-12 ) and alpha ( 47.2.3.10/47-12 ) registers if necessary. 7. set the vsync_en and/or field_en bits in stat us_config register to enable vsync or field interrupt. meanwhile, disable error interrupt. 8. when software receives vsync interrupt a nd/or field interrupt, read field_no bit of status_config register 3 . 9. according to field_no bit, pr ogram the dma_addr register ( 47.2.3.6/47-10 ). this is the field start address in system memory , or frame start address in progressive video input mode. 10. if want to use the de-interlace (weaving) function, program the line start address offset value in the dma_inc ( 47.2.3.7/47-10 ) register 4 . 11. clear error status first if necessary. 12. write dma_act bit of status_config regist er to start fifo and dma transfer. this operation actually starts the viu2 to operate. 1. mode444 bit shall not be set when the down-scaler is enabled. 2. if dither_on or round_on are both set, only round will be enabled. 3. reading the field_no bit is optional, espe cially in progressive video input mode. 4. progressive video input shall be used when down scaling is enabled for better display quality.
pxd20 microcontroller reference manual, rev. 1 47-24 freescale semiconductor preliminary?subject to change without notice 47.4.2 application information normally, the user shall not change the register values of the function enable bits, input/o utput video size, color conversion coefficients, dma_inc, mode32bi t, scaling factors and b/c adjust loop-up-table contents after viu2 is started up. when video i nput source is changed, user should reset viu2 and re-configure related registers. 47.4.2.1 register configuration timing window as mentioned above, dynamic configur ation on registers is not recommended becaus e it may cause error if it?s not configured in a certain timi ng window, especially for invsz and dma_inc. register configurati on timing window is shown in be low diagram. all registers, except soft_reset bit, are recommended to be configured during vertical blanking, after dma transfer is done and field identification bit is changed (f ield interrupt is asserted). figure 47-22. register conf iguration timing window configuration timing window f v h dma_done
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 48-1 preliminary?subject to change without notice chapter 48 voltage regulators and power supplies 48.1 introduction this device includes three on-chip voltage regulator s for power management and distribution, allowing low-power operation and optimi zation of power consumption. on this device, the general purpose inputs and outputs (gpio) are arranged in several banks with separate external gpio power supply pins, allowing groups of gpio to opera te at different supply voltages. 48.2 power-up sequencing the preferred power-up sequence for pxd20 is as follows: 1. generic io supplies or noise -free supplies, consisting of: ? vdda ? vdde_a ? vdde_b ? vddm ? vdd_dr ? vdd33_dr ? vddpll 2. all 3.3v supplies (vdde_b & vdd33_dr) should be ramped up first, and then the rest of the i/o supplies should be ramped up (vdda, vdde_a, vddm, vdd_dr). 3. vddr, the regulator input supply, should be the last suppl y to ramp up; all supplies can be ramped up together as long as vddr is included. so al l 5v supplies should be ramped up after the 3.3v supplies, and if all the supplies ar e of the same level, they can be ramped up together as well. 4. lv supply (vdd12). if vreg is in bypass mode and the core suppl y (1.2v) is suppl ied externally, then this should be the last supply given. note for ddr, the 3.3 v supply (vdd33_d r) should come before vdd_dr. this sequence ensures that when vreg releases it s lvds, the io and other hv segments are powered properly. this is important because pxd20 doesn't moni tor lvds on io hv supplies. 48.3 voltage regulators the internal voltage regulator s are used to provide a 1.2 v digital suppl y to the internal logic of the device. the main/input supply is 3.3 v to 5.0 v 10% and the digital/regulated output supply is 1.2 v 10%. the voltage regulator used in this device comprises three regulators. ? high power or main regulator (hpreg) requi ring an external npn ballast transistor. ? low power regulator (lpreg)
pxd20 microcontroller reference manual, rev. 1 48-2 freescale semiconductor preliminary?subject to change without notice ? ultra low power regulator (ulpreg) the hpreg and lpreg regulators are switched off in standby mode to sa ve power consumption by the regulator itself. during stop a nd halt modes only, the hpreg regul ator may be switched off. the ulpreg regulator is always kept on. the internal voltage regulators require an external cap acitance to be connected to the 1.2 v supply pins in order to provide a stable low volta ge digital supply to the device. capacitances should be placed on the board as near as possible to the associated pins. the regulator has two digital domains, one for the ma in regulator (hpreg) and the low power regulator (lpreg) called the ?high power domai n,? and one for the ultra low pow er regulator (ulpreg) called the ?standby domain.? for each domain there is a low vol tage detector (lvd) fo r the 1.2 v output voltage (ulvdd and mlvdd). additiona lly, there are two low voltage dete ctors for the main /input supply with different thresholds, one at 3.3 v (u lvdm), the other at 5 v (ulvdm5).
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 48-3 preliminary?subject to change without notice 48.3.1 block diagram figure 48-1. voltage regulator diagram 48.3.2 external signals table 48-1 provides an overview of the volta ge regulator external signals. core mlvdd bkup ulvdm5 ulvdd ulvdm por hpreg lpreg ulpreg vplusio vplusio vplusio vboard npn
pxd20 microcontroller reference manual, rev. 1 48-4 freescale semiconductor preliminary?subject to change without notice 48.3.3 detailed signal descriptions 48.3.3.1 vddr vddr is the 3.3 v to 5 v supply for the vol tage regulators and lvd blocks. see the pxd20 microcontroller data sheet for details of recommended dec oupling capacitance on this pin. 48.3.3.2 vrc vrc is the 1.2 v regulator output that drives the base of the external npn ballast transistor. 48.4 memory map and register definition 48.4.1 voltage regulator cont rol register (vreg_ctl) table 48-1. voltage regulator external signals name type voltage description vddr supply 3.0 v - 5.5 v power supply for the voltage regulators vssr ground - ground supply for digital core and voltage regulators vrc output - regulator drive for external npn transistor base table 48-2. voltage regulator memory map address register location vreg_base + 0x0000 vreg_ctl - voltage regulator control register on page 48-4 address offset: 00h access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5v_lvd _mask w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 figure 48-2. voltage regulator control register (vreg_ctl)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 48-5 preliminary?subject to change without notice 48.5 functional description 48.5.1 high power or main regulator (hpreg) the hpreg converts the 3.3 v to 5 v input supply voltage to the 1.2 v digital supply. the nominal target output is 1.2 v. the actual output will be in range of 1.08?1.32 v in th e full current load range 0?400 ma after trimming. the hpreg regulator requires an ex ternal npn ballast transistor. r ecommended transistors are njd2873 or bcp68 from on semiconductor. stabilization of the hpreg is achi eved using an external capacitan ce. the minimum recommended value is 600 nf with low esr. limit the series inductance per pad to less than 15 nh. the regulator is enabled by the mvro n bits in the m ode configuration register s in the mc_me module. these bits allow the regulator to be opti onally disabled in certain low power modes. 48.5.2 low power re gulator (lpreg) the lpreg generates power for the chip in stop m ode, providing the output suppl y of 1.2 v. the control part of the regulator can be used to disable the lo w power regulator. this action is managed by mc_me. 48.5.3 ultra low power regulator (ulpreg) the ulpreg generates power for th e standby domain as well as a part of the main domain. the control circuit of ulpreg ca n be used to disable the ultra low power regulator by sw. this action is managed by mc_me. 48.5.4 low voltage detectors (lvd) and power on reset (por) four lvds are available (see figure 48-1 ). ? ulvdm for the 3.3 v to 5 v input supply with threshold at the 3.3 v level ? ulvdm5 for the 3.3 v to 5 v input suppl y with threshold at the 5 v level ? two lvd_digs, ulvdd and mlvdd, for the 1.2 v output voltage ulvdm and ulvdm5 sense the 3.3 v to 5 v power supply for the core digital logic, shared with the gpio ring supply, and indicate when the 3.3 v to 5 v supply is stable. th e threshold levels of ulvdm5 are factory-trimmed. table 48-3. vreg_ctl field descriptions field description 5v_lvd_mask 5v lvd mask : mask bit for 5 v lvd from regulator this is a read/write bit and must be unmasked by writing a ?0? by software to generate lvd functional reset request to mc_rgm for 5 v trip. 1 5 v lvd is masked 0 5 v lvd is not masked.
pxd20 microcontroller reference manual, rev. 1 48-6 freescale semiconductor preliminary?subject to change without notice two lvd_digs are provided in the design. one lvd_di g is placed in the high power domain and senses the hpreg/lpreg output, indicating that the 1.2 v output is stable. the other lvd_dig is placed in the standby domain and senses the stand by 1.2 v supply level, indicating that the 1.2 v output is stable. the reference voltage used for all lvds is genera ted by the low power reference generator and is factory-trimmed for lvd_dig. th erefore, during the pre-trimming period, lvd_dig exhibits higher thresholds whereas, after trimming, the thresholds come within the desired range. power-down pins are provided for lvds. when lvds are power ed down, their outputs are pulled high. por is required to initialize the ch ip during the voltage s upply rise time. por works only on the rising edge of the main supply voltage. to ensure that it functions during the following rising edge of the supply voltage, it is reset by the output of the ulvdm block when the main supply goes below the lower voltage threshold of ulvdm. por is asserted on power-up when the vdd supply is above the minimum value of v porup (refer to the device data sheet for this valu e). it will be released only after the vdd supply goes above v porh (refer to the device data sheet for this value). vdd above v porh ensures that the power management module, including the internal lvd modules, are fully functional. 48.5.5 vreg digital interface the voltage regulator digital interface provides the temporization delay at initial power-up and at exit from low-power modes. a signal, indicating that ultra lo w power domain is powered, is used at power-up to release reset to temporization count er. at exit from low-power mode s, the power-down for high power regulator request signal is monitored by the digital interface and used to release reset to the temporization counter. in both cases, on co mpletion of the delay counter , an end-of-count signal is released; this is gated with an other signal indicating that the main domain voltage is fine, in order to release the vregok signal. this is used by mc_rgm to release the reset to the device. it manages other specific requirements, including the transition be tween high power or low power mode to ultra lo w power mode, avoiding a voltage drop below the permissi ble threshold limit of 1.08v. the vreg digital interface also contai ns a control register to mask th e 5 v lvd status from the voltage regulator at power-up. 48.6 gpio power supply configuration the gpio pins on this device are organized in four separate banks. each ba nk has associated vdd/vss power supply pairs. the four banks of gpio can be powered independe ntly, allowing these banks to be run at different voltages. v dda must always be at th e same voltage as vdde_a. table 48-4 describes the gpio banks, their main functions, supply pins and associated port pins. for full details of gpio functionality, refer to chapter 3, signal description .
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 48-7 preliminary?subject to change without notice table 48-4. gpio power bank supplies and functionality gpio bank available functions 1 1 not all functions are available simultaneously. refer to chapter 3, signal description. supply pins port pins stepper motor bank stepper motors [1:0], emios stepper motors [3:2], emios stepper motors [5:4] vddm, vssm portd[7:0] portd[15:8] porte[7:0] analog bank adc, 32 khz sxosc vdde_a, vsse_a portc[15:0] portl[3:0] dram bank dram memory control, address and data pins vdd_dr, vss ddr_odt ddr_cke ddr_clk ddr_clkb ddr_cs ddr_ras ddr_cas ddr_web ddr_a[0:15] ddr_ba[0:2] ddr_dq[0:31] ddr_dqs[0:3] ddr_dm[0:3] digital bank dcu3, dculite, dspi, quadspi, flexcan, linflex, i 2 c, emios0, emios1, pdi, viu2, adc-mux, sgm, nexus vdde_b, vss porta[15:0] portb[15:0] portf[15:0] portg[12:0] porth[0:5] portj[15:0] portk[11:0] portl[13:4] portm[13:0] portn[15:0] portp[7:0] reset
pxd20 microcontroller reference manual, rev. 1 48-8 freescale semiconductor preliminary?subject to change without notice figure 48-3. power supply configuration 48.7 power domain organization to satisfy stringent require ments for current consumption in the di fferent operational modes, this device is partitioned into different power domains. orga nization into these power domains primarily means having separate power suppl ies that are separated from each othe r by the use of power switches. these r analog bank stepper motor bank digital bank digital bank dram bank vreg 4-16 mhz fmpll0/1 fxosc vddr vrc_ctrl vddm vddm vddm vdde_a vdde_b vdd_dr vdde_b vdde_b vdde_b vddpll vss (vsspll pin) vdda vssa 3.0 v to 5.5 v 3.0 v to 3.6 v to 3-5 v or 3.3 v supply to 3.3 v supply to 3.3 v supply to 3-5 v or 3.3 v supply vdd12 vss vdd12 vss vss vssm vssm vssm vdd12 vss vdd12 vss vdd12 vss vdd12 vss vss vsse_a vss vss dram supply (1.8 v, 2.5 v, or 3.3 v) vpp prog external ballast npn
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 48-9 preliminary?subject to change without notice different separated power supplies are hence able to switch off power to certain regions of the device, to avoid even leakage current consumption in logic supplied by the co rresponding power supply. this device employs three prima ry power domains: power domains pd0 and pd1, and a ram-only power domain pd2.see chapter 2, memory map , for details of ram locations in each domain. power domain organization and connections to the internal regulator are depicted in figure 48-4 .
pxd20 microcontroller reference manual, rev. 1 48-10 freescale semiconductor preliminary?subject to change without notice figure 48-4. power domain organization vdd_lv_bkp power domain 0 (pd0) power domain 1 (pd1) mc_pcu hpvdd ulpvdd lpvdd sw1 128 khz rc mc_rgm 16 mhz rc vrc_ctrl hv por1hv por2hv nbypass hppd lppd vreg api can sampler wkpu cflash 1mb rc dig wakeup pads siul option reset e200z4d platform pa 0 mc_cgm mc_me peripherals fmpll0 adc 8 kb ram power domain 2 56 kb ram sw2 pa x pbx pcx pfx pjx bits rtc 4-16 mhz 32 khz osc osc fmpll1 vdd5 pa 1 pa 2 ph5 : : vdd12 (pd2) graphics ram dflash
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 48-11 preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 48-12 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-1 preliminary?subject to change without notice chapter 49 wakeup unit (wkpu) 49.1 overview the wkpu supports 24 1 external sources that can generate bot h interrupts and wake up events, of which one can cause non-maskable interrupt requests. figure 49-1 is a block diagram of the wakeup unit and its interfaces to other system components. the wkpu operates separately from th e external siul and its interrupt capability is independent from the siul external interrupt feature. the wakeup lines are mapped to the interrupt vectors as shown in table 49-1 . figure 49-1. wakeup unit block diagram 1. up to 23 external sources in the 416-pin package; up to 19 external sources in the 208-pin package; up to 15 external sources in the 176-pin package ips bus pads interrupt controller pbridge mode / power ctl irqs sys wakeup wakeup 25 platform 4 nmi / wakeup - configuration irq / wakeup - configuration wakeup unit iomux rtc, etc. 0-25 filter filter filter bypass filter bypass nmi enable
pxd20 microcontroller reference manual, rev. 1 49-2 freescale semiconductor preliminary?subject to change without notice 49.2 features the wakeup unit supports th ese distinctive features: ? non-maskable interrupt support with ? 1 nmi source with bypa ssable glitch filter table 49-1. wakeup vector mapping wakeup vector wakeup number function package port #1 #2 #3 176 208 416 0 wkup0 pb1 canrx_0 ? ? x x x wkup1 pb3 lin_rxd_0 ? ? x x x wkup2 pb4 sck_1 ma0 ? x x x wkup3 pb9 sck_0 emios1[20] ? x x x wkup4 pb10 canrx_1 pdi2 emios0[23] x x x wkup5 pb12 rxd_1 emios1[19] cs2_0 x x x wkup6 pc0 an[0] ? ? x x x wkup7 pc10 an[10] ? ? x x x 1 wkup8 pf0 emios1[19] evto dculite_b2 x x x wkup9 pf2 nmi ? ? x x x wkup10 pf3 emios1[21] mseo dculite_b4 x x x wkup11 pf8 sda_0 cs2_1 rxd_1 x x x wkup12 pj4 viu[0] emios0[21] emios0[23] x x x wkup13 pj6 viu[2] emios0[19] emios0[15] x x x wkup14 pk7 rxd_2 dculite_r2 tcon8 ? x x wkup15 pl0 an[19] canrx_1 dculite_tag ? x x 2 wkup16 pl2 an[17] canrx_0 emios1[22] ? x x wkup17 pl9 sck_2 pdi_pclk emios1[21] ? x x wkup18 pm3 canrx_2 rxd_3 tcon[4] ? x x wkup19 pm10 rxd_2 canrx_2 emios0[16] x ? ? wkup20 pn0 dculite_hsync ? tcon4 ? ? x wkup21 pn2 dculite_r0 rxd_2 viu[0] ? ? x wkup22 pn10 dculite_g0 rxd_3 viu[2] ? ? x wkup23 pp2 dculite_b0 canrx_2 viu[4] ? ? x 3 wkup24 ? api ? ? ? ? ? wkup25 ? rtc ? ? ???
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-3 preliminary?subject to change without notice ? independent interrupt destinatio n: non-maskable interrupt, criti cal interrupt, or machine check request ? edge detection ? external wakeup/interrupt support with ? up to 4 system interrupt vectors for 26 interrupt sources ? analog glitch filter per each wakeup line ? independent interrupt mask ? edge detection ? configurable system wakeup trigge ring from all interrupt sources ? configurable pullup ? on-chip wakeup support ? up to 26 wakeup sources ? wakeup status mapped to same register as external wakeup/interrupt status 49.3 external signal description the wkpu has 24 external signal inputs. these can be used as syst em wakeup sources in certain power down modes. they can also be used as additional ex ternal interrupt sources in normal run mode. when used as external interrupt sources they operate independently from the external interrupt sources available on the siul although they may share a single pin. these 24 external signal inputs include one signal i nput that can be used as a non-maskable interrupt source in normal run mode or a system wakeup sources in certain power down modes. note be aware that the wake-up pins are en abled in all modes. therefore, the wake-up pins should be correctly term inated to ensure minimal current consumption. any unused wake-up signa l input should be terminated by using an external pull-up or pull-dow n, or by internal pull-up enabled at wipuer. also, care must be taken on packages where the wake-up signal inputs are not bonded. for these packages, the user must ensure the internal pull-ups are enabled for those signals not bonded. 49.4 memory map and register description this section provides a detailed description of all registers accessible in the wkpu module. 49.4.1 memory map table 49-2 gives an overview on the wkpu registers implemented.
pxd20 microcontroller reference manual, rev. 1 49-4 freescale semiconductor preliminary?subject to change without notice note reserved registers will read as 0, writ es will have no effect . if supported and enabled by the soc, a transfer error wi ll be issued when trying to access completely reserved register space. 49.4.2 register description this section describes in address order all the wakeup unit registers. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. the numbering conven tion of register is msb=0, however the numering of internal field is lsb=0, e.g. eif[5] = wisr[26]. table 49-2. wkpu memory map address offset register abbreviation location 0x0000 nmi status flag register nsr on page 49-5 0x0004 - 0x0007 reserved 0x0008 nmi configuration register ncr on page 49-5 0x000c - 0x0013 reserved 0x0014 wakeup/interrupt status flag register wisr on page 49-7 0x0018 interrupt request enable register irer on page 49-7 0x001c wakeup request enable register wrer on page 49-8 0x0020 - 0x0027 reserved 0x0028 wakeup/interrupt rising-edge event enable register wireer on page 49-8 0x002c wakeup/interrupt falling-edge event enable register wifeer on page 49-9 0x0030 wakeup/interrupt filt er enable register wifer on page 49-9 0x0034 wakeup/interrupt pullup enable register wipuer on page 49-10 0x0038 - 0x03fff reserved always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write-o nly bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 49-2. key to register fields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-5 preliminary?subject to change without notice 49.4.2.1 nmi status flag register (nsr) this register holds the non-mask able interrupt status flags. 49.4.2.2 nmi configurat ion register (ncr) this register holds the configuration bits for the non-maskable interrupt settings. address:0x0000 access: user read/write (write 1 to clear) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nif novf 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w w1c w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-3. nmi status flag register (nsr) table 49-3. nsr field descriptions field description 0 nif nmi status flag this flag can be cleared only by writing a 1. writing a 0 has no effect. if enabled (nree or nfee set), nif causes an interrupt request. 1 an event as defined by nree and nfee has occurred 0 no event has occurred on the pad 1 novf nmi overrun status flag this flag can be cleared only by writing a 1. writin g a 0 has no effect. it will be a copy of the current nif value whenever an nmi event occurs, thereby indicating to the software that an nmi occurred while the last one was not yet serviced. if enabled (nree or nfee set), novf causes an interrupt request. 1 an overrun has occurred on nmi input 0 no overrun has occurred on nmi input
pxd20 microcontroller reference manual, rev. 1 49-6 freescale semiconductor preliminary?subject to change without notice note writing a ?0? to both nree and nfee disables the nmi functionality completely (i.e. no system wakeup or interrupt will be generated on any pad activity)! address: 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nloc k ndss nwre 0 nree nfee nfe 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-4. nmi configuration re gister (ncr) table 49-4. ncr field descriptions field description 0 nlock nmi configuration lock register writing a 1 to this bit locks the c onfiguration for the nmi until it is unlocked by a system reset. writing a 0 has no effect. 1-2 ndss nmi destination source select 00 non-maskable interrupt 01 critical interrupt 10 machine check request 11 reserved - no nmi, critical interrup t, or machine check request generated 3 nwre[x] nmi wakeup request enable 1 a set nif bit or set novf bit causes a system wakeup request 0 system wakeup requests from the corresponding nif bit are disabled 5 nree nmi rising-edge events enable 1 rising-edge event is enabled 0 rising-edge event is disabled 6 nfee nmi falling-edge events enable 1 falling-edge event is enabled 0 falling-edge event is disabled 7 nfe nmi filter enable enable analog glitch filter on the nmi pad input. 1 filter is enabled 0 filter is disabled
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-7 preliminary?subject to change without notice 49.4.2.3 wakeup/interrupt stat us flag register (wisr) this register holds the wakeup/interrupt flags. note not all bits are available in all packages. note status bits associated with on-chip wa keup sources are located to the left of the external wakeup/interrupt status bi ts and are read onl y. the wakeup for these sources must be configured and cleared at the on-ch ip wakeup source. also, the configuration registers for the external interrupts/wakeups do not have corresponding bits. 49.4.2.4 interrupt request enable register (irer) this register is used to enable the interrupt messa ging from the wakeup/interrupt pads to the interrupt controller. note not all bits are available in all packages. address: 0x0014 access: user read/write (write 1 to clear) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 eif25 eif24 eif23 eif22 eif21 eif20 eif19 eif18 eif17 eif16 eif15 eif14 eif13 eif12 eif11 eif10 eif9 eif8 eif7 eif6 eif5 eif4 eif3 eif2 eif1 eif0 w w1c reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-5. wakeup/interrupt st atus flag register (wisr) table 49-5. wisr field descriptions field description eif x external wakeup/interrupt status flag x . this flag can be cleared only by writing a 1. writin g a 0 has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 1 an event as defined by wireer and wifeer has occurred 0 no event has occurred on the pad address: 0x0018 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 eire25 eire24 eire23 eire22 eire21 eire20 eire19 eire18 eire17 eire16 eire15 eire14 eire13 eire12 eire11 eire10 eire9 eire8 eire7 eire6 eire5 eire4 eire3 eire2 eire1 eire0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-6. interrupt request enable register (irer)
pxd20 microcontroller reference manual, rev. 1 49-8 freescale semiconductor preliminary?subject to change without notice 49.4.2.5 wakeup request en able register (wrer) this register is used to enable the system wakeup messaging from the wakeup/in terrupt pads to the mode entry and power control modules. note not all bits are available in all packages. 49.4.2.6 wakeup/interrupt rising-edge event enable register (wireer) this register is used to enable rising-edge trig gered events on the corresponding wakeup/interrupt pads. note not all bits are available in all packages. the rtc_api can only be configured on the rising edge. . table 49-6. irer field descriptions field description eire[x] external interrupt request enable x. 1 a set eif[x] bit causes an interrupt request 0 interrupt requests from the co rresponding eif[x] bit are disabled address: 0x001c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 wre25 wre24 wre23 wre22 wre21 wre20 wre19 wre18 wre17 wre16 wre15 wre14 wre13 wre12 wre11 wre10 wre9 wre8 wre7 wre6 wre5 wre4 wre3 wre2 wre1 wre0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-7. wakeup request enable register (wrer) table 49-7. wrer field descriptions field description wre[x] external wakeup request enable x. 1 a set eif[x] bit causes a system wakeup request 0 system wakeup requests from the co rresponding eif[x] bit are disabled address: 0x0028 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 iree25 iree24 iree23 iree22 iree21 iree20 iree19 iree18 iree17 iree16 iree15 iree14 iree13 iree12 iree11 iree10 iree9 iree8 iree7 iree6 iree5 iree4 iree3 iree2 iree1 iree0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-8. wakeup/interrupt rising-edge event enable register (wireer)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-9 preliminary?subject to change without notice 49.4.2.7 wakeup/interrupt falling-edge event enable register (wifeer) this register is used to enable falling-edge tri ggered events on the corresponding wakeup/interrupt pads. note not all bits are available in all packages. 49.4.2.8 wakeup/interrupt filter enable register (wifer) this register is used to enable an analog filter on the corresponding interr upt pads to filter out glitches on the inputs. note not all bits are available in all packages. there is no analog filter for the rtc_api. table 49-8. wireer field descriptions field description iree[x] external interrupt rising-edge events enable x. 1 rising-edge event is enabled 0 rising-edge event is disabled address: 0x002c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 ifee25 ifee24 ifee23 ifee22 ifee21 ifee20 ifee19 ifee18 ifee17 ifee16 ifee15 ifee14 ifee13 ifee12 ifee11 ifee10 ifee9 ifee8 ifee7 ifee6 ifee5 ifee4 ifee3 ifee2 ifee1 ifee0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-9. wakeup/interrupt falling-edge event enable register (wifeer) table 49-9. wifeer field descriptions field description ifeex external interrupt falling-edge events enable x. 1 falling-edge event is enabled 0 falling-edge event is disabled address: 0x0030 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 ife25 ife24 ife23 ife22 ife21 ife20 ife19 ife18 ife17 ife16 ife15 ife14 ife13 ife12 ife11 ife10 ife9 ife8 ife7 ife6 ife5 ife4 ife3 ife2 ife1 ife0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-10. wakeup/interrupt filter enable register (wifer)
pxd20 microcontroller reference manual, rev. 1 49-10 freescale semiconductor preliminary?subject to change without notice 49.4.2.9 wakeup/interrupt pullup enable register (wipuer) this register is used to enable a pullup on the corresponding interrupt pads to pull an unconnected wakeup/interrupt input to a value of ?1?. note not all bits are available in all packages. 49.5 functional description 49.5.1 wkpu behavior the wkpu provides external internal interrupts and lo w-power wakeups for the chi p. it is possible to use the connected pins to raise an interrupt, a wakeup, or both. table 49-12 describes the behavior of the chip for various operating modes and wakeup configurations. table 49-10. wifer fi eld descriptions field description ife[x] external interrupt filter enable x. enable analog glitch filter on the external interrupt pad input. 1 filter is enabled 0 filter is disabled address: 0x0034 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 ipue25 ipue24 ipue23 ipue22 ipue21 ipue20 ipue19 ipue18 ipue17 ipue16 ipue15 ipue14 ipue13 ipue12 ipue11 ipue10 ipue9 ipue8 ipue7 ipue6 ipue5 ipue4 ipue3 ipue2 ipue1 ipue0 w reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 figure 49-11. wakeup/interrupt pullup enable register (wipuer) table 49-11. wipuer field descriptions field description ipue[x] external interrupt pullup enable x. 1 pullup is enabled 0 pullup is disabled table 49-12. wkpu behavior operating mode wakeup interrupt standby restart 1 program flow after low power mode exit halt n/a enabled n/a jump to isr
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-11 preliminary?subject to change without notice 49.5.2 non-maskable interrupts the wakeup unit supports one non-maskab le interrupt which is allocated to pin 45 of the 176-pin package, to pin 53 of the 208-pin package, and to pin aa7 of the bga package. the wakeup unit supports the genera tion of three types of interrupts from the nmi. the wakeup unit supports the capturing of a second ev ent per nmi input before the interr upt is cleared, thus reducing the chance of losing an nmi event. each nmi passes through a bypassable analog glitch filter. note glitch filter control a nd pad configuration should be done while the nmi is disabled in order to avoid erroneou s triggering by glitches caused by the configuration process itself. stop - system clock enabled enabled disabled n/a continue from previous instruction enabled enabled n/a continue from previous instruction then jump to isr stop - system clock disabled enabled disabled n/a continue from previous instruction enabled enabled n/a continue from previous instruction then jump to isr standby enabled disabled flash memory jump to reset vector in flash memory ram jump to start of ram (0x4000_0000) enabled enabled flash memory jump to reset vector in flash memory, then jump to isr 2 ram jump to start of ram (0x4000_0000) then jump to isr 2 1 configured using standby reset sequence r egister (rgm_stdby) in the mc_rgm module 2 isr is pending until interrupts have been configured at intc. table 49-12. wkpu behavior (continued) operating mode wakeup interrupt standby restart 1 program flow after low power mode exit
pxd20 microcontroller reference manual, rev. 1 49-12 freescale semiconductor preliminary?subject to change without notice figure 49-12. nmi pad diagram 49.5.2.1 nmi management the nmi can be enabled or disabled using the single ncr register laid out to cont ain all configuration bits for an nmi in a single byte (see figure 49-4 ). the pad defined as an nmi can be configured by the user to recognize interrupts with an active rising edge, an active falling edge or both edges being active. a setting of having both edge events disabled results in no interrupt being detected and should not be configured. the active nmi edge is controlled by the user th rough the configuration of the nree and nfee bits. note after reset, nree and nfee are set to ?0?, therefore the nmi functionality is disabled after reset and must be enabled explicitly by software. once the pad?s nmi functionality has been enabled, the pad cannot be reconfigured in the iomux to override or disable the nmi. the nmi destination interrupt is c ontrolled by the user through the c onfiguration of the ndss bits. see table 49-4 for details. glitch filter edge detect flag overrun destination nmi critical irq machine check wakeup enable cpu mode/ pwr ctl ndss nwre nree nfee nfe nmi configuration register (ncr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 49-13 preliminary?subject to change without notice an nmi supports a status flag and an overrun flag which are lo cated in the nsr register (see table 49-3 ). this register is a clear-by-write-1 register type, pr eventing inadvertent overwriti ng of other flags in the same register. the stat us flag is set whenever an nmi event is detected. the overrun flag is set whenever an nmi event is detected and the status fl ag is set (i.e. has not yet been cleared). note the overrun flag is cleared by writing a ?1? to the appropriate overrun bit in the nsr register. if the status bit is cl eared and the overrun b it is still set, the pending interrupt will not be cleared. 49.5.3 external wake ups and interrupts the wakeup unit supports four interr upt vectors to the intc of the chip and a single wakeup source for the chip. each interrupt vector can support up to the number of external interrupt sources from the device pads with the total across all vectors being equal to th e number of external interrupt sources. each external interrupt source is assigned to one interrupt vector. th e interrupt vector assignmen t is sequential so that one interrupt vector is for extern al interrupt sources 0 through n-1, th e next is for n through n+m-1, and so forth. see figure 49-13 for an overview of the external interr upt and wakeup implementation including the control and status registers. figure 49-13. external interrupt pad diagram all of the external interrupt pads within a single group have equal priori ty. it is the responsibility of the user software to search through th e group of sources in the most a ppropriate way for their application. interrupt controller int vectors pads wireer[25:0] interrupt edge enable wifeer[25:0] falling rising edge detection analog glitch filter wifer[25:0] glitch filter enable interrupt enable or or irq_23_16 irq_15_08 irq_07_00 flag[23:16] flag[15:8] wisr[25:0] flag[7:0] wrer[25:0] wakeup enable mode/ pwr ctl irer[25:0] or or flag[25:24] irq_25_24
pxd20 microcontroller reference manual, rev. 1 49-14 freescale semiconductor preliminary?subject to change without notice note glitch filter control and pad configuration should be done while the external interrupt line is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. 49.5.3.1 external interrupt management each external interrupt can be enabled or disabl ed independently. this can be performed using the interrupt request enable register (i rer). a pad defined as an external interrupt can be configured by the user to recognize external interrupts with an ac tive rising edge, an active fal ling edge or both edges being active. note writing a ?0? to both iree[x] and ifee[ x] disables the external interrupt functionality for that pad completely (i .e. no system wakeup or interrupt will be generated on any activity on that pad)! the active irq edge is controlled by the users th rough the configuration of the registers wireer and wifeer. each external interrupt supports an i ndividual flag which is held in the fl ag register (wisr). this register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the same register. 49.5.3.2 on-chip wakeup management each wakeup can be enabled or di sabled independently using the wakeup request enable register (wrer). the active wakeup edge is controlled by the users through the configuration of the wireer and wifeer registers. each internal and external wakeup sets an individual flag which is held in the flag register (wisr). this register is a clear-by-writ e-1 register type, preventing inadvertent overwriting of other flags in the same register.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 50-1 preliminary?subject to change without notice chapter 50 device performance optimization 50.1 introduction the pxd20 contains several features that can influe nce the overall level of performance provided by the device. some of these features may be in itialized upon negation of reset either by a software program called the boot assist module (bam), by a ha rdware state machine or by appropr iate default register settings. although the device exits the reset state into a functi onal state it does not necessarily have the default optimum performance settings for any given application. this chapter provides guidance for users to fully optim ize their application to achieve the highest possible performance from the pxd20. it provi des a description of the areas that should be focused on when optimizing an application for perf ormance by describing the features and recommending settings to be applied. it focuses on hardware confi gurations although certain aspects of the applicat ion software such as compiler settings and optimizations wi ll be discussed. 50.2 features the pxd20 has the following hardware features that can be confi gured to impact the overall performance of the device: ? branch prediction ? branch target buffer ? branch prediction control ? frequency-modulated pll ? platform flash controller ? flash access wait state a nd address pipelining control ? flash instruction prefetching ? flash data prefetching ?crossbar switch ? system cache ? instruction cache ? memory management unit ? dram controller priority manager further application level features ca n impact the appli cation performance: ? hardware single precision floating point ? signal processing extension (spe-apu) ? variable length encoding (vle) ? compiler optimizations
pxd20 microcontroller reference manual, rev. 1 50-2 freescale semiconductor preliminary?subject to change without notice further factors that impact the overall application performance are the use of the intelligent peripherals: ? use of dma rather than cpu to transfer data efficiently ? use of dma service requests rather than cpu interrupts to avoid software polling ? off-loading tasks from the cpu to the edma ? careful allocation of cache usage for code ranges. different items in this list will have different performance impacts in a real system. features like the crossbar switch, system cache, the fmpll and the flash access times tend to provide the most significant performance impacts in term s of hardware settings. the subsequent sections in th is chapter describe how to c onfigure and use these features. 50.3 configuring hardware features 50.3.1 branch target buffer (btb) 50.3.1.1 description to resolve branch instructions and improve the accuracy of branch predic tions the e200z4d core implements a dynamic branch pred iction mechanism using a branch target buffer (btb), a fully associative address cache of branch target addresses. its pur pose is to accelerate the execution of software loops with some potential change of flow within the loop body. in addition, the btb on the e200z4d has a subroutine call stack that speeds up indirect branches. 50.3.1.2 recommended configuration by default, the btb is disabled fo llowing reset onthe e200z4d. it is controlled by the branch unit control and status register (bucsr). the btb?s contents should be fl ushed and invalidated by writing bucsr[bbfi] = 1, and it may be enabled by subsequently writing bucsr[bpen] = 1. additional control is available by configuring bucsr[bpred] and bucsr[balloc] to control whether forward or backward branches (or both) are candidates for entry into the btb, and thus for branch prediction. by default th e bucsr[bpred] and bucs r[balloc] fields are set to 0b00, which enables forward and backward branch prediction. it is reco mmended to not disable branch prediction although for extremely fine tuning of a gi ven application the optimum se tting of bucsr[bpred] and bucsr[balloc] should be assessed. 0 bbfi 0 balloc 0 bpred bpen 012345678910111213141516171819202122232425262728293031 spr - 1013; read/write; reset - 0x0 figure 50-1. branch unit control and status register (bucsr)
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 50-3 preliminary?subject to change without notice further details of the bucsr can be f ound in the e200z4 core reference manual. 50.3.2 frequency-modulated pll0 50.3.2.1 description the frequency-modulated phase-locke d loop (fmpll0) allows the user to generate high speed system clocks from a crystal oscillator or external clock generator. furthe r, the fmpll0 s upports programmable frequency modulation of the system clock. this module is typically configured early in the initialization code to ensure satisfactory pe rformance levels are achieved. 50.3.2.2 recommended configuration after reset the pxd20 device uses the fast internal rc oscillator (firc) as its system clock (approximately 16 mhz). typically, th e source of the system clock is changed to the fmpll0 to provide acceptable performance. section 8.5, frequency-modulated phase-locked loop (fmpll) , provides details on how the fmpll0 should be initiali zed in an application. the maximu m frequency of operation for this device is specified in the device data sheet. table 50-1. bucsr field descriptions field description bbfi branch target buffer flash invalidate when set, bbfi flash clears the valid bit of all btb entries; clearing occurs regardless of the value of the enable bit (bpen). note : bbfi is always read as 0. balloc branch target buffer allocation control 00: branch target buffer allocation for all branches is enabled. 01: branch target buffer allocation is disabled for backward branches. 10: branch target buffer allocation is disabled for forward branches. 11: branch target buffer allocation is disabled for both branch directions. this field controls btb allocation for branch accele ration when bpen = 1. note that btb hits are not affected by the settings of this fi eld. note that for branches with aa = ?1?, the msb of the displacement field is still used to indicate forward/backward, even though the branch is absolute. bpred branch prediction control (static) 00: branch predicted taken on btb miss for all branches. 01: branch predicted taken on btb miss only for forward branches. 10: branch predicted taken on btb miss only for backward branches. 11: branch predicted not taken on bt b miss for both branch directions. this field controls operation of static prediction mechanism on a btb miss. unless disabled, fetching of the predicted target location will be performed for branch acceleration. bpred operates independently of bpen, and with a bpen setting of 0, will be used to perform static prediction of all unresolved branches. note that btb hits are not affected by the settings of this field. note that for certain applications, setting bpred to a non-default value may result in improved performance. bpen branch target buffer (btb) enable 0: btb prediction disabled. no hits are generat ed from the btb and no new entries are allocated. entries are not automatically in validated when bpen is cleared; bbfi controls entry invalidation. 1: btb prediction enabled (enables btb to predict branches).
pxd20 microcontroller reference manual, rev. 1 50-4 freescale semiconductor preliminary?subject to change without notice system performance cannot be linearly extrapolated with system frequency, as is often th e expectation. it is due to the insertion of additional flash wait states as sy stem frequency increases that system performance does not scale linearly. take care to ensure that the corr ect internal and/or extern al flash configuration is chosen for the selected system frequency. the speci fic flash access times to be applied are detailed in section 21.4.5, pflash2p . 50.3.3 flash bus interface unit 50.3.3.1 description the platform flash controller (pfc) interfaces the sy stem bus to the flash memory array controller. the pfc contains prefetch buffers and a prefetch cont roller which, if enabled, speculatively prefetches sequential lines of data from the fl ash array into the buffer. prefetch buffer hits allow zero-wait state responses. the platform flash configuration regi sters (pfcrx) control access to the internal flash array. its settings define the number of cycles requ ired to access the array, access ti mes, and how the prefetch buffering scheme operates. following negation of reset the instruction and data prefetching is disabled, and the number of cycles required to access the internal flash array is set to its maximum value of fifteen additional wait states. 50.3.3.2 recommended configuration as the operating frequency of the device is set by configuring the fmpll0 (see section 8.5, frequency-modulated phase-locked loop (fmpll) ), the number of cycles required to access the internal array should be configured accordingl y. note that the flash pfcrx regi sters cannot be altered by code executing from the flash arra y. code for configuring the flash shoul d be executed from a separate memory array i.e copied to and executed from system ram. section 21.4.5, pflash2p , documents the register fields used to configure flash wait state settings. the ?platform flash controller el ectrical characteristics? section of the device data sheet contains the specific values for the flash wait state settings for a given operating frequency. this also provides recommendations for the prefetch buffer settings. note that the pf crx settings may vary between revisions of the pxd20. 50.3.4 crossbar switch 50.3.4.1 description the multi-port crossbar sw itch (xbar) supports simultaneous c onnections between master ports and slave ports. the xbar allows for conc urrent transactions to occur from any master port to any slave port. if a slave port is simultaneously requested by more th an one master port, arbitrat ion logic selects the higher priority master and grants it owne rship of the slave port. all other ma sters requesting that slave port are stalled until the higher priority master completes its transactions. by defaul t, requesting masters are granted access based on a fixed pr iority. a round-robin priority mode also is available.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 50-5 preliminary?subject to change without notice the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate concurrently with multiple slaves. in order to maximi ze data throughput it is essential to keep arbitration delays to a minimu m. the configuration of the crossb ar can have implications for the performance of a system and particul ar care should be taken when assi gning master priorities in a fixed priority application. further, by correctly parking saves on releva nt masters the initial access times to the slaves can be minimized by negating any initial arbitration penalties. 50.3.4.2 recommended configuration the specific settings for a given situation are app lication dependent and thus should be assessed by the user. the primary flash port is fixed to the e200z4d instruction bus master to maximise execution speed for that core however the assignment of the sec ond flash port will depend on which other masters are accessing the flash the most. best pe rformance may be obtaine d by prioritising the ed ma or the data bus of the e200z4d. similarly as signment of the system and graphics ram ports depend on how the cores, dcu and dculite, and edma use the rams. more details of the xbar regist er configuration can be found in section 9.3, xbar registers . 50.3.5 cache 50.3.5.1 description the pxd20 e200z4d provides an 8 kb in struction, 2-way or 4-way set-associativ e, harvard cache design with a 32-byte line size. the cache is disabled by default after reset. the cache improves system performance by providing low-latency instructions to the instruction pipelines, which decouples processor performance fr om system memory perfor mance. there are several stages to enabling the cache. not only does the cache it self have to be invalidated then enabled, but memory regions upon which it can operate must be configured in the mmu to permit cache access. 50.3.5.2 recommended configuration the exact usage of cache is appli cation dependent but some general guidelines for using cache to improve performance in a typical appl ication are listed below: ? enable instruction cache for all internal and exte rnal memories that code is being executed from. ? consider locking critical pe rformance routines in cache. the process of enabling the instruction cache i nvolves first invalidating the cache (by setting l1csr1[icinv]) then when invalidation is comple ted (l1csr1[icinv, icabt] = 0) enabling the cache (by setting l1csr1[ice]). the l1csr1 special purpose re gister is detailed below. for further details of cache conf iguration registers refer to the e200z4 core reference manual.
pxd20 microcontroller reference manual, rev. 1 50-6 freescale semiconductor preliminary?subject to change without notice note that configuration of the cache has to be performed in conjun ction with configura tion of the memory management unit. refer to section section 50.3.6, memory management unit (mmu) . 0 icece icei 0 icedt 0 icul iclo iclfc icloa icea 0 icabt icinv ice 012345678910111213141516171819202122232425262728293031 spr - 1011; read/write; reset - 0x0 figure 50-2. l1 cache control and status register 1 (l1csr1) table 50-2. l1csr1 field descriptions field description icece instruction cache error checking enable icei instruction cache error injection enable icedt instruction cac he error detection type icul instruction cache unable to lock iclo instruction cache lock overflow iclfc instruction cache lock bits flash clear icloa instruction cache lock overflow allocate icea instruction cache error action icabt instruction cache operation aborted indicates a cache invalidate or a cache lock bits flash clear operation was aborted prior to completion. this bit is set by hardware on an aborted condition, and will remain set until cleared by software writing 0 to this bit location. icinv instruction cache invalidate 0: no cache invalidate 1: cache invalidation operation when written to a ?1?, a cache invalidation operation is initiated by hardware. once complete, this bit is reset to ?0?. writing a ?1? while an invalidation oper ation is in progress will result in an undefined operation. writing a ?0? to this bit while an invalidation operation is in progress will be ignored. cache invalidation operations require approximately 36 cycles to complete. invalidation occurs regardless of the enable (ice) value. during cache invalidations, the parity check bits are written with a value dependent on the icedt selection. icedt should be written with the desired value for subsequent cache operation when icinv is set to ?1? for proper operation of the cache. ice instruction cache enable 0: cache is disabled 1: cache is enabled when disabled, cache lookups are not performed for instruction accesses. other l1csr0 cache control operations are still available.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 50-7 preliminary?subject to change without notice 50.3.6 memory management unit (mmu) 50.3.6.1 description the memory management unit is a 32-bit power ar chitecture compliant impl ementation which provides functionality that includes addre ss translation and appli cation of access attributes to memory ranges defined in translation lookaside buffer entr ies. although the mmu does not directly impact performance, it is within the mmu th at memory regions are configured to permit the use of system cache to improve performance and variable length encoding (vle) to enhance code density. thus it is essential that the mmu is correctly configured to ensu re optimal application performance is achieved. 50.3.6.1.1 recommende d configuration the core uses mmu assist regist ers (masx) which are special purpos e registers to fa cilitate reading, writing and searching the translati on lookaside buffer (tlb) entries. these mas registers are software managed by tlbre , tlbwe , tlbsx , tlbsync , and tlbivax instructions. refer to the core reference manual for full details of the mmu and its configurations. there are several mmu assist register registers (mas0?3) that require configuring. details of these are provided in the e200z4d reference manual. specifically, the mas2 register contains the fields to control whether a specified memory region described by the valid tl b entry is cache inhi bited or whether vle encoding is valid. refer to the e200z4d core reference manual for fu rther details of mmu c onfiguration registers. epn 0 vle wimge 012345678910111213141516171819202122232425262728293031 spr - 626; read/write figure 50-3. mmu assist register 2 (mas2) table 50-3. mas2 field descriptions field description epn effective page number [0:21] vle vle 0: this page is a standard booke page 1: this page is a vle page w write-through required i cache inhibited 0: this page is considered cacheable 1: this page is considered cache-inhibited m memory coherence required g memory coherence required e endianness
pxd20 microcontroller reference manual, rev. 1 50-8 freescale semiconductor preliminary?subject to change without notice 50.3.7 dramc priority manager 50.3.7.1 description the dramc priority manage r provides a way of automatically ad justing the priorities of masters requesting access to the dram such that access is shared according to the needs of the application. the priority of each reque sting master is dynamically adjusted so that its priority increases if it is not being serviced and decreases once it has been serviced. the adjustment of the priority is controlled by look up tables (luts) for each of the masters. in this way it is possible for a ma ster to very quickly gain a higher priority or delay until absolutely n ecessary before a change is made. 50.3.7.1.1 recommende d configuration assign rapidly escalating luts to masters with lim ited internal buffers, for example the gfx2d and the core. in these cases the masters will stall if they do have rapid access to the dr am. masters with internal buffers will tend to call on the dram for a burst a ccess more periodically and can be delayed for a time since their internal buffers will allo w them to continue processing theref ore their priority can be escalated more slowly. the dcu is a special case since it has an override option which allows fastest access when data is requested. 50.4 application software 50.4.1 compiler optimizations the most significant opportunity for influencing the perf ormance of a given applic ation is by compiler and linker optimizations. optimizing is a trade off betw een code size and performance. typically higher performance of the application comes at the expense of larger code size. compilers use a host of features, such as loop unrolling, function inlini ng and application profile feedback to make the desired trade-offs between enhanced performan ce and minimized code size. the data in figure 50-4 shows the effects of compil er optimization on a simple application. in this case, the dhrystone benchmark was run under three conditions: ? optimized for small code size ? optimized for high performance ? a trade-off between co de size and performance although this is an extreme example, it highlights how significant the role of the compiler and linker is in determining the overall perf ormance of an application.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 50-9 preliminary?subject to change without notice figure 50-4. influence of compiler settings on application performance and code size note data measured using dhrystone vers ion 2.1 run on a power architecture based powertrain device using a standard commercial compiler. the compiler optimizations do not nece ssarily have to be applied to the entire application. analysis of an application can identify time crit ical functions that may subseque ntly be targeted for performance optimization, without incurring the impact of optimizing the entire application. there are several other asp ects of the compiler and li nker that should be considered. in particular, the use of small data areas (sdas, sometim es referred to as special data areas) can make a significant performance improvement. refer to compiler documentation for usage guidelines on small data areas. 50.4.2 signal processing extension to further optimize time critical functions, the si gnal processing extension a uxiliary processing unit (spe-apu) may be used. the spe-apu provides a se t of single instruction multiple data (simd) instructions. these simd instructi ons typically involve performing th e same operation on multiple data elements stored within a single 64-bit register. through the implem entation of simd instructions, including vector multiply and accumulate (mac) instructions, the spe apu provides digital signal processing (dsp) functionality. this can be used to accelerate signal processing routines, such as finite impulse response (fir), infi nite impulse response (iir ) and discrete fourier tr ansforms (dft). a more general benefit of the spe instruction set is the abilit y to load/store 64-bits of data in single instruction. thus highly load/store intensive functions make good candidates for spe optimization. 0 ucle spe 0 we ce 0 ee pr fp me 0 de 0 is ds 0 ri 0 012345678910111213141516171819202122232425262728293031 read / write; reset - 0x0 figure 50-5. machine state register (msr) performance vs. code size normalized execution time normalized code size size optimized trade-off speed optimized 1.2 1.0 0.8 0.6 0.4 0.2 0 1.2 1.0 0.8 0.4 0.2 00.6
pxd20 microcontroller reference manual, rev. 1 50-10 freescale semiconductor preliminary?subject to change without notice 50.4.3 hardware single precision floating point the spe-apu also supports 32-bit ieee ? -754 single-precision floating-point formats, and supports vector and scalar single-precision fl oating-point operations. most compil er vendors include libraries that can emulate floating point functionality. however, by specifying th e correct compiler options, the single precision floating point inst ructions may be used. to enable use of hardware floating point the msr[spe] fi eld must be set. refer to section 50.4.2, signal processing extension for register details. 50.4.4 variable length encoding in addition to the base power architecture instruc tion set support, the e200z4d core also implements the vle (variable-length encoding) apu, providing improved code density. the vle-apu can be viewed as a supplement to the existing power architecture instru ction set that can be conditionally applied to a portion of, or an entire application for which improved code density is desired. using it is straightforward: 1. select the appropriate compiler targ et and option to generate vle code. 2. configure the memory management unit (mmu) to specify vle attributes for the relevant mmu pages. refer to the re gister description in section 50.3.6, memory management unit (mmu) . vle-enabled cores run both power ar chitecture and vle instruction enc odings on a page by page basis, with pages defined by the mmu. the reduction is code size is typically between 25% and 30%. table 50-4. msr field descriptions field description ucle user cache lock enable spe spe available 0: execution of spe apu vector instructions is di sabled; spe unavailable exc eption taken instead, and spe bit is set in esr. 1: execution of spe apu vect or instructions is enabled. we wait state (power management) enable ce critical interrupt enable ee external interrupt enable pr problem state fp floating-point available me machine check enable de debug interrupt enable is instruction address space ds data address space ri recoverable interrupt
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor 50-11 preliminary?subject to change without notice 50.5 peripherals and general application guidelines optimizing the device conf iguration and compiler setup is only one part of optimizing an entire application. correct use of the periphe rals can also dramatically improve overall system performance. in particular, use of the interrupt controller,and the e nhanced direct memory access (edma), can off-load significant work from the e200z4d. for example, edma may be used to shift data to avoid unnecessary cpu loading. most peripheral modules can generate edma requests to trigger data transfers. an exampl e of a typical application is to use the edma to move can messages from one flexcan module to another. section 50.6, performance optimization checklist , provides several system level examples of how to optimize an application. 50.6 performance optimization checklist table 50-5. performance optimization checklist?part 1. hardware configuration description register(s) details branch target buffer flush with bucsr[bbfi] enable with bucsr[bpen] flush and enable to improve accuracy of branch predictions. branch prediction bucsr[ bpred]/hid0[bpred] bucsr[balloc] consider fine tuning of btb operation for specific applications. system frequency fmpll_cr fmpll_mr select desired frequency and frequency modulation taking into account the performance impact of additional wait states. flash wait states fpcr0[apc, wwsc, rwsc] refer to flash chapter section 21.3.2.8, platform flash configuration registers (pfcrp0 and pfcrp1) , for fpcr settings for fmpll frequency ranges. flash prefetching fpcr[dpfen, ipfe n, pflim, bfen] enable prefetchi ng for instructions. prefetching for data should be assessed for the specific application. flash prefetch algorithm fpcr[bcfg] allocate buffers to data and/or instructions. fine tune for specific applications. crossbar switch sgpcrn and mprn configure ports according to most likely master to access a slave. in single core designs assign the e200z4d data port to the second flash port. in multi-core designs prioritise the flash and ram ports to the heaviest users cache invalidate icache with l1csr1[icinv] enable icache with l1csr1[ice] invalidate and the enable the cache for instructions. memory management unit tlb_mas2[vle, i] configure relevant pages for cache and vle by setting mmu tlb attributes. dramc priority manager mlutn and associated configuration registers configure the priority manager such that core cache misses or gfx2d requests escalate quickly
pxd20 microcontroller reference manual, rev. 1 50-12 freescale semiconductor preliminary?subject to change without notice table 50-6. performance optimization checklist?part 2. software configuration description registers details compiler optimization ? use the features of the compiler to select the optimum trade off between code size and performance improvements. hardware single precision floating point enable with msr[spe] set compiler switches to specify using hardware single precision floating point as opposed to software emulation. signal processing extensions enable with msr[spe] take advantage of the spe-apu to encode time critical functions using spe assembly code. variable length encoding enabled with tlb_mas2[vle ] set compiler switches and configure the mmu to take advantage of the vle-apu. table 50-7. performance optimization checklist?part 3. peripherals and general application guidelines peripherals and general application guidelines use edma rather than the core to move data where possibl e. most peripherals can generate edma requests to shift data. ? use dma to fill and empty communication devices buffers. ? use dma to copy graphics from flash into ram for further processing or reuse ? use dma to initialize dcu and dculite clut shift loading from the cpu to the e200z0h and ctu whenever possible. ? the e200z0h can handle interrupts and scheduling for comunications peripherals. ? the ctu can trigger the adc direct ly with no need for cpu interruption. avoid software polling and allow peripherals to trigger interrupts or request edma servicing. ? use hardware instead of software vectored interrupts to reduce latency. ? trigger edma requests rather than interrupting the cpu to move data/results.
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-1 preliminary?subject to change without notice appendix a registers under protection for this device the regist er protection module is operable on the registers of table a-1 . note registers protected in the dcu3 a nd dculite are described in their respective chapters. table a-1. registers under protection module register register size module base register offset protected bitfields code flash memory, 4 registers to protect code flash mcr 32 c3f88000 000 bits[0:31] code flash biu0 32 c3f88000 01c bits[0:31] code flash biu1 32 c3f88000 020 bits[0:31] code flash biu2 32 c3f88000 024 bits[0:31] pram2p, 1 register to protect pram2p cr viu2, 1 register to protect viu2 status_config gxg, 16 registers to protect gxg gxgcnfg0 gxg gxgcnfg1 gxg gxgcnfg2 gxg gxgcnfg3 gxg gxgbase0 gxg gxgbase1 gxg gxgbase2 gxg gxgbase3 gxg gxgfrst0 gxg gxgfrst1 gxg gxgfrst2 gxg gxgfrst3 gxg gxglast0 gxg gxglast1
pxd20 microcontroller reference manual, rev. 1 a-2 freescale semiconductor preliminary?subject to change without notice gxg gxglast2 gxg gxglast3 dramc dramc all registers tcon, 53 registers to protect tcon tcon_ctrl tcon tcon_bmc tcon tcon_comp0 tcon tcon_comp1 tcon tcon_comp2 tcon tcon_comp3 tcon tcon_comp0_msk0 tcon tcon_comp0_msk1 tcon tcon_comp0_msk2 tcon tcon_comp0_msk3 tcon tcon_pulse0 tcon tcon_pulse1 tcon tcon_pulse2 tcon tcon_pulse3 tcon tcon_pulse4 tcon tcon_pulse5 tcon tcon_pulse0_msk tcon tcon_pulse1_msk tcon tcon_pulse2_msk tcon tcon_pulse3_msk tcon tcon_pulse4_msk tcon tcon_pulse5_msk tcon tcon_smx0 tcon tcon_smx1 tcon tcon_smx2 tcon tcon_smx3 tcon tcon_smx4 table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-3 preliminary?subject to change without notice tcon tcon_smx5 tcon tcon_smx6 tcon tcon_smx7 tcon tcon_smx8 tcon tcon_smx9 tcon tcon_smx10 tcon tcon_smx11 tcon tcon_smx12 tcon tcon_smx13 tcon tcon_omux_low tcon tcon_omux_high tcon tcon_lut0 tcon tcon_lut1 tcon tcon_lut2 tcon tcon_lut3 tcon tcon_lut4 tcon tcon_lut5 tcon tcon_lut6 tcon tcon_lut7 tcon tcon_lut8 tcon tcon_lut9 tcon tcon_lut10 tcon tcon_lut11 tcon tcon_lut12 tcon tcon_lut13 tcon tcon_ctrl2 siul, 64 registers to protect siul irer 32 c3f90000 018 bits[0:31] siul ireer 32 c3f90000 028 bits[0:31] siul ifeer 32 c3f90000 02c bits[0:31] siul ifer 32 c3f90000 030 bits[0:31] siul pcr0 16 c3f90000 040 bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-4 freescale semiconductor preliminary?subject to change without notice siul pcr1 16 c3f90000 042 bits[0:15] siul pcr2 16 c3f90000 044 bits[0:15] siul pcr3 16 c3f90000 046 bits[0:15] siul pcr4 16 c3f90000 048 bits[0:15] siul pcr5 16 c3f90000 04a bits[0:15] siul pcr6 16 c3f90000 04c bits[0:15] siul pcr7 16 c3f90000 04e bits[0:15] siul pcr8 16 c3f90000 050 bits[0:15] siul pcr9 16 c3f90000 052 bits[0:15] siul pcr10 16 c3f90000 054 bits[0:15] siul pcr11 16 c3f90000 056 bits[0:15] siul pcr12 16 c3f90000 058 bits[0:15] siul pcr13 16 c3f90000 05a bits[0:15] siul pcr14 16 c3f90000 05c bits[0:15] siul pcr15 16 c3f90000 05e bits[0:15] siul pcr16 16 c3f90000 060 bits[0:15] siul pcr17 16 c3f90000 062 bits[0:15] siul pcr18 16 c3f90000 064 bits[0:15] siul pcr19 16 c3f90000 066 bits[0:15] siul pcr34 16 c3f90000 084 bits[0:15] siul pcr35 16 c3f90000 086 bits[0:15] siul pcr36 16 c3f90000 088 bits[0:15] siul pcr37 16 c3f90000 08a bits[0:15] siul pcr38 16 c3f90000 08c bits[0:15] siul pcr39 16 c3f90000 08e bits[0:15] siul pcr40 16 c3f90000 090 bits[0:15] siul pcr41 16 c3f90000 092 bits[0:15] siul pcr42 16 c3f90000 094 bits[0:15] siul pcr43 16 c3f90000 096 bits[0:15] siul pcr44 16 c3f90000 098 bits[0:15] siul pcr45 16 c3f90000 09a bits[0:15] siul pcr46 16 c3f90000 09c bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-5 preliminary?subject to change without notice siul pcr47 16 c3f90000 09e bits[0:15] siul pcr48 16 c3f90000 0a0 bits[0:15] siul pcr49 16 c3f90000 0a2 bits[0:15] siul pcr50 16 c3f90000 0a4 bits[0:15] siul pcr51 16 c3f90000 0a6 bits[0:15] siul pcr52 16 c3f90000 0a8 bits[0:15] siul pcr53 16 c3f90000 0aa bits[0:15] siul pcr54 16 c3f90000 0ac bits[0:15] siul pcr55 16 c3f90000 0ae bits[0:15] siul pcr56 16 c3f90000 0b0 bits[0:15] siul pcr57 16 c3f90000 0b2 bits[0:15] siul pcr58 16 c3f90000 0b4 bits[0:15] siul pcr59 16 c3f90000 0b6 bits[0:15] siul pcr60 16 c3f90000 0b8 bits[0:15] siul pcr61 16 c3f90000 0ba bits[0:15] siul pcr62 16 c3f90000 0bc bits[0:15] siul pcr63 16 c3f90000 0be bits[0:15] siul pcr64 16 c3f90000 0c0 bits[0:15] siul pcr65 16 c3f90000 0c2 bits[0:15] siul pcr66 16 c3f90000 0c4 bits[0:15] siul pcr67 16 c3f90000 0c6 bits[0:15] siul pcr68 16 c3f90000 0c8 bits[0:15] siul pcr69 16 c3f90000 0ca bits[0:15] siul pcr70 16 c3f90000 0cc bits[0:15] siul pcr71 16 c3f90000 0ce bits[0:15] siul pcr72 16 c3f90000 0d0 bits[0:15] siul pcr73 16 c3f90000 0d2 bits[0:15] siul pcr74 16 c3f90000 0d4 bits[0:15] siul pcr75 16 c3f90000 0d6 bits[0:15] siul pcr76 16 c3f90000 0d8 bits[0:15] siul pcr77 16 c3f90000 0da bits[0:15] siul pcr78 16 c3f90000 0dc bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-6 freescale semiconductor preliminary?subject to change without notice siul pcr79 16 c3f90000 0de bits[0:15] siul pcr80 16 c3f90000 0e0 bits[0:15] siul pcr81 16 c3f90000 0e2 bits[0:15] siul pcr82 16 c3f90000 0e4 bits[0:15] siul pcr83 16 c3f90000 0e6 bits[0:15] siul pcr84 16 c3f90000 0e8 bits[0:15] siul pcr85 16 c3f90000 0ea bits[0:15] siul pcr86 16 c3f90000 0ec bits[0:15] siul pcr87 16 c3f90000 0ee bits[0:15] siul pcr88 16 c3f90000 0f0 bits[0:15] siul pcr89 16 c3f90000 0f2 bits[0:15] siul pcr90 16 c3f90000 0f4 bits[0:15] siul pcr91 16 c3f90000 0f6 bits[0:15] siul pcr92 16 c3f90000 0f8 bits[0:15] siul pcr93 16 c3f90000 0fa bits[0:15] siul pcr94 16 c3f90000 0fc bits[0:15] siul pcr95 16 c3f90000 0fe bits[0:15] siul pcr96 16 c3f90000 100 bits[0:15] siul pcr97 16 c3f90000 102 bits[0:15] siul pcr98 16 c3f90000 104 bits[0:15] siul pcr99 16 c3f90000 106 bits[0:15] siul pcr100 16 c3f90000 108 bits[0:15] siul pcr101 16 c3f90000 10a bits[0:15] siul pcr102 16 c3f90000 10c bits[0:15] siul pcr103 16 c3f90000 10e bits[0:15] siul pcr104 16 c3f90000 110 bits[0:15] siul pcr105 16 c3f90000 112 bits[0:15] siul pcr106 16 c3f90000 114 bits[0:15] siul pcr107 16 c3f90000 116 bits[0:15] siul pcr108 16 c3f90000 118 bits[0:15] siul pcr109 16 c3f90000 11a bits[0:15] siul pcr110 16 c3f90000 11c bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-7 preliminary?subject to change without notice siul pcr111 16 c3f90000 11e bits[0:15] siul pcr112 16 c3f90000 120 bits[0:15] siul pcr113 16 c3f90000 122 bits[0:15] siul pcr114 16 c3f90000 124 bits[0:15] siul pcr115 16 c3f90000 126 bits[0:15] siul pcr116 16 c3f90000 128 bits[0:15] siul pcr117 16 c3f90000 12a bits[0:15] siul pcr118 16 c3f90000 12c bits[0:15] siul pcr119 16 c3f90000 12e bits[0:15] siul pcr120 16 c3f90000 130 bits[0:15] siul pcr121 16 c3f90000 132 bits[0:15] siul pcr122 16 c3f90000 134 bits[0:15] siul pcr123 16 c3f90000 136 bits[0:15] siul pcr124 16 c3f90000 138 bits[0:15] siul pcr125 16 c3f90000 13a bits[0:15] siul pcr126 16 c3f90000 13c bits[0:15] siul pcr127 16 c3f90000 13e bits[0:15] siul pcr128 16 c3f90000 140 bits[0:15] siul pcr129 16 c3f90000 142 bits[0:15] siul pcr130 16 c3f90000 144 bits[0:15] siul pcr131 16 c3f90000 146 bits[0:15] siul pcr132 16 c3f90000 148 bits[0:15] siul pcr133 16 c3f90000 14a bits[0:15] siul pcr134 16 c3f90000 14c bits[0:15] siul pcr135 16 c3f90000 14e bits[0:15] siul pcr136 16 c3f90000 150 bits[0:15] siul pcr137 16 c3f90000 152 bits[0:15] siul pcr138 16 c3f90000 154 bits[0:15] siul pcr139 16 c3f90000 156 bits[0:15] siul pcr140 16 c3f90000 158 bits[0:15] siul pcr141 16 c3f90000 15a bits[0:15] siul pcr142 16 c3f90000 15c bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-8 freescale semiconductor preliminary?subject to change without notice siul pcr143 16 c3f90000 15e bits[0:15] siul pcr144 16 c3f90000 160 bits[0:15] siul pcr145 16 c3f90000 162 bits[0:15] siul pcr146 16 c3f90000 164 bits[0:15] siul pcr147 16 c3f90000 166 bits[0:15] siul pcr148 16 c3f90000 168 bits[0:15] siul pcr149 16 c3f90000 16a bits[0:15] siul pcr150 16 c3f90000 16c bits[0:15] siul pcr151 16 c3f90000 16e bits[0:15] siul pcr152 16 c3f90000 170 bits[0:15] siul pcr153 16 c3f90000 172 bits[0:15] siul pcr154 16 c3f90000 174 bits[0:15] siul pcr155 16 c3f90000 176 bits[0:15] siul pcr156 16 c3f90000 178 bits[0:15] siul pcr157 16 c3f90000 17a bits[0:15] siul pcr158 16 c3f90000 17c bits[0:15] siul pcr159 16 c3f90000 17e bits[0:15] siul pcr160 16 c3f90000 180 bits[0:15] siul pcr161 16 c3f90000 182 bits[0:15] siul pcr162 16 c3f90000 184 bits[0:15] siul pcr163 16 c3f90000 186 bits[0:15] siul pcr164 16 c3f90000 188 bits[0:15] siul pcr165 16 c3f90000 18a bits[0:15] siul pcr166 16 c3f90000 18c bits[0:15] siul pcr167 16 c3f90000 18e bits[0:15] siul pcr168 16 c3f90000 190 bits[0:15] siul pcr169 16 c3f90000 192 bits[0:15] siul pcr170 16 c3f90000 194 bits[0:15] siul pcr171 16 c3f90000 196 bits[0:15] siul pcr172 16 c3f90000 198 bits[0:15] siul pcr173 16 c3f90000 19a bits[0:15] siul pcr174 16 c3f90000 19c bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-9 preliminary?subject to change without notice siul pcr175 16 c3f90000 19e bits[0:15] siul pcr176 16 c3f90000 1a0 bits[0:15] siul pcr177 16 c3f90000 1a2 bits[0:15] siul pcr178 16 c3f90000 1a4 bits[0:15] siul pcr179 16 c3f90000 1a6 bits[0:15] siul pcr180 16 c3f90000 1a8 bits[0:15] siul pcr181 16 c3f90000 1aa bits[0:15] siul pcr182 16 c3f90000 1ac bits[0:15] siul pcr183 16 c3f90000 1ae bits[0:15] siul pcr184 16 c3f90000 1b0 bits[0:15] siul pcr185 16 c3f90000 1b2 bits[0:15] siul pcr186 16 c3f90000 1b4 bits[0:15] siul pcr187 16 c3f90000 1b6 bits[0:15] siul pcr188 16 c3f90000 1b8 bits[0:15] siul pcr189 16 c3f90000 1ba bits[0:15] siul pcr190 16 c3f90000 1bc bits[0:15] siul pcr191 16 c3f90000 1be bits[0:15] siul pcr192 16 c3f90000 1c0 bits[0:15] siul pcr193 16 c3f90000 1c2 bits[0:15] siul pcr194 16 c3f90000 1c4 bits[0:15] siul pcr195 16 c3f90000 1c6 bits[0:15] siul pcr196 16 c3f90000 1c8 bits[0:15] siul pcr197 16 c3f90000 1ca bits[0:15] siul pcr198 16 c3f90000 1cc bits[0:15] siul pcr199 16 c3f90000 1ce bits[0:15] siul pcr200 16 c3f90000 1d0 bits[0:15] siul pcr201 16 c3f90000 1d2 bits[0:15] siul pcr202 16 c3f90000 1d4 bits[0:15] siul pcr203 16 c3f90000 1d6 bits[0:15] siul pcr204 16 c3f90000 1d8 bits[0:15] siul pcr205 16 c3f90000 1da bits[0:15] siul pcr206 16 c3f90000 1dc bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-10 freescale semiconductor preliminary?subject to change without notice siul pcr207 16 c3f90000 1de bits[0:15] siul pcr208 16 c3f90000 1e0 bits[0:15] siul pcr209 16 c3f90000 1e2 bits[0:15] siul pcr210 16 c3f90000 1e4 bits[0:15] siul pcr211 16 c3f90000 1e6 bits[0:15] siul pcr212 16 c3f90000 1e8 bits[0:15] siul pcr213 16 c3f90000 1ea bits[0:15] siul pcr214 16 c3f90000 1ec bits[0:15] siul pcr215 16 c3f90000 1ee bits[0:15] siul pcr216 16 c3f90000 1f0 bits[0:15] siul pcr217 16 c3f90000 1f2 bits[0:15] siul pcr218 16 c3f90000 1f4 bits[0:15] siul pcr219 16 c3f90000 1f6 bits[0:15] siul pcr220 16 c3f90000 1f8 bits[0:15] siul pcr221 16 c3f90000 1fa bits[0:15] siul pcr222 16 c3f90000 1fc bits[0:15] siul pcr223 16 c3f90000 1fe bits[0:15] siul pcr224 16 c3f90000 200 bits[0:15] siul pcr225 16 c3f90000 202 bits[0:15] siul pcr226 16 c3f90000 204 bits[0:15] siul pcr227 16 c3f90000 206 bits[0:15] siul pcr228 16 c3f90000 208 bits[0:15] siul pcr229 16 c3f90000 20a bits[0:15] siul pcr230 16 c3f90000 20c bits[0:15] siul pcr231 16 c3f90000 20e bits[0:15] siul pcr232 16 c3f90000 210 bits[0:15] siul pcr233 16 c3f90000 212 bits[0:15] siul pcr234 16 c3f90000 214 bits[0:15] siul pcr235 16 c3f90000 216 bits[0:15] siul pcr236 16 c3f90000 218 bits[0:15] siul pcr237 16 c3f90000 21a bits[0:15] siul pcr238 16 c3f90000 21c bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-11 preliminary?subject to change without notice siul pcr239 16 c3f90000 21e bits[0:15] siul pcr240 16 c3f90000 220 bits[0:15] siul pcr241 16 c3f90000 222 bits[0:15] siul pcr242 16 c3f90000 224 bits[0:15] siul pcr243 16 c3f90000 226 bits[0:15] siul pcr244 16 c3f90000 228 bits[0:15] siul pcr245 16 c3f90000 22a bits[0:15] siul pcr246 16 c3f90000 22c bits[0:15] siul pcr247 16 c3f90000 22e bits[0:15] siul pcr248 16 c3f90000 230 bits[0:15] siul pcr249 16 c3f90000 232 bits[0:15] siul pcr250 16 c3f90000 234 bits[0:15] siul pcr251 16 c3f90000 236 bits[0:15] siul pcr252 16 c3f90000 238 bits[0:15] siul pcr253 16 c3f90000 23a bits[0:15] siul pcr254 16 c3f90000 23c bits[0:15] siul pcr255 16 c3f90000 23e bits[0:15] siul pcr256 16 c3f90000 240 bits[0:15] siul pcr257 16 c3f90000 242 bits[0:15] siul pcr258 16 c3f90000 244 bits[0:15] siul pcr259 16 c3f90000 246 bits[0:15] siul pcr260 16 c3f90000 248 bits[0:15] siul pcr261 16 c3f90000 24a bits[0:15] siul pcr262 16 c3f90000 24c bits[0:15] siul pcr263 16 c3f90000 24e bits[0:15] siul pcr264 16 c3f90000 250 bits[0:15] siul pcr265 16 c3f90000 252 bits[0:15] siul pcr266 16 c3f90000 254 bits[0:15] siul pcr267 16 c3f90000 256 bits[0:15] siul pcr268 16 c3f90000 258 bits[0:15] siul pcr269 16 c3f90000 25a bits[0:15] siul pcr270 16 c3f90000 25c bits[0:15] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-12 freescale semiconductor preliminary?subject to change without notice siul pcr271 16 c3f90000 25e bits[0:15] siul pcr272 16 c3f90000 260 bits[0:15] siul pcr273 16 c3f90000 262 bits[0:15] siul pcr274 16 c3f90000 264 bits[0:15] siul pcr275 16 c3f90000 266 bits[0:15] siul pcr276 16 c3f90000 268 bits[0:15] siul pcr277 16 c3f90000 26a bits[0:15] siul pcr278 16 c3f90000 26c bits[0:15] siul pcr279 16 c3f90000 26e bits[0:15] siul pcr280 16 c3f90000 270 bits[0:15] siul pcr281 16 c3f90000 272 bits[0:15] siul psmi0 8 c3f90000 500 bits[0:31] siul psmi4 8 c3f90000 504 bits[0:31] siul psmi8 8 c3f90000 508 bits[0:31] siul psmi12 8 c3f90000 50c bits[0:31] siul psmi16 8 c3f90000 510 bits[0:31] siul psmi20 8 c3f90000 514 bits[0:31] siul psmi24 8 c3f90000 518 bits[0:31] siul psmi28 8 c3f90000 51c bits[0:31] siul psmi32 8 c3f90000 520 bits[0:31] siul psmi36 8 c3f90000 524 bits[0:31] siul psmi40 8 c3f90000 528 bits[0:31] siul psmi44 8 c3f90000 52c bits[0:31] siul psmi48 8 c3f90000 530 bits[0:31] siul psmi52 8 c3f90000 534 bits[0:31] siul ifmc0 32 c3f90000 1000 bits[0:31] siul ifmc1 32 c3f90000 1004 bits[0:31] siul ifmc2 32 c3f90000 1008 bits[0:31] siul ifmc3 32 c3f900 00 100c bits[0:31] siul ifmc4 32 c3f90000 1010 bits[0:31] siul ifmc5 32 c3f90000 1014 bits[0:31] siul ifmc6 32 c3f90000 1018 bits[0:31] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-13 preliminary?subject to change without notice siul ifmc7 32 c3f900 00 101c bits[0:31] siul ifmc8 32 c3f90000 1020 bits[0:31] siul ifmc9 32 c3f90000 1024 bits[0:31] siul ifmc10 32 c3f90000 1028 bits[0:31] siul ifmc11 32 c3f90000 102c bits[0:31] siul ifmc12 32 c3f90000 1030 bits[0:31] siul ifmc13 32 c3f90000 1034 bits[0:31] siul ifmc14 32 c3f90000 1038 bits[0:31] siul ifmc15 32 c3f90000 103c bits[0:31] siul ifmc16 32 c3f90000 1040 bits[0:31] siul ifmc17 32 c3f90000 1044 bits[0:31] siul ifmc18 32 c3f90000 1048 bits[0:31] siul ifmc19 32 c3f90000 104c bits[0:31] siul ifmc20 32 c3f90000 1050 bits[0:31] siul ifmc21 32 c3f90000 1054 bits[0:31] siul ifmc22 32 c3f90000 1058 bits[0:31] siul ifmc23 32 c3f90000 105c bits[0:31] siul ifcpr 32 c3f90000 1080 bits[0:31] mc_me, 41 registers to protect mc_me me_me 32 c3fdc000 008 bits[0:31] mc_me me_im 32 c3fdc000 010 bits[0:31] mc_me me_test_mc 32 c3fdc000 024 bits[0:31] mc_me me_safe_mc 32 c3fdc000 028 bits[0:31] mc_me me_drun_mc 32 c3fdc000 02c bits[0:31] mc_me me_run0_mc 32 c3fdc000 030 bits[0:31] mc_me me_run1_mc 32 c3fdc000 034 bits[0:31] mc_me me_run2_mc 32 c3fdc000 038 bits[0:31] mc_me me_run3_mc 32 c3fdc000 03c bits[0:31] mc_me me_halt_mc 32 c3fdc000 040 bits[0:31] mc_me me_stop_mc 32 c3fdc000 048 bits[0:31] mc_me me_standby_mc 32 c3fdc000 054 bits[0:31] mc_me me_run_pc0 32 c3fdc000 080 bits[0:31] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-14 freescale semiconductor preliminary?subject to change without notice mc_me me_run_pc1 32 c3fdc000 084 bits[0:31] mc_me me_run_pc2 32 c3fdc000 088 bits[0:31] mc_me me_run_pc3 32 c3fdc000 08c bits[0:31] mc_me me_run_pc4 32 c3fdc000 090 bits[0:31] mc_me me_run_pc5 32 c3fdc000 094 bits[0:31] mc_me me_run_pc6 32 c3fdc000 098 bits[0:31] mc_me me_run_pc7 32 c3fdc000 09c bits[0:31] mc_me me_lp_pc0 32 c3fdc000 0a0 bits[0:31] mc_me me_lp_pc1 32 c3fdc000 0a4 bits[0:31] mc_me me_lp_pc2 32 c3fdc000 0a8 bits[0:31] mc_me me_lp_pc3 32 c3fdc000 0ac bits[0:31] mc_me me_lp_pc4 32 c3fdc000 0b0 bits[0:31] mc_me me_lp_pc5 32 c3fdc000 0b4 bits[0:31] mc_me me_lp_pc6 32 c3fdc000 0b8 bits[0:31] mc_me me_lp_pc7 32 c3fdc000 0bc bits[0:31] mc_me me_pctl[4..7] 32 c3fdc000 0c4 bits[0:31] mc_me me_pctl[16..19] 32 c3fdc000 0d0 bits[0:31] mc_me me_pctl[20..23] 32 c3fdc000 0d4 bits[0:31] mc_me me_pctl[32..35] 32 c3fdc000 0e0 bits[0:31] mc_me me_pctl[44..47] 32 c3fdc000 0ec bits[0:31] mc_me me_pctl[48..51] 32 c3fdc000 0f0 bits[0:31] mc_me me_pctl[56..59] 32 c3fdc000 0f8 bits[0:31] mc_me me_pctl[60..63] 32 c3fdc000 0fc bits[0:31] mc_me me_pctl[68..71] 32 c3fdc000 104 bits[0:31] mc_me me_pctl[72..75] 32 c3fdc000 108 bits[0:31] mc_me me_pctl[88.91] 32 c3fdc000 118 bits[0:31] mc_me me_pctl[92..95] 32 c3fdc000 11c bits[0:31] mc_me me_pctl[104..107] 32 c3fdc000 128 bits[0:31] mc_cgm, 3 registers to protect mc_cgm cgm_oc_en 8 c3fe0000 373 bits[0:7] mc_cgm cgm_ocds_sc 8 c3fe0000 374 bits[0:7] mc_cgm cgm_sc_dc[0..3] 32 c3fe0000 37c bits[0:31] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor a-15 preliminary?subject to change without notice cmu 0, 1 register to protect cmu 0 cmu_csr 32 c3fe0100 000 bits[24:31] mc_rgm, 9 registers to protect mc_rgm rgm_fes 16 c3fe4000 000 bits[0:15] mc_rgm rgm_des 16 c3fe4000 002 bits[0:15] mc_rgm rgm_ferd 16 c3fe4000 004 bits[0:15] mc_rgm rgm_derd 16 c3fe4000 006 bits[0:15] mc_rgm rgm_fear 16 c3fe4000 010 bits[0:15] mc_rgm rgm_dear 16 c3fe4000 012 bits[0:15] mc_rgm rgm_fess 16 c3fe4000 018 bits[0:15] mc_rgm rgm_stdby 16 c3fe4000 01a bits[0:15] mc_rgm rgm_fbre 16 c3fe4000 01c bits[0:15] mc_pcu, 1 register to protect mc_pcu pconf2 32 c3fe8000 008 bits[0:31] table a-1. registers under protection (continued) module register register size module base register offset protected bitfields
pxd20 microcontroller reference manual, rev. 1 a-16 freescale semiconductor preliminary?subject to change without notice
pxd20 microcontroller reference manual, rev. 1 freescale semiconductor b-1 preliminary?subject to change without notice appendix b revision history this appendix describes corrections to the pxd20 microcontroller reference manual . for convenience, the corrections ar e grouped by revision. this is the first revision of this manual.
pxd20 microcontroller reference manual, rev. 1 b-2 freescale semiconductor preliminary?subject to change without notice

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