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freescale semiconductor data sheet: advance information document number: pxs20 rev. 1, 09/2011 ? freescale semiconductor, inc., 2011. all rights reserved. preliminary?subject to change without notice this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. pxs20 tbd mapbga?225 15 mm x 15 mm qfn12 ##_mm_x_##mm sot-343r ##_mm_x_##mm pkg-tbd ## mm x ## mm 257 mapbga (14 x 14 x 0.8 mm) (20 x 20 x 1.4 mm) 144 lqfp ? high-performance e200z4d dual core ? 32-bit power architecture ? technology cpu ? core frequency as high as 120 mhz ? dual issue five-stage pipeline core ? variable length encoding (vle) ? memory management unit (mmu) ? 4 kb instruction cache with error detection code ? signal processing engine (spe) ? memory available ? 1 mb flash memory with ecc ? 128 kb on-chip sram with ecc ? built-in rww capabilities for eeprom emulation ? sil3/asild innovative safety concept: lockstep mode and fail-safe protection ? sphere of replication (sor) for key components (such as cpu core, edma, crossbar switch) ? fault collection and control unit (fccu) ? redundancy control and checker unit (rccu) on outputs of the sor connected to fccu ? boot-time built-in self-test for memory (mbist) and logic (lbist) triggered by hardware ? boot-time built-in self-test for adc and flash memory triggered by software ? replicated safety enhanced watchdog ? replicated junction temperature sensor ? non-maskable interrupt (nmi) ? 16-region memory protection unit (mpu) ? clock monitoring units (cmu) ? power management unit (pmu) ? cyclic redundancy check (crc) unit ? decoupled parallel mode for high-performance use of replicated cores ? nexus class 3+ interface ? interrupts ? replicated 16-prio rity controller ? replicated 16-channel edma controller ? gpios individually programmable as input, output or special function ? three 6-channel general-purpose etimer units ? 2 flexpwm units ? four 16-bit channels per module ? communications interfaces ? 2 linflexd channels ? 3 dspi channels with automatic chip select generation ? 2 flexcan interfaces (2.0b active) with 32 message objects ? flexray module (v2.1 rev. a) with 2 channels, 64 message buffers and data rates up to 10 mbit/s ? two 12-bit analog-to-digital converters (adcs) ? 16 input channels ? programmable cross triggering unit (ctu) to synchronize adcs conversion with timer and pwm ? sine wave generator (d/a with low pass filter) ? on-chip can/uart bootstrap loader ? single 3.0 v to 3.6 v voltage supply ? ambient temperature range ?40 c to 125 c ? junction temperature range ?40 c to 150 c pxs20 microcontroller data sheet
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 2 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.3 device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.5.1 high-performance e200z4d core . . . . . . . . . . . .7 1.5.2 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . .8 1.5.3 memory protection unit (mpu) . . . . . . . . . . . . . .8 1.5.4 enhanced direct memory access (edma) . . . . .9 1.5.5 on-chip flash memory with ecc . . . . . . . . . . . .9 1.5.6 on-chip sram with ecc . . . . . . . . . . . . . . . . . .9 1.5.7 platform flash memory controller. . . . . . . . . . .10 1.5.8 platform static ram controller (sramc) . . . . .10 1.5.9 memory subsystem access time . . . . . . . . . . .11 1.5.10 error correction status module (ecsm) . . . . . .11 1.5.11 peripheral bridge (pbridge) . . . . . . . . . . . . . .11 1.5.12 interrupt controller (intc). . . . . . . . . . . . . . . . .11 1.5.13 system clocks and clock generation . . . . . . . .12 1.5.14 frequency-modulated phase-locked loop (fmpll). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5.15 main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.5.16 internal reference clock (rc) oscillator. . . . . .13 1.5.17 clock, reset, power mode, and test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.5.18 periodic interrupt timer module (pit) . . . . . . . .13 1.5.19 system timer module (stm). . . . . . . . . . . . . . .14 1.5.20 software watchdog timer (swt) . . . . . . . . . . .14 1.5.21 fault collection and control unit (fccu) . . . . .14 1.5.22 system integration unit lite (siul) . . . . . . . . . .14 1.5.23 non-maskable interrupt (nmi) . . . . . . . . . . . . . .15 1.5.24 boot assist module (bam). . . . . . . . . . . . . . . . .15 1.5.25 system status and configuration module (sscm) 15 1.5.26 controller area network module (can) . . . . . .15 1.5.27 flexray . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 1.5.28 serial communication interface module (uart)16 1.5.29 serial peripheral interface (spi) . . . . . . . . . . . .17 1.5.30 pulse width modulator (pwm) . . . . . . . . . . . . .17 1.5.31 etimer module. . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.32 sine wave generator (swg) . . . . . . . . . . . . . .19 1.5.33 analog-to-digital converter module (adc) . . . .19 1.5.34 junction temperature sensor . . . . . . . . . . . . . .20 1.5.35 cross triggering unit (ctu) . . . . . . . . . . . . . . .20 1.5.36 cyclic redundancy checker (crc) unit . . . . . .20 1.5.37 redundancy control and checker unit (rccu)21 1.5.38 voltage regulator / power management unit (pmu)21 1.5.39 built-in self-test (bist) capability . . . . . . . . . .21 1.5.40 ieee 1149.1 jtag controller (jtagc) . . . . . . 21 1.5.41 nexus port controller (npc) . . . . . . . . . . . . . . 22 2 package pinouts and signal descriptions . . . . . . . . . . . . . . . 23 2.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2 supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.4 pin muxing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 73 3.3 recommended operating conditions . . . . . . . . . . . . . . 74 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4.1 general notes for specifications at maximum junction temperature. . . . . . . . . . . . . . . . . . . . . 76 3.5 electromagnetic interference (emi) characteristics (cut1) 77 3.6 electrostatic discharge (esd) characteristics . . . . . . . 78 3.7 static latch-up (lu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.8 voltage regulator electrical c haracteristics . . . . . . . . . 79 3.9 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . 82 3.10 supply current characteristics (cut2) . . . . . . . . . . . . . . 83 3.11 temperature sensor electrical characteristics . . . . . . . 84 3.12 main oscillator elec trical characteristics . . . . . . . . . . . 84 3.13 fmpll electrical characteristics . . . . . . . . . . . . . . . . . 86 3.14 16 mhz rc oscillator electric al characteristics . . . . . . 88 3.15 adc electrical characteristics . . . . . . . . . . . . . . . . . . . 88 3.15.1 input impedance and adc accuracy . . . . . . . . 88 3.16 flash memory electrical charac teristics . . . . . . . . . . . 93 3.17 swg electrical characteristics. . . . . . . . . . . . . . . . . . . 94 3.18 ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.18.1 pad ac specifications. . . . . . . . . . . . . . . . . . . . 94 3.19 reset sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 3.19.1 reset sequence duration . . . . . . . . . . . . . . . . . 96 3.19.2 reset sequence description. . . . . . . . . . . . . . . 96 3.19.3 reset sequence trigger m apping . . . . . . . . . . . 98 3.19.4 reset sequence ? start condition . . . . . . . . . 100 3.19.5 external watchdog window. . . . . . . . . . . . . . . 101 3.20 ac timing characteristics . . . . . . . . . . . . . . . . . . . . . . 101 3.20.1 reset pin characteristics . . . . . . . . . . . . . . . 102 3.20.2 wkup/nmi timing . . . . . . . . . . . . . . . . . . . . . 103 3.20.3 ieee 1149.1 jtag interface timing . . . . . . . . 103 3.20.4 nexus timing. . . . . . . . . . . . . . . . . . . . . . . . . . 105 3.20.5 external interrupt timing (irq pin) . . . . . . . . . 107 3.20.6 dspi timing . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4 package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . 113 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6 document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 118
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 3 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical char acteristics of the devices. this document provides electrical speci fications, pin assignments, and package diagrams for the pxs20 series of microcontroller units (mcus). for functional characteristics, see the pxs20 microcontroller reference manual . for use of the pxs20 in a fail-safe system according to safety stan dard iec 61508, see the safety application guide for mpc5643l. the pxs20 mcu series is available in two silicon versions, or ?cuts?. these are referred to as ?cut1? and ?cut2? throughout this document. functional differences between the two cuts are clearly identified with the labels ?cut1? and ?cut2?. 1.2 description the pxs20 series microcontroller s are system-on-chip devices that are built on power architecture technology and contain enhancements that improve the architecture?s fit in embedded applications, include additional instruction support for digital signal processing (dsp) and inte grate technologies such as an enhanced time pr ocessor unit, enhanced queued analog-to-digital converter, controller area network, and an enhanced modular input-output system. the pxs20 family of 32-bit microcontrollers is the latest achie vement in integrated safety controllers. the advanced and cost-efficient host processor core of the pxs20 family complies with the power architecture embedd ed category. it operates at speeds as high as 120 mhz and offers high -performance processing optimized for low power consumption. it capitalizes on the available development infrastructure of cu rrent power architecture devices and is su pported with software drivers, operating systems and configuration code to as sist with users? implementations. 1.3 device comparison table 1. pxs20 family feature set feature pxs20 cpu type 2 e200z4 (in lock-step or decoupled operation) architecture harvard execution speed 0 ? 120 mhz (+2% fm) dmips intrinsic performance > 240 mips simd (dsp + fpu) yes mmu 16 entry instruction set ppc yes instruction set vle yes instruction cache 4 kb, edc mpu-16 regions yes, replicated module semaphore unit (sema4) yes buses core bus ahb, 32-bit address, 64-bit data internal periphery bus 32-bit address, 32-bit data
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 4 crossbar master slave ports lock step mode: 4 3 decoupled parallel mode: 6 3 memory code/data flash 1 mb, ecc, rww static ram (sram) 128 kb, ecc modules interrupt controller (intc) 16 interrupt levels, replicated module periodic interrupt timer (pit) 1 4 channels system timer module (stm) 1 4 channels, replicated module software watchdog timer (swt) yes, replicated module edma 16 channels, replicated module flexray 1 64 message buffers, dual channel can 2 32 message buffers uart with dma support 2 clock out yes fault control & collection unit (fccu) yes cross triggering unit (ctu) yes etimer 3 6 channels pwm 2 module 4 (2 + 1) channels analog-to-digital converter (adc) 2 12-bit adc, 16 channels per adc (3 internal, 4 shared and 9 external) modules (cont.) sine-wave generator (swg) 32 point serial peripheral interface (spi) 3 spi as many as 8 chip selects cyclic redundancy checker (crc) unit yes junction temperature sensor (tsens) yes, replicated module digital i/os ? 16 supply device power supply 3.3 v with integrated bypassable ballast transistor external ballast transistor not needed for bare die analog reference voltage 3.0 v ? 3.6 v and 4.5 v ? 5.5 v clocking frequency-modulated phase-locked loop (fmpll) 2 internal rc oscillator 16 mhz external crystal oscillator 4 ? 40 mhz debug nexus level 3+ packages type 144 lqfp 257 mapbga table 1. pxs20 family feature set (continued) feature pxs20
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 5 temperature temperature range (junction) ?40 to 150 c ambient temperature range using external ballast transistor (lqfp) ?40 to 125 c ambient temperature range using external ballast transistor (bga) tbd table 1. pxs20 family feature set (continued) feature pxs20
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 6 1.4 block diagram figure 1 shows a top-level block diagram of the pxs20 device. figure 1. pxs20 block diagram crossbar switch (xbar) memory protection unit (mpu) fpu vle i-cache e200z4 redundancy checker mmu swt ecsm pmu stm intc edma debug jtag nexus flexray? spe2 vle cache e200z4 mmu swt ecsm pmu stm intc edma redundancy checker pbridge 1 mb flash (ecc) crossbar switch (xbar) memory protection unit (mpu) redundancy checker pbridge 128 kb sram (ecc) redundancy checker bam pxs20 block diagram sscm fmpll fmpll ircosc cmu cmu cmu tsens tsens crc pit pit bam xosc siu wkpu adc adc ctu pwm pwm etimer etimer etimer can can uart/lin uart/lin spi spi spi fccu
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 7 figure 2. pxs20 block diagram (continued) 1.5 feature details 1.5.1 high-performance e200z4d core the e200z4d power architecture ? core provides the following features: ? 2 independent execution units, both supporting fixed-point and floating-point operations ? dual issue 32-bit power architecture ? technology compliant ? 5-stage pipeline (if, dec, ex1, ex2, wb) ? in-order execution and instruction retirement ? full support for power architecture ? instruction set and variable length encoding (vle) ? mix of classic 32-bit and 16-bit instruction allowed ? optimization of code size possible ? thirty-two 64-bit general purpose registers (gprs) ? harvard bus (32-bit address, 64-bit data) ? i-bus interface capable of one outstanding transac tion plus one piped with no wait-on-data return ? d-bus interface capable of two trans actions outstandin g to fill ahb pipe ? i-cache and i-cache controller ? 4 kb, 256-bit cache line (pr ogrammable for 2- or 4-way) ? no data cache ? 16-entry mmu ? 8-entry branch table buffer ? branch look-ahead instructio n buffer to accelerate branching ? dedicated branch address calculator ? 3 cycles worst case for missed branch ? load/store unit ? fully pipelined ? single-cycle load latency ? big- and little-endian modes supported adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller cmu ? clock monitoring unit crc ? cyclic redundanc y check unit ctu ? cross triggering unit ecc ? error correction code ecsm ? error correction status module edma ? enhanced direct memory access controller fccu ? fault collection and control unit fmpll ? frequency modulated phase locked loop intc ? interrupt controller ircosc ? internal rc oscillator jtag ? joint test action group interface mc ? mode entry, clock, reset, & power pbridge ? peripheral i/o bridge pit ? periodic interrupt timer pmu ? power management unit pwm ? pulse width modulator module rc ? redundancy checker rtc ? real time clock sema4 ? semaphore unit siul ? system integration unit lite spi ? serial peripherals interface controller sscm ? system status and configuration module stm ? system timer module swg ? sine wave generator swt ? software watchdog timer tsens ? temperature sensor uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network wkpu ? wakeup unit xosc ? crystal oscillator
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 8 ? misaligned access support ? single stall cycle on load to use ? single-cycle throughput (2-cycle latency) integer 32 32 multiplication ? 4 ? 14 cycles integer 32 32 division (average division on various benchmark of nine cycles) ? single precision floating-point unit ? 1 cycle throughput (2-cycle latency) floating-point 32 32 multiplication ? target 9 cycles (worst case acceptable is 12 cy cles) throughput floating-point 32 32 division ? special square root and min/max function implemented ? signal processing support: apu-spe 1.1 ? support for vectorized mode: as many as two floating-point instructions per clock ? vectored interrupt support ? reservation instruction to support read-modify-write constructs ? extensive system development and tracing support via nexus debug port 1.5.2 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connec tions between four master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. the crossbar allows four concurrent trans actions to occur from any master port to any slave port, although one of those transfe rs must be an instruction fetch from internal flash memory. if a slave port is simultaneously requ ested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. all other masters request ing that slave port are stalled until the higher priority master completes its transactions. the crossbar provides the following features: ? 4 masters and 3 slaves suppor ted per each replicated crossbar ? masters allocation for each crossbar: e200z4d core with two independent bus interface units (biu) for i and d access (2 masters), one edma, one flexray ? slaves allocation for each crossbar: a redundant flash-memory controller with 2 slave ports to guarantee maximum flexibility to handle instruction and data array, one redundant sr am controller with 1 slave port each and 1 redundant peripheral bus bridge ? 32-bit address bus and 64-bit data bus ? programmable arbitration priority ? requesting masters can be treated with equal priority a nd are granted access to a slave port in round- robin method, based upon the id of the last master to be granted access or a priority or der can be assigned by software at application run time ? temporary dynamic priori ty elevation of masters the xbar is replicated for each processor. 1.5.3 memory protection unit (mpu) the memory protection unit splits the physical memory into 16 different regions. each master (edma, flexray, cpu) can be assigned different access rights to each region. ? 16-region mpu with concurrent checks against each master access ? 32-byte granularity for protected address region the memory protection unit is replicated for each processor.
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 9 1.5.4 enhanced direct memory access (edma) the enhanced direct memory access (edma) controller is a s econd-generation modul e capable of performing complex data movements via 16 programmable channels, with minimal interventi on from the host processor. the hardware microarchitecture includes a dma engine which performs source and destination ad dress calculations, and the actual data movement operations, along with an sram-based memory contai ning the transfer control descriptors (t cd) for the channels. this implementation is used to minimize the overall block size. the edma module provides the following features: ? 16 channels supporting 8-, 16-, and 32 -bit value single or block transfers ? support variable sized queues and circular buffered queue ? source and destination address registers independently configured to post-increment or stay constant ? support major and minor loop offset ? support minor and major loop done signals ? dma task initiated either by hardware requestor or by software ? each dma task can optionally generate an inte rrupt at completion an d retirement of the task ? signal to indicate closure of last minor loop ? transfer control descriptors mapped inside the sram the edma controller is rep licated for each processor. 1.5.5 on-chip flash memory with ecc this device includes programmable, non-volatile flash memory. the non-volatile memory (nvm) can be used for instruction storage or data storage, or both. the flash memory module in terfaces with the system bus th rough a dedicated flash memory array controller. it supports a 64-bit data bus width at the sy stem bus port, and a 128-bit read data interface to flash memory . the module contains four 128-bit prefetch buffers. prefetch buffe r hits allow no-wait responses. buffer misses incur a 3 wait state response at 120 mhz. the flash memory module prov ides the following features ? 1 mb of flash memory in unique multi-partitioned hard macro ? sectorization: 16 kb + 2 48 kb + 16 kb + 2 64 kb + 2 128 kb + 2 256 kb ? eeprom emulation (in software) within same module but on different partition ? 16 kb test sector and 16 kb shadow sector for test, censorship device and user option bits ? wait states: ? 3 wait states at 120 mhz ? 2 wait states at 80 mhz ? 1 wait state at 60 mhz ? flash memory line 128-bit wide with 8-bit ecc on 64-bit word (total 144 bits) ? accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations ? 1-bit error correction, 2-bit error detection 1.5.6 on-chip sram with ecc the pxs20 sram provides a general-purpose single port memory. ecc handling is done on a 32-bit boundary for data and it is exte nded to the address to have the highest possible diagnostic coverage including the array internal address decoder. the sram module provides the following features: ? system sram: 128 kb
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 10 ? ecc on 32-bit word (syndrome of 7 bits) ? ecc covers sram bus address ? 1-bit error correction, 2-bit error detection ? wait states: ? 1 wait state at 120 mhz ? 0 wait states at 80 mhz and 60 mhz 1.5.7 platform flash memory controller the following list summarizes the key f eatures of the flash memory controller: ? single ahb port interface supports a 64-bi t data bus. all ahb aligned and unali gned reads within the 32-bit container are supported. only aligned word writes are supported. ? array interfaces support a 128- bit read data bus and a 64-bit write data bus for each bank. ? code flash (bank0) interface provid es configurable read buffering and page prefetch support. ? four page-read buffers (each 128 bits wide) and a prefet ch controller support specula tive reading and optimized flash access. ? single-cycle read responses (0 ahb data-phase wait states) for hits in the buffers. the buffers implement a least-recently-used replacement al gorithm to maximize performance. ? data flash (bank1) interface includes a 12 8-bit register to temporar ily hold a single flash pa ge. this logic supports single-cycle read responses (0 ahb data-phase wait states) for accesses that hit in the holding register. ? no prefetch support is provided for this bank. ? programmable response for read-while-write sequences in cluding support for stall-while-write, optional stall notification interrupt, optional flash operation a bort , and optional abort notification interrupt. ? separate and independent configurable access timing (on a per bank basis) to support use across a wide range of platforms and frequencies. ? support of address-based read access timing for emulatio n of other memory types. ? support for reporting of single- and multi-bit error events. ? typical operating configuration loaded in to programming model by system reset. the platform flash controller is replicated for each processor. 1.5.8 platform static ram controller (sramc) the sramc module is the platform sram array controll er, with integrated error detection and correction. the main features of the sramc provide connectivity for the following interfaces: ? xbar slave port (64-bit data path) ? ecsm (ecc error reporting, er ror injection and configuration) ? sram array the following functions are implemented: ? ecc encoding (32-bit boundary for data and complete address bus) ? ecc decoding (32-bit boundary and entire address) ? address translation from the ahb protocol on the xbar to the sram array the platform sram controller is replicated for each processor.
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 11 1.5.9 memory subsystem access time every memory access the cpu performs requir es at least one system clock cycle fo r the data phase of the access. slower memories or peripherals may require additiona l data phase wait states. additional data phase wait states may also occur if the slave being accessed is not parked on th e requesting master in the crossbar. table 2 shows the number of additional data phase wait states required for a range of memory accesses. 1.5.10 error correction status module (ecsm) the ecsm on this device manages the ecc configuration and repo rting for the platform memories (flash memory and sram). it does not implement the actual ecc calculation. a detected error (double erro r for flash memory or sram) is also reported to the fccu. the following errors and indications are reported into the ecsm dedicated registers: ? ecc error status and configurat ion for flash memory and sram ? ecc error reporting for flash memory ? ecc error reporting for sram ? ecc error injection for sram 1.5.11 peripheral bridge (pbridge) the pbridge implements the following features: ? duplicated periphery ? master access right per peripheral (per mast er: read access enable; write access enable) ? write buffering for peripherals ? checker applied on pbridge output toward periphery ? byte endianess swap capability 1.5.12 interrupt controller (intc) the intc provides priority-based preemptive scheduling of interrupt requests, suitable for stati cally scheduled hard real-time systems. table 2. platform memory access time summary ahb transfer data phase wait states description e200z4d instruction fetch 0 flash memory prefetch buffer hit (page hit) e200z4d instruction fetch 3 flash memory prefetch buffer miss (based on 4-cycle random flash array access time) e200z4d data read 0?1 sram read e200z4d data write 0 sram 32-bit write e200z4d data write 0 sram 64-bit writ e (executed as 2 x 32-bit writes) e200z4d data write 0?2 sram 8-,16-bit write (read-modify-write for ecc) e200z4d flash memory read 0 flash memory prefetch buffer hit (page hit) e200z4d flash memory read 3 flash memory prefetch buffer miss (at 120 mhz; includes 1 cycle of program flash memory controller arbitration)
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 12 for high-priority interrupt requests, the tim e from the assertion of the interrupt reque st from the peripher al to when the proc essor is executing the interrupt serv ice routine (isr) has been minimized. the intc provides a unique vector for each interrupt request source for quick determination of which isr needs to be ex ecuted. it also provides an ample number of priorities so tha t lower priority isrs do not dela y the execution of higher priority isrs. to allow the approp riate priorities for each source of interrupt request, the priority of each in terrupt request is software configurable. the intc supports the priority ceiling protocol for coherent accesse s. by providing a modifiable priority mask, the priority ca n be raised temporarily so that all tasks whic h share the resource can not preempt each other. the intc provides the following features: ? duplicated periphery ? unique 9-bit vector per interrupt source ? 16 priority levels with fixed ha rdware arbitratio n within priority levels for each interrupt source ? priority elevation for shared resource the intc is replicated for each processor. 1.5.13 system clocks and clock generation the following list summarizes the system clock and clock generation on this device: ? lock status continuously monitored by lock detect circuitry ? loss-of-clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter (for improved electromagnetic interfer ence performance and fewer external components required) ? programmable output clock divider of system clock ( ? 1, ? 2, ? 4, ? 8) ? pwm module and as many as three et imer modules running on an auxiliary clock independent from system clock (with max frequency 120 mhz) ? on-chip crystal oscillator with automatic level control ? dedicated internal 16 mhz internal rc oscillator for rapid start-up ? supports automated frequency trimming by hardwa re during device startup and by user application ? auxiliary clock domain for motor control periphery (pwm, etimer, ctu, adc, and swg) 1.5.14 frequency-modulated phase-locked loop (fmpll) each device has two fmplls. each fmpll allows the user to generate high speed system clocks starting from a minimum reference of 4 mhz input clock. further, the fmpll supports programmable frequency modulation of the system clock. the fmpll multiplication factor, output clock divider ratio are all software configurab le. the fmplls have the following major features: ? input frequency: 4?40 mhz continuous range (limited by the crystal oscillator) ? voltage controlled oscillator (vco) range: 256?512 mhz ? frequency modulation via software control to reduce and control emission peaks ? modulation depth 2% if centered or 0% to ?4% if downshifted via software control register ? modulation frequency: triangular modulation with 25 khz nominal rate ? option to switch m odulation on and off via software interface ? reduced frequency divider (rfd) for reduced frequency operation without re-lock ? 3 modes of operation ? bypass mode ? normal fmpll mode with crystal reference (default) ? normal fmpll mode with external reference ? lock monitor circuitry with lock status
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 13 ? loss-of-lock detection for reference and feedback clocks ? self-clocked mode (scm) operation ? on-chip loop filter ? auxiliary fmpll ? used for flexray due to precise symbol rate requirement by the protocol ? used for motor control periphery and connected ip (a/d digital interface ct u) to allow independent frequencies of operation for pwm and timers and jitter-free control ? option to enable/disable modulation to avoid protocol violation on jitter and/or potential unadjusted error in electric motor control loop ? allows to run motor control periphery at different (preci sely lower, equal or higher as required) frequency than the system to ensure higher resolution 1.5.15 main oscillator the main oscillator provides these features: ? input frequency range 4?40 mhz ? crystal input mode ? external reference clock (3.3 v) input mode ? fmpll reference 1.5.16 internal referenc e clock (rc) oscillator the architecture uses constant current charging of a capacitor. the voltage at the capacitor is compared to the stable bandgap reference voltage. the rc oscilla tor is the device safe clock. the rc oscillator provides these features: ? nominal frequency 16 mhz ? 5% variation over voltage and temperature after process trim ? clock output of the rc oscillator serves as system clock source in case loss of lo ck or loss of clock is detected by the fmpll ? rc oscillator is used as the default system clock during st artup and can be used as back-up input source of fmpll(s) in case xosc fails 1.5.17 clock, reset, power mode, an d test control modules (mc_cgm, mc_rgm, mc_pcu, and mc_me) these modules provide the following: ? clock gating and clock distribution control ? halt, stop mode control ? flexible configurable system and auxiliary clock dividers ? various execution modes ? reset, idle, test, safe ? various run modes with software selectable powered modules ? no stand-by mode implemented (no internal switchable power domains) 1.5.18 periodic interrupt timer module (pit) the pit module implements the following features:
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 14 ? 4 general purpose interrupt timers ? 32-bit counter resolution ? can be used for software tick or dma trigger operation 1.5.19 system timer module (stm) the stm implements th e following features: ? up-counter with 4 output compare registers the stm is replicated for each processor. 1.5.20 software watchdog timer (swt) this module implements the following features: ? fault tolerant output ? safe internal rc oscillator as reference clock ? windowed watchdog ? program flow control monitor with 16-bit pseudorandom key generation ? allows a high level of safety (sil3 monitor) the swt module is replicated for each processor. 1.5.21 fault collection and control unit (fccu) the fccu module has the following features: ? redundant collection of hardware checker results ? redundant collection of error information and la tch of faults from critical modules on the device ? collection of self-test results ? configurable and graded fault control ? internal reactions (no inte rnal reaction, irq, functional reset, de structive reset, or safe mode entered) ? external reaction (failure is reported to the extern al/surrounding system via configurable output pins) 1.5.22 system integration unit lite (siul) the siul controls mcu reset configurati on, pad configuration, external interr upt, general purpose i/o (gpio), internal peripheral multiplexing, and system reset operation. the reset conf iguration block contains the external pin boot configuration logic. the pad configuration block controls the static electrical characteristics of i/ o pins. the gpio block provides uniform and discrete input/output control of the i/o pins of the mcu. the siu provides the following features: ? centralized pad control on a per-pin basis ? pin function selection ? configurable weak pull-up/down ? configurable slew rate control (slow/medium/fast) ? hysteresis on gpio pins ? configurable automatic safe mode pad control ? input filtering for external interrupts
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 15 1.5.23 non-maskable interrupt (nmi) the non-maskable interrupt with de-glitching fi lter supports high-priority core exceptions. 1.5.24 boot assist module (bam) the bam is a block of read-only memory with hard-coded cont ent. the bam program is executed only if serial booting mode is selected via boot configuration pins. the bam provides the following features: ? enables booting via serial mode (can or lin/uart) ? supports programmable 64-bit password protection for serial boot mode ? supports serial bootloading of either classic powerpc book e co de (default) or freescale vle code ? automatic switch to serial boot mode if internal flash memory is blank or invalid 1.5.25 system status and configuration module (sscm) the sscm on this device f eatures the following: ? system configuration and status ? debug port status and debug port enable ? multiple boot code starting locations out of reset through implementation of search for valid reset configuration half word ? sets up the mmu to allow user boot code to execute as e ither classic powerpc book e c ode (default) or as freescale vle code out of flash memory ? triggering of device self-tests during reset phase of device boot 1.5.26 controller area network module (can) the can module is a communication controller implementing the can protocol according to bosch specification version 2.0b. although the can interface was designed to be used primarily as a vehicle networking bus, it is widely used in industrial and other transport applications due to its robust operation, time determinism, co st effectiveness, and optional redundant physical layer implementation. the can module provides the following features: ? full implementation of the can protocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0 to 8 bytes data length ? programmable bit rate as fast as 1mbit/s ? 32 message buffers of 0 to 8 bytes data length ? each message buffer configurable as receive or transmit buffer, all supporting standard and extended messages ? programmable loop-back mode supporting self-test operation ? 3 programmable mask registers ? programmable transmit-first scheme: lo west id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? independent of the transmission medium (an external transceiver is assumed) ? high immunity to emi
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 16 ? short latency time due to an arbitr ation scheme for high-priority messages ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort procedure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator cloc k to avoid fmpll jitter 1.5.27 flexray the flexray module provides the following features: ? full implementation of flexray protocol specification 2.1 rev. a ? 64 configurable message buffers can be handled ? dual channel or single channe l mode of operation, each as fast as 10 mbit/s data rate ? message buffers configurab le as transmit or receive ? message buffer size configurable ? message filtering for all message buffers ba sed on frame id, cycle count, and message id ? programmable acceptance filters for receive fifo ? message buffer header, status, and payloa d data stored in system memory (sram) ? internal flexray memories have error detection and correction 1.5.28 serial communicatio n interface module (uart) the uart module with dma support on this device features the following: ? uart features: ? full-duplex operation ? standard non return-to-ze ro (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate m odulus counter and 16-bit fractional ? 2 receiver wake-up methods ? lin features: ? autonomous lin frame handling ? message buffer to store identif ier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 17 ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 1.5.29 serial peripheral interface (spi) the spi modules provide a synchronous serial interface fo r communication between the pxs20 and external devices. a spi module provides these features: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? as many as 8 chip select lines availabl e, depending on package and pin multiplexing ? 4 clock and transfer attributes registers ? chip select strobe available as alternate function on one of the chip select pins for de-glitching ? fifos for buffering as many as 5 tran sfers on the transm it and receive side ? queueing operation possible through use of the edma ? general purpose i/o functionality on pins when not used for spi 1.5.30 pulse width modulator (pwm) the pwm module contains four pwm channels, each of which is configured to control a single half-bridge power stage. two modules are included on 257 mapbga devices; on the 144 lqfp p ackage, only one module is present. additionally, four fault input channels are provided per pwm module. this pwm is capable of controlling most motor types, including: ? ac induction motors (acim) ? permanent magnet ac motors (pmac) ? brushless (bldc) and brush dc motors (bdc) ? switched (srm) and variable reluctance motors (vrm) ? stepper motors a pwm module implements the following features: ? 16 bits of resolution for center, ed ge aligned, and asymmetrical pwms
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 18 ? maximum operating frequency as high as 120 mhz ? clock source not modulated and independent from system clock (generated via secondary fmpll) ? fine granularity control for enhanced resolution of the pwm period ? pwm outputs can operate as complementary pairs or independent channels ? ability to accept signed nu mbers for pwm generation ? independent control of both edges of each pwm output ? synchronization to external hardware or other pwm supported ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half cycle reload capability ? multiple adc trigger events can be generated per pwm cycle via hardware ? fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? independent top and bottom deadtime insertion ? each complementary pair can operate with its own pwm frequency and deadtime values ? individual software control for each pwm output ? all outputs can be forced to a value simultaneously ? pwmx pin can optionally output a third signal from each channel ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation can be used for input capture functions ? enhanced dual edge capture functionality ? option to supply the source for each complementar y pwm signal pair from any of the following: ? external digital pin ? internal timer channel ? external adc input, taking into account values set in adc high- and low-limit registers ? dma support 1.5.31 etimer module the pxs20 provides three etimer modules on the 257 mapbga device, and two etimer modules on the 144 lqfp package. six 16-bit general purpose up/down timer/counters per module are implemented with the following features: ? maximum clock frequency of 120 mhz ? individual channel capability ? input capture trigger ? output compare ? double buffer (to capture rising edge and falling edge) ? separate prescaler for each counter ? selectable clock source ? 0?100% pulse measurement ? rotation direction flag (quad decoder mode) ? maximum count rate ? equals peripheral clock divided by 2 for external event counting ? equals peripheral clock for internal clock counting ? cascadeable counters ? programmable count modulo
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 19 ? quadrature decode capabilities ? counters can share available input pins ? count once or repeatedly ? preloadable counters ? pins available as gpio when timer functionality not in use ? dma support 1.5.32 sine wave generator (swg) a digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver ). ? frequency range from 1 khz to 50 khz ? sine wave amplitude from 0.47 v to 2.26 v 1.5.33 analog-to-digital converter module (adc) the adc module features include: analog part: ? 2 on-chip adcs ? 12-bit resolution sar architecture ? a/d channels: 9 external, 3 internal and 4 shared with other a/d (total 16 channels) ? one channel dedicated to each t-sensor to en able temperature readi ng during application ? separated reference for each adc ? shared analog supply voltage for both adcs ? one sample and hold unit per adc ? adjustable sampling and conversion time digital part: ? 4 analog watchdogs comparing adc results against predefined levels (low, high, range) before results are stored in the appropriate adc result location ? 2 modes of operation: motor control mode or regular mode ? regular mode features ? register based interface with the cp u: one result register per channel ? adc state machine managing three request flows: regul ar command, hardware inj ected command, software injected command ? selectable priority between softwa re and hardware injected commands ? 4 analog watchdogs comparing adc results ag ainst predefined levels (low, high, range) ? dma compatible interface ? motor control mode features ? triggered mode only ? 4 independent result queues (1 ? 16 entries, 2 ? 8 entries, 1 ? 4 entries) ? result alignment circuitry (left justified; right justified) ? 32-bit read mode allows to have channel id on one of the 16-bit parts ? dma compatible interfaces ? built-in self-test features triggered by software
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 20 1.5.34 junction temperature sensor the junction temperature sensor provides a value via an adc channel that can be us ed by software to calculate the device junction temperature. the key parameters of the junction temperature sensor include: ? nominal temperature ra nge from ?40 to 150 c ? software temperature alarm via analog adc compar ator possible 1.5.35 cross triggering unit (ctu) the adc cross triggering unit allows automatic generation of adc conversion requests on user selected conditions without cpu load during the pwm period and with minimized cpu load for dynamic configuration. the ctu implements the following features: ? cross triggering between adc, pwm, etimer, and external pins ? double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers ? maximum operating frequency less than or equal to 120 mhz ? trigger generation unit configurable in sequential mode or in triggered mode ? trigger delay unit to compensate the delay of external low pass filter ? double buffered global trigger unit allowing etimer synchronization and/or adc command generation ? double buffered adc command list pointers to minimize adc-trigger unit update ? double buffered adc conversion command li st with as many as 24 adc commands ? each trigger capable of generating consecutive commands ? adc conversion command allows control of adc chan nel from each adc, single or synchronous sampling, independent result queue selection ? dma support with safety features 1.5.36 cyclic redundancy checker (crc) unit the crc module is a configurable multiple data flow unit to compute crc signatures on data written to its input register. the crc unit has the following features: ? 3 sets of registers to allow 3 concur rent contexts with possib ly different crc computations , each with a selectable polynomial and seed ? computes 16- or 32-bit wide crc on the fly (single-cycle computation) and stores result in internal register. the following standard crc po lynomials are implemented: ? x 16 + x 12 + x 5 + 1 [16-bit crc-ccitt] ? x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 [32-bit crc-ethernet(32)] ? key engine to be coupled with comm unication periphery where crc application is added to allow implementation of safe communication protocol ? offloads core from cycle-consuming crc and helps checking configuration signa ture for safe st art-up or periodic procedures ? crc unit connected as peripheral bus on internal peripheral bus ? dma support 1.5.37 redundancy control and checker unit (rccu) the rccu checks all outputs of the sphere of replication (addre sses, data, control signals). it has the following features:
introduction pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 21 ? duplicated module to guarantee highest poss ible diagnostic coverage (check of checker) ? multiple times replicated ips are used as checkers on the sor outputs 1.5.38 voltage regulator / power management unit (pmu) the on-chip voltage regulator module provides the following features: ? single external rail required ? single high supply required: nominal 3.3 v for packaged option ? packaged option requires extern al ballast transistor due to reduced diss ipation capacity at high temperature but can use embedded transistor if power dissipation is maintained within package dissipation capacity (lower frequency of operation) ? all i/os are at same voltage as external supply (3.3 v nominal) ? duplicated low-voltage detectors (lvd) to guarantee proper operation at all stages (res et, configuration, normal operation) and, to maximize safety coverage, one lvd can be tested while the other operates (on-line self-testing feature) 1.5.39 built-in self-test (bist) capability this device includes the following protection against latent faults: ? boot-time memory built-in self-test (mbist) ? boot-time scan-based logic built-in self-test (lbist) ? run-time adc built-in self-test (bist) ? run-time built-in self test of lvds 1.5.40 ieee 1149.1 jtag controller (jtagc) the jtagc block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. all data input to and output from the jtagc block is communicated in serial format. the jtagc block is compliant with the ieee standard. the jtag controller provides the following features: ? ieee test access port (tap) interface with 5 pins: ?tdi ?tms ?tck ?tdo ?jcomp ? selectable modes of operation include jt agc/debug or normal system operation ? 5-bit instruction register that supports the following ieee 1149.1-2001 defined instructions: ?bypass ? idcode ?extest ?sample ? sample/preload ? 3 test data registers: a bypass register, a boundary scan register, and a device identifica tion register. the size of the boundary scan register is parameterized to suppo rt a variety of boundary scan chain lengths. ? tap controller state machine that cont rols the operation of the data register s, instruction regist er and associated circuitry
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice introduction freescale semiconductor 22 1.5.41 nexus port controller (npc) the npc module provides real-time development support capabilities for this device in compliance with the ieee-isto 5001-2008 standard. this development support is supplied for mcus without requiring external address and data pins for internal visibility. the npc block interfaces to the host pro cessor and internal buses to provide de velopment support as per the ieee-isto 5001-2008 class 3+, including selected features from class 4 standard. the development support provided includes program trace, data trace, watchpoint trace, owners hip trace, run-time access to the mcus internal memory map and access to the power architecture ? internal registers during ha lt. the nexus interface also supports a jtag only mode using only the jtag pins. the following features are implemented: ? full and reduced port modes ? mcko (message clock out) pin ? 4 or 12 mdo (message data out) pins 1 ?2 mseo (message start/end out) pins ?evto (event out) pin ? auxiliary input port ?evti (event in) pin ? 5-pin jtag port (jcomp, tdi, tdo, tms, and tck) ? supports jtag mode ? host processor (e200) deve lopment support features ? data trace via data write messaging (dwm) and data read messaging (drm). this allows the development tool to trace reads or writes, or both, to selected internal memory resources. ? ownership trace via ownership trace me ssaging (otm). otm facilitates owne rship trace by prov iding visibility of which process id or operating sy stem task is activated. an ownershi p trace message is transmitted when a new process/task is activated, allowing de velopment tools to trace ownership flow. ? program trace via branch trace messagi ng (btm). branch trace messaging disp lays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the deve lopment tool to interpolate what transpires between the discontinuities. thus, static code may be traced. ? watchpoint messaging (wpm ) via the auxiliary port ? watchpoint trigger enable of pr ogram and/or data trace messaging ? data tracing of instructi on fetches via private opcodes 1. 4 mdo pins on 144 lq fp package, 12 mdo pins on 257 mapbga package.
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 23 2 package pinouts and signal descriptions 2.1 package pinouts figure 3 shows the pxs20 in the 144 lqfp package. figure 3. pxs20 144 lqfp pinout (top view) figure 4 shows the pxs20 in the 257 mapbga package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi a[6] d[1] f[4] f[5] vdd_hv_io vss_hv_io f[6] mdo0 a[7] c[4] a[8] c[5] a[5] c[7] vdd_hv_reg_0 vss_lv_cor vdd_lv_cor f[7] f[8] vdd_hv_io vss_hv_io f[9] f[10] f[11] d[9] vdd_hv_osc vss_hv_osc xtal extal reset d[8] d[5] d[6] vss_lv_pll0_pll1 vdd_lv_pll0_pll1 a[4] vpp_test f[12] d[14] g[3] c[14] g[2] c[13] g[4] d[12] g[6] vdd_hv_fla vss_hv_fla vdd_hv_reg_1 vss_lv_cor vdd_lv_cor a[3] vdd_hv_io vss_hv_io b[4] tck tms b[5] g[5] a[2] g[7] c[12] g[8] c[11] g[9] d[11] g[10] d[10] g[11] a[1] a[0] d[7] fccu_f[0] vdd_lv_cor vss_lv_cor c[1] e[4] b[7] e[5] c[2] e[6] b[8] e[7] e[2] vdd_hv_adr0 vss_hv_adr0 b[9] b[10] b[11] b[12] vdd_hv_adr1 vss_hv_adr1 vdd_hv_adv vss_hv_adv b[13] e[9] b[15] e[10] b[14] e[11] c[0] e[12] e[0] bctrl vdd_lv_cor vss_lv_cor vdd_hv_pmu a[15] a[14] c[6] fccu_f[1] d[2] f[3] b[6] vss_lv_cor a[13] vdd_lv_cor a[9] f[0] vss_lv_cor vdd_lv_cor vdd_hv_reg_2 d[4] d[3] vss_hv_io vdd_hv_io d[0] c[15] jcomp a[12] e[15] a[11] e[14] a[10] e[13] b[3] f[14] b[2] f[15] f[13] c[10] b[1] b[0] 144 lqfp package
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 24 figure 4. pxs20 257 mapbga pinout (top view) table 3 and table 4 provide the pin function summaries for the 144-pin and 257-pin packages, respectively, listing all the signals multiplexed to each pin. 1234567891011121314151617 a v ss v ss v dd_hv h[2] h[0] g[14] d[3] c[15] v dd_hv a[12] h[10] h[14] a[10] b[2] c[10] v ss v ss b v ss v ss b[6] a[14] f[3] a[9] d[4] d[0] v ss h[12] e[15] e[14] b[3] f[13] b[0] v dd_hv v ss c v dd_hv nc 1 1 nc = not connected (the pin is physically not connected to anything on the device) v ss fccu_ f[1] d[2] a[13] v dd_hv v dd_hv i[0] jcomp h[11] i[1] f[14] b[1] v ss a[4] f[12] d f[5] f[4] a[15] c[6] v ss v dd_lv f[0] v dd_hv v ss nc a[11] e[13] f[15] v dd_hv v pp _test d[14] g[3] e mdo0 f[6] d[1] nmi nc c[14] g[2] i[3] f h[1] g[12] a[7] a[8] v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv nc c[13] i[2] g[4] g h[3] v dd_hv c[5] a[6] v dd_lv v ss v ss v ss v ss v ss v dd_lv d[12] h[13] h[9] g[6] h g[13] v ss c[4] a[5] v dd_lv v ss v ss v ss v ss v ss v dd_lv v ss v dd_hv v dd_hv h[6] j f[7] g[15] v dd_hv v dd_hv v dd_lv v ss v ss v ss v ss v ss v dd_lv v dd_lv v dd_hv v ss h[15] k f[9] f[8] see note 2 2 pin k3 is nc on cut1 and rdy on cut2/3. c[7] v dd_lv v ss v ss v ss v ss v ss v dd_lv nc h[8] h[7] a[3] l f[10] f[11] d[9] nc v dd_lv v ss v ss v ss v ss v ss v dd_lv nc tck h[4] b[4] m v dd_hv v dd_hv d[8] nc v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv v dd_lv c[11] b[5] tms h[5] n xtal v ss d[5] v ss_lv_ pll nc c[12] a[2] g[5] p v ss reset d[6] v dd_lv_ pll v dd_lv v ss b[8] nc v ss v dd_hv b[14] v dd_lv v ss v dd_hv g[10] g[8] g[7] r extal fccu _f[0] v ss d[7] b[7] e[6] v refp_ hv_ad0 b[10] v refp_ hv_ad1 b[13] b[15] c[0] bctrl a[1] v ss d[11] g[9] t v ss v dd_hv nc c[1] e[5] e[7] v refn_ hv_ad0 b[11] v refn_ hv_ad1 e[9] e[10] e[12] e[0] a[0] d[10] v dd_hv v ss u v ss v ss nc e[4] c[2] e[2] b[9] b[12] v dd_hv v ss e[11] nc nc v dd_hv g[11] v ss v ss 1234567891011121314151617
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 25 table 3. 144 lqfp pin function summary pin # port/function peripheral ou tput function input function 1nmi ? 2 a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] 3 d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx 4 f[4] siul gpio[84] gpio[84] npc mdo[3] ? 5 f[5] siul gpio[85] gpio[85] npc mdo[2] ? 6v dd_hv_io ? 7v ss_hv_io ? 8 f[6] siul gpio[86] gpio[86] npc mdo[1] ? 9mdo0 ? 10 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] 11 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] 12 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] 13 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23]
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 26 14 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] 15 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin 16 v dd_hv_reg_0 ? 17 v ss_lv_cor ? 18 v dd_lv_cor ? 19 f[7] siul gpio[87] gpio[87] npc mcko ? 20 f[8] siul gpio[88] gpio[88] npc mseo[1] ? 21 v dd_hv_io ? 22 v ss_hv_io ? 23 f[9] siul gpio[89] gpio[89] npc mseo[0] ? 24 f[10] siul gpio[90] gpio[90] npc evto ? 25 f[11] siul gpio[91] gpio[91] npc evti ? 26 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? 27 v dd_hv_osc ? 28 v ss_hv_osc ? 29 xtalin ? 30 xtalout ? 31 reset ? table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 27 32 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] 33 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] 34 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] 35 v ss_lv_pll0_pll1 ? 36 v dd_lv_pll0_pll1 ? 37 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? 38 fccu_f[0] fccu f[0] f[0] 39 v dd_lv_cor ? 40 v ss_lv_cor ? 41 c[1] siul ? gpio[33] adc_0 ? an[2] 42 e[4] siul ? gpio[68] adc_0 ? an[7] 43 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] 44 e[5] siul ? gpio[69] adc_0 ? an[8] 45 c[2] siul ? gpio[34] adc_0 ? an[3] 46 e[6] siul ? gpio[70] adc_0 ? an[4] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 28 47 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] 48 e[7] siul ? gpio[71] adc_0 ? an[6] 49 e[2] siul ? gpio[66] adc_0 ? an[5] 50 v dd_hv_adr0 ? 51 v ss_hv_adr0 ? 52 b[9] siul ? gpio[25] adc_0 adc_1 ? an[11] 53 b[10] siul ? gpio[26] adc_0 adc_1 ? an[12] 54 b[11] siul ? gpio[27] adc_0 adc_1 ? an[13] 55 b[12] siul ? gpio[28] adc_0 adc_1 ? an[14] 56 v dd_hv_adr1 ? 57 v ss_hv_adr1 ? 58 v dd_hv_adv ? 59 v ss_hv_adv ? 60 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] 61 e[9] siul ? gpio[73] adc_1 ? an[7] 62 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] 63 e[10] siul ? gpio[74] adc_1 ? an[8] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 29 64 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] 65 e[11] siul ? gpio[75] adc_1 ? an[4] 66 c[0] siul ? gpio[32] adc_1 ? an[3] 67 e[12] siul ? gpio[76] adc_1 ? an[6] 68 e[0] siul ? gpio[64] adc_1 ? an[5] 69 bctrl ? 70 v dd_lv_cor ? 71 v ss_lv_cor ? 72 v dd_hv_pmu ? 73 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] 74 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] 75 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] 76 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] 77 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 30 78 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] 79 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] 80 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? 81 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] 82 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? 83 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] 84 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] 85 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? 86 b[5] siul gpio[21] gpio[21] jtagc ? tdi 87 tms ? 88 tck ? table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 31 89 b[4] siul gpio[20] gpio[20] jtagc tdo ? 90 v ss_hv_io ? 91 v dd_hv_io ? 92 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] 93 v dd_lv_cor ? 94 v ss_lv_cor ? 95 v dd_hv_reg_1 ? 96 v ss_hv_fla ? 97 v dd_hv_fla ? 98 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] 99 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd 100 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] 101 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 102 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? 103 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 32 104 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] 105 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] 106 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] 107 v pp_test 1 ? 108 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] 109 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] 110 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] 111 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] 112 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 33 113 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd 114 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] 115 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? 116 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd 117 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] 118 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] 119 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] 120 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] 121 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 34 122 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] 123 jcomp ? ? jcomp 124 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync 125 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] 126 v dd_hv_io ? 127 v ss_hv_io ? 128 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] 129 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] 130 v dd_hv_reg_2 ? 131 v dd_lv_cor ? 132 v ss_lv_cor ? 133 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 35 134 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] 135 v dd_lv_cor ? 136 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] 137 v ss_lv_cor ? 138 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] 139 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? 140 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx 141 fccu_f[1] fccu f[1] f[1] 142 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] 143 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 36 144 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] 1 v pp_test should always be tied to ground (v ss ) for normal operations. table 4. 257 mapbga pin function summary pin # port/function peripheral ou tput function input function a1 v ss_hv_io_ring ? a2 v ss_hv_io_ring ? a3 v dd_hv_io_ring ? a4 h[2] siul gpio[114] gpio[114] npc mdo[5] ? a5 h[0] siul gpio[112] gpio[112] npc mdo[7] ? a6 g[14] siul gpio[110] gpio[110] npc mdo[9] ? a7 d[3] siul gpio[51] gpio[51] flexray cb_tx ? etimer_1 etc[4] etc[4] flexpwm_0 a[3] a[3] a8 c[15] siul gpio[47] gpio[47] flexray ca_tr_en ? etimer_1 etc[0] etc[0] flexpwm_0 a[1] a[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync a9 v dd_hv_io_ring ? a10 a[12] siul gpio[12] gpio[12] dspi_2 sout ? flexpwm_0 a[2] a[2] flexpwm_0 b[2] b[2] siul ? eirq[11] table 3. 144 lqfp pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 37 a11 h[10] siul gpio[122] gpio[122] flexpwm_1 x[2] x[2] etimer_2 etc[2] etc[2] a12 h[14] siul gpio[126] gpio[126] flexpwm_1 a[3] a[3] etimer_2 etc[4] etc[4] a13 a[10] siul gpio[10] gpio[10] dspi_2 cs0 cs0 flexpwm_0 b[0] b[0] flexpwm_0 x[2] x[2] siul ? eirq[9] a14 b[2] siul gpio[18] gpio[18] linflexd_0 txd ? sscm debug[2] ? siul ? eirq[17] a15 c[10] siul gpio[42] gpio[42] dspi_2 cs2 ? flexpwm_0 a[3] a[3] flexpwm_0 ? fault[1] a16 v ss_hv_io_ring ? a17 v ss_hv_io_ring ? b1 v ss_hv_io_ring ? b2 v ss_hv_io_ring ? b3 b[6] siul gpio[22] gpio[22] mc_cgm clk_out ? dspi_2 cs2 ? siul ? eirq[18] b4 a[14] siul gpio[14] gpio[14] flexcan_1 txd ? etimer_1 etc[4] etc[4] siul ? eirq[13] b5 f[3] siul gpio[83] gpio[83] dspi_0 cs6 ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 38 b6 a[9] siul gpio[9] gpio[9] dspi_2 cs1 ? flexpwm_0 b[3] b[3] flexpwm_0 ? fault[0] b7 d[4] siul gpio[52] gpio[52] flexray cb_tr_en ? etimer_1 etc[5] etc[5] flexpwm_0 b[3] b[3] b8 d[0] siul gpio[48] gpio[48] flexray ca_tx ? etimer_1 etc[1] etc[1] flexpwm_0 b[1] b[1] b9 v ss_hv_io_ring ? b10 h[12] siul gpio[124] gpio[124] flexpwm_1 b[2] b[2] b11 e[15] siul gpio[79] gpio[79] dspi_0 cs1 ? siul ? eirq[27] b12 e[14] siul gpio[78] gpio[78] etimer_1 etc[5] etc[5] siul ? eirq[26] b13 b[3] siul gpio[19] gpio[19] sscm debug[3] ? linflexd_0 ? rxd b14 f[13] siul gpio[93] gpio[93] etimer_1 etc[4] etc[4] siul ? eirq[31] b15 b[0] siul gpio[16] gpio[16] flexcan_0 txd ? etimer_1 etc[2] etc[2] sscm debug[0] ? siul ? eirq[15] b16 v dd_hv_io_ring ? b17 v ss_hv_io_ring ? c1 v dd_hv_io_ring ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 39 c2 not connected ? c3 v ss_hv_io_ring ? c4 fccu_f[1] fccu f[1] f[1] c5 d[2] siul gpio[50] gpio[50] etimer_1 etc[3] etc[3] flexpwm_0 x[3] x[3] flexray ? cb_rx c6 a[13] siul gpio[13] gpio[13] flexpwm_0 b[2] b[2] dspi_2 ? sin flexpwm_0 ? fault[0] siul ? eirq[12] c7 v dd_hv_reg_2 ? c8 v dd_hv_reg_2 ? c9 i[0] siul gpio[128] gpio[128] etimer_2 etc[0] etc[0] dspi_0 cs4 ? flexpwm_1 ? fault[0] c10 jcomp ? ? jcomp c11 h[11] siul gpio[123] gpio[123] flexpwm_1 a[2] a[2] c12 i[1] siul gpio[129] gpio[129] etimer_2 etc[1] etc[1] dspi_0 cs5 ? flexpwm_1 ? fault[1] c13 f[14] siul gpio[94] gpio[94] linflexd_1 txd ? c14 b[1] siul gpio[17] gpio[17] etimer_1 etc[3] etc[3] sscm debug[1] ? flexcan_0 ? rxd flexcan_1 ? rxd siul ? eirq[16] c15 v ss_hv_io_ring ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 40 c16 a[4] siul gpio[4] gpio[4] etimer_1 etc[0] etc[0] dspi_2 cs1 ? etimer_0 etc[4] etc[4] mc_rgm ? fab siul ? eirq[4] c17 f[12] siul gpio[92] gpio[92] etimer_1 etc[3] etc[3] siul ? eirq[30] d1 f[5] siul gpio[85] gpio[85] npc mdo[2] ? d2 f[4] siul gpio[84] gpio[84] npc mdo[3] ? d3 a[15] siul gpio[15] gpio[15] etimer_1 etc[5] etc[5] flexcan_1 ? rxd flexcan_0 ? rxd siul ? eirq[14] d4 c[6] siul gpio[38] gpio[38] dspi_0 sout ? flexpwm_0 b[1] b[1] sscm debug[6] ? siul ? eirq[24] d5 v ss_lv_core_ring ? d6 v dd_lv_core_ring ? d7 f[0] siul gpio[80] gpio[80] flexpwm_0 a[1] a[1] etimer_0 ? etc[2] siul ? eirq[28] d8 v dd_hv_io_ring ? d9 v ss_hv_io_ring ? d10 not connected ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 41 d11 a[11] siul gpio[11] gpio[11] dspi_2 sck sck flexpwm_0 a[0] a[0] flexpwm_0 a[2] a[2] siul ? eirq[10] d12 e[13] siul gpio[77] gpio[77] etimer_0 etc[5] etc[5] dspi_2 cs3 ? siul ? eirq[25] d13 f[15] siul gpio[95] gpio[95] linflexd_1 ? rxd d14 v dd_hv_io_ring ? d15 v pp_test 1 ? d16 d[14] siul gpio[62] gpio[62] flexpwm_0 b[1] b[1] etimer_0 ? etc[3] d17 g[3] siul gpio[99] gpio[99] flexpwm_0 a[2] a[2] etimer_0 ? etc[4] e1 mdo0 ? e2 f[6] siul gpio[86] gpio[86] npc mdo[1] ? e3 d[1] siul gpio[49] gpio[49] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? flexray ? ca_rx e4 nmi ? e14 not connected ? e15 c[14] siul gpio[46] gpio[46] etimer_1 etc[2] etc[2] ctu_0 ext_tgr ? e16 g[2] siul gpio[98] gpio[98] flexpwm_0 x[2] x[2] dspi_1 cs1 ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 42 e17 i[3] siul gpio[131] gpio[131] etimer_2 etc[3] etc[3] dspi_0 cs7 ? ctu_0 ext_tgr ? flexpwm_1 ? fault[3] f1 h[1] siul gpio[113] gpio[113] npc mdo[6] ? f2 g[12] siul gpio[108] gpio[108] npc mdo[11] ? f3 a[7] siul gpio[7] gpio[7] dspi_1 sout ? siul ? eirq[7] f4 a[8] siul gpio[8] gpio[8] dspi_1 ? sin siul ? eirq[8] f6 v dd_lv_core_ring ? f7 v dd_lv_core_ring ? f8 v dd_lv_core_ring ? f9 v dd_lv_core_ring ? f10 v dd_lv_core_ring ? f11 v dd_lv_core_ring ? f12 v dd_lv_core_ring ? f14 not connected ? f15 c[13] siul gpio[45] gpio[45] etimer_1 etc[1] etc[1] ctu_0 ? ext_in flexpwm_0 ? ext_sync f16 i[2] siul gpio[130] gpio[130] etimer_2 etc[2] etc[2] dspi_0 cs6 ? flexpwm_1 ? fault[2] f17 g[4] siul gpio[100] gpio[100] flexpwm_0 b[2] b[2] etimer_0 ? etc[5] table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 43 g1 h[3] siul gpio[115] gpio[115] npc mdo[4] ? g2 v dd_hv_io_ring ? g3 c[5] siul gpio[37] gpio[37] dspi_0 sck sck sscm debug[5] ? flexpwm_0 ? fault[3] siul ? eirq[23] g4 a[6] siul gpio[6] gpio[6] dspi_1 sck sck siul ? eirq[6] g6 v dd_lv_core_ring ? g7 v ss_lv_core_ring ? g8 v ss_lv_core_ring ? g9 v ss_lv_core_ring ? g10 v ss_lv_core_ring ? g11 v ss_lv_core_ring ? g12 v dd_lv_core_ring ? g14 d[12] siul gpio[60] gpio[60] flexpwm_0 x[1] x[1] linflexd_1 ? rxd g15 h[13] siul gpio[125] gpio[125] flexpwm_1 x[3] x[3] etimer_2 etc[3] etc[3] g16 h[9] siul gpio[121] gpio[121] flexpwm_1 b[1] b[1] dspi_0 cs7 ? g17 g[6] siul gpio[102] gpio[102] flexpwm_0 a[3] a[3] h1 g[13] siul gpio[109] gpio[109] npc mdo[10] ? h2 v ss_hv_io_ring ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 44 h3 c[4] siul gpio[36] gpio[36] dspi_0 cs0 cs0 flexpwm_0 x[1] x[1] sscm debug[4] ? siul ? eirq[22] h4 a[5] siul gpio[5] gpio[5] dspi_1 cs0 cs0 etimer_1 etc[5] etc[5] dspi_0 cs7 ? siul ? eirq[5] h6 v dd_lv ? h7 v ss_lv ? h8 v ss_lv ? h9 v ss_lv ? h10 v ss_lv ? h11 v ss_lv ? h12 v dd_lv ? h14 v ss_lv ? h15 v dd_hv_reg_1 ? h16 v dd_hv_fla ? h17 h[6] siul gpio[118] gpio[118] flexpwm_1 b[0] b[0] dspi_0 cs5 ? j1 f[7] siul gpio[87] gpio[87] npc mcko ? j2 g[15] siul gpio[111] gpio[111] npc mdo[8] ? j3 v dd_hv_reg_0 ? j4 v dd_hv_reg_0 ? j6 v dd_lv ? j7 v ss_lv ? j8 v ss_lv ? j9 v ss_lv ? j10 v ss_lv ? j11 v ss_lv ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 45 j12 v dd_lv ? j14 v dd_lv ? j15 v dd_hv_reg_1 ? j16 v ss_hv_fla ? j17 h[15] siul gpio[127] gpio[127] flexpwm_1 b[3] b[3] etimer_2 etc[5] etc[5] k1 f[9] siul gpio[89] gpio[89] npc mseo[0] ? k2 f[8] siul gpio[88] gpio[88] npc mseo[1] ? k3 (cut1) not connected ? k3 (cut2) rdy npc rdy ? siul gpio[132] gpio[132] k4 c[7] siul gpio[39] gpio[39] flexpwm_0 a[1] a[1] sscm debug[7] ? dspi_0 ? sin k6 v dd_lv ? k7 v ss_lv ? k8 v ss_lv ? k9 v ss_lv ? k10 v ss_lv ? k11 v ss_lv ? k12 v dd_lv ? k14 not connected ? k15 h[8] siul gpio[120] gpio[120] flexpwm_1 a[1] a[1] dspi_0 cs6 ? k16 h[7] siul gpio[119] gpio[119] flexpwm_1 x[1] x[1] etimer_2 etc[1] etc[1] table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 46 k17 a[3] siul gpio[3] gpio[3] etimer_0 etc[3] etc[3] dspi_2 cs0 cs0 flexpwm_0 b[3] b[3] mc_rgm ? abs[2] siul ? eirq[3] l1 f[10] siul gpio[90] gpio[90] npc evto ? l2 f[11] siul gpio[91] gpio[91] npc evti ? l3 d[9] siul gpio[57] gpio[57] flexpwm_0 x[0] x[0] linflexd_1 txd ? l4 not connected ? l6 v dd_lv ? l7 v ss_lv ? l8 v ss_lv ? l9 v ss_lv ? l10 v ss_lv ? l11 v ss_lv ? l12 v dd_lv ? l14 not connected ? l15 tck ? l16 h[4] siul gpio[116] gpio[116] flexpwm_1 x[0] x[0] etimer_2 etc[0] etc[0] l17 b[4] siul gpio[20] gpio[20] jtagc tdo ? m1 v dd_hv_osc ? m2 v dd_hv_io_ring ? m3 d[8] siul gpio[56] gpio[56] dspi_1 cs2 ? etimer_1 etc[4] etc[4] dspi_0 cs5 ? flexpwm_0 ? fault[3] table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 47 m4 not connected ? m6 v dd_lv ? m7 v dd_lv ? m8 v dd_lv ? m9 v dd_lv ? m10 v dd_lv ? m11 v dd_lv ? m12 v dd_lv ? m14 c[11] siul gpio[43] gpio[43] etimer_0 etc[4] etc[4] dspi_2 cs2 ? m15 b[5] siul gpio[21] gpio[21] jtagc ? tdi m16 tms ? m17 h[5] siul gpio[117] gpio[117] flexpwm_1 a[0] a[0] dspi_0 cs4 ? n1 xtalin ? n2 v ss_hv_io_ring ? n3 d[5] siul gpio[53] gpio[53] dspi_0 cs3 ? flexpwm_0 ? fault[2] n4 v ss_lv_pll0_pll1 ? n14 not connected ? n15 c[12] siul gpio[44] gpio[44] etimer_0 etc[5] etc[5] dspi_2 cs3 ? n16 a[2] siul gpio[2] gpio[2] etimer_0 etc[2] etc[2] flexpwm_0 a[3] a[3] dspi_2 ? sin mc_rgm ? abs[0] siul ? eirq[2] table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 48 n17 g[5] siul gpio[101] gpio[101] flexpwm_0 x[3] x[3] dspi_2 cs3 ? p1 v ss_hv_osc ? p2 reset ? p3 d[6] siul gpio[54] gpio[54] dspi_0 cs2 ? flexpwm_0 x[3] x[3] flexpwm_0 ? fault[1] p4 v dd_lv_pll0_pll1 ? p5 v dd_lv_core_ring ? p6 v ss_lv_core_ring ? p7 b[8] siul ? gpio[24] etimer_0 ? etc[5] adc_0 ? an[1] p8 not connected ? p9 v ss_hv_io_ring ? p10 v dd_hv_io_ring ? p11 b[14] siul ? gpio[30] etimer_0 ? etc[4] siul ? eirq[19] adc_1 ? an[1] p12 v dd_lv_core_ring ? p13 v ss_lv_core_ring ? p14 v dd_hv_io_ring ? p15 g[10] siul gpio[106] gpio[106] flexray dbg2 ? dspi_2 cs3 ? flexpwm_0 ? fault[2] p16 g[8] siul gpio[104] gpio[104] flexray dbg0 ? dspi_0 cs1 ? flexpwm_0 ? fault[0] siul ? eirq[21] table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 49 p17 g[7] siul gpio[103] gpio[103] flexpwm_0 b[3] b[3] r1 xtalout ? r2 fccu_f[0] fccu f[0] f[0] r3 v ss_hv_io_ring ? r4 d[7] siul gpio[55] gpio[55] dspi_1 cs3 ? dspi_0 cs4 ? swg analog output ? r5 b[7] siul ? gpio[23] linflexd_0 ? rxd adc_0 ? an[0] r6 e[6] siul ? gpio[70] adc_0 ? an[4] r7 v dd_hv_adr0 ? r8 b[10] siul ? gpio[26] adc_0 adc_1 ? an[12] r9 v dd_hv_adr1 ? r10 b[13] siul ? gpio[29] linflexd_1 ? rxd adc_1 ? an[0] r11 b[15] siul ? gpio[31] siul ? eirq[20] adc_1 ? an[2] r12 c[0] siul ? gpio[32] adc_1 ? an[3] r13 bctrl ? r14 a[1] siul gpio[1] gpio[1] etimer_0 etc[1] etc[1] dspi_2 sout ? siul ? eirq[1] r15 v ss_hv_io_ring ? table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 50 r16 d[11] siul gpio[59] gpio[59] flexpwm_0 b[0] b[0] etimer_0 ? etc[1] r17 g[9] siul gpio[105] gpio[105] flexray dbg1 ? dspi_1 cs1 ? flexpwm_0 ? fault[1] siul ? eirq[29] t1 v ss_hv_io_ring ? t2 v dd_hv_io_ring ? t3 not connected ? t4 c[1] siul ? gpio[33] adc_0 ? an[2] t5 e[5] siul ? gpio[69] adc_0 ? an[8] t6 e[7] siul ? gpio[71] adc_0 ? an[6] t7 v ss_hv_adr0 ? t8 b[11] siul ? gpio[27] adc_0 adc_1 ? an[13] t9 v ss_hv_adr1 ? t10 e[9] siul ? gpio[73] adc_1 ? an[7] t11 e[10] siul ? gpio[74] adc_1 ? an[8] t12 e[12] siul ? gpio[76] adc_1 ? an[6] t13 e[0] siul ? gpio[64] adc_1 ? an[5] t14 a[0] siul gpio[0] gpio[0] etimer_0 etc[0] etc[0] dspi_2 sck sck siul ? eirq[0] table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 51 t15 d[10] siul gpio[58] gpio[58] flexpwm_0 a[0] a[0] etimer_0 ? etc[0] t16 v dd_hv_io_ring ? t17 v ss_hv_io_ring ? u1 v ss_hv_io_ring ? u2 v ss_hv_io_ring ? u3 not connected ? u4 e[4] siul ? gpio[68] adc_0 ? an[7] u5 c[2] siul ? gpio[34] adc_0 ? an[3] u6 e[2] siul ? gpio[66] adc_0 ? an[5] u7 b[9] siul ? gpio[25] adc_0 adc_1 ? an[11] u8 b[12] siul ? gpio[28] adc_0 adc_1 ? an[14] u9 v dd_hv_adv ? u10 v ss_hv_adv ? u11 e[11] siul ? gpio[75] adc_1 ? an[4] u12 not connected ? u13 not connected ? u14 v dd_hv_pmu ? u15 g[11] siul gpio[107] gpio[107] flexray dbg3 ? flexpwm_0 ? fault[3] u16 v ss_hv_io_ring ? u17 v ss_hv_io_ring ? 1 v pp_test should always be tied to ground (v ss ) for normal operations. table 4. 257 mapbga pin function summary (continued) pin # port/function peripheral ou tput function input function
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 52 2.2 supply pins table 5. supply pins supply pin # symbol description 144 pkg 257 pkg vreg control and power supply pins bctrl voltage regulator external npn ballast base control pin 69 r13 v dd_lv_cor core logic supply 70 vdd_lv 1 v ss_lv_cor core regulator ground 71 vss_lv 2 v dd_hv_pmu voltage regulator supply 72 u14 adc_0/adc_1 reference voltage and adc supply v dd_hv_adr0 adc_0 high reference voltage 50 r7 v ss_hv_adr0 adc_0 low reference voltage 51 t7 v dd_hv_adr1 adc_1 high reference voltage 56 r9 v ss_hv_adr1 adc_1 low reference voltage 57 t9 v dd_hv_adv adc voltage supply for adc_0 and adc_1 58 u9 v ss_hv_adv adc ground for adc_0 and adc_1 59 u10 power supply pins (3.3 v) v dd_hv_io 3.3 v input/output supply voltage 6 vdd_hv 3 v ss_hv_io 3.3 v input/output ground 7 vss_hv 4 v dd_hv_reg_0 vdd_hv_reg_0 16 j3 v dd_hv_io 3.3 v input/output supply voltage 21 vdd_hv 3 v ss_hv_io 3.3 v input/output ground 22 vss_hv 4 v dd_hv_osc crystal oscillator amplifier supply voltage 27 m1 v ss_hv_osc crystal oscillator amplifier ground 28 p1 v ss_hv_io 3.3 v input/output ground 90 vss_hv 4 v dd_hv_io 3.3 v input/output supply voltage 91 vdd_hv 3 v dd_hv_reg_1 vdd_hv_reg_1 95 h15 v ss_hv_fla vss_hv_fla 96 j16 v dd_hv_fla vdd_hv_fla 97 h16 v dd_hv_io vdd_hv_io 126 vdd_hv 3 v ss_hv_io vss_hv_io 127 vss_hv 4 v dd_hv_reg_2 vdd_hv_reg_2 130 c7 power supply pins (1.2 v) v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 17 vss_hv 2
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 53 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 18 vdd_lv 1 v ss 1v2 vss_lv_pll0_pll1 / 1.2 v decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v dd_lv_pll. 35 n4 v dd 1v2 vdd_lv_pll0_pll1 decoupling pins for on-chip fmpll modules. decoupling capacitor must be connected between this pin and v ss_lv_pll. 36 p4 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 39 vdd_lv 1 v ss_lv_cor vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 40 vss_lv 2 v dd_lv_cor vdd_lv_cor decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v ss_lv_regcor. 70 vdd_lv 1 v ss_lv_cor vss_lv_regcor0 decoupling pins for core logic and regulator feedback. decoupling capacitor must be connected between this pins and v dd_lv_regcor. 71 vss_lv 2 v dd_lv_cor vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v ss_lv_cor pin. 93 vdd_lv 1 v ss_lv_cor vss_lv_cor / 1.2 v decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 94 vss_lv 2 v dd 1v2 vdd_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 131 vdd_lv 1 v ss 1v2 vss_lv_cor decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 132 vss_lv 2 v dd 1v2 vdd_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 135 vdd_lv 1 v ss 1v2 vss_lv_cor / decoupling pins for core logic. decoupling capacitor must be connected between these pins and the nearest v dd_lv_cor pin. 137 vss_lv 2 1 vdd_lv balls are tied together on the 257 mapbga substrate. 2 vss_lv balls are tied together on the 257 mapbga substrate. 3 vdd_hv balls are tied together on the 257 mapbga substrate. 4 vss_hv balls are tied together on t he 257 mapbga substrate. table 5. supply pins (continued) supply pin # symbol description 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 54 2.3 system pins 2.4 pin muxing table 7 defines the pin list and muxing for this device. each entry of table 7 shows all the possible configura tions for each pin, via the altern ate functions. the default function assigned to each pin after re set is indicated by alt0. note pins labeled ?nc? are to be left unconnected . any connection to an external circuit or voltage may cause unpredictable device behavior or damage. pins labeled ?reserved? are to be tied to ground. not doing so may cause unpredictable device behavior. table 6. system pins symbol description direction pin # 144 pkg 257 pkg dedicated pins mdo0 1 1 this pad is configured for fast (f) pad speed. nexus message data output ? line 0 output only 9 e1 nmi 2 2 this pad contains a weak pull-up. non maskable interrupt input only 1 e4 xtal input for oscillator amplifier circuit and internal clock generator input only 29 n1 extal oscillator amplifier output output only 30 r1 tms 2 jtag state machine control input only 87 m16 tck 2 jtag clock input only 88 l15 jcomp 3 3 this pad contains a weak pull-down. jtag compliance select input only 123 c10 reset pin reset bidirectional reset with schmitt-trigger characteristics and noise filter. this pin has medium drive strength. bidirectional 31 p2 test pin vpp test pin for testing purpose only. to be tied to ground in normal operating mode. 107 d15
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 55 table 7. pin muxing port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg port a a[0] pcr[0] siul gpio[0] alt0 gpio[0] ? pull down m s 73 t14 etimer_0 etc[0] alt1 etc[0] psmi[35]; padsel=0 dspi_2 sck alt2 sck psmi[1]; padsel=0 siul ? ? eirq[0] ? a[1] pcr[1] siul gpio[1] alt0 gpio[1] ? pull down m s 74 r14 etimer_0 etc[1] alt1 etc[1] psmi[36]; padsel=0 dspi_2 sout alt2 ? ? siul ? ? eirq[1] ? a[2] pcr[2] siul gpio[2] alt0 gpio[2] ? pull down m s 84 n16 etimer_0 etc[2] alt1 etc[2] psmi[37]; padsel=0 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=0 dspi_2 ? ? sin psmi[2]; padsel=0 mc_rgm ? ? abs[0] ? siul ? ? eirq[2] ? a[3] pcr[3] siul gpio[3] alt0 gpio[3] ? pull down m s 92 k17 etimer_0 etc[3] alt1 etc[3] psmi[38]; padsel=0 dspi_2 cs0 alt2 cs0 psmi[3]; padsel=0 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=0 mc_rgm ? ? abs[2] ? siul ? ? eirq[3] ?
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 56 a[4] pcr[4] siul gpio[4] alt0 gpio[4] ? pull down m s 108 c16 etimer_1 etc[0] alt1 etc[0] psmi[9]; padsel=0 dspi_2 cs1 alt2 ? ? etimer_0 etc[4] alt3 etc[4] psmi[7]; padsel=0 mc_rgm ? ? fab ? siul ? ? eirq[4] ? a[5] pcr[5] siul gpio[5] alt0 gpio[5] ? pull down m s 14 h4 dspi_1 cs0 alt1 cs0 ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=0 dspi_0 cs7 alt3 ? ? siul ? ? eirq[5] ? a[6] pcr[6] siul gpio[6] alt0 gpio[6] ? pull down m s 2 g4 dspi_1 sck alt1 sck ? siul ? ? eirq[6] ? a[7] pcr[7] siul gpio[7] alt0 gpio[7] ? pull down m s 10 f3 dspi_1 sout alt1 ? ? siul ? ? eirq[7] ? a[8] pcr[8] siul gpio[8] alt0 gpio[8] ? pull down m s 12 f4 dspi_1 ? ? sin ? siul ? ? eirq[8] ? a[9] pcr[9] siul gpio[9] alt0 gpio[9] ? pull down m s 134 b6 dspi_2 cs1 alt1 ? ? flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=0 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 57 a[10] pcr[10] siul gpio[10] alt0 gpio[10] ? pull down m s 118 a13 dspi_2 cs0 alt1 cs0 psmi[3]; padsel=1 flexpwm_0 b[0] alt2 b[0] psmi[24]; padsel=0 flexpwm_0 x[2] alt3 x[2] psmi[29]; padsel=0 siul ? ? eirq[9] ? a[11] pcr[11] siul gpio[11] alt0 gpio[11] ? pull down m s 120 d11 dspi_2 sck alt1 sck psmi[1]; padsel=1 flexpwm_0 a[0] alt2 a[0] psmi[20]; padsel=0 flexpwm_0 a[2] alt3 a[2] psmi[22]; padsel=0 siul ? ? eirq[10] ? a[12] pcr[12] siul gpio[12] alt0 gpio[12] ? pull down m s 122 a10 dspi_2 sout alt1 ? ? flexpwm_0 a[2] alt2 a[2] psmi[22]; padsel=1 flexpwm_0 b[2] alt3 b[2] psmi[26]; padsel=0 siul ? ? eirq[11] ? a[13] pcr[13] siul gpio[13] alt0 gpio[13] ? pull down m s 136 c6 flexpwm_0 b[2] alt2 b[2] psmi[26]; padsel=1 dspi_2 ? ? sin psmi[2]; padsel=1 flexpwm_0 ? ? fault[0] psmi[16]; padsel=1 siul ? ? eirq[12] ? a[14] pcr[14] siul gpio[14] alt0 gpio[14] ? pull down m s 143 b4 flexcan_1 txd alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=0 siul ? ? eirq[13] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 58 a[15] pcr[15] siul gpio[15] alt0 gpio[15] ? pull down m s 144 d3 etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=0 flexcan_0 ? ? rxd psmi[33]; padsel=0 siul ? ? eirq[14] ? port b b[0] pcr[16] siul gpio[16] alt0 gpio[16] ? pull down m s 109 b15 flexcan_0 txd alt1 ? ? etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=0 sscm debug[0] alt3 ? ? siul ? ? eirq[15] ? b[1] pcr[17] siul gpio[17] alt0 gpio[17] ? pull down m s 110 c14 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=0 sscm debug[1] alt3 ? ? flexcan_0 ? ? rxd psmi[33]; padsel=1 flexcan_1 ? ? rxd psmi[34]; padsel=1 siul ? ? eirq[16] ? b[2] pcr[18] siul gpio[18] alt0 gpio[18] ? pull down m s 114 a14 linflex_0 txd alt1 ? ? sscm debug[2] alt3 ? ? siul ? ? eirq[17] ? b[3] pcr[19] siul gpio[19] alt0 gpio[19] ? pull down m s 116 b13 sscm debug[3] alt3 ? ? linflex_0 ? ? rxd psmi[31]; padsel=0 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 59 b[4] 2 pcr[20] siul gpio[20] alt0 gpio[20] ? pull down f s 89 l17 jtagc tdo alt1 ? ? b[5] pcr[21] siul gpio[21] alt0 gpio[21] ? pull up m s 86 m15 jtagc ? ? tdi ? b[6] pcr[22] siul gpio[22] alt0 gpio[22] ? pull down f s 138 b3 mc_cgm clk_out alt1 ? ? dspi_2 cs2 alt2 ? ? siul ? eirq[18] ? b[7] pcr[23] siul ? alt0 gpi[23] ? ? ? ? 43 r5 linflex_0 ? ? rxd psmi[31]; padsel=1 adc_0 ? ? an[0] 3 ? b[8] pcr[24] siul ? alt0 gpi[24] ? ? ? ? 47 p7 etimer_0 ? ? etc[5] psmi[8]; padsel=2 adc_0 ? ? an[1] 3 ? b[9] pcr[25] siul ? alt0 gpi[25] ? ? ? ? 52 u7 adc_0 adc_1 ??an[11] 3 ? b[10] pcr[26] siul ? alt0 gpi[26] ? ? ? ? 53 r8 adc_0 adc_1 ??an[12] 3 ? b[11] pcr[27] siul ? alt0 gpi[27] ? ? ? ? 54 t8 adc_0 adc_1 ??an[13] 3 ? b[12] pcr[28] siul ? alt0 gpi[28] ? ? ? ? 55 u8 adc_0 adc_1 ??an[14] 3 ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 60 b[13] pcr[29] siul ? alt0 gpi[29] ? ? ? ? 60 r10 linflex_1 ? ? rxd psmi[32]; padsel=0 adc_1 ? ? an[0] 3 ? b[14] pcr[30] siul ? alt0 gpi[30] ? ? ? ? 64 p11 etimer_0 ? ? etc[4] psmi[7]; padsel=2 siul ? ? eirq[19] ? adc_1 ? ? an[1] 3 ? b[15] pcr[31] siul ? alt0 gpi[31] ? ? ? ? 62 r11 siul ? ? eirq[20] ? adc_1 ? ? an[2] 3 ? port c c[0] pcr[32] siul ? alt0 gpi[32] ? ? ? ? 66 r12 adc_1 ? ? an[3] 3 ? c[1] pcr[33] siul ? alt0 gpi[33] ? ? ? ? 41 t4 adc_0 ? ? an[2] 3 ? c[2] pcr[34] siul ? alt0 gpi[34] ? ? ? ? 45 u5 adc_0 ? ? an[3] 3 ? c[4] pcr[36] siul gpio[36] alt0 gpio[36] ? pull down m s 11 h3 dspi_0 cs0 alt1 cs0 ? flexpwm_0 x[1] alt2 x[1] psmi[28]; padsel=0 sscm debug[4] alt3 ? ? siul ? ? eirq[22] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 61 c[5] pcr[37] siul gpio[37] alt0 gpio[37] ? pull down m s 13 g3 dspi_0 sck alt1 sck ? sscm debug[5] alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=0 siul ? ? eirq[23] ? c[6] pcr[38] siul gpio[38] alt0 gpio[38] ? pull down m s 142 d4 dspi_0 sout alt1 ? ? flexpwm_0 b[1] alt2 b[1] psmi[25]; padsel=0 sscm debug[6] alt3 ? ? siul ? ? eirq[24] ? c[7] pcr[39] siul gpio[39] alt0 gpio[39] ? pull down m s 15 k4 flexpwm_0 a[1] alt2 a[1] psmi[21]; padsel=0 sscm debug[7] alt3 ? ? dspi_0 ? ? sin ? c[10] pcr[42] siul gpio[42] alt0 gpio[42] ? pull down m s 111 a15 dspi_2 cs2 alt1 ? ? flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=0 c[11] pcr[43] siul gpio[43] alt0 gpio[43] ? pull down m s 80 m14 etimer_0 etc[4] alt1 etc[4] psmi[7]; padsel=1 dspi_2 cs2 alt2 ? ? c[12] pcr[44] siul gpio[44] alt0 gpio[44] ? pull down m s 82 n15 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=0 dspi_2 cs3 alt2 ? ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 62 c[13] pcr[45] siul gpio[45] alt0 gpio[45] ? pull down m s 101 f15 etimer_1 etc[1] alt1 etc[1] psmi[10]; padsel=0 ctu_0 ? ? ext_in psmi[0]; padsel=0 flexpwm_0 ? ? ext_sync psmi[15]; padsel=0 c[14] pcr[46] siul gpio[46] alt0 gpio[46] ? pull down m s 103 e15 etimer_1 etc[2] alt1 etc[2] psmi[11]; padsel=1 ctu_0 ext_tgr alt2 ? ? c[15] pcr[47] siul gpio[47] alt0 gpio[47] ? pull down sym s 124 a8 flexray ca_tr_en alt1 ? ? etimer_1 etc[0] alt2 etc[0] psmi[9]; padsel=1 flexpwm_0 a[1] alt3 a[1] psmi[21]; padsel=1 ctu_0 ? ? ext_in psmi[0]; padsel=1 flexpwm_0 ? ? ext_sync psmi[15]; padsel=1 port d d[0] pcr[48] siul gpio[48] alt0 gpio[48] ? pull down sym s 125 b8 flexray ca_tx alt1 ? ? etimer_1 etc[1] alt2 etc[1] psmi[10]; padsel=1 flexpwm_0 b[1] alt3 b[1] psmi[25]; padsel=1 d[1] pcr[49] siul gpio[49] alt0 gpio[49] ? pull down m s 3 e3 etimer_1 etc[2] alt2 etc[2] psmi[11]; padsel=2 ctu_0 ext_tgr alt3 ? ? flexray ? ? ca_rx ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 63 d[2] pcr[50] siul gpio[50] alt0 gpio[50] ? pull down m s 140 c5 etimer_1 etc[3] alt2 etc[3] psmi[12]; padsel=1 flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=0 flexray ? ? cb_rx ? d[3] pcr[51] siul gpio[51] alt0 gpio[51] ? pull down sym s 128 a7 flexray cb_tx alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=1 flexpwm_0 a[3] alt3 a[3] psmi[23]; padsel=2 d[4] pcr[52] siul gpio[52] alt0 gpio[52] ? pull down sym s 129 b7 flexray cb_tr_en alt1 ? ? etimer_1 etc[5] alt2 etc[5] psmi[14]; padsel=2 flexpwm_0 b[3] alt3 b[3] psmi[27]; padsel=2 d[5] pcr[53] siul gpio[53] alt0 gpio[53] ? pull down m s 33 n3 dspi_0 cs3 alt1 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=0 d[6] pcr[54] siul gpio[54] alt0 gpio[54] ? pull down m s 34 p3 dspi_0 cs2 alt1 ? ? flexpwm_0 x[3] alt3 x[3] psmi[30]; padsel=1 flexpwm_0 ? ? fault[1] psmi[17]; padsel=1 d[7] pcr[55] siul gpio[55] alt0 gpio[55] ? pull down m s 37 r4 dspi_1 cs3 alt1 ? ? dspi_0 cs4 alt3 ? ? swg analog output ? ? ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 64 d[8] pcr[56] siul gpio[56] alt0 gpio[56] ? pull down m s 32 m3 dspi_1 cs2 alt1 ? ? etimer_1 etc[4] alt2 etc[4] psmi[13]; padsel=2 dspi_0 cs5 alt3 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=1 d[9] pcr[57] siul gpio[57] alt0 gpio[57] ? pull down m s 26 l3 flexpwm_0 x[0] alt1 x[0] ? linflexd_1 txd alt2 ? ? d[10] pcr[58] siul gpio[58] alt0 gpio[58] ? pull down m s 76 t15 flexpwm_0 a[0] alt1 a[0] psmi[20]; padsel=1 etimer_0 ? ? etc[0] psmi[35]; padsel=1 d[11] pcr[59] siul gpio[59] alt0 gpio[59] ? pull down m s 78 r16 flexpwm_0 b[0] alt1 b[0] psmi[24]; padsel=1 etimer_0 ? ? etc[1] psmi[36]; padsel=1 d[12] pcr[60] siul gpio[60] alt0 gpio[60] pull down m s 99 g14 flexpwm_0 x[1] alt1 x[1] psmi[28]; padsel=1 linflexd_1 ? ? rxd psmi[32]; padsel=1 d[14] pcr[62] siul gpio[62] alt0 gpio[62] ? pull down m s 105 d16 flexpwm_0 b[1] alt1 b[1] psmi[25]; padsel=2 etimer_0 ? ? etc[3] psmi[38]; padsel=1 port e e[0] pcr[64] siul ? alt0 gpi[64] ? ? ? ? 68 t13 adc_1 ? ? an[5] 3 ? e[2] pcr[66] siul ? alt0 gpi[66] ? ? ? ? 49 u6 adc_0 ? ? an[5] 3 ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 65 e[4] pcr[68] siul ? alt0 gpi[68] ? ? ? ? 42 u4 adc_0 ? ? an[7] 3 ? e[5] pcr[69] siul ? alt0 gpi[69] ? ? ? ? 44 t5 adc_0 ? ? an[8] 3 ? e[6] pcr[70] siul ? alt0 gpi[70] ? ? ? ? 46 r6 adc_0 ? ? an[4] 3 ? e[7] pcr[71] siul ? alt0 gpi[71] ? ? ? ? 48 t6 adc_0 ? ? an[6] 3 ? e[9] pcr[73] siul ? alt0 gpi[73] ? ? ? ? 61 t10 adc_1 ? ? an[7] 3 ? e[10] pcr[74] siul ? alt0 gpi[74] ? ? ? ? 63 t11 adc_1 ? ? an[8] 3 ? e[11] pcr[75] siul ? alt0 gpi[75] ? ? ? ? 65 u11 adc_1 ? ? an[4] 3 ? e[12] pcr[76] siul ? alt0 gpi[76] ? ? ? ? 67 t12 adc_1 ? ? an[6] 3 ? e[13] pcr[77] siul gpio[77] alt0 gpio[77] ? pull down m s 117 d12 etimer_0 etc[5] alt1 etc[5] psmi[8]; padsel=1 dspi_2 cs3 alt2 ? ? siul ? ? eirq[25] ? e[14] pcr[78] siul gpio[78] alt0 gpio[78] ? pull down m s 119 b12 etimer_1 etc[5] alt1 etc[5] psmi[14]; padsel=3 siul ? ? eirq[26] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 66 e[15] pcr[79] siul gpio[79] alt0 gpio[79] ? pull down m s 121 b11 dspi_0 cs1 alt1 ? ? siul ? ? eirq[27] ? port f f[0] pcr[80] siul gpio[80] alt0 gpio[80] ? pull down m s 133 d7 flexpwm_0 a[1] alt1 a[1] psmi[21]; padsel=2 etimer_0 ? ? etc[2] psmi[37]; padsel=1 siul ? ? eirq[28] ? f[3] pcr[83] siul gpio[83] alt0 gpio[83] ? pull down m s 139 b5 dspi_0 cs6 alt1 ? ? f[4] pcr[84] siul gpio[84] alt0 gpio[84] ? pull down f s 4 d2 npc mdo[3] alt2 ? ? f[5] pcr[85] siul gpio[85] alt0 gpio[85] ? pull down f s 5 d1 npc mdo[2] alt2 ? ? f[6] pcr[86] siul gpio[86] alt0 gpio[86] ? pull down f s 8 e2 npc mdo[1] alt2 ? ? f[7] pcr[87] siul gpio[87] alt0 gpio[87] ? pull down f s 19 j1 npc mcko alt2 ? ? f[8] pcr[88] siul gpio[88] alt0 gpio[88] ? pull down f s 20 k2 npc mseo[1] alt2 ? ? f[9] pcr[89] siul gpio[89] alt0 gpio[89] ? pull down f s 23 k1 npc mseo[0] alt2 ? ? f[10] pcr[90] siul gpio[90] alt0 gpio[90] ? pull down f s 24 l1 npc evto alt2 ? ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 67 f[11] pcr[91] siul gpio[91] alt0 gpio[91] ? pull down m s 25 l2 npc evti alt2 ? ? f[12] pcr[92] siul gpio[92] alt0 gpio[92] ? pull down m s 106 c17 etimer_1 etc[3] alt1 etc[3] psmi[12]; padsel=2 siul ? ? eirq[30] ? f[13] pcr[93] siul gpio[93] alt0 gpio[93] ? pull down m s 112 b14 etimer_1 etc[4] alt1 etc[4] psmi[13]; padsel=3 siul ? ? eirq[31] ? f[14] pcr[94] siul gpio[94] alt0 gpio[94] ? pull down m s 115 c13 linflexd_1 txd alt1 ? ? f[15] pcr[95] siul gpio[95] alt0 gpio[95] ? pull down m s 113 d13 linflexd_1 ? ? rxd psmi[32]; padsel=2 fccu fccu_ f[0] ?fccu f[0]alt0f[0] ? ?ss 38r2 fccu_ f[1] ?fccu f[1]alt0f[1] ? ?ss 141c4 port g g[2] pcr[98] siul gpio[98] alt0 gpio[98] ? pull down m s 102 e16 flexpwm_0 x[2] alt1 x[2] psmi[29]; padsel=1 dspi_1 cs1 alt2 ? ? g[3] pcr[99] siul gpio[99] alt0 gpio[99] ? pull down m s 104 d17 flexpwm_0 a[2] alt1 a[2] psmi[22]; padsel=2 etimer_0 ? ? etc[4] psmi[7]; padsel=3 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 68 g[4] pcr[100] siul gpio[100] alt0 gpio[100] ? pull down m s 100 f17 flexpwm_0 b[2] alt1 b[2] psmi[26]; padsel=2 etimer_0 ? ? etc[5] psmi[8]; padsel=3 g[5] pcr[101] siul gpio[101] alt0 gpio[101] ? pull down m s 85 n17 flexpwm_0 x[3] alt1 x[3] psmi[30]; padsel=2 dspi_2 cs3 alt2 ? ? g[6] pcr[102] siul gpio[102] alt0 gpio[102] ? pull down m s 98 g17 flexpwm_0 a[3] alt1 a[3] psmi[23]; padsel=3 g[7] pcr[103] siul gpio[103] alt0 gpio[103] pull down m s 83 p17 flexpwm_0 b[3] alt1 b[3] psmi[27]; padsel=3 g[8] pcr[104] siul gpio[104] alt0 gpio[104] ? pull down m s 81 p16 flexray dbg0 alt1 ? ? dspi_0 cs1 alt2 ? ? flexpwm_0 ? ? fault[0] psmi[16]; padsel=2 siul ? ? eirq[21] ? g[9] pcr[105] siul gpio[105] alt0 gpio[105] ? pull down m s 79 r17 flexray dbg1 alt1 ? ? dspi_1 cs1 alt2 ? ? flexpwm_0 ? ? fault[1] psmi[17]; padsel=2 siul ? ? eirq[29] ? g[10] pcr[106] siul gpio[106] alt0 gpio[106] ? pull down m s 77 p15 flexray dbg2 alt1 ? ? dspi_2 cs3 alt2 ? ? flexpwm_0 ? ? fault[2] psmi[18]; padsel=1 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 69 g[11] pcr[107] siul gpio[107] alt0 gpio[107] ? pull down m s 75 u15 flexray dbg3 alt1 ? ? flexpwm_0 ? ? fault[3] psmi[19]; padsel=2 g[12] pcr[108] siul gpio[108] alt0 gpio[108] ? pull down f s ? f2 npc mdo[11] alt2 ? ? g[13] pcr[109] siul gpio[109] alt0 gpio[109] ? pull down f s ? h1 npc mdo[10] alt2 ? ? g[14] pcr[110] siul gpio[110] alt0 gpio[110] ? pull down f s ? a6 npc mdo[9] alt2 ? ? g[15] pcr[111] siul gpio[111] alt0 gpio[111] ? pull down f s ? j2 npc mdo[8] alt2 ? ? port h h[0] pcr[112] siul gpio[112] alt0 gpio[112] ? pull down f s ? a5 npc mdo[7] alt2 ? ? h[1] pcr[113] siul gpio[113] alt0 gpio[113] ? pull down f s ? f1 npc mdo[6] alt2 ? ? h[2] pcr[114] siul gpio[114] alt0 gpio[114] ? pull down f s ? a4 npc mdo[5] alt2 ? ? h[3] pcr[115] siul gpio[115] alt0 gpio[115] ? pull down f s ? g1 npc mdo[4] alt2 ? ? h[4] pcr[116] siul gpio[116] alt0 gpio[116] ? pull down m s ? l16 flexpwm_1 x[0] alt1 x[0] ? etimer_2 etc[0] alt2 etc[0] psmi[39]; padsel=0 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 70 h[5] pcr[117] siul gpio[117] alt0 gpio[117] ? pull down m s ? m17 flexpwm_1 a[0] alt1 a[0] ? dspi_0 cs4 alt3 ? ? h[6] pcr[118] siul gpio[118] alt0 gpio[118] ? pull down m s ? h17 flexpwm_1 b[0] alt1 b[0] ? dspi_0 cs5 alt3 ? ? h[7] pcr[119] siul gpio[119] alt0 gpio[119] ? pull down m s ? k16 flexpwm_1 x[1] alt1 x[1] ? etimer_2 etc[1] alt2 etc[1] psmi[40]; padsel=0 h[8] pcr[120] siul gpio[120] alt0 gpio[120] ? pull down m s ? k15 flexpwm_1 a[1] alt1 a[1] ? dspi_0 cs6 alt3 ? ? h[9] pcr[121] siul gpio[121] alt0 gpio[121] ? pull down m s ? g16 flexpwm_1 b[1] alt1 b[1] ? dspi_0 cs7 alt3 ? ? h[10] pcr[122] siul gpio[122] alt0 gpio[122] ? pull down m s ? a11 flexpwm_1 x[2] alt1 x[2] ? etimer_2 etc[2] alt2 etc[2] ? h[11] pcr[123] siul gpio[123] alt0 gpio[123] ? pull down m s ? c11 flexpwm_1 a[2] alt1 a[2] ? h[12] pcr[124] siul gpio[124] alt0 gpio[124] ? pull down m s ? b10 flexpwm_1 b[2] alt1 b[2] ? h[13] pcr[125] siul gpio[125] alt0 gpio[125] ? pull down m s ? g15 flexpwm_1 x[3] alt1 x[3] ? etimer_2 etc[3] alt2 etc[3] psmi[42]; padsel=0 table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
package pinouts and signal descriptions pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 71 h[14] pcr[126] siul gpio[126] alt0 gpio[126] ? pull down m s ? a12 flexpwm_1 a[3] alt1 a[3] ? etimer_2 etc[4] alt2 etc[4] ? h[15] pcr[127] siul gpio[127] alt0 gpio[127] ? pull down m s ? j17 flexpwm_1 b[3] alt1 b[3] ? etimer_2 etc[5] alt2 etc[5] ? port i i[0] pcr[128] siul gpio[128] alt0 gpio[128] ? pull down m s ? c9 etimer_2 etc[0] alt1 etc[0] psmi[39]; padsel=1 dspi_0 cs4 alt2 ? ? flexpwm_1 ? ? fault[0] ? i[1] pcr[129] siul gpio[129] alt0 gpio[129] ? pull down m s ? c12 etimer_2 etc[1] alt1 etc[1] psmi[40]; padsel=1 dspi_0 cs5 alt2 ? ? flexpwm_1 ? ? fault[1] ? i[2] pcr[130] siul gpio[130] alt0 gpio[130] ? pull down m s ? f16 etimer_2 etc[2] alt1 etc[2] psmi[41]; padsel=1 dspi_0 cs6 alt2 ? ? flexpwm_1 ? ? fault[2] ? table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 72 i[3] pcr[131] siul gpio[131] alt0 gpio[131] ? pull down m s ? e17 etimer_2 etc[3] alt1 etc[3] psmi[42]; padsel=1 dspi_0 cs7 alt2 ? ? ctu_0 ext_tgr alt3 ? ? flexpwm_1 ? ? fault[3] ? rdy (cut2 only) pcr[132] (cut2 only) siul gpio[132] alt0 gpio[132] ? pull down f s ? k3 (cut2 only) npc rdy alt2 ? ? 1 programmable via the src (slew rate control) bit in the respecti ve pad configuration register; s = slow, m = medium, f = fast, sym = symmetric (for flexray) 2 the default function of this pin out of reset is alt1 (tdo). 3 analog table 7. pin muxing (continued) port name pcr peripheral alternate output function output mux sel input functions input mux select weak pull config during reset pad speed 1 pin # src =1 src =0 144 pkg 257 pkg
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 73 3 electrical characteristics 3.1 introduction this section contains detailed information on power cons iderations, dc/ac electrical ch aracteristics, and ac timing specifications for this device. this device is designed to operate at 120 mhz. the electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. these specifications may not be fully tested or guarant eed at this early stage of th e product life cycle. finalized specifications will be published af ter complete characterization and device qualifications have b een completed. the ?symbol? column of the electrical parameter and timings tabl es contains an additional column containing ?sr?, ?cc?, ?p?, ?c?, ?t?, or ?d?. ? ?sr? identifies system requirements?conditions that mu st be provided to ensure normal device operation. an example is the input voltage of a voltage regulator. ? ?cc? identifies controller characteris tics?indicating the characteristics and timing of the signals that the chip provides. ? ?p?, ?c?, ?t?, or ?d? apply only to controller characteristics?sp ecifications that define normal device operation. they specify how each charac teristic is guaranteed. ? p: parameter is guaranteed by produc tion testing of each individual device. ? c: parameter is guaranteed by design characterization. measurements are taken from a statistically relevant sample size across process variations. ? t: parameter is guaranteed by design characterization on a small sample size from t ypical devices under typical conditions unless otherwise noted. all values are shown in the typical (?typ?) column are within this category. ? d: parameters are derived mainly from simulations. 3.2 absolute maximum ratings table 8. absolute maximum ratings 1 symbol parameter conditions min max 2 unit v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? ?0.3 4.0 3, 4 v v ss_hv_reg sr 3.3 v voltage regulator reference voltage ? ?0.1 0.1 v v dd_hv_iox sr 3.3 v input/output supply voltage ? ?0.3 3.6 3, 4 v v ss_hv_iox sr input/output ground voltage ? ?0.1 0.1 v v dd_hv_fla sr 3.3 v flash supply voltage ? ?0.3 3.6 3, 4 v v ss_hv_fla sr flash memory ground ? ?0.1 0.1 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ? ?0.3 4.0 3, 4 v v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ? ?0.1 0.1 v v dd_hv_adr0 5 v dd_hv_adr1 sr 3.3 v / 5.0 v adc_0 high reference voltage 3.3 v / 5.0 v adc_1 high reference voltage ? ?0.3 6.0 v v ss_hv_adr0 v ss_hv_adr1 sr adc_0 ground and low reference voltage adc_1 ground and low reference voltage ? ?0.1 0.1 v v dd_hv_adv sr 3.3 v adc supply voltage ? ?0.3 4.0 3, 4 v
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 74 3.3 recommended operating conditions v ss_hv_adv sr 3.3 v adc supply ground ? ?0.1 0.1 v tv dd sr slope characteristics on all v dd during power up ? 0.5 3.0 10 6 (3.0 v/sec) v/s v in sr voltage on any pin with respect to ground (v ss_hv_io x ) ? ?0.3 6.0 v relative to v dd ?0.3 v dd +0.3 6 i injpad sr injected input current on any pin during overload condition ? ?10 10 ma i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 ma t stg sr storage temperature ? ?55 150 c 1 functional operating conditions are given in the dc electrical characteristics. absolute maximum ratings are stress ratings only, and functional operation at the maxima is no t guaranteed. stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2 absolute maximum voltages are currently maximum burn-in voltages. absolute maximum specifications for device stress have not yet been determined. 3 5.3 v for 10 hours cumulative over lifetime of device, 3.3 v +10% for time remaining. 4 voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance. 5 v dd_hv_adr0 and v dd_hv_adr1 cannot be operated be operated at diff erent voltages, and need to be supplied by the same voltage source. 6 only when v dd < 5.2 v. table 9. recommended operating conditions (3.3 v) symbol parameter conditions min max 1 unit v dd_hv_reg sr 3.3 v voltage regulator supply voltage ? 3.0 3.6 v v ss_hv_reg sr 3.3 v voltage regulator reference voltage ? 0 0 v v dd_hv_iox sr 3.3 v input/output supply voltage ? 3.0 3.6 v v ss_hv_iox sr input/output ground voltage ? 0 0 v v dd_hv_fla sr 3.3 v flash supply voltage ? 3.0 3.6 v v ss_hv_fla sr flash memory ground ? 0 0 v v dd_hv_osc sr 3.3 v crystal oscillator amplifier supply voltage ? 3.0 3.6 v v ss_hv_osc sr 3.3 v crystal oscillator amplifier reference voltage ? 0 0 v v dd_hv_adr0 2 v dd_hv_adr1 sr 3.3 v / 5.0 v adc_0 high reference voltage 3.3 v / 5.0 v adc_1 high reference voltage ? 4.5 to 5.5 or 3.0 to 3.6 v v dd_hv_adv sr 3.3 v adc supply voltage ? 3.0 3.6 v v ss_hv_ad0 v ss_hv_ad1 sr adc_0 ground and low reference voltage adc_1 ground and low reference voltage ?00v v ss_hv_adv sr 3.3 v adc supply ground ? 0 0 v v dd_lv_regcor 3 sr internal supply voltage ? ? ? v table 8. absolute maximum ratings 1 (continued) symbol parameter conditions min max 2 unit
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 75 3.4 thermal characteristics v ss_lv_regcor 4 sr internal reference voltage ? 0 0 v v dd_lv_cor x 2 sr internal supply voltage ? ? ? v v ss_lv_cor x 3 sr internal reference voltage ? 0 0 v v dd_lv_pll 2 sr internal supply voltage ? ? ? v v ss_lv_pll 3 sr internal reference voltage ? 0 0 v t a sr ambient temperature under bias f cpu ? 120 mhz ?40 125 c t j sr junction temperature under bias ? ?40 150 c 1 full functionality cannot be guaranteed when voltage drops below 3.0 v. in particular, adc electrical characteristics and i/os dc electrical specification may not be guaranteed. 2 v dd_hv_adr0 and v dd_hv_adr1 cannot be operated at different voltages, and need to be supplied by the same voltage source. 3 can be connected to emitter of external npn. low voltage supplies are not under user control. they are produced by an on-chip voltage regulator. 4 for the device to function properly, the low voltage grounds (v ss_lv_ xxx ) must be shorted to high voltage grounds (v ss_hv_ xxx ) and the low voltage supply pins (v dd_lv_ xxx ) must be connected to the external ballast emitter, if one is used. table 10. thermal characteristics for 144 lqfp package 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol parameter conditions value unit r ? ja d thermal resistance, junction-to-ambient natural convection 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board ? 1s 42 c/w four layer board ? 2s2p 34 r ? jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 34 c/w four layer board ? 2s2p 28 r ? jb d thermal resistance junction-to-board 3 3 junction-to-board thermal resistance determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. ?22c/w r ? jc d thermal resistance junction-to-case 4 4 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. ?8c/w ? jt d junction-to-package-top natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. ?3c/w table 9. recommended operating conditions (3.3 v) (continued) symbol parameter conditions min max 1 unit
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 76 3.4.1 general notes for specification s at maximum junction temperature an estimation of the chip junction temperature, t j , can be obtained from equation 1 : t j =t a +(r ? ja p d ) eqn. 1 where: t a = ambient temperatur e for the package ( o c) r ? ja = junction to ambient thermal resistance ( o c/w) p d = power dissipation in the package (w) the junction to ambient th ermal resistance is an industry st andard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two va lues in common usage: the value determined on a single layer board and the value obtained on a board with two planes. for pack ages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. th e value obtained on the board with the intern al planes is usually appropriate if the board has low power dissipation and the components are well separated. when a heat sink is used, the th ermal resistance is expressed in equation 2 as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: r ? ja =r ? jc + r ? ca eqn. 2 where: r ? ja = junction to ambient thermal resistance (c/w) r ? jc = junction to case thermal resistance (c/w) r ? ca = case to ambient thermal resistance (c/w) table 11. thermal characteristics for 257 mapbga package 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol parameter conditions value unit r ? ja d thermal resistance junction-to-ambient natural convection 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. single layer board ? 1s 46 c/w four layer board ? 2s2p 26 r ? jma d thermal resistance, junction-to-ambient forced convection at 200 ft/min single layer board ? 1s 37 c/w four layer board ? 2s2p 22 r ? jb d thermal resistance junction-to-board 3 3 junction-to-board thermal resistance determined per jedec jesd51-8. thermal test board meets jedec specification for the specified package. ?13c/w r ? jc d thermal resistance junction-to-case 4 4 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported va lue includes the thermal resistance of the interface layer. ?8c/w ? jt d junction-to-package-top natural convection 5 5 thermal characterization parameter indicating the te mperature difference between the package top and the junction temperature per jedec jesd51-2. when greek le tters are not available, the thermal characterization parameter is written as psi-jt. ?2c/w
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 77 r ? jc is device related and cannot be influenced by the user. the user controls the thermal envi ronment to change the case to ambient thermal resistance, r ? ca . for instance, the user can change the size of th e heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in th e application when heat sink s are not used, the thermal characterization parameter ( ? jt ) can be used to determine the junction temperat ure with a measurement of the temperature at the top center of the package case using equation 3 : t j =t t +( ? jt p d ) eqn. 3 where: t t = thermocouple temperature on top of the package (c) ? jt = thermal characterization parameter (c/w) p d = power dissipation in the package (w) the thermal characterization parameter is measured per jesd51-2 specification using a 40 gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple juncti on and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to av oid measurement errors caused by cooling effects of the thermocouple wire. 3.4.1.1 references semiconductor equipment and materials international 3081 zanker road san jose, ca 95134 usa (408) 943-6900 mil-spec and eia/jesd (jedec) specifi cations are available from global engi neering documents at 800-854-7179 or 303-397-7956. jedec specifications are available on the web at http://www.jedec.org. 1. c.e. triplett and b. joiner, ?an experimental characterization of a 272 pbga within an automotive engine controller module,? proceedings of semi therm, san diego, 1998, pp. 47?54. 2. g. kromann, s. shidore, and s. addison, ?thermal mo deling of a pbga for air-cooled applications,? electronic packaging and production, pp. 53?58, march 1998. 3. b. joiner and v. adams, ?measurement and simulation of junction to board thermal resistance and its application in thermal modeling,? proceedings of se mitherm, san diego, 1999, pp. 212?220. 3.5 electromagnetic interference (emi) characteristics (cut1) the characteristics in table 13 were measured using: ? device configuration, tet conditions, and em testing per standard iec61967-2 ? supply voltage of 3.3 v dc ? ambient temperature of 25 ? c the configuration information referenced in table 13 is explained in table 12 .
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 78 3.6 electrostatic discharge (esd) characteristics electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size depends on the number of su pply pins in the device (3 parts ( n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. table 12. emi configuration summary configuration name description configuration a ? high emission = all pads have max slew rate, lvds pads running at 40 mhz ? oscillator frequency = 40 mhz ? system bus frequency = 80 mhz ? no pll frequency modulation ? iec level i ( ? 36 db ? v) configuration b ? reference emission = pads use min, mid and max slew rates, lvds pads disabled ? oscillator frequency = 40 mhz ? system bus frequency = 80 mhz ? 2% pll frequency modulation ? iec level k( ? 30 db ? v) table 13. emi emission testing specifications symbol parameter conditions min typ max unit v eme cc radiated emissions configuration a; frequency range 150 khz?50 mhz ?16?db ? v configuration a; frequency range 50?150 mhz ?16? configuration a; frequency range 150?500 mhz ?32? configuration a; frequency range 500?1000 mhz ?25? configuration b; frequency range 50?150 mhz ?15? configuration b; frequency range 50?150 mhz ?21? configuration b; frequency range 150?500 mhz ?30? configuration b; frequency range 500?1000 mhz ?24?
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 79 3.7 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 3.8 voltage regulator electrical characteristics the voltage regulator is composed of the following blocks: ? high power regulator hpreg1 (internal ballast to support core current) ? high power regulator hpreg2 (external npn to support core current) ? low voltage detector (lvd_main_1) for 3.3 v supply to io (v ddio ) ? low voltage detector (lvd_main_2) for 3.3 v supply (v ddreg ) ? low voltage detector (lvd_main_3) for 3.3 v flash supply (v ddflash ) ? low voltage detector (lvd_dig_main) for 1.2 v digital core supply (hpv dd ) ? low voltage detector (lvd_dig_bkup) for the self-test of lvd_dig_main ? high voltage detector (hvd_dig_main) for 1.2 v digital core supply (hpv dd ) ? high voltage detector (hvd_dig_bkup ) for the self-test of hvd_dig_main. ?power on reset (por) hpreg1 uses an internal ballast to suppor t the core current. hpreg2 is used only when external npn transistor is present on board to supply core current. the pxs20 always powers up using hpreg1 if an external npn tran sistor is present. then the pxs20 makes a transition from hpreg1 to hpreg2. this tran sition is dynamic. once hpreg2 is fully operational, the controller part of hpreg1 is switched off. the following bipolar tr ansistors are supported: ? bcp68 from on semiconductor table 14. esd ratings 1, 2 1 all esd testing is in conformity with cdf-aec-q100 st ress test qualification for automotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. no. symbol parameter conditions class max value 3 3 data based on characterization resu lts, not tested in production. unit 1v esd(hbm) sr electrostatic discharge (human body model) t a =25c conforming to aec-q100-002 h1c 2000 v 2v esd(mm) sr electrostatic discharge (machine model) t a =25c conforming to aec-q100-003 m2 200 v 3v esd(cdm) sr electrostatic discharge (charged device model) t a =25c conforming to aec-q100-011 c3a 500 v 750 (corners) table 15. latch-up results no. symbol parameter conditions class 1 lu sr static latch-up class t a = 125 c conforming to jesd 78 ii level a
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 80 ? bcx68 from infineon table 16. voltage regulator electrical specifications symbol parameter conditions min typ max unit sr external decoupling/ stability capacitor min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 12 ?40f sr combined esr of external capacitor ?0.01 ?0.10 ? sr number of pins for external decoupling/ stability capacitor ?5 ??? c v1v2 sr total capacitance on 1.2 v pins ceramic capacitors, taking into account tolerance, aging, voltage and temperature variation 300 ? 900 nf t su start-up time after main supply stabilization c load =10f4 ? ?2.5ms ? main high voltage power - low voltage detection, upper threshold ?? ?2.9v ? d main supply low voltage detector, lower threshold ?2.6 ??v ? d digital supply high voltage detector upper threshold before a destructive reset initialization phase completion cut2: 1.355 ? cut1: 1.5 cut2: 1.495 v after a destructive reset initialization phase completion cut1: 1.32 cut2: 1.43 ? cut1: 1.4 cut2: 1.47 ? d digital supply high voltage detector lower threshold before a destructive reset initialization phase completion cut1: 1.330 cut2: 1.315 ? cut1: 1.4 cut2: 1.455 v after a destructive reset initialization phase completion cut2: 1.39 ? cut2: 1.43 ? d digital supply low voltage detector lower threshold after a destructive reset initialization phase completion 1.080 ? cut1: 1.110 cut2: 1.12 v ? d digital supply low voltage detector upper threshold after a destructive reset initialization phase completion cut1: 1.17 cut2: 1.16 ? cut1: 1.19 cut2: 1.20 v ? d por rising/ falling supply threshold voltage ?1.6 ?2.6v
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 81 figure 5. bcp68 board schematic example note the combined esr of the capacitors used on 1.2 v pins (v1v2 in the picture) shall be in the range of 30 m ? to 150 m ? . the minimum value of the esr is constrained by the resonance caused by the external compon ents, bonding inductance, and internal decoupling. the minimum esr is required to avoid the resonance and make the regulator stable. ? sr supply ramp rate ? 3? 0.5 10 6 v/s ? d lvd_main: time constant of rc filter at lv d i n p u t 3.3v noise rejection at the input of lvd comparator 1.1 ? ? s ? d hvd_dig: time constant of rc filter at lvd input 1.2v noise rejection at the input of lvd comparator 0.1 ? ? s ? d lvd_dig: time constant of rc filter at lvd input 1.2v noise rejection at the input of lvd comparator 0.1 ? ? s table 16. voltage regulator electrical specifications (continued) symbol parameter conditions min typ max unit bcrtl c ext c int r b l b r s v1v2 ring on board v dd v1v2 pin esr c v1v2 pxs20 bcp68
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 82 3.9 dc electrical characteristics table 17 gives the dc electrical char acteristics at 3.3 v (3.0 v < v dd_hv_io x <3.6v). table 17. dc electrical characteristics 1 1 these specifications are design targets and subject to change per device characterization. symbol parameter conditions min typ max unit v il d minimum low level input voltage ? ?0.1 2 2 ?sr? parameter values must not exceed the absolute maximum ratings shown in ta b l e 8 . ??v v il p maximum level input voltage ? ? ? 0.35 v dd_hv_iox v v ih p minimum high level input voltage ? 0.65 v dd_hv_iox ??v v ih d maximum high level input voltage ? ? ? v dd_hv_iox +0.1 2 v v hys t schmitt trigger hysteresis ? 0.1 v dd_hv_io x ??v v ol_s p slow, low level output voltage i ol =1.5ma ? ? 0.5 v v oh_s p slow, high level output voltage i oh = ?1.5 ma v dd_hv_io x ?0.8 ? ? v v ol_m p medium, low level output voltage i ol =2ma ? ? 0.5 v v oh_m p medium, high level output voltage i oh =?2ma v dd_hv_iox ?0.8 ? ? v v ol_f p fast, high level output voltage i ol =1.5ma ? ? 0.5 v v oh_f p fast, high level output voltage i oh = ?1.5 ma v dd_hv_io x ?0.8 ? ? v v ol_sym p symmetric, high level output voltage i ol =1.5ma ? ? 0.5 v v oh_sym p symmetric, high level output voltage i oh = ?1.5 ma v dd_hv_io x ?0.8 ? ? v i inj t dc injection current per pin ? ?1 ? 1 ma i pu p equivalent pull-up current v in =v il ?130 ? ? a v in =v ih ???10 i pd p equivalent pull-down current v in =v il 10 ? ? a v in =v ih ??130 i il p input leakage current (all bidirectional ports) t j = ?40 to +150 c -1 ? 1 ? a input leakage current (all adc input-only ports) -0.5 ? 0.5 input leakage current (shared adc input-only ports) -1 ? 1 v ilr p reset , low level input voltage ? ?0.1 2 ?0.35v dd_hv_io x v v ihr p reset , high level input voltage ? 0.65 v dd_hv_io x ?v dd_hv_iox +0.1 2 v v hysr d reset , schmitt trigger hysteresis ? 0.1 v dd_hv_io x ??v v olr d reset , low level output voltage i ol =2ma ? ? 0.5 v i pd d reset , equivalent pull-down current v in =v il 10 ? ? a v in =v ih ??130
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 83 3.10 supply current characteristics (cut2) current consumption data is given in table 18 . these specifications are design target s and are subject to change per device characterization. table 18. current consumption characteristics symbol parameter conditions min typ max unit i dd_lv_full +i dd_lv_pll t operating current 1.2 v supplies t j =ambient v dd_lv_cor =1.32v ?? 50ma+ 2.18 ma*f cpu [mhz] ma 1.2 v supplies t j = 150 ? c v dd_lv_cor =1.32v ?? 80ma+ 2.50 ma*f cpu [mhz] i dd_lv_typ +i dd_lv_pll t operating current 1.2 v supplies t j =ambient v dd_lv_cor =1.32v ?? 26ma+ 2.10 ma*f cpu [mhz] ma 1.2 v supplies t j = 150 ? c v dd_lv_cor =1.32v ?? 41ma+ 2.30 ma*f cpu [mhz] i dd_lv_typ +i dd_lv_pll 1 p operating current 1.2 v supplies t j =ambient v dd_lv_cor =1.32v ?? 279mama 1.2 v supplies t j = 150 ? c v dd_lv_cor =1.32v ?? 318ma i dd_lv_bist +i dd_lv_pll t operating current 1.2 v supplies during lbist (full lbist configuration) t j =ambient v dd_lv_cor =1.32v ?? tbd ma 1.2 v supplies t j = 150 ? c v dd_lv_cor =1.32v ?? tbd i dd_lv_stop t operating current in v dd stop mode t j =ambient v dd_lv_cor =1.32v ?? 50 ma tt j =55 ? c v dd_lv_cor =1.32v ?? 57 pt j = 150 ? c v dd_lv_cor =1.32v ?? 80 i dd_lv_halt t operating current in v dd halt mode t j =ambient v dd_lv_cor =1.32v ?? 58 ma tt j =55 ? c v dd_lv_cor =1.32v ?? 64 pt j = 150 ? c v dd_lv_cor =1.32v ?? 72
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 84 3.11 temperature sensor electrical characteristics 3.12 main oscillator electrical characteristics the device provides an oscillator/resonator driver. figure 6 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. i dd_hv_adc 2,3 t operating current t j = 150 ? c 120 mhz adc operating at 60 mhz v dd_hv_adc =3.6v ?? 10 ma i dd_hv_aref 3 t operating current t j = 150 ? c 120 mhz adc operating at 60 mhz v dd_hv_ref =3.6v ?? 3 ma t j = 150 ? c 120 mhz adc operating at 60 mhz v dd_hv_ref =5.5v ?? 5 i dd_hv_osc t operating current t j = 150 ? c 3.3 v supplies 120 mhz ? ? 900 ? a i dd_hv_flash 4 t operating current t j = 150 ? c 3.3 v supplies 120 mhz ?? 4 ma 1 enabled modules in 'typical mode': flexpw m0, etimer0/1/2, ctu, swg, dma, flex can0/1, linflex, ad c1, dspi0/1, pit, crc, pll0/1, i/o supply current excluded 2 internal structures hold the input voltage less than vdda + 1 .0 v on all pads powered by vdda supplies, if the maximum injection current specification is met (3 ma for all pins) and vdda is within the operati ng voltage specifications. 3 this value is the total current for both adcs. 4 vflash is only available in the calibration package. table 19. temperature sensor electrical characteristics symbol parameter conditions min max unit ? p accuracy t j = ?40 c to t a = 25 c ?10 10 c t j = t a to 125 c ?7 7 c t s d minimum sampling period ? 4 ? s table 18. current consumption characteristics (continued) symbol parameter conditions min typ max unit
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 85 figure 6. crystal oscillator and resonator connection scheme note xtal/extal must not be directly used to drive external circuits. figure 7. main oscillator electrical characteristics c l c l crystal xtal extal r p resonator xtal extal device device device xtal extal i r v dd v xoschsop t xoschssu v xtal v xoschs valid internal clock 90% 10% 1/f xoschs mtrans 1 0
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 86 3.13 fmpll electrical characteristics table 20. main oscillator electrical characteristics symbol parameter conditions 1 1 v dd = 3.3 v 10%, t j = ?40 to +150 c, unless otherwise specified. value unit min typ max f xoschs sr oscillator frequency ? 4.0 ? 40.0 mhz g mxoschs p oscillator transconductance v dd = 3.3 v 10% 4.5 ? 13.25 ma/v v xoschs d oscillation amplitude f osc = 4, 8, 10, 12, 16 mhz 1.3 ? ? v f osc =40mhz 1.1 ? ? v xoschsop d oscillation operating point ? ? 0.82 ? v i xoschs d oscillator consumption ? ? ? 3.5 ma t xoschssu t oscillator start-up time f osc = 4, 8, 10, 12 mhz 2 2 the recommended configuration for maxi mizing the oscillator margin are: xosc_margin = 0 for 4 mhz quartz xosc_margin = 1 for 8/16/40 mhz quartz ?? 6ms f osc =16, 40mhz 2 ?? 2 v ih sr input high level cmos schmitt trigger oscillator bypass mode 0.65 v dd ?v dd +0.4 v v il sr input low level cmos schmitt trigger oscillator bypass mode ?0.4 ? 0.35 v dd v table 21. fmpll electrical characteristics symbol parameter conditions min typ max unit f ref_crystal f ref_ext d fmpll reference frequency range 1 crystal reference 4 ? 40 mhz f pll_in d phase detector input frequency range (after pre-divider) ?4?16mhz f fmpllout d clock frequency range in normal mode ?4?120 2 mhz f free p free running frequency measured using clock division (typically ? 16) 20 ? 150 mhz f sys d on-chip fmpll frequency 2 ? 16 ? 120 mhz t cyc d system clock period ? ? ? 1 / f sys ns f lorl f lorh d loss of reference frequency window 3 lower limit 1.6 ? 3.7 mhz upper limit 24 ? 56 f scm d self-clocked mode frequency 4,5 ?20?tbdmhz t lock p lock time stable oscillator (f pllin = 4 mhz), stable v dd ? ? 200 s
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 87 t lpll d fmpll lock time 6, 7 ? ? ? 200 ? s t dc d duty cycle of reference ?40?60% c jitter t clkout period jitter 8,9,10,11 long-term jitter (avg. over 2 ms interval), f sys maximum ?6 ? 6 ns ? t pkjit t single period jitter (peak to peak) phi @ 120 mhz, input clock @ 4 mhz ? ? 175 ps phi @ 100 mhz, input clock @ 4 mhz ? ? 185 ps phi @ 80 mhz, input clock @ 4 mhz ? ? 200 ps ? t ltjit t long term jitter phi @ 16 mhz, input clock @ 4 mhz ??6ns f lck d frequency lock range ? ?6 ? 6 % f sys f ul d frequency un-lock range ? ?18 ? 18 % f sys f cs f ds d modulation depth center spread 0.25 ? 2.0 12 % f sys down spread ?0.5 ? -8.0 f mod d modulation frequency 13 ? ? ? 100 khz 1 considering operation with fmpll not bypassed. 2 with fm; the value does not include a possible +2% modulation 3 ?loss of reference frequency? window is the reference fr equency range outside of which the fmpll is in self clocked mode. 4 self clocked mode frequency is the frequency that the fm pll operates at when the reference frequency falls outside the f lor window. 5 f vco is the frequency at the output of the vco; its range is 256?512 mhz. f scm is the self-clocked mode frequency (free running frequency); its range is 20?150 mhz. f sys =f vco ? odf 6 this value is determined by the crystal manufacturer and board design. for 4 mhz to 20 mhz crystals specified for this fmpll, load capacitors should not exceed these limits. 7 this specification applies to the period required for th e fmpll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 8 this value is determined by the cr ystal manufacturer and board design. 9 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fmpll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 10 proper pc board layout procedures must be followed to achieve specifications. 11 values are with frequency modulation disabled. if frequ ency modulation is enabled, jitter is the sum of c jitter and either f cs or f ds (depending on whether center spread or down spread modulation is enabled). 12 this value is true when operating at frequencies above 60 mhz, otherwise f cs is 2% (above 64 mhz). 13 modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 khz. table 21. fmpll electrical characteristics (continued) symbol parameter conditions min typ max unit
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 88 3.14 16 mhz rc oscillator electrical characteristics 3.15 adc electrical characteristics the device provides a 12-bit successive approximatio n register (sar) analog-to-digital converter. figure 8. adc characteristics and error definitions 3.15.1 input impedance and adc accuracy to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenua ting the noise present on the inpu t pin; further, it sources c harge during the sampling phase, when the analog si gnal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to table 22. rc oscillator electrical characteristics symbol parameter conditions min typ max unit f rc p rc oscillator frequency t j =25c ? 16 ? mhz ? rcmvar p fast internal rc oscillator variation with respect to f rc . ???5% (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 1 lsb ideal =(vrefh-vrefl)/ 4096 = 3.3v/ 4096 = 0.806 mv total unadjusted error tue = +/- 6 lsb = +/- 4.84mv
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 89 be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq =1 / (f c ? c s ), where fc represents the conversion rate at the considered channel). to minimize the erro r induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s +r f +r l +r sw +r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 equation 4 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 9. input equivalent circuit a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivale nt circuit reported in figure 9 ): a charge sharing phenomenon is installed when the sampling phas e is started (a/d switch close). v a r s r f r l r sw r ad +++ + r eq -------------------------------------------------------------------------- - ? 1 2 -- -lsb ? r f c f r s r l r sw1 c p2 v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 90 figure 10. transient behavior during sampling phase in particular two different transient periods can be distinguished: ? a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 ? a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? v a1 c s c p1 c p2 ++ ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ? 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ?
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 91 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 11. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 ?? f c (nyquist) f f ? f 0 (anti-aliasing filtering condition) t c ?? 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 92 table 23. adc conversion characteristics symbol parameter conditions 1 1 v dd = 3.3 v, t j = ?40 to +150 c, unless otherwise specified and analog input voltage from v agnd to v aref . min typ max unit f ck sr adc clock frequency (depends on adc configuration) (the duty cycle depends on ad_ck 2 frequency) 2 ad_ck clock is always half of the adc module input cl ock defined via the auxiliary clock divider for the adc. ?3?60mhz f s sr sampling frequency ? ? ? 1.00 3 3 this is the maximum frequency t hat the analog portion of the adc can attain. a sustained conversion at this frequency is not possible. mhz t sample d sample time 4 60 mhz 383 ? ? ns t conv d conversion time 5 tbd 625 ? ? ns c s 6 d adc input sampling capacitance ? ? ? 7.32 pf c p1 6 d adc input pin capacitance 1 ? ? ? 5 (7) pf c p2 6 d adc input pin capacitance 2 ? ? ? 0.8 pf r sw1 6 d internal resistance of analog source v ref range=4.5to5.5v ? ? 0.3 k ? v ref range=3.0to3.6v ? ? 875 ? r ad 6 d internal resistance of analog source ? ? ? 825 ? inl p integral non linearity ? ?2 ? 2 lsb dnl p differential non linearity 8 ??1?2lsb ofs t offset error ? ?6 ? 6 lsb gne t gain error ? ?6 ? 6 lsb is1winj (cut2 only) (single adc channel) max leakage 150c ? ? 250 na max positive/negative injection ?3 ? 3 ma is1wwinj (cut2 only) (double adc channel) max leakage 150c ? ? 300 na max positive/negative injection |vref_ad0 - vref_ad1| < 150mv ?3.6 ? 3.6 ma snr t signal-to-noise ratio ? 67 ? ? db thd t total harmonic distortion ? tbd ? ? db sinad t signal-to-noise and distortion ? 65 ? ? db enob t effective number of bits ? 10.5 ? ? bits tue is1winj (cut2 only) p total unadjusted error for is1winj without current injection ?6 ? 6 lsb t with current injection ?8 ? 8 lsb tue is1wwinj (cut2 only) p total unadjusted error for is1wwinj without current injection ?8 ? 8 lsb t with current injection ?10 ? 10 lsb
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 93 3.16 flash memory electrical characteristics 4 during the sample time the input capacitance cs can be charged /discharged by the external source. the internal resistance of the analog source must allow the capacitan ce to reach its final voltage level within t sample . after the end of the sample time t sample , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t sample depend on programming. 5 this parameter does not include the sample time t sample , but only the time for determining the digital result and the time to load the result register with the conversion result. 6 see figure 9 . 7 for the 144-pin package. 8 no missing codes. table 24. flash memory program and erase electrical specifications no. symbol parameter min typ 1 1 typical program and erase times assume nominal supply values and operation at t j =25 c. these values are characterized, but not tested. factory avg 2 2 factory average program and erase times represent the ef fective performance averaged over > 1024 pages or blocks, and are provided for factory throughput estimation assu ming < 100 program/erase cycles, nominal supply values and operation at t j =25 c. these values are characterized, but not tested. initial max 3 3 initial max program and erase times provide guidance for time-out limits used in the factory and apply for < 100 program/erase cycles, nominal supply values and operation at t j =25 c. these values are verified at production test. lifetime max 4 4 lifetime max program and erase times apply across the voltage, temperature, and cycling range of product life. these values are characterized, but not tested. unit 1t dwprogram * 5 5 see notes for individual specifications, as shown in column headings. double word (64 bits) program time 6 6 actual hardware programming times. these do not include software overhead. ? 39 ? ? 500 s 2t pprogram * 5 page(128 bits) program time 6 ? 48 53 100 500 s 3t 16kpperase * 5 16 kb block pre-program and erase time ? tbd tbd 500 5000 ms 4t 48kpperase * 5 48 kb block pre-program and erase time ? tbd tbd 750 5000 ms 5t 64kpperase * 5 64 kb block pre-program and erase time ? tbd tbd 900 5000 ms 6t 128kpperase * 5 128 kb block pre-program and erase time ? tbd tbd 1300 7500 ms 7t 256kpperase * 5 256 kb block pre-program and erase time ? tbd tbd 2600 15000 ms table 25. flash memory timing symbol parameter value unit min typ max t res d time from clearing the mcr-esus or psus bit with ehv = 1 until done goes low ? ? 100 ns t done d time from 0 to 1 transition on the mcr-ehv bit initiating a program/erase until the mcr-done bit is cleared ?? 5ns
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 94 3.17 swg electrical characteristics 3.18 ac specifications 3.18.1 pad ac specifications table 26. flash memory module life no. symbol parameter value unit min typ max 1 p/e c number of program/erase cycles per block for 16 kb, 48 kb, and 64 kb blocks over the operating temperature range 1 1 operating temperature range is t j from ?40 c to 150 c. typical endurance is evaluated at 25 ? c. product qualification is performed to the minimu m specification. for additional inform ation on the freescale definition of typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 100000 ? ? cycles 2 p/e c number of program/erase cycles per block for 128 kb and 256 kb blocks over the operating temperature range 1 1000 100000 2 2 typical p/e cycles is 100,000 cycles for 128 kb and 256 kb blocks. for additi onal information on the freescale definition of typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . ?cycles 3 retention c minimum data retention at 85 c average ambient temperature 3 blocks with 0?1,000 p/e cycles blocks with 1,001?10,000 p/e cycles blocks with 10,001?100,000 p/e cycles 3 ambient temperature averaged over duration of applicat ion, not to exceed product operating temperature range. 20 10 5 ? ? ? ? ? ? years table 27. swg electrical characteristics symbol parameter min max unit sinad d signal-to-noise ratio plus distortion 50 ? db table 28. pad ac specifications (3.3 v , ipp_hve = 0 ) 1 no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew 3 (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max 1 slow t3 ?40??40?? 40.01? 2 25 3 ?40??50?? 20.01? 2 50 3 ? 40 ? ? 75 ? ? 2 0.01 ? 2 100 3 ? 40 ? ? 100 ? ? 2 0.01 ? 2 200
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 95 figure 12. pad output delay 3.19 reset sequence this section shows the duration for different reset sequences. it describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences. 2 medium t 1 ? 15 ? ? 12 ? ? 40 2.5 ? 7 25 1 ? 15 ? ? 25 ? ? 20 2.5 ? 7 50 1 ? 15 ? ? 40 ? ? 13 2.5 ? 7 100 1 ? 15 ? ? 70 ? ? 7 2.5 ? 7 200 3 fast t 1 ? 6 ? ? 4 ? ? 72 3 ? 40 25 1?6??7??557?40 50 1?6??12??407?40 100 1?6??18??257?40 200 4symmetrict1 ? 8 ?? 5 ??50 3 ?25 25 5 pull up/down (3.6 v max) d?????tbd?????? 50 1 propagation delay from v dd_hv_io x /2 of internal signal to pchannel/nchannel switch-on condition. 2 slope at rising/falling edge. 3 data based on characterization results, not tested in production. table 28. pad ac specifications (3.3 v , ipp_hve = 0 ) 1 (continued) no. pad tswitchon 1 (ns) rise/fall 2 (ns) frequency (mhz) current slew 3 (ma/ns) load drive (pf) min typ max min typ max min typ max min typ max v dde /2 v oh v ol rising edge output delay falling edge output delay pad data input pad output
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 96 3.19.1 reset sequence duration table 29 specifies the minimum and the maximum reset sequence dura tion for the five different reset sequences described in section 3.19.2, reset sequence description . 3.19.2 reset sequence description the figures in this section show the intern al states of the chip during the five di fferent reset sequences. the doted lines in the figures indicate the starting point and the end point for which the duration is specified in table 29 . the start point and end point conditions as well as the reset trigger mapping to the different reset sequences is specified in section 3.19.3, reset sequence trigger mapping . with the beginning of drun mode the first instruction is fetche d and executed. at this point application execution starts and the internal reset sequence is finished. the figures below show the internal states of the chip during the execution of the re set sequence and the po ssible states of th e signal pin reset . note reset is a bidirectional pin. the voltage level on this pin can either be driven low by an external reset generator or by the chip internal reset circuitry. a high level on this pin can only be generated by an external pull up resist or which is strong enough to overdrive the weak internal pull down resistor. the rising edge on reset in the following figures indicates the time when the de vice stops driving it low. the reset sequence durations given in table table 29 are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping reset asserted low beyond the last phase3. table 29. reset sequences no. symbol parameter conditions t reset unit min typ max 1 1 the maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of reset by an external reset generator. 1t drb cc destructive reset sequence, bist enabled cut1 52 60 65 ms cut2 40 47 51 ms 2t dr cc destructive reset sequence, bist disabled ? 500 4200 5000 ? s 3t erlb cc external reset sequence long, bist enabled cut1 52 57 65 ms cut2 41 45 49 ms 4t frl cc functional reset sequence long ? 35 150 400 ? s 5t frs cc functional reset sequence short ? 1 4 10 ? s
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 97 figure 13. destructive reset sequence, bist enabled figure 14. destructive reset sequence, bist disabled figure 15. external reset sequence long, bist enabled phase3 bist phase1,2 phase0 phase1,2 phase3 establish irc and pwr flash init device config self test setup drun lbist mbist flash init device config application execution t drb, min < t reset < t drb, max reset sequence start condition reset sequence trigger reset_b reset phase3 phase1,2 phase0 establish irc and pwr flash init device config drun application execution t dr, min < t reset < t dr, max reset sequence trigger reset sequence start condition reset_b reset phase3 bist phase1,2 phase1,2 phase3 flash init device config self test setup drun lbist mbist flash init device config application execution t erlb, min < t reset < t erlb, max reset sequence trigger reset sequence start condition reset_b reset
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 98 figure 16. functional reset sequence long figure 17. functional reset sequence short the reset sequences shown in figure 16 and figure 17 are triggered by functional reset events. reset is driven low during these two reset sequences only if the corresponding functional re set source (which triggered the reset sequence) was enabled to drive reset low for the duration of th e internal reset sequence 1 . 3.19.3 reset sequence trigger mapping the following table shows the possible tri gger events for the different reset sequen ces. it specifies the reset sequence start conditions as well as the reset sequ ence end indications that are the basis for the timing data provided in table 29 . 1.see rgm_fbre register for more details. phase3 phase1,2 flash init device config drun application execution t frl, min < t reset < t frl, max reset sequence trigger reset sequence start condition reset_b reset phase3 drun application execution t frs, min < t reset < t frs, max reset sequence trigger reset sequence start condition reset_b reset
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 99 table 30. reset sequence trigger ? reset sequence reset sequence trigger reset sequence start condition reset sequence end indication reset sequence destructiv e reset sequence, bist enabled 1 1 whether bist is executed or not depends on the chip configuration data stored in the shadow sector of the nvm. destructiv e reset sequence, bist disabled 1 external reset sequenc e long, bist enabled functiona l reset sequenc e long functiona l reset sequenc e short all internal destructive reset sources (lvds or internal hvd during power-up and during operation) section 3.1 9.4.1, destructive reset release of reset 2 2 end of the internal reset sequence (as specified in ta bl e 2 9 ) can only be observed by release of reset if it is not held low externally beyond the end of the internal sequence which would pr olong the internal reset phase3 till reset is released externally. triggers cannot trigger cannot trigger cannot trigger assertion of reset 3 3 the assertion of reset can only trigger a reset sequence if the device was running (reset released) before. reset does not gate a destructive reset sequence, bist enabled or a destructive reset sequence, bist disabled . however, it can prolong these sequences if reset is held low externally beyond the end of the internal sequence (beyond phase3). section 3.1 9.4.2, external reset via reset cannot trigger triggers 4 4 if reset is configured for long reset (default) and if bist is enabled via chip configuration data stored in the shadow sector of the nvm. triggers 5 5 if reset is configured for long reset (default) and if bist is disabled via chip configuration data stored in the shadow sector of the nvm. triggers 6 6 if reset is configured for short reset all internal functional reset sources configured for long reset sequence starts with internal reset trigger release of reset 7 7 internal reset sequence can only be observed by state of reset if bidirectional reset functionality is enabled for the functional reset source which triggered the reset sequence. cannot trigger cannot trigger triggers cannot trigger all internal functional reset sources configured for short reset cannot trigger cannot trigger cannot trigger triggers
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 100 3.19.4 reset sequence ? start condition the impact of the voltage thresholds on the starting point of the internal reset sequence are becoming important if the voltage rails / signals ramp up with a ve ry slow slew rate compared to the overall reset sequence duration. 3.19.4.1 destructive reset figure 18 shows the voltage threshold that determines the start of the destructive reset sequence, bist enabled and the start for the destructive reset sequence, bist disabled . figure 18. reset sequence start for destructive resets 3.19.4.2 external reset via reset figure 19 shows the voltage thresholds that determine the start of the reset sequences initiated by the assertion of reset as specified in table 30 . table 31. voltage thresholds variable name value v min refer to ta bl e 1 6 v max refer to ta bl e 1 6 supply rail vdd_hv_pmu t reset, max starts here t reset, min starts here supply rail v max t v v min
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 101 figure 19. reset seque nce start via reset assertion 3.19.5 external watchdog window if the application design requires the use of an external watchdog the data provided in section 3.19, reset sequence can be used to determine the correct positioning of the trigger window for the external watchdog. figure 20 shows the relationships between the minimum and the maximum duration of a given reset sequen ce and the position of an external watchdog trigger window. figure 20. reset sequence - external watchdog trigger window position 3.20 ac timing characteristics ac test timing conditions: unless otherwise noted, all test conditio ns are as follows: ? tj = ?40 to 150 c ? supply voltages as specified in table 9 t reset, max starts here t reset, min starts here reset_b 0.65 * vdd_hv_io t v 0.35 * vdd_hv_io reset external watchdog window closed earliest application start latest application start internal reset sequence start condition (signal or voltage rail) external watchdog window open t reset, min t reset, max t wdstart, min t wdstart, max external watchdog window closed external watchdog window open basic application init basic application init application time required to prepare watchdog trigger watchdog needs to be triggered within this window watchdog trigger application running application running
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 102 ? input conditions: all inputs: tr, tf = 1 ns ? output loading: all outputs: 50 pf 3.20.1 reset pin characteristics the pxs20 implements a dedi cated bidirectional reset pin. figure 21. start-up reset requirements figure 22. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 103 3.20.2 wkup/nmi timing 3.20.3 ieee 1149.1 jtag interface timing table 32. reset electrical characteristics no. symbol parameter conditions 1 1 v dd = 3.3 v 10%, t j = ?40 to +150 c, unless otherwise specified min typ max unit 1t tr d output transition time output pin 2 2 c l includes device and package capacitance (c pkg <5pf). c l = 25pf ? ? 12 ns c l = 50pf ? ? 25 c l = 100pf ? ? 40 2w frst p nreset input filtered pulse ? ? ? 40 ns 3w nfrst p nreset input not filtered pulse ? 500 ? ? ns table 33. wkup/nmi glitch filter no. symbol parameter min typ max unit 1w fnmi d nmi pulse width that is rejected ? ? 45 ns 2w nfnmi d nmi pulse width that is passed 205 ? ? ns table 34. jtag pin ac electrical characteristics no. symbol parameter conditions min max unit 1t jcyc d tck cycle time ? 62.5 ? ns 2t jdc d tck clock pulse width (measured at v dde /2) ? 40 60 % 3t tckrise d tck rise and fall times (40%?70%) ? ? 3 ns 4t tmss, t tdis d tms, tdi data setup time ? 5 ? ns 5t tmsh, t tdih d tms, tdi data hold time ? 25 ? ns 6t tdov d tck low to tdo data valid ? ? 20 ns 7t tdoi d tck low to tdo data invalid ? 0 ? ns 8t tdohz d tck low to tdo high impedance ? ? 20 ns 11 t bsdv d tck falling edge to output valid ? ? 50 ns 12 t bsdvz d tck falling edge to output valid out of high impedance ? ? 50 ns 13 t bsdhz d tck falling edge to output high impedance ? ? 50 ns 14 t bsdst d boundary scan input valid to tck rising edge ? 50 ? ns 15 t bsdht d tck rising edge to boundary scan input invalid ? 50 ? ns
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 104 figure 23. jtag test clock input timing figure 24. jtag test access port timing tck 1 2 2 3 3 tck 4 5 6 7 8 tms, tdi tdo
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 105 figure 25. jtag boundary scan timing 3.20.4 nexus timing table 35. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. no. symbol parameter conditions min max unit 1t mcyc d mcko cycle time ? 15.6 ? ns 2t mdc d mcko duty cycle ? 40 60 % 3t mdov d mcko low to mdo, mseo , evto data valid 2 2 for all nexus modes except ddr mode, mdo, mseo , and evto data is held valid until next mcko low cycle. ? ?0.1 0.25 t mcyc 4t evtipw devti pulse width ? 4.0 ? t tcyc 5t evtopw devto pulse width ? 1 t mcyc 6t tcyc d tck cycle time 3 ? 62.5 ? ns 7t tdc d tck duty cycle ? 40 60 % 8t ntdis, t ntmss d tdi, tms data setup time ? 8 ? ns 9 t ntdih, t ntmsh d tdi, tms data hold time 5 ? ns 10 t jov d tck low to tdo/rdy data valid 0 25 ns tck output signals input signals output signals 11 12 13 14 15
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 106 figure 26. nexus output timing figure 27. nexus double data rate (ddr) mode output timing 3 the system clock frequency needs to be f our times faster than the tck frequency. 1 2 mcko mdo mseo evto output data valid 3 evti 4 5 mcko mdo, mseo mdo/mseo data are valid during mcko rising and falling edge
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 107 figure 28. nexus tdi, tms, tdo timing 3.20.5 external interrupt timing (irq pin) table 36. external interrupt timing no. symbol parameter conditions min max unit 1t ipwl d irq pulse width low ? 3 ? t cyc 2t ipwh d irq pulse width high ? 3 ? t cyc 3t icyc d irq edge to edge time 1 1 applies when irq pins are configured for rising edge or falling edge events, but not both. ?6?t cyc tdo/rdy 8 9 tms, tdi 10 tck 6 7
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 108 figure 29. external interrupt timing 3.20.6 dspi timing table 37. dspi timing no. symbol parameter conditions min max unit 1t sck d dspi cycle time master (mtfe = 0) 62 ? ns d slave (mtfe = 0) 62 ? d slave receive only mode 1 16 ? 2t csc d pcs to sck delay ? 16 ? ns 3t asc d after sck delay ? 16 ? ns 4t sdc d sck duty cycle ? t sck /2 - 10 t sck /2 + 10 ns 5t a d slave access time ss active to sout valid ? 40 ns 6t dis d slave sout disable time ss inactive to sout high-z or invalid ? 10 ns 7t pcsc d pcsx to pcss time ? 13 ? ns 8t pasc dpcss to pcsx time ? 13 ? ns 9t sui d data setup time for inputs master (mtfe = 0) 20 ? ns slave 2? master (mtfe = 1, cpha = 0) 5? master (mtfe = 1, cpha = 1) 20 ? 10 t hi d data hold time for inputs master (mtfe = 0) ?5 ? ns slave 4 ? master (mtfe = 1, cpha = 0) 11 ? master (mtfe = 1, cpha = 1) ?5 ? 11 t suo d data valid (after sck edge) master (mtfe = 0) ? 4 ns slave ? 23 master (mtfe = 1, cpha = 0) ? 12 master (mtfe = 1, cpha = 1) ? 4 irq 1 2 3
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 109 figure 30. dspi classic spi timing ? master, cpha = 0 12 t ho d data hold time for outputs master (mtfe = 0) ?2 ? ns slave 6 ? master (mtfe = 1, cpha = 0) 6 ? master (mtfe = 1, cpha = 1) ?2 ? 1 slave receive only mode can operate at a maximum frequency of 60 mhz. in this mode, the dspi can receive data on sin, but no valid data is transmitted on sout. table 37. dspi timing (continued) no. symbol parameter conditions min max unit data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol=0) (cpol=1) 3 2 note: the numbers shown are referenced in ta bl e 3 7 .
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 110 figure 31. dspi classic spi timing ? master, cpha = 1 figure 32. dspi classic spi timing ? slave, cpha = 0 data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol=0) (cpol=1) note: the numbers shown are referenced in ta b l e 3 7 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol=0) (cpol=1) note: the numbers shown are referenced in ta b l e 3 7 .
electrical characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 111 figure 33. dspi classic spi timing ? slave, cpha = 1 figure 34. dspi modified transfer format timing ? master, cpha = 0 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note: the numbers shown are referenced in ta bl e 3 7 . pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol=0) (cpol=1) note: the numbers shown are referenced in ta b l e 3 7 .
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 112 figure 35. dspi modified transfer format timing ? master, cpha = 1 figure 36. dspi modified transfer format timing ? slave, cpha = 0 pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol=0) (cpol=1) note: the numbers shown are referenced in ta b l e 3 7 . last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol=0) (cpol=1) 12 note: the numbers shown are referenced in ta b l e 3 7 .
package characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 113 figure 37. dspi modified transfer format timing ? slave, cpha = 1 figure 38. dspi pcs strobe (pcss ) timing 4 package characteristics 4.1 package mechanical data 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol=0) (cpol=1) note: the numbers shown are referenced in ta bl e 3 7 . pcsx 7 8 pcss note: the numbers shown are referenced in ta bl e 3 7 .
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package characteristics freescale semiconductor 114 figure 39. 144 lqfp package mechanical drawing (1 of 2)
package characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 115 figure 40. 144 lqfp package mechanical drawing (2 of 2)
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice package characteristics freescale semiconductor 116 figure 41. 257 mapbga package mechanical drawing (1 of 2)
package characteristics pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice freescale semiconductor 117 figure 42. 257 mapbga package mechanical drawing (2 of 2)
pxs20 microcontroller data sheet, rev. 1 preliminary?subject to change without notice ordering information freescale semiconductor 118 5 ordering information figure 43. pxs20 orderable part number description 6 document revision history table 39 summarizes revisions to this document. table 38. pxs20 orderable part number summary part number flash/sram package speed (mhz) mpxs2005vlq80 512 kb / 128 kb 144 lqfp (20 mm x 20 mm) 80 mpxs2010vlq80 1 mb / 128 kb 144 lqfp (20 mm x 20 mm) 80 mpxs2010vmm80 1mb / 128kb 257 mapbga (14 mm x 14 mm) 80 mpxs2010vlq120 1 mb / 128 kb 144 lqfp (20 mm x 20 mm) 120 mpxs2010vmm120 1mb / 128kb 257 mapbga (14 mm x 14 mm) 120 table 39. revision history revision date description of changes 1 30 sep 2011 initial release. mpx 20 note: not all options are available on all devices. see ta bl e 3 8 for more information. s qualification status brand family class flash memory size temperature range v = ?40 c to 105 c operating frequency 80 = 80 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification (engineering samples) m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 10 v temperature range mm package identifier 120 r operating frequency tape and reel indicator package identifier lq = 144 lqfp 120 = 120 mhz (ambient) mm = 257 mapbga family d = display graphics n = connectivity/network r = performance/real time control s=safety flash memory size 05 = 512 kb 10 = 1 mb
how to reach u s : home page: www.freescale.com web s upport: http://www.freescale.com/support u s a/europe or location s not li s ted: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com a s ia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2011. all rights reserved. pxs20 rev. 1 09/2011

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