THC63LVDR84B_rev.2.2_e copyright?2011 thine electronics, inc. 1/10 thine electronics, inc. THC63LVDR84B lvds 24bit color host-lcd panel in terface receiver (rising edge clock) general description the THC63LVDR84B receiver supports wide vcc range(2.5~3.6v). at single 2.5v supply, the THC63LVDR84B reduces emi and power consump- tion. the THC63LVDR84B receiver convert the four lvds(low voltage differentia l signaling) data streams back into 24bits of cmos/ttl data with rising edge clock. at a transmit clock frequency of 85mhz, 24bits of rgb data and 4bits of lcd timing and control data (hsync, vsync, cntl1, cn tl2) are transmitted at a rate of 2.3gbps. features ? wide dot clock and wide vcc range: ? rising edge clock ? pll requires no external components ? rx power consumption < 80mw @vcc 2.5v, 65mhz grayscale ? power-down mode ? low profile 56 lead tssop package ? pin compatible with ds90cr286atmd 15 to 20 20 to 70 70 to 85 2.5 to 2.7 n/a available n/a 2.7 to 3.0 available available n/a 3.0 to 3.6 available available available n/a : not available clock frequency[mhz] vcc[v] block diagram lvds to ttl parallel pll ra +/- rb +/- rc +/- rd +/- rclk +/- /pdwn ra0-6 rc0-6 rd0-6 receiver (15 to 85mhz) cmos/ttl rb0-6 output clock (lvds) 15 to 85mhz data (lvds) (105-595mbit/on each lvds channel) 7 7 7 7 clock out THC63LVDR84B
copyright?2011 thine electronics, inc. 2/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e pin out pin description pin name pin # type description ra+, ra- 10, 9 lvds in lvds data inputs rb+, rb- 12, 11 lvds in rc+, rc- 16, 15 lvds in rd+, rd- 20, 19 lvds in rclk+, rclk- 18, 17 lvds in lvds clock inputs ra0~ra6 27,29,30, 32,33,35,37 out pixel data outputs rb0~rb6 38,39,43, 45,46,47,51 out rc0~rc6 53,54,55,1,3,5,6 out rd0~rd6 7,34,41,42,49,50,2 out clkout 26 out pixel clock output /pdwn 25 in h: normal operation l: power down (all outputs are pulled to ground) vcc 31,40,48,56 power power supply pins for ttl outputs and digital circuitry gnd 4,28,36,44,52 ground ground pins fo r ttl outputs and digital circuitry lvdsvcc 13 power power supply pin for lvds inputs lvdsgnd 8,14,21 ground ground pins for lvds inputs pllvcc 23 power power supply pin for pll circuitry pllgnd 22,24 ground ground pins for pll circuitry 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 rc3 rd6 rc4 gnd rc5 rc6 rd0 lvdsgnd ra- ra+ rb- rb+ lvdsvcc lvdsgnd rc- rc+ rclk- rclk+ rd- rd+ lvdsgnd pllgnd pllvcc pllgnd /pdwn clkout ra0 gnd vcc rc2 rc1 rc0 gnd rb6 rd5 rd4 vcc rb5 rb4 rb3 gnd rb2 rd3 rd2 vcc rb1 rb0 ra6 gnd ra5 rd1 ra4 ra3 vcc ra2 ra1 THC63LVDR84B
copyright?2011 thine electronics, inc. 3/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e absolute maximum ratings recommended operating conditions electrical characteristics cmos/ttl dc specifications vcc = vcc = pvcc = lvcc lvds receiver dc specifications vcc = vcc = pvcc = lvcc supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) cmos/ttl output voltage -0.3v ~ (v cc + 0.3v) lvds receiver input voltage -0.3v ~ (v cc + 0.3v) junction temperature +125 storage temperature range -55 ~ +150 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 1.9w parameter min. max. units all supply voltage 2.5 3.6 v operating ambient temperature -10 70 clock frequency vcc=2.5v to 2.7v 20 70 mhz vcc=2.7v to 3.0v 15 70 mhz vcc=3.0v to 3.6v 15 85 mhz symbol parameter conditions min. typ. max. units v ih high level input voltage 2.0 vcc v v il low level input voltage gnd 0.8 v v oh1 high level output voltage vcc= 3.0v ~ 3.6v i oh = -4ma 2.4 v v ol1 low level output voltage vcc = 3.0v ~ 3.6v i ol = 4ma 0.4 v v oh2 high level output voltage vcc= 2.5v ~ 3.0v i oh = -2ma 2.1 v v ol2 low level output voltage vcc = 2.5v ~ 3.0v i ol = 2ma 0.4 v i in input current a symbol parameter conditions min. typ. max. units v th differential input high threshold vic = +1.2v 100 mv v tl differential input low threshold -100 mv i in input current v in = +2.4v/0v vcc = 3.6v a c c c c c c 0v vin vcc ? 10 10
copyright?2011 thine electronics, inc. 4/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e supply current vcc = vcc = pvcc = lvcc symbol parameter condition(*) typ. max. units i rccg receiver supply current 16grayscale pattern cl=8pf, vcc=3.3v f = 65mhz 41 53 ma f = 85mhz 52 64 ma cl=8pf, vcc=2.5v f = 65mhz 30 42 ma i rccw receiver supply current worst case pattern cl=8pf, vcc=3.3v f = 65mhz 72 94 ma f = 85mhz 84 96 ma cl=8pf, vcc=2.5v f = 65mhz 42 64 ma i rccs receiver power down supply current /pdwn = l 10 a clkin rx0 rx1 rx2 rx3 rx4 rx5 rx6 16 gray scale pattern clkin even rxin odd rxin worst case pattern
copyright?2011 thine electronics, inc. 5/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e switching characteristics vcc = vcc = pvcc = lvcc symbol parameter min. typ. max. units t rcp clk out period vcc = 2.5 - 2.7v 14.28 t 50.0 ns vcc = 2.7 - 3.0v 14.28 t 66.6 ns vcc = 3.0 - 3.6v 11.76 t 66.6 ns t rch clk out high time 3t/7 ns t rcl clk out low time 4t/7 ns t rcd rclk +/- to clk out delay 5t/7 ns t rs ttl data setup to clk out 0.35t-0.3 ns t rh ttl data hold from ckl out 0.45t-1.6 ns t tlh ttl low to high transition time 2.0 3.0 ns t thl ttl high to low transition time 1.8 3.0 ns t rip1 input data position0 (t = 11.76ns) -0.4 0.0 0.4 ns t rip0 input data position1 (t = 11.76ns) t/7-0.4 t/7 t/7+0.4 ns t rip6 input data position2 (t = 11 .76ns) 2t/7-0.4 2t/7 2t/7+0.4 ns t rip5 input data position3 (t = 11 .76ns) 3t/7-0.4 3t/7 3t/7+0.4 ns t rip4 input data position4 (t = 11 .76ns) 4t/7-0.4 4t/7 4t/7+0.4 ns t rip3 input data position5 (t = 11 .76ns) 5t/7-0.4 5t/7 5t/7+0.4 ns t rip2 input data position6 (t = 11 .76ns) 6t/7-0.4 6t/7 6t/7+0.4 ns t rpll phase lock loop set 10.0 ms ac timing diagrams ttl output 8pf 20% 80% 20% 80% t tlh t thl ttl output ttl output load
copyright?2011 thine electronics, inc. 6/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e ac timing diagrams v diff = 0v rx+/- rx6 rx5 rx4 rx3 rx2 rx1 rx0 v diff = 0v t rip2 t rip3 t rip4 t rip5 t rip6 t rip0 t rip1 t rcd rclk+ t rcl t rch t rcp clkout t rs t rh data valid rx0 - rx6 vcc/2 vcc/2 vcc/2 vcc/2 vcc/2 vcc/2 note: 1) vdiff = (ra+) - (ra-), ...... (rclk+) - (rclk-) data valid
copyright?2011 thine electronics, inc. 7/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e ac timing diagrams phase lock loop set time vcc t rpll /pdwn 3.6v rclk+/- clkout vcc/2 vcc/2 vcc/2
THC63LVDR84B_rev.2.2_e copyright?2011 thine electronics, inc. 8/10 thine electronics, inc. note 1)power on sequence power on lvds-tx after THC63LVDR84B. 2)cable connection and disconnection don't connect and disconnec t the lvds cable, when the powe r is supplied to the system. 3)gnd connection connect the each gnd of the pcb wh ich lvds-tx and THC63LVDR84B on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 4)multi drop connection multi drop connection is not recommended. 5)asynchronous use asynchronous use such as following systems are not recommended. THC63LVDR84B lvds-tx THC63LVDR84B tclk+ tclk- lvds-tx lvds-tx ic clkout clkout data data THC63LVDR84B THC63LVDR84B ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVDR84B THC63LVDR84B ic tclk+ tclk- tclk+ tclk- clkout data data ic
copyright?2011 thine electronics, inc. 9/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e package 0.50 typ 0.17~0.27 14.00 0.10 1 0.25 gage plane 0.60 0.15 1.00 0.10 0.05 0.95 0.05 1.20 max detail of lead end unit:mm 0~8 s 0.10 s 8.10 0.10 6.10 0.10
copyright?2011 thine electronics, inc. 10/10 thine electronics, inc. THC63LVDR84B_rev.2.2_e thine electronics, inc. e-mail: sales@thine.co.jp notices and requests 1. the product specifications described in this mate rial are subject to cha nge without prior notice. 2. the circuit diagrams de scribed in this material are exampl es of the application which may not always apply to the customer's design. we are not responsible for possibl e errors and omissions in this material. please note if errors or omissions s hould be found in this material, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other proprietary. c opying or disclosing to third parties the contents of this material without our prior pe rmission is prohibited. 4. note that if infringement of any third party's industrial ow nership should occur by using this product, we will be exempted fr om the responsibility unless it di rectly relates to the production process or functions of the product. 5. this product is presumed to be used for gene ral electric equipment, not for the applications which require very high reliabili ty (including medical equipmen t directly concerning people's life, aerospace equipment, or nuc lear control equipment). also, when using this product for the equipment concerned with the control and safety of the transportation means, the traffic signal equipment, or various types of safety equipment, please do it after applying appropriate measures to the product. 6. despite our utmost efforts to im prove the quality and re liability of the product, faults will occur with a certain small probability, which is inevitable to a se mi-conductor product. therefore, you are encouraged to have sufficiently redundant or error preventive de sign applied to the use of the product so as not to have our pr oduct cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by th emselves if this produc t falls under the category of strategic goods under the foreign exch ange and foreign trade control law.
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