61108hkim/12299rm (ot) no.6042-1/9 stk672-120-e overview the stk672-120-e is a unipolar fixed-current chopper type 2-phase stepping motor driver hybrid ic. it features power mosfets in the output stage and a built-in phase signal dist ribution ic. the incorporation of a phase distribution ic allows the stk672-120-e to control the speed of the motor ba sed on the frequency of an external input clock signal. it supports two types of excitation for motor control: 2-phase ex citation and 1-2 phase excitation. it also provides a function for switching the motor direction. applications ? two-phase stepping motor drive in send/receive facsimile units ? paper feed in copiers, industrial robots, and other ap plications that require 2-ph ase stepping motor drive features ? the motor speed can be controlled by the frequency of an external clock signal (the clock pin signal). ? the excitation type is switched according to the state (low or high) of the mode pin. the m ode is set to 2-phase or 1-2 phase excitation on the rising edge of the clock signal. ? a motor direction switching pin (the cwb pin) is provided. ? all inputs are schmitt inputs and 40k (typical: ?50 to +100%) pull-up resistors are built in. ? the motor current can be set by changing the vref pin voltage. since a 0.165 current detection resistor is built in, a current of 1a is set for each 0.165v of applied voltage. ? the input frequency range for the clock signal used for motor speed co ntrol is 0 to 25khz. ? supply voltage ranges: v cc = 10 to 42v, v dd = 5.0v 5% ? this ic supports motor operating currents of up to 2.4a at tc = 105c, and of up to 4.0a at tc = 25c. ordering number : EN6042A thick-film hybrid ic unipolar fixed-current c hopper (self-excited pwm) scheme and built-in phase signal distribution ic two-phase stepping motor driver (square wave drive) ou tput current 2.4a specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
stk672-120-e no.6042-2/9 specifications maximum ratings at tc = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc max no signal 52 v maximum supply voltage 2 v dd max no signal -0.3 to +7.0 v input voltage v in max logic input pins -0.3 to +7.0 v output current i oh max v dd = 5v, clock 200hz 4.0 a repeated avalanche capacity ear max 36 mj allowable power dissipation pd max with an arbitrarily large heat sink. per mosfet 8.5 w operating substrate temperature tc max 105 c junction temperature tj max 150 c storage temperature tstg -40 to +125 c allowable operating ranges at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage 1 v cc with signals applied 10 to 42 v maximum supply voltage 2 v dd with signals applied 5.0 5% v input voltage v ih 0 to v dd v output current 1 i oh 1 tc = 105c, clock 200hz 2.4 a output current 2 i oh 2 tc = 80c, clock 200hz see the motor curren (i oh ) derating curve 3.0 a clock frequency f cl minimum pulse width: 20 s 0 to 25 khz phase driver withstand voltage v dss i d = 1ma (tc = 25c) 100 min v electrical characteristics at tc = 25 c, v cc = 24v, v dd = 5v rating parameters symbols conditions min typ max unit v dd supply current i cco clock = gnd 2.6 6 ma output average current ioave with r/l = 3 /3.8mh in each phase vref = 0.176v 0.56 0.62 0.69 a fet diode forward voltage vdf if = 1a (r l = 23 ) 1.1 1.7 v output saturation voltage vsat r l = 23 0.4 0.56 v high-level input voltage v ih pins 6 to 9 (4 pins) 4.0 v low-level input voltage v il pins 6 to 9 (4 pins) 1.0 v input current i il with pins 6 to 9 at the ground level. pull-up resistance: 40k (typical) 62 125 250 a vref input voltage v rh pin 12 0 3.5 v vref input bias current i ib with pin 12 at 1v 50 500 na note: a fixed-voltage power supply must be used. package dimensions unit:mm (typ) 4167 1 12 46.6 41.2 12.7 25.5 (9.6) 11 2=22 3.6 0.5 2.0 8.5 4.0 0.4 2.9 1.0
stk672-120-e no.6042-3/9 internal equivalent circuit block diagram mode clock cwb resetb vref sp v dd 10 8 9 7 6 12 11 off time setting phase advance counter excitation mode selection phase excitation signal generation chopping circuit aab bbb 54 32 f1 f2 f3 f4 r1 r2 1 + - + - rsa vrefb c2 sub vrefa c1 gnd rsb itf02596
stk672-120-e no.6042-4/9 sample application circuit ? to minimize noise in the 5v system, lo cate the ground side of ca pacitor co2 in the above circuit as close as possible to pin 1 of the ic. ? insert resistor ro3 (47 to 100 ) so that the discharge energy from capacito r co4 is not directly applied to the cmos ic in this hybrid device. if the diode d1 has vf characteristics with vf less than or equal to 0.6v (when if = 0.1a), this will be smaller than the cmos ic input pin diode vf . if this is the case ro3 may be replaced with a short without problem. ? standard or hc type input levels are used for the pin 7, 8, and 9 inputs. ? if open-collector type circuits are used for the pin 7, 8, and 9 inputs, these circuit will be in the high-impedance state for high level inputs. as a result, chopping circuit noise ma y cause the input circuits to operate incorrectly. to prevent incorrect operation due to such noise, capacitors with values between 470 and 1000pf must be connected between pins 7 and 11, 8 and 11, and 9 and 11. (a capacitor with a value between 470 and 1000pf must be connected between pins 6 and 11 as well if an open-collector output ic is used for the resetb pin (pin 6) input.) ? taking the input bias current (i ib ) characteristics into account, the resistor ro1 must not exceed 100k . ? the following circuit (for a lowered current of over 0.2a ) is recommended if the application needs to temporarily lower the motor current. here , a value of close to 100k must be used for resistor ro1 to make the transistor output saturation voltage as low as possible. 5v ro1 ro2 ro3 vref 5v ro1 ro2 ro3 vref stk672-120-e co3 10 f resetb 5v ro1 ro2 0.1 f co1 vref ro3 5v d1 co4 + + + 10 f 9 10 8 7 6 12 1 itf02597 p.gnd v cc 24v 2 3 4 5 a ab b bb gnd co2 at least 100 f two-phase stepping motor v dd =5v clock mode cwb 11
stk672-120-e no.6042-5/9 input pin functions (cmos input levels) pin pin no. function input conditions when operating clock 9 reference clock for motor phase current swit ching operates on the rising edge of the signal mode 8 excitation mode selection low: 2-phase excitation high: 1-2 phase excitation cwb 7 motor direction switching low: cw (forward) high: ccw (reverse) resetb 6 system reset and a, ab, b, and bb outputs cutoff. applications must apply a reset signal for at least 20 s when power is first applied. a reset is applied by a low level ? a simple reset function is formed from d1, co4, and ro3 in this application circuit. with the clock input held low, when the 5v supply voltage is brought up a reset is a pplied if the motor output phases a and bb are driven. if the 5v supply voltage rise time is slow (over 50ms), the motor output phases a and bb may not be driven. increase the value of the capacitor co4 and check circuit operation again. ? see the timing chart for the concrete details on circuit operation. usage notes ? 5v system input pins [resetb and clock (input signal timi ng when power is first applied)] as shown in the timing chart, a resetb signal input is requ ired by the driver to operate with the timing in which the f1 gate is turned on first. the resetb signal timing must be set up to have a width of at least 20 s, as shown below. the capacitor co4 and the resistor ro3 in the application circuit form simple reset circuit that uses the rc time constant rising time. however, when designing the resetb input based on cmos levels, the application must have the timing shown in figure 1. figure 1 resetb and clock signals input timing see the timing chart for details on the clock, mode, cwb, and other input pins. [vref ] in the sample application circuit, the peak value of the motor current (i oh ) is set by ro1, ro2, and v dd (5v) as described by the formula below. figure 2 motor current i o flowing into the driver ic i oh = vref rs here, rs is hybrid ic internal current detection resistor vref = (r02 (r01 + r02)) 5v stk672-120-e: rs = 0.165 at least 20 0
stk672-120-e no.6042-6/9 ? allowable motor current operating range the motor current (i oh ) must be held within the range corresponding to the area under the curve shown in figure 4. for example, if the operating substrate temperature tc is 105 c, then i oh must be held under i oh = 2.4a, and in hold mode i oh must be held under i oh = 2.0a. ? thermal design [operating range in which a heat sink is not used] thermal design that lowers this hybrid ic?s operating subs trate temperature can be effect ive in improving end product quality. the size of the heat sink required by this hybr id ic varies with the average power dissipation p d . the value of p d increases as the output current in creases, as shown in figure 5. since there are periods when current flows and periods when the current is off during actual motor operation, p d cannot be determined from the data presente d in figure 5. therefore, we calculate p d assuming that actual motor operation consists of repetitions of the operation shown in figure 3. figure 3 motor current timing t1: motor rotation operation time t2: motor hold operation time t3: motor current off time t2 may be reduced, depending on the application. t0: single repeated motor operating cycle i o 1 and i o 2: motor current peak values due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. note that figure 3 presents the concepts here, and that the on/off duty of the actual signals will differ. the hybrid ic internal average power dissipation p d can be calculated from the following formula. p d = (t1 p1 + t2 p2 + t3 0) t0 (i) (here, p1 is the p d for i o 1 and p2 is the p d for i o 2) if the value calculated in formula (i) above is under 1.5w, then there will be no need to use a heat sink for ambient temperatures ta up to 60c. see figure 6 for operating substrat e temperature rise data when a heat sink is not attached. if a heat sink is to be used, to lower tc if p d increases, use formula (ii) and the gr aph in figure 7 to determine the size of the heat sink. c - a = (tc max?ta) p d (ii) tc max: maximum operating substrate temperature = 105 c ta: the hybrid ic ambient temperature while formulas (i) and (ii) above are adequate for thermal desi gn, note that figure 5 is merely a single example of one operating mode for a single motor. for example, while fi gure 5 shows a 2-phase excitation motor, if 1-2 phase excitation is used with a 500hz clock frequency, the driv e will be turned off for 25% of the time and the loss p d will be reduced to 75% of that in figure 5. it is extremely difficult for sanyo to calculate the intern al average power dissipation p d for all possible end product conditions. after performing the above rough calculations, alwa ys install the hybrid ic in an actual end product and verify that the substrate temperature tc does not rise above 105c. t1 t2 t0 t3 -i o 1 i o 2 i o 1 motor phase current (sink side)
stk672-120-e no.6042-7/9 timing chart 2-phase excitation 1-2 phase excitation itf02606 itf02605 mode resetb cwb clock mode resetb cwb clock gate f1 gate f2 gate f3 gate f4 v ref a 100% 100% v refb gate f1 gate f2 gate f3 gate f4 v ref a 100% 100% v refb
stk672-120-e no.6042-8/9 1-2 phase excitation (cwb) switching from 2-phase to 1-2 phase excitation itf02608 itf02607 mode resetb cwb cloc k mode resetb cwb cloc k gate f1 gate f2 gate f3 gate f4 v ref a 100% 100% v refb gate f1 gate f2 gate f3 gate f4 v ref a 100% 100% v refb
stk672-120-e no.6042-9/9 ps this catalog provides informati on as of june, 2008. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibil ity for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these probabilistic failures or malfunction could give rise to accident s or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the us e of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control l aws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. 20 0 40 120 60 80 100 105 0 1.0 0.5 3.0 2.0 2.5 1.5 4.0 4.5 3.5 itf02609 0.5 0 1.0 1.5 2.0 2.5 3.5 3.0 0 40 10 20 30 80 60 70 50 itf02611 10 23 57 100 1000 23 57 1.0 2 3 5 7 10 100 2 3 5 7 itf02612 0.5 0 1.0 4.0 3.0 1.5 2.0 2.5 3.5 0 6 2 4 10 18 12 14 16 8 itf02610 2.0 2.4 operating substrate temperature, tc - c motor current, i oh - a i oh - tc operating region when f cl 200hz operating region in hold mode with no heat sink, the ic vertical, and convection cooling w i t h n o s u r f a c e f i n i s h i n g w i t h a b l a c k s u r f a c e f i n i s h i n g figure 4 hybrid ic internal average power disspation, p d - w substrate temperature rise, tc - c tc - p d figure 6 motor current, i oh - a hybrid ic internal aver age power dissipation, p d - w p d - i oh v cc =24v, v dd =5.0v clock=500hz continuous 2-phase excitation operation motor used: r=0.63 l=0.62mh the data are typical values. v cc =24v motor: r=0.4 l=1.2mh figure 5 figure 7 heat sink area, s - cm 2 heat sink thermal resistance, c-a - c/w s - c-a
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