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first release features ? built using the advantages and compatibility of cmos and ixys hdmos tm processes ? latch-up protected up to 9 amps ? high 9a peak output current ? wide operating range: 4.5v to 30v ? - 55c to +125c extended operating temperature ? high capacitive load drive capability: 1800pf in <15ns ? matched rise and fall times ? low propagation delay time ? low output impedance ? low supply current applications ? driving mosfets and igbts ? motor controls ? line drivers ? pulse generators ? local power on/off switch ? switch mode power supplies (smps) ? dc to dc converters ? pulse transformer driver ? class d switching amplifiers ? power charge pumps general description the ixdi509 and ixdn509 are high speed high current gate drivers specifically designed to drive the largest ixys mosfets & igbts to their minimum switching time and maximum practical frequency limits. the ixdi509 and ixdn509 can source and sink 9 amps of peak current while producing voltage rise and fall times of less than 30ns. the inputs of the drivers are compatible with ttl or cmos and are virtually immune to latch up over the entire operating range. patented* design innovations eliminate cross conduction and current "shoot-through". improved speed and drive capabilities are further enhanced by matched rise and fall times. the ixdi509 is configured as a inverting gate driver, and the ixdn509 is configured as a non-inverting gate driver. the ixdi509 and ixdn509 are each available in the 8-pin p- dip (pi) package, the 8-pin soic (sia) package, and the 6-lead dfn (d1) package, (which occupies less than 65% of the board area of the 8-pin soic). *united states patent 6,917,227 ordering information part number description package type packing style pack qty configuration ixdi509pi 9a low side gate driver i.c. 8-pin pdip tube 50 ixdi509sia 9a low side gate driver i.c. 8-pin soic tube 94 ixdi509siat/r 9a low side gate driver i.c. 8-pin soic 13? tape and reel 2500 ixdi509d1 9a low side gate driver i.c. 6-lead dfn 2? x 2? waffle pack 56 ixdi509d1t/r 9a low side gate driver i.c. 6-lead dfn 13? tape and reel 2500 inverting ixdn509pi 9a low side gate driver i.c. 8-pin pdip tube 50 ixdn509sia 9a low side gate driver i.c. 8-pin soic tube 94 ixdn509siat/r 9a low side gate driver i.c. 8-pin soic 13? tape and reel 2500 ixdn509d1 9a low side gate driver i.c. 6-lead dfn 2? x 2? waffle pack 56 ixdn509d1t/r 9a low side gate driver i.c. 6-lead dfn 13? tape and reel 2500 non-inverting ds99670a(10/07) note: all parts are lead-free and rohs compliant copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 9 ampere low-side ultrafast mosfet drivers
2 copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 figure 2 - ixdn509 non-inverting 9a gate driver functional block diagram figure 1 - ixdi509 inverting 9a gate driver functional block diagram * united states patent 6,917,227 n p out vcc in anti-cross conduction circuit * gnd gnd vcc n p out vcc in anti-cross conduction circuit * gnd gnd vcc
3 ixdi509 / ixdn509 absolute maximum ratings (1) operating ratings (2) parameter value supply voltage 35 v all other pins -0.3 v to v cc + 0.3v junction temperature 150 c storage temperature -65 c to 150 c lead temperature (10 sec) 300 c parameter value operating supply voltage 4.5v to 30v operating temperature range -55 c to 125 c ixys reserves the right to change limits, test conditions, and dimensions. package thermal resistance * 8-pin pdip (pi) j-a (typ) 125 c/w 8-pin soic (sia) j-a (typ) 200 c/w 6-lead dfn (d1) j-a (typ) 125-200 c/w 6-lead dfn (d1) j-c (max) 2.0 c/w 6-lead dfn (d1) j-s (typ) 6.3 c/w unless otherwise noted, 4.5v v cc 30v . all voltage measurements with respect to gnd. ixd_509 configured as described in test conditions . electrical characteristics @ t a = 25 o c (3) symbol parameter test conditions min typ max units v ih high input voltage 4.5v v cc 18v 2.4 v v il low input voltage 4.5v v cc 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc - 0.025 v v ol low output voltage 0.025 v r oh high state output resistance v cc = 18v 0.6 1 ? r ol low state output resistance v cc = 18v 0.4 0.8 ? i peak peak output current v cc = 15v 9 a i dc continuous output current limited by package power dissipation 2 a t r rise time c load =10,000pf v cc =18v 25 45 ns t f fall time c load =10,000pf v cc =18v 23 40 ns t ondly on-time propagation delay c load =10,000pf v cc =18v 18 35 ns t offdly off-time propagation delay c load =10,000pf v cc =18v 19 30 ns v cc power supply voltage 4.5 18 30 v i cc power supply current v cc = 18v, v in =0v v in = 3.5v v in = v cc 1 75 3 75 a ma ma (4)
4 copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 * the following notes are meant to define the conditions for the j-a , j-c and j-s values: 1) the j-a (typ) is defined as junction to ambient. the j-a of the standard single die 8-lead pdip and 8-lead soic are dominated by the resistance of the package, and the ixd_5xx are typical. the values for these packages are natural convection values with verti cal boards and the values would be lower with forced convection. for the 6-lead dfn package, the j-a value supposes the dfn package is soldered on a pcb. the j-a (typ) is 200 c/w with no special provisions on the pcb, but because the center pad provides a low thermal resistance to the die, it is easy to reduce the j-a by adding connected copper pads or traces on the pcb. these can reduce the j-a (typ) to 125 c/w easily, and potentially even lower. the j-a for dfn on pcb without heatsink or thermal management will vary significantly with size, construction, layout, materials, etc. this typical range tells the user what he is likely to get if he does no thermal management. 2) j-c (max) is defined as juction to case, where case is the large pad on the back of the dfn package. the j-c values are generally not published for the pdip and soic packages. the j-c for the dfn packages are important to show the low thermal resistance from junction to the die attach pad on the back of the dfn, -- and a guardband has been added to be safe. 3) the j-s (typ) is defined as junction to heatsink, where the dfn package is soldered to a thermal substrate that is mounted on a heatsi nk. the value must be typical because there are a variety of thermal substrates. this value was calculated based on easily availab le ims in the u.s. or europe, and not a premium japanese ims. a 4 mil dialectric with a thermal conductivity of 2.2w/mc was assumed. the re sult was given as typical, and indicates what a user would expect on a typical ims substrate, and shows the potential low thermal resist ance for the dfn package. unless otherwise noted, 4.5v v cc 30v , tj < 150 o c all voltage measurements with respect to gnd. ixd_502 configured as described in test conditions . all specifications are for one channel. electrical characteristics @ temperatures over -55 o c to 125 o c (3) symbol parameter test conditions min typ max units v ih high input voltage 4.5v v cc 18v 2.4 v v il low input voltage 4.5v v cc 18v 0.8 v v in input voltage range -5 v cc + 0.3 v i in input current 0v v in v cc -10 10 a v oh high output voltage v cc ? 0.025 v v ol low output voltage 0.025 v r oh high state output resistance v cc = 18v 2 ? r ol low state output resistance v cc = 18v 1.5 ? i dc continuous output current 1 a t r rise time c load =10,000pf v cc =18v 60 ns t f fall time c load =10,000pf v cc =18v 60 ns t ondly on-time propagation delay c load =10,000pf v cc =18v 55 ns t offdly off-time propagation delay c load =10,000pf v cc =18v 40 ns v cc power supply voltage 4.5 18 30 v i cc power supply current v cc =18v, v in = 0v v in = 3.5v v in = v cc 0.13 3 0.13 a ma ma notes: 1. operating the device beyond the parameters listed as ?absolute maximum ratings? may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. the device is not intended to be operated outside of the operating ratings. 3. electrical characteristics provided are associated with the stated test conditions. 4. typical values are presented in order to communicate how the device is expected to perform, but not necessarily to highlight any specific performance limits within which the device is guaranteed to function. (4)
5 ixdi509 / ixdn509 pin symbol function description 1, 8 v cc supply voltage power supply input voltage. these pins provide power to the entire device. the range for this voltage is 4.5v to 30v. 2 in input input drive signal, ttl or cmos compatible. 6, 7 out output driver output. for application purposes, these pins are connected, through a resistor, to the gate of a mosfet/igbt. 4, 6 gnd ground the device ground pins. internally connected to all circuitry, these pins provide ground reference for the entire chip and should be connected to a low noise analog ground plane for optimum performance. pin description caution: follow proper esd procedures when handling and assembling this component. figure 3 - characteristics test diagram 0v 5.0v 0v vcc ixdi414 ixdn414 0v vcc a gilent 1147a current probe 15nf 10uf 25v ixd_509 ixdi509 ixdn509 2500 pf c load pin configurations note: solder tabs on bottom of dfn packages are grounded 8 pin dip (pi) 8 pin soic (sia) v cc in n/c gnd v cc out out 1 2 3 4 8 7 6 5 i x d i 5 0 9 gnd 8 pin dip (pi) 8 pin soic (sia) v cc in n/c gnd v cc out out 1 2 3 4 8 7 6 5 i x d n 5 0 9 gnd 6 lead dfn (d1) (bottom view) in n/c gnd v cc gnd out 1 2 3 6 5 4 i x d n 5 0 9 6 lead dfn (d1) (bottom view) in n/c gnd v cc gnd out 1 2 3 6 5 4 i x d i 5 0 9
6 copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 ixys reserves the right to change limits, test conditions, and dimensions. figure 4 - timing diagrams inverting (ixdi509) timing diagram 0v 5v 90% 10% 2.5v input vcc 0v 10% 90% output pw min t f t offdly t r t ondly non-inverting (ixdn509) timing diagram input output 5v 90% 2.5v 10% 0v 0 v vcc 90% 10% t ondly t offdly t r t f pw min
7 ixdi509 / ixdn509 typical performance characteristics fig. 5 fig. 6 fig. 7 fig. 8 fig. 9 fig. 10 rise / fall time vs. temperature v supply = 15v c load = 1000pf 0 1 2 3 4 5 6 7 8 -50 0 50 100 150 temperature (c) rise / fall time (ns) rise time vs. capacitive load 0 5 10 15 20 25 30 35 100 1000 10000 load capacitance (pf) rise time (ns) 5v 15v 30v fall time vs. capacitive load 0 5 10 15 20 25 30 35 100 1000 10000 load capacitance (pf) fall time (ns) 30v 15v 5v input threshold levels vs. supply voltage 0 0.5 1 1.5 2 2.5 0 5 10 15 20 25 30 35 supply voltage (v) threshold level (v) positive going input negative going input rise time vs. supply voltage 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 supply voltage (v) rise time (ns) 100pf 1000pf 10000pf 5400pf fall time vs. supply voltage 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 supply voltage (v) fall time (ns) 100pf 1000pf 10000pf 5400pf
8 copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 fig. 11 fig. 16 fig. 12 fig. 13 fig. 14 fig. 15 propagation delay vs. supply voltage rising input, c load = 1000pf 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 supply voltage (v) propagation delay time (ns) propagation delay vs. supply voltage falling input, c load = 1000pf 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 supply voltage (v) propagation delay time (ns) quiescent current vs. supply voltage 0.01 0.1 1 10 100 1000 10000 0 5 10 15 20 25 30 35 supply voltage (v) quiesent current (ua) inverting input = "0" non-inverting input = "0" inverting / non-inverting input = "1" quiescent current vs. temperature v supply = 15v 0.01 0.1 1 10 100 1000 -50 0 50 100 150 temperature (c) quiescent current (ua) non-inverting, input= "0" inverting, input= "0" inverting / non-inverting, input= "1" propagation delay vs. temperature v supply = 15v c load = 1000pf 0 5 10 15 20 25 30 35 -50 0 50 100 150 temeprature (c) propagation delay time (ns) positve going input negative going input input threshold levels vs. temperature v supply = 15v 0 0.5 1 1.5 2 2.5 3 -50 0 50 100 150 temperature (c) input threshold level (v) positive going input negative going input
9 ixdi509 / ixdn509 supply current vs. capacitive load v supply = 5v 0.01 0.1 1 10 100 100 1000 10000 load capacitance (pf) supply current (ma) 100khz 1mhz 2mhz 10khz supply current vs. capacitive load v supply = 15v 0.1 1 10 100 1000 100 1000 10000 load capacitance (pf) supply current (ma) 100khz 1mhz 2mhz 10khz supply current vs. frequency v supply = 5v 0.01 0.1 1 10 100 10 100 1000 10000 frequency (khz) supply current (ma) 100pf 1000pf 10000pf 5400pf supply current vs. frequency v supply = 15v 0.1 1 10 100 1000 10 100 1000 10000 frequency (khz) supply current (ma) 100pf 1000pf 10000pf 5400pf fig. 18 fig. 20 fig. 17 fig. 19 fig. 21 fig. 22 supply current vs. capacitive load v supply = 30v 0.1 1 10 100 1000 100 1000 10000 load capacitance (pf) supply current (ma) 2mhz 1mhz 100khz 10khz supply current vs. frequency v supply = 30v 0.1 1 10 100 1000 10 100 1000 10000 frequency (khz) supply current (ma) 100pf 1000pf 5400pf 10000pf
10 copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 output sink current vs. supply voltage -25 -20 -15 -10 -5 0 0 5 10 15 20 25 30 35 supply voltage (v) sink current (a) output sink current vs. temperature v supply = 15v -14 -12 -10 -8 -6 -4 -2 0 -50 0 50 100 150 temperature (c) output sink current (a) fig. 24 fig. 25 fig. 26 fig. 28 fig. 23 fig. 27 output source current vs. supply voltage 0 5 10 15 20 25 0 5 10 15 20 25 30 35 supply voltage (v) source current (a) output source current vs. temperature v supply = 15v 0 2 4 6 8 10 12 -50 0 50 100 150 temperature (c) output source current (a) high state output resistance vs. supply voltage 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 5 10 15 20 25 30 35 supply voltage (v) output rsistance (ohms) low state output resistance vs. supply voltage 0 0.2 0.4 0.6 0.8 1 1.2 0 5 10 15 20 25 30 35 supply voltage (v) output resistance (ohms)
11 ixdi509 / ixdn509 when designing a circuit to drive a high speed mosfet utilizing the ixd_509, it is very important to observe certain design criteria in order to optimize performance of the driver. particular attention needs to be paid to supply bypassing , grounding , and minimizing the output lead inductance . say, for example, we are using the ixd_509 to charge a 5000pf capacitive load from 0 to 25 volts in 25ns . using the formula: i c =c( ? v/ ? t), where ? v=25v c=5000pf & ? t=25ns, we can determine that to charge 5000pf to 25 volts in 25ns will take a constant current of 5a. (in reality, the charging current won?t be constant, and will peak somewhere around 8a). supply bypassing in order for our design to turn the load on properly, the ixd_509 must be able to draw this 5a of current from the power supply in the 25ns. this means that there must be very low impedance between the driver and the power supply. the most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is an order of magnitude larger than the load capacitance. usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (these capacitors should be carefully selected and should have low inductance, low resistance and high-pulse current-service ratings). lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the ixd_509 to an absolute minimum. grounding in order for the design to turn the load off properly, the ixd_509 must be able to drain this 5a of current into an adequate grounding system. there are three paths for returning current that need to be considered: path #1 is between the ixd_509 and its load. path #2 is between the ixd_509 and its power supply. path #3 is between the ixd_509 and whatever logic is driving it. all three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. in addition, every effort should be made to keep these three ground paths distinctly separate. otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the ixd_509. output lead inductance of equal importance to supply bypassing and grounding are issues related to the output lead inductance. every effort should be made to keep the leads between the driver and its load as short and wide as possible. if the driver must be placed farther than 0.2? (5mm) from the load, then the output leads should be treated as transmission lines. in this case, a twisted- pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load. supply bypassing, grounding practices and output lead inductance
12 copyright ? 2007 ixys corporation all rights reserved ixdi509 / ixdn509 ixys semiconductor gmbh edisonstrasse15 ; d-68623; lampertheim tel: +49-6206-503-0; fax: +49-6206-503627 e-mail: marcom@ixys.de ixys corporation 3540 bassett st; santa clara, ca 95054 tel: 408-982-0700; fax: 408-496-0670 e-mail: sales@ixys.net www.ixys.com h e e a a1 b d d c l h x 45 h h l e e b c m n m n e1 e ea l eb e d d1 c b3 b2 b a2 0.018 [0.47] 0 . 0 2 0 [ 0 . 5 1 ] 0 . 0 1 9 [ 0 . 4 9 ] 0 . 0 3 9 [ 1 . 0 0 ] 0 . 1 5 7 0 . 0 0 5 [ 3 . 9 9 0 . 1 3 ] 0.1970.005 [5.000.13] 0 . 1 2 0 [ 3 . 0 5 ] 0.100 [2.54] 0.137 [3.48] s0.002^0.000; o s0.05^0.00;o [] 0.035 [0.90]

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