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512kx72 (dlw)double late write ram - 1 - rev 0.1 dec 2001 K7Z327285M preliminary document title 512kx72 dlw(double late write) ram the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revision history rev. no. 0.0 0.1 remark preliminary preliminary history 1. initial document. 1. device name change from double late write sigmaram to double late write ram draft date aug. 29. 2001 dec. 17. 2001
512kx72 (dlw)double late write ram - 2 - rev 0.1 dec 2001 K7Z327285M preliminary 32mb ntram(flow through / pipelined) , double late write ram x72 ordering informa tion org. part number mode vdd speed ft ; access time(ns) pipelined ; cycle time(mhz) pkg temp 2mx18 k7m321825m-q(h/f)c65/75/85 flowthrough 3.3 6.5/7.5/8.5ns q:100tqfp h:119bga f:165fbga c (commercial temperature range) k7n321801m-q(h/f)c25/22/20/16/15/13 pipelined 3.3 250/225/200/167/150/133mhz k7n321845m-q(h/f)c25/22/20/16/15/13 pipelined 2.5 250/225/200/167/150/133mhz 1mx36 k7m323625m-q(h/f)c65/75/85 flowthrough 3.3 6.5/7.5/8.5ns k7n323601m-q(h/f)c25/22/20/16/15/13 pipelined 3.3 250/225/200/167/150/133mhz k7n323645m-q(h/f)c25/22/20/16/15/13 pipelined 2.5 250/225/200/167/150/133mhz 512kx72 k7n327245m-hc25/22/20/16/15/13 pipelined (normal type) 2.5 250/225/200/167/150/133mhz h : 209bga K7Z327285M-hc27/25 pipelined (sigma type) 1.8 275/250mhz
512kx72 (dlw)double late write ram - 3 - rev 0.1 dec 2001 K7Z327285M preliminary 512kx72-bit dlw(double late write) ram the K7Z327285M is 37,748,736 -bits synchronous static srams. the double late write ram utilizes all the bandwidth in any combi- nation of operating cycles. address, data inputs, and all control signals except ep2, ep3, and sd are synchronized to input clock. write cycles are internally self-timed and initiated by the rising edge of the clock input. this feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. for read cycles, the sram output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. the K7Z327285M are implemented with samsung s high per- formance cmos technology and is available in 209bga pack- ages. multiple power and ground pins minimize ground bounce. general description features ? double late write mode , pipelined read mode. ? compatible with double late write sigma ram tm x72. ? 1.8v +150/-100 mv power supply. ? 1.8v i/o supply. ? byte writable function. ? single read/write control pin. ? self-timed write cycle. ? complement echo clock outputs ? selectable impedance output buffer(zq) ? 2 user programmable chip enable inputs for easy depth expansion.(ep2, ep3) ? supports linear burst mode only. ? slow down function. ? ieee 1149.1 jtag compatible boundary scan ? 209 bump, 14mm x 22mm, 1mm bump pitch bga package ? 209bga(11x19 ball grid array package). fast access times parameter symbol -27 -2 5 unit cycle time t cyc 3.6 4.0 ns clock access time t cd 2.0 2. 1 ns logic block diagram we bw x clk e 1 e2 e3 adv dqa0 ~ dqh7 address address register c o n t r o l l o g i c a 0 ~a 1 72 dqpa ~ dqph output buffer register data-in register data-in register k k k register burst address counter write address register write control logic c o n t r o l r e g i s t e r k a [0:18] a 2 ~a 18 a 0 ~a 1 (x=a ~ h) 512k x 72 memory array ep2 ep3 echo clock buffer output k cq1, cq1 cq2, cq2 4
512kx72 (dlw)double late write ram - 4 - rev 0.1 dec 2001 K7Z327285M preliminary 209bga package pin configurations (top view) 512 kx72 common i/o-top view 1 2 3 4 5 6 7 8 9 10 11 a dqg dqg a e2 a adv a e3 a dqb dqb b dqg dqg bw c bw g nc we a bw b bw f dqb dqb c dqg dqg bw h bw d nc(128m) e1 nc bw e bw a dqb dqb d dqg dqg v ss nc nc mcl nc nc v ss dqb dqb e dqpg dqpc v ddq v ddq v dd v dd v dd v ddq v ddq dqpf dqpb f dqc dqc v ss v ss v ss zq v ss v ss v ss dqf dqf g dqc dqc v ddq v ddq v dd ep2 v dd v ddq v ddq dqf dqf h dqc dqc v ss v ss v ss ep3 v ss v ss v ss dqf dqf j dqc dqc v ddq v ddq v dd mch v dd v ddq v ddq dqf dqf k cq2 cq2 ck nc v ss mcl v ss nc nc cq1 cq1 l dqh dqh v ddq v ddq v dd mch v dd v ddq v ddq dqa dqa m dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa n dqh dqh v ddq v ddq v dd sd v dd v ddq v ddq dqa dqa p dqh dqh v ss v ss v ss mcl v ss v ss v ss dqa dqa r dqpd dqph v ddq v ddq v dd v dd v dd v ddq v ddq dqpa dqpe t dqd dqd v ss nc nc mcl nc nc v ss dqe dqe u dqd dqd nc a nc(64m) a a a nc dqe dqe v dqd dqd a a a a1 a a a dqe dqe w dqd dqd tms tdi a a0 a tdo tck dqe dqe
512kx72 (dlw)double late write ram - 5 - rev 0.1 dec 2001 K7Z327285M preliminary pin description table pin name description type comments a address input - adv advance input active high bw x (x=a ~ h) byte write enable input active low ck clock input active high dq data i/o input/output - cq echo clock outputs output active high cq echo clock outputs output active low e1 chip enable input active low e2 & e3 chip enable input programmable active high or low ep2 & ep3 chip enable program pin input - sd slow down input input active low tck test clock input active high tdi test data in input - tdo test data out output - tms test mode select input - mch must connect high input active high mcl must connect low input active low nc no connect - not connected to die we write input active low v dd core power supply input 1.8v v ddq output driver power supply input 1.8v v ss ground input - zq output impedance control input low = low impedance(high drive) high = high impedance(low drive)
512kx72 (dlw)double late write ram - 6 - rev 0.1 dec 2001 K7Z327285M preliminary function description the K7Z327285M is double late write ram designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, or vice versa. because a double late write ram is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. e p 2 , e p 3 and sd are asynchronous control input. read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, all three chip enables( e1 , e2 , e3 ) are active, the write enable input signals we are driven high, and adv driven low.the internal array is read between the first rising edge and the second rising edge of the clock and the data is latched in the out- put register. at the second clock edge the data is driven out of the sram. write operation occurs when we is driven low at the rising edge of the clock. bw x [h:a] can be used for byte write operation. the double late write ram uses a double-late write cycle to utilize 100% of the bandwidth. at the first rising edge of the clock, we and address are registered, and the data associated with that address is required two cycle later. subsequent addresses are generated by adv high for the burst access as shown below. the starting point of the burst seguence is provided by the external address. the burst address counter wraps around to its initial state upon completion. double late write ram supports linear burst sequence only. burst sequence table (linear burst order ) a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 slow down function sd is helpful to prevent to bus contention in read operation after write operation , especially high frequency application. when sd is low, the sram is operated in a slow down mode. in a slow down mode, the enable/disable timings of output data become slower , which are defined as tkhqv,tkhqz,tkhqx,tkhqx1/tkhch and tklcl. the valid data window in slow down mode is same with normal operation mode , so it will be helpful in read operation after writ e operation when sd is high , the sram returns to normal operation node. the state of sd must be fixed before operation , and it can not be changed during operation.
512kx72 (dlw)double late write ram - 7 - rev 0.1 dec 2001 K7Z327285M preliminary programmable enables double late write ram feature s two user programmable chip enable inputs, e2 and e3. the sense of the inputs, whether they func- tion as active low or active high inputs, is determined by the state of the programming inputs, e p 2 and e p 3. for example, if e p 2 is held at v dd , e2 functions as an active high enable. if e p 2 is held to vss, e2 functions as an active low chip enable input. programmability of e2 and e3 allows four banks of depth expansion to be accomplished with no additional logic. by programming the enable inputs of four double late write rams in binary sequence(00, 01, 10, 11)and driving the enable inputs with two address inputs. f our double late write ram can be made to look like one larger ram to the system. deselection of the ram via e1 does not deactive the echo clocks. example four bank depth expansion schematic bank enable truth table ep2 ep3 e2 e3 bank 0 v ss v ss active low active low bank 1 v ss v dd active low active high bank 2 v dd v ss active high active low bank 3 v dd v dd active high active high a e3 e2 e1 ck w dq a 0 - a n-2 a n-1 a n bank 0 a 0 - a n e1 ck we dq 0 - dq n a e3 e2 e1 ck w dq a 0 - a n-2 a n-1 a n bank 1 a e3 e2 e1 ck w dq a 0 - a n-2 a n-1 a n bank 2 a e3 e2 e1 ck w dq a 0 - a n-2 a n-1 a n bank 3
512kx72 (dlw)double late write ram - 8 - rev 0.1 dec 2001 K7Z327285M preliminary state diagram for double late write ram read write deselect read write x,x,h,x l,t,l,h x,x,h,x l,t,l,h l,t,l,h bank l,t,l,h l,t,l,l deselect x,f,l,x, or x,x,h,x h,t,l,x x,f,l,x h,t,l,x l,t,l,l h,t,l,x h,t,l,x, or x,x,h,x x,f,l,x x,f,l,x l,t,l,l l,t,l,h x,x,h,x h,t,l,x x,f,l,x h,t,l,x x,f,l,x continue continue x,x,h,x l,t,l,l l,t,l,l l,t,l,h notes : 1. the notation "x,x,x,x" controlling the state transitions above indicate the states of inputs e1 ,e,adv, and we respectively. 2. if (e2=ep2 and e3=ep3) then e="t" else e="f". 3. "h"=input "high"; "l"=input"low"; "x"=input"don?t care"; "t"=input "true"; "f"=input "false".
512kx72 (dlw)double late write ram - 9 - rev 0.1 dec 2001 K7Z327285M preliminary truth tables write truth table notes : 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of clk( - ). w e bw a bw b bw c bw d bw e bw f bw g bw h operation h x x x x x x x x read l l h h h h h h h write byte a l h l h h h h h h write byte b l h h l h h h h h write byte c l h h h l h h h h write byte d l h h h h l h h h write byte e l h h h h h l h h write byte f l h h h h h h l h write byte g l h h h h h h h l write byte h l l l l l l l l l write all bytes l h h h h h h h h write abort/nop note : 1. x=don?t care, h=high, l=low. 2. e =t(true) if e 2= active and e3 = active ; e=f(false) if e2=inactive or e3=inactive . 3. " * " indicates that the dq input requirement / output state and cq output state are determined by the previous operation. 4 . b w x = f(false) if all byte write enable pins are high. b w x =t(true) if any one byte write enable pin is low. 5 . dqs are tri-state in response to bank deselect, deselect, and write commands . 6 . deassertion of e1 does not deactive the echo clock outputs( cq1, cq1 , cq2, cq2 ). echo clock outputs are tri-stated in response to bank deselect commands only. previous cycle input type e 1 (tn) e (tn) adv (tn) we (tn) bw x (tn) current operation address dq /cq (tn) dq/ cq (tn+1) notes n/a d h t l x x deselect cycle none * hi-z/cq 4 deselect c x x h x x deselect cycle, continue next hi-z /cq hi-z/cq 4 n/a d x f l x x bank deselect cycle none * hi-z 4, 5 bank deselect c x x h x x bank deselect cycle, continue next hi-z hi-z 4 , 5 n/a r l t l h x read cycle, begin burst external * q /cq 2 read c x x h x x read cycle, continue burst next q /cq q/cq n/a w l t l l x write cycle, begin burst external * d/cq 2, 3 n/a w l t l l f non-write cycle, begin burst external * * 2, 3 write c x x h x t write cycle, continue burst next d/cq d/cq 3 write c x x h x f non-write cycle, continue burst next * d/cq 3, 4, 5
512kx72 (dlw)double late write ram - 10 - rev 0.1 dec 2001 K7Z327285M preliminary absolute maximum ratings* *note : stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0. 3 to 2.5 v voltage on any other pin relative to v ss v in -0. 3 to vdd+0.3 v power dissipation p d 1.6 w storage temperature t stg -65 to 150 c operating temperature t opr 0 to 70 c storage temperature range under bias t bias -10 to 85 c operating conditions (0 c t a 70 c) *note : v dd and v ddq must be supplied with identical v ol tage levels . parameter symbol min typ. max unit supply voltage v dd 1.7 1.8 1.95 v v ddq 1.7 1.8 1.95 v ground v ss 0 0 0 v selectable impedance output driver dc electrical characteristics the kz327285m is supplied with selectable (high or low) impedance output buffers. zq=vddq zq=0v *note : the zq level supplied with selectable impedance allows selection between high drive strength ( zq=low) and low drive strength (z q=high) . parameter symbol test condition min max unit low drive output low voltage v oll i ol =4.0ma - 0.4 v low drive output high voltage v ohl i oh =-4.0ma v ddq - 0.4 - v parameter symbol test condition min max unit high drive output low voltage v olh i ol = 8.0ma - 0.4 v high drive output high voltage v ohh i oh =-8.0ma v ddq - 0.4 - v capacitance* (t a =25 c, f=1mhz) *note : sampled not 100% tested. parameter symbol test condition min max unit input capacitance c in v in =0v - 5 pf output capacitance c out v out =0v - 7 pf
512kx72 (dlw)double late write ram - 11 - rev 0.1 dec 2001 K7Z327285M preliminary dc electrical characteristics (v dd =1.8v + 150/-100mv , t a =0 c to +70 c) notes : 1. reference ac operating conditions and characteristics for input and timing. 2. data states are all zero. 3. in case of i/o pins, the max. v ih =v ddq +0.3v 4. the ep2, ep3 pins must not be changed during operation. parameter symbol test conditions min max unit notes input leakage current i il v dd =max ; v in =v ss to v dd -2 +2 m a output leakage current i ol output disabled, -2 +2 m a operating current i cc v dd =max , i out =0ma cycle time 3 t cyc min -27 - tbd ma 1,2 -25 - tbd standby current i sb1 e2 or e3 false, i out =0ma , f=max all inputs v il or 3 v ih - tbd ma i sb2 e1 3 v ih , i out =0ma, f=max, all inputs v il or 3 v ih - tbd ma i sb3 device deselected, i out =0ma, f=0, all inputs=fixed (v dd -0.2v or 0.2v) - tbd ma input low voltage v il -0.3 0.3*v ddq v 3 input low voltage for ep2,ep3, sd v il1 -0.3 0.3 v input high voltage v ih 0.7*v ddq v dd +0.3 v 3 input high voltage for ep2,ep3, sd v ih1 v dd - 0.3 v dd +0.3 v test conditions (t a =0 to 70 c, v dd = 1.8v + 150/-100mv , unless otherwise specified) parameter value input pulse level 0 to 1.8v input rise and fall time(measured at 20% to 80%) 2.0v/ns input and output timing reference levels 0.9v output load see fig. 1 v ss v ih v ss- 0.8v 20% t cyc (min)
512kx72 (dlw)double late write ram - 12 - rev 0.1 dec 2001 K7Z327285M preliminary ac timing characteristics when /sd=vdd (v dd =1.8v + 150/-100mv, t a =0 to 70 c) notes : 1. all address inputs must meet the specified setup and hold times for all rising clock(clk) edges when adv is sampled low and e1 is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this devi ce is chip selected. 2. chip selects must be valid at each rising edge of clk(when adv is low) to remain enabled. 3. a write cycle is defined by w e low having been registered into the device at adv low, a read cycle is defined by w e high with adv low, both cases must meet setup and hold times. 4. to avoid bus contention, at a given voltage and temperature t khqx1 is more than t khqz. the specs as shown do not imply bus contention because t khqx1 is a min. parameter that is worst case at totally different test conditions (0 c,1.95v) than t khqz , which is a max. parameter(worst case at 70 c,1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. parameter symbol -27 -25 unit min max min max cycle time t khkh 3.6 - 4.0 - ns clock high to output valid t khqv - 2.0 - 2.1 ns clock high to output high-z t khqz 0.5 2.0 0.5 2.1 ns output hold from clock high t khqx 0.5 - 0.5 - ns clock high to output low-z t khqx1 0.5 - 0.5 - ns clock high to cq high t khch 0.5 1.9 0.5 2.0 ns clock low to cq low t klcl 0.5 2.0 0.5 2.3 ns output hold from cq high t chqx -0.4 - -0.5 - ns cq high to output low-z t chqx1 -0.4 - -0.5 - ns cq high to output valid t chqv - 0.4 - 0.5 ns clock high to cq low-z t khcx1 0.5 - 0.5 - ns clock high to cq high-z t khcz 0.5 1.9 0.5 2.0 ns clock high pulse width t khkl 1.4 - 1.5 - ns clock low pulse width t klkh 1.4 - 1.5 - ns address setup to clock high t avkh 0.7 - 0.8 - ns chip enable setup to clock high t evkh 0.7 - 0.8 - ns write setup to clock high( we , bw x ) t wvkh 0.7 - 0.8 - ns data setup to clock high t dvkh 0.7 - 0.8 - ns address advance setup to clock high t advvkh 0.7 - 0.8 - ns address hold from clock high t khax 0.4 - 0.5 - ns chip enable hold from clock high t khex 0.4 - 0.5 - ns write hold from clock high( we , bw x ) t khwx 0.4 - 0.5 - ns data hold from clock high t khdx 0.4 - 0.5 - ns address advance hold from clock high t khadvx 0.4 0.5 - ns fig. 1 * including scope and jig capacitance output load(a) dout zo=50 w rl=50 w vl= vddq/2 30pf* ac test load diagram
512kx72 (dlw)double late write ram - 13 - rev 0.1 dec 2001 K7Z327285M preliminary ac timing characteristics when /sd=vss (v dd =1.8v + 150/-100mv, t a =0 to 70 c) notes : 1. all address inputs must meet the specified setup and hold times for all rising clock(clk) edges when adv is sampled low and e1 is sampled low. all other synchronous inputs must meet the specified setup and hold times whenever this devi ce is chip selected. 2. chip selects must be valid at each rising edge of clk(when adv is low) to remain enabled. 3. a write cycle is defined by w low having been registered into the device at adv low, a read cycle is defined by w high with adv low, both cases must meet setup and hold times. 4. to avoid bus contention, at a given voltage and temperature t khqx1 is more than t khqz. the specs as shown do not imply bus contention because t khqx1 is a min. parameter that is worst case at totally different test conditions (0 c,1.95v) than t khqz , which is a max. parameter(worst case at 70 c,1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. parameter symbol -27 -25 unit min max min max cycle time t khkh 3.6 - 4.0 - ns clock high to output valid t khqv - 2.9 - 3.0 ns clock high to output high-z t khqz 1.4 2.9 1.4 3.0 ns output hold from clock high t khqx 1.4 - 1.4 - ns clock high to output low-z t khqx1 1.4 - 1.4 - ns clock high to cq high t khch 1.4 2.8 1.4 2.9 ns clock low to cq low t klcl 1.4 2.9 1.4 3.2 ns output hold from cq high t chqx -0.4 - -0.5 - ns cq high to output low-z t chqx1 -0.4 - -0.5 - ns cq high to output valid t chqv - 0.4 - 0.5 ns clock high to cq low-z t khcx1 1.4 - 1.4 - ns clock high to cq high-z t khcz 1.4 2.8 1.4 2.9 ns clock high pulse width t khkl 1.4 - 1.5 - ns clock low pulse width t klkh 1.4 - 1.5 - ns address setup to clock high t avkh 0.7 - 0.8 - ns chip enable setup to clock high t evkh 0.7 - 0.8 - ns write setup to clock high( w , bw x ) t wvkh 0.7 - 0.8 - ns data setup to clock high t dvkh 0.7 - 0.8 - ns address advance setup to clock high t advvkh 0.7 - 0.8 - ns address hold from clock high t khax 0.4 - 0.5 - ns chip enable hold from clock high t khex 0.4 - 0.5 - ns write hold from clock high( w , bw x ) t khwx 0.4 - 0.5 - ns data hold from clock high t khdx 0.4 - 0.5 - ns address advance hold from clock high t khadvx 0.4 0.5 - ns
512kx72 (dlw)double late write ram - 14 - rev 0.1 dec 2001 K7Z327285M preliminary ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg- ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controll er without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 bypass bypass register 4 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 bypass bypass register 4 1 1 1 bypass bypass register 4
512kx72 (dlw)double late write ram - 15 - rev 0.1 dec 2001 K7Z327285M preliminary boundary scan order information tbd
512kx72 (dlw)double late write ram - 16 - rev 0.1 dec 2001 K7Z327285M preliminary jtag dc operating conditions *note : 1. in case of i/o pins, the max. v ih =v ddq +0.3v parameter symbol min typ max unit note power supply voltage v dd 1.7 1.8 1.95 v input high level v ih 1.05 - v dd +0.3 v 1 input low level v il -0.3 - 0.7 v output high voltage(i oh =-2ma) v oh 1.5 - v dd v output low voltage(i ol =2ma) v ol v ss - 0.45 v jtag ac test conditions parameter symbol min unit note input high/low level v ih /v il 1.8/0.0 v input rise/fall time tr/tf 1.0/1.0 ns input and output timing reference level 0.9 v jtag ac characteristics parameter symbol min max unit note tck cycle time t chch 20 - ns tck high pulse width t chcl 10 - ns tck low pulse width t clch 10 - ns tms input setup time t mvch 5 - ns tms input hold time t chmx 5 - ns tdi input setup time t dvch 5 - ns tdi input hold time t chdx 5 - ns sram input setup time t svch 5 - ns sram input hold time t chsx 5 - ns clock low to output valid t clqv 0 10 ns jtag timing diagram tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
512kx72 (dlw)double late write ram - 17 - rev 0.1 dec 2001 K7Z327285M preliminary c l o c k a d d r e s s t i m i n g w a v e f o r m o f r e a d / w r i t e c y c l e w i t h c o n t i n u e o p e r a t i o n t k h k l t k l k h t a v k h t k h a x a 1 a 2 a 3 w e e 1 t w v k h t k h w x t e v k h t k h e x a d v d a t a i n d a t a o u t t k h q v t k h q z q 2 - 1 q 1 - 1 d o n t c a r e u n d e f i n e d t a d v v k h t k h a d v x c q c q a 4 d 4 - 3 d 4 - 2 d 4 - 1 d 3 - 1 d 4 - 4 t k h k h t d v k h t k h d x t k h q x r e a d d e s e l e c t r e a d w r i t e w r i t e t k l c l t k h c h c h q x 1 t c h q v t k h q x 1 q 2 - 2 q 2 - 3 q 2 - 4
512kx72 (dlw)double late write ram - 18 - rev 0.1 dec 2001 K7Z327285M preliminary t i m i n g w a v e f o r m o f s i n g l e r e a d / w r i t e c l o c k a d d r e s s w e e 1 a d v d a t a i n t d v k h t k h d x d a t a o u t a 2 a 4 a 5 d 2 - 1 d o n t c a r e u n d e f i n e d a 1 a 3 a 7 a 6 d 5 - 1 a 1 0 a 9 a 8 q 6 - 1 d 8 - 1 c q c q q 1 - 1 q 3 - 1 q 4 - 1 q 7 - 1 r e a d d e s e l e c t w r i t e r e a d r e a d w r i t e r e a d w r i t e r e a d w r i t e
512kx72 (dlw)double late write ram - 19 - rev 0.1 dec 2001 K7Z327285M preliminary e c h o c l o c k c o n t r o l i n t w o b a n k s c l o c k a d d r e s s e 1 w e a d v e 2 b a n k 1 d o u t a 2 a 4 a 5 d o n t c a r e u n d e f i n e d t c y c a 1 a 3 a 7 a 6 n o t e : e 1 d o e s n o t d e s e l e c t t h e e c h o c l o c k o u t p u t s . e c h o c l o c k o u t p u t s a r e a 1 0 a 9 a 8 a 5 e 2 b a n k 2 b a n k 1 c q 1 + c q 2 d o u t b a n k 2 r e a d r e a d r e a d r e a d r e a d r e a d r e a d r e a d r e a d r e a d c q b a n k 1 c q b a n k 2 q 1 - 1 q 3 - 1 q 5 - 1 q 7 - 1 q 9 - 1 t k h c x 1 h i q 2 - 1 q 4 - 1 q 6 - 1 q 8 - 1 d e s e l e c t e d b y e 2 o r e 3 b e i n g s a m p l e d f a l s e .
512kx72 (dlw)double late write ram - 20 - rev 0.1 dec 2001 K7Z327285M preliminary b a n k s w i t c h w i t h e 1 d e s e l e c t c l o c k a d d r e s s e 1 w e a d v e 2 b a n k 1 d o u t a 4 a 5 d o n t c a r e u n d e f i n e d a 1 a 2 a 7 a 6 a 1 0 a 9 a 8 c q a 3 e 2 b a n k 2 b a n k 1 c q 1 + c q 2 d o u t b a n k 2 q 2 - 1 r e a d d e s e l e c t r e a d r e a d r e a d r e a d r e a d r e a d r e a d r e a d b a n k 1 c q b a n k 2 h i - z h i - z q 3 - 1 q 4 - 1 q 5 - 1 q 6 - 1 q 7 - 1 q 8 - 1 q 1 - 1 t k l c x 1
512kx72 (dlw)double late write ram - 21 - rev 0.1 dec 2001 K7Z327285M preliminary 209 bump bga package dimensions 14mm x 22mm body, 1.0mm bump pitch, 11x19 bump array 209- ? 0.06 0.10 1.00(bsc) 12.50 0 . 5 0 0 . 0 5 0 . 9 0 c1.00 c0.70 14.00 2 2 . 0 0 2 0 . 5 0 0 . 0 5 note : 1. all dimensions are in millimeters. 2. solder ball to pcb offset: 0.10 max. 3. pcb to cavity offset: 0.10 max. indicator of ball(1a) location 1.00x10=10.00(bsc) 1 . 0 0 ( b s c ) 1 . 0 0 x 1 8 = 1 8 . 0 0 ( b s c ) 1 . 5 0 2 . 2 0 m a x

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