View ADD8754ACPZ-REEL_4901813.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lcd panel power, v com , and g ate modulation add8754 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005 analog devices, inc. all rights reserved. features step-up switching regulator with 2 a power switch 650 khz or 1.2 mhz switching frequency output adjustable to 20 v 350 ma logic voltage regulator selectable output voltages: 2.5 v, 2.85 v, 3.3 v v com amplifier with 300 ma drive gate pulse modulation circuitry independently adjustable delay and falling slope general 3 v to 5.5 v input undervoltage lockout thermal shutdown 24-lead, pb-free lfcsp package applications tft lcd panels for monitors, tvs, and notebooks functional block diagram add8754 vgh vgh_m vdd_1 ce re vflk vdpm 05110-001 gate pulse modulation vcom amplifier logic voltage regulator under voltage lockout and thermal protection fb freq shdn vdd_2 out step-up switching regulator vin_2 vin_1 ss comp ldo_out adj lx pos neg figure 1. general description the add8754 is optimized for use in tft lcd applications, requiring only external charge pump components to provide all the requirements for panel power, v com , and gate modulation. included in a single chip are a high frequency step-up dc-to-dc switching regulator, logic voltage regulator, v com amplifier, and gate pulse modulation circuitry. the step-up dc-to-dc converter provides up to 20 v output and includes a 2 a internal switch. either a 650 khz or 1.2 mhz step- up switching regulator frequency can be chosen, allowing easy filtering and low noise operation. it achieves 93% efficiency and features soft start to limit the inrush current at startup. the internal voltage regulator operates with an input voltage range of 3 v to 5.5 v and delivers a load current of up to 350 ma. three selectable output voltages are available: 2.5 v, 2.85 v, and 3.3 v. the proprietary v com amplifier can deliver a peak output current of 300 ma and is specifically designed to drive tft panel loads. the gate pulse modulator allows shaping of the tft gate high voltage to improve image quality. the integrated switches provide the ability to independently control the delay and slope for the gate drive voltage. the add8754 is offered in a 24-lead, pb-free lfcsp package and is specified over the industrial temperature range of ?40 to +85c.
add8754 rev. 0 | page 2 of 28 table of contents specifications ..................................................................................... 3 step-up switching regulator specifications ............................. 3 ldo regulator specifications .................................................... 4 v com amplifier specifications .................................................... 5 gate pulse modulator specifications ......................................... 6 general specifications ................................................................. 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 current-mode, step-up switching regulator operation ..... 12 v com amplifier ........................................................................... 16 gate pulse modulator circuit ................................................... 16 power-up sequence ................................................................... 17 shutdown ..................................................................................... 17 uvlo ........................................................................................... 17 power dissipation ....................................................................... 18 layout guidelines ....................................................................... 19 typical application circuits ......................................................... 20 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 4/05revision 0: initial version
add8754 rev. 0 | page 3 of 28 specifications step-up switching regulator specifications vin_1 = vin_2 = shdn = 5 v, v out 1 = vdd_1 = vdd_2 = 14 v, t a = 25c, freq = gnd, unless otherwise noted. table 1. parameter symbol conditions min typ max unit supply input voltage range vin 3.0 5.5 v output 1 output voltage range v out 1 20 v load regulation 10 ma i load 150 ma, v out 1 = 10 v 200 v/ma line regulation i load = 350 ma, 4.5 v vin_1 5.5 v mv load regulation 10 ma i load 150 ma, v out 1 = 10 v 200 v/ma line regulation i load = 150 ma, 3.0 v vin_1 5.5 v mv overall regulation line, load, temperature (?40c t a +85c) ?3 +3 % reference feedback voltage vfb 1.200 1.211 1.220 v error amplifier transconductance g mea 100 a/v gain a v 1000 v/v input bias current i b 225 na switch on resistance r ds (on) 170 m leakage current i lkg v lx = 14 v, shdn = gnd 0.5 a peak current limit i cl 2.6 a oscillator oscillator frequency f osc freq = gnd 650 khz freq = vin_1 1.2 mhz maximum duty cycle d max vfb = 1 v 90 95 % soft start peak current ss = gnd 2.5 a 1 refer to the figure 23.
add8754 rev. 0 | page 4 of 28 ldo regulator specifications vin_1 = vin_2 = shdn = 5 v, adj = ldo_out, 1 cldo = 2.2 f, t a = 25c, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input input voltage range vin 2 adj = ldo_out 1 3.0 5.5 v adj = open 3 3.35 5.5 v adj = gnd 4 3.8 5.5 v output output voltage ldo_out i ldo = 1 ma, adj = gnd 3.31 v i ldo = 350 ma, adj = gnd 3.29 v i ldo = 1 ma, adj = open 2.86 v i ldo = 350 ma, adj = open 2.84 v i ldo = 1 ma, adj = ldo_out 2.51 v i ldo = 350 ma, adj = ldo_out 2.49 v voltage accuracy i ldo = 1 ma to 350 ma, ?40c t a +85c ?3 +3 % line regulation i ldo = 1 ma 3 mv/v load regulation i ldo = 1 ma to 350 ma 20 mv dropout voltage v drop ldo_out = 98% of ldo_out(nom), i ldo = 350 ma 300 500 mv current limit i ldpk 350 ma 1 sets ldo_out(nom) to 2.5 v. 2 vin = vin_1 = vin_2. 3 sets ldo_out(nom) to 2.85 v. 4 sets ldo_out(nom) to 3.3 v.
add8754 rev. 0 | page 5 of 28 v com amplifier specifications vin_1 = vin_2 = shdn = 5 v, vdd_2 = 14 v, pos = 4.0 v, neg = out, t a = 25c, unless otherwise noted. table 3. parameter symbol conditions min typ max unit input characteristics offset voltage v os 19 mv noninverting input bias current i b 50 300 na input voltage range 2 vdd_2 ? 3 v common-mode rejection ratio cmrr v cm = 2 v to (vdd_2 ? 3) v 60 db output characteristics output voltage swing v oh i out (source) = 50 ma vdd_2 ? 0.5 v v ol i out (sink) = 50 ma 50 mv output current 1 i out 300 ma power supply supply voltage vdd_2 8 18 v power supply rejection ratio psrr 7.5 v vdd_2 18.5 v 65 70 db supply current i sy no load, pos = vdd_2 /2 2 ma dynamic performance slew rate 2 sr r l = 10 k, c l = 10 pf 105 v/s gain bandwidth gbw ?3 db, r l = 10 k, c l = 10 pf 1.95 mhz 1 not short-circuit protected. 2 slew rate is the average of the rising and the falling slew rates.
add8754 rev. 0 | page 6 of 28 gate pulse modulator specifications vin_1 = vin_2 = shdn = 5 v, vgh = 20 v, vdd_1 = 14 v, t a = 25c, unless otherwise noted. table 4. parameter symbol condition min typ max unit input characteristics vgh voltage vgh 7 30 v vgh input current i vgh vflk = gnd, vdpm = ldo_out 95 a vdd_1 voltage 7 vgh v vdd_1 input current i vdd_1 vflk = vdpm = ldo_out 0.02 a control input characteristics vflk voltage low v lowflk 0.8 v vflk voltage high v highflk 2.2 v vflk input current i flk 0.9 vflk ldo_out ?1 +1 a vdpm voltage low v lowdpm 0.8 v vdpm voltage high v highdpm 2.2 v vdpm input current i vdpm 0.9 vdpm ldo_out ?1 +1 a switching characteristics vgh to vgh_m on resistance r vgh vdpm = vflk = ldo_out 60 vgh_m discharge current 1 i vgh_m vflk < 0.8 v, re = 33 k 8.0 ma delay characteristics delay time 2 t delay ce = 470 pf, re = 33 k 1.88 s 1 discharge current = 302.5/(re + 5000). 2 delay time = ce 4200. general specifications vin_1 = vin_2 = shdn = 5 v, t a = 25c, unless otherwise noted. table 5. parameter symbol conditions min typ max unit shutdown input voltage low v il 0.8 v input voltage high v ih 2.2 v shutdown pin input current gnd shdn 5.5 v ?1 +1 a total ground current shdn = gnd 2.0 a total v in current (i vin_1 + i vin_2 ) shdn = gnd ?1 +1 a undervoltage lockout uvlo rising threshold v uvlor vin_1 rising 2.8 v uvlo falling threshold v uvlof vin_1 falling 2.6 v quiescent current step-up regulator in nonswitching state i q 300 500 a step-up regulator in switching state i qsw 2 3 ma
add8754 rev. 0 | page 7 of 28 absolute maximum ratings t = 25c, unless otherwise noted. a table 6. parameter symbol rating stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. re, ce, fb, shdn , vin_2, freq, comp, ss, vin_1, ldo_out, adj, vdpm, vflk to gnd, pgnd, and agnd ?0.5 v to +6.5 v ?0.5 v to +16 v out, neg and pos to gnd, pgnd, and agnd lx to gnd, pgnd, and agnd ?0.5 v to +22 v vdd_2 and out to gnd, pgnd, and agnd ?0.5 v to +18.5 v absolute maximum ratings apply individually only, not in combination. 0.5 v voltage between gnd and agnd, gnd and pgnd, and agnd and pgnd ?0.5 v to +32 v vdd_1, vgh, and vgh_m to gnd, pgnd, and agnd 5 v differential voltage between pos and neg package power dissipation p d (t j max ? t a )/ ja thermal resistance ja 38c/w maximum junction temperature t j max 125c operating temperature range t a ?40c to +85c storage temperature range t s ?65c to +150c 250c reflow peak temperature (20 sec to 40 sec) esd caution esd (electrostatic discharge) sensit ive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
add8754 rev. 0 | page 8 of 28 pin configuration and fu nction descriptions 24 1 2 3 4 5 6 18 17 16 15 14 13 23 22 21 20 19 789101112 top view (not to scale) add8754 gnd vgh_m vflk vdpm vdd_1 vdd_2 lx vin_2 freq comp ss vin_1 05110-002 vgh re ce pgnd fb out neg pos agnd adj ldo_out shdn figure 2. pin configuration table 7. pin function descriptions pin mnemonic description 1 gnd ground. 2 vgh_m gate pulse modulator output. th is pin supplies the gate drive signal. 3 vflk gate pulse modulator control input. 4 vdpm gate pulse modulator enable. vgh_m is enabled when the vo ltage on this pin is more than 2.2 v. vgh_m goes to gnd when this pin is connected to gnd. 5 vdd_1 gate pulse modulator low voltage input. 6 vdd_2 v amplifier supply. com 7 out v amplifier output. com 8 neg inverting input of v amplifier. com 9 pos noninverting input of v amplifier. com 10 agnd analog ground. 11 adj ldo output voltage select. refer to table 13 for details. 12 ldo_out ldo output. 13 vin_1 supply input. this pin supplies power to the ldo and step-up switching regulator. typically connected to vin_2. 14 ss soft start. a capacitor must be connected be tween gnd and this pin to set the soft start time. 15 comp compensation for the step-up converte r. a capacitor and resistor are connected in series between gnd and this pin for stable operation. 16 freq frequency select. set the switching frequency with a logic level. the step-up switching regulator operates at 650 khz when this pin is connected to gnd and at 1.2 mhz when connected to vin_1. 17 vin_2 step-up switching regulator power supply. this pin su pplies power to the driver for the switch. typically connected to vin_1. 18 lx step-up switching regulator switch node. 19 shdn device shutdown pin. this pin allows users to shut the device off when connected to gnd. the normal operating mode is to pull this pin to vin_1. 20 fb feedback voltage sense to set the output voltage of the step-up switching regulator. 21 pgnd step-up switching regulator power ground. 22 ce gpm time delay. a capacitor must be connect ed between gnd and this pi n to set the delay time. 23 re gpm negative ramp rate. a resistor must be connected between gnd and this pin to set the negative ramp rate. 24 vgh gate pulse modulator high voltage input.
add8754 rev. 0 | page 9 of 28 typical performance characteristics freq = gnd freq = vin vin = 5v v out = 10v 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1k i load (ma) 05110-049 2.90 2.85 2.80 2.75 2.70 2.65 2.60 2.55 2.50 2.45 output voltage (v) 0 50 100 150 200 250 300 350 400 load current (ma) adj = open adj = ldo_out 05110-050 figure 3. efficiency vs. load current (ma) figure 6. ldo output voltage vs. load current, vin = 3.3 v 3.4 3.3 3.2 3.1 3.0 2.9 2.8 output voltage (v) 0 50 100 150 200 250 300 350 400 load current (ma) adj = gnd adj = open 05110-051 1 3 2 t 05110-026 ch1 = v out 5v/div ch2 = il 1a/div ch3 = sd 5v/div v in = 5v v out = 10v i out = 200ma c ss = 0f figure 7. ldo output voltage vs. load current, vin = 5 v figure 4. start-up response from shutdown, c ss = 0 f 6 5 4 3 2 1 0 ?1 volts (v) ?80 ?40 0 40 80 120 160 200 240 time ( s) 05110-052 280 sd pin 750nf output cap 10 f output cap 2.2 f output cap 1 3 2 t 05110-027 ch1 = v out 5v/div ch2 = il 1a/div ch3 = sd 5v/div v in = 5v v out = 10v i out = 200ma c ss = 10nf figure 8. ldo power-up response from shutdown figure 5. start-up response from shutdown, c ss = 10 f
add8754 rev. 0 | page 10 of 28 6 5 4 3 2 1 0 ?1 volts (v) ?80 ?40 0 40 80 120 160 200 240 time ( s) 05110-053 280 sd pin 750nf output cap 2.2 f output cap 10 f output cap 05110-056 3.32 3.30 3.28 3.26 400 200 0 v out (v) i load (ma) adj = gnd v out = 20mv/div i out = 200ma/div t load step from 30k to 10 figure 9. ldo power-up response from shutdown = 3.3 v figure 12. ldo load transient response, v out 6 5 4 3 2 1 0 ?1 volts (v) ?80 ?40 0 40 80 120 160 200 240 time ( s) 05110-054 280 750nf output cap 2.2 f output cap 10 f output cap sd pin t 05110-057 4v 3v 2v 1v v out (v) v in (v) adj = gnd v in high = 5.5v v in low = 3.8v figure 10. ldo power-up response from shutdown = 3.3 v figure 13. ldo line transient response, v out 05110-055 2.52 2.50 2.48 2.46 300 200 100 0 100 s adj = ldo_out v out = 20mv/div i out = 100ma/div v out (v) i load (ma) t 05110-058 4v 3v 2.5v 2v 1v v out (v) v in (v) adj = ldo_out v in high = 5.5v v in low = 3.8v = 2.5 v figure 11. ldo load transient response, v = 2.5 v figure 14. ldo line transient response, v out out
add8754 rev. 0 | page 11 of 28 50k 25k 10k 5k 0k 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 delay time ( s) 0 100 200 300 400 500 600 700 capacitance ce (pf) 05110-061 0 t 05110-059 1 ch1 2.00 v a ch1 12.0 v m 40.0ns : 8.00v @: 5.04v : 102ns @: ?83.2ns rising slew rate, vdd_2 = 14 v figure 15. v figure 17. gpm delay time vs. ce capacitance com 1 t 05110-060 ch1 2.00 v a ch1 5.16 v m 40.0ns : 8.08v @: 9.08v : 60.8ns @: 1.88 s falling slew rate, vdd_2 = 14 v figure 16. v com
add8754 rev. 0 | page 12 of 28 theory of operation uvlo and thermal protection vin_1 ref gate high mod. circuit ref slope comp osc add8754 f/f r s q bias fb freq v dd_2 out agnd shdn vgh vgh_m vdd_1 ce re vflk vdpm lx pgnd ldo_out adj pos neg vin_2 vin_1 ss comp 05110-048 g m gnd vdd_2 agnd v com a 20 nf soft start capacitor results in negligible input-current overshoot at startup, making it suitable for most applications. however, if an unusually large output capacitor is used, a longer soft start period is required to prevent large input inrush current. table 8. typical soft start period v figure 18. detailed functional block diagram current-mode, step-up switching regulator operation the add8754 uses current mode to regulate the output voltage. this current-mode regulation system allows fast transient response while maintaining a stable output voltage. by selecting the proper resistor-capacitor network from comp to gnd, the regulator response can be optimized for a wide range of input voltages, output voltages, and load conditions. frequency selection the add8754s frequency is user-selectable to operate either at 650 khz to optimize the regulator for high efficiency or at 1.2 mhz for small external components. connect freq to vin_2 for 1.2 mhz operation, or connect freq to gnd for 650 khz operation. soft start capacitor the voltage at ss ramps up slowly by charging the soft start capacitor (c ss ) with an internal 2.5 a current source. table 8 lists the values for the soft start period based on maximum output current and maximum switching frequency. the soft start capacitor limits the rate of voltage rise on the comp pin, which in turn limits the peak switch current at startup. table 8 shows a typical soft start period, t ss , at the maximum output current, i out_max , for several conditions. in (v) v out (v) c out (f) c ss (nf) t ss (ms) 3.3 9 10 20 2.5 3.3 9 10 100 8.2 3.3 12 10 20 3.5 3.3 12 10 100 15 5 9 10 20 0.4 5 9 10 100 1.5 5 12 10 20 0.62 5 12 10 100 2 on/off control the shdn input turns the add8754 on or off. when the step- up dc-to-dc converter is turned off, there is a dc path from the input to the output through the inductor and output diode. this causes the output voltage to remain slightly below the input voltage by the forward voltage of the diode, preventing the output voltage from dropping to zero when the regulator is shut down. see figure 25 for the typical application circuit to disconnect the output voltage from the input voltage at shutdown. setting the output voltage the add8754 features an adjustable output voltage range of (v in + 2 v) to 20 v. the output voltage is set by the resistive voltage divider from the output voltage (v out ) to the 1.21 v feedback input at fb. use the following formula to determine the output voltage: = 1.21 v (1 + r1 / r2 ) (1) v out use an r2 resistance of 10 k or less to prevent output voltage errors due to the 10 na fb input bias current. choose r1 based on the following formula: ? ? ? ? ? ? ? ? ? 21.1 21.1 r1 = r2 for example, r1 = 75.8 k = 10 v and r2 = 10 k (2) with v out
add8754 rev. 0 | page 13 of 28 inductor selection the inductor ripple current ( i l ) in steady state is the inductor is an integral part of the step-up converter. it stores energy during the switch-on time and transfers that energy to the output through the output diode during the switch-off time. use inductance in the range of 1 h to 22 h. in general, lower inductance values have higher saturation current and lower series resistance for a given physical size. however, lower inductance results in higher peak current, which can lead to reduced efficiency and greater input and/or output ripple and noise. peak-to-peak inductor ripple current at close to 30% of the maximum dc input current typically yields an optimal compromise. l t v on in i = (5) l solving for the inductance value, l , l on in i t v l = (6) make sure that the peak inductor current (the maximum input current plus half of the inductor ripple current) is less than the rated saturation current of the inductor. in addition, ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. for determining the inductor ripple current, the input (v in ) and output (v out ) voltages determine the switch duty cycle (d) by the following equation: d = out in out v vv ? (3) for duty cycles greater than 50% that occur with input voltages greater than half the output voltage, slope compensation is required to maintain stability of the current-mode regulator. for stable current-mode operation, ensure that the selected inductance is equal to or greater than l min : using the duty cycle and switching frequency, f sw , determine the on time by using the following equation: sw in out min f vv ll ? => a8.1 (7) sw f d t = (4) on table 9. inductor manufacturers vendor part l (h) max dc current max dcr (m) height (mm) cmd4d11-2r2mc 2.2 0.95 116 1.2 sumida www.sumida.com cmd4d11-4r7mc 4.7 0.75 216 1.2 cdrh4d28-100 10 1.00 128 3.0 cdrh5d18-220 22 0.80 290 2.0 cr43-4r7 4.7 1.15 109 3.5 cr43-100 10 1.04 182 3.5 ds1608-472 4.7 1.40 60 2.9 coilcraft www.coilcraft.com ds1608-103 10 1.00 75 2.9 d52lc-4r7m 4.7 1.14 87 2.0 toko www.tokoam.com d52lc-100m 10 0.76 150 2.0
add8754 rev. 0 | page 14 of 28 choosing the input and output capacitors diode selection the add8754 requires input and output bypass capacitors to supply transient currents while maintaining a constant input and output voltage. use a low effective series resistance (esr) 10 f or greater input capacitor to prevent noise at the add8754 input. place the capacitors between vin_1, vin_2, and gnd and as close as possible to the add8754. ceramic capacitors are preferred because of their low esr character- istics. alternatively, use a high value, medium esr capacitor in parallel with a 0.1 f low esr capacitor as close as possible to the add8754. the output diode conducts the inductor current to the output capacitor and load while the switch is off. for high efficiency, minimize the forward voltage drop of the diode. schottky diodes are recommended. however, for high voltage, high temperature applications, where the schottky diode reverse leakage current becomes significant and can degrade efficiency, use an ultrafast junction diode. the diode must be rated to handle the average output load current. many diode manufacturers derate the current capability of the diode as a function of the duty cycle. verify that the output diode is rated to handle the average output load current with the minimum duty cycle. the minimum duty cycle of the add8754 is the output capacitor maintains the output voltage and supplies current to the load while the add8754 switch is on. the value and characteristics of the output capacitor greatly affect the output voltage ripple and stability of the regulator. use a low esr output capacitor; ceramic dielectric capacitors are preferred. out max in out min v vv d _ ? = (12) for very low esr capacitors such as ceramic capacitors, the ripple current due to the capacitance is calculated as follows. because the capacitor discharges during the on time, t where v in_max is the maximum input voltage. on , the charge removed from the capacitor, q c , is the load current multiplied by the on time. therefore, the output voltage ripple ( v out ) is out on l out c out c t i c q v == (8) where: c out is the output capacitance. i l is the average inductor current. sw on f d t = (9) out in out v v v d ? = (10) choose the output capacitor based on the following equation: out out sw in out l out vvf vvi c ? ? ) ( (11) table 10. capacitor manufacturers vendor eb ddress avx www.avxcorp.com murata www.murata.com sanyo www.sanyovideo.com taiyo yuden www.t-yuden.com for example, d min = 0.45 when v = 10 v and v out in_max = 5.5 v table 11. schottky diode manufacturers vendor eb ddress on semiconductor www.onsemi.com diodes, inc. www.diodes.com central semiconductor corp. www.centralsemi.com sanyo www.sanyovideo.com loop compensation use of external components to compensate the regulator loop allows optimization of the loop dynamics for a given application. a step-up converter produces an undesirable right-half plane zero in the regulation feedback loop. this requires compensat- ing the regulator such that the crossover frequency occurs well below the frequency of the right-half plane zero. the right-half plane zero is determined by the following equation: l r v v rhpf load out in z ? ? ? ? ? ? ? ? = 2 )( 2 (13) where: f z (rhp) is the right-half plane zero. r load is the equivalent load resistance, or the output voltage divided by the load current.
add8754 rev. 0 | page 15 of 28 to stabilize the regulator, make sure that the regulator crossover frequency is less than or equal to one-fifth of the right-half plane zero and less than or equal to one-fifteenth of the switching frequency. for v the regulator loop gain is out cs comp mea out in out fb vl zgzg v v v v a = (14) where: a vl is the loop gain. v fb is the feedback regulation voltage, 1.210 v. v out is the regulated output voltage. v in is the input voltage. g mea is the error amplifier transconductance gain. z comp is the impedance of the series rc network from comp to gnd. g cs is the current sense transconductance gain (the inductor current divided by the voltage at comp), which is internally set by the add8754. z out is the impedance of the load and output capacitor. to determine the crossover frequency, it is important to note that at that frequency the compensation impedance ( z comp ) is dominated by the resistor and the output impedance ( z out ) is dominated by the impedance of the output capacitor. therefore, when solving for the crossover frequency, (by definition of the crossover frequency) the equation is simplified to 1 2 1 = = out c cscmea out in out fb vl cf grg v v v v a (15) where: f c is the crossover frequency. r c is the compensation resistor. solving for r c , cs mea infb out out out c c ggvv vvcf r = 2 (16) fb = 1.21 v, g mea = 100 s, and g = 2 sec, cs in out out out c c v vvcf r = 4 1055.2 (17) once the compensation resistor is known, set the zero formed by the compensation capacitor and resistor to one-fourth of the crossover frequency, or cc c rf c = 2 (18) where c c is the compensation capacitor. ref fb c2 c c r c error amp 05110-007 g mea figure 19. compensation components the capacitor c2 is chosen to cancel the zero introduced by output capacitance esr. solving for c2, c out r c esr c2 = (19) for low esr output capacitance, such as with a ceramic capaci- tor, c2 is optional. for optimal transient performance, the r c and c c might need to be adjusted by observing the load transient response of the add8754. for most applications, the compensation resistor should be in the range of 30 k to 400 k, and the compensation capacitor should be in the range of 100 pf to 1.2 nf. table 12 shows external component values for several applications. table 12. recommended external components fo r various input/output voltage conditions v in (v) v out (v) f sw l (h) c out (f) c in (f) r 1 (k) r 2 (k) r c (k) c c (pf) i out_max (ma) 5 9 650 khz 10 10 10 63.4 10 84.5 390 450 5 9 1.2 mhz 4.7 10 10 63.4 10 178 100 450 5 12 650 khz 10 10 10 88.7 10 140 220 350 5 12 1.2 mhz 4.7 10 10 88.7 10 300 100 350 3.3 9 650 khz 10 10 10 63.4 10 71.5 820 350 3.3 9 1.2 mhz 4.7 10 10 63.4 10 150 180 350 3.3 12 650 khz 10 10 10 88.7 10 130 420 250 3.3 12 1.2 mhz 4.7 10 10 88.7 10 280 100 250
add8754 rev. 0 | page 16 of 28 v com amplifier the delay capacitance in farad is calculated using the following equation: the output of the v com amplifier is designed to control the voltage on the v com plane of the lcd display. the v com amplifier is designed to source and sink the capacitive pulse current and ensure stable operation with high load capacitance. ce = ( delay time ) 0.000238 the re in ohms is calculated using the following equation: input overvoltage protection () 5000 302 ? = ecapacitanc loadrateslew re whenever the input exceeds the supply voltage, attention must be paid to the input overvoltage characteristics. when an overvoltage occurs, the amplifier can be damaged, depending on the voltage level and the magnitude of the fault current. when the input voltage exceeds the supply voltage by more than 0.6 v, the internal pin junctions allow current to flow from the input to the supplies. this input current is not inherently damaging to the device, provided it is 5 ma or less. when the voltage on the vdpm pin is less than the turn-on threshold value, the ce pin is internally connected to gnd to discharge the delay capacitor. s1 s2 s3 ref l o g i c gnd s4 vin_1 gate high mod. circuit gnd gnd ramp resistor delay capacitor ce re v out /vgh vdd_1 vgh_m vgh v dpm vflk cl 05110-008 short-circuit output conditions the v com amplifier does not have internal short-circuit protection circuitry. as a precaution, do not short the output directly to the positive power supply or to the ground. gate pulse modulator circuit the gate pulse modulator is used for lcd applications in which shaping of the gate high voltage signal improves image quality. a charge pump is used to generate the on voltage, vgh. a lower gate voltage level, vdd_1, is desired during the last portion of the gates on time and is provided by vout. the integrated gate pulse modulator circuit provides control over the slope and delay of the transition between these two tft on-voltage levels. figure 20. gate pulse modulator functional block diagram the gate pulse modulator circuit has four input pins (vgh, vdd_1, vdpm, and vflk) and one output pin (vgh_m). vflk is a digital control signal, usually provided by the timing controller, whose high or low level determines which of the two input voltages, vgh or vdd_1, is passed through to vgh_m. the gate high modulator circuit becomes active when the voltage on pin vdpm exceeds the turn-on threshold value of 2.2 v. enable ? vdpm control signal ? vflk output signal ? vgh_m with load capacitance cl low low low t1 t2 t1 t2 delay controlled by ce vgh vdd_1 slope controlled by re 05110-009 when the control voltage vflk switches from logic low to logic high during normal operation with vdpm at logic high (see figure 21 ), the output voltage vgh_m transitions from vdd_1 to vgh. when the control voltage vfk switches from logic high to logic low, the output voltage vgh_m transitions from vgh to vdd_1 after a time delay determined by the size of a capacitor from the ce pin to the gnd and a slew rate determined by the size of resistor from the re pin to the gnd. figure 21. gate pulse modulator timing diagram
add8754 rev. 0 | page 17 of 28 ldo input capacitor selection power-up sequence for the input voltage of the add8754 ldo regulator (vin_1), a local bypass capacitor is recommended. the input capacitor provides bypassing for the internal amplifier used in the voltage regulation loop. use at least a 1 f low esr capacitor. larger input capacitance and lower esr provide better supply noise rejection. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. most lcd panels require that when vin is applied, ldo_out, vgl, boost_out, vgh, and vgh_m are established sequentially, as indicated in figure 22 . add8754 provides this sequence with appropriate capacitors for the vgl and vgh charge pumps. vin vdpm vgh vgl boost_out ldo_out vgh_m 05110-010 shdn shdn threshold level ldo output capacitor selection the output capacitor improves the regulator response to sudden load changes. the output capacitor helps determine the perfor- mance of any ldo. the add8754 ldo requires at least a 2.2 f capacitor. transient response is a function of output capacitance, in that larger values of output capacitance decrease peak devia- tions, providing improved transient response for large load current changes. choose the capacitors by comparing their lead inductance, esr, and dissipation factor. output capacitance affects stability, and a larger cap provides a greater phase margin for the add8754 ldo. mlcc capacitors provide the best combination of low esr and small size. figure 22. power-up sequence timing diagram ldo regulator note that the capacitance of some capacitor types show wide variations over temperature. a good quality dielectric x7r or better capacitor is recommended. the add8754 low dropout (ldo) regulator has three preset output voltage settings. as shown in table 13 , by tying the adj pin low, a 3.3 v nominal output is selected. by tying adj to the output voltage, a 2.5 v nominal output is selected. by leaving adj as an open circuit, a nominal voltage of 2.85 v is selected. shutdown applying a ttl high signal to the shutdown pin (tying it to the vin_1) turns on all outputs. pulling shdn down to 0.4 v or below (tying it to gnd) turns off all outputs. in shutdown mode, quiescent current is reduced to a typical value of 300 a. table 13. ldo output voltage selection ldo output voltage adj pin 2.5 v ldo_out uvlo 2.85 v no connection an undervoltage lockout (uvlo) circuit is included with a built in hysteresis. add8754 turns on when vin_1 rises above 2.8 v and shuts down when vin_1 falls below 2.6 v. 3.3 v gnd
add8754 rev. 0 | page 18 of 28 power dissipation the add8754s maximum power dissipation depends on the thermal resistance from the ic die to the ambient environment and the ambient temperature. the thermal resistance depends on the ic package, pc board copper area, other thermal mass, and airflow. the add8754, with the exposed backside pad soldered to a 2-layer pc board with nine 12 mil-diameter thermal vias, can dissipate about 1.5 w into 65c still air before the die exceeds 125c. more pc board copper, cooler ambient air, and more airflow increase the dissipation capability, whereas less copper or warmer air decreases the ics dissipation capability. the major contributors to the power dissipation are the ldo regulator and the v com amplifier. step-up converter the largest portions of power dissipation in the step-up converter are the internal mosfet, the inductor, and the output diode. for a 90% efficiency step-up converter, about 3% to 5% of the power is lost in the internal mosfet, about 3% to 4% in the inductor, and about 1% in the output diode. the rest of the 1% to 3% is distributed among the input and output capacitors and the pc board traces. for an input power of about 3 w, the power lost in the internal mosfet is about 90 mw to 150 mw. ldo the power dissipated in the ldo depends on the output current, the output voltage, and the supply voltage: pd ldo = (vin_1 ? ldo_out) i ldo_out v com amplifier the power dissipated in the v com amplifier depends on the output current, the output voltage, and the supply voltage: pd source = i out ( source ) (v dd_2 ? v out ) pd sink = i out ( sink ) v out where: i out ( source ) is the output current sourced by the v com amplifier. i out ( sink ) is the output current that the v com amplifier sinks to agnd. in a typical case where the supply voltage is 12 v and the output voltage is 6 v with an output source current of 20 ma, the power dissipated is 120 mw. thermal overload protection thermal overload protection prevents excessive power dissipation from overheating the add8754. when the junction temperature exceeds t j = 145c, a thermal sensor immediately activates the fault protection, which shuts down the device, allowing the ic to cool. the device self-starts once the die temperature falls below t j = 105c. thermal overload protection protects the controller in the event of fault conditions. for continuous operation, do not exceed the absolute maximum junction temperature rating of t j = 125c.
add8754 rev. 0 | page 19 of 28 layout guidelines when designing a high frequency, switching, regulated power supply, layout is very important. using a good layout can solve many problems associated with these types of supplies. some of the main problems are loss of regulation at high output current and/or large input-to-output voltage differentials, excessive noise on the output and switch waveforms, and instability. using the following guidelines can help minimize these problems. make all power (high current) traces as short, direct, and thick as possible. it is good practice on a standard pcb board to make the traces an absolute minimum of 15 mil (0.381 mm) per ampere. the inductor, output capacitors, and output diode should be as close to each other as possible. this helps reduce the emi radiated by the power traces that is due to the high switching currents through them. this also reduces lead inductance and resistance, which in turn reduce noise spikes, ringing, and resistive losses that produce voltage errors. the grounds of the ic, input capacitors, output capacitors, and output diode (if applicable), should be connected close together, directly to a ground plane. it is also a good idea to have a ground plane on both sides of the printed circuit board (pcb). this reduces noise by reducing ground-loop errors and absorbing more of the emi radiated by the inductor. for multilayer boards of more than two layers, a ground plane can be used to separate the power plane (power traces and components) and the signal plane (feedback, compensation, and components) for improved performance. on multilayer boards, the use of vias is required to connect traces and different planes. if a trace needs to conduct a significant amount of current from one plane to the other, it is good practice to use one standard via per 200 ma of current. arrange the components so that the switching current loops curl in the same direction. due to the how switching regulators operate, there are two power states: one state when the switch is on, and one when the switch is off. during each state, there is a current loop made by the power components currently conducting. place the power components so that the current loop is conducting in the same direction during each of the two states. this prevents magnetic field reversal caused by the traces between the two half cycles and reduces radiated emi. layout procedure to achieve high efficiency, good regulation, and stability, a good pcb layout is required. it is recommended that the reference board layout be followed as closely as possible because it is already optimized for high efficiency and low noise. use the following general guidelines when designing pcbs: 1. keep cin close to the in and gnd leads of the add8754. 2. keep the high current path from cin (through l1) to the sw and pgnd leads as short as possible. 3. keep the high current path from cin (through l1), d1, and cout as short as possible. 4. keep high current traces as short and wide as possible. 5. keep nodes connected to sw away from sensitive traces such as fb or comp to prevent coupling of the traces. if these traces need to be run near each other, place a ground trace between the two as a shield. 6. place the feedback resistors as close as possible to the fb pin to prevent noise pickup. 7. place the compensation components as close as possible to the comp pin. 8. avoid routing noise-sensitive traces near the high current traces and components. 9. use a thermal pad size that is the same as the dimension of the exposed pad on the bottom of the package. heat sinking when using a surface-mount power ic or external power switches, the pcb can often be used as the heat sink. this is done by simply using the copper area of the pcb to transfer heat from the device.
add8754 rev. 0 | page 20 of 28 typical application circuits lx vin_2 freq comp ss vin_1 gnd vgh_m vflk vdpm vdd_1 vdd_2 out neg pos agnd adj ldo_ out vgh re ce pgnd fb c8 0.1 f r8 100k r7 250k +14v from v out vflk to gate driver r3 100k r4 250k c9 1 f cldo 4.7 f v logic +3.3v d1 1n5818 cout 20 f c sd 10 f r sd 180k l 10 h vin +5v v out +14v cin 10 f c ss 10nf r c 180k c c 470pf r9 10 r1 100k r2 9.5k ce 390pf c1 0.1 f c5 0.1 f bav99 d6 d7 c6 0.1 f r6 300 re 33k c10 0.47 f vz1 bzx84c5v1 vgl ?5v vz2 bzx84c28 c7 1 f c3 1 f c4 0.47 f c2 0.1 f d3 d2 d5 d4 bav99 bav99 r5 1k add8754 192021 22 23 24 1 2 3 4 5 6 78 9101112 18 17 16 15 14 13 05110-003 vcom +4.0v shdn +14v from v out +14v from v out figure 23. 1.2 mhz application circuit for tft lcd panel with charge pumps for vgh and vgl
add8754 rev. 0 | page 21 of 28 lx vin_2 freq comp ss vin_1 gnd vgh_m vflk vdpm vdd_1 vdd_2 out neg pos agnd adj ldo_ out vgh re ce pgnd fb c8 0.1 f r8 100k r7 250k vflk to gate driver r3 4.7k r4 7.5k c9 1 f +12v from v out +12v from v out cldo 4.7 f v logic +3.3v cvgl 0.1 f vin +5v v out +12v cin 10 f c ss 10nf r c 180k c c 470pf r1 91k r2 10k ce 390pf d2 1n914 re 33k cvgh 10 f add8754 192021 22 23 24 1 2 3 4 5 6 78 9101112 18 17 16 15 14 13 05110-004 vcom +4.0v cout 20 f vgl ?5v d1 1n5818 +30v vgh t shdn r12 1k +12v from v out rvgl 50 vz1 bzx84c5v1 rvgh 75 vz2 1n7451a d3 1n914 t = transtek magnetics tms60059cs figure 24. 1.2 mhz application circuit for tft lcd display with transformer for vgh and vgl
add8754 rev. 0 | page 22 of 28 lx vin_2 freq comp ss vin_1 gnd vgh_m vflk vdpm vdd_1 vdd_2 out neg pos agnd adj ldo_ out vgh re ce pgnd fb c8 0.1 f r8 100k r7 250k +14v from v out vflk to gate driver r3 100k r4 250k c9 1 f cldo 4.7 f v logic +3.3v d1 1n5818 cout 20 f l 10 h vin +5v v out +14v cin 10 f c ss 10nf r c 180k c c 470pf r9 10 r1 100k r2 9.5k ce 390pf c1 0.01 f c5 0.01 f bav99 d6 d7 c6 0.1 f r6 300 re 33k c10 0.47 f vz1 bzx84c5v1 vgl ?5v vz2 bzx84c28 vgh +28v c7 1 f c3 1 f c4 0.47 f c2 0.01 f d3 d2 d5 d4 bav99 bav99 r5 1k add8754 192021 22 23 24 1 2 3 4 5 6 78 9101112 18 17 16 15 14 13 05110-005 vcom +4.0v enable fdc6331 r10 10k shdn +14v from v out +14v from v out r sd 180k c sd 10 f figure 25. 1.2 mhz application circuit for tft lcd display with charge pumps with input power disconnect switch
add8754 rev. 0 | page 23 of 28 lx vin_2 freq comp ss vin_1 gnd vgh_m vflk vdpm vdd_1 vdd_2 out neg pos agnd adj ldo_ out vgh re ce pgnd fb c8 0.1 f r8 100k r7 250k +14v from v out vflk to gate driver r3 100k r4 250k c9 1 f cldo 4.7 f v logic +3.3v d1 1n5818 cout 20 f l 10 h vin +5v v out +14v cin 10 f c ss 10nf r c 180k c c 470pf r9 10 r1 100k r2 9.5k ce 390pf c1 0.01 f c5 0.01 f bav99 d6 d7 c6 0.1 f r6 300 re 33k c10 0.47 f vz1 bzx84c5v1 vgl ?5v vz2 bzx84c28 vgh +28v c7 1 f c3 1 f c4 0.47 f c2 0.01 f d3 d2 d5 d4 bav99 bav99 r5 1k add8754 19 2021 22 23 24 1 2 3 4 5 6 78 9101112 18 17 16 15 14 13 05110-047 vcom +4.0v r10 10k shdn +14v from v out +14v from v out q1 2n7000 boost and charge pump enable figure 26. 1.2 mhz application circuit for tft lcd display with ldo_always_ on
add8754 rev. 0 | page 24 of 28 out neg pos agnd adj ldo_ out r b 6k c10 2.2pf add8754 05110-006 vcom 4.0v r a 1k ad5259brmz10 vdd vlogic scl sda a w b gnd ad0 ad1 r4 315k v out 14v r3 10k c9 0.1 f r10 2.2k r11 2.2k signal from factory pc, software provided by adi a djustable from 3v to 5v wit h 15mv per step adjustment figure 27. add8754 with programmable v com the v com calibration for flicker reduction is one of the essential steps in the panel manufacturing process. in a typical panel production environment, such a process can take additional time to complete and, therefore, impacts production throughput. one additional concern is that a potentiometer typically used only for calibration offers limited resolution. the resistance can drift over time and can be noticeable after a few years of operation. the production throughput, image quality, and panel reliability concerns can all be solved by using a digital potentiometer. as shown in figure 27 , ad5259, a low cost 256-step digital poten- tiometer with nonvolatile memory, can calibrate the add8754 v com voltage precisely, reliably, and time efficiently. in the worst case, where the temperature, aging effect, and resistance tolerance of the ad5259 are all accounted for, the circuit in figure 27 makes the v com voltage adjustable from 3.0 v to 5.0 v with 15 mv per step adjustment. a micro- controller or i 2 c programmer can be used to provide the control signal for the ad5259, but adi provides programming software that simplifies the calibration process. the software can be installed in the factory computer, and two tester probes can be connected to the computers parallel port to implement the v com programming. the v com voltage can be calculated as out ab ab com v rrr rr d v ++ + = 7 256 3 4 3 where: d is the decimal code of the ad5259 programmable resistance between the w-to-b terminals. r ab is the ad5259 nominal resistance.
add8754 rev. 0 | page 25 of 28 outline dimensions 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant to jedec standards mo-220-vggd-2 figure 28. 24-lead lead frame chip scale package [lfcsp_vq] 4 4 mm body, very thin quad (cp-24-1) dimensions shown in millimeters ordering guide model temperature range package description package option quantity ADD8754ACPZ-REEL ?40c to +85c 24-lead lfcsp_vq cp-24-1 5,000 1 ADD8754ACPZ-REEL7 ?40c to +85c 24-lead lfcsp_vq cp-24-1 1,500 1 1 z = pb-free part.
add8754 rev. 0 | page 26 of 28 notes
add8754 rev. 0 | page 27 of 28 notes
add8754 rev. 0 | page 28 of 28 notes ?2005 analog devices, inc. all ri ghts reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05110C0C4/05(0)

▲Up To Search▲

Price & Availability of ADD8754ACPZ-REEL

	To Download ADD8754ACPZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .