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fujitsu semiconductor data sheet ds05303351e 1 memory flash memory card mb98a808ax-/809ax-/810ax-/811ax-20 flash erasable and programmable memory card 256k / 512k / 1m / 2m-byte description the fujitsu mb98a808ax, MB98A809AX, mb98a810ax and mb98a811ax are flash electrically erasable and programmable (flash) memory cards capable of storing and retrieving large amounts of data. the memory circuits are housed in a credit-card sized 68-pin package. internal circuit is protected by two metal panels, one at the top and bottom of the card, that help to reduce chip damage from electrostatic discharge. a unique feature of the fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus configuration. all cards are portable and operate on low power at high speed. in accordance with the personal computer memory card international association (pcmcia) and japan electrical industry development association (jeida) industry standard specification, flash memory cards offer additional eeprom memory that is used to store attribute data. the attribute memory is a flash memory card option. (see page 2 for description of the three available options.) ? conformed to pcmcia and jeida industry standards. ? credit card size : 85.6mm (length) 54.0mm (width) 3.3mm (thick) ? pcmcia / jeida conformed two-piece 68-pin connector (with a two-row built-in receptacle) ? single +5.0 v 5% power supply (+12.0 v 5%vpp) ? command control for write / erase operation ? write protect function this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. package crd-68p-m17
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 2 absolute maximum ratings (see warning) parameter supply voltage symbol value unit output voltage ambient temperature storage temperature 0.5 to +6.0 v v v c c input voltage warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc v in v out t a t stg 0 to +60 30 to +70 v v pp1 , v pp2 2.0 to +14.0 programming voltage * 1 note: * 1 minimum dc input voltage is 0.5 v. 0.5 to v cc +0.5 0.5 to v cc +0.5 t bias 10 to 70 c storage temperature at turning on the power
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 3 attribute memory options eeprom 1pcs 300 ns 300 ns 300 ns 300 ns eeprom 1pcs eeprom 1pcs eeprom 1pcs option 2: attribute memory in a separate location is not supported. when reg line is asserted, affo is output to the data bus to indicate that attribute data may be stored in main memory. option 1: attribute memory is not supported. reg pin : not contacted option 3: attribute memory is supported. the data is stored in 16k-bit eeprom. when the reg line is asserted, data stored in eeprom is output to the data bus. part number main memory access time memory device attribute memory access time memory device mb98a808a3 mb98a809a3 mb98a810a3 mb98a811a3 note: * to be configured by user. memory organization * 200 ns part number main memory access time memory device attribute memory access time memory device mb98a808a2 mb98a809a2 mb98a810a2 mb98a811a2 memory organization * n / a n / a n / a n / a n / a n / a n / a n / a pcmcia and jeida standard memory cards from fujitsu provide a separate eeprom memory address space for recording fundamental card information. it is used by the card manufacturers to record basic configuration information such as device type, size, speed, etc. the attribute memory is selected by asserting the reg pin on the card interface. option descriptions as follows: 200 ns 200 ns 200 ns 200 ns 200 ns 200 ns 200 ns part number main memory access time memory device attribute memory access time memory device mb98a808a1 mb98a809a1 mb98a810a1 mb98a811a1 memory organization * n / a n / a n / a n / a n / a n / a n / a n / a 200 ns 1m flash memory 2pcs 1m flash memory 16pcs 1m flash memory 4pcs 1m flash memory 8pcs 200 ns 200 ns 200 ns 256k 8 bits/ 128k 16 bits 512k 8 bits/ 256k 16 bits 1m 8 bits/ 512k 16 bits 2m 8 bits/ 1m 16 bits 256k 8 bits/ 128k 16 bits 512k 8 bits/ 256k 16 bits 1m 8 bits/ 512k 16 bits 2m 8 bits/ 1m 16 bits 256k 8 bits/ 128k 16 bits 512k 8 bits/ 256k 16 bits 1m 8 bits/ 512k 16 bits 2m 8 bits/ 1m 16 bits 1m flash memory 2pcs 1m flash memory 16pcs 1m flash memory 4pcs 1m flash memory 8pcs 1m flash memory 2pcs 1m flash memory 16pcs 1m flash memory 4pcs 1m flash memory 8pcs
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 4 ce 0 ce 15 a0 a1 bvd1 bvd2 d0 17 8 8 gnd v cc d15 1mb flash memory 1 (mb98a808ax) 2 (MB98A809AX) 4 (mb98a810ax) 8 (mb98a811ax) internal circuit r1 = 10 k w r r = 100 k w fig. 1 mb98a808ax, 809ax, 810ax, and 811ax block diagram 11 r r r 16k eeprom *1 input decoder & buffer i/o trans- ceiver & buffer v cc ? ? ? ? ? ? ? ? ? ? add add i/o i/o * 1 eeprom is only available in option 3 (for attribute memory) flash memory cards. * 2 see pins 47, 48, and 49 in apin assignments.o *3 n.c. terminal in mb98a8xxa1 series. add i/o v pp v pp v pp1 v pp2 1 (mb98a808ax) 2 (MB98A809AX) 4 (mb98a810ax) 8 (mb98a811ax) a18 * 2 a19 * 2 a20 * 2 notes: wp r r 1mb flash memory wp.sw we oe ce 1 ce 2 cd 1 cd 2 we oe ce we oe ce oe we cs reg *3 a17 c1
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 5 pin assignments cd 1cd 1cd 1cd 1 MB98A809AX mb98a808ax mb98a811ax gnd d3 d4 d5 d6 d7 a10 a11 a9 a8 a13 a14 n.c. a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 wp gnd gnd d3 d4 d5 d6 d7 a10 a11 a9 a8 a13 a14 n.c. a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 wp gnd gnd d3 d4 d5 d6 d7 a10 a11 a9 a8 a13 a14 n.c. a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 wp gnd v cc mb98a810ax gnd d3 d4 d5 d6 d7 a10 a11 a9 a8 a13 a14 n.c. a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 wp gnd gnd d11 d12 d13 d14 d15 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. d8 d9 d10 gnd gnd d11 d12 d13 d14 d15 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. d8 d9 d10 gnd gnd d11 d12 d13 d14 d15 n.c. n.c. n.c. a17 n.c. n.c. n.c. n.c. n.c. n.c. n.c. d8 d9 d10 gnd gnd d11 d12 d13 d14 d15 n.c. n.c. n.c. a17 n.c. n.c. n.c. n.c. n.c. n.c. d8 d9 d10 gnd pin no. 135 236 3 4 37 5 38 6 39 7 40 8 41 9 42 10 43 11 44 12 45 13 46 14 47 15 48 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 49 a16 a17 a17 v pp 1v pp 2 bvd2 bvd1 bvd2 bvd1 bvd2 bvd1 bvd2 bvd1 v cc v cc v cc v cc v cc v cc v cc v pp 1v pp 1v pp 1v pp 2v pp 2v pp 2 a18 a18 a19 a18 a19 a20 MB98A809AX mb98a808ax mb98a811ax mb98a810ax a18 *1 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. *1: a18 doesn't relate with aho and alo level. *2: n.c. terminal in mb98a8xxa1 series. ce 1ce 1ce 1ce 1 ce 2ce 2ce 2ce 2 oe oe oe oe we we we we reg /n.c. *2 reg /n.c. *2 reg /n.c. *2 reg /n.c. *2 cd 2cd 2cd 2cd 2
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 6 pin descriptions symbol pin name input/output function a0 to a20 d0 to d15 ce 1 ce 2 oe we cd 1, cd 2 wp bvd1, bvd2 v cc gnd n.c. address input data input/output card enable for lower byte card enable for upper byte output enable write enable card detect write protect battery voltage detect power supply ground non connection input input/output input input input input output output output address inputs, a0 to a20. data inputs/outputs. this data bus size (8-bit or 16-bit) is selected with ce 1 and ce 2. active low. lower byte (d0 to d7) is selected for read / write / erase function of flash memory cards. active low. upper byte (d8 to d15) is selected for read / write / erase function of flash memory cards. active low. output enable for flash memory cards. active low. write enable for flash memory cards. these pins detect if the card has been correctly inserted. both pins are tied to gnd internally. write controller for flash memory cards. this pin outputs the protect / non protect status of awp switcho. power supply voltage. (+5.0 v 5%) system ground. v pp 1 v pp 2 programming voltage 1 programming voltage 2 input input programming voltage for lower byte. programming voltage for upper byte. both pins are tied to v cc internally. reg attribute memory select input active low. attribute memory is selected for read / write func- tion of identification data of flash memory cards. (n.c. or affo data or attribute data.) pin locations 34 68 1 35 fig. 2 bottom view (connector side) front side back side
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 7 function truth table main memory function * 1 d out (upper byte) ce 2ce 1a0oe we v pp 2v pp 1 mode h h h l l x h l l l h x l h x x x xx x l l l l hh h h h h v ppl standby read ( 8) read ( 8) read ( 8) read ( 16) output disable data input / output high-z high-z high-z high-z high-z d out d out (lower byte) d8 to d15 d0 to d7 p or np p or np p or np p or np p or np p or np wp sw wp * 2 x x x x x x d out (upper byte) v ppl v ppl v ppl v ppl v ppl v ppl v ppl v ppl v ppl v ppl v ppl read function (reg =v ih ) d out d out ce 2ce 1a0oe we v pp 2v pp 1 mode h h h l l x h l l l h x l h x x x xx x l l l l h l h h h v ppl * 3 standby read ( 8) read ( 8) read ( 16) write ( 16) output disable data input / output high-z high-z high-z high-z high-z d in d8 to d15 d0 to d7 h h l l l l h l x x l h h h h h h l l l h read ( 8) write ( 8) write ( 8) write ( 8) high-z high-z d out high-z wp * 2 x l l l l l l l l l l p or np np np np np wp sw notes: * 1 h = v ih , l = v il , x = either v il or v ih , wp sw = write protect switch, p = protect , np = non protect * 2 l-level is output when wpsw=np. h-level is output when wpsw=p. * 3 v ppl is recommended though it is functionable at v pph . v ppl *3 v ppl *3 v ppl *3 erase / write / verify function (reg =v ih ) np np np np np v pph v pph v pph v pph v pph v pph v pph v pph v pph v pph v pph v pph v pph v pph d out d in d in d in v ppl *3 v ppl *3
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 8 function truth table (continued) ce 2 h mode h d7 to d0 data input/output h h h l h l l l l h x h l l h x x l l h h h x h h l l l d15 to d8 l l l l l l np standby high-z high-z high-z d out * 3 l l l x h l l x x x x x l l h h h h l h l l l l output disable high-z high-z wp sw. high-z d in high-z high-z (lower byte) (lower byte) h x high-z h d out * 3 (lower byte) d in (lower byte) x h np np np np np np np np np h h h h h l h l l l l h x h l l h x x l l h h h x h h l l l h p standby high-z high-z high-z l l l x h l l x x x x x l l h h h h l h output disable high-z high-z h h h d out * 3 (lower byte) d out * 3 (lower byte) output disable output disable output disable output disable high-z high-z high-z p p p p p p p p p high-z notes: * 1 h = v ih , l = v il , x = either v il or v ih , wp sw = write protect switch, p = protect , np = non protect * 2 n.c. for mb98a808a1, 809a1, 810a1, and 811a1. * 3 h-level is output for mb98a808a2, 809a2, 810a2, and 811a2. h h h h h h h h h attribute memory function * 1 (reg = v il ) * 2 ce 1a0oe we wp read ( 8) read ( 8) write ( 8) write ( 8) read ( 8) write ( 8) read ( 16) write ( 16) read ( 16) read ( 8) read ( 8) read ( 8)
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 9 write / erase chip decoding information note: h=v ih , l=v il , x=either v ih or v il ce 2ce 1a0 h bus organization chip 0 chip 1 chip 2 chip 3 chip 4 chip 5 chip 6 chip 7 chip 8 chip 9 chip 10 chip 11 chip 12 chip 13 chip 14 chip 15 chip 0, chip 1 chip 1 chip 3 chip 5 chip 7 chip 9 chip 13 chip 15 chip 2, chip 3 chip 4, chip 5 chip 6, chip 7 chip 8, chip 9 chip 10, chip 11 chip 12, chip 13 chip 14, chip 15 chip 11 l h l h l h l h l h l h l h l h l h l h l h l h l h l h l h l l h l h l h l h l h l h l h l h l h l h l h l h l h l h l l l h x x a21 a22 a23 8-bit bus 16-bit bus decode chips
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 10 command definition table command table for 8-bit mode write read intelligent id codes * 4 second bus cycle operation * 1 address * 2 data * 3 first bus cycle operation * 1 address * 2 data * 3 write write write write write write read write write read write 00h 90h 20h a0h 40h ch ffh za wa wa za wa wa 20h evd wd wvd ffh bus cycle required read memory set up erase / erase * 5 erase verify *5 set up write / write * 6 write verify * 6 command reset *7 *8 1 3 2 2 2 2 2 ra ia za ea za ea read id ia eee command table for 16-bit mode write read intelligent id codes * 4 second bus cycle operation * 1 address * 2 data * 3 first bus cycle operation * 1 address * 2 data * 3 write write write write write write read write write write 0000h 9090h 2020h a0a0h 4040h c0c0h ffffh za wa wa za wa wa 2020h evd wd wvd ffffh bus cycle required read memory set up erase / erase * 5 erase verify *5 command reset *7 *8 1 3 2 2 2 2 2 ra ia za ea za ea set up write / write * 6 write verify * 6 read read eee ia id notes: * 1 bus operations are defined in afunction truth tableo. * 2 ia = identifier address: 00h for manufacturer code, 01h for device code. ea = address of memory location to be read during erase verify. ra = read address wa = address of memory location to be written. za = address of 128k-byte zones involved in erase operation. addresses are latched on the falling edge of the write enable pulse. * 3 id = data read from location ia during device identification. manufacturer = 31h for 8-bit, 3131h for 16-bit / device = b4h for 8-bit, b4b4h for 16-bit evd = data read from location ea during erase verify. wd = data to be programmed at location wa. data is latched on the rising edge of write enable. wvd = data read from location wa during write verify. wa is latched on the write command. * 4 following the read intelligent id command, two read operations access manufacturer and device codes. * 5 aerase flowcharto in fig.6, fig.7 and fig.8 illustrate the erase algorithm. * 6 awrite flowcharto in fig.4 and fig.5 illustrate the write algorithm. *7 the second bus cycle must be followed by the desired command register write. *8 the reset command operates on a zone basis. to reset the entire card requires reset write cycles to each zone.
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 11 address configurations * 1 (main memory) d7 to d0 8-bit bus organization (ce 1 = v il , ce 2 = v ih ) 0000 0001 0010 0011 1100 1101 1110 1111 h h h h h h h h l l l l l l l l d15 to d8 0 add. 1 add. 2 add. 3 add. 2,097,148 add. 2,097,149 add. 2,097,150 add. 2,097,151 add. 8-bit bus organization (ce 1 = v ih , ce 2 = v il ) * 2 * 1 h = v ih , l = v il , x = either 0 or 1. *2 even addresses are not available in this mode. 16-bit bus organization (ce 1 = v il , ce 2 = v il ) 0 0 0 0 1 1 1 1 notes: 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 a20 to a0 h h h h h h h h l l l l l l l l 1 add. 3 add. 5 add. 7 add. 2,097,145 add. 2,097,147 add. 2,097,149 add. 2,097,151 add. d7d0 d15d8 l l l l l l l l 1 add. 3 add. 5 add. 7 add. 2,097,145 add. 2,097,147 add. 2,097,149 add. 2,097,151 add. l l l l l l l l 0 add. 2 add. 4 add. 6 add. 2,097,144 add. 2,097,146 add. 2,097,148 add. 2,097,150 add. ce 2ce 1 d7 to d0 000x 001x 010x 011x 100x 101x 110x 111x d15 to d8 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 a20 to a0 ce 2ce 1 d7 to d0 000x 001x 010x 011x 100x 101x 110x 111x d15 to d8 0 0 0 0 1 1 1 1 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 a20 to a0 ce 2ce 1
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 12 recommended operating conditions parameter symbol unit min v cc t a v c v cc supply voltage ambient temperature max 0 4.75 5.25 +55 v typ. 5.0 0 gnd ground ee e dc characteristics * 1 this value does not apply to ce 1, ce 2, we and reg . * 2 this value does not apply to bvd1, bvd2, cd 1 and cd 2. *3 this value apply to v pp1 and v pp2 . * 4 this value does not apply to bvd1 and bvd2. * 5 write / erase are inhibited when v pp =v ppl . parameter symbol max unit ma ma min test condition i cc1 i cc2 i li i lo v cc =v cc max v in =0 v or v cc i ol =3.2 ma, v cc =v cc min v ih v il 0.8 m a input leakage current * 1 output leakage current * 2 v cc standby current v cc active read current v cc write current v cc erase current v pp read current or *3 standby current v pp write current *3 v pp erase current *3 input low voltage input high voltage v cc =v cc max ce 1=ce 2=v ih v cc =v cc max ce 1=ce 2=v il cyc. =200 ns, i out =0 ma write in progress erase in progress v pp v cc v pp >v cc v pp =v pph erase in progress v pp =v pph write in progress i oh =2.0 ma, v cc =v cc min m a ma ma ma ma v v i cc3 i sb1 i pp1 i pp2 i pp3 0.3 0.9 1.8 9 7 30 30 250 20 20 1.0 1.0 typ 0.9 1.7 85 125 2.0 20 10 30 value notes: i sb2 v cc =v cc max ce 1=ce 2=v cc 0.2 v v cc =v cc max v in =0 v or v cc 7.0 14.0 ma ma 250 v pp leakage current *3 i pps output low voltage output high voltage * 4 v pp during read-only operation v pp during write/erase operation v oh v ol v pph v ppl v pp v cc note: *5 2.4 3.8 0 11.4 v cc +0.3 0.4 6.5 12.6 m a ma v v v v e e e e e e e ee e e e e e e e e e e e e e e e e
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 13 capacitance (t a =25 c, f=1mhz, v in =v i/o =gnd) *1 this value does not apply to ce 1, ce 2, we and reg . *2 this value does not apply to ce 1, ce 2, bvd1 and bvd2. parameter symbol unit min c in c i/o pf input capacitance * 1 i/o capacitance * 2 max 50 50 pf notes: e e fig. 3 ac test conditions ? input pulse levels: 0.6 v to 2.6 v ? input pulse rise and fall times: 5 ns (transient between 0.8 v and 2.4 v) ? timing reference levels input: v il = 0.8 v, v ih = 2.4 v output: v ol = 0.8 v, v oh = 2.0 v ? output load +5 v r1 r2 c l d out (i/o) * including jig and stray capacitance all parameters except t clz , t olz , t ehqz , t df , t rclz , t rolz , t rchz and t rohz t clz , t olz , t ehqz, tdf , t rclz , t rolz , t rchz and t rohz 1.8 k w r1 1.8 k w r2 990 w 990 w c l 100 pf 5 pf parameter measured load i load ii
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 14 ac characteristics (at recommended operating conditions unless otherwise noted.) parameter symbol max unit min 200 ns read cycle time card enable access time address access time output enable access time card enable to output in low-z * 2 output enable to output in low-z * 2 output hold from address, ce , or oe change * 3 t rc t ce t acc t oe t clz t olz t oh ns ns ns ns ns ns 200 200 100 5 5 5 t df 60 ns output disable to output in high-z * 2 card disable to output in high-z * 2 t ehqz 60 ns main memory read cycle * 1 e e e e e e e e e ns 300 ns 300 300 ns 150 ns ns ns 5 5 ns 60 ns 5 60 ns attribute memory read cycle * 1 * 4 read cycle time t rrc address access time t raa card enable access time t rce output enable access time t roe output hold from address change t roh card enable to output low-z * 2 t rclz output enable to output low-z * 2 t rolz card enable to output high-z * 2 t rchz output enable to output high-z * 2 t rohz * 1 rise / fall time < 5 ns. * 2 transition is measured at the point of 500 mv from steady state voltage. this parameter is specified using load ii in fig.3. * 3 this parameter is specified from the rising edge of oe , ce 1 and ce 2, whichever occurs first. * 4 this parameter is for mb98a808a3, 809a3, 810a3, and 811a3. notes: parameter symbol max unit min e e e e e e e e e
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 15 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) main memory read cycle timing diagram (we = v ih , reg = v ih ) ce 1 = oe = v il , ce 2 = v ih : 8-bit bus organization read cycle 1: address (a0 to a20) d0 to d7 previous data valid data valid t acc t oh v ih v il v oh v ol note: *1 a0 = either v ih or v il . previous data valid data valid ce 1 = v ih , ce 2 = oe = v il : 8-bit bus organization read cycle 2: address * 1 (a1 to a20) d8 to d15 or d0 to d15 t acc t oh v ih v il v oh v ol : undefined ce 1 = ce 2 = oe = v il : 16-bit bus organization t rc t rc
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 16 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) oe ce 1 main memory read cycle timing diagram (we = v ih , reg = v ih ) ce 2 = v ih : 8-bit bus organization read cycle 3: address (a0 to a20) high-z data valid t acc t oe v ih v il v oh v ol : undefined t ce v ih v il v ih v il t oh d0 to d7 t rc t clz t olz t ehqz t df
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 17 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) oe ce 1 = ce 2 oe ce 2 t df main memory read cycle timing diagram (we = v ih , reg = v ih ) note: *1 a0 = either v il or v ih . high-z data valid d8 to d15 ce 1 = v ih : 8-bit bus organization read cycle 4: address *1 (a1 to a20) t acc t oe v ih v il v oh v ol t ce v ih v il v ih v il t oh t rc t clz t olz t ehqz ce 1 = ce 2 = v il : 16-bit bus organization read cycle 5: : undefined high-z data valid d0 to d15 address *1 (a1 to a20) t acc t oe v ih v il v oh v ol t ce v ih v il v ih v il t oh t rc t clz t olz t ehqz t df
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 18 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) oe ce 1 attribute memory read cycle timing diagram (we = v ih , reg = v il ) * 1 : undefined notes: ce 2 = v ih : 8-bit bus organization read cycle 2: previous data valid data valid ce 1 = oe = v il , ce 2 = v ih : 8-bit bus organization read cycle 1: address * 2 (a0 to a11) d0 to d7 or d0 to d15 *3 t raa t roh v ih v il v oh v ol t rrc high-z data valid d0 to d7 address (a0 to a11) t raa t roe v ih v il v oh v ol t rce v ih v il v ih v il t rohz t rrc t rclz t rolz t rchz ce 1 = ce 2 = oe = v il : 16-bit bus organization * 1 this timing diagram is for mb98a808a3, 809a3, 810a3, and 811a3. affo data is available on mb98a808a2, 809a2, 810a2, and 811a2 only. * 2 a0 = either v ih or v il during 16 bits bus organization. *3 h-level is output from d8 to d15. t roh
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 19 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) oe ce 1 = ce 2 d0 to d7 * 3 : undefined high-z data valid address * 2 (a1 to a11) t raa t roe v ih v il v oh v ol t rce v ih v il v ih v il t rohz t rrc t rclz t rolz t rchz t roh ce 1 = ce 2: 16-bit bus organization read cycle 3: notes: attribute memory read cycle timing diagram (we = v ih , reg = v il ) * 1 * 1 this timing diagram is for mb98a808a3, 809a3, 810a3, and 811a3. affo data is available on mb98a808a2, 809a2, 810a2, and 811a2 only. * 2 a0 = either v ih or v il . * 3 h-level is output from d8 to d15.
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 20 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) t cp parameter symbol max unit min 200 notes: ns write cycle time address set up time address hold time data set up time data hold time write recovery time before read card enable set up time before write t wc t as t ah t ds t dh t whgl ns ns ns ns m s card enable hold time write enable pulse width write enable pulse width high duration of write operation * 3 duration of erase operation * 3 t cs t ch t wp t wph t whwh1 t whwh2 0 100 80 30 6 40 0 100 60 10 9.5 m s ns ns ns ns t ws t wh t cph 0 0 140 60 ns ns ns ns card enable pulse width card enable pulse width high write enable set up time write enable hold time * 1 read timing parameters during write / erase operations are the same as during read only operations. refer to ac characteristics for main memory read cycle. * 2 rise/fall time 5 ns. * 3 the integrated stop timer terminates the write / erase operations, thereby eliminating the need for a maximum specification. main memory write / erase cycle * 1 * 2 read recovery time before write t ghwl 0 m s v pp set up time to chip enable low t ghwl 1.0 ms m s e e e e e e e e e e e e e e e e e e
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 21 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) rating min max unit typ 1.0 *2 sec. chip erase time *1 chip write time write / erase cycle sec. cycle 2.0 *2 100,000 main memory write / erase performance * 1 10 12.5 *3 notes: * 1 excludes 00h writing prior to erasure. *2 t a = 25 c, v pp = 12 v, 100,000 cycles. *3 minimum byte writing time excluding system overhead is 16 m s (10 m s program + 6 m s write recovery), while maximum is 400 m s/byte. (16 m s 25 loops allowed by algorithm). e e ee parameter symbol max unit min note: address set up time address hold time data set up time data hold time write recovery time card enable set up time t ras t rcs t roes t rwp t rah ns ns ns ns card enable hold time write pulse width t rds t rdh t rch t roeh t rre 20 0 20 100 50 50 20 0 20 50 ns ns ns ns t rrbo t rweh 100 10 ns ns write enable hold time * 1 this parameter is for mb98a808a3, 809a3, 810a3, and 811a3. attribute memory write cycle * 1 output enable set up time output enable hold time end of write to output time ns ns write cycle time t rwr ms 10 n 10000 times number of write per byte e e e e e e e e e e e e e e
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 22 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) program command latch address & data pro- gram- ming program verify command program verify setup progrm command data in = 40h data in data in = c0h : undefined main memory write cycle timing diagram (we = controlled) * 1 write cycle 1: ce 2 = v ih : 8-bit bus organization note: *1 a0, a18, a19 and a20 have to be fixed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. t wc t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh1 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t oh high-z t clz t ce t vpel valid data we oe ce 1 v ih v il address (a1 to a17) v ih v il v ih v il v ih v il v ih v il d0 to d7 v ppl v pp address (a0, a18, a19, a20) 12 v v ih v il t wp t olz
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 23 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) program command latch address & data pro- gram- ming program verify command program verify setup program command data in = 40h data in data in = c0h : undefined main memory write cycle timing diagram (we = controlled) * 1 write cycle 2: ce 1 = v ih : 8-bit bus organization notes: *1 a0, a18, a19 and a20 have to be fixed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh1 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il address (a1 to a17) v ih v il v ih v il v ih v il v ih v il d8 to d15 v ppl v pp address*2 (a0, a18, a19, a20) 12 v v ih v il t wp t wc
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 24 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) program command latch address & data pro- gram- ming program verify command program verify setup program command data in = 4040h data in data in = c0c0h main memory write cycle timing diagram (we = controlled) * 1 write cycle 3: ce 1 = ce 2: 16-bit bus organization notes: *1 a0, a18, a19 and a20 have to be fixed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh1 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1=ce 2 v ih v il address (a1 to a17) v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a0, a18, a19, a20) 12 v v ih v il t wp t wc d0 to d15 : undefined
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 25 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) data in = 40h data in data in = c0h main memory write cycle timing diagram (ce = controlled) * 1 write cycle 4: ce 2 = v ih : 8-bit bus organization note: *1 a0, a18, a19 and a20 have to be fixed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. program command latch address & data pro- gram- ming program verify command program verify t wc t wc t wc t ah t as t rc setup program command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh1 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address (a0, a18, a19, a20) 12 v v ih v il : undefined address (a1 to a17) d0 to d7
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 26 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) data in = 40h data in data in = c0h main memory write cycle timing diagram (ce = controlled) * 1 write cycle 5: ce 1 = v ih : 8-bit bus organization program command latch address & data pro- gra- ming program verify command program verify t wc t wc t wc t ah t as t rc setup program command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh1 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address *2 (a0, a18, a19, a20) 12 v v ih v il notes: *1 a0, a18, a19 and a20 have to be fixed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . : undefined address (a1 to a17) d8 to d15
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 27 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) data in = 4040h data in data in = c0c0h main memory write cycle timing diagram (ce = controlled) * 1 write cycle 6: ce 1 = ce 2: 16-bit bus organization program command latch address & data pro- gram- ming program verify command program verify t wc t wc t wc t ah t as t rc setup program command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh1 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1=ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a0, a18, a19, a20) 12 v v ih v il notes: *1 a0, a18, a19 and a20 have to be fixed during programming command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . : undefined address (a1 to a17) d0 to d15
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 28 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) data in = 20h data in = 20h data in = a0h main memory erase cycle timing diagram (we = controlled) * 1 erase cycle 1: ce 2 = v ih : 8-bit bus organization note: *1 a0, a18, a19 and a20 have to be fixed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. erase command erasing erase verify command erase verify t wc t wc t wc t ah t as t rc setup erase command t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh2 t whgl t wp t dh t dh t wp t wp t chz t oe t dh t ds t ds t ds t olz t oh t clz t ce t vpel valid data ce 1 oe we v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address (a0, a18, a19, a20) 12 v v ih v il high-z t ohz : undefined address (a1 to a17) d0 to d7
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 29 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) erase command erasing erase verify command erase verify setup erase command data in = 20h data in = 20h data in = a0h main memory erase cycle timing diagram (we = controlled) * 1 erase cycle 2: ce 1 = v ih : 8-bit bus organization notes: *1 a0, a18, a19 and a20 have to be fixed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . t wc t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh2 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a0, a18, a19, a20) 12 v v ih v il t wp : undefined address (a1 to a17) d8 to d15
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 30 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) erase command erasing erase verify command erase verify setup erase command data in = 2020h data in = 2020h data in = a0a0h main memory erase cycle timing diagram (we = controlled) * 1 erase cycle 3: ce 1 = ce 2: 16-bit bus organization notes: *1 a0, a18, a19 and a20 have to be fixed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . t wc t wc t wc t ah t as t rc t cs t ch t ch t cs t cs t ch t wph t ghwl t whwh2 t whgl t ohz t wp t dh t dh t wp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1=ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a0, a18, a19, a20) 12 v v ih v il t wp : undefined address (a1 to a17) d0 to d15
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 31 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) erase command erasing erase verify command erase verify setup erase command data in = 20h data in = 20h data in = a0h erase cycle 4: ce 2 = v ih : 8-bit bus organization t wc t wc t wc t ah t as t rc t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh2 t whgl t ohz t cp t dh t dh t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data ce 1 oe we v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address (a0, a18, a19, a20) 12 v v ih v il t cp note: *1 a0, a18, a19 and a20 have to be fixed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. : undefined address (a1 to a17) d0 to d7 main memory erase cycle timing diagram (ce = controlled) * 1
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 32 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) data in = 20h data in = 20h data in = a0h main memory erase cycle timing diagram (ce = controlled) * 1 erase cycle 5: ce 1 = v ih : 8-bit bus organization erase command erasing erase verify command erase verify t wc t wc t wc t ah t as t rc setup erase command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh2 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address *2 (a0, a18, a19, a20) 12 v v ih v il notes: *1 a0, a18, a19 and a20 have to be fixed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . : undefined address (a1 to a17) d8 to d15
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 33 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) data in = 2020h data in = 2020h data in = a0a0h main memory erase cycle timing diagram (ce = controlled) * 1 erase cycle 6: ce 1 = ce 2: 16-bit bus organization erase command erasing erase verify command erase verify t wc t wc t wc t ah t as t rc setup erase command t ws t wh t wh t ws t ws t wh t cph t ghwl t whwh2 t whgl t ohz t cp t dh t dh t cp t cp t chz t oe t dh t ds t ds t ds t olz t oh high-z t clz t ce t vpel valid data we oe ce 1=ce 2 v ih v il v ih v il v ih v il v ih v il v ih v il v ppl v pp address*2 (a0, a18, a19, a20) 12 v v ih v il notes: *1 a0, a18, a19 and a20 have to be fixed during erase command input because these addresses are chip decoding addresses. refer to the write/erase chip decoding information. *2 a0 = either v il or v ih . : undefined address (a1 to a17) d0 to d15
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 34 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) ce 1 attribute memory write cycle timing diagram (we = controlled, reg = v il ) * 1 address (a0 to a11) high-z t rcs v ih v il v ih v il : undefined t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d7 * 2 t rrbo t roes t rdh t rah t rre t roeh t rwr high-z i7 notes: *1 this timing diagram is for mb98a808a3, 809a3, 810a3, and 811a3. affo data is available on mb98a808a2, 809a2, 810a2, and 811a2 only. *2 data polling operation. . oe we d0 to d7 write cycle 1: ce 2 = v ih : 8-bit bus organization o7
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 35 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) we oe ce 1 = ce 2 attribute memory write cycle timing diagram (we = controlled, reg = v il ) * 1 high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d7 * 3 t rrbo t roes t rdh t rah t rre t roeh t rwr d0 to d7 * 2 high-z o7 notes: *1 this timing diagram is for mb98a808a3, 809a3, 810a3, and 811a3. affo data is available on mb98a808a2, 809a2, 810a2, and 811a2 only. *2 h-level or l-level is output from d8 to d15. *3 data polling operation. : undefined address (a0 to a11) write cycle 2: ce 1 = ce 2: 16-bit bus organization i7
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 36 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) we oe ce 1 attribute memory write cycle timing diagram (ce = controlled, reg = v il ) * 1 high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d7 * 2 t rrbo t roes t rdh t rah t rre t roeh t rwr high-z o7 notes: *1 this timing diagram is for mb98a808a3, 809a3, 810a3 and 811a3. affo data is available on mb98a808a2, 809a2, 810a2, and 811a2 only. *2 data polling operation. : undefined address (a0 to a11) d0 to d7 write cycle 3: ce 2 = v ih : 8-bit bus organization i7
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 37 ac characteristics (continued) (at recommended operating conditions unless otherwise noted.) oe ce 1 = ce 2 attribute memory write cycle timing diagram (ce = controlled, reg = v il ) * 1 high-z t rcs v ih v il v ih v il t rweh v ih v il v ih v il v oh v ol v ih v il t ras data valid t rch high-z t rwp t rds d7 * 3 t rrbo t roes t rdh t rah t rre t roeh t rwr high-z o7 notes: *1 this timing diagram is for mb98a808a3, 809a3, 810a3, and 811a3. affo data is available on mb98a808a2, 809a2, 810a2, and 811a2 only. *2 h-level or l-level is output from d8 to d15. *3 data polling operation. we : undefined d0 to d7 * 2 address (a0 to a11) write cycle 4: ce 1 = ce 2: 16-bit bus organization i7
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 38 write / erase information start v pph =12.0 v 0.6 v v cc = 5.0 v 0.25 v v pp1 = v pp2 = v pph yes fig. 4 write flowchart for 8-bit organization v ppl 6.5 v write setup command = 40h s: start address g: address n: stop address x: counter value g s yes no x 1 write data to card time out (10 m s) write verify command = c0h time out (6 m s) read data from card verify data x = 25? no x = x + 1 read command = 00h g = n? v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl end yes read command = 00h v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl error no g = g + 1
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 39 write / erase information (continued) start v pph =12.0 v 0.6 v v cc = 5.0 v 0.25 v v pp1 = v pp2 = v pph yes fig. 5 write flowchart for 16-bit organization v ppl 6.5 v write setup command = 4040h (when y = 0) = ff40h (when y = 1) = 40ffh (when y = 2) s: start address g: address n: stop address xo: odd byte counter value xe: even byte counter value y: programming flag g s yes no xe 1, xo 1, y 0 time out (10 m s) write verify command = c0c0h (when y = 0) = 00c0h (when y = 1) = c000h (when y = 2) time out (6 m s) verify data xe = 25? or xo = 25? read command = 0000h g = n? v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl end yes v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl error no g = g + 2 write data to card = wdwdh (when y = 0) = ffwdh (when y = 1) = wdffh (when y = 2) read data from card read command = 0000h lower byte? yes y= 2 xo = xo + 1 no upper byte? yes y = 1 xe = xe + 1 no y = 0, xe = xe + 1 xo = xo + 1 no
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 40 write / erase information (continued) lower byte erase address set up (a0 = 0) start v pph =12.0 v 0.6 v v cc = 5.0 v 0.25 v v pp1 = v pp2 = v pph yes fig. 6 erase flowchart for 8-bit organization v ppl 6.5 v erase setup command = 20h g: address n1: lower byte end address n2: upper byte end address x: counter value no x 1 erase command = 20h time out (10 ms) erase verify command = a0h time out (6 m s) read data from card data = ffh? x = 3000? no x = x + 1 g = n1? no g = g + 2 yes 1 2 (continued on page 41.) (continued on page 41.) all data = 00h? write 00h to card yes
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 41 write / erase information (continued) v pph =12.0 v 0.6 v yes fig. 7 erase flowchart for 8-bit organization (continued) v ppl 6.5 v erase setup command = 20h g: address n1: lower byte end address n2: upper byte end address x: counter value no x 1 erase command = 20h time out (10 ms) erase verify command = a0h time out (6 m s) read data from card data = ffh? x = 3000? yes x = x + 1 read command = 00h g = n2? v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl end no read command = 00h v cc = 5.0 v 0.25 v v pp1 = v pp2 = v ppl error no g = g + 2 1 2 (continued from page 40.) (continued from page 40.) upper byte erase address setup (a0 = 1) yes
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 42 write / erase information (continued) write 0000h to card start v cc =5 v 0.25 v v pph =12.0 v 0.6 v v ppl 6.5 v yes fig. 8 erase flowchart for 16-bit organization erase setup command = 2020h (when y = 0) = ff20h (when y = 1) = 20ffh (when y = 2) g: address n: stop address xo: odd byte counter value xe: even byte counter value y: erasing flag no xe 1, xo 1, y 0 time out (10 m s) erase verify command = a0a0h (when y = 0) = 00a0h (when y = 1) = a000h (when y = 2) time out (6 m s) data = ffffh? xe = 3000? or xo = 3000? read command = 0000h g = n? end yes error no g = g + 2 erase command = 2020h (when y = 0) = ff20h (when y = 1) = 20ffh (when y = 2) read data from card read command = 0000h lower byte? yes y = 2 xo = xo + 1 no upper byte? yes y = 1 xe = xe + 1 no v cc , v pp1 = v pp2 = v ppl v cc , v pp1 = v pp2 = v ppl y = 0, xe = xe + 1 xo = xo + 1 no v cc , v pp1 = v pp2 = v pph data = 0000h? erase address setup yes
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 43 1. special monitoring pins wp switch wp (output) protect h non protect l (a) (b) v cc cd 1 cd 2 system side card side fig. 10 fig. 9 unique features for flash memory card 1.1 cd 1, cd 2: card detection pins these pins detect the insertion of the card into the system. (see fig. 9.) when the memory card has been correctly inserted, cd 1 and cd 2 are detected by the system. cd 1, cd 2 are tied to ground on the card side as shown in fig. 9. 1.2 wp: write protect pins this pin monitors the position of the write protect switch. as shown in fig. 10, the flash memory card has a write protect switch at the top of the card. to write to the card, the switch must be turned to the anon protecto position and the we pin low. l-level is output on the wp pin. to prevent writing to the card, the switch must be turned to the aprotecto position. h-level is output on the wp pin. non protect flash memory card write protect switch v cc protect device handling precautions this device in composed of fine electronic parts, so take care in handling or keeping it as below. ? the card is made fine, so do not keep it in the high temperature nor high humiditly, place like in the direct sun-shine nor near the heater. ? the card should not be bent, scratched, dropped nor be shocked violently. ? this device should never be taken a part. it could destroy the card or your personal computer hardware. ? to help you handle this device safely, request us the device specifications when purchasing this device.
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 44 package dimensions 68-pin memory card (case no.: crd-68p-m17) note: dimensions comform with pc card standard 95
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mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 46 memo
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 47 memo
mb98a808ax-20 MB98A809AX-20 mb98a810ax-20 mb98a811ax-20 48 for further information please contact: japan north and south america europe asia pacific fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 951341804, u.s.a. tel: (408) 9229000 fax: (408) 4329044/9045 i 9702 ? fujitsu limited printed in japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 411, kamikodanaka nakaharaku, kawasakishi kanagawa 21188, japan tel: (044) 7543763 fax: (044) 7543329 fujitsu microelectronics asia pte. limited #0508, 151 lorong chuan new tech park singapore 556741 tel: (65) 2810770 fax: (65) 2810220 fujitsu mikroelektronik gmbh am siebenstein 610 63303 dreieichbuchschlag germany tel: (06103) 6900 fax: (06103) 690122 all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. complete information sufficient for construction purposes is not necessarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu assumes no responsibil- ity for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information described in this document are not intended for use with equipments which require extremely high reliability such as aero- space equipments, undersea repeaters, nuclear control systems or medi- cal equipments for life support.

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