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EM73491 4-bit micro-controller for telecom product 1 * this specification are subject to be changed without notice. 6.11.1998 general description EM73491 is an advanced single chip cmos 4-bit micro-controller. it contains 4k-byte rom, 244-nibble ram, 4-bit alu, 13-level subroutine nesting, 22-stage time base, two independent 12-bit timer/counter and one data pointer (dp) for the kernel function, and the EM73491 also contains 5 interrupt sources, 8 i/o ports (including 1 output port , 2 input ports and 5 bidirection ports) and it can also support user the internal reset. for the application in the telecom product, EM73491 also supports user the beep tone and dtmf function. except low-power consumption and high speed, EM73491 also has sleep and hold mode operation for power saving function. EM73491 is suitable for appliaction in telecom products and family appliances. features ? operation voltage : 2.2v to 5.5v (clock frequency : 480 khz to 4 mhz) ? clock source : single clock system available for resonator or crystal and external clock source by mask option. ? frequency selection : 480k/800k/960k/3.58m/3.84m/4m hz decided by mask option. ? instruction set : 110 powerful instructions. ? instruction cycle time : up to 2 m s for 4 mhz. ? rom capacity : 4k x 8 bits. ? ram capacity : 244 x 4 bits. ? input port : 2 ports (5-bit) port 0 : pull-up or pull-down resistor available by mask option for input port function. pull-up resistor available by mask option for used as sleep releasing port. port 14 : pull-up resistor available by mask option. ? output port : 1 port (1-bit) (push-up or open-drain type decided by mask option). ? bidirection i/o port : 5 ports (16-bit) (push-pull or open-drain type decided by mask option). ? 12 bits timer/counter : two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. ? built-in time base counter : 22 stages. ? subroutine nesting : up to 13 levels. ? interrupt : external . . . . . 2 input interrupt sources. internal . . . . . . 2 timer overflow interrupts. 1 time base interrupt. ? beep tone function. ? dtmf tone function. ? power saving function : sleep function, cpu hold internal state and stop oscillating. hold function, cpu hold internal state and oscillator still working. ? package type : EM73491bp dip 22 pins. EM73491dp dip 28 pins. patent number : 75201, 62630, 61007 (r.o.c) patent pending : 83216083 (r.o.c)
2 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 pin configurations function block diagram p8.2/int0 p14.0/wakeupe reset xout xin test p0.3/wakeup3 p0.2/wakeup2 p0.1/wakeup1 p0.0/wakeup0 tone EM73491bp 22 pin dip 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 vdd p5.0 p5.1 p5.2 p6.0 p6.2 p7.0 p7.2 p3.0 vss p20.0/beep 28 pin dip EM73491dp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 p6.3 p7.0 p7.1 p7.2 p7.3 p3.0 vss p20.0/beep tone p0.0/wakeup0 p0.1/wakeup1 p0.2/wakeup2 p0.3/wakeup3 test p6.2 p6.1 p6.0 p5.3 p5.2 p5.1 p5.0 vdd p8.2/int0 p8.0/int1 p14.0/wakeupe reset xout xin reset control clock generator timing generator sleep mode control data bus time base (2 channels) 12 bits timer counter rom pc acc alu stack pointer stack ram hr lr i/o control system control interrupt control instruction register instruction decoder flag z c s g reset xin xout data pointer sio p7 p6 p5 tone p20.0/beep dtmf general beep general p14.0/wakeupe p0.0 /wakeup0 p0.1/wakeup1 p0.2/wakeup2 p0.3/wakeup3 p3.0 p5.0-p5.3 p6.0-p6.3 p7.0-p7.3 p8.0/int1 p8.2/int0 p8.3/trga
EM73491 4-bit micro-controller for telecom product 3 * this specification are subject to be changed without notice. 6.11.1998 pin descriptions symbol pin-type function v dd power supply (+) v ss power supply (-) reset reset-a external reset input pin or internal reset function by mask option mask option : none pull-up xin osc-a crystal or external clock source connecting pin xout osc-a crystal connecting pin p0.(0..3)/wakeup0..3 input-d 4 bits input port with sleep/hold releasing and r-option function mask option : r-option enable, wakeup disable, none r-option enable, wakeup disable, pull-up r-option disable, wakeup enable, none r-option disable, wakeup enable, pull-up r-option disable, wakeup disable, none r-option disable, wakeup disable, pull-up r-option disable, wakeup disable, pull-down p3.0 i/o-g 1-bit bidirection i/o pin mask option : nmos open-drain pmos open-drain push-pull p5(0..3),p6(0..3) i/o-f 4 bits bidirection i/o ports with r-option function p7(0..3) mask option : r-option enable, push-pull r-option disable, open-drain r-option disable, push-pull p8.0/int1 i/o-c 2 bit bidirection i/o port with external interrupt sources input p8.2/int0 mask option : open-drain push-pull p8.3/trga i/o-c 1 bit bidirection i/o pin with timer/counter a external input mask option : open-drain push-pull p14.0/wakeupe input-f 1 bit input pin with sleep/hold releasing function mask option : none pull-pull p20.0/beep output-b 1 bit output pin is shared with beep output pin mask option : open-drain push-pull tone dtmf output pin test test pin must be connected to v ss
4 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 function descriptions program rom ( 4k x 8 bits ) 4 k x 8 bits program rom contains users program and some fixed data . the basic structure of program rom can be divided into 5 parts. 1. address 000h: reset start address. 2. address 002h - 00ch: 5 kinds of interrupt service rountine entry addresses . 3. address 00eh-086h : scall subroutine entry address, only available at 00eh,016h,01eh,026h, 02eh, 036h, 03eh, 046h, 04eh, 056h, 05eh, 066h, 06eh, 076h ,07eh, 086h . 4. address 000h - 7ffh : lcall subroutine entry address 5. address fe0h - fffh : the data region for 5-to-8 bits data conversion table . 6. address 000h - fffh : except used as above function, the other region can be used as users program region. address 4096 x 8 bits 000h reset start address 002h int0; external interrupt service routine entry address 004h 006h trga; timer/countera interrupt service routine entry address 008h trgb; timer/counter b interrupt service routine entry address 00ah tbi; time base interrupt service routine entry address 00ch int1; external interrupt service routine entry address 00eh 086h fe0h fffh users program and fixed data are stored in the program rom. users program is according the pc value to send next executed instruction code . fixed data can be read out by two ways. (1) table-look-up instruction: table-look-up instruction is depended on the data pointer ( dp ) to indicate to rom address, then to get the rom code data . ldax acc ? rom[dp] l ldaxi acc ? rom[dp] h ,dp+1 dp is a 12-bit data register which can store the program rom address to be the pointer for the rom code data . first, user load rom address into dp by instruction "ldadpl, ldadpm, ldadph". then user can get the lower nibble of rom code data by instruction "ldax" and higher nibble by instruction "ldaxi". program example: read out the rom code of address 777h by table-look-up instruction. ldia #07h; stadpl ; [dp] l ? 07h stadpm ; [dp] m ? 07h stadph ; [dp] h ? 07h, load dp=777h : . . . . . . data conversion table for "out12" instruction scall, subroutine call entry address
EM73491 4-bit micro-controller for telecom product 5 * this specification are subject to be changed without notice. 6.11.1998 ldl #00h; ldh #03h; ldax ; acc ? 6h stami ; ram[30] ? 6h ldaxi ; acc ? 5h stam ; ram[31] ? 5h ; org 777h data 56h; : (2) 5-to-8 bits data conversion instruction: out12 : if cf=1 port1= rom[ff0h+ram[hl]] l ; port2= rom [ff0h+ram[hl]] h if cf=0 port1= rom[fe0h+ram[hl]] l ; port2= rom[fe0h+ram[hl]] h 5-to-8 bits data conversion instruction can read fixed data from data conversion table (fe0-fff) out to port1 and port2 synchronously, the 5-bit data is composed by cf and ram data which specified by hl, when cf=1, the 8-bit data is located in address of ff0h+ ram[hl] of rom, in the other way, when cf=0, the 8-bit data is located in address fe0h + ram[hl] of rom. program example : to output port1, port2 data by 5-to-8 bits data conversion instruction. ldl #00h; ldh #03h; ldia #00h; stam ; ram[30] ? 00h ttcfs; cf ? 1 out12; : : org ff0h data 40h; 7ch; 12h; 18h; 2ch; 09h; 01h; 5ch; 00h; 08h;
6 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 data ram ( 244-nibble ) there is total 244 - nibble data ram from address 00 to f3h data ram includes 3 parts: zero page region, stacks and data area. zero- page: from 00h to 0fh is the location of zero-page . it is used as the pointer in zero -page addressing mode for the instruction of "std #k,y; add #k,y; clr y,b; cmp y,b". program example: to wirte immediate data "07h" to address "03h" of ram and to clear bit 2 of ram. std #07h, 03h ; ram[03] ? 07h clr 0eh,2 ; ram[0eh] 2 ? 0 stack: there are 13 - level ( maximum ) stack for user using for subroutine ( including interrupt and call). user can assign any level be the starting stack by giving the level number to stack pointer( sp) . when user using any instruction of call or subroutine, before entry the subroutine, the previous pc address will be saved into stack until return from those subroutines ,the pc value will be restored by the data saved in stack. data area: except the special area used by user, the whole ram can be used as data area for storing and loading general data. addressing mode (1) indirect addressing mode: indirect addressing mode indicates the ram address by specified hl register . for example: ldam ; acc ? ram[hl] stam ; ram[hl] ? acc (2) direct addressing mode: direct addressing mode indicates the ram address by immediate data . increment address b0h - bfh c0h - cfh d0h - dfh e0h - efh level 0 level 4 level 8 level 12 level 1 level 5 level 9 level 2 level 6 level 10 level 3 level 7 level 11 increment zero-page 00h - 0fh 10h - 1fh f0h - f3h : : :
EM73491 4-bit micro-controller for telecom product 7 * this specification are subject to be changed without notice. 6.11.1998 program counter (4k rom) program counter ( pc ) is composed by a 12-bit counter, which indicates the next executed address for the instruction of program rom. for a 4k - byte size rom, pc can indicate address form 000h - fffh, for branch and call instrcutions, pc is changed by instruction indicating. (1) branch instruction: sbr a object code: 00aa aaaa condition: sf=1; pc ? pc 11-6.a ( branch condition satisified ) pc hold original pc value+1 aaaaaa sf=0; pc ? pc +1( branch condition not satisified) pc original pc value + 1 lbr a object code: 1100 aaaa aaaa aaaa condition: sf=1; pc ? a ( branch condition satisified) pcaaaaaaaaaaaa sf=0 ; pc ? pc + 2 ( branch condition not satisified ) pc original pc value + 2 (2) subroutine instruction: scall a object code: 1110 nnnn condition : pc ? a ; a=8n+6 ; n=1..15 ; a=86h, n=0 pc0000 aaaaaaa a lcall a object code: 0100 0 aaa aaaa aaaa condition: pc ? a for example: lda x ; acc ? ram[x] sta x ; ram[x] ? acc (3) zero-page addressing mode for zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. for example: std #k,y ; ram[y] ? #k add #k,y; ram[y] ? ram[y] + #k
8 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 pc0aaaaaaaaaaa ret object code: 0100 1111 condition: pc ? stack[sp]; sp + 1 pc the return address stored in stack rt i object code: 0100 1101 condition : flag. pc ? stack[sp]; ei ? 1; sp + 1 pc the return address stored in stack (3) interrupt acceptance operation: when an interrupt is accepted, the original pc is pushed into stack and interrupt vector will be loaded into pc,the interrupt vectors are as following: int0 (external interrupt from p8.2) pc000000000010 trga (timer a overflow interrupt) pc000000000110 trgb (time b overflow interrupt) pc000000001000 tbi (time base interrupt) pc000000001010 int1 (external interrupt from p8.0) pc000000001100 (4) reset operation: pc000000000000 (5) other operations: for 1-byte instruction execution: pc + 1 for 2-byte instruction execution: pc + 2 accumulator
EM73491 4-bit micro-controller for telecom product 9 * this specification are subject to be changed without notice. 6.11.1998 accumulator is a 4-bit data register for temporary data . for the arithematic, logic and comparative opertion .., acc plays a role which holds the source data and result . flags there are four kinds of flag, cf ( carry flag ), zf ( zero flag ), sf ( status flag ) and gf ( general flag ), these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation . all flags will be put into stack when an interrupt subroutine is served, and the flags will be restored after rti instruction executed . (1) carry flag ( cf ) the carry flag is affected by following operation: a. addition : cf as a carry out indicator, when the addition operation has a carry-out, cf will be "1", in another word, if the operation has no carry-out, cf will be "0". b. subtraction : cf as a borrow-in indicator, when the subtraction operation must has a borrow, in the cf will be "0", in another word, if no borrow-in, cf will be "1". c. comparision: cf is as a borrow-in indicator for comparision operation as the same as subtraction operation. d. rotation: cf shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. cf test instruction : for tfcfc instruction, the content of cf sends into sf then clear itself "0". for ttsfc instruction, the content of cf sends into sf then set itself "1". (2) zero flag ( zf ) zf is affected by the result of alu, if the alu operation generate a "0" result, the zf will be "1", otherwise, the zf will be "0". (3) status flag ( sf ) the sf is affected by instruction operation and system status . a. sf is initiated to "1" for reset condition . b. branch instruction is decided by sf, when sf=1, branch condition will be satisified, otherwise, branch condition will not be satisified by sf = 0 . (4) general flag ( gf ) gf is a one bit general purpose register which can be set, clear, test by instruction sgf, cgf and tgs. program example: check following arithematic operation for cf, zf, sf
10 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 cf zf sf ldia #00h; - 1 1 ldia #03h; - 0 1 adda #05h; - 0 1 adda #0dh; - 0 0 adda #0eh; - 0 0 alu the arithematic operation of 4 - bit data is performed in alu unit . there are 2 flags can be affected by the result of alu operation, zf and sf . the operation of alu can be affected by cf only . alu structure alu supported user arithematic operation function, including : addition, subtraction and rotaion. alu function (1) addition: for instruction addam, adcam, addm #k, add #k,y .... alu supports addition function. the addition operation can affect cf and zf. for addition operation, if the result is "0", zf will be "1", otherwise, not equal "0", zf will be "0", when the addition operation has a carry-out. cf will be "1", otherwise, cf will be "0". example: operation carry zero 3+4=7 0 0 7+f=6 1 0 0+0=0 0 1 8+8=0 1 1 (2) subtraction: for instruction subm #k, suba #k, sbcam, decm... alu supports user subtraction function . the subtraction operation can affect cf and zf, for subtraction operation, if the result is negative, cf will be "0", it means a borrow out, otherwise, if the result is positive, cf will be "1". for zf, if the result of subtraction operation is "0", the zf will be "1", otherwise, zf will be "1". example: operation carry zero 8-4=4 1 0 7-f= -8(1000) 0 0 9-9=0 1 1 zf cf sf gf alu data bus
EM73491 4-bit micro-controller for telecom product 11 * this specification are subject to be changed without notice. 6.11.1998 (3) rotation: there are two kinds of rotation operation, one is rotation left, the other is rotation right. rlca instruction rotates acc value to left, shift the cf value into the lsb bit of acc and the shift out data will be hold in cf. rrca instruction operation rotates acc value to right, shift the cf value into the msb bit of acc and the shift out data will be hold in cf. program example: to rotate acc right and shift a "1" into the msb bit of acc . ttcfs; cf ? 1 rrca; rotate acc right and shift cf=1 into msb. hl register hl register are two 4-bit registers, they are used as a pair of pointer for the address of ram memory and also 2 independent temporary 4-bit data registers. for some instruction, l register can be a pointer to indicate the pin number ( port5 - port7 ) . hl register structure hl register function (1) for instruction : ldl #k, ldh #k, tha, thl, incl, decl, exal, exah, hl register used as a temporary register . program example: load immediate data "5h" into l register, "dh" into h register. ldl #05h; ldh #0dh; (2) for instruction ldam, stam, stami .., hl register used as a pointer for the address of ram memory. program example: store immediate data #ah into ram of address 35h. acc cf msb lsb 3 2 1 0 h register 3 2 1 0 l register acc cf msb lsb
12 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 ldl #5h; ldh #3h; stdmi #0ah; ram[35] ? ah (3) for instruction : selp, clpl, tfpl, l regieter be a pointer to indicate the bit of i/o port. when lr = 4 - 7, indicate p5.0 - p5.3 lr = 8 - b, indicate p6.0 - p6.3 lr = c - f, indicate p7.0 - p7.3 program example: to set bit 2 of port6 to "1" ldl #0ah; sepl ; p6.2 ? 1 stack pointer (sp) stack pointer is a 4-bit register which stores the present stack level number. before using stack, user must set the sp value first, cpu will not initiate the sp value after reset condition . when a new subroutine is accepted, the sp will be decreased one automatically, in another word, if returning from a subroutine, the sp will be increased one . the data transfer between acc and sp is by instruction of "ldasp" and "stasp". data pointer (dp) data pointer is a 12-bit register which stores the address of rom can indicate the rom code data specified by user (refer to data rom). clock and timing generator the clock generator is supported by a single clock system, the clock source comes from crystal (resonator),the working frequency range is 480 k hz to 4 mhz depending on the working voltage. clock and timing generator structure the clock generator connects outside compoments ( crystal or resonator by xin and xout pin for crystal osc type) the clock generator generates a basic system clock "fc". when cpu sleeping, the clock generator will be stoped until the sleep condition released. the system clock control generates 4 basic phase signals ( s1, s2, s3, s4 ) and system clock . sleep xin xout clock generator system clock control fc system clock s1 s2 s3 s4
EM73491 4-bit micro-controller for telecom product 13 * this specification are subject to be changed without notice. 6.11.1998 clock and timing generator function the frequency of fc is the oscillation frequency for xin, xout by crystal ( resonator). when cpu sleeps, the xout pin will be in "high" state . the instruction cycle equal 8 basic clock fc. 1 instructure cycle = 8 / fc timing generator and time base the timing generator produces the system clock from basic clock pulse which can be normal mode or slow mode clock. 1 instruction cycle = 8 basic clock pulses there are 22 stages time base . when working in the single clock mode, the timebase clock source is come from fc. time base provides basic frequency for following function: 1. tbi (time base interrupt) . 2. timer/counter, internal clock source. 3. warm-up time for sleep - mode releasing. time base interrupt (tbi ) the time base can be used to generate a fixed frequency interrupt . there are 8 kinds of frequencies can be selected by setting "p25" single clock mode p25 3 2 1 0 ( initial value 0000 ) 0 0 x x: interrupt disable 0 1 0 0: interrupt frequency xin / 2 10 hz 0 1 0 1: interrupt frequency xin / 2 11 hz 0 1 1 0: interrupt frequency xin / 2 12 hz 0 1 1 1: interrupt frequency xin / 2 13 hz 1 1 0 0: interrupt frequency xin / 2 9 hz 1 1 0 1: interrupt frequency xin / 2 8 hz 1 1 1 0: interrupt frequency xin / 2 15 hz 1 1 1 1: interrupt frequency xin / 2 17 hz 1 0 x x: reserved xin/clk xout crystal connection xin/clk xout rc connection fc prescaler binary counter 123 4 5678910111213 22 21 20 19 18 17 16 15 14
14 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 timer / counter ( timera, timerb) timer/counters can support user three special functions: 1. even counter 2. timer. 3. pulse-width measurement. these three functions can be executed by 2 timer/counter independently. for timera, the counter data is saved in timer register tah, tam, tal, which user can set counter initial value and read the counter value by instruction "ldatah(m,l), statah(m,l)" and timer register is tbh, tbm, tbl and w/r instruction "ldatbh (m,l), statbh (m,l)". the basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, p28 and p29 are the command ports for timera and timer b, user can choose different operation mode and different internal clock rate by setting these two ports. when timer/counter overflow, it will generate a trga(b) interrupt request to interrupt control unit. timer/counter control p8.3/trga is the external timer input for timera, it is used in event counter and pulse-width measure ment mode. timer/counter command port: p28 is the command port for timer/countera and p29 is for the timer/ counterb. port 28 3 2 1 0 tmsa ipsa initial state: 0000 timer/counter mode selection tmsa (b) function description 0 0 stop 0 1 event counter mode 1 0 timer mode 1 1 pulse width measurement mode port 29 3 2 1 0 tmsb ipsb initial state: 0000 interrupt control trga request p8.3/ trga event counter control timer control pulse-width measurement control internal clock p28 12 bit counter tmsa ipsa data bus timer control internal clock p29 12 bit counter tmsb ipsb trgb request
EM73491 4-bit micro-controller for telecom product 15 * this specification are subject to be changed without notice. 6.11.1998 timer/counter function timer/countera can be programmable for timer, event counter and pulse width measurement. timer/counter b only can be programmable for timer. event counter mode for event counter mode, timer/counter increases one at any rising edge of p8.3/trga for timera. when timera counts overflow, it will give interrupt control an interrupt request trga. program example: enable timera with p28. ldia #0100b; outa p28; enable timera with event counter mode timer mode for timer mode ,timer/counter increase one at any rising edge of internal pulse . user can choose 4 kinds of internal pulse rate by setting ipsb for timerb (ipsa for timera). when timer/counter counts overflow, trgb (trga) will be generated to interrupt control unit. program example: to generate trga interrupt request after 60 ms with system clock xin=4mhz ldia #0100b; exae; enable mask 2 eicil 110111b; interrupt latch ? 0, enable ei ldia #06h; p8.3/trga timera value n n+1 n+2 n+3 n+4 n+5 n+6 internal pulse timerb (timera )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 internal pulse-rate selection ipsa(b) function description 0 0 xin/2 hz 0 1 xin/2 hz 1 0 xin/2 hz 1 1 xin/2 hz 10 14 18 22
16 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 ldia #01h; statam; ldia #0fh; statah; ldia #1000b; outa p28; enable timera with internal pulse rate: xin/2 10 hz note: the preset value of timer/counter register is calculated as following procedure. internal pulse rate: xin/2 10 ; xin = 4mhz the time of timer counter count one = 2 10 /xin = 1024/4000=0.256ms the number of internal pulse to get timer overflow = 60 ms/ 0.256ms = 234.375 = 0eah the preset value of timer/counter register = 1000h - 0eah = 0f16h pulse width measurement mode for the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as external timer/counter input (p8.3/trga ), interrupt request will be generated as soon as timer/counter count overflow. program example: enable timera by pulse width measurement mode . ldia #1100b; outa p28; enable timera with pulse width measurement mode. interrupt function there are 5 interrupt sources, 1 external interrupt sources, 4 internal interrupt sources . multiple interrupts are admitted according the priority . type interrupt source priority interrupt interrupt program rom latch enable condition entry address external external interrupt(int0) 1 il5 ei=1 002h internal reserved 2 il4 ei=1, mask3=1 004h internal timera overflow interrupt (trga) 3 il3 ei=1, mask2=1 006h internal timerb overflow interrupt (trgb) 4 il2 ei=1, mask1=1 008h internal time base interrupt(tbi) 5 il1 00ah external external interrupt(int1) 6 il0 ei=1,mask0=1 00ch statal; internal pulse timera value n n+1 n+2 n+3 n+4 n+5 p8.3/trga
EM73491 4-bit micro-controller for telecom product 17 * this specification are subject to be changed without notice. 6.11.1998 interrupt structure interrupt controller: il0-il5 : interrupt latch . hold all interrupt requests from all interrupt sources. ilr can not be set by program, but can be reset by program or system reset, so il only can decide which interrupt source can be accepted. mask0-mask3 : except int0 ,mask register can promit or inhibit all interrupt sources. ei : enable interrupt flip-flop can promit or inhibit all interrupt sources, when inter- rupt happened, ei is cleared to "0" automatically, after rti instruction happened, ei will be set to "1" again . priority checker: check interrupt priority when multiple interrupts happened. interrupt function the procedure of interrupt operation: 1. push pc and all flags to stack. 2. set interrupt entry address into pc. 3. set sf= 1. 4. clear ei to inhibit other interrupts happened. 5. clear the il for which interrupt source has already be accepted. 6. to excute interrupt subroutine from the interrupt entry address. 7. cpu accept rti, restore pc and flags from stack . set ei to accept other interrupt requests. program example: to enable interrupt of "int0, trga" ldia #1100b; exae; set mask register "1100b" eicil 111111b ; enable interrupt f.f. reset by system reset and program instruction mask0 mask1 mask1 mask2 mask3 il0 int1 r0 il1 tbi r1 il2 r2 il3 trga r3 il4 r4 il5 int0 r5 priority checker ei entry address generator interrupt request interrupt entry address reset by system reset and program instruction set by program instruction trgb
18 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 power saving function ( sleep / hold functlon ) during sleep and hold condition, cpu holds the systems internal status with a low power consumption, for the sleep mode, the system clock will be stoped in the sleep condition and system need a warm up time for the stability of system clock running after wakeup . in the other way, for the hold mode, the system clock does not stop at all and it does not need a warm-up time any way. the sleep and hold mode is controlled by port 16 and released by p0(0..3)/wakeup0..3 or p14.0/ wakeupe. sleep and hold condition: 1. osc stop ( sleep only ) and cpu internal status held . 2. internal time base clear to "0". 3. cpu internal memory ,flags, register, i/o held original states. 4. program counter hold the executed address after sleep release. release condition: 1. osc start to oscillating.(sleep only). 2. warm-up time passing ( sleep only ). 3. according pc to execute the following program. there are two kinds of sleep/hold release mode . 1. edge release mode: release sleep/hold condition by the falling edge of any one of p0(0..3)/wakeup0..3 or by the rising edge of p14.0/wakeupe. 2. level release mode: release sleep/hold condition by the low level of any one of p0(0..3)/wakeup0..3 or by the high level of p14.0/wakeupe. the p14.0 responses the wakeup status and it's function as following : p16 3 2 1 0 initial value :0000 swwt set wake-up warm-up time 2 /xin 2 /xin 2 /xin hold mode se enable sleep/hold 0 reserved 1 enable sleep / hold rnode 0 1 wake-up in edge release mode wake-up in level release mode 0 0 0 1 1 0 1 1 18 14 16 wm se swwt wm set wake-up release mode
EM73491 4-bit micro-controller for telecom product 19 * this specification are subject to be changed without notice. 6.11.1998 wakeup status p14.0/wakeupe p0.0/wakeup0 p0.1/wakeup1 p0.2/wakeup2 p0.3/wakeup3 m0 m1 m2 m3 beep tone generator beep tone generator can generate a series of square wave in audiable frequency . the beep tone output pin is shared with p20.0 . when beep tone is disable, p20.0 is a general purpose output pin, in the other way, if beep tone enable, p20.0 is the beep tone output pin. wakeup status = (p0.0+m0)(p0.1+m1)(p0.2+m2)(p0.3+m3)(p14.0) the m0..3 are the mask options of p0(0..3)/wakeup0..3 for wakeup function. when m0..3 is equal to 0, the wakeup mask option is enabled. otherwise, the wakeup mask option is disabled. if user want to start the sleep/hold operation with the wakeup status being high, the sleep/hold function will be released immediately. so, to start the sleep/hold operation in level release mode, the wakeup status must be recognized to low by program. program example: detect the wakeup status to start the sleep/hold operation in the level release mode. wake: tfp p14.0 ;wait the wakeup status goes to low b wake ldia #1100b ;enable sleep operation in level release mode, warm-up time is 2 18 /xin outa p16 note : there are 4 independent mask option (m0..3) for wakeup function in EM73491. so,the wakeup function of p0(0..3)/wakeup0..3 and are enabled or disabled independently. freq. selector beep tone p20.0 data latch be bfs p19 3210 p20.0 output data p20.0 /beep beep tone source form time base
20 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 p19 is the command port for beep tone generator. the bit0,1 are called bfs, it is the selection bit for the beep tone output frequency . the bit 3 is called be, it controls the enable and the disable of beep tone. port 19 3 2 1 0 be beep tone enable be bfs 0 disable initial state : 0x00 1 enable according to the different clock frequency, xin, beep tone has following selection . bfs beep tone freq. selection bfs beep tone freq. selection 800 khz 960 khz 0 0 xin / 2 7 khz(3.75khz) 0 0 xin / 2 8 khz 3.125 khz 3.75 khz 0 1 xin / 2 8 khz ( 1.875 khz ) 0 1 xin / 2 9 khz 1.563 khz 1.875 khz 1 0 xin / 2 9 khz ( 937.5 hz ) 1 0 xin / 2 10 khz 781.3 hz 937.5 hz 1 1 xin / 2 10 khz ( 486.75 hz) 1 1 xin / 2 11 khz 390.6 hz 468.8 hz xin = 480 khz xin = 800k/960k hz bfs beep tone freq. selection 3.84 mhz 3.58 mhz 4 mhz 0 0 xin / 2 10 khz 3.75 khz 3.496 khz 3.906 khz 0 1 xin /2 11 khz 1.875 khz 1.748 khz 1.953 khz 1 0 xin /2 12 khz 937.5 khz 874 hz 976.5 khz 1 1 xin /2 13 khz 468.8 khz 437 hz 488.2 khz xin = 3.58 m /3.84 m /4 m hz program example: to send 1.875khz beep tone with system clock 480 khz ldia #1111b outa p20 ; clear beep tone output ldia #1001b outa pl9 ; send beep tone : to send 874hz beep tone with system clock 3.58 mhz ldia #1111b outa p20 ; clear beep tone output ldia #1010b outa p19 ; send beep tone : to disable beep tone ldia #0000b; outa p19 ; disable beep tone : dtmf (dual tone multi frequency) tone built-in dtmf generator can generate dialing tone signals for the telephone of dialing tone type. there are two kinds of dtmf tone . one is the group of low frequency, the other is the group of high frequency, each group has 4 kinds of frequency, user can choose single tone frequency or dual tone (combined both low and high frequencies) by setting p13,so user can get 16 kinds of dtmf frequency totally . dtmf generator contains a low frequency sine - wave generator for generating the dtmf signal which selected by row register and a high frequency sine - wave generator for generating the dtmf signal which selected by column register. adder is controlled by the bit3 of p13(ste) which controls the dual tone or single tone of dtmf signal.
EM73491 4-bit micro-controller for telecom product 21 * this specification are subject to be changed without notice. 6.11.1998 the bit3 of p13 is the control bit of enable dual or signal tone mode of the dtmf signal. port13 3 2 1 0 ste single tone enable ste initial state:0xxx 0 dual tone mode 1 single tone mode port 1 and port 2 is the register for low frequency ( row ) and high frequency ( column ) selection standard tone output frequency 480 khz row 800 khz deviation 3.58 mhz deviation 960 khz deviation 4 mhz deviation 3.84 mhz 0001 697 hz 699.3 hz +.3% 699.2 hz +.3% 697.7 hz +.1% 698.0 hz +.1% 0010 770 hz 796.2 hz - .1% 771.6 hz +.2% 769.2 hz - .1% 771.6 hz +.2% 0100 852 hz 854.7 hz +.3% 854.0 hz +.2% 851.1 hz - .1% 850.3 hz - .2% 1000 941 hz 943.4 hz +.2% 940.1 hz - .1% 937.5 hz - .4% 940.0 hz - .1% column 0001 1209 hz 1204.8 hz - .3% 1203.0 hz - .5% 1212.1 hz +.3% 1213.6 hz +.4% 0010 1336 hz 1333.3 hz - .2% 1331.8 hz - .3% 1333.3 hz - .2% 1329.8 hz - .5% 0100 1477 hz 1470.4 hz - .4% 1472.0 hz - .3% 1481.5 hz +.3% 1470.6 hz - .4% 1000 1633 hz 1639.3 hz +.4% 1645.2 hz +.7% 1621.6 hz - .7% 1623.4 hz - .6% dtmf tone is enable by setting port 1 and port 2 and bit3 of p13 . when user sets in single tone mode,either row or column register must be set by an effective value, otherwise, if any ineffective value or both register are load effective value, tone output will be disable. in the other way, for dual tone mode, both row and column register must be set by effective value, then the dtmf tone output will output in dual tone mode, otherwise, if either row or column register is set by ineffective value, the dtmf tone output will be disable and there is no tone output . program example: row register port 1 dtmf low-freq. selection sine wave generator ste adder dtmf tone output column register port 2 dtmf high-freq. selection sine wave generator system clock low frequency sine-wave generator high frequency sine-wave generator
22 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 (1) out dtmf tone signal for single tone of 697.7hz out #1000b,p13; set in single tone rnode out #0000b,p2 ; set an ineffective value for column register out #0001b,p1 ; enable dtmf signal of 697.7hz (2) out dtmf signal for dual tone by out12 instruction ( 5-to-8 bits data conversion ) ldl #00h; ldh #03h; stdmi #0lh; ram[30] ? 01h tfcfc, cf ? 0 out12, dtmf tone out key "1" org fe0h data 0001 0001b; corresponding to telephone key "1" data 0010 0001b; corresponding to telephone key "4" : : r option function for i/o pin r-option can provide more function for i/o pins. for example, it can be used in keyboard scan for telecom products. when the key is pressed, this i/o pin is a normal i/o pin. when the key in not pressed and the r-option function is enabled, this i/o pin can use as input pin to detect external status of this pad. r-option can provide the hi-z function for output driver and use the weak pmos to pull high. when the r- option control signal is high, the weak pmos turns off and the output data latch is in the normal mode. in the case, there are two mask options (push-pull, open-drain) for this i/o pin. when the r-option control signal is low, the weak pmos turns on and the output data latch is hi-z. in this case, the input data is low when this pad connects a 560k w external resistor to gnd, and the input data is high when this pad is open outside. control of r option r-option control signal can be decided by p20.3. when the cpu resets, the initial value is high. in the sleep mode, p20.3 must be set to high and the output pins with r-option function must be clear to low for power saving. p20 3210 initial value : 1 * * * 0 * * * : r-option enable 1 * * * : r-option disable pad weak pmos r-option control signal output data latch output data input data push-pull open-drain mask option r-option mask option 560k
EM73491 4-bit micro-controller for telecom product 23 * this specification are subject to be changed without notice. 6.11.1998 ex ; normal program ; i/o operation : : ; r-option operation for p5, p6 out #0fh, p5 ; let p5 pins pull high out #0fh, p6 ; let p6 pins pull high ldia #00h outa p20 ; enable r-option function ; wait 1 ms for deviation capacitor to charge up ina p5 ; read p5 pins' external status sta 05h ina p6 ; read p6 pins' external status sta 06h ldia #08h outa p20 ; disable r-option function : ; let pins low for sleep mode out #00h, p5 out #00h, p6 ; enable sleep mode : r option function for p0 (input only) there is some difference between i/o pin's and input pin's r-option function. when input pin's r-option mask option is selected, there are two pin's mask options (none, pull-up) can be slected. when the r-option control signal is low, the weak pmos will turn on and pin's pull-up resistor will turn off (this pin's mask option selects pull-up). in this case, the input data is low when this pad connects a 560k w external resistor to gnd, and the input data is high when this pad is open outside. when the r-option control signal is high, the weak pmos will trun off and pin's pull-down resistor will trun on. in sleep mode, user must disable r-option function for power saving. the r-option control signal is also decided by p20.3. ex ; normal program ; i/o operation : : ; r-option operation for p0 ldia #00h outa p20 ; enable r-option function ; wait 1 ms for deviation capacitor to charge up ina p0 ; read p5 pins' external status sta 00h ldia #08h outa p20 ; disable r-option function pad weak pmos r-option control signal input data none, pull-up, pull-down mask option r-option mask option 560k
24 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 : : ; enable sleep mode resetting function when cpu in normal working condition and reset pin holds in low level for three instruction cycles at least, then cpu begins to initialize the whole internal states, and when reset pin changes to high level, cpu begins to work in normal condition. the cpu internal state during reset condition is as following table : hardware condition in reset state initial value program counter 000h status flag 01h interrupt enable flip-flop ( ei ) 00h mask0 ,1, 2, 3 00h interrupt latch ( il ) 00h p1, 2, 13, 16, 25, 28, 29 00h p3, 5, 6, 7, 8, 20 0fh xin start oscillation the reset pin is a hysteresis input pin and it has a pull-up resistor available by mask option. the simplest reset circuit is connect reset pin with a capacitor to v ss and a diode to v dd . reset
EM73491 4-bit micro-controller for telecom product 25 * this specification are subject to be changed without notice. 6.11.1998 EM73491 i/o port description : port input function output function note 0 e input port , wakeup function 1 -- i dtmf row register 2 -- i dtmf column register 3 e p3.0, input pin e p3.0, output pin 4-- -- 5 e input port, r-option e output port, r-option 6 e input port, r-option e output port, r-option 7 e input port, r-option e output port, r-option 8 e input port, external interrupt input e output port no p8.1 9-- -- 10 -- -- 11 -- -- 12 -- -- 13 -- i dtmf control register 14 e p14.0, input pin, wakeup function -- 15 -- -- 16 i sleep mode control register 17 -- 18 -- 19 i beep control register 20 i p20.3 : r-option control register 21 -- 22 -- 23 -- 24 -- 25 i timebase control register 26 -- 27 -- 28 i timer/counter a control register 29 i timer/counter b control register 30 -- 31 --
26 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 dtmf electrical characteristics (v dd =5 0.5v, v ss =0v, t opr =25 c) sym. min. typ. max. unit conditions pehb 1 2 3 db pehb=20log(col/row) v tone 120 150 180 mvrms rl>10k w ,v dd =2.7v(row) dis - - 10 % distortion f tone - - 0.7 % stability, except error of osc absolute maximum ratings items sym. ratings conditions supply voltage v dd -0.5v to 6v input voltage v in -0.5v to v dd +0.5v output voltage v o -0.5v to v dd +0.5v power dissipation p d 300mw t opr =50 c operating temperature t opr 0 c to 50 c storage temperature t stg -55 c to 125 c recommanded operating conditions items sym. ratings condition supply voltage v dd 2.4v to 5.5v input voltage v ih 0.90xv dd to v dd v il 0v to 0.10xv dd operating frequency f c 480k to 4.19mhz xin,xout (crystal osc) dc electrical characteristics (v dd =5 0.5v, v ss =0v, t opr =25 c) parameters sym. min. typ. max. unit conditions supply current i dd - 4.5 5.5 ma v dd =5.5v,no load fc=4.19mhz(crystal osc) - 0.1 1 m av dd =5.5v, sleep mode without voltage detect - 2.5 - m av dd =2.5v, sleep mode with voltage detect hysteresis voltage v hys+ 0.50v dd - 0.75v dd v reset, p8, p9,p14, p0 v hys- 0.20v dd - 0.40v dd v input current i ih -- 1 m a reset , p0, v dd =5.5v,v ih =5.5/0v -- 1 m a open-drain,v dd =5.5v,v ih =5.5/0v i il - - -1 ma push-pull,v dd =5.5v ,v il =0.4v output voltage v oh 2.4 - - v push-pull,v dd =4.5v,i oh =-250 m a v ol - - 0.4 v v dd =4.5v,i ol =2ma leakage current i lo --1 m a open-drain, v dd =5.5v, v o =5.5v input resistor r in 30 90 150 k w p0 100 300 450 k w reset r-option threshold point v th - 0.45v dd -vv dd =3~5.5v r-option weak pmos r wp -2-m w v dd =3~5.5v resistance
EM73491 4-bit micro-controller for telecom product 27 * this specification are subject to be changed without notice. 6.11.1998 appliction circuit v ss v dd p0.3 p0.2 p0.1 p0.0 p6.3 p6.2 p6.1 p6.0 reset p20.0 EM73491 p5.0 tone p3.0 xout xin mute beep tip ring crystal osc xout xin resonator osc r out =5~10k
28 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 reset pin type type reset-a type reset-b oscillation pin type type osc-a input pin type type input-a type input-d reset mask option xin xout crystal osc. : mask option r-option control signal weak pmos p0/wakeup type input-a reset : mask option internal reset type reset-a mask option wakeup function mask option output pin type type input-f mask option p14 /wakeup
EM73491 4-bit micro-controller for telecom product 29 * this specification are subject to be changed without notice. 6.11.1998 i/o pin type type i/o type i/o-c output pin type path a : for set and clear bit of port instructions, data goes through path a from output data latch to cpu. path b : for input and test instructions, data from output pin go through path b to cpu and the output data latch will be set to high. output data latch mux type output input data output data special function control output input data output data path b path a output data latch output data path b path a type i/o output data latch sel special function control input input data mask option : mask option : mask option input data output data path b path a output data latch type i/o r-option control signal mask option weak pmos type i/o-f type i/o-g type output type output-b : mask option
30 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 instruction table (1) data transfer mnemonic object code ( binary ) operation description byte cycle flag cz s lda x 0110 1010 xxxx xxxx acc ? ram[x] 2 2 - z 1 ldam 0101 1010 acc ? ram[hl] 1 1 - z 1 ldax 0110 0101 acc ? rom[dp] l 12-z1 ldaxi 0110 0111 acc ? rom[dp] h ,dp++ 1 2 - z 1 ldh #k 1001 kkkk hr ? k11--1 ldhl x 0100 1110 xxxx xx00 lr ? ram[x],hr ? ram[x+1] 2 2 - - 1 ldia #k 1101 kkkk acc ? k11-z1 ldl #k 1000 kkkk lr ? k11--1 sta x 0110 1001 xxxx xxxx ram[x] ? acc 2 2 - - 1 stam 0101 1001 ram[hl] ? acc 1 1 - - 1 stamd 0111 1101 ram[hl] ? acc, lr-- 1 1 - z c stami 0111 1111 ram[hl] ? acc, lr++ 1 1 - z c' std #k,y 0100 1000 kkkk yyyy ram[y] ? k22--1 stdmi #k 1010 kkkk ram[hl] ? k, lr++ 1 1 - z c' tha 0111 0110 acc ? hr 1 1 - z 1 tla 0111 0100 acc ? lr 1 1 - z 1 (2) rotate mnemonic object code ( binary ) operation description byte cycle flag czs rlca 0101 0000 ? cf ? acc ? 11czc' rrca 0101 0001 ? cf ? acc ? 11czc' ( 3) arithmetic operation mnemonic object code ( binary ) operation description byte cycle flag c zs adcam 0111 0000 acc ? acc + ram[hl] + cf 1 1 c z c' add #k,y 0100 1001 kkkk yyyy ram[y] ? ram[y] +k 2 2 - z c' adda #k 0110 1110 0101 kkkk acc ? acc+k 2 2 - z c' addam 0111 0001 acc ? acc + ram[hl] 1 1 - z c' addh #k 0110 1110 1001 kkkk hr ? hr+k 2 2 - z c' addl #k 0110 1110 0001 kkkk lr ? lr+k 2 2 - z c' addm #k 0110 1110 1101 kkkk ram[hl] ? ram[hl] +k 2 2 - z c' deca 0101 1100 acc ? acc-1 1 1 - z c decl 0111 1100 lr ? lr-1 1 1 - z c decm 0101 1101 ram[hl] ? ram[hl]-1 1 1 - z c inca 0101 1110 acc ? acc + 1 1 1 - z c'
EM73491 4-bit micro-controller for telecom product 31 * this specification are subject to be changed without notice. 6.11.1998 incl 0111 1110 lr ? lr + 1 1 1 - z c' incm 0101 1111 ram[hl] ? ram[hl]+1 1 1 - z c' suba #k 0110 1110 0111 kkkk acc ? k-acc 2 2 - z c sbcam 0111 0010 acc ? ram[hl]- acc - cf' 1 1 c z c subm #k 0110 1110 1111 kkkk ram[hl] ? k - ram[hl] 2 2 - z c ( 4) logical operation mnemonic object code ( binary ) operation description byte cycle flag czs anda #k 0110 1110 0110 kkkk acc ? acc&k 2 2 - z z' andam 0111 1011 acc ? acc & ram[hl] 1 1 - z z' andm #k 0110 1110 1110 kkkk ram[hl] ? ram[hl]&k 2 2 - z z' ora #k 0110 1110 0100 kkkk acc ? acc k 2 2 - z z' oram 0111 1000 acc ? acc ram[hl] 1 1 - z z' orm #k 0110 1110 1100 kkkk ram[hl] ? ram[hl] k 2 2 - z z' xoram 0111 1001 acc ? acc^ram[hl] 1 1 - z z' (5) exchange mnemonic object code ( binary ) operation description byte cycle flag czs exa x 0110 1000 xxxx xxxx acc ? ram[x] 2 2 - z 1 exah 0110 0110 acc ? hr 1 2 - z 1 exal 0110 0100 acc ? lr 1 2 - z 1 exam 0101 1000 acc ? ram[hl] 1 1 - z 1 exhl x 0100 1100 xxxx xx00 lr ? ram[x], hr ? ram[x+1] 2 2 - - 1 (6) branch mnemonic object code ( binary ) operation description byte cycle flag czs sbr a 00aa aaaa if sf=1 then pc ? pc 11-6 .a 6-0 11--1 else null lbr a 1100 aaaa aaaa aaaa if sf= 1 then pc ? a else null 2 2 - - 1 (7) compare mnemonic object code ( binary ) operation description byte cycle flag czs cmp #k,y 0100 1011 kkkk yyyy k-ram[y] 2 2 c z z' cmpa x 0110 1011 xxxx xxxx ram[x]-acc 2 2 c z z' cmpam 0111 0011 ram[hl] - acc 1 1 c z z' cmph #k 0110 1110 1011 kkkk k - hr 2 2 - z c cmpia #k 1011 kkkk k - acc 1 1 c z z' cmpl #k 0110 1110 0011 kkkk k-lr 2 2 - z c - - - - - -
32 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 (8) bit manipulation mnemonic object code ( binary ) operation description byte cycle flag czs clm b 1111 00bb ram[hl] b ? 011--1 clp p,b 0110 1101 11bb pppp port[p] b ? 022--1 clpl 0110 0000 port[lr 3-2 +4] lr 1-0 ? 012--1 clr y,b 0110 1100 11bb yyyy ram[y] b ? 022--1 sem b 1111 01bb ram[hl] b ? 111--1 sep p,b 0110 1101 01bb pppp port[p] b ? 122--1 sepl 0110 0010 port[lr 3-2 +4] lr l-0 ? 112 --1 set y,b 0110 1100 01bb yyyy ram[y] b ? 122--1 tf y,b 0110 1100 00bb yyyy sf ? ram[y] b '22--* tfa b 1111 10bb sf ? acc b '11--* tfm b 1111 11bb sf ? ram[hl] b '11--* tfp p,b 0110 1101 00bb pppp sf ? port[p] b '22--* tfpl 0110 0001 sf ? port[lr 3-2 +4] lr 1-0 '12--* tt y,b 0110 1100 10bb yyyy sf ? ram[y] b 22--* ttp p,b 0110 1101 10bb pppp sf ? port[p] b 22--* (9) subroutine mnemonic object code ( binary ) operation description byte cycle flag czs lcall a 0100 0aaa aaaa aaaa stack[sp] ? pc, 2 2 - - - sp ? sp -1, pc ? a scall a 1110 nnnn stack[sp] ? pc, 1 2 - - - sp ? sp - 1, pc ? a, a = 8n + 6 (n 1 0),0086h (n = 0) ret 0100 1111 sp ? sp + 1, pc ? stack[sp] 1 2 - - - (10) input/output mnemonic object code ( binary ) operation description byte cycle flag czs ina p 0110 1111 0100 pppp acc ? port[p] 2 2 - z z' inm p 0110 1111 1100 pppp ram[hl] ? port[p] 2 2 - - z' out #k,p 0100 1010 kkkk pppp port[p] ? k22--1 outa p 0110 1111 000p pppp port[p] ? acc 2 2 - - 1 outm p 0110 1111 100p pppp port[p] ? ram[hl] 2 2 - - 1 out12 0111 0111 port[2].port[1] ? 12--1 rom[fe0h+cf.ram[hl]] (11) flag manipulation mnemonic object code ( binary ) operation description byte cycle flag czs cgf 0101 0111 gf ? 011--1 sgf 0101 0101 gf ? 111--1
EM73491 4-bit micro-controller for telecom product 33 * this specification are subject to be changed without notice. 6.11.1998 tfcfc 0101 0011 sf ? cf', cf ? 0110-* tgs 0101 0100 sf ? gf 1 1 - - * ttcfs 0101 0010 sf ? cf, cf ? 1111-* tzs 0101 1011 sf ? zf 1 1 - - * (12) interrupt control mnemonic object code ( binary ) operation description byte cycle flag czs cil r 0110 0011 11rr rrrr il ? il & r 2 2 - - 1 dicil r 0110 0011 10rr rrrr eif ? 0,il ? il&r 2 2 - - 1 eicil r 0110 0011 01rr rrrr eif ? 1,il ? il&r 2 2 - - 1 exae 0111 0101 mask ? acc 1 1 - - 1 rti 0100 1101 sp ? sp+1,flag.pc 1 2 * * * ? stack[sp],eif ?1 (13) cpu control mnemonic object code ( binary ) operation description byte cycle flag czs nop 0101 0110 no operation 1 1 - - - (14) timer/counter & data pointer & stack pointer control mnemonic object code ( binary ) operation description byte cycle flag czs ldadpl 0110 1010 1111 1100 acc ? [dp] l 22-z1 ldadpm 0110 1010 1111 1101 acc ? [dp] m 22-z1 ldadph 0110 1010 1111 1110 acc ? [dp] h 22-z1 ldasp 0110 1010 1111 1111 acc ? sp 2 2 - z 1 ldatal 0110 1010 1111 0100 acc ? [ta] l 22-z1 ldatam 0110 1010 1111 0101 acc ? [ta] m 22-z1 ldatah 0110 1010 1111 0110 acc ? [ta] h 22 -z1 ldatbl 0110 1010 1111 1000 acc ? [tb] l 22-z1 ldatbm 0110 1010 1111 1001 acc ? [tb] m 22-z1 ldatbh 0110 1010 1111 1010 acc ? [tb] h 22-z1 stadpl 0110 1001 1111 1100 [dp] l ? acc 2 2 - - 1 stadpm 0110 1001 1111 1101 [dp] m ? acc 2 2 - - 1 stadph 0110 1001 1111 1110 [dp] h ? acc 2 2 - - 1 stasp 0110 1001 1111 1111 sp ? acc 2 2 - - 1 statal 0110 1001 1111 0100 [ta] l ? acc 2 2 - - 1 statam 0110 1001 1111 0101 [ta] m ? acc 2 2 - - 1 statah 0110 1001 1111 0110 [ta] h ? acc 2 2 - - 1 statbl 0110 1001 1111 1000 [ tb] l ? acc 2 2 - - 1 statbm 0110 1001 1111 1001 [tb] m ? acc 2 2 - - 1 statbh 0110 1001 1111 1010 [tb] h ? acc 2 2 - - 1
34 EM73491 4-bit micro-controller for telecom product * this specification are subject to be changed without notice. 6.11.1998 **** symbol description symbol description symbol description hr h register lr l register pc program counter dp data pointer sp stack pointer stack[sp] stack specified by sp a cc accumulator flag all flags cf carry flag zf zero flag sf status flag gf general flag ei enable interrupt register il interrupt latch mask interrupt mask port[p] port ( address : p ) ta timer/counter a tb timer/counter b ram[hl] data memory (address : hl ) ram[x] data memory (address : x ) rom[dp] l low 4-bit of program memory rom[dp] h high 4-bit of program memory [dp] l low 4-bit of data pointer register [dp] m middle 4-bit of data pointer register [dp] h high 4-bit of data pointer register [ta] l ([tb] l ) low 4-bit of timer/counter a (timer/counter b) register [ta] m ([tb] m ) middle 4-bit of timer/counter a [ta] h ([tb] h ) high 4-bit of timer/counter a (timer/counter b) register (timer/counter b) register ? transfer ? exchange + addition - substraction & logic and logic or ^ logic xor ' inverse operation . concatenation #k 4-bit immediate data x 8-bit ram address y 4-bit zero-page address p 4-bit or 5-bit port address b bit address r 6-bit interrupt latch pc 11-6 bit 11 to 6 of program counter lr 1 -0 contents of bit assigned by bit a 5-0 bit 5 to 0 of destination address for 1 to 0 of lr branch instruction lr 3-2 bit 3 to 2 of lr - -

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