1 ? fn6473.0 5962-0623601qpc, 5962-0623602QPC 670mhz low noise amplifiers the 5962-0623601qpc and 5962-0623602QPC are fully dscc smd compliant parts and the smd data sheets are available on the dscc website (http://www.dscc.dla.mil/ programs/specfind/default.asp). the 5962-0623601qpc is electrically equivalent to the el5132 and the 5962-0623602QPC is electrically equivalent to the el5133, reference these data sheets for additional information. these amplifiers are ultra-low voltage noise, high speed, low power consumption vo ltage feedback amplifiers. both amplifiers are stable at gains as low as 10. not only do these devices find perfect application in high gain applications, they maintain their performance down to lower gain settings. these amplifiers are available in sbdip packages. all parts are specified for operation over the -55c to +125c temperature range. features ? 670mhz -3db bandwidth ? ultra low noise 0.9nv/ hz ? 1000v/s slew rate ? low supply current = 16ma ? single supplies from 5v to 12v ? dual supplies from 2.5v to 6v ? fast disable on the 5962-0623601qpc applications ? pre-amplifier ? receiver ? filter ? if and baseband amplifier ? adc drivers ? dac buffers ? instrumentation ? communications devices. pinouts 5962-0623601qpc (8 ld sbdip) top view 5962-0623602QPC (8 ld sbdip) top view ordering information part number part marking temp (c) package pkg. dwg. # 5962-0623601qpc 5962-0623 601qpc -55 to +125 8 ld sbdip d8.3 5962-0623602QPC 5962-0623 602qpc -55 to +125 8 ld sbdip d8.3 1 2 3 4 8 7 6 5 - + nc in- in+ vs- ce vs+ out nc 1 2 3 4 8 7 6 5 - + nc in- in+ vs- nc vs+ out nc data sheet march 28, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6473.0 march 28, 2007 absolute maxi mum ratings (t a = +25c) thermal information supply voltage from v s + to v s - . . . . . . . . . . . . . . . . . . . . . . . 13.2v slewrate between v s + and v s - . . . . . . . . . . . . . . . . . . . . . . . . 1v/s i in -, i in +, ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma continuous output current . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . .-55c to +125c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192mw caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a electrical specifications v s + = +5v, v s - = -5v, r l = 500 , r f = 10k , r g = 100 , t a = +25c, unless otherwise specified. parameter description conditions min typ max unit r in input resistance common mode 5 m c in input capacitance 2pf bw -3db bandwidth r f = 225 , a v = +10, r l = 1k 670 mhz bw 0.1db bandwidth r f = 225 , a v = +10, r l = 1k 90 mhz gbwp gain bandwidth product 3000 mhz pm phase margin r l = 1k , c l = 6pf 55 sr slew rate r l = 100 , v out = 2.5v 1000 v/s t r , t f rise time, fall time 0.1v step 2.0 ns os overshoot 0.1v step 10 % t s 0.01% settling time 6.6 ns dg differential gain r f = 1k , r load = 150 0.01 % dp differential phase r f = 1k , r load = 150 0.01 e n input noise voltage f = 10khz 0.9 nv/ hz i n input noise current f = 10khz 3.5 pa/ hz enable (5962-0623601qpc only) t en enable time 220 ns t dis disable time 175 ns pin descriptions part pin name function 5962-0623601qpc 5962-0623602QPC 1, 5 1, 5, 8 nc not connected 2 2 in- inverting input 3 3 in+ non-inverting input 4 4 vs- negative power supply 6 6 out amplifier output 7 7 vs+ positive power supply 8ce enable and disable input 5962-0623601qpc, 5962-0623602QPC
3 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6473.0 march 28, 2007 5962-0623601qpc, 5962-0623602QPC ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d8.3 mil-std-1835 cdip2-t8 (d-4, configuration c) 8 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.405 - 10.29 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n8 88 rev. 0 4/94
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