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w963a6bbn 512k word 16bit low power pseudo sram publ i c at i on rel e ase dat e : march 10, 2003 - 1 - revi si on a1 table of contents- 1. general d escription ......................................................................................................... ......... 3 2. features .................................................................................................................... ..................... 3 4. ball conf igurati on .......................................................................................................... .......... 4 5. ball des cription ............................................................................................................ .............. 4 6. block diagram ............................................................................................................... ............... 5 7. function t ruth t able ........................................................................................................ ........ 6 8. elecrical cha racteris tics ................................................................................................... .. 7 abs o lute maxi mum ra tings ....................................................................................................... ....... 7 recommended operat ing condi tions ............................................................................................... 7 capacit ance .................................................................................................................... .................. 8 dc charac te ris t ic s ............................................................................................................. ............... 8 ac charac te ris t ic s ............................................................................................................. ............... 9 read oper ation ................................................................................................................. ......................... 9 write oper a t i o n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......................... 11 pow e r dow n and pow e r dow n program pa ramete rs ............................................................................... 13 other t i ming parame ters ........................................................................................................ ................. 13 ac t e st conditi ons ............................................................................................................. ...................... 13 9. timing wavefor ms ............................................................................................................ ......... 14 read timing #1 ( oe control ac c e s s ) ............................................................................................ 14 read timing #2 ( ce1 control ac c e s s ) .......................................................................................... 15 read timing #3 (address access after oe control ac c e s s ) ........................................................ 16 read timing #4 (address access after ce1 control ac c e s s ) ....................................................... 17 write timing #1 ( ce1 contro l) ....................................................................................................... 18 write timing #2-1 ( we control, single wri te operat ion) .............................................................. 19 write timing #2 ( we control, continuous write oper ation) ......................................................... 20 read/write timing #1-1 ( ce1 contro l) ........................................................................................... 21 read/write timing #1-2 ( ce1 contro l) ........................................................................................... 22 read ( oe control) / write ( we control) ti ming #2- 1 .................................................................. 23
w963a6bbn - 2 - read ( oe control) / write ( we control) ti ming #2- 2 .................................................................. 24 power down pr ogram ti ming ...................................................................................................... ... 25 power down entry and exit timing ............................................................................................... .. 25 power-up ti ming #1 ............................................................................................................. ........... 25 power-up ti ming #2 ............................................................................................................. ........... 26 standby entry timing a fter read or write ...................................................................................... 2 6 10. package di mension .......................................................................................................... ........ 27 tfbga 48 balls (6 x 8 mm^2, pitc h 0.75 mm) ................................................................................ 27 11. ordering informat ion ....................................................................................................... .... 28 12. version history ............................................................................................................ ........... 29
w963a6bbn 1. general description w963a6bbn is a 8m bits cmos pseudo static random access memory (pseudo sram), organized as 512k words x 16 bits. using advanced si ngle transistor dram architecture and 0.175 2. features ? ? ? ? ? ? ? ? ? ? ? ? ? 3. product options p a r a m e t e r w 9 6 3 a 6 b b n 7 0 w 9 6 3 a 6 b b n 8 0 t rc 70 ns min. 80 ns min. i dds1 70 publ i c at i on rel e ase dat e : march 10, 2003 - 3 - revi si on a1
w963a6bbn 4. ball configuration a top view e b c d f 1 h 23 5 6 ( fbga48 , 6 x 8mm , pitch 0.75mm ) lb dq9 dq10 v ss v dd dq15 dq16 a18 oe ub dq11 dq12 dq13 dq14 nc a8 a0 a3 a5 a17 nc a14 a12 a9 a1 a4 a6 a7 a16 a15 a13 a10 a2 ce1 dq2 dq4 dq5 dq6 we a11 ce2 dq1 dq3 v dd v ss dq7 dq8 nc 4 g 5. ball description symbol d e s c r i p t i o n a0 ? a18 address input ce1 chip enable input 1, low: enable ce2 chip enable input 2, high: e nable, low: enter power down mode we write enable input oe output enable input lb lower byte write control ub upper byte write control i/o0 ? i/o15 data inputs/outputs v dd p o w e r s u p p l y v ss g r o u n d n c n o c o n n e c t i o n - 4 -
w963a6bbn 6. block diagram a ddres s la t c h & buff e r row decode r me m o r y cell a rra y 33, 554,4 32 b i t s in p u t / out p ut buff e r i n p u t d a ta la t c h & cont rol se nse / sw i t c h colum n / decod e r a ddress la t ch & buffer a0 to a18 dq1 to dq8 dq9 to dq1 6 ce2 ti mi n g c o nt rol ce1 we lb ub oe po w e r c o nt rol v dd v ss out p ut da t a c o nt rol pe publ i c at i on rel e ase dat e : march 10, 2003 - 5 - revi si on a1
w963a6bbn 7. function truth table mode n o t e c e 2 ce1 we oe lb ub a 0 - 1 8 d q 1 - 8 d q 9 - 1 6 i dd data retention standby (deselect) h x x x x x high- z high- z i dds yes output disable * 1 h h x x * 5 h i g h - z h i g h - z no read h h valid high-z high-z r e a d * 2 h l l *4 valid output valid output valid w r ite (upper by te) h l valid invalid input valid w r ite (low er by te) l h valid input valid invalid write (w ord) h l l h l l v a l i d input valid input valid i dda yes pow e r dow n * 3 l x x x x x x high- z high- z i ddp no/yes notes : l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance, key = key address. *1: output disable mode s hould not be kept longer than 1 s. *2: by te control at read mode is not supported. *3: pow e r dow n mode can be entered from standby state and all dq pins are in high-z state. i ddp current and data retention depend on the selection of pow e r dow n program. *4: either or both lb and ub must be low for read operation. *5: can be either v il or v ih but must be valid before read or write. - 6 -
w963a6bbn 8. elecrical characteristics absolute maximum ratings paramet e r s y m b o l val u e unit voltage of v dd supply relative to v ss v dd - 0.5 to + 3 .6 v voltage at any pin relative to v ss v in , v out -0.5 to + 3 .6 v short circuit output current i out 5 0 m a storage temperature t stg -55 to +125 c warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions (reference to v ss ) p a r a m e t e r n o t e s s y m b o l m i n . m a x . u n i t v dd 2 . 7 3 . 3 v supply voltage v ss 0 0 v high level input voltage *1 v ih 2 . 2 v dd + 0 .3 v low level input voltage *2 v il - 0 . 3 0 . 5 v ambient temperature t a 0 7 0 c ambient temperature t a - 2 5 8 5 c ambient temperature t a - 4 0 8 5 c notes : *1: maximum dc voltage on input and i/o pins are v dd +0.3v. during voltage transitions, inputs may positive overshoot t o v dd +1.0v for periods of up to 5ns. *2: minimum dc voltage on input and i/o pi ns are -0.3v. during voltage transiti ons, inputs may negative overshoot to - 1.0v for periods of up to 5ns. warning: recommended operating conditions ar e normal operating ranges for t he semiconductor device. all the device? s electrical characteristics ar e w a rranted w hen operated w i thin these ranges. alw a ys use semiconductor devices w i thin the recommended operating conditi ons. operation outside these ranges may adversely affect reliab ility and could result in device failure. no w a rranty is made w i th respect to uses, operat ing conditions, or combi nations not represented on the datasheet. users considering application outside the listed conditions are advised to contact their w i nbond repres entative beforehand. publ i c at i on rel e ase dat e : march 10, 2003 - 7 - revi si on a1
w963a6bbn capacitance test conditions: t a = 25 c, f = 1.0 mhz descript i o n s y m b o l t est set u p t y p . m a x . unit address input capacitance c in1 v in = 0v - 5 p f control input capacitance c in2 v in = 0v - 5 p f data input/output capacitance c io v io = 0v - 8 p f dc characteristics (under recommended operating conditions unless otherwise noted) notes*1, *2, *3 p a r a m e t e r s y m . test condi t i o n s m i n . m a x . u n i t input leakage current i li v in = v ss to v dd - 1 . 0 + 1 . 0 a output leakage current i lo v out = v ss to v dd , output disable - 1 . 0 + 1 . 0 a output high voltage level v oh v dd = v dd , i oh = -0.5 ma 2 . 2 - v output low voltage level v ol i ol = 1 ma - 0 . 4 v ( t t l ) i dds v dd = v dd max., v in = v ih or v il ce1 = ce 2 = v ih - 3 m a standby current ( c m o s ) i dds1 v dd = v dd max., v in 0.2v or v in v dd - 0.2v, ce1 = ce 2 v dd - 0.2v - 7 0 a i dda1 t rc / t wc = minimum - 2 0 m a ac tive current i dda2 v dd = v dd max., v in = v ih or v il , ce1 = v il and ce2 = v ih , i out = 0 ma t rc / t wc = 1 s - 3 m a notes : *1: all voltages are reference to v ss . *2: dc characteristics are measured after follow ing po wer-up timing. *3: i out depends on the output load conditions. - 8 -
w963a6bbn ac characteristics (under recommended operating conditions unless otherwise noted) read operation - 7 0 - 8 0 paramet e r s y m . m i n . m a x . m i n . m a x . u n i t n o t e s read cycle time t rc 7 0 - 8 0 - n s chip enable access time t ce - 6 5 - 7 5 n s *1, *3 output enable access time t oe - 4 0 - 4 5 n s *1 a ddress a ccess time t aa - 6 5 - 7 5 n s *1 output data hold time t oh 5 - 5 - n s *1 ce1 low to output low-z t cl z 5 - 5 - n s *2 oe low to output low-z t olz 0 - 0 - n s *2 ce1 high to output high-z t chz - 2 0 - 2 5 n s *2 oe high to output high-z t ohz - 2 0 - 2 5 n s *2 address setup time to ce1 low t asc - 5 - - 5 - n s *4 t aso 3 0 - 3 5 - n s *3, *5 address setup time to oe low t aso[abs] 1 0 - 1 0 - n s *6 lb / ub setup time to ce1 low t bsc - 5 - - 5 - n s lb / ub setup time to oe low t bso 1 0 - 1 0 - n s address invalid time t ax - 5 - 5 n s address hold time from ce1 low t cl a h 7 0 - 8 0 - n s address hold time from oe low t olah 4 0 - 4 5 - n s *9 address hold time from ce1 high t cha h - 5 - - 5 - n s address hold time from oe high t ohah - 5 - - 5 - n s lb / ub hold time from ce1 high t chb h - 5 - - 5 - n s lb / ub hold time from oe high t ohbh - 5 - - 5 - n s ce1 low to oe low delay time t cl ol 2 5 1 0 0 0 3 0 1 0 0 0 n s *3, *5, *7, *8 oe low to ce1 high delay time t olch 3 5 - 4 0 - n s *7 ce1 high pulse width t cp 1 2 - 1 5 - n s t op 2 5 1 0 0 0 3 0 1 0 0 0 n s *5, *7, *8 oe high pulse width t op[abs] 1 2 - 1 5 - n s *6 publ i c at i on rel e ase dat e : march 10, 2003 - 9 - revi si on a1
w963a6bbn read operation, continued notes: *1: the output load is 30 pf *2: the output load is 5 pf. *3: the t ce is applicable if oe is brought to low before ce1 goes low and is also applicable if actual value of both or either t aso or t cl ol is shorter than specified value. *4: applicable if oe is brought to low before ce1 goes low . *5: the t aso , t cl ol (mi n ) and t op (mi n ) are reference values w hen the access time is determined by t oe . if actual value of each parameter is shorter than specified minimum value, t oe become longer by the amount of subtracting actual value from specifi ed minimum value. for example, if actual t aso , t aso (actual), is shorter than sp ecified minimum value, t aso (mi n ), duri ng oe control access ( i e., ce1 stay s low ), the t oe become t oe (max) + t aso (mi n ) - t aso (ac t ual ). *6: the t aso[abs] and t op[abs] is the absolute mi nimum value during oe contr o l access. *7: if actual value of either t cl ol or t op is shorter than specifi ed minimum value, both t olah and t olch become t rc (mi n ) - t cl ol (actual) or t rc (mi n ) - t op (ac t ual ). *8: maximum value is applicable if ce1 is kept at low . - 10 -
w963a6bbn ac characteristics, continued write operation - 7 0 - 8 0 p a r a m e t e r s y m . m i n . m a x . m i n . m a x . unit n o t e s write cy cle time t wc 7 0 - 8 0 - n s *1 address setup time t as 0 - 0 - n s *2 address hold time t ah 3 5 - 4 0 - n s *2 ce1 write setup time t cs 0 1 0 0 0 0 1 0 0 0 n s ce1 write hold time t ch 0 1 0 0 0 0 1 0 0 0 n s we setup time t ws 0 - 0 - n s we hold time t wh 0 - 0 - n s lb and ub setup time t bs - 5 - - 5 - n s lb and ub hold time t bh - 5 - - 5 - n s oe setup time t oes 0 1 0 0 0 0 1 0 0 0 n s *3 t oeh 3 0 1 0 0 0 3 5 1 0 0 0 n s *3, *4 oe hold time t oeh [ abs] 1 2 - 1 5 - n s *5 oe high to ce1 low setup time t ohcl - 5 - - 5 - n s *6 oe high to address hold time t ohah - 5 - - 5 - n s *7 ce1 write pulse width t cw 4 5 - 5 0 - n s *1, *8 we write pulse width t wp 4 5 - 5 0 - n s *1, *8 ce1 write recov e ry time t wr c 1 0 - 1 5 - n s *1, *9 we write recov e ry time t wr 1 0 1 0 0 0 1 5 1 0 0 0 n s *1, *3, *9 data setup time t ds 1 5 - 2 0 - n s data hold time t dh 0 - 0 - n s ce1 high pulse width t cp 1 2 - 1 5 - n s *9 publ i c at i on rel e ase dat e : march 10, 2003 - 11 - revi si on a1
w963a6bbn write operation, continued notes: *1: minimum value must be equal or greater than the sum of actual t cw (or t wp ) and t wr c (or t wr ). *2: new w r ite address is valid from either ce1 or we is brought to high. *3: the t oeh is specified from end of t wc (mi n .). the t oeh (min) is a reference value w h en the access time is determined b y t oe . if actual value, t oeh (actual) is shorter than specif ied minimum value, t oe become longer by the amount of subtracting actual value from spec ified minimum value. *4: the t oeh (max) is applicable if ce1 is kept at low and both we and oe are kept at high. *5: the t oeh [ abs] is the absolute minimum value if w r ite cy cle is terminated by we and ce1 stay s low . *6: t ohcl (min) must be satisfied if read operation is not performed prior to w r ite operation. in case oe is disabled after t ohcl (mi n .), we low must be asserted after t rc (mi n ) from ce1 low . in other w o rds, read operation is initiated if t ohcl (mi n .) is not satisfied. *7: applicable if ce1 stay s low after read operation. *8: t cw and t wp is applicable if w r ite operation is initiated by ce1 and we , respectively . *9: t wr c and t wr is applicable if w r ite operation is terminated by ce1 and we , respectively . the t wr (mi n ) can be ignored if ce1 is brought to high together or after we is brought to high. in such case, the t cp (mi n ) must be satisfied. - 12 -
w963a6bbn ac characteristics, continued p o we r d o wn a n d p o we r d o wn p r o g r a m p a r a m e t e r s - 7 0 - 8 0 p a r a m e t e r s y m . m i n . m a x . m i n . m a x . unit n o tes ce2 low setup time for power down entry t cs p 1 0 - 1 0 - n s ce2 low hold time after power down entry t c2 l p 7 0 - 8 0 - n s ce1 high setup time following ce2 high after power down ex it t chs 1 0 - 1 0 - n s other timing parameters - 7 0 - 8 0 paramet e r s y m . m i n . m a x . m i n . m a x . unit n o tes ce1 high to oe invalid time for standby entry t chox 1 0 - 1 0 - n s ce1 high to we invalid time for standby entry t chw x 1 0 - 1 0 - n s *1 ce2 low hold time after power-up t c 2lh 5 0 - 5 0 - s *2 ce2 high hold time after power-up t c2 hl 5 0 - 5 0 - s *3 ce1 high hold time following ce2 high after power-up t chh 3 5 0 - 3 5 0 - s *2 input transition time t t 1 2 5 1 2 5 n s *4 notes: *1: some data might be w r itten into any address location if t chw x (mi n ) is not satisfied. *2: must satisfy t chh (mi n ) after t c 2lh (mi n ). *3: requires pow e r dow n mode entry and exit after t c2 hl . *4: the input transition time (t t ) at ac testing is 5ns as show n in below . if actual t t is longer than 5ns, it may violate ac specified of some timing parameters. ac test conditions symbol d e s c r i p t i o n t est set u p val u e unit not e v ih input high level v dd = 2.7v to 3.3v 2 . 3 v v il input low level v dd = 2.7v to 3.3v 0 . 5 v v ref input timing measurement level v dd = 2.7v to 3.3v 1 . 3 v t t input transition time between v il and v ih 5 n s publ i c at i on rel e ase dat e : march 10, 2003 - 13 - revi si on a1
w963a6bbn 9. timing waveforms read timing #1 ( oe control access) dq (o utput) addr e s s ce1 oe lb / ub t rc t rc t ce t clol t oe t as o t bso t olz t oha h t op t ohb h t bs o t oh z t oh t olz t oh t oh z t ohb h t oe t ol c h t oh a h t aso add r e ss va lid a d dress v a lid v a l i d d a ta o u tp u t v a l i d d a ta o u tp u t note: ce2, pe and we must be high for entire read cy cle. either or both lb and ub must be low w hen both ce1 and oe are low . - 14 -
w963a6bbn timing waveforms, continued read timing #2 ( ce1 control access) dq (o u t put) ad d r ess ce 1 oe lb / ub t rc t rc t ce t olz t ch ah t cp t ch bh t bsc t ch z t oh t cl z t oh t ch z t ch bh t ch ah t asc a ddre ss v a l id addr es s v a l i d v a l i d da t a out p ut va lid da t a o u t p ut t asc t bsc t ce note: ce2, pe and we must be high for entire read cy cle. either or both lb and ub must be low w hen both ce1 and oe are low . publ i c at i on rel e ase dat e : march 10, 2003 - 15 - revi si on a1
w963a6bbn timing waveforms, continued read timing #3 (address access after oe control access) dq (o utput) ce 1 oe lb / ub t rc t rc t olz t oh t oh t ohb h t oha h v a l i d da t a o u t p ut v a l id da t a out p ut t bso ad d r ess va lid a d d r ess val id t ax t ohz t aso t ola h t oe t aa ad dre ss note: ce2, pe and we must be high for entire read cy cle. either or both lb and ub must be low w hen both ce1 and oe are low . - 16 -
w963a6bbn timing waveforms, continued read timing #4 (address access after ce1 control access) dq (o ut put ) ce 1 oe l b / ub t rc t rc t cl z t oh t oh t chb h t cha h v a l i d da t a o u t p ut v a l id da t a out p ut t bs c ad d r ess va lid a d d r ess val id t ax t ch z t cl ah t ce t aa ad dre ss t as c note: ce2, pe and we must be high for entire read cy cle. either or both lb and ub must be low w hen both ce1 and oe are low . publ i c at i on rel e ase dat e : march 10, 2003 - 17 - revi si on a1
w963a6bbn timing waveforms, continued write timing #1 ( ce1 control) dq (intput ) ad d r ess we oe lb / u b ad d r ess val id val id d a t a in t p u t t ws t as t as t ah t wc t bs t oh c l t wc t wr c t bh t bs t dh t ds ce 1 t wh t ws note: ce2 and pe must be high for entire w r ite cy cle. - 18 -
w963a6bbn timing waveforms, continued write timing #2-1 ( we control, single write operation) dq (intput ) ad d r ess we oe lb / u b ad d r ess val id val id d a t a in t p u t t cs t as t ah t wp t bs t oe s t wc t dh t ds ce 1 t oh a h t oh c l t bh t as t cp t wr t ch t bh t oh z note: ce2 and pe must be high for entire w r ite cy cle. publ i c at i on rel e ase dat e : march 10, 2003 - 19 - revi si on a1
w963a6bbn timing waveforms, continued write timing #2 ( we control, continuous write operation) dq (intput ) ad d r ess we oe lb / u b ad d r ess val id val id d a t a in t p u t t cs t as t ah t wp t bs t oes t wc t dh t ds ce 1 t oh a h t oh c l t oh b h t as t wr t bh t oh z t bs note: ce2 and pe must be high for entire w r ite cy cle. - 20 -
w963a6bbn timing waveforms, continued read/write timing #1-1 ( ce1 control) dq (i nt p u t ) ad d r ess we oe lb / ub a ddre s s v a l id val id d a t a in t p u t t ws t as t ah t cw t bs t oh c l t wc t dh t ds ce 1 t chah t wh t ch b h t as t wr c t bh t ch z t bs o t cp t oh t wh t ws t olz t cl o l val id dat a int p ut note: write address is valid from either ce1 or we of last falling edge. publ i c at i on rel e ase dat e : march 10, 2003 - 21 - revi si on a1
w963a6bbn timing waveforms, continued read/write timing #1-2 ( ce1 control) dq ad d r ess we oe l b / ub t rc t cl z t oh t ch a h ad d r ess valid valid dat a o u t p ut val id dat a o u t p ut t oeh t oe t as w r it e a ddre s s t t (m i n ) t wh t ws note: the t oeh is specified from the time satisfied both t wr c and t wr (mi n ). - 22 -
w963a6bbn timing waveforms, continued read ( oe control) / write ( we control) timing #2-1 dq (int pu t) ad d r ess we oe lb / u b w r it e ad d r ess val id dat a int p ut l o w t as t ah t wp t bs t oes t wc t dh t ds ce 1 t oha h t ohb h t aso t oh z t oh t wr t olz t oeh v a lid da t a int p u t t oeh t bh r ead ad d r ess note: ce1 can be tied to low for we and oe controlled operation. when ce1 is tied to low , output is exclusively controlled by oe . publ i c at i on rel e ase dat e : march 10, 2003 - 23 - revi si on a1
w963a6bbn timing waveforms, continued read ( oe control) / write ( we control) timing #2-2 dq ad d r ess we oe l b / ub t rc t ol z t oh t oh a h ad d r ess valid valid dat a o u t p ut val id dat a o u t p ut t note: ce1 can be tied to low for we and oe controlled operation. when ce1 is tied to low , output is exclusively controlled by oe . - 24 -
w963a6bbn timing waveforms, continued pow e r dow n program timing pe addr e s s (a20 -16) t eas ce 1 t ep s t ea h t ep t ep h ke y note: ce2 must be high for pow e r dow n program operation. any other inputs not specifi ed above can be either high or low . pow e r dow n entry and exit timing ce2 dq hi g h -z t c2lp t cs p p o we r d o wn e n t r y po w e r d o wn mo de power d o w n ex it ce1 t chs t ch h (t ch hn ) note: this pow e r dow n mode can be also used for pow e r-up #2 below except that t chhn can not be used at pow e r-up timing. pow e r-up timing #1 ce 2 v dd v dd mi n t c2lh ce 1 t ch s t ch h 0v note: the t c 2lh specifies after v dd reaches specified minimum level. publ i c at i on rel e ase dat e : march 10, 2003 - 25 - revi si on a1
w963a6bbn timing waveforms, continued pow e r-up timing #2 ce 2 v dd v dd mi n t c2 h l ce 1 t c 2lp 0v t cs p t chh t c2 h l t ch s note: the t c2 hl specifies from ce2 low to high transition after v dd reaches specified minimum level. ce1 must be brought to high prior to or together w i th ce2 low to high transition. standby entry timing after read or write ce1 oe we a c ti v e (rea d) st an db y t ch o x a c t i v e (w ri t e ) st an db y t ch w x note: both t chox and t chw x define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period from either last addre ss transition of a0, a1 and a2, or ce1 low to high transition. - 26 -
w963a6bbn 10. package dimension tfbga 48 balls (6 x 8 mm^2, pitch 0.75 mm) publ i c at i on rel e ase dat e : march 10, 2003 - 27 - revi si on a1
w963a6bbn 11. ordering information part no. speed operating t e mperat ure package w963a6bbn70 70 ns 0 to 70 tfbga 48, 6 mm x 8 mm, ball pitch 0.75 mm w963a6bbn70e 70 ns -25 to 85 tfbga 48, 6 mm x 8 mm, ball pitch 0.75 mm w963a6bbn70i 70 ns -40 to 85 tfbga 48, 6 mm x 8 mm, ball pitch 0.75 mm w963a6bbn80 80 ns 0 to 70 tfbga 48, 6 mm x 8 mm, ball pitch 0.75 mm W963A6BBN80E 80 ns -25 to 85 tfbga 48, 6 mm x 8 mm, ball pitch 0.7 5mm w963a6bbn80i 80 ns -40 to 85 tfbga 48, 6 mm x 8 mm, ball pitch 0.75 mm notes: 1. winbond reserves the right to make changes to its products w i thout prior notice. 2. purchasers are responsible for performing appropriate qualit y assurance testing on products intended for use in applications w here personal injury might occur as a consequence of product failure. - 28 -
w963a6bbn publ i c at i on rel e ase dat e : march 10, 2003 - 29 - revi si on a1 12. version history v e r s i o n d a t e p a g e descript i o n a1 march 10, 2003 - create new document headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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