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MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 1 advanced information advanced digital video encoder y/cb/cr output support hcmos technology MC44722A mc44723a the MC44722A and mc44723a are advanced digital video encoders (dve). they convert itu-601/656 standard 4:2:2 bit- paralellel data into analog composite video, s-video or analog component signals y/cb/cr in pal and ntsc formats. they accept the multiplexed two 8-bit or 16-bit ((cb,y,cr)y) signals from digital sources such as mpeg decoders and can act as a sync generator master or as a sync slave. all video processing is done digitally and requires no external adjustment. specifically designed for digital satellite, digital cable decoders, multimedia terminals and dvd players. ?world wide operation (pal-bdghi, pal-n,pal-m, ntsc-m) ?smpte 170m / itu - r 624 composite video output ?programmable color sub-carrier frequencies ?analog standard timing for horizontal, vertical, frame and composite sync outputs ?sync extraction from digital input data (sav, eav) ?sync polarity and horizontal / vertical phase control ?master or slave sync (h/vsync, h/fsync, itu-r656 slave) operation ?interlaced or non-interlaced support ?625/50 or 525/60 itu-601/656 two 8-bit or 16-bit ((cb,y,cr)y) digital input ?luma 2x / chroma 4x output interpolating filter ?dual digital a / b selectable inputs ?external vbi information data input (teletext information data) ?selectable one set of signal within (cvbs/y/c) or (y/cb/cr) ?selectable analog component output ( beta cam or mii component interface level ) ?three analog outputs through 10-bit dacs ?easily programmed via serial bus ( i2c or 4-wired spi bus) ?2 hardware selectable i2c chip addresses ?closed-caption, cgms and wss information data insertion ?macrovision ver. 7.01 anti-copy signal insertion(MC44722A only) ?on chip color - bar generator ?5v tolerante input ?+3.3v power supply or +3.3v(digital)/+5v(analog) power supply ?pin compatible with mc44722/3 the MC44722A device is protected by u.s. patent number 4,631,603,4,577,216 and 4,819,098 and other intellectual property rights. the use of macrovision's copy protection technology in the device must be authorized by macrovision and is intended for home and other limited pay- per-view uses only, unless otherwise authorized in writing by macrovision. reverse engineering or disassembly is prohibited. ft suffix 48 qfp (0.8mm pitch)
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . [pin assignment] 2 cvbs / cb hsync c/fsync/vbi vmute dvia3 dvia4 dvia5 dvia6 dvia7 a/b_sel dvib7 dvib6 dvib6 dvib4 dvss dvdd dvib3 MC44722A mc44723a 1 2 3 4 5 6 7 8 9 12 14 15 16 17 18 19 20 21 vreff 13 24 22 10 11 36 35 34 33 32 31 30 29 28 25 27 26 23 47 46 45 44 43 42 41 40 48 37 39 38 cvbs / cb cvbs/cbvdd y y yvdd c / cr c / cr cvdd davss ibias davdd chipa test so sda/si scl/sck sel dvss clock dvdd reset pal/ntsc dvia0 dvia1 dvia2 f / vsync dvib2 dvib1 dvib0 tp
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . pin name i/o descriptions [pin descriptions] 3 1 cvbs / cb o analog composite video signal output or cb signal output current drive(positive) 2 cvbs /cb o analog composite video signal output or cb signal output current drive(negative) 3 cvbs/cbvdd power supply for cvbs / cb dac circuit 4 y o analog luminance signal output current drive(positive) 5 y o analog luminance signal output current drive(negative) 6 yvdd power supply for y dac circuit 7 c/cr o analog chrominance signal output or cr signal output current drive(positive) 8 c/cr o analog chrominance signal output or cr signal output current drive(negative) 9 c/crvdd power supply for c / cr dac circuit 10 davss ground for dac circuit 11 ibias o reference current for the 3 dacs 12 davdd power supply for dac circuit 13 vreff reference full scale voltage for the 3 dacs 14 chipa i2c chip address select { 0 : 42(hex)/43(hex) 1 : 1c(hex )/1d(hex) } 15 test i test pin(ground) 16 so z(o) if spi mode, serial data output / if i2c mode, connect to ground 17 sda/si i/o(i) serial data input, open drain output / if spi mode, serial data input 18 scl/sck i serial clock 19 sel (i) connect to ground / if spi mode, this pin is chip select 20 dvss ground for digital circuit 21 clock i 27mhz clock input 22 dvdd power supply for digital circuit 23 reset i reset signal, active low 24 pal/ntsc i ntsc/pal select . this pin active only reset time. (ntsc : low pal : high ) 25~32 dvia7~0 i 8-bit multiplexed y/cr/cb 4:2:2 data(itu rec656) input(dvia) or multiplexed y data (itu- rec656/601) input in 16-bit input mode (dvia7 : msb ) 33 vmute i video mute on reset ( 0 : nomal, 1 : mute ), or test data input 34 c/fsync/vbi i/o csync/frame sync output or external vbi information input 35 f/vsync i/o frame sync or vertical sync input/output 36 hsync i/o horizontal sync input/output 37 a/b_sel i/o switch control for 8-bit x 2 multiplexed y/cr/cb 4:2:2 data(itu- rec656) input (dvia) or (dvib) , or test data i/o 38~41 dvib8~5 i/o 8-bit multiplexed 4:2:2 data(itu- rec656/601) input(2), or multiplexed cr/cb data (itu- rec656/601) input in 16-bit input mode (msb: dvib8), or test data input/output 42 dvss ground for digital circuit 43 dvdd power supply for digital circuit 44~47 dvib4~1 i/o 8-bit multiplexed 4:2:2 data(itu- rec656/601) input(dvib), or multiplexed cr/cb data(itu- rec656/601) input in 16-bit input mode (lsb:dvib1), or test data i/o 48 tp i/o for test (should be ground) note : power supply group digital ---> 22-pin, 43-pin, analog ---> 3-pin, 6-pin, 9-pin, 12-pin
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 4 [block diagram] dac yout yout cout / cr cout / cr cvbsout / cb cvbsout / cb yvdd cvbs/cbvdd c/crvdd davdd davss ibias bias c/fsync/vbi f/vsync hsync dvia[7 : 0] sda/si scl/sck 0 0 0 0 cgms_gen cc_gen sync_generator copy protection bus off_set bg modulator subcarrier gen 0 dac 0 dac 0 test test pal/ntsc reset vmute demux y cb cr h,v chipa dvdd dvdd dvss dvss i2c/spi chip-address 42/43(hex) 1c/1d(hex) clock MC44722A/3a vreff sel so i2c / spi dvib[7 : 0] tp
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 5 clock 27.0mhz. this signal on the clock pin needs to be active and stable for 5 cycles before the reset pin is de-asserted. [function descriptions] fig 1 : dvia/dvib data input timing input clock 27mhz input data dvia/dvib 50% tds tdh clock 27mhz output data h/v/f sync output data tp td td fig 2 : sync data output timing reset procedure reset is a level sensitive input pin. driving the reset pin low causes a dve reset. the 27mhz dve clock signal must be active before reset is released. de-asserting reset will latch the status of the pal/ ntsc, vmute and sel pins. the pal/ntsc pin determines the default values for the dve control registers. the default register values have been chosen so that standard pal or ntsc video will appear at the dac outputs immediately when a valid input digital video data stream is present and vmute is low at reset. the vmute pin controls the "out of reset" operation of the analog output signals. when "1" at reset, the video output is muted - output signal is "black - sync". when "0" at reset, the video output is from the input video data. this control can be used to mute the disable noise signals from a mpeg decoder at reset until a clear and stable picture is available. the value on the sel pins determine the default serial communication mode. if low, the dve use i2c bus operation. if high, the dve use 4-wired spi operation. after reset, the vbi signals (closed-caption, cgms and wss ) are disabled. (see page --- for sub-address register descriptions.)
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . video timing / sync generator the dve outputs pal-b,d,g,h,i, pal-n, pal-m or ntsc-m standard video signals. the dve sync generator can be operated in two sync modes, master or slave. in master mode, the dve generates all the correct horizontal and vertical or frame sync signals internally, and outputs the csync signal through the c/fsync/vbi pin(c/fsync). in slave mode, the dve derives the sync signals from the bit-parallel input data stream start active video (sav) and end active video (eav) data packet information. sync signals are output on the hsync and f/vsync or c/fsync/vbi pins and can be programmed for positive or negative polarity. the phase of hsync can also be controlled. also, the dve allows more two slave modes. one is h/vsync slave, and the another is h/fsync slave mode. vertical blanking corresponds to the ?ollowing lines. 625/50 624-22 311-335 itu-r line numbering 525/60 1-19 264-282 smpte line numbering (see figures 3,4,5,6,7,8,9,10, and 11 for sub-address register descriptions.) input data format the input digital video is in accord with the itu-r rec.656 and smpte 125m standards. it is two 8-bit or 16-bit multiplexed 4:2:2 ((cb,y,cr)y) data stream. samples are latched on the rising edge of the clock signal. data is input on pins dvia[ 7 : 0 ] and dvib[ 7 : 0 ] (see figures 3 and 4 for sub-address register descriptions.) 6 fig 3 : digital input timing(525/60 system) in master mode 70(hex){[1:0]=01} 1440t hsync phase sub-address71[2:0] hsync clock 128t t 244t hsync polarity sub-address71[5] +4t delay -3t delay dvia[7:0] cr 718 cb 718 y 718 y 719 00 00 ff cb 2 cr 0 cb 0 y 0 y 1 y 2 invalid 00 00 xy ff y 718 y 719 dvib[7:0] cr 718 cb 718 cb 2 cr 0 cb 0 invalid dvia[7:0] y2 y 1 y 0 invalid 16-bit input mode 8-bit input mode cb 718 cr 718 cr 2 cr 0 cb 0 or 242t
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 7 csync csync 525 524 1234567891011 212223 262 261 263 264 265 266 267 268 269 270 271 272 273 283 284 285 fig 5 : sync timing::525/60 interlaced system in master mode vsync hsync vsync hsync sub-address71[7] =0 fsync fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync fig 4 : digital input timing(625/50 system) in master mode 70(hex){[1:0]=01} 1440t hsync phase sub-address71[2:0] hsync clock 128t t 264t hsync polarity sub-address71[5] +4t delay -3t delay dvia[7:0] cr 718 cb 718 y 718 y 719 00 00 ff cb 2 cr 0 cb 0 y 0 y 1 y 2 invalid 00 00 xy ff y 718 y 719 dvib[7:0] cr 718 cb 718 cb 2 cr 0 cb 0 invalid dvia[7:0] y2 y 1 y 0 invalid 16-bit input mode 8-bit input mode cb 718 cr 718 cr 2 cr 0 cb 0 or 262t
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 8 csync 262 261 1234567891011 212223 fig 7 : sync timing::525/60 non-interlaced system in master mode csync 310 311 312 1 2 3 4 6 7 8 21 22 23 5 309 308 vsync hsync vsync hsync fig 8 : sync timing::625/50 non-interlaced system in master mode 9 sub-address71[7] =1 fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync sub-address71[7] =1 csync 623 624 625 1 2 4 6 7 8 21 22 23 csync 311 312 313 314 315 316 317 318 319 320 321 334 335 5 622 621 310 309 vsync hsync vsync hsync fig 6 : sync timing::625/50 interlaced system in master mode 9 fsync fsync polarity sub-address71[3] vsync polarity sub-address71[4] fsync sub-address71[7] =0 3
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . fig 10 : sync timing::525/60 interlaced system in slave mode vsync hsync fsync vsync polarity sub-address71[5] csync 34567 fsync polarity sub-address71[4] odd field csync vsync hsync fsync 266 267 268 269 even field sub-address71[1:0] =10, 11 hsync delay sub-address 7a[7:0], 71[3:0] internal hsync reset counter 9 fig 9 : analog sync timing::rise and fall 2.37us 29.41us 27.04us 4.74us 0.148us 0.148us 63.56us ntsc pal 0.222us 0.222us 2.37us 29.63us 27.26us 4.74us 64.00us
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 10 fig 11 : sync timing::625/50 interlaced system in slave mode vsync hsync fsync vsync polarity sub-address71[5] fsync polarity sub-address71[4] odd field csync 6251234 csync vsync hsync fsync 313 314 315 316 even field sub-address71[1:0] =10, 11 hsync delay sub-address 7a[7:0], 71[3:0] internal hsync reset counter
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . chroma / luma encoding the dve de-multiplexes the 4:2:2 digital video data stream. the de-multiplexed y or luma samples are interpolated at the clock rate. offset compensation is then added, next any vbi signals consisting of closed-caption, cgms and wss are added to the appropriate lines, then finally composite sync pulses are added to the luma signal.(see figure 14.) de-multiplexed component color cb and cr samples are interpolated at the clock rate. the luma and chroma interpolation filter compensate for the sin(x)/x attenuation to on chip d/a converter and simplify the output filter and allows more accurate encoding. a set of 3 different filters is available for each luma and chroma filtering. and user can select within these filters to fit a wide variety of applications. (see figure 12 and 13, and sub-address resister 6f ) the dve generates the necessary subcarrier color frequency for pal or ntsc encoding from the 27mhz system clock. this color subcarrier is then modulated by the base band component color cb and cr signals to create the video chroma signal. (see figure 15.) a 7.5 ire pedestal is added for the 60hz field rate. this can be added for the 50hz field rate through serial bus control. (see sub-address register descriptions) 11 "cvbs and s-video" or "ycbcr" outputs the internal digital video signals drive 10-bit d/a converters. converter outputs are bidirectional current sources where the current is proportional to the digital data with reference to the ibias reference current. the pins cvbs/cb, y and c/cr are the respective composite, luma and chroma or y/cb/cr signal current source pins. each of the dacs can drive 75ohm load resister. user can select 1 sets of signals from the above 2 signal sets (cvbs/y/c or y/cb/cr ). (see "application diagram" and "sub-address register descriptions".) in y/cr/cb analog component output mode, user can select one of the component interface level , beta cam or m2 format ( see sub-address register 6e ). bias current gain dacs can be switched off through serial bus control to reduce power consumption. both outputs of unused dacs should be connected to ground through a resister to avoid charge buildup. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 6 frequency [mhz] amplitude [db] fig. 12 luma filtering including dac attenuation 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 -9 -6 -3 0 3 6 frequency [mhz] amplitude [db] f1 = 6mhz f2 = 5mjz f3 = 2.5mhz f1 = 3mhz f2 = 2.5mhz f3 = 1.5mhz fig. 13 chroma filtering
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . fig 14 : luminance output range 12 106 16 235 210 170 145 81 41 16 digital y input code(16~235) 525/60 and 625/50 system 100%amplitude,100%saturation color bar 0 11 30 41 59 70 89 100 -33 ire 670 620 540 490 412 362 282 232 44 200 0 code 1023 0 11 30 41 59 70 89 100 -43 ire 670 620 540 490 412 362 282 232 44 232 analog y output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5ire setup off 0 code 1023 232 0 7.5 30 41 59 70 89 100 -40 ire 670 620 540 490 412 362 282 232 56 analog y output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5ire setup off 0 code 1023 232 11 0 7.5 30 41 59 70 89 100 -40 ire 670 620 540 490 412 362 282 232 12 analog y output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5ire setup on 0 code 1023 232 11 200 analog y output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5ire setup on
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 13 fig 15 : chrominance output range 146 128 16 34 222 240 110 128 digital cr-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar digital cb-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar 16 166 54 202 90 240 128 128 228 324 302 324 228 110 302 -6 3 -48 -21.5 21.5 48 63 67 ire analog c output level(625/50 system) 100%amplitude,100%saturation color bar => 7.5ire setup on/off -67 0 code 512 0 1023 ire analog c output level(525/60 system) 100%amplitude,100%saturation color bar => 7.5ire setup off/on -59 -45 -20 20 45 59 63 -63 0 228 324 302 324 228 110 302 code 512 0 1023
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . fig 16 : y/cb/cr output range ( beta cam component interface level ) 14 584 512 64 136 888 960 440 512 digital cr-input code 100%amplitude,100%saturation color bar => 7.5ire setup on/off ire 0 code 1023 -59 -45 -20 20 45 59 63 -63 0 512 64 664 216 808 360 960 512 512 -63 -48 -21.5 21.5 48 63 ire 0 code 512 0 1023 digital cb-input code 100%amplitude,100%saturation color bar => 7.5ire setup on/off 670 620 540 490 412 362 282 232 12 200 0 code 1023 ire 670 620 540 490 412 362 282 232 56 232 analog y output level 100%amplitude,100%saturation color bar => 7.5ire setup off 0 code 1023 232 ire 0 7.5 30 41 59 70 89 100 -40 11 0 30 41 59 70 89 100 -40 11 analog y output level 100%amplitude,100%saturation color bar => 7.5ire setup on
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . fig 17 : y/cb/cr output range ( m2 component interface level ) 15 584 512 64 136 888 960 440 512 digital cr-input code 100%amplitude,100%saturation color bar => 7.5ire setup on/off ire 0 code 1023 -59 -45 -20 20 45 59 63 -63 0 512 64 664 216 808 360 960 512 512 -63 -48 -21.5 21.5 48 63 ire 0 code 512 0 1023 digital cb-input code 100%amplitude,100%saturation color bar => 7.5ire setup on/off 0 11 30 41 59 70 89 100 -43 ire 670 620 540 490 412 362 282 232 44 232 analog y output level 100%amplitude,100%saturation color bar => 7.5ire setup off 0 code 1023 0 11 30 41 59 70 89 100 -33 ire 670 620 540 490 412 362 282 232 44 200 analog y output level 100%amplitude,100%saturation color bar => 7.5ire setup on 0 code 1023 232
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . closed-caption encoding closed-captioned or extended data service signals can be encoded by the dve onto output video line 21/284 (ntsc) and line 22/335 (pal). the cc data is input through the serial bus interface. two 8-bit byte data pairs are encoded for each field. there are four registers for holding the data - two bytes per field. the serial data is 7bit us-ascii msb first, proceeded by an odd parity bit. total 8-bits. (p-7-6-5-4-3-2-1-0) the dve automatically generates the required clock run in and start bit for cc encoding. (see figure 16.) when closed-captioning is enabled, the system micro processor (up) should update the cc data once each frame. this dve will automatically null characters when there is no cc data to encoder after the cc data has been processed by setting the $87[5] register. it is recommended to write cc data only to the inactive frame. field1 and field2 data are double-buffered by the frame sync falling edge of previous frame, updating frame 2 data during frame1 display and frame1 data during frame2 display. when the $87[4] register is set, the dve will generate the parity bit automatically. (see figures 26 and 27 for sub-address register descriptions.) copy generation management system (cgms) encoding cgms signals can be encoded by the dve onto output video line 20 (525 / 60 for japan). cgms identification signals also identify and control the tv screen presentation mode - wide screen, letter box and or normal -16:9 or 4:3. data is double-buffered and is latched at the start of field 1. crc code is generated by controling $88 [ 0 ] cgms_parity bit automatically. (see figures 24 for sub-address register descriptions.) 16 wide screen signaling (wss) encoding wss signals can be encoded by the dve onto output video line 23 (625 / 50 for europe). wss identification signals also identify and control the tv screen presentation mode - wide screen, letter box and or normal -16:9 or 4:3. data is double-buffered and is latched at the start of field 1. odd parity code is generated by controling $88 [ 1 ] wss_parity bit automatically. (see figures 25 for sub-address register descriptions.)
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . serial control bus control of the dve device is accomplished through the i2c-bus or 4-wired spi serial bus. in i2c mode, pins sda and scl are the respective data and clock signals. device address can be 42(hex)/43(hex) or 1c(hex)/1d(hex) . slave address is chosen at reset by the state of the chipa pin signal { 0 : 42(hex)/43(hex), 1 : 1c(hex)/1d(hex) } sub-address register read and write operations are documented in the following figures 22a - 22b. in spi mode, pins so, si, sck and sel are the respective data input, output, serial clock and chip select signals. register read and write operations are documented in the following figures 23a - 23b 17 macrovision tm copy protection when enabled, the luma and chroma signals are modified according to the macrovision tm copy protection process for pay per view (ppv) and dvd applications revision 7.01 dated sep 6th , 1996. enabling and control is through the serial control bus. no MC44722A parts will be sent to the customer until the customer provides motorola with written confirmation of a license, non-disclosure or a waiver from macrovision tm . the mc44723a device is available without macrovision tm encoding.
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 18 fig 18-a : i2c-bus interface write operation timing msb d7 d6 d5 d4 d3 d2 d1 d0 lsb scl sda msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb scl sda msb d7 d6 d5 d4 d3 d2 d1 d0 lsb start chip address(write) ack sub-address data 1 data n ack ack ack stop msb d7 d6 d5 d4 d3 d2 d1 d0 lsb scl sda msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb start chip address(write) ack sub-address data 1 ack ack by mcu ack stop scl sda start chip address(read) msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb data n ack by mcu ack by mcu stop scl sda data 2 fig 18-b : i2c-bus interface read operation timing
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 19 fig 19-a : spi-bus interface write operation timing msb d7 d6 d5 d4 d3 d2 d1 d0 lsb sck si msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb sck si msb d7 d6 d5 d4 d3 d2 d1 d0 lsb start write command sub-address data 1 data n sel x sel msb xxxxxxxx lsb so (don't care) msb xxxxxxxx lsb x msb d7xxxxxxx lsb so (don't care) msb xxxxxxxx lsb
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . msb d7 d6 d5 d4 d3 d2 d1 d0 lsb sck si msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb xxxxxxxx lsb start write command sub-address data 1 stop sck si start read command msb xxxxxxxx lsb msb xxxxxxxx lsb data n stop sck si data 2 fig 19-b : spi-bus interface read operation timing sel x msb xxxxxxxx lsb so (don't care) msb xxxxxxxx lsb x sel x msb xxxxxxxx lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb so x sel msb d7 d6 d5 d4 d3 d2 d1 d0 lsb msb d7 d6 d5 d4 d3 d2 d1 d0 lsb so 20
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 21 [specifications] dac blocks characteristics(power supply 5.0v,ta=25 c) characteristics sym. min typ max unit other resolution - - - 10 bit integral non-linearity inl - - 2.0 lsb vref = 1.5v, ibias = 1.8k w , rl = 180 w differential non-linearity dnl - - 1.0 lsb vref = 1.5v, ibias = 1.8k w , rl = 180 w analog output voltage vyo 1.35 1.5* 1.65 vp-p vref = 1.5v, ibias = 1.8k w , rl = 180 w full scale output voltage vyfs 1.35 1.5** 1.65 v vref = 1.5v, ibias = 1.8k w , rl = 180 w zero scale output voltage vyzs - 0.0*** 0.1 v vref = 1.5v, ibias = 1.8k w , rl = 180 w external load resistance r l 75 - - w dac blocks characteristics(power supply 3.3v,ta=25 c) characteristics sym. min typ max unit other resolution - - - 10 bit integral non-linearity inl - - 2.0 lsb vref = 1.0v, ibias = 1.8k w , rl = 180 w differential non-linearity dnl - - 1.0 lsb vref = 1.0v, ibias = 1.8k w , rl = 180 w analog output voltage vyo 0.85 1.00* 1.15 vp-p vref = 1.0v, ibias = 1.8k w , rl = 180 w full scale output voltage vyfs 0.85 1.00** 1.15 v vref = 1.0v, ibias = 1.8k w , rl = 180 w zero scale output voltage vyzs - 0.0*** 0.1 v vref = 1.0v, ibias = 1.8k w , rl = 180 w external load resistance r l 75 - - w note : d/a converter output full scale voltage vyts (v) = (vref / iref ) * k * r load (k = 10 : dac current gain) ( code 3ff(fex)) power dissipation pd = [ (vref/iref * 10 * 3ch) + 10ma (bais current)] * 3.3v (or 5v) electrical characteristics characteristic symbol min typ max unit other power supply voltage(analog blocks) avdd 3.1 3.3 3.5 v davdd 4.75 5.0 5.25 power supply voltage(digital blocks) dvdd 3.1 3.3 3.5 v dvdd supply current(analog blocks) aicc - 70 - ma vref = 1.0v, supply current(digital blocks) dicc - 50 - ma iref = 1.8k w , rl = 180 w operating temperature ta 0 - 70 c * : code 000(hex) ~code max. ** : code max. *** : code 000(hex) * : code 000(hex) ~code max. ** : code max. *** : code 000(hex) maximum ratings dc supply voltage vdd -0.5 ~ +7.0 v input voltage, all inputs vin -1.5 ~ vdd+1.5 v output voltage, all outputs vout -0.5 ~ vdd+1.5 v dc output current, per pin iout 25 ma power dissipation pd 750 mw storage temperature tstg -65 ~ +150 c other -1.5 ~ vdd+1.95v at vdd=3.3v
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 22 tds 50% tdh tr tf clock input data 50% valid not valid not valid clock blocks characteristics characteristic symbol min typ max unit clock rate fc - 27.0 - mhz clock duty cycle dty 45 50 55 % digital blocks electrical characteristics(power supply 3.3v,ta=25 c 3 c) characteristics symbol min typ max unit input voltage high vih 2.0 - 5.25 v low vil - - 0.8 v output voltage high voh 2.4 - - v (2.0ma) low vol - - 0.4 v input leakage current iin - 2.5 - m a hi-z leakage current ioz - 20 - m a input capacitance cin - - 20 pf load capacitance c l - - 20 pf data setup time tds 4 - - ns data hold time tdh 5 - - ns input rise time tr - - 5 ns input fall time tf - - 5 ns data delay td - - 27 ns [specifications] i2c/spi-bus blocks characteristics(power supply 3.3v,ta=25 c 3 c) characteristics symbol min typ max unit input voltage low v ilm - - 0.8 v input voltage high v ihm 2.3 - 5.25 v input current v im - - 10 m a sda output voltage (i om =3ma) v om - - 0.4 v output current (during acknowledge) i om 3 - - ma spi maxmum clock rate fspi - - 3 mhz
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . [i2c-bus slave address 42(hex)/43(hex) or 1c(hex)/1d(hex)] write mode data n data 0 sub address slave address -------- sa aa ap if more than 1byte data is transmitted, then auto-increment of the sub address is performed s start condition slave address 42(hex) or 1c(hex) a acknowledge, generated by the slave sub address sub address byte data 0 first data byte data n continued data byte(sub address is auto increment) p stop condition read mode slave address sub address n sa ap slave address sa p data n am data n + 1 am ------ am then slave receiver slave transmitter 42(hex) or 1c(hex) 43(hex) or 1d(hex) 42(hex) or 1c(hex) s start condition slave address slave receiver is act transmitter is ad a acknowledge, generated by the slave sub address n sub address byte data n data byte of register n data n + 1 data byte of register n + 1 (address auto-increment) am acknowledge, generated by the micro controller p stop condition (when last am must be '1' ) 23
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . write mode data n data 0 sub address write command -------- s p if more than 1byte data is transmitted, then auto-increment of the sub address is performed s chip select on ( hi to lo) write command 42(hex) or 1c(hex) sub address sub address byte data 0 first data byte data n continued data byte(sub address is auto increment) p chip select off (lo to hi) read mode write command sub address n sp read command sp data n data n + 1 --------- then slave receiver slave transmitter 42(hex) or 1c(hex) 43(hex) or 1d(hex) 42(hex) or 1c(hex) s chip select on (hi to lo) sub address n sub address byte set read command 43(hex) or 1d(hex) data n data byte of register n data n + 1 data byte of register n + 1 (address auto-increment) p chip select off (lo to hi) 24 [spi-bus]
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . y fil mode 0 : luma filter switch 0 : wide 6mhz (default) 1 : narrow 2.5mhz v fil, u fil mode0 : chroma filter switch 0 : wide 3.0mhz(default) 1 : narrow 1.5mhz cr fil, cb fil mode 0 : cr/cb filter switch 0 : wide 3.0mhz(default) 1 : narrow 1.5mhz cr /cb fil mode 1 : wide filter switch 0 : wide0 3.0mhz(default) 1 : wide1 2.5mhz y fil mode 1 : wide filter switch 0 : wide0 6.0mhz(default) 1 : wide1 5mhz sub-address 6f : interpolation filter switch (write) msb lsb register 6f default : 0000_0000(bin) v fil mode0 y fil mode0 u fil mode0 cr fil mode0 cb fil mode0 cb/cr/u/v fil mode1 y fil mode1 - 25 m2/beta : y select m2 type, betacam type 00 : betacam (default)* 01 : m2 ( 7.5ire setup )* 10 : betacam ( 7.5ire setup )* 11 : m2* note * : these bit can related w/ sub address $72 [ 4 ] setup bit. y mode : separate switch 0 : y /cbcr's y is same as y /c/cvbs's y (default) 1 : y /cbcr's y is the betacam or m2 y signal cbcr gain : cb/cr gain 0 : normal operation (default) 1 : 1/2 gain (disable code divided by 2) [register mapping and description] sub-address 6e : y/cbcr mode setup (write) msb lsb register 6e cbcr mode y mode m2/beta[0] default : 0000_0000(bin) m2/beta[1] ----
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 26 sub-address 70 : variable i/o switch (write/read) msb lsb register 70 bs-off self-sw color bar select vblk sw c/fsync sw default : 0000_0001(bin) f/vsync sw m/s mode1 m/s mode0 bs - off : color burst control switch on/off 0 : color burst on (default) 1 : color burst off self - sw : internal self h/v counter reset switch on / off 0 : self counter reset off (default) 1 : self counter reset on note : this mode is only valid at when 70h[1: 0] is "10(bin)" or "11(bin)". color bar select : color bar select luma chroma 0 : color bar 100% 75% 1 : color bar 100% 100% vblk sw : vertical blanking mask enable switch on-off 0 : reject vbi information data in vertical blanking period (default) 1 : through vbi information data in vertical blanking period c/fsync sw : composite sync/frame sync output switch 0 : frame sync output (default) 1 : composite sync output f/vsync sw : frame sync /vertical sync output switch 0 : vertical sync output (default) 1 : frame sync output m/s sync mode1 : master or slave sync mode m/s sync mode0 00 : 601 h/v master mode 01 : 656 slave mode(no h/vsync output) (default) 10 : fsync/hsync slave mode 11 : vsync/hsync slave mode
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . sub-address 71 : sync control (write/read) msb lsb register 71 non-inter vbi sw h-polarity v-polarity default : 0000_0100(bin) f-polarity h- delay2 h-delay1 h-delay0 non-inter : non-interlaced mode select 0 : interlace mode (default) 1 : non-interlace mode vbi sw : vertical blanking information signal input control switch on 34 pin 0 : vbi input off (default) 1 : vbi input on h-polarity : polarity of hsync 0 : negative (default) 1 : positive v-polarity : polarity of vsync 0 : negative (default) 1 : positive f-polarity : polarity of fsync 0 : field1 (odd) = low level (default) 1 : field1 (odd) = high level h-delay2 : delay on hsync with reference to dvia/dvib data in master mode h-delay1 000: + 4 clock delay h-delay0 001: + 3 clock delay 010: + 2 clock delay 011: + 1 clock delay 100: + 0 clock delay 101: - 1 clock delay 110: - 2 clock delay 111: - 3 clock delay note : this h-delay can be also related with 7a[7:0] register and can delay totally +2023 clock delay in h/v or h/fsync slave mode. 27
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . sub-address 72 : pal/ntsc setup (write / read) msb lsb register 72 phase-set c/fsync/vbi i/o sw color bar setup75 625/525 pal/ ntsc2 pal/ ntsc1 default : 0000_1000(bin) ntsc (if "pal/ntsc" pin is low level) 0000_0101(bin) pal test phase-set : color sub-carrier phase synchronization 0 : free running (default) 1 : 1 phase reset/8 field and 1 phase reset/4 frame test : for test, should be "0" c/fsync/vbi : input/output switch on 34 pin (c/fsync/vbi pin ) i/o sw 0 : vbi input(default) 1 : csync or frame sync output color bar : internal color bar generator control 0 : normal operation (default) 1 : color bar generator on (need to set color bar mode on sub-address 70[5]. ) setup75 : setup level for luminance 0 : setup level for luminance = 0ire 1 : setup level for luminance = 7.5ire 625/525 : control line mode 0 : 525 lines / 60 hz mode 1 : 625 lines / 50 hz mode pal/ntsc2 : subcarrier control pal/ntsc1 00 : ntsc(m) 01 : pal (bdghi) 10 : pal (m) 11 : pal (n) 28
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 29 sub-address 73: vertical blanking information luma (y) level (write only) msb lsb y7 y6 y5 y4 y3 y2 y1 y0 register 73 msb lsb v3 v2 v1 v0 v6 v5 v4 register 75 v7 sub-address 75: burst chroma (v) level (write only) default : 1000_0000(bin) msb lsb u7 u6 u5 u4 u3 u2 u1 u0 register 74 sub-address 74: burst chroma (u) level (write only) default : 77(dec) (ntsc) 89(dec) (pal) default : 128(dec) (ntsc) 155(dec) (pal)
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 30 sub-address 76 : dac set 1 signal control (write only) msb lsb register 76 cr cb luma dac 1pin default : 0000_0000(bin) dac 7pin dac 4pin cr : cr/cb signal control (data path enable) cb 0 : cr, cb on (default) 1 : chrominance off luma : luminance control (data path enable) 0 : luminance on (default) 1 : luminance off dac 1pin : d/a converter (1) output on-off control dac 4pin 0 : cvbs/cb dac, c/cr dac, y dac output on (default) dac 7pin 1 : cvbs/cb dac, c/cr dac, y dac output off dac set 1 mode : 1~9-pin's d/a converter output signal control 10 : y/cr/cb output on 00 : y/c/cvbs output on dac set 1 mode[0] sub-address 77 : reserved msb lsb register 77 - - -- - - - dac set 1 mode[1] -
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 31 sub-address 78~79 : sub-carrier phase control (write only) sc-ph9 : sub-carrier phase control sc-ph8 00_0000_0000 : sub-carrier phase 0 degree (default) sc-ph7 to sc-ph6 11_1111_1111 : sub-carrier phase 359 degree sc-ph5 sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0 msb lsb register 78 sc-ph9 sc-ph8 sc-ph7 sc-ph6 default : 0000_0000(bin) sc-ph5 msb lsb register 79 default : 0000_0000(bin) sc-ph4 sc-ph3 sc-ph2 sc-ph1 sc-ph0 --- - - -
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 32 sub-address 7b : digital video input select control (write only) msb lsb register 7b -- default : 0000_0000(bin) y_tmg cr_tmg : cr clock timing delay in 16-bit digital input mode 00 : cr clock delay 0 clock (default) 01 : cr clock delay +1 clock 10 : cr clock delay +2 clock 11 : cr clock delay +3 clock (see fig 3,4 ) cb_tmg : cb clock timing delay in 16-bit digital input mode 00 : cb clock delay 0 clock (default) 01 : cb clock delay +1 clock 10 : cb clock delay +2 clock 11 : cb clock delay +3 clock (see fig 3,4 ) y_tmg : y clock timing delay in 16-bit digital input mode 0 : y clock delay 0 clock (default) 1 : y clock delay +1 clock 16-bit : 16-bit yy / cbcr digital video input mode input mode 0 : 8-bit multiplexed cbycry digital video input mode (default) 1 : 16-bit yy / cbcr digital video input mode 16-bit input mode cb_tmg[0] h-delay10 : delay on hsync with reference to dvia/dvib data h-delay9 0000_0000_000 : hsync delay 0 delay h-delay8 to h-delay7 1111_1111_000 : hsync delay +255 delay h-delay6 h-delay5 h-delay4 h-delay3 note : this h-delay can be also related with 71[3:0] register and can delay totally +2023 delay(1111_1111_111) in h/v or h/fsync slave mode. sub-address 7a : hsync delay control (write only) msb lsb register 7a h-delay10 h-delay9 h-delay8 h-delay7 default : 0000_0000(bin) h-delay6 h-delay5 h-delay4 h-delay3 cb_tmg[1] cr_tmg[0] cr_tmg[1]
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 33 sub-address 7c : signal control 3(write only) y sync : y sync signal on/off (y/cb/cr mode only) 0 : y sync on (default) 1 : y sync off cbcr bf : cbcr burst on/off 0 : cb/cr bf data off 1 : cb/cr bf data on chroma bf : chroma burst on/off 0 : chroma bf data on 1 : chroma bf data off msb lsb register 7c ysync - - - default : 0000_0000(bin) - - cbcr bf chroma bf
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . v-delay9 : delay on vsync with reference to dvia/dvib data in slave mode v-delay8 0000_0000_00 : vsync delay 0 delay v-delay7 to v-delay6 1111_1111_11 : hsync delay +1023 delay v-delay5 v-delay4 v-delay3 v-delay2 v-delay1 v-delay0 34 sub-address 7d~7e : vsync delay control (write only) msb lsb register 7d v-delay7 v-delay6 v-delay5 v-delay4 default : 0000_0000(bin) v-delay3 v-delay2 v-delay1 v-delay0 msb lsb register 7e -- - - default : 0000_0000(bin) - - v-delay9 v-delay8
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . msb lsb xx xx xx register 82 sub-address 80~82: cgms characters for field1(line20)/field2(line283) (write only) ntsc only msb lsb cgms7 cgms6 cgms5 cgms4 cgms3 cgms2 cgms1 cgms0 msb lsb register 80 register 81 b8 b7 b6 b5 b4 b3 b2 b1 b16 b15 b14 b13 b12 b11 b10 b9 b20 b19 b18 b17 xx 2.235 m s 49.1 m s b1 ref b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 70ire 0ire -40ire fig 20 : cgms wave form 35 fig 21 : wss wave form 11.0 m s 27.4 m s 38.4 m s 44.5 m s sub-address 80~81: wss characters for line23 (write only) pal only msb lsb wss7 wss6 wss5 wss4 wss3 wss2 wss1 wss0 msb lsb -- wss13 wss12 wss11 wss10 wss9 wss8 register 80 register 81 b8 b7 b6 b5 b4 b3 b2 b1 b16 b15 b14 b13 b12 b11 b10 b9 500mv cgms15 cgms14 cgms13 cgms12 cgms11 cgms10 cgms9 cgms8 cgms19 cgms18 cgms17 cgms16 11.2 m s
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . sub-address 83~84 :closed caption characters/extended data for field1(line21) (write) first byte to encode register 83 register 84 ccp118 ccb117 ccb116 ccb115 ccb114 ccb113 ccb112 ccb111 ccp128 ccb127 ccb126 ccb125 ccb124 ccb123 ccb122 ccb121 msb lsb msb lsb second byte to encode parity b7 b6 b5 b4 b3 b2 b1 parity b7 b6 b5 b4 b3 b2 b1 register 85 register 86 ccp218 ccb217 ccb216 ccb215 ccb214 ccb213 ccb212 ccb211 ccp228 ccb227 ccb226 ccb225 ccb224 ccb223 ccb222 ccb221 msb lsb msb lsb sub-address 85~86 :closed cation character/extended data for field2(line284) first byte to encode second byte to encode parity b7 b6 b5 b4 b3 b2 b1 parity b7 b6 b5 b4 b3 b2 b1 36 10.50 m s 12.91 m s 4.15 m s 33.764 m s b 1 b 2 b 3 b 4 b 5 b 6 b 7 p a r i t y b 1 b 2 b 3 b 4 b 5 b 6 b 7 p a r i t y character1 character2 50ire 0ire 50ire 0ire -40ire fig 22 : closed caption wave form fsync sub-address 80, 81, 82, 83, 84, 85 and 86 (previous frame data) are double-buffered by frame sync falling edge field 1 field 2 fig 23 : vbi data update timing note : this closed caption wafeform is defined by when the register $72 [3] = "1" is set
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 37 sub-address 87 :closed caption / cgms / wss msb lsb register 87 cc2_flag cc1_flag cc_null wss cgms cc2 cc1 cc2_flag : closed caption status flag for field2/field1 ( read only) cc1_flag 0 : automatically set to " 1 " when 2-byte closed caption data are written, and then cleared to "0" when the data is send to doubled buffer 1 : do not work " 1 " to these bits. " 0 " is correct. cc_null : automatically set the null code when the data is send to doubled buffer 0 : keep the current cc data in the resister. 1 : automatically set the null code in the cc data resister cc_parity: cc parity generation on-off 0 : use parity bit in data. (default) 1 : automatically generate parity bit. wss : wss information data insertion on-off 0 : wss information data insertion off 1 : wss information data insertion on cgms : cgms information data insertion on-off 0 : cgms information data insertion off 1 : cgms information data insertion on cc2 : closed caption/extended data for field2 encoding on-off 0 : closed caption/extended data for field2 encoding off 1 : closed caption/extended data for field2 encoding on cc1 : closed caption/extended data for field1 encoding 0 : closed caption/extended data for field1 encoding off 1 : closed caption/extended data for field1 encoding on default 00h cc_parity sub-address 88 :cgms/wss parity generation on-off msb lsb register 88 -- - wss_parity cgms_parity -- default 00h - wss_parity cgms_parity :wss/cgms parity generation on-off 0 : use parity bit in data. (default) 1 : automatically generate parity bit. '
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 38 6eh[7:4] n.a. 6eh[3] cb/cr gain control 6eh[2] y mode switch 6eh[1:0] m2/beta cam select 6f[7] n.a. 6f[6:0] interpolation filter switch 70h:[7] burst control (default 0:on) [6] self counter reset switch (default 0:off) [5] color bar select (default 0:luma 100% chroma 75%) [4] vertical blanking switch(default 0:off) [3] 34 pin output mode select (csync:1, flame sync:0) [2] f/vsync select(default 0:vsync) [1:0] master/slave mode select(default 01:656_slave) 71h:[7] interlaced / non-interlaced (default 0:interlaced) [6] vbi input control on 34 pin (default 0:off) [5] horizontal sync polarity (default 0) [4] vertical sync polarity (default 0) [3] frame sync polarity (default 0) [2:0] hsync delay control (default 100:0 clock delay) (in slave mode can use with 7a[7:0]) 72h:[7] sub-carrier phase synchronization(default 0) [6] test mode (default 0:off) [5] 34 pin i/o switch(default 1:cysnc output) [4] color bar generate(default 0:off) [3] setup level control(default 1:7.5ire) [2] 625lines50hz/525lines60hz (default set pal/ntsc pin) [1:0] pal/ntsc (default set pal/ntsc pin) 00:ntsc/m 01:pal/bdghi (10:pal/m) (11:pal/n) 73h[7:0] vbi luma level register(default 80h) 74h[7:0] burst u_register(default 77d:ntsc/89d:pal) 75h[7:0] burst v_register(default 128d:ntsc/155d:pal) 76h[7] cr on/off (default 0:on) [6] cb on/off (default 0:on) [5] luma on/off(default 0:on) (default 0: on) [4:2] 1pin dac/4pin dac/7pin dac on/off(default 0: on) [1:0] d/a converter output signal control (default 00 : cbvs/y/c output) 77h[7:0] reserved 78h[7:0] sub-carrier phase control(default 00h) 79h[1:0] sub-carrier phase control(default 00) 79h[7:2] n.a. 7a[7:0] hsync-delay control (in slave mode, is valid with 71h[2:0] register) 7b[7:6] n.a.. [5:2] cr/cb clock timing delay in 16-bit digital input mode (default 00: clock delay 0) [1] y clock timing delay in 16-bit digital input mode (default 0: clock delay 0) [0] 16-bit multiplexed cbycry digital video input mode (default 0: 8-bit ycrcb digital video input mode) 7c[7] ysync signal on/off(ycrcb mode only)(default 0: on) [6:1] n.a. [0] chroma burst on/off(default 0: on) 7d[7:0] delay on vsync with reference to dvia/dvib data in slave mode 7e[7:2] n.a. [1:0] delay on vsync with reference to dvia/dvib data in slave mode 80~82h cgms characters for field1(line20)/field2(line283) 80~81h wss characters for field1(line23) 83h[7:0] cc character1(line21) (default 'h80) 84h[7:0] cc character2(line21) (default 'h80) 85h[7:0] cc character1(line284) (default 'h80) 86h[7:0] cc character2(line284) (default 'h80) 87h[7:6] closed caption status flag for field2 [5] automatic set to null code(closed caption data) [4] automatic generate cc parity bit (default 0: off) [3] wss information data insertion on/off (default 0: off) [2] cgms on/off (default 0: off) [1] cc closed caption/extended data for field2 encoding (default 0: off) [0] cc closed caption/extended data for field1 encoding (default 0: off) 88h[7:2] reserved [1] wss_parity generation on-off [0] cgms_parity generation on-off i2c-bus slave receiver sub-address map ** write mode ** s | slave_address(w) | a | sub_address | a | data0 | a | ... | datan | a | p s start condition slave_address 42(hex) or 1c(hex) a acknowledge generated by dve sub_address sub_address register data0 first data datan continued data(address is auto incremented) p stop condition <<<<<<<< spi-bus format >>>>>> ** write mode ** s | write command | sub_address | data0 | ... | datan | p s chip select on (high to low) write command 43(hex) or 1d(hex) sub_address sub_address byte data0 first data datan continued data byte(address is auto incremented) p chip select off (low to high) <<<<<<<< i2c-bus format >>>>>>
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . [ application diagram 1 ] 39 cvbs/cb hsync c/fsync/vbi vmute dvia3 dvia4 dvia5 dvia6 dvia7 a/b_sel dvib7 dvib6 dvib5 dvib4 dvss dvdd dvib3 MC44722A/3a 1 2 3 4 5 6 7 8 9 12 14 15 16 17 18 19 20 21 vreff 13 24 22 10 11 36 35 34 33 32 31 30 29 28 25 27 26 23 47 46 45 44 43 42 41 40 48 37 39 38 cvbs/cb cvbs/cbvdd y y yvdd c/cr c/cr c/crvdd davss ibias davdd chipa test so sda/si scl/sck sel dvss clock dvdd reset pal/ntsc dvia0 dvia1 dvia2 f/vsync dvin2 dvib1 dvib0 tp mpeg decoder dvdd 47uf 0.01uf dvdd 47uf 0.01uf clock 10uf 100k if ntsc system = "0" else pal system = "1" mcu 47uf 0.01uf 4.7k 4.7k 1.8k 47uf 0.01uf 180 180 180 47uf 0.01uf 47uf 0.01uf 47uf 0.01uf 180 cvbs 180 y 180 c 0.01uf 1k 2k
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . [ application diagram 2 ] 40 cvbs/cb hsync dvss dvdd MC44722A/3a 1 2 3 4 5 6 7 8 9 12 14 15 16 17 18 19 20 21 vreff 13 24 22 10 11 36 35 34 33 32 31 30 29 28 25 27 26 23 47 46 45 44 43 42 41 40 48 37 39 38 cvbs/cb cvbs/cbvdd y y yvdd c/cr c/cr c/crvdd davss ibias davdd chipa test so sda/si scl/sck sel dvss clock dvdd reset pal/ntsc f/vsync mpeg decoder dvdd 47uf 0.01uf dvdd 47uf 0.01uf clock 10uf 100k if ntsc system = "0" else pal system = "1" mcu 47uf 0.01uf 4.7k 4.7k 1.8k 47uf 0.01uf 180 180 180 47uf 0.01uf 47uf 0.01uf 47uf 0.01uf 180 cvbs 180 y 180 c 0.01uf 1k 2k *oqvutfmfdutx %7*"<> %7*#<> other decoder or osd c/fsync/vbi vmute dvia3 dvia4 dvia5 dvia6 dvia7 dvia0 dvia1 dvia2 a/b_sel dvib7 dvib6 dvib5 dvib4 dvib3 dvin2 dvib1 dvib0 tp
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . 41 48-pin qfp package (0.8mm pitch) a detail a zd or ze min max a a1 a2 b c d e e hd he l l1 y zd ze - 1.70 0.05 0.15 1.40typ 0.3 0.10 11.90 11.90 13.80 13.80 0.30 0.80 0 - 1.60 1.60 0.45 0.20 12.10 12.10 0.80 14.20 14.20 0.70 1.20 10 0.10 a1 a2 e b he e hd d l1 l c detail a unit : mm
MC44722A/3a rev 0.05 07/15/98 no. this document contains information on a new product. specifications and information herein are subject to change without notice . unit mm a min max a a1 a2 b c d e e hd he l l1 y zd ze - 2.00 0.00 0.25 1.4typ 0.14 0.05 6.80 6.80 8.80 8.80 0.30 0.80 0 - 0.75 0.75 0.30 0.20 7.20 7.20 0.50 9.20 9.20 0.70 1.20 10 0.10 a a zd or ze a1 a2 e b he e hd d l1 l c 48-pin vqfp package (0.5mm pitch) 42

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