philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor features symbol quick reference data ? dual device v ds = 25 v ? low threshold voltage ? fast switching i d = 6.3 a ? logic level compatible ? surface mount package r ds(on) 30 m w (v gs = 10 v) r ds(on) 55 m w (v gs = 4.5 v) general description pinning sot96-1 n-channel enhancement mode pin description field-effect power transistor in a plastic envelope using ' trench ' 1 source 1 technology. the device has very low on-state resistance. it is 2 gate 1 intended for use in dc to dc converters and general purpose 3 source 2 switching applications. 4 gate 2 the PHN203 is supplied in the sot96-1 (so8) surface mounting 5,6 drain 2 package. 7,8 drain 1 limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v ds repetitive peak drain-source t j = 25 ?c to 150?c - 25 v voltage v ds continuous drain-source voltage - 25 v v dgr drain-gate voltage r gs = 20 k w -25v v gs gate-source voltage - 20 v i d drain current per mosfet 1 t a = 25 ?c - 6.3 a t a = 70 ?c - 5 a i d drain current per mosfet (both t a = 25 ?c - 4.4 a mosfets conducting) 1 t a = 70 ?c - 3.5 a i dm drain current per mosfet (pulse t a = 25 ?c - 25 a peak value) p tot total power dissipation (either or t a = 25 ?c - 2 w both mosfets conducting) 1 t a = 70 ?c - 1.3 w t stg , t j storage & operating temperature - 55 150 ?c d1 g1 s1 d1 d2 g2 d2 s2 12 34 5 6 7 8 pin 1 index 1 surface mounted on fr4 board, t 10 sec january 1999 1 rev 1.000
philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor thermal resistances symbol parameter conditions typ. max. unit r th j-a thermal resistance junction surface mounted on fr4 board, t 10 - 62.5 k/w to ambient sec; either or both mosfets conducting r th j-a thermal resistance junction surface mounted on fr4 board; either or 150 - k/w to ambient both mosfets conducting avalanche energy limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit e as non-repetitive avalanche unclamped inductive load, i as = 6.3 a; - 20 mj energy (per mosfet) t p = 0.2 ms; t j prior to avalanche = 25?c; v dd 15 v; r gs = 50 w ; v gs = 10 v i as non-repetitive avalanche - 6.3 a current (per mosfet) electrical characteristics t j = 25?c, per mosfet unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 10 m a; 25 - - v voltage t j = -55?c 22.5 - - v v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1 2 2.8 v t j = 150?c 0.4 - - v t j = -55?c - 3.2 v r ds(on) drain-source on-state v gs = 10 v; i d = 4 a - 27 30 m w resistance v gs = 4.5 v; i d = 2 a - 40 55 m w v gs = 10 v; i d = 4 a; t j = 150?c - 43 51 m w g fs forward transconductance v ds = 20 v; i d = 4 a 5 9.7 - s i dss zero gate voltage drain v ds = 20 v; v gs = 0 v; - 60 100 na current v ds = 20 v; v gs = 0 v; t j = 150?c - 0.1 10 m a i gss gate source leakage current v gs = 20 v; v ds = 0 v - 10 100 na q g(tot) total gate charge i d = 4 a; v dd = 20 v; v gs = 10 v - 20 - nc q gs gate-source charge - 1.9 - nc q gd gate-drain (miller) charge - 6.1 - nc t d on turn-on delay time v dd = 20 v; r d = 18 w ;-8-ns t r turn-on rise time v gs = 10 v; r g = 6 w -11-ns t d off turn-off delay time resistive load - 31 - ns t f turn-off fall time - 17 - ns l d internal drain inductance measured from drain lead to centre of die - 2.5 - nh l s internal source inductance measured from source lead to source - 5 - nh bond pad c iss input capacitance v gs = 0 v; v ds = 20 v; f = 1 mhz - 611 - pf c oss output capacitance - 260 - pf c rss feedback capacitance - 137 - pf january 1999 2 rev 1.000
philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor reverse diode limiting values and characteristics t j = 25?c, per mosfet unless otherwise specified symbol parameter conditions min. typ. max. unit i s continuous source diode t a = 25 ?c - - 2.85 a current (per mosfet) i sm pulsed source diode current - - 25 a (per mosfet) v sd diode forward voltage i f = 1.25 a; v gs = 0 v - 0.75 1 v t rr reverse recovery time i f = 1.25 a; -di f /dt = 100 a/ m s; - 35 - ns q rr reverse recovery charge v gs = 0 v; v r = 25 v - 24 - nc fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t a ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t a ); conditions: v gs 3 4.5 v fig.3. safe operating area. t a = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance; z th j-a = f(t); parameter d = t p /t normalised power dissipation, pd (%) 0 20 40 60 80 100 120 0 25 50 75 100 125 150 ambient temperature, ta (c) PHN203 0.01 0.1 1 10 100 0.1 1 10 100 drain-source voltage, vds (v) peak pulsed drain current, idm (a) 10 s 100 ms 10 ms rds(on) = vds/ id 1 ms tp = 10 us 100 us normalised drain current, id (%) 0 20 40 60 80 100 120 0 25 50 75 100 125 150 ambient temperature, ta (c) PHN203 0.01 0.1 1 10 100 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 1e+00 1e+01 pulse width, tp (s) peak pulsed drain current, idm (a) single pulse d = 0.5 0.2 0.1 0.05 0.02 tp d = tp/t d p t january 1999 3 rev 1.000
philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ); parameter v gs fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ); parameter v gs fig.7. typical transfer characteristics. i d = f(v gs ) fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ) fig.9. normalised drain-source on-state resistance. r ds(on) /r ds(on)25 ?c = f(t j ) fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs PHN203 0 1 2 3 4 5 6 7 8 9 10 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 drain-source voltage, vds (v) drain current, id (a) 2.6 v 2.8 v 3 v 3.6 v tj = 25 c vgs = 5 v 3.2 v 3.4 v 10v PHN203 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 012345678910 drain current, id (a) transconductance, gfs (s) vds > id x rds(on) tj = 25 c 150 c PHN203 0 0.1 0.2 0.3 0.4 0.5 012345678910 drain current, id (a) drain-source on resistance, rds(on) (ohms) vgs =5 v 2.6v 2.8v 3.4v 10v tj = 25 c 3.6v 3.2 v 3 v -50 0 50 100 150 0 0.5 1 1.5 2 sot223 30v trench tj / c a normalised rds(on) = f(tj) PHN203 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 gate-source voltage, vgs (v) drain current, id (a) vds > id x rds(on) tj = 25 c 150 c -60 -40 -20 0 20 40 60 80 100 120 140 tj / c vgs(to) / v 4 3 2 1 0 max. typ. min. january 1999 4 rev 1.000
philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ) fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. maximum permissible non-repetitive avalanche current (i as ) versus avalanche time (t p ); unclamped inductive load 012345 1e-06 1e-05 1e-04 1e-03 1e-02 1e-01 sub-threshold conduction typ min max PHN203 0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 drain-source voltage, vsds (v) source-drain diode current, if (a) tj = 25 c 150 c vgs = 0 v PHN203 100 1000 10000 0.1 1 10 100 drain-source voltage, vds (v) capacitances, ciss, coss, crss (pf) ciss coss crss PHN203 1 10 1e-06 1e-05 1e-04 1e-03 1e-02 avalanche time, tp (s) non-repetitive avalanche current, ias (a) 25 c vds id tp tj prior to avalanche =125 c PHN203 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 5 10 15 20 25 30 gate charge, qg (nc) gate-source voltage, vgs (v) id = 4a tj = 25 c vdd = 20 v january 1999 5 rev 1.000
philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor mechanical data fig.16. sot96 surface mounting package. notes 1. this product is supplied in anti-static packaging. the gate-source input must be protected against static discharge during transport or handling. 2. refer to integrated circuit packages, data handbook ic26. 3. epoxy meets ul94 v0 at 1/8". unit a max. a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 0.25 dimensions (inch dimensions are derived from the original mm dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.4 sot96-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 4 5 pin 1 index 1 8 y 076e03s ms-012aa 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.20 0.19 0.16 0.15 0.050 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.01 0.041 0.004 0.039 0.016 0 2.5 5 mm scale so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1 95-02-04 97-05-22 january 1999 6 rev 1.000
philips semiconductors product specification dual n-channel enhancement mode PHN203 trenchmos tm transistor definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1999 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. january 1999 7 rev 1.000
|
