integrated circuit systems, inc. ICS93701 0417b?10/29/02 block diagram ddr phase lock loop clock driver pin configuration 48-pin tssop recommended application: ddr clock driver product description/features: low skew, low jitter pll clock driver i 2 c for functional and output control feedback pins for input to output synchronization spread spectrum tolerant inputs switching characteristics: peak - peak jitter (66mhz): <120ps peak - peak jitter (>100mhz): <75ps cycle - cycle jitter (66mhz):<120ps cycle - cycle jitter (>100mhz):<65ps output - output skew: <100ps duty cycle: 49.5% - 50.5% slew rate: 1v/ns - 2v/ns gnd clkc0 clkt0 vdd clkt1 clkc1 gnd gnd clkc2 clkt2 vdd sclk clk_int clk_inc avdd agnd gnd clkc3 clkt3 vdd clkt4 clkc4 gnd vddi c 2 gnd clkc5 clkt5 vdd clkt6 clkc6 gnd gnd clkc7 clkt7 vdd sdata fb_inc vdd fb_outt gnd clkc8 clkt8 vdd clkt9 clkc9 gnd fb_int fb_outc ICS93701 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 functionality s t u p n is t u p t u o e t a t s l l p d d v at n i _ k l cc n i _ k l ct k l cc k l ct t u o _ b fc t u o _ b f v 5 . 2 ) m o n ( lhlhlh n o v 5 . 2 ) m o n ( hlhlhl n o v 5 . 2 ) m o n ( ) z h m 0 2 < ) 1 ( zz z z f f o pll fb_int fb_inc clk_inc clk_int sclk s data control logic fb_outt fb_outc clkt0 clkt1 clkt2 clkt3 clkt4 clkt5 clkt6 clkt7 clkt8 clkt9 clkc0 clkc1 clkc2 clkc3 clkc4 clkc5 clkc6 clkc7 clkc8 clkc9
2 ICS93701 0417b?10/29/02 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d , 5 2 , 4 2 , 8 1 , 8 , 7 , 1 8 4 , 2 4 , 1 4 , 1 3 d n gr w pd n u o r g , 7 4 , 3 4 , 0 4 , 0 3 , 6 2 2 , 6 , 9 , 9 1 , 3 2 ) 0 : 9 ( c k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o s k c o l c " y r a t n e m e l p m o c " , 6 4 , 4 4 , 9 3 , 9 2 , 7 2 3 , 5 , 0 1 , 0 2 , 2 2 ) 0 : 9 ( t k l ct u o. s t u p t u o r i a p l a i t n e r e f f i d f o k c o l c " e u r t " , 8 2 , 1 2 , 1 1 , 4 , 5 4 , 8 3 , 4 3 d d vr w pv 5 . 2 y l p p u s r e w o p 2 1k l c sn ii f o t u p n i k c o l c 2 t u p n i t n a r e l o t v 5 , t u p n i c 3 1t n i _ k l cn it u p n i k c o l c e c n e r e f e r " e u r t " 4 1c n i _ k l cn it u p n i k c o l c e c n e r e f e r " y r a t n e m e l p m o c " 5 1i d d v 2 cr w pi r o f r e w o p v 3 . 3 2 c 6 1d d v ar w pv 5 . 2 , y l p p u s r e w o p g o l a n a 7 1d n g ar w p. d n u o r g g o l a n a 2 3c t u o _ b ft u o t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " y r a t n e m e l p m o c " d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a s e h c t i w s . c n i _ b f o t 3 3t t u o _ b ft u o s e h c t i w s t i . k c a b d e e f l a n r e t x e r o f d e t a c i d e d , t u p t u o k c a b d e e f " " e u r t " o t d e r i w e b t s u m t u p t u o s i h t . k l c e h t s a y c n e u q e r f e m a s e h t t a . t n i _ b f 5 3t n i _ b fn i r o f l l p l a n r e t n i e h t o t l a n g i s k c a b d e e f s e d i v o r p , t u p n i k c a b d e e f " e u r t " . r o r r e e s a h p e t a n i m i l e o t t n i _ k l c h t i w n o i t a z i n o r h c n y s 6 3c n i _ b fn i l l p l a n r e t n i e h t o t l a n g i s s e d i v o r p , t u p n i k c a b d e e f " y r a t n e m e l p m o c " . r o r r e e s a h p e t a n i m i l e o t c n i _ k l c h t i w n o i t a z i n o r h c n y s r o f 7 3a t a d sn ii r o f t u p n i a t a d 2 t u p n i t n a r e l o t v 5 , t u p n i l a i r e s c
3 ICS93701 0417b?10/29/02 byte 0: output control (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b0 3 , 9 21 8 c k l c , 8 t k l c 6 t i b6 2 , 7 21 9 c k l c , 9 t k l c 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r byte 1: output control (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r byte 3: reserved (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r byte 4: reserved (1= enable, 0 = disable) byte 2: reserved (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r byte 5: reserved (1= enable, 0 = disable) note: don?t write into this register, writing into this register can cause malfunction t i b# n i pd w pn o i t p i r c s e d 7 t i b2 , 31 0 c k l c , 0 t k l c 6 t i b6 , 51 1 c k l c , 1 t k l c 5 t i b9 , 0 11 2 c k l c , 2 t k l c 4 t i b9 1 , 0 21 3 c k l c , 3 t k l c 3 t i b3 2 , 2 21 4 c k l c , 4 t k l c 2 t i b7 4 , 6 41 5 c k l c , 5 t k l c 1 t i b3 4 , 4 41 6 c k l c , 6 t k l c 0 t i b0 4 , 9 31 7 c k l c , 7 t k l c
4 ICS93701 0417b?10/29/02 absolute maximum ratings supply voltage (vdd & avdd). . . . . . . . . . . -0.5v to 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd + 0.5 v ambient operating temperature . . . . . . . . . . 0c to +85c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input / supply / common output parameters t a = 0 - 85 o c; supply voltage a vdd , v dd = 2.5v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units input high current i ih v in = v dd or gnd 5a input low current i il v in = v dd or gnd 5a i dd2.5 cl = 0pf @ 100mhz 185 210 ma i ddpd cl = 0pf @ 100mhz 0.15 100 ma output high current i oh v dd = 2.3v, v out = 1v -18 -32 ma output low current i ol v dd = 2.3v, v out = 1.2v 26 35 ma input clamp voltage v ik v ddq = 2.3v i in = -18ma -1.2 v v dd = min to max, i oh = -1 ma v ddq = 2.3v, i oh = -12 ma v dd = min to max i ol =1 ma v ddq = 2.3 v i ol =12 ma input capacitance 1 c in v in = gnd or v dd 3pf output capacitance 1 c out v out = gnd or v dd 3pf 1 guaranteed by design, not 100% tested in production. operating supply current high impedance output current i oz v dd =2.7v, v out =v dd or gnd 0.1 10 a 0.6 v ol low-level output voltage high-level output voltage v oh v ddq - 0.1 1.7 v v 0.05 2.45 v v 0.35 0.1 2.10
5 ICS93701 0417b?10/29/02 recommended operating condition (see note1) t a = 0 - 85 o c; supply voltage a vdd , v dd = 2.5v +/- 0.2v (unless otherwise stated) parameter symbol conditions min typ max units v ddq , a vdd 2.3 2.5 2.7 v ddi2c 2.3 3.6 v v il -0.3 0 v dd -0.4 v v ih 0.4 0.71 v dd +0.3 v dc - clkt, fb_int 0.36 v ddq +0.6 v ac - clkt, fb_int 0.5 v ddq +0.6 v output differential crossing voltage v ox v ddq /2 -0.2 1.25 v ddq /2 +0.2 v 1 differential input signal voltage specifies the differential voltage [v tr - v cp ] required for switching, where v tr is the true input level and v cp is the complementary input level. input voltage level analog/core supply voltage input differential-pair voltage swing 1 v id v input differential crossing voltage v ix 0.45x(v ih -v il )0.55x(v ih -v il ) timing requirements t a = 0 - 85 o c; supply voltage a vdd , v dd = 2.5v +/- 0.2v (unless otherwise stated) parameter symbol conditions min max units max clock frequency freq op 2.5v+0.2v @ 25 o c 33 270 mhz application frequency range freq app 2.5v+0.2v @ 25 o c 60 170 mhz input clock duty cycle d tin 40 60 % from v dd = 3.3v to 1% target freq. 100 s clk stabilization t stab
6 ICS93701 0417b?10/29/02 switching characteristics parameter symbol condition min typ max units low-to high level propagation delay time high-to low level propagation delay time output enable time t en pd# to any output 3 ns output disable time tdis pd# to any output 3 ns period jitter 100/133/166mhz -40 25 40 ps half-period jitter t(jit_hper) 100/133/166mhz -120 50 100 ps cycle to cycle jitter1 t cyc- t cyc 100/133/166mhz 30 65 ps phase error t (phase error) 100/133/166mhz -150 -100 150 ps output to output skew t skew 60 100 ps pulse skew t skewp 60 100 ps 66mhz to 100mhz 49.5 50 50.5 % 101mhz to 133mhz 48.5 49 50 % 135mhz to 167mhz 48.5 49 50 % slew rate t slew load = 120 ? /14pf 11.92 ps notes: 1. refers to transition on noninverting outputs in pll bypass mode. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at high frequencies. this is due to the formula: duty cycle=t wh /t c , where the cycle (t c ) decreases as the frequency goes up. duty cycle dc 2 3.5 t phl 1 clk_in to any output 3.5 t plh 1 clk_in to any output ns ns
7 ICS93701 0417b?10/29/02 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends a dummy command code ics clock will acknowledge controller (host) sends a dummy byte count ics clock will acknowledge controller (host) starts sending first byte (byte 0) through byte 5 ics clock will acknowledge each byte one at a time . controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the byte count controller (host) acknowledges ics clock sends first byte (byte 0) through byte 5 controller (host) will need to acknowledge each byte controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to write:
8 ICS93701 0417b?10/29/02 recommended layout for the ICS93701 general layout precautions: use copper flooded ground on the top signal layer under the clock buffer the area under u1 on the right is an example. flood over the ground vias. 1) use power vias for power and ground. vias 20 mil or larger in diameter have lower high frequency impedance. vias for signals may be minimum drill size. 2) make all power and ground traces are as wide as the via pad for lower inductance. 3) vaa for pin 16 has a low pass rc filter to decouple the digital and analog supplies. the 4.7uf capacitors may be replaced with a single low esr device with the same total capacitance. vaa is routed on a outside signal layer. do not cut a power or ground plane and route in it. 4) notice that ground vias are never shared. 5) when ever possible, vcc (net v2p5 in the schematic) pins have a decoupling capacitor. power is always routed from the plane connection via to the capacitor pad to the vcc pin on the clock buffer. moats or plane cuts are not used to isolate power. 6) differential mode clock output traces are routed: a. with a ground trace between the pairs. trace is grounded on both ends. b. without a ground trace, clock pairs are routed with a separation of at least 5 times the thickness of the dielectric. if the dielectric thickness is 4.5 mil, the trace separation is at least 18 mils. component values: ref desg. value description package c1,c4,c5, c7,c11,c12 .01uf ceramic mlc 0603 c2,c3,c8, c9 4.7uf ceramic mlc 1206 c10 .22uf ceramic mlc 0603 c6 2200pf ceramic mlc 0603 r12 120 ? 0603 r9 4.7 ? 0603 u1 ICS93701ag tssop48 c2 4.7uf 1 2 v2p5 fb_in# c3 4.7uf 1 2 v2a5 c9 4.7uf 1 2 c7 .01uf 1 2 v2p5 c16 .01uf 1 2 c10 .22uf 1 2 c1 .01uf 1 2 c5 .01uf 1 2 c11 .01uf 1 2 r12 120 1 2 v2a5 v2a5 clk_in# u1 ICS93701 16 4 11 15 21 28 34 38 45 1 7 8 18 24 25 31 41 42 48 17 35 36 13 14 37 12 3 2 5 6 10 9 20 19 22 23 46 47 44 43 39 40 29 30 27 26 33 32 avdd vdd vdd vdd vdd vdd vdd vdd vdd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd agnd fb_int fb_inc clk_int clk_inc sda scl clkt0 clkc0 clkt1 clkc1 clkt2 clkc2 clkt3 clkc3 clkt4 clkc4 clkt5 clkc5 clkt6 clkc6 clkt7 clkc7 clkt8 clkc8 clkt9 clkc9 fb_outt fb_outc c12 .01uf 1 2 c6 .0022pf 1 2 scl r9 4.7 1 2 c13 .01uf 1 2 sda c14 .01uf 1 2 fb_in c8 4.7uf 1 2 c15 .01uf 1 2 clk_in c4 .01uf 1 2
9 ICS93701 0417b?10/29/02 ordering information ICS93701 y gt designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type g = tssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y g - ppp - t index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimension s see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153
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