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M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers description these are single-chip microcomputers designed with high-perfor- mance cmos silicon gate technology, including the internal flash memory. these are housed in 100-pin plastic molded qfp. these microcomputers support the 7900 series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 series instruction set. the cpu of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. these microcomputers include the 4-channel dma controller and the dram controller. therefore, these microcomputers are suitable for office, business, and industrial equipment controller that require fast processing of large data. for the internal flash memory, single-power-supply programming and erasure, using a prom programmer or the control by the cen- tral processing unit (cpu), is supported. also, each of these micro- computers has the memory area dedicated for storing a certain software which controls programming and erasure (reprogramming control software). therefore, on these microcomputers, the program can easily be changed even after they are mounted on the board. distinctive features number of basic machine instructions .................................... 203 memory [M37920FCCGP, m37920fcchp] flash memory (user rom area) ................................. 120 kbytes ram ............................................................................. 4096 bytes [m37920fgcgp, m37920fgchp] flash memory (user rom area) ................................. 248 kbytes ram ............................................................................. 6144 bytes [all of the above computers] flash memory (boot rom area) ................................... 16 kbytes instruction execution time the fastest instruction at 20 mhz frequency ........................ 50 ns single power supply .................................................... 5 v ?0.5 v interrupts ........... 6 external sources, 20 internal sources, 7 levels multi-functional 16-bit timer ................................................... 5 + 3 serial i/o (uart or clock synchronous) ..................................... 2 10-bit a-d converter ............................................ 4-channel inputs dma controller .............................................................. 4 channels dram controller real-time output .... 4 bits 2 channels, or 6 bits 1 channel + 2 bits 1 channel 12-bit watchdog timer programmable input/output (ports p0?12) .............................. 85 power supply voltage .................................................. 5 v ?0.5 v programming/erase voltage ........................................ 5 v ?0.5 v programming method ............ programming in a unit of 256 bytes erase method ............................................ block erase or total erase (data protection per block is enabled.) programming/erase control by software command maximum number of reprograms ............................................ 100 application control devices for personal computer peripheral equipment such as cd-rom drives, dvd-rom drives, hard disk drives, high density fdd, printers control devices for office equipment such as copiers and facsimiles control devices for industrial equipment such as communication and measuring instruments
preliminar y notice: this is not a final specification. some parametric limits are subject to change. M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 2 outline 100p6s-a m37920fxcgp pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p6 6 /dmareq 3 ? p6 5 /ta4 in /dmareq 2 ? p6 4 /ta4 out /dmaack 2 ? p6 0 /ta1 out /dmaack 0 ? p5 7 /ta2 in /rtp1 3 ? p5 6 /ta2 out /rtp1 2 ? p5 5 /rtp1 1 ? p5 4 /rtp1 0 ? p5 3 /rtp0 3 ? p5 2 /rtp0 2 ? p5 1 /ta0 in /rtp0 1 ? p5 0 /ta0 out /rtp0 0 ? p9 6 /wrh/ucas ? p9 5 /wrl/lcas ? p9 4 /cas/w ? p9 3 /cs 3 /ras 3 ? p9 2 /cs 2 /ras 2 ? p9 1 /cs 1 /ras 1 ? p9 0 /cs 0 ? p4 4 /hlda ? p4 3 /hold ? p4 2 /tc ? p4 1 / 1 ? p4 0 /ale ? p3 3 /bhw ? p3 2 /blw ? p3 1 /rd ? 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p6 3 /ta3 in /dmareq 1 ? p6 2 /ta3 out /dmaack 1 ? p6 1 /ta1 in /dmareq 0 ? ? p3 0 /rdy byte nmi reset md0 v ss x in x out v cc ? p2 7 /d 15 ? p2 6 /d 14 ? p2 5 /d 13 ? p2 4 /d 12 ? p2 3 /d 11 ? p2 2 /d 10 ? p2 1 /d 9 ? p2 0 /d 8 ? p1 7 /d 7 ? p1 4 /d 4 ? p1 3 /d 3 ? p1 2 /d 2 ? p1 1 /d 1 ? p1 0 /d 0 md1 v ss ? p0 7 /a 23 ? p0 6 /a 22 /ma 11 ? p0 5 /a 21 ? p0 4 /a 20 /ma 10 ? p0 3 /a 19 ? p0 2 /a 18 /ma 9 ? p0 1 /a 17 ? p0 0 /a 16 /ma 8 ? p11 7 /a 15 /ma 7 ? p11 6 /a 14 /ma 6 ? p11 5 /a 13 /ma 5 ? p11 4 /a 12 /ma 4 ? p11 3 /a 11 /ma 3 ? p11 2 /a 10 /ma 2 ? p11 1 /a 9 /ma 1 ? p11 0 /a 8 /ma 0 ? p10 7 /a 7 ? p10 6 /a 6 ? p10 5 /a 5 ? p10 4 /a 4 ? p10 3 /a 3 ? p10 2 /a 2 ? p10 1 /a 1 ? p1 6 /d 6 ? p1 5 /d 5 p10 0 /a 0 ? p8 6 /clk 0 ? p8 5 /r x d 0 ? p8 4 /t x d 0 ? p8 3 /cts 0 /rts 0 ? p8 2 /cts 0 /clk 1 ? p8 1 /r x d 1 ? v cc av cc v ref av ss v ss p7 3 /an 3 /ad trg /int 4 ? p7 2 /an 2 /int 3 ? p7 1 /an 1 ? p7 0 /an 0 ? p12 2 /int 2 /tb2 in ? p12 1 /int 1 /tb1 in ? p12 0 /int 0 /tb0 in ? p8 0 /t x d 1 ? M37920FCCGP m37920fgcgp
3 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers m37920fxchp pin configuration (top view) outline 100p6q-a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p6 6 /dmareq 3 ? p6 5 /ta4 in /dmareq 2 ? p6 4 /ta4 out /dmaack 2 ? p6 0 /ta1 out /dmaack 0 ? p5 7 /ta2 in /rtp1 3 ? p5 6 /ta2 out /rtp1 2 ? p5 5 /rtp1 1 ? p5 4 /rtp1 0 ? p5 3 /rtp0 3 ? p5 2 /rtp0 2 ? p5 1 /ta0 in /rtp0 1 ? p5 0 /ta0 out /rtp0 0 ? p9 6 /wrh/ucas ? p9 5 /wrl/lcas ? p9 4 /cas/w ? p9 3 /cs 3 /ras 3 ? p9 2 /cs 2 /ras 2 ? p9 1 /cs 1 /ras 1 ? p9 0 /cs 0 ? p4 4 /hlda ? p4 3 /hold ? p4 2 /tc ? p4 1 / 1 ? p4 0 /ale ? 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p6 3 /ta3 in /dmareq 1 ? p6 2 /ta3 out /dmaack 1 ? p6 1 /ta1 in /dmareq 0 ? ? p3 0 /rdy 30 29 28 ? p3 1 /rd 27 ? p3 2 /blw 26 ? p3 3 /bhw byte nmi reset md0 v ss x in x out v cc ? p2 7 /d 15 ? p2 6 /d 14 ? p2 5 /d 13 ? p2 4 /d 12 ? p2 3 /d 11 ? p2 2 /d 10 ? p2 1 /d 9 ? p2 0 /d 8 ? p1 7 /d 7 ? p1 4 /d 4 ? p1 3 /d 3 ? p1 2 /d 2 ? p1 1 /d 1 ? p1 0 /d 0 md1 v ss ? p0 7 /a 23 ? p0 6 /a 22 /ma 11 ? p0 5 /a 21 ? p0 4 /a 20 /ma 10 ? p0 3 /a 19 ? p0 2 /a 18 /ma 9 ? p0 1 /a 17 ? p0 0 /a 16 /ma 8 ? p11 7 /a 15 /ma 7 ? p11 6 /a 14 /ma 6 ? p11 5 /a 13 /ma 5 ? p11 4 /a 12 /ma 4 ? p11 3 /a 11 /ma 3 ? p11 2 /a 10 /ma 2 ? p11 1 /a 9 /ma 1 ? p11 0 /a 8 /ma 0 ? p10 7 /a 7 ? p10 6 /a 6 ? p10 5 /a 5 ? p10 4 /a 4 ? p1 6 /d 6 ? p1 5 /d 5 p10 0 /a 0 ? 80 p10 1 /a 1 ? 79 p10 2 /a 2 ? 78 p10 3 /a 3 ? 77 76 p8 6 /clk 0 ? p8 5 /r x d 0 ? p8 4 /t x d 0 ? p8 3 /cts 0 /rts 0 ? p8 2 /cts 0 /clk 1 ? p8 1 /r x d 1 ? v cc av cc v ref av ss v ss p7 3 /an 3 /ad trg /int 4 ? p7 2 /an 2 /int 3 ? p7 1 /an 1 ? p7 0 /an 0 ? p12 2 /int 2 /tb2 in ? p12 1 /int 1 /tb1 in ? p12 0 /int 0 /tb0 in ? p8 0 /t x d 1 ? m37920fcchp m37920fgchp
preliminar y notice: this is not a final specification. some parametric limits are subject to change. M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 4 block diagram data bank register dt (8) program counter pc (16) incrementer/decrementer (24) program bank register pg (8) input buffer register ib (16) direct page register dpr0 (16) stack pointer s (16) index register y (16) index register x (16) arithmetic logic unit (16) accumulator b (16) accumulator a (16) instruction register (8) central processing unit (cpu) incrementer (24) program address register pa (24) data address register da (24) bus interface unit (biu) reset md1 reference voltage input v ref (0v) av ss avcc vcc external data bus width select input byte clock generating circuit clock input x in x out data buffer dq 0 (8) instruction queue buffer q 0 (8) data bus (odd) address bus a-d converter (10) watchdog timer timer tb1 (16) timer tb2 (16) timer tb0 (16) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta0 (16) input/output port p8 input/output port p7 input/output port p4 input/output port p10 input/output port p6 input/output port p5 input/output port p11 input/output port p1 input/output port p2 input/output port p3 input/output port p0 md0 (0v) vss processor status register ps (11) nmi data bus (even) data buffer dq 1 (8) data buffer dq 2 (8) data buffer dq 3 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) instruction queue buffer q 3 (8) instruction queue buffer q 4 (8) instruction queue buffer q 5 (8) instruction queue buffer q 6 (8) instruction queue buffer q 7 (8) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) direct page register dpr1 (16) direct page register dpr2 (16) direct page register dpr3 (16) clock output reset input note: flash memory ram M37920FCCGP, m37920fcchp 120 kbytes 4096 bytes m37920fgcgp, m37920fgchp 248 kbytes 6144 bytes uart1(9) uart0(9) ram (note) p8(7) p7(4) p9(7) p4(5) p10(8) p6(7) p5(8) dram controoler dma0(16) dma1(16) dma2(16) dma3(16) p11(8) p12(3) p1(8) p2(8) p3(4) p0(8) flash memory (note) input/output port p9 input/output port p12
5 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers power supply voltage power dissipation ports input/output characteristics functions (microcomputer mode) functions parameter number of basic machine instructions instruction execution time external clock input frequency f(x in ) memory size programmable input/output ports multi-functional timers serial i/o a-d converter watchdog timer dma controller dram controller chip-select wait control real-time output interrupts clock generating circuit input/output withstand voltage output current flash memory (user rom area) ram flash memory (boot rom area) p0 p2, p5, p10, p11 p3, p7 p4 p6, p8, p9 p12 ta0 ta4 tb0 tb2 uart0 and uart1 memory expansion operating ambient temperature range device structure package flash memory M37920FCCGP, m37920fcchp 120 kbytes (user rom area) m37920fgcgp, m37920fgchp 248 kbytes ram M37920FCCGP, m37920fcchp 4096 bytes m37920fgcgp, m37920fgchp 6144 bytes note: 203 50 ns (the fastest instruction at f(x in ) = 20 mhz) 20 mhz (max.) (note) (note) 16 kbytes 8-bit ? 6 4-bit ? 2 5-bit ? 1 7-bit ? 3 3-bit ? 1 16-bit ? 5 16-bit ? 3 (uart or clock synchronous serial i/o) ? 2 10-bit successive approximation method ? 1 (4 channels) 12-bit ? 1 4 channels maximum transfer rate 20 mbytes/sec. (at f(x in ) = 20 mhz, 0 wait, 1-bus cycle transfer) 10 mbytes/sec. (at f(x in ) = 20 mhz, 0 wait, 2-bus cycles transfer) 1 channel incorporates 8-bit refresh timer. supports cas before ras refresh method or self refresh method. chip select area ? 4 (cs 0 cs 3 ). a wait number and bus width can be set for each chip select area. 4 bits ? 2 channels; or 6 bits ? 1 channel + 2 bits ? 1 channel 6 external types, 20 internal types. each interrupt except nmi can be set to a priority level within the range of 0 7 by software. built-in (externally connected to a ceramic resonator or quartz crystal resonator). 5 v0.5 v 125 mw (at f(x in ) = 20 mhz) 5 v 5 ma up to 16 mbytes. note that bank ff 16 is a reserved area. 20 to 85 c cmos high-performance silicon gate process 100-pin plastic molded qfp
preliminar y notice: this is not a final specification. some parametric limits are subject to change. M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 6 user rom area boot rom area flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode flash memory parallel i/o mode flash memory serial i/o mode flash memory cpu reprogramming mode power supply voltage programming/erase voltage flash memory mode block division for erasure programming method erase method programming/erase control data protection method number of commands maximum number of reprograms 5 v0.5 v (in the flash memory parallel i/o mode, 3.3 v0.3 v) 5 v0.5 v (in the flash memory parallel i/o mode, 3.3 v0.3 v) 3 modes: parallel i/o, serial i/o, and cpu reprogramming modes (note 1) 1 block (16 kbytes ? 1) (note 2) programmed per page (in a unit of 256 kbytes) user rom area + boot rom area user rom area user rom area total erase/block erase user rom area + boot rom area user rom area user rom area programming/erase control by software commands protected per block, by using a lock bit. 8 commands 100 functions (flash memory mode) functions parameter 2: on shipment, our reprogramming control firmware for the flash memory serial i/o mode has been stored into the boot rom area. note that the boot rom area can be erased/programmed only in the flash memory parallel i/o mode. user rom area M37920FCCGP, m37920fcchp 5 blocks (8 kbytes ? 3, 32 kbytes ? 1, 64 kbytes ? 1), total 120 kbytes m37920fgcgp, m37920fgchp 7 blocks (8 kbytes ? 3, 32 kbytes ? 1, 64 kbytes ? 3), total 248 kbytes notes 1:
7 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers vcc, vss md0 md1 reset x in x out byte avcc, avss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 3 p4 0 p4 4 power supply input md0 md1 reset input clock input clock output external data bus width select input analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 input input input input output input input i/o i/o i/o i/o i/o apply 5 v0.5 v to vcc, and 0 v to vss. this pin controls the processor mode. connect this pin to v ss for the single-chip mode or memory expansion mode, and v cc for the microprocessor mode. connect this pin to vss. the microcomputer is reset when l level is applies to this pin. these are input and output pins of the internal clock generating circuit. connect a ceramic or quartz- crystal resonator between the x in and x out pins. when an external clock is used, the clock source should be connected to the x in pin, and the x out pin should be left open. this pin determines whether the external data bus has an 8-bit width or 16-bit width for the memory expansion mode or microprocessor mode. the width is 16 bits when l signal is input, and 8 bits when h signal is input. power supply input pin for the a-d converter. connect avcc to vcc, and avss to vss externally. this is the reference voltage input pin for the a-d converter. in single-chip mode port p0 is an 8-bit i/o port. this port has an i/o direction register, and each pin can be programmed for input or output. these pins enter the input mode at reset. in memory expansion and microprocessor modes address (a 16 a 23 ) is output. in dram space is accessed, multiplexed address (ma 8 ma 11 ) is output. in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes the low-order 8 bits of data (d 0 d 7 ) are input/output. in single-chip mode or when 8-bit external data bus is used with h level applied to pin byte in memory expansion or microprocessor mode these pins have the same functions as port p0. when the 16-bit external data bus is used with l level applied to pin byte in memory expansion or microprocessor mode the high-order 8 bits of data (d 8 d 15 ) are input or output. in single-chip mode these pins have the same functions as port p0. in memory expansion mode p3 0 functions as an i/o port pin. according to the register setting, this pin funtions as an output pin of rdy. p3 1 , p3 2 , p3 3 funtion as output pins of rd, blw, bhw, respectively. in microprocessor mode p3 0 functions as an input pin of rdy; and p3 1 , p3 2 , p3 3 function as output pins of rd, blw, bhw, respectively. in single-chip mode these pins have the same functions as port p0. p4 2 also funtions as pin tc. in memory expansion mode p4 0 p4 4 function as i/o port pins. according to the register setting, these pins function as output pins or input pins of ale, 1 , tc, hold, hlda, respectively. in microprocessor mode p4 0 and p4 1 function as outpout pins of ale, 1 . according to the register setting, these pins also funtion as i/o port pins. p4 2 funtions as an i/o port pin. accord- ing to the register setting, this pin also funtions as pin tc. p4 3 functions as an in- put pin of hold, and p4 4 functions as an output pin of hlda. pin description (microcomputer mode) functions input/ output name pin
preliminar y notice: this is not a final specification. some parametric limits are subject to change. M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 8 i/o i/o i/o i/o i/o i/o i/o i/o input functions input/ output name pin p5 0 p5 7 p6 0 p6 6 p7 0 p7 3 p8 0 p8 6 p9 0 p9 6 p10 0 p10 7 p11 0 p11 7 p12 0 p12 2 nmi in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timers a0, a2, and output pins for the real-time out- put. in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for timers a1, a3, a4, input pins for dma requests, and output pins for dma acknowledge signals. in addition to having the same functions as port p0 in the single-chip mode, these pins also function as input pins for the a-d converter. p7 2 and p7 3 also function as input pins for int 3 and int 4 . in addition to having the same functions as port p0 in the single-chip mode, these pins also function as i/o pins for uart0, uart1. in single-chip mode these pins have the same function as port p0. in memory expansion or microprocessor mode according to the software setting, p9 0 p9 3 also funtion as chip select output pins. while dram space is selected, p9 4 p9 6 function as output pins for dram control signals. some pins of p9 1 p9 3 , coressponding to the selected dram space, function as pins ras. in single-chip mode these pins have the same functions as port p0. in memory expansion and microprocessor modes address (a 0 a 7 ) is output. in single-chip mode these pins have the same functions as port p0. in memory expansion or microprocessor mode address (a 8 a 15 ) is output. while dram space is accessed, multiplexed address (ma 0 ma 7 ) is output. in addition to having the same functions as port p0 in the single-ship mode, these pins also function as input pins for timers b0 b2. this pin is for a non-maskable interrupt. i/o port p5 i/o port p6 i/o port p7 i/o port p8 i/o port p9 i/o port p10 i/o port p11 i/o port p12 non-maskable interrupt
9 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers basic function blocks these microcomputers contain the following devices on the single chip: the flash memory, ram, cpu, bus interface unit, and periph- eral devices such as the interrupt control circuit, timers, serial i/o, a-d converter, i/o ports, clock generating circuit, etc. memory figures 1 and 2 show the memory maps. the address space is 16 mbytes from addresses 0 16 to ffffff 16 . the address space is di- vided into 64-kbyte units called banks. the banks are numbered from 0 16 to ff 16 . bank ff 16 is a reserved area for the development support tool. therefore, do not use bank ff 16 . internal flash memory and internal ram are assigned as shown in figures 1 and 2. addresses ffc0 16 to ffff 16 contain the reset and the interrupt vector addresses, and the interrupt vectors are stored there. for details, refer to the section on interrupts. assigned to addresses 0 16 to ff 16 are peripheral devices such as i/o ports, a-d converter, uart, timers, interrupt control registers, dma controoler, dram controller, etc. for the flash memory in the boot rom area, refer to the section on the flash memory mode. fig. 1 memory map of M37920FCCGP and m37920fcchp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area dma0 dma1 dma2 dma3 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 4096 bytes internal flash memory 120 kbytes (user rom area) peripheral devices control registers 001fff 16 002000 16 feffff 16 ff0000 16 0017ff 16 001800 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 reserved area for development support tool
preliminar y notice: this is not a final specification. some parametric limits are subject to change. M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 10 fig. 2 memory map of m37920fgcgp and m37920fgchp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area dma0 dma1 dma2 dma3 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 nmi reset dbc 000000 16 bank 0 16 ffffff 16 fe0000 16 00ffff 16 010000 16 01ffff 16 bank fe 16 000000 16 000800 16 0000ff 16 00fffe 16 00ffc0 16 internal ram 6144 bytes internal flash memory 248 kbytes (user rom area) peripheral devices control registers 001fff 16 002000 16 feffff 16 ff0000 16 00ffff 16 00ffc0 16 bank 1 16 bank ff 16 020000 16 02ffff 16 bank 2 16 030000 16 03ffff 16 bank 3 16 reserved area for development support tool
11 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 4 location of sfrs (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 00000a 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 port p2 register port p3 register port p1 direction register port p0 direction register port p1 register port p0 register port p2 direction register port p3 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register port p10 register port p11 register port p10 direction register port p11 direction register a-d control register 0 a-d control register 1 a-d register 1 a-d register 2 a-d register 3 uart0 transmit/receive mode register uart0 baud rate register (brg0) uart0 transmit buffer register uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register address (hexadecimal notation) 000040 16 000041 16 000042 16 000043 16 000044 16 000045 16 000046 16 000047 16 000048 16 000049 16 00004a 16 00004b 16 00004c 16 00004d 16 00004e 16 00004f 16 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 address (hexadecimal notation) count start register one-shot start register timer a clock division select register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a1 mode register timer a0 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 1 watchdog timer register particular function select register 0 particular function select register 1 debug control register 0 int 3 interrupt control register uart0 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register int 1 interrupt control register watchdog timer frequency select register debug control register 1 int 4 interrupt control register uart1 transmit interrupt control register timer a2 interrupt control register timer b1 interrupt control register int 2 interrupt control register address comparison register 0 address comparison register 1 particular function select register 2 reserved area (note) note: do not write to this address. uart0 transmit/receive control register 0 up-down register processor mode register 0 a-d conversion interrupt control register uart0 receive interrupt control register int 0 interrupt control register port p9 register port p9 direction register port p12 register port p12 direction register a-d register 0 reserved area (note) reserved area (note)
preliminar y notice: this is not a final specification. some parametric limits are subject to change. M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 12 fig. 5 location of sfrs (2) 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 0000a0 16 0000a1 16 0000a2 16 0000a3 16 0000a4 16 0000a5 16 0000a6 16 0000a7 16 0000a8 16 0000a9 16 0000aa 16 0000ab 16 0000ac 16 0000ad 16 0000ae 16 0000af 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 0000b6 16 0000b7 16 0000b8 16 0000b9 16 0000ba 16 0000bb 16 0000bc 16 0000bd 16 0000be 16 0000bf 16 real-time output control register pulse output data register 0 pulse output data register 1 reserved area (note) cts/rts separate select register 000080 16 000081 16 000082 16 000083 16 000084 16 000085 16 000086 16 000087 16 000088 16 000089 16 00008a 16 00008b 16 00008c 16 00008d 16 00008e 16 00008f 16 000090 16 000091 16 000092 16 000093 16 000094 16 000095 16 000096 16 000097 16 000098 16 000099 16 00009a 16 00009b 16 00009c 16 00009d 16 00009e 16 00009f 16 address (hexadecimal notation) cs 0 control register l cs 0 control register h cs 1 control register l cs 1 control register h cs 2 control register l cs 2 control register h cs 3 control register l cs 3 control register h area cs 0 start address register area cs 1 start address register area cs 2 start address register area cs 3 start address register reserved area (note) reserved area (note) flash memory control register note: do not write to this address. reserved area (note) reserved area (note) reserved area (note) reserved area (note) address (hexadecimal notation) dram control register refresh timer dmac control register l dmac control register h dma0 interruput control register dma1 interruput control register dma2 interruput control register dma3 interruput control register source address register 0 l source address register 0 m source address register 0 h destination address register 0 l destination address register 0 m destination address register 0 h transfer counter register 0 l transfer counter register 0 m transfer counter register 0 h dma0 mode register l dma0 mode register h dma0 control register source address register 1 l source address register 1 m source address register 1 h destination address register 1 l destination address register 1 m destination address register 1 h transfer counter register 1 l transfer counter register 1 m transfer counter register 1 h dma1 mode register l dma1 mode register h dma1 control register source address register 2 l source address register 2 m source address register 2 h destination address register 2 l destination address register 2 m destination address register 2 h transfer counter register 2 l transfer counter register 2 m transfer counter register 2 h dma 2 mode register l dma 2 mode register h dma 2 control register source address register 3 l source address register 3 m source address register 3 h destination address register 3 l destination address register 3 m destination address register 3 h transfer counter register 3 l transfer counter register 3 m transfer counter register 3 h dma 3 mode register l dma 3 mode register h dma 3 control register
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 13 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. central processing unit (cpu) the cpu has 13 registers, and they are shown in figure 6. each of these registers is described below. accumulator a (a) accumulator a is the main register of the microcomputer. it consists of 16 bits and the low-order 8 bits can be used separately. data length flag m determines whether the register is used as 16-bit reg- ister or as 8-bit register. it is used as a 16-bit register when flag m is ??and as an 8-bit register when flag m is ?? flag m is a part of the processor status register (ps) which is described later. data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator a. accumulator b (b) accumulator b has the same functions as accumulator a, but the use of accumulator b requires more instruction bytes and execution cycles than accumulator a. accumulator e accumulator e is a 32-bit register and consists of accumulator a (low-order 16 bits) and accumulator b (high-order 16 bits). it is used for 32-bit data processing. index register x (x) index register x consists of 16 bits and the low-order 8 bits can be used separately. index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is ??and as an 8-bit register when flag x is ?? flag x is a part of the processor status register (ps) which is described later. in index addressing modes in which register x is used as the index register, the contents of this address are added to obtain the real ad- dress. index register x functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). index register y (y) index register y consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is ??and as an 8-bit register when flag x is ?? flag x is a part of the processor status register (ps) which is described later. in index addressing modes in which register y is used as the index register, the contents of this address are added to obtain the real ad- dress. index register y functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). 1570 1570 15 7 0 1570 15 0 15 0 15 0 15 7 0 00000 ipl 2 ipl 1 ipl 0 nvmxd i zc dpr0 to dpr3 pc s y h y l x h x l b h b l a h a l accumulator a accumulator b index register x index register y stack pointer s program counter pc direct page registers dpr0 to dpr3 processor status register ps carry flag zero flag interrupt disable flag decimal mode flag index register length flag data length flag overflow flag negative flag processor interrupt priority level ipl 70 70 pg program bank register pg data bank register dt dt 15 7 0 15 7 0 a h a l b h b l accumulator e 31 0 fig. 6 register structure
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 14 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. stack pointer (s) stack pointer (s) is a 16-bit register. it is used during a subroutine call or interrupts. it is also used during stack, stack pointer relative, or stack pointer relative indirect indexed y addressing mode. program counter (pc) program counter (pc) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. there is a bus interface unit between the program memory and the cpu, so that the program memory is accessed through bus interface unit. this is described later. program bank register (pg) program bank register is an 8-bit register that indicates the high-or- der 8 bits of the next program memory address to be executed. when a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (pg) is increased by 1. also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (pc) using the branch instruction, the contents of the program bank regis- ter (pg) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries. data bank register (dt) data bank register (dt) is an 8-bit register. with some addressing modes, the data bank register (dt) is used to specify a part of the memory address. the contents of data bank register (dt) is used as the high-order 8 bits of a 24-bit address. addressing modes that use the data bank register (dt) are direct indirect, direct indexed x indi- rect, direct indirect indexed y, absolute, absolute bit, absolute in- dexed x, absolute indexed y, absolute bit relative, and stack pointer relative indirect indexed y. direct page registers 0 to 3 (dpr0 to dpr3) the direct page register is a 16-bit register. an addressing mode of which name includes direct generates an address of data to be ac- cessed, regarding the contents of this register as the base address. the 7900 series has been expanded direct page registers up to 4 (dpr0 to dpr3), in comparison to the 7700 series which has the single direct page register. accordingly, the 7900 series s direct ad- dressing method which uses direct page registers differs from that of the 7700 series. however, the conventional direct addressing method, using only dpr0, is still be selectable, in order to make use of the 7700 series software property. for more details, refer to the section on the direct page. processor status register (ps) processor status register (ps) is an 11-bit register. it consists of flags to indicate the result of operation and cpu interrupt levels. branch operations can be performed by testing the flags c, z, v, and n. the details of each bit of the processor status register are described below. 1. carry flag (c) the carry flag contains the carry or borrow generated by the alu af- ter an arithmetic operation. this flag is also affected by shift and ro- tate instructions. this flag can be set and reset directly with the sec and clc instructions or with the sep and clp instructions. 2. zero flag (z) the zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. this flag can be set and reset directly with the sep and clp instructions. 3. interrupt disable flag (i) when the interrupt disable flag is set to 1 , all interrupts except ___ watchdog timer, nmi, and software interrupt are disabled. this flag is set to 1 automatically when an interrupt is accepted. it can be set and reset directly with the sei and cli instructions or sep and clp instructions. 4. decimal mode flag (d) the decimal mode flag determines whether addition and subtraction are performed as binary or decimal. binary arithmetic is performed when this flag is 0 . if it is 1 , decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. arithmetic operation is performed using four digits when data length flag m is 0 and with two digits when it is 1 . decimal adjust is automatically performed. (decimal operation is possible only with the adc and sbc instruc- tions.) this flag can be set and reset with the sep and clp instruc- tions.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 15 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. 5. index register length flag (x) the index register length flag determines whether index register x and index register y are used as 16-bit registers or as 8-bit registers. the registers are used as 16-bit registers when flag x is 0 and as 8- bit registers when it is 1 . this flag can be set and reset with the sep and clp instructions. 6. data length flag (m) the data length flag determines whether the data length is 16-bit or 8-bit. the data length is 16 bits when flag m is 0 and 8 bits when it is 1 . this flag can be set and reset with the sem and clm instruc- tions or with the sep and clp instructions. 7. overflow flag (v) the overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. if data length flag m is 0 , the overflow flag is set when the result of addition or subtrac- tion is outside the range between 32768 and +32767. if data length flag m is 1 , the overflow flag is set when the result of addition or subtraction is outside the range between 128 and +127. it is reset in all other cases. the overflow flag can also be set and reset directly with the sep, and clv or clp instructions. additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of 2147483648 to +2147483647 in the rmpa operation. 8. negative flag (n) the negative flag is set when the result of arithmetic operation or data transfer is negative (if data length flag m is 0 , data s bit 15 is 1 . if data length flag m is 1 , data s bit 7 is 1 .) it is reset in all other cases. it can also be set and reset with the sep and clp instruc- tions. 9. processor interrupt priority level (ipl) the processor interrupt priority level (ipl) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. interrupt is enabled when the interrupt priority of the device request- ing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. when an interrupt is enabled, the cur- rent processor interrupt priority level is saved in a stack and the pro- cessor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. refer to the section on inter- rupts for more details. note: fix bits 11 to 15 of the processor status register (ps) to 0 .
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 16 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. bank in order to effectively use the integrated hardware on the chip, this cpu core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. in other words, the 64 kbytes specified by the low-order 16 bits are one unit (referred to as bank ), and the address space is divided into 256 banks (0 16 to ff 16 ) specified by the high-order 8 bits. in the program area on the address space, the bank is specified by the program bank register (pg), and the address in the bank is specified by the program counter (pc). as for each bank boundary, when an overflow has occurred in pc, the contents of pg are incremented by 1. when a borrow has oc- curred in pc, the contents of pg are decremented by 1. under the normal conditions, therefore, programming without concern for the bank boundaries is possible. furthermore, as for the data area on the address space, the bank is specified by the data bank register (dt), and the address in the bank is specified by the operation result by using the various addressing modes (note). note: some addressing modes directly specify a bank. direct page the internal memory and control registers for internal peripheral de- vices, etc. are assigned to bank 0 16 (addresses 0 16 to ffff 16 ). the direct page and direct addressing modes have been provided for the effective access to bank 0 16 . in the 7900 series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only dpr0, as in the 7700 series, and the ex- panded direct addressing mode, which uses up to 4 direct page reg- isters as selected by the user. the addressing mode is selected according to the contents of bit 1 of the processor mode register 1. this bit 1 is cleared to 0 at reset. (in other words, the conventional direct addressing mode is selected.) however, once this bit 1 has been set to 1 by software, this bit cannot be cleared to 0 again, except by reset. that is to say, when one of these two direct address- ing modes has been selected just after reset, the selected address- ing mode cannot be switched to another one while the program is running. conventional direct addressing mode the direct page area consists of 256-byte space. its bank address is 00 16 , and the base address of its low-order 16-bit address is speci- fied by the contents of the direct page register 0 (dpr0). in this con- ventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the dpr0 con- tents, and the cpu accesses each address in the direct page area. expanded direct addressing mode the direct page area consists of four 64-byte spaces. their bank address is 00 16 , and the four base addresses of their low-order 16- bit addresses are respectively specified by the contents of four direct page registers. in this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows: high-order 2 bits: regarded as a selection field for dpr0 to dpr3. low-order 6 bits: regarded as an offset value for the selected direct page register. then, the cpu accesses each address in each direct page area: refer to 7900 series software manual for details concerning the various addressing modes which use the direct page area. instruction set the cpu core of the 7900 series has an expanded instruction set based on the existing 7700/7751 series cpu core. in addition, its source code (mnemonic) has the complete upper compatibility with the 7700 series instruction set. for details concerning addressing modes and instruction set, refer to 7900 series software manual .
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 17 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. bus interface unit data transfer shown below is always performed via the bus interface unit (biu), which is located between the cpu and the internal buses: between the cpu and the internal memory, internal peripheral de- vices, external areas between the dma controller (dmac) and the internal memory, in- ternal peripheral devices, external areas figure 7 shows the biu and the bus structure. the cpu and biu, or dmac and biu are connected by a dedicated bus respectivery, and any transfer between the cpu and biu, or dmac and biu is con- trolled by this dedicated bus. on the other hand, data transfer between the biu and internal pe- ripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. the bus control method where the code bus and the data bus sepa- rate out (hereafter, this method is referred to as the separate code/ data bus method) is employed in order to improve data transfer ca- fig. 7 biu and bus structure internal code bus (cb 0 to cb 31 ) central processing unit (cpu) sfr : special function register ? the cpu bus, dmac bus, internal bus, and external bus separate out independently. external devices internal control signal cpu bus internal bus internal data bus (db 0 to db 15 ) internal memory internal peripheral devices (sfr) external bus a 0 to a 23 (ma 0 to ma 11 ) d 0 to d 7 d 8 to d 15 control signal bus interface unit (biu) bus conversion circuit internal address bus (ad 0 to ad 23 ) dma controller (dmac) dmac bus refresh request dram control signal dram controller (dramc) hold hold request hlda pabilities. as a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal periph- eral devices are connected only to the data bus. each width of external buses are as follows: a 24-bit address bus, 16-bit data bus. the external data bus transfers instruction codes and data. when the code or data access occurs for the external, the external access is performed via the bus conversion circuit. when the dram is selected in external devices, the internal dmac controller (dramc) is operated, and access for dram and dram refresh operation become enabled. for details, refer to the section on the chip select wait controller and dramc described later. when accessing the external devices, it is possible to insert the re- covery cycles. refer to the section on the processor modes and chip select wait controller described later. when the burst rom is used as an external device, refer to the sec- tion on the chip select wait controller described later.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 18 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. name program address register instruction queue buffer data address register data buffer biu structure the biu consists of four registers shown in figure 8. table 1 lists the functions of each register. table 1. functions of each register fig. 8 register structure of biu functions indicates a storage address for an instruction to be next taken into an instruction queue buffer. temporarily stores an instruction which has been taken from a memory. consists of 10 bytes. indicates an address where data will be next read from or written to. temporarily stores data which has been read from internal memory, internal peripheral devices, and external areas by the biu; or temporarily stores data which is to be written to internal memory, internal peripheral devices, and external areas by the cpu or dmac. consists of 32 bits. pa q0 q9 da dq b23 b0 b7 b0 b23 b0 b31 b0 program address register instruction queue buffer data address register data buffer
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 19 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. x 0 0 x x 0 ad 1 (a 1 ) even-numbered address 4-byte boundary 8-byte boundary biu functions (1) instruction prefetch the biu has ten instruction queue buffers; each buffer consists of 1 byte. when there is an opening in the bus and the instruction queue buffer, an instruction code is read from the program memory (in other words, the memory where a program is stored) and prefetched into an instruction queue buffer. the prefetched instruction code is trans- ferred from the biu to the cpu, in response to a request from the cpu, via a dedicated bus. when a branch occurs as a result of a branch instruction (jmp, bra, etc.), subroutine call, or interrupt, the contents of the instruction queue buffer are initialized and the biu reads a new instruction from the branch destination address. note that the operations of the biu instruction prefetch also differ de- pending on the store addresses for instructions. the store addresses for instructions to be prefetched are categorized as listed in table 2. (2) data read operation when executing an instruction for reading data from the internal memory, internal peripheral devices, or external areas, at first, the cpu informs the bius data address register of the address where the data has been located. next, the biu reads the above data from the specified address, passes it to the data buffer, and then, transfers it to the cpu. (3) data write operation when executing an instruction for writing data into the internal memory, internal peripheral devices, or external area, at first, the cpu informs the bius data address register of the address where the data has been located. next, the biu passes the above data to the data buffer register, and then, writes it into the specified address. (4) bus cycle in order for the biu to execute the above operations (1) through (3), the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal control signals must be appropriately controlled during data transfer between the biu and internal memory, internal peripheral devices, external areas. this operation is called ?us cycle? the bus cycle is affected by the following conditions at instruction prefetch and data access. [instruction prefetch] ?whether the address area locates in the internal area or the ex- ternal area. ?when the address area locates in the external area ? whether the bus width of external devices = 16 bits or 8 bits: (a) when the external bus width = 16 bits: whether the start address for access locates at a 4- byte boundary or at an 8-byte boundary. (b) when the external bus width = 8 bits: whether the start address for access locates at an even-numbered address, a 4-byte boundary or at the 8- byte bound ary. ? whether the prefetch operation is generated by a branch, or not. ? number of waits ? others: whether any the burst rom access and the dram space is specified or not. (for details, refer to the section on the chip select wait controller and dram controller described later.) table 2. store addresses for instructions to be prefetched low-order 3 bits of store address for instruction ad 2 (a 2 ) 0 0 0 ad 0 (a 0 ) [data access] ?whether the address area locates in the internal area or the ex- ternal area. ?length of data to be transferred: byte, word, double word ?when the address area locates in the external area: ? whether the bus width of external devices = 16 bits or 8 bits: ? number of waits ? others: whether the dram space is specified or not. (for details, refer to the section on the chip select wait controller and dram controller described later.) the biu controls the bus cycle depending on the above conditions. instruction prefetch and data access are performed as shown in tables 3 to 10. x: 0 or 1
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 20 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. access to internal area access to external area when address locates at 4-byte boundary or when branched: double consecutive access when branched or at instruction prefetch when external data bus width = 16 bits when external data bus width = 8 bits biu internal address bus internal code bus cb 31 to cb 0 code 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw d 7 to d 0 d 7 to d 0 d 15 to d 8 d 15 to d 8 address address + 2 when address of instruction to be prefetched locates at 8-byte boundary: quadruple consecutive access 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw d 7 to d 0 d 7 to d 0 d 7 to d 0 d 7 to d 0 d 15 to d 8 d 15 to d 8 d 15 to d 8 d 15 to d 8 address address + 2 address + 4 address + 6 when address is even-numbered address or when branched: double consecutive access 1 a 23 to a 0 d 7 to d 0 ale rd blw bhw d 7 to d 0 d 7 to d 0 address address + 1 when address of instruction to be prefetched locates at 4-byte boundary or 8-byte boundary: quadruple consecutive access 1 a 23 to a 0 d 7 to d 0 ale rd blw bhw d 7 to d 0 d 7 to d 0 d 7 to d 0 d 7 to d 0 address address + 1 address + 2 address + 3 internal ram table 3. instruction prefetch
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 21 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 4. data access (1) external data bus width = 16 bits byte data read byte data written word data read word data written access starting from even-numbered address access starting from odd-numbered address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw d 7 to d 0 address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw d 7 to d 0 address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw d 7 to d 0 address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw d 7 to d 0 address d 15 to d 8 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 d 15 to d 8 d 7 to d 0 d 15 to d 8 d 15 to d 8 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 d 15 to d 8 d 7 to d 0 d 15 to d 8 invalid invalid invalid invalid
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 22 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 5. data access (2) external data bus width = 16 bits double word data read double word data written access starting from even-numbered address access starting from odd-numbered address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 d 15 to d 8 d 7 to d 0 d 7 to d 0 d 15 to d 8 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 address + 2 d 15 to d 8 d 7 to d 0 d 15 to d 8 d 7 to d 0 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 address + 2 d 15 to d 8 d 7 to d 0 d 15 to d 8 d 7 to d 0 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 d 15 to d 8 d 7 to d 0 d 7 to d 0 d 15 to d 8 invalid invalid
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 23 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 6. data access (3) external data bus width = 8 bits byte data read byte data written word data read word data written access starting from even- or odd-numbered address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 (note) (note) ale rd blw bhw d 7 to d 0 address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 (note) (note) (note) (note) (note) (note) ale rd blw bhw d 7 to d 0 address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 d 7 to d 0 d 7 to d 0 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 ale rd blw bhw address address + 1 d 7 to d 0 d 7 to d 0 note: when the voltage level at pin byte = l , functions as pins d 15 to d 8 are valid. however, when 8-bit width is selected as the external bus width by the chip select wait controller, the functions as pins d 15 to d 8 and bhw become invalid. when the voltage level at pin byte = h , these pins function as programmable i/o port (p2) pins.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 24 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 7. data access (4) external data bus width = 8 bits double word data read double word data written access starting from even- or odd-numbered address 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 (note) (note) ale rd blw bhw address address + 1 address + 2 address + 3 d 7 to d 0 d 7 to d 0 d 7 to d 0 d 7 to d 0 1 a 23 to a 0 d 7 to d 0 d 15 to d 8 (note) (note) ale rd blw bhw address address + 1 address + 2 address + 3 d 7 to d 0 d 7 to d 0 d 7 to d 0 d 7 to d 0 note: when the voltage level at pin byte = l , functions as pins d 15 to d 8 are valid. however, when 8-bit width is selected as the external bus width by the chip select wait controller, the functions as pins d 15 to d 8 and bhw become invalid. when the voltage level at pin byte = h , these pins function as programmable i/o port (p2) pins.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 25 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. table 8. wait number (instruction prefetch or data access) access to internal area access to external area 1 a 23 to a 0 ale rd, blw, bhw data biu internal address bus internal code bus cb 31 to cb 0 code biu internal address bus internal data bus db 15 to db 0 data 0-wait access 1 a 23 to a 0 ale rd, blw, bhw data 1-wait access 1 a 23 to a 0 ale rd, blw, bhw data 2-wait access 1 a 23 to a 0 ale rd, blw, bhw data ale expansion wait access external data bus external data bus external data bus external data bus
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers 26 single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 9 recovery cycle (at instruction prefetch) at double consecutive access (when address locates at 4-byte boundary or when branched) 1 a 23 to a 0 ale rd address at quadruple consecutive access (when address locates at 8-byte boundary) 1 a 23 to a 0 ale rd address + 2 address instruction prefetch recovery cycle next access cycle address address address + 4 address + 6 address + 2 instruction prefetch next access cycle note: external data bus width = 16 bits and at 0 wait. fig. 10 recovery cycle (at data access) 1 a 23 to a 0 ale rd, address access cycle recovery cycle next access cycle blw, bhw note: at 0 wait.
27 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers selection of processor mode figures 11, 12 show the bit configurations of the processor mode registers 0, 1. any of the three processor modes (single-chip mode, memory ex- pansion mode, microprocessor mode) can be selected with the fol- lowing: ?processor mode bits of the processor mode register 0 (bits 1 and 0 at address 5e 16 ; figure 11) table 9 lists the selection method of a processor mode. the memory map which the cpu can access depends on the se- lected processor mode. figure 13 shows the memory maps in three processor modes. also, the functions of ports p0 to p4, p10, p11, and part of port p9 depend on the selected processor mode. for details, see table 10. in the single-chip mode, ports p0 to p4, p10, p11, and p9 function as i/o ports. in this mode, only the internal area (sfrs, internal ram, internal rom) is accessible. in the memory expansion and microprocessor modes, external de- vices assigned in the external memory area can be connected via buses. therefore, ports p0 to p4, p10, p11, and part of port p9 func- tion as i/o pins for the address bus, data bus, bus control signals. (some of port functions are selectable.) in the memory expansion mode, all of the internal area (sfrs, inter- nal ram, internal rom) and external area are accessible. in the mi- croprocessor mode, the internal area except for the internal rom (in other words, sfrs and internal ram) and the external area are ac- cessible. note that, when the external devices are located to an area where the internal area and external area overlap, only the internal area can be read/written; the external area cannot be read/written. table 11 lists each bus control signals function. fig. 11 bit configuration of processor mode register 0 76543210 processor mode register 0 processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : do not select. interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : do not select. software reset bit by a write of 1 to this bit, the microcomputer will be reset, and then, restarted. external bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ale expansion wait clock 1 output select bit 0 : 1 output is disabled. (p4 1 functions as an programmable i/o port pin.) 1 : 1 output is enabled. (p4 1 functions as the clock 1 output pin.) address 5e 16
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 28 single-chip mode sfr unused area ram rom unused area reserved area (note) memory expansion mode : external memory area. note: do not access this area. sfr ram rom reserved area (note) microprocessor mode sfr ram 0 16 ff 16 feffff 16 ff0000 16 ffffff 16 fig. 13 memory maps in three processor modes fig. 12 bit configuration of processor mode register 1 76543210 processor mode register 1 fix this bit to ?? rdy input select bit (notes 2 to 4) 0 : rdy input is disabled. (p3 0 functions as a programmable i/o port pin.) 1 : rdy input is enabled. (p3 0 functions as pin rdy.) ale output select bit (notes 2 and 3) 0 : ale output is disabled. (p4 0 functions as a programmable i/o port pin.) 1 : ale output is enabled. (p4 0 functions as pin ale.) direct page register switch bit (note 1) 0 : only dpr0 is used. 1 : dpr0 to dpr3 are used. recovery cycle insert select bit (notes 2 and 3) 0 : no recovery cycle is inserted at access to the external area. 1 : recovery cycle is inserted at access to the external area. address 5f 16 hold input, hlda output select bit (notes 2 to 4) 0 : hold input and hlda output are disabled. (p4 3 and p4 4 function as programmable i/o port pins.) 1 : hold input and hlda output are enabled. (p4 3 and p4 4 function as pins hold and hlda, respectively.) ??at read. internal rom access wait bit (note 5) 0 : 1 wait 1 : 0 wait 00 notes 1: after reset, this bit? contents can be switched only once. during the software execution, be sure not to switch this bit? co ntents. 2: in the single-chip mode, these bits?functions are disabled regardless of these bits?contents. 3: while v ss level voltage is applied to pin md0, each of these bits is ??at reset. while v cc level voltage is applied to pin md0, on the other hand, each of these bits is ??at reset. 4: in the memory expansion or microprocessor mode, if this bit? contents is switched from ??to ?? this bit will be cleared t o ?? after this clearance, this bit cannot return to ?? if it is necessary to set this bit to ?? be sure to reset the microcompu ter. 5: in the microprocessor mode, this bit is invalid. when the internal flash memory is repro g rammed in the cpu repro g rammin g mode, be sure to clear this bit to ?? v ss v cc md0 after reset is removed, the single-chip mode is selected. by changing the processor mode bits?contents by soft- ware, the single-chip mode, memory expansion mode or microprocessor mode can be selected. description mode after reset is removed, the mi- croprocessor mode is se- lected. ?single-chip mode ? memory expansion mode ?microprocessor mode table 9. selection method of processor mode ?microprocessor mode
29 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers microprocessor mode v cc level voltage is applied 10 sfr area internal ram area external memory area external memory area low-order address (a 0 to a 7 ) is output. middle-order address (a 8 to a 15 ) is output. multiplexed address (ma 0 to ma 7 ) is output (note 3) high-order address (a 16 to a 23 ) is output. multiplexed address (ma 8 to ma 11 ) is output (note 3) low-order data (d 0 to d 7 , data at even- numbered address) is input/output. low-order data (d 0 to d 7 , data at even-/ odd-numbered address) is input/output. low-order data (d 0 to d 7 , data at odd- numbered address) is input/output. i/o port pins p2 0 to p2 7 ready signal rdy is input. i/o port pin p3 0 (note 5) read signal rd is output write signal blw (write to even-num- bered address) is output. write signal blw (write to even-/odd- numbered address) is output. write signal bhw (write to odd-num- bered address) is output. i/o port pin p3 3 memory expansion mode v ss level voltage is applied 01 sfr area internal ram area internal rom area external memory area low-order address (a 0 to a 7 ) is output. middle-order address (a 8 to a 15 ) is output. multiplexed address (ma 0 to ma 7 ) is output (note 3) high-order address (a 16 to a 23 ) is output. multiplexed address (ma 8 to ma 11 ) is out- put (note 3) low-order data (d 0 to d 7 , data at even- numbered address) is input/output. low-order data (d 0 to d 7 , data at even-/ odd-numbered address) is input/output. low-order data (d 0 to d 7 , data at odd-num- bered address) is input/output. i/o port pins p2 0 to p2 7 i/o port pin p3 0 ready signal rdy is input (note 5). read signal rd is output. write signal blw (write to even-numbered address) is output. write signal blw (write to even-/odd-num- bered address) is output. write signal bhw (write to odd-numbered address) is output. i/o port pin p3 3 table 10. relationship between processor modes, memory area, and port function mode (note 1) single-chip mode v ss level voltage is applied 00 sfr area internal ram area internal rom area (do not access.) i/o port pins p10 0 to p10 7 i/o port pins p11 0 to p11 7 i/o port pins p0 0 to p0 7 i/o port pins p1 0 to p1 7 i/o port pins p2 0 to p2 7 i/o port pin p3 0 i/o port pin p3 1 i/o port pin p3 2 i/o port pin p3 3 memory area port pins p10 0 to p10 7 port pins p11 0 to p11 7 port pins p0 0 to p0 7 port pins p1 0 to p1 7 external data bus width = 16 bits external data bus width = 8 bits external data bus width = 8 bits port pins p2 0 to p2 7 port pin p3 0 port pin p3 1 external data bus width = 16 bits external data bus width = 8 bits external data bus width = 16 bits port pin p3 2 port pin p3 3 external data bus width = 8 bits pin md0 processor mode bits (note 2) sfr area internal ram area internal rom area other area external data bus width = 16 bits notes 1: for details of the processor mode setting, see table 9. 2: processor mode bits = bits 1 and 0 of the processor mode register 0 (address 5e 16). 3: while dram space is accessed, the multiplexed address is output. 4: in the memory expansion mode, by the corresponding select bits of the processor mode register 0 and 1 (addresses 5e 16 , 5f 16 ), port pins p3 0 , p4 0 to p4 3 can operate as pins for rdy input, ale output, 1 output, hlda output, hold input, respectively. in the microprocessor mode, by the above select bits, the above pins (rdy, ale, 1 , hlda, hold) can operate as port pins p3 0 , p4 0 to p4 3 , respec- tively. 5: in the memory expansion mode, port pin p9 0 can operate as the cs 0 output pin by the cs 0 output select bit of the cs 0 control register l (bit 7 at address 80 16 ). 6: in the memory expansion and microprocessor modes, port pins p9 1 to p9 3 can operate as the cs 1 /cs 2 /cs 3 output pins by the cs i output select bits (i = 1 to 3) (bit 7s at addresses 82 16 , 84 16 , 86 16 ). i/o port pin p4 0 i/o port pin p4 1 clock 1 is output (note 4) . i/o port pin p4 2 i/o port pin p4 3 i/o port pin p9 0 i/o port pins p9 1 to p9 3 port pin p4 0 port pin p4 1 port pin p4 2 port pin p4 3 port pin p9 0 port pins p9 1 to p9 3 i/o port pin p4 0 address latch enable signal ale is output (note 4) . i/o port pin p4 1 clock 1 is output (note 4) . i/o port pin p4 2 hold acknowledge signa hlda is output (note 4) . i/o port pin p4 3 hold request signal hold is input (note 4) . i/o port pin p9 0 chip select signal cs 0 is output (note 5) . i/o port pins p9 1 to p9 3 c hip select signals cs 1 to cs 3 are output (note 6) . address latch enable signal ale is output. i/o port pin p4 0 (note 4) clock 1 is output. i/o port pin p4 1 (note 4) hold acknowledge signal hlda is output. i/o port pin p4 2 (note 4) hold request signal hold is input. i/o port pin p4 3 (note 4) chip select signal cs 0 is output. i/o port pin p9 1 to p9 3 chip select signals cs 1 to cs 3 are output (note 6) .
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 30 signal rd blw bhw ale 1 rdy hold hdla cs 0 cs 3 byte table 11. each bus control signal s function i/o output output output output input input output output input function read signal. outputs l at read from the external area. write signal. outputs l at write to the external area. address latch enable signal. outputs h level pulse in the period just before signals rd, blw, bhw become l . this is used to latch an address in the external. internal standard clock s output. outputs system clock (f sys ). ready signal. the l level period of the last 1 in the ac- cess cycle for the external area (in other words, l level period of rd, blw, bhw) will be extended while l level voltage is applied to this pin. hold request signal. appliance of l level voltage will gen- erate a hold request; appliance of h level voltage will re- quest to terminate the hold state. hold acknowledge signal. outputs l in the hold state. chip select signal. outputs l in access to the specified chip select area. input signal to select the external data bus width. when this pin s level = vss, 16-bit width will be selected; and when vcc, 8-bit width will be selected. remarks for operation differences between blw and bhw de- pending on the external data bus width, see table 5. in order to latch an address with signal ale, do as follows: while ale = h , be sure to open a latch, so the address will pass it. while ale = l , be sure to hold the address. acceptance and termination of a hold request is performed at completion of the bus cycle while the biu operates. in the hold state, a 0 a 23 , d 0 d 15 , rd, blw, bhw, ale, cs 0 cs 3 enter the floating state. at termination of the hold state, simultaneously with the timing when hlda becomes h level, the above floating state is terminated. then, bus access will be restarted 1 cycle of 1 after. in the hold state, also, the cpu operates with access to the internal area. if the cpu accesses the external area, in the hold state, the cpu stops its operation. for details, refer to the section on the chip select wait con- troller. when byte = vss level, by the register setting, each chip select area (cs 1 to cs 3 ) can have the 8-bit data bus, inde- pendently. for details, refer to the section on the chip select wait con- troller.
31 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers chip select wait controller by the control of the chip select wait controller (cswc), the chip se- lect function for the maximum of 4 blocks can be set at the bus ac- cess to the external area. also, by the setting of the cswc, port pins p9 0 to p9 3 can operate as chip select output pins (cs 0 to cs 3 ). figure 14 shows a chip select output waveform example. this chip select function determines the following items of the chip select area: start address, address s block size, wait number, exter- nal data bus width, rdy control validity, dram specification, burst rom specification, and recovery cycle insertion validity. for the external area except for areas cs 0 to cs 3 , the processor mode registers 0, 1 determine the above items. after reset is re- moved, when the microcomputer starts it s operation in the micropro- cessor mode, area cs 0 is automatically selected. table 12 lists the function of areas cs 0 to cs 3 . figure 15 shows the bit configuration of the cs 0 /cs 1 /cs 2 /cs 3 con- trol register ls. these registers determine the following items of a device to be connected: wait number, external data bus width ( note 1: the external data bus width of area cs 0 is determined by pin byte s level.), rdy control validity, dram space specification ( note 2: for area cs 0 , this function is invalid.), burst rom access specification, recovery cycle insertion validity. for dram access, refer to the section on the dram controller. figure 16 shows the bit configuration of the cs 0 /cs 1 /cs 2 /cs 3 con- trol register hs. these registers determine block size of an external area to be connected. for areas cs 1 and cs 2 , by selecting mode 1 with the area csk setting mode select bit, an chip select area can be set to the external area in bank 0. figure 17 shows the bit configuration of the area cs 0 /cs 1 /cs 2 /cs 3 start address registers. for details of these addresses setting, see figures 18 to 20. when area cs i is accessed 1 a 23 to a 0 ale rd, when the same area cs i is accessed sequentially 1 a 23 to a 0 ale rd, address + 2 one access cycle address one access cycle address cs i blw, bhw blw, bhw one access cycle cs i fig. 14 chip select output waveform example burst rom access for rom supporting the burst rom access, the burst rom access can be specified. the burst rom access is valid only when the ex- ternal data bus width = 16 bits with an instruction prefetched. in the other cases, the normal access is performed regardless of the con- tents of the burst rom access select bit. figure 21 shows a waveform example at burst rom access. when an instruction is prefetched from the burst rom, 8 bytes are fetched starting from an 8-byte boundary (the low-order 3 bits of ad- dress, a 2 , a 1 , a 0 = 000 ) in waveform (a). when branched, regard- less of the 8-byte boundary of the branch destination address, access starting from the 4-byte boundary (the low-order 2 bits of ad- dress, a 1 , a 0 = 00 ) is performed in waveform (b). once the 8-byte boundary has been selected, instructions will be prefetched in wave- form (a) until a branch.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 32 0 wait, 1 wait, 2 wait, or ale expansion wait (selected by bits 0, 1 at address 5e 16 .) determined by pin byte s level valid (selected by bit 2 at address 5f 16 .) not available. not available. available. cs 3 banks 2 16 to fe 16 128 kbytes, 256 kbytes, 512 kbytes, 1 mbytes, 2 mbytes, 4 mbytes, or 8 mbytes 0 wait, 1 wait, 2 wait, or ale expansion wait (selected by bits 0, 1 at address 86 16 .) valid (when dram space is specified, however, this control is invalid.) (selected by bit 2 at address 5f 16 and bit 3 at address 86 16 .) available. available. available. 0 wait, 1 wait, 2 wait, or ale expansion wait (selected by bits 0, 1 at addresses 82 16 , 84 16 .) space where start address can be set block size wait external data bus width rdy control dram space specification burst rom access (note 1) recovery cycle insertion 0 wait, 1 wait, 2 wait, or ale expansion wait (selected by bits 0, 1 at address 80 16 .) determined by pin byte s level. valid (selected by bit 2 at address 5f 16 and bit 3 at address 80 16 .) not available. available. available. cs 0 bank 0 16 128 kbytes, 512 kbytes, or 1 mbytes cs 1 , cs 2 mode 0 banks 0 16 to fe 16 128 kbytes, 256 kbytes, 512 kbytes, 1 mbytes, 2 mbytes, 4 mbytes, or 8 mbytes mode 1 bank 0 16 4 kbytes or 8 kbytes external area except for cs 0 to cs 3 table 12. function of areas cs 0 to cs 3 notes 1: burst rom access is valid only when the external data bus width is 16 bits at instruction prefetch. 2: when byte = vcc level, the external data bus width is fixed to 8 bits. valid (when dram space is specified, however, this control is invalid.) (selected by bit 2 at address 5f 16 and bit 3 at addresses 82 16 , 84 16 .) available. available. available. when byte = v ss level, 8-bit width or 16-bit width can be selected arbitrary (note 2) .
33 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 76543210 cs 0 control register l external data bus width select bit 0 : 16-bit width 1 : 8-bit width rdy control bit (note 2) 0 : rdy control is valid. 1 : rdy control is invalid. area cs 0 wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ale expansion wait (note 1) address 80 16 burst rom access select bit (note 3) 0 : normal access 1 : burst rom access recovery cycle insert select bit 0 : no recovery cycle is inserted at access to area cs 0 . 1 : recovery cycle is inserted at access to area cs 0 . cs 0 output select bit 0 : cs 0 output is disabled. (p9 0 functions as a programmble i/o port pin.) 1 : cs 0 output is enabled. (p9 0 functions as pin cs 0 .) notes 1: when the burst rom access is specified (bit 5= 1), be sure not to select 11 2 (ale expansion wait). 2: this bit is valid when the rdy input select bit (bit 2 at address 5f 16 ) = 1 . 3: while v cc level voltage is applied to pin byte, the normal access is selected regardless of this bit s contents. 76543210 cs 1 control register l cs 2 control register l cs 3 control register l external data bus width select bit 0 : 16-bit width 1 : 8-bit width (note 2) rdy control bit (note 3) 0 : rdy control is valid. 1 : rdy control is invalid. area cs j wait number select bits (j = 1 to 3) 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ale expansion wait (note 1) dram space select bit 0 : except dram space 1 : dram space address 82 16 84 16 86 16 burst rom access select bit (note 4) 0 : normal access 1 : burst rom access recovery cycle insert select bit (note 5) 0 : no recovery cycle is inserted at access to area cs j . 1 : recovery cycle is inserted at access to area cs j . cs j output select bit (j = 1 to 3) 0 : cs j output is disabled. (p9 j functions as programmable i/o port pins.) 1 : cs j output is enabled. (p9 j functions as pin cs j .) notes 1: when the dram space is specified (bit 4 = 1), fix these bits to 01 2 (1 wait). also, when the burst rom access is specified (bit 5 = 1), be sure not to select 11 2 (ale expansion wait). 2: while v cc level voltage is applied to pin byte, this bit is fixed to 1 (8-bit width). 3: this bit is valid when the rdy input select bit (bit 2 at address 5f 16 ) = 1 . also, when dram space is specified (bit 4 = 1), the rdy control is invalid regardless of this bit s contets. 4: when only the external data bus width select bit (bit 2) = 1 or while v cc level voltage is applied to pin byte, the normal access is selected regardless of this bit s contents. 5: when the dram space is specified (bit 4 = 1), fix this bit to 0 (no recovery cycle). 0 at read. fig. 15 bit configuration of cs 0 /cs 1 /cs 2 /cs 3 control register ls
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 34 fig. 16 bit configuration of cs 0 /cs 1 /cs 2 /cs 3 control register hs 76543210 cs 0 control register h area cs 0 block size select bit 0 0 0 : 0 byte (area cs 0 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : do not select. 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : do not select. 1 1 0 : do not select. 1 1 1 : do not select. address 81 16 76543210 cs 1 control register h cs 2 control register h area cs k block size select bit (k = 1, 2) address 83 16 85 16 when mode 0 is selected 0 0 0 : 0 byte (area cs k is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes when mode 1 is selected 0 0 0 : 0 byte (area cs k is invalid.) 0 0 1 : do not select. 0 1 0 : do not select. 0 1 1 : do not select. 1 0 0 : 4 kbytes 1 0 1 : 8 kbytes 1 1 0 : do not select. 1 1 1 : do not select. 76543210 cs 3 control register h area cs 3 block size select bit 0 0 0 : 0 byte (area cs 3 is invalid.) 0 0 1 : 128 kbytes 0 1 0 : 256 kbytes 0 1 1 : 512 kbytes 1 0 0 : 1 mbytes 1 0 1 : 2 mbytes 1 1 0 : 4 mbytes 1 1 1 : 8 mbytes address 87 16 area cs k setting mode select bit (k = 1, 2) 0 : mode 0 (a block can be set to 16-mbyte space in a unit of 128 kbytes.) 1 : mode 1 (a block can be set to bank 0 in a unit of 4 kbytes.) 0 at read. 0 at read. 0 at read.
35 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers area cs 0 start address register these bits determine a 8 to a 15 of the area cs 0 start address. any of the following values can be set to these bits: 10 16 , 20 16 , 40 16 , and 80 16 . (bits 0 to 3 are always 0 at read.) address 8a 16 area cs 1 start address register area cs 2 start address register when mode 0 is selected, these bits determine a 16 to a 23 of the area cs 1 /cs 2 start address. when mode 1 is selected, these bits determine a 8 to a 15 of the area cs 1 /cs 2 start address. (bit 0 is always 0 at read.) address 8c 16 8e 16 area cs 3 start address register these bits determine a 16 to a 23 of the area cs 3 start address. (bit 0 is always 0 at read.) address 90 16 note: do not set a value other than 10 16 , 20 16 , 40 16 , and 80 16 . see figure 18. note: the start address setting depends on the block size, which has been selected by the area cs 1 /cs 2 block size select bits (bits 0 to 2 at address 83 16 , bits 0 to 2 at address 85 16 ). see figures 19 and 20. note: the start address setting depends on the block size, which has been selected by the area cs 3 block size select bits (bits 0 to 2 at address 87 16 ). see figure 20. 76543210 0 at read. 76543210 0 at read. 76543210 0 at read. fig. 17 bit configuration of area cs 0 /cs 1 /cs 2 /cs 3 start address registers
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 36 fig. 18 area cs 0 0 16 128 k bytes 512 k bytes 1 mbytes start address : 1000 16 value to be set to area cs 0 start address register = 10 16 block size 128 k bytes 512 k bytes 1 mbytes start address : 2000 16 value to be set to area cs 0 start address register = 20 16 block size 128 k bytes 512 k bytes 1 mbytes start address : 4000 16 value to be set to area cs 0 start address register = 40 16 block size 128 k bytes 512 k bytes 1 mbytes start address : 8000 16 value to be set to area cs 0 start address register = 80 16 block size : area cs 0 cannot be assigned here. note: when an area where area cs 0 and the internal area overlap is accessed, the internal area will be accessed. in this case, pin cs 0 outputs h level. 1000 16 1ffff 16 7ffff 16 fffff 16 2000 16 4000 16 8000 16
37 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 19 area cs 1 /cs 2 (mode 1) 0 16 1000 16 2000 16 ( ffff 16 ) block size : 4 kbytes addresses which can be start address (address ffff 16 is not included; note 1 ) 3000 16 4000 16 5000 16 6000 16 7000 16 8000 16 0 16 2000 16 (ffff 16 ) block size : 8 kbytes addresses which can be start address (address ffff 16 is not included; note 1 ) 4000 16 6000 16 4 kbytes 8 kbytes f000 16 e0 0 0 16 8000 16 notes 1: only a 8 to a 15 of one of these addresses can be set to the area cs 1 /cs 2 start address register. do not set another address not shown here. 2: when an area where area cs 1 /cs 2 and the internal area overlap is accessed, the internal area will be accessed. in this case, pin cs 1 /cs 2 outputs h level.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 38 fig. 20 area cs 1 /cs 2 (mode 0) and area cs 3 notes 1: only a 16 to a 23 of one of these addresses can be set to the area cs 1 /cs 2 /cs 3 start address register. do not set another address not shown here. 2: when an area where area cs 1 /cs 2 /cs 3 and the internal area overlap is accessed, the internal area will be accessed. in this case, pin cs 1 /cs 2 /cs 3 outputs h level. block size : 128 kbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) : area cs 1 /cs 2 /cs 3 cannot be assigned here. (0 16 ) 20000 16 40000 16 60000 16 80000 16 a0000 16 c0000 16 e0000 16 100000 16 f60000 16 f80000 16 fa0000 16 fc0000 16 fe0000 16 ( ff0000 16 ) ( ffffff 16 ) 120000 16 block size : 256 kbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 40000 16 80000 16 c0000 16 100000 16 f80000 16 fc0000 16 ( ff0000 16 ) ( ffffff 16 ) block size : 512 kbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 80000 16 100000 16 f80000 16 ( ff0000 16 ) ( ffffff 16 ) block size : 1 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 100000 16 200000 16 300000 16 400000 16 500000 16 600000 16 700000 16 800000 16 b00000 16 c00000 16 d00000 16 e00000 16 f00000 16 ( ff0000 16 ) ( ffffff 16 ) 900000 16 a00000 16 block size : 2 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 200000 16 400000 16 600000 16 800000 16 c00000 16 e00000 16 ( ff0000 16 ) ( ffffff 16 ) a00000 16 block size : 4 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 400000 16 800000 16 c00000 16 ( ff0000 16 ) ( ffffff 16 ) block size : 8 mbytes addresses which can be start address (addresses 0 16 and ff0000 16 to ffffff 16 are not included; note 1 ) (0 16 ) 800000 16 ( ff0000 16 ) ( ffffff 16 ) : reserved area. do not access this area.
39 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 21 operating waveform example at burst rom access note: the above is applied when 0 wait is selected. (b) external address bus rd external data bus data (instruction) external data bus data (instruction) data (instruction) data (instruction) address address (a) external address bus (a 0 to a 23 ) rd external data bus (d 0 to d 7 ) data (instruction) external data bus data (instruction) data (instruction) data (instruction) 1 address address address address data (instruction) data (instruction) data (instruction) data (instruction) (d 8 to d 15 ) (a 0 to a 23 ) (d 0 to d 7 ) (d 8 to d 15 ) 1
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 40 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. interrupts table 13 shows the interrupt sources and the corresponding inter- rupt vector addresses. reset is also described as a type of interrupt in this section, too. dbc and brk instruction are interrupts used only for debugging. therefore, do not use these interrupts. interrupts other than reset, watchdog timer, zero divide, nmi, and address matching detection all have interrupt control registers. table 14 shows the addresses of the interrupt control registers, and figure 22 shows the bit configuration of the interrupt control register. the interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. also, interrupt request bits other than watchdog timer and nmi can be cleared by software. any of int 2 through int 0 interrupt requests is generated by an ex- ternal input. int 2 to int 0 are external interrupts; whether to cause an interrupt at the input level (level sense) or at the edge (edge sense) can be se- lected with the level/edge select bit. furthermore, the polarity of the interrupt input can be selected with the polarity select bit. timer and uart interrupts are described in the respective section. the priorities of interrupts when multiple interrupt requests are caused simultaneously are partially fixed by hardware, but, the other can be adjusted by software as shown in figure 23. the hardware priority is fixed as the following: reset > nmi > watchdog timer > other interrupts interrupts dma3 dma2 dma1 dma0 address matching detection interrupt int 4 external interrupt int 3 external interrupt a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 external interrupt int 1 external interrupt int 0 external interrupt nmi external interrupt watchdog timer dbc (do not select.) break instruction (do not select.) zero divide reset table 13 interrupt sources and interrupt vector addresses vector addresses 00ffc0 16 00ffc1 16 00ffc2 16 00ffc3 16 00ffc4 16 00ffc5 16 00ffc6 16 00ffc7 16 00ffca 16 00ffcb 16 00ffd0 16 00ffd1 16 00ffd2 16 00ffd3 16 00ffd4 16 00ffd5 16 00ffd6 16 00ffd7 16 00ffd8 16 00ffd9 16 00ffda 16 00ffdb 16 00ffdc 16 00ffdd 16 00ffde 16 00ffdf 16 00ffe0 16 00ffe1 16 00ffe2 16 00ffe3 16 00ffe4 16 00ffe5 16 00ffe6 16 00ffe7 16 00ffe8 16 00ffe9 16 00ffea 16 00ffeb 16 00ffec 16 00ffed 16 00ffee 16 00ffef 16 00fff0 16 00fff1 16 00fff2 16 00fff3 16 00fff4 16 00fff5 16 00fff6 16 00fff7 16 00fff8 16 00fff9 16 00fffa 16 00fffb 16 00fffc 16 00fffd 16 00fffe 16 00ffff 16 fig. 22 bit configuration of interrupt control register 76543210 interrupt priority level interrupt request bit 0 : no interrupt requested 1 : interrupt requested 76543210 interrupt priority level interrupt request bit 0 : no interrupt requested 1 : interrupt requested polarity select bit 0 : interrupt request bit is set to ??at ??level when level sense is selected; this bit is set to ??at falling edge when edge sense is selected. 1 : interrupt request bit is set to ??at ??level when level sense is selected; this bit is set to ??at rising edge when edge sense is selected. level/edge select bit 0 : edge sense 1 : level sense bit configuration of interrupt control registers for dma0 to dma3, a-d converter, uart0, uart1, timers a0 to a4, and timers b0 to b2, and int 3 , int 4 . bit configuration of interrupt control registers for int 0 ?int 2.
41 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. interrupts caused by the address matching detection and when di- viding by zero are software interrupts and are not included in figure 23. other interrupts previously mentioned are a-d converter, uart, etc. interrupts. the priority of these interrupts can be changed by chang- ing the priority level in the corresponding interrupt control register by software. figure 24 shows a diagram of the interrupt priority detection circuit. when an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. if the pri- orities are the same, the one above has priority. this comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. finally the selected interrupt is compared with the processor interrupt priority level (ipl) contained in the processor status register (ps) and the request is accepted if it is higher than ipl and the interrupt disable flag i is ?? the request is not accepted if flag i is ?? the reset, nmi, and watchdog timer interrupts are not affected by the interrupt dis- able flag i. when an interrupt is accepted, the contents of the processor status register (ps) is saved to the stack and the interrupt disable flag i is set to ?? furthermore, the interrupt request bit of the accepted interrupt is cleared to ??and the processor interrupt priority level (ipl) in the processor status register (ps) is replaced by the priority level of the accepted interrupt. therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag i to ??and enable further interrupts. for reset, watchdog timer, zero divide, nmi, and address match de- table 14. addresses of interrupt control registers interrupt control registers int 3 interrupt control register int 4 interrupt control register a-d interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register dma0 interrupt control register dma1 interrupt control register dma2 interrupt control register dma3 interrupt control register addresses 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 tection interrupts, which do not have an interrupt control register, the processor interrupt level (ipl) is set as shown in table 15. the interrupt request bit and the interrupt priority level of each inter- rupt source are sampled and latched at each operation code fetch cycle while is ?? however, no sampling pulse is generated until the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. the detection of an interrupt which has the highest priority is performed during that time. fig. 23 interrupt priority fig. 24 interrupt priority detection watchdog timer nmi priority is determined by hardware a-d converter, uart, etc. interrupts priority can be changed by software inside ? . reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ??? reset a-d uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 nmi watchdog timer ipl interrupt request level 0 interrupt disable flag i int 3 int 1 int 2 int 1 int 0 int 4 dma1 dma0 dma2 dma3
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 42 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. as shown in figure 25, there are three different interrupt priority de- tection time from which one is selected by software. after the se- lected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been com- pleted. the time is selected with bits 4 and 5 of the processor mode register 0 (address 5e 16 ) shown in figure 26. table 16 shows the relation- ship between these bits and the number of cycles. after a reset, the processor mode register 0 is initialized to 00 16. therefore, the long- est time is automatically set, however, the shortest time must be se- lected by software. table 15. value loaded in processor interrupt level (ipl) during an interrupt interrupt types reset watchdog timer nmi zero divide address matching detection setting value 0 7 7 not change value of ipl. not change value of ipl. table 16. relationship between interrupt priority detection time select bit and number of cycles priority detection time select bit bit 5 0 0 1 bit 4 0 1 0 7 cycles of 4 cycles of 2 cycles of number of cycles (note) fig. 25 interrupt priority detection time operation code fetch cycle sampling pulse priority detection time select one between 0 to 2 with bits 4 and 5 of processor mode register 0 ? ? ? ? ? ? ? ? ? ? ? ? 0 1 2
43 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 26 bit configuration of processor mode register 0 76543210 processor mode register 0 processor mode bits 0 0 : single-chip mode 0 1 : memory expansion mode 1 0 : microprocessor mode 1 1 : do not select. interrupt priority detection time select bits 0 0 : 7 cycles of 0 1 : 4 cycles of 1 0 : 2 cycles of 1 1 : do not select. software reset bit by a write of 1 to this bit, the microcomputer will be reset, and then, restarted. external bus wait number select bits 0 0 : 0 wait 0 1 : 1 wait 1 0 : 2 wait 1 1 : ale expansion wait clock 1 output select bit 0 : 1 output is disabled. (p4 1 functions as a programmable i/o port pin.) 1 : 1 output is enabled. (p4 1 functions as the clock 1 output pin.) address 5e 16
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 44 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. timer there are eight 16-bit timers. they are divided by type into timer a(5) and timer b(3). the timer i/o pins are multiplexed with i/o pins for port p5 and p6. to use these pins as timer input pins, the port direction register bit corresponding to the pin must be cleared to 0 to specify input mode. timer a figure 27 shows a block diagram of timer a. timer a has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. the mode is se- lected with bits 0 and 1 of the timer ai mode register (i = 0 to 4). each of these modes is described below. figure 28 shows the bit configuration of the timer a clock division se- lect register. timers a0 to a4 use the count source which has been selected by bits 0 and 1 of this register. (1) timer mode [00] figure 29 shows the bit configuration of the timer ai mode register during timer mode. bits 0, 1 and 5 of the timer ai mode register must be 0 in timer mode. the timer a s count source is selected by bits 6 and 7 of the timer ai mode register and the contents of the timer a clock division select register. (see table 17.) the counting of the selected clock starts when the count start bit is 1 and stops when it is 0 . figure 30 shows the bit configuration of the count start bit. the counter is decremented, an interrupt is caused and the interrupt re- quest bit in the timer ai interrupt control register is set when the con- tents becomes 0000 16 . at the same time, the contents of the reload register is transferred to the counter and count is continued. fig. 27 block diagram of timer a timer one-shot pulse pulse width count start register (address 40 16 ) countdown data bus (odd) data bus (even) reload register(16) counter (16) (low-order 8 bits) (high-order 8 bits) countdown is always selected when not in the event counter mode. timer a0 47 16 46 16 timer a1 49 16 48 16 timer a2 4b 16 4a 16 timer a3 4d 16 4c 16 timer a4 4f 16 4e 16 countup/countdown switching toggle flip-flop up-down register (address 44 16 ) polarity selection addresses external trigger event counter tai in (i = 0 4) tai out (i = 0 4) timer (gate function) count source select bits pulse output f 1( ) f 2 f 16 f 64 f 512 f 4096 timer a clock division select bit
45 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. when bit 2 of the timer ai mode register is 1 , the output is gener- ated from tai out pin. the output is toggled each time the contents of the counter reaches to 0000 16 . when the contents of the count start bit is 0 , l is output from tai out pin. when bit 2 is 0 , tai out can be used as a normal port pin. when bit 4 is 0 , tai in can be used as a normal port pin. when bit 4 is 1 , counting is performed only while the input signal from the tai in pin is h or l as shown in figure 31. therefore, this can be used to measure the pulse width of the tai in input signal. whether to count while the input signal is h or while it is l is de- termined by bit 3. if bit 3 is 1 , counting is performed while the tai in pin input signal is h and if bit 3 is 0 , counting is performed while it is l . note that, the duration of h or l on the tai in pin must be 2 or more cycles of the timer count source. when data is written to timer ai register with timer ai halted, the same data is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. when the value set in the timer ai register is n, the timer frequency division ratio is 1/(n+1). 0 0 : always 00 in timer mode 0 : no pulse output (tai out is normal port pin.) 1 : pulse output 0 : no gate function (tai in is normal port pin.) 1 0 : count only while tai in input is l . 1 1 : count only while tai in input is h . 0 : always 0 in timer mode. clock source select bits see table 17. timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register 7 00 6543210 addresses 56 16 57 16 58 16 59 16 5a 16 0 fig. 29 bit configuration of timer ai mode register during timer mode fig. 28 bit configuration of timer a clock division select register table 17. relationship between timer a clock division select bits, clock source select bits, and count source timer a clock division select bit (see table 17.) 76543210 timer a clock division select register address 45 16 0 at read. 000000 clock source select bits (bits 7 and 6 at addresses 56 16 to 5a 16 ) 1 0 0 0 0 1 timer a clock division select bits (bits 1 and 0 at address 45 16 ) f 2 f 16 f 64 1 1 f 512 00 f 1( ) f 16 f 64 f 4096 01 f 1( ) f 64 f 512 f 4096 10 11 do not select. note: timers a0 to a4 use the same clock, which is selected by the timer a clock division select bits.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 46 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 30 bit configuration of count start register fig. 31 count waveform when gate function is available 76543210 timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit count start register (stop at 0 , start at 1 ) address 40 16 selected clock source fi tai in bit 4 bit 3 10 timer mode register bit 4 bit 3 11 timer mode register
47 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. (2) event counter mode [01] figure 32 shows the bit configuration of the timer ai mode register during event counter mode. in event counter mode, bit 0 of the timer ai mode register must be 1 and bits 1 and 5 must be 0 . the input signal from the tai in pin is counted when the count start bit shown in figure 30 is 1 and counting is stopped when it is 0 . count is performed at the fall of the input signal when bit 3 is 0 and at the rise of the signal when it is 1 . in event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the tai out pin. when bit 4 of the timer ai mode register is 0 , the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is 0 and increment when it is 1 ). figure 33 shows the bit configuration of the up-down register. when bit 4 of the timer ai mode register is 1 , the input signal from the tai out pin is used to determine whether to increment or decre- ment the count. however, note that bit 2 must be 0 if bit 4 is 1. it is because if bit 2 is 1 , tai out pin becomes an output pin to output pulses. the count is decremented when the input signal from the tai out pin is l and incremented when it is h . determine the level of the input signal from the tai out pin before a valid edge is input to the tai in pin. an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or ffff 16 (increment count). at the same time, the contents of the reload register is transferred to the counter and the count is continued. when bit 2 is 1, each time the counter reaches 0000 16 (decrement count) or ffff 16 (increment count), the waveform s polarity is re- versed and is output from tai out pin. if bit 2 is 0 , tai out pin can be used as a normal port pin. however, if bit 4 is 1 and the tai out pin is used as an output pin, the output from the pin changes the count direction. therefore, bit 4 must be 0 unless the output from the tai out pin is to be used to se- lect the count direction. fig. 32 bit configuration of timer ai mode register during event counter mode fig. 33 bit configuration of up-down register 76543210 1 0 0 0 1 : always 01 in event counter mode 0 : no pulse output 1 : pulse output 0 : count at the falling edge of input signal 1 : count at the rising edge of input signal 0 : increment or decrement according to up/down bit 1 : increment or decrement according to tai out pin input signal level 0 : always 0 in event counter mode : not used in event counter mode timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16 timer a0 up-down bit timer a1 up-down bit timer a2 up-down bit timer a3 up-down bit timer a4 up-down bit timer a2 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a3 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a4 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode up-down register 76543210 address 44 16
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 48 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. nored. (see figure 36.) note that bits 5, 6, and 7 of the up-down reg- ister (address 44 16 ) are the two-phase pulse signal processing se- lect bits for timers a2, a3 and a4 respectively. each timer operates in normal event counter mode when the corresponding bit is 0 and performs two-phase pulse signal processing when it is 1 . count is started by setting the count start bit to 1 . data write and read are performed in the same way as for normal event counter mode. note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. also, there can be no pulse output in this mode. data write and data read are performed in the same way as for timer mode. that is, when data is written to timer ai halted, it is also writ- ten to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. the counter can be read at any time. in event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer a2, a3, or a4. there are two types of two-phase pulse processing operations. one uses timers a2 and a3, and the other uses timer a4. in both processing operations, two pulses described above are input to the ta jout (j = 2 to 4) pin and taj in pin respectively. when timers a2 and a3 are used, as shown in figure 34, the count is incremented when a rising edge is input to the tak in pin after the level of tak out (k=2, 3) pin changes from l to h , and when the falling edge is input, the count is decremented. for timer a4, as shown in figure 35, when a phase-related pulse with a rising edge input to the ta4 in pin is input after the level of ta4 out pin changes from l to h , the count is incremented at the respective rising edge and falling edge of the ta4 out pin and ta4 in pin. when a phase-related pulse with a falling edge input to the ta4 out pin is input after the level of ta4 in pin changes from h to l , the count is decremented at the respective rising edge and falling edge of the ta4 in pin and ta4 out pin. when performing this two-phase pulse signal processing, timer aj mode register bit 0 and bit 4 must be set to 1 and bits 1, 2, 3, and 5 must be 0 . bits 6 and 7 are ig- fig. 36 bit configuration of timer aj mode register when performing two-phase pulse signal processing in event counter mode fig. 34 two-phase pulse processing operation of timers a2 and a3 fig. 35 two-phase pulse processing operation of timer a4 76543210 1 0 0 0 1 0 0 1 : always 01 in event counter mode 0 1 0 0 : always 0100 when processing two-phase pulse signal : not used in event counter mode timer a2 mode register timer a3 mode register timer a4 mode register addresses 58 16 59 16 5a 16 tak out tak in (k = 2, 3) increment- count increment- count increment- count decrement- count decrement- count decrement- count ta4 out ta4 in decrement-count at each edge increment-count at each edge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? decrement-count at each edge increment-count at each edge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
49 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. (3) one-shot pulse mode [10] figure 37 shows the bit configuration of the timer ai mode register during one-shot pulse mode. in one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1 . the trigger is enabled when the count start bit is 1 . the trigger can be generated by software or it can be input from the tai in pin. soft- ware trigger is selected when bit 4 is 0 and the input signal from the tai in pin is used as the trigger when it is 1 . bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when it is 1 . software trigger is generated by setting 1 to a bit in the one-shot start register. each bit corresponds to each timer. figure 38 shows the bit configuration of the one-shot start register. as shown in figure 39, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7 and the contents of the timer a clock division select register. (set table 17.) if the contents of the counter is not 0000 16 , the tai out pin goes h when a trigger signal is received. the count direction is decrement. when the counter reaches 0001 16 , the tai out pin goes l and count is stopped. the contents of the reload register is transferred to the counter. at the same time, an interrupt request signal is gener- ated and the interrupt request bit in the timer ai interrupt control reg- ister is set. this is repeated each time a trigger signal is received. the output pulse width is if the count start flag is 0 , tai out goes l . therefore, the value cor- responding to the desired pulse width must be written to timer ai be- fore setting the timer ai count start bit. as shown in figure 40, a trigger signal can be received before the operation for the previous trigger signal is completed. in this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. except when retriggering while operating, the contents of the reload register are not transferred to the counter by triggering. when retriggering, there must be at least one timer count source cycle before a new trigger can be issued. data write is performed in the same way as for timer mode. when data is written in timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. undefined data is read when timer ai is read. 1 pulse frequency of the selected clock (counter s value at the time of trigger). fig. 37 bit configuration of timer ai mode register during one-shot pulse mode fig. 38 bit configuration of one-shot start register 76543210 0 1 1 0 1 0 : always 10 in one-shot pulse mode 1 : always 1 in one-shot pulse mode 0 : software trigger 1 0 : trigger at the falling edge of tai in input 1 1 : trigger at the rising edge of tai in input 0 : always 0 in one-shot pulse mode clock source select bits (see table 17.) timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16 76543210 timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit timer a3 one-shot start bit timer a4 one-shot start bit must be fixed to 0 . one-shot start register address 42 16 0
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 50 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. fig. 39 pulse output example when external rising edge is selected fig. 40 example when trigger is re-issued during pulse output selected clock source fi tai in (rising edge) tai out example when the contents of the reload register is 0003 16 selected clock source fi tai in (rising edge) tai out example when the contents of the reload register is 0004 16
51 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. (4) pulse width modulation mode [11] figure 41 shows the bit configuration of the timer ai mode register during pulse width modulation mode. in pulse width modulation mode, bits 0, 1, and 2 must be set to 1 . bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is 0 and 8-bit length pulse width modulator is selected when it is 1 . the 16-bit length pulse width modulator is described first. the pulse width modulator can be started with a software trigger or with an input signal from a tai in pin (external trigger). the software trigger mode is selected when bit 4 is 0 . pulse width modulator is started and a pulse is output from tai out when the count start bit is set to 1 . the external trigger mode is selected when bit 4 is 1 . pulse width modulation starts when a trigger signal is input from the tai in pin when the count start bit is 1 . whether to trigger at the fall or rise of the trigger signal is determined by bit 3. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise when it is 1 . when data is written to timer ai with the pulse width modulator halted, it is written to the reload register and the counter. then when the count start bit is set to 1 and a software trigger or an external trigger is issued to start modulation, the waveform shown in figure 42 is output continuously. once modulation is started, triggers are not accepted. if the value in the reload register is m, the duration h of pulse is m and the output pulse period is (2 16 1). an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set at each fall of the output pulse. the width of the output pulse is changed by updating timer data. the update can be performed at any time. the output pulse width is changed at the rise of the pulse after data is written to the timer. the contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. undefined data is read when timer ai is read. the 8-bit length pulse width modulator is described next. the 8-bit length pulse width modulator is selected when the timer ai mode register bit 5 is 1 . the reload register and the counter are both divided into 8-bit halves. 1 selected clock frequency 1 selected clock frequency the low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. the prescaler counts the clock selected by bits 6, 7, and the contents of the timer a clock division select register. (see table 17.) a pulse is generated when the counter reaches 0000 16 as shown in figure 43. at the same time, the contents of the reload register is transferred to the counter and count is continued. fig. 41 bit configuration of timer ai mode register during pulse width modulation mode 76543210 1 1 1 1 1 : always 11 in pulse width modulation mode 1 : always 1 in pulse width modulation mode 0 : software trigger 1 0 : trigger at the falling of tai in input 1 1 : trigger at the rising of tai in input 0 : 16-bit pulse width modulator 1 : 8-bit pulse width modulator clock source select bits (see table 17.) timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register addresses 56 16 57 16 58 16 59 16 5a 16
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp 52 mitsubishi microcomputers single-chip 16-bit cmos microcomputer flash memory version preliminar y notice: this is not a final specification. some parametric limits are subject to change. high-order 8 bits of the reload register are m, the duration h of pulse is and the output pulse period is 1 selected clock frequency therefore, if the low-order 8 bits of the reload register are n, the pe- riod of the generated pulse is (n + 1). the high-order 8 bits function as an 8-bit length pulse width modula- tor using this pulse as input. the operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. if the 1 selected clock frequency 1 selected clock frequency fig. 42 16-bit length pulse width modulator output pulse example fig. 43 8-bit length pulse width modulator output pulse example selected clock source fi tai in (rising edge) tai out 1/fi (2 16 1) 1/fi (m) this trigger is not accepted example when the contents of the reload register is 0003 16 selected clock source fi tai in (falling edge) prescaler output (when n = 2) 8-bit length pulse width modulator output (when m = 2) 1/fi (n + 1) (2 8 1) 1/fi (n + 1) (m) 1/fi (n + 1) (n + 1) m. (n + 1) (2 8 1).
53 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers timer b figure 44 shows a block diagram of timer b. timer b has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. the mode is selected with bits 0 and 1 of the timer bi mode register (i=0 to 2). each of these modes is described below. (1) timer mode [00] figure 45 shows the bit configuration of the timer bi mode register during timer mode. bits 0 and 1 of the timer bi mode register must always be ??in timer mode. bits 6 and 7 are used to select the clock source. the counting of the selected clock starts when the count start bit is ??and stops when ?? as shown in figure 30, the timer bi count start bit is at the same ad- dress as the timer ai count start bit. the count is decremented, an interrupt occurs, and the interrupt request bit in the timer bi interrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register is stored in the counter and count is continued. timer bi does not have a pulse output function or a gate function like timer a. when data is written to timer bi halted, it is written to the reload reg- ister and the counter. when data is written to timer bi which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. fig. 44 block diagram of timer b data bus (odd) data bus (even) reload register (16) counter (16) count start register note: perform a write and read to/from timer bi register in the condition of 16-bit data length : data length flag (m) = 0 . (address 40 16 ) counter reset circuit (low-order 8 bits) (high-order 8 bits) addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16 event counter mode timer mode pulse period measurement/pulse width measurement mode count source select bits f 2 f 16 f 64 f 512 tbi in (i = 0 to 2) polarity selection and edge pulse generator
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 54 (2) event counter mode [01] figure 46 shows the bit configuration of the timer bi mode register during event counter mode. in event counter mode, bit 0 in the timer bi mode register must be 1 and bit 1 must be 0 . the input signal from the tbi in pin is counted when the count start bit is 1 and counting is stopped when it is 0 . count is performed at the fall of the input signal when bits 2, and 3 are 0 and at the rise of the input signal when bit 3 is 0 and bit 2 is 1 . when bit 3 is 1 and bit 2 is 0 , count is performed at the rise and fall of the input signal. data write, data read and timer interrupt are performed in the same way as for timer mode. (3) pulse period measurement/pulse width measurement mode [10] figure 47 shows the bit configuration of the timer bi mode register during pulse period measurement/pulse width measurement mode. in pulse period measurement/pulse width measurement mode, bit 0 must be 0 and bit 1 must be 1 . bits 6 and 7 are used to select the clock source. the selected clock is counted when the count start bit is 1 and counting stops when it is 0 . the pulse period measurement mode is selected when bit 3 is 0 . in pulse period measurement mode, the selected clock is counted dur- ing the interval starting at the fall of the input signal from the tbi in pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. in this case, the reload register acts as a buffer register. when bit 2 is 0 , the clock is counted from the fall of the input signal to the next fall. when bit 2 is 1 , the clock is counted from the rise of the input signal to the next rise. in the case of counting from the fall of the input signal to the next fall, counting is performed as follows. as shown in figure 48, when the fall of the input signal from tbi in pin is detected, the contents of the counter is transferred to the reload register. next, the counter is cleared and count is started from the next clock. when the fall of the next input signal is detected, the contents of the counter is trans- ferred to the reload register once more, the counter is cleared, and the count is started. the period from the fall of the input signal to the next fall is measured in this way. after the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer bi interrupt control register is set. however, no interrupt request signal is generated when the contents of the counter is trans- ferred first to the reload register after the count start bit is set to 1 . when bit 3 is 1 , the pulse width measurement mode is selected. pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the tbi in pin input signal to the next rise or from the rise of the input signal to the next fall as shown in figure 49. fig. 45 bit configuration of timer bi mode register during timer mode fig. 46 bit configuration of timer bi mode register during event counter mode fig. 47 bit configuration of timer bi mode register during pulse period measurement/pulse width measurement mode 0 0 : always 00 in timer mode : not used in timer mode and may be any not used in timer mode clock source select bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 76543210 0 0 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16 0 1 : always 01 in event counter mode 0 0 : count at the falling edge of input signal 0 1 : count at the rising edge of input signal 1 0 : count at the both falling edge and rising edge of input signal : not used in event counter mode 76543210 1 0 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16 1 0 : always 10 in pulse period measurement/pulse width measurement mode 0 0 : count from the falling edge of input signal to the next falling one 0 1 : count from the rising edge of input signal to the next rising one 1 0 : count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one timer bi overflow flag clock source select bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 76543210 0 1 timer b0 mode register timer b1 mode register timer b2 mode register addresses 5b 16 5c 16 5d 16
55 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers when timer bi is read, the contents of the reload register is read. note that in this mode, the interval between the fall of the tbi in pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. timer bi overflow flag which is bit 5 of timer bi mode register is set to 1 when the timer bi counter reaches 0000 16 , which indicates that a pulse width or pulse period is longer than that which can be mea- sured by a 16-bit length. this flag is cleared by writing data to the corresponding timer bi mode register. this flag is set to 1 at reset. fig. 48 pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one ) fig. 49 pulse width measurement mode operation selected clock source fi tbi in reload register counter counter 0 count start bit interrupt request signal selected clock source fi tbi in reload register counter counter 0 count start bit interrupt request signal
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 56 serial i/o mode select bits 0 0 0 : programmable i/o port (serial i/o is invalid.) 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart internal/external clock select bit 0 : internal clock 1 : external clock stop bit length select bit (valid in uart mode.) 0 : 1 stop bit 1 : 2 stop bits odd/even parity select bit (valid in uart mode with the parity enable bit = ??) 0 : odd parity 1 : even parity parity enable bit (valid in uart mode) 0 : no parity 1 : with parity sleep select bit (valid in uart mode) 0 : no sleep 1 : sleep 76543210 uart 0 transmit/receive mode register uart 1 transmit/receive mode register addresses 30 16 38 16 serial i/o ports two independent serial i/o ports are provided. figure 50 shows a block diagram of the serial i/o ports. bits 0 to 2 of the uarti(i = 0,1) transmit/receive mode register shown in figure 51 are used to determine whether to use port p8 as a programmable i/o port, clock synchronous serial i/o port, or asyn- chronous (uart) serial i/o port which uses start and stop bits. figures 52 and 53 show the block diagrams of the receiver/transmit- ter. figure 54 shows the bit configuration of the uarti transmit/receive control register. each communication method is described below. fig. 51 bit configuration of uarti transmit/receive mode register fig. 50 block diagram of serial i/o port uarti receive register t x d i r x d i receive control circuit transmit control circuit uarti transmit register 1/16 divider 1/2 divider 1/(n + 1) divider 1/16 divider transfer clock transfer clock uarti transmit buffer register uart clock synchronous clock synchronous clock synchronous (when internal clock selected) brg count source select bits f 2 f 16 f 64 f 512 clock synchronous (internal clock) uart d 7 d 6 d 5 d 4 d 3 d 2 d 1 uarti receive buffer register d 0 d 7 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0d 8 0 0 0 0 0 0 brgi uart0 (addresses 33 16 , 32 16 ) uart1 (addresses 3b 16 , 3a 16 ) uart0 (addresses 37 16, 36 16 ) uart1 (addresses 3f 16 , 3e 16 ) cts 0 /rts 0 clock synchronous (external clock) n = a value set into the uarti baud rate register (brgi) clk 1 cts 0 cts 0 /clk 1 clk 0 data bus (even) data bus (odd) bit converter data bus (odd) data bus (even) bit converter
57 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers data bus (odd) data bus (even) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp par no parity uarti receive register r x d i uarti receive buffer register 9-bit uart 7-bit uart 7-bit uart 8-bit uart synchronous uart 8-bit uart 9-bit uart synchronous synchronous parity 2sp 1sp 0 0 0 0 0 0 0 sp : stop bit par : parity bit fig. 52 block diagram of receiver fig. 53 block diagram of transmitter d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp par t x d i 2sp sp 1sp uart 0 data bus (odd) data bus (even) no parity 7-bit uart 9-bit uart synchronous 7-bit uart 8-bit uart 9-bit uart synchronous 8-bit uart synchronous parity sp : stop bit par : parity bit uarti transmit register uarti receive transmit register
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 58 fig. 54 bit configuration of uarti transmit/receive control register /lsb msb t x epty 76543210 r/c cs 1 cs 0 brg count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 cts/rts function select bit (note 1) 0 : cts function is selected. 1 : rts function is selected. transmit register empty flag 0 : data is present in the transmit register. (transmission is in progress.) 1 : no data is present in the transmit register. (transmission is completed.) cts/rts enable bit (note 2) 0 : cts, rts function is enabled. 1 : cts, rts function is disabled. uart receive interrupt mode select bit 0 : reception interrupt 1 : reception error interrupt clk polarity select bit (this bit is used in the clock synchronous serial i/o mode.) (note 3) 0 : at the falling edge of a transfer clock, transmit data is output; at the rising edge, receive data is input. when not in transfer, pin clk s level is h . 1 : at the rising edge of a transfer clock, transmit data is output; at the falling edge, receive data is input. when not in transfer, pin clk s level is l . transfer format select bit (this bit is used in the clock synchronous serial i/o mode.) (note 3) 0 : lsb (least significant bit) first 1 : msb (most significant bit) first 76543210 re ri oer fer per sum ti te transmit enable bit transmit buffer empty flag receive enable bit receive complete flag overrun error flag framing error flag (note 4) parity error flag (note 4) error sum flag (note 4) uart0 transmit/receive control register 0 uart1 transmit/receive control register 0 address 34 16 3c 16 uart0 transmit/receive control register 1 uart1 transmit/receive control register 1 address 35 16 3d 16 cpl notes 1: valid when the cts/rts enable bit = 0 . 2: fix this bit to 1 in uart1 transmit/receive control register 0. (uart1 is not equipped with the cts/rts function.) 3: fix this bit to 0 in uart mode or when serial i/o is invalid. 4: valid in uart mode.
59 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers clock synchronous serial communi- cation a case where communication is performed between two clock syn- chronous serial i/o ports as shown in figure 55 will be described. (the transmission side will be denoted by subscript j and the receiv- ing side will be denoted by subscript k.) bit 0 of the uartj transmit/receive mode register and uartk trans- mit/receive mode register must be set to 1 and bits 1 and 2 must be 0 . the length of the transmission data is fixed at 8 bits. bit 3 of the uartj transmit/receive mode register of the clock send- ing side is cleared to 0 to select the internal clock. bit 3 of the uartk transmit/receive mode register of the clock receiving side is set to 1 to select the external clock. bits 4, 5 and 6 are ignored in clock synchronous mode. bit 7 must always be 0 . the clock source is selected by bit 0 (cs 0 ) and bit 1 (cs 1 ) of the clock-sending-side uartj transmit/receive control register 0. as shown in figure 50, the selected clock is divided by (n + 1), then by 2, is passed through a transmission control circuit, and is output as transmission clock clkj. therefore, when the selected clock is fi, bit rate = f i / {(n + 1) 2} on the clock receiving side, the cs 0 and cs 1 bits of the uartk transmit/receive control register 0 are ignored because an external clock is selected. uart0 is equipped with the cts and rts functions. uart1 is not equipped with the cts/rts function. bit 4 of the uart0 transmit/receive control register 0 is used to de- termine whether to use cts 0 or rts 0 signal. bit 4 must be 0 when cts 0 or rts 0 signal is used. bit 4 must be 1 when cts 0 and rts 0 signals are not used. when cts 0 and rts 0 signals are not used, cts 0 /rts 0 pin can be used as a normal port pin. when using this pin as pin cts 0 /rts 0 , : if bit 2 of the uart0 transmit/receive control register 0 is cleared to 0 , cts 0 input is selected. if bit 2 is set to 1 , rts 0 output is selected. figure 56 shows the bit configuration of the cts/rts separate se- lect register. by using bit 0 of the cts/rts separate select register (cts/rts separate select bit), the function of the cts 0 /rts 0 pin can be separated into two functions. when bit 0 = 1 , the above separation is performed. when bit 0 = 0 , no separation is per- formed. when the cts 0 /rts 0 pin is separated, rts 0 function is selected. when the cts 0 /clk 1 pin is separated, cts 0 function is selected. the following describes the case where the cts and rts signals are used. when the cts and rts signals are not used, however, the cts input is not necessary, and there is no rts output. since uart1 is not equipped with the cts/rts function, uart1 is regarded as the case where the cts and rts signals are not used. fig. 55 clock synchronous serial communication uartj transmit register txdj rxdj clkj ctsj uartj transmit buffer register uartj receive buffer register uartj receive register uartj transmit/receive mode register uartj transmit/receive control register 0 uartj transmit/receive control register 1 000 0 t x epty cs 1 cs 0 re ri oer fer per cpl cpl sum ti te 0 uartk transmit register uartk transmit buffer register uartk receive buffer register uartk receive register uartk transmit/receive mode register uartk transmit/receive control register 0 uartk transmit/receive control register 1 011 0 1 t x epty msb /lsb re ri oer fer per sum ti te 0 1 txdk rxdk clkk rtsk msb /lsb
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 60 transmission transmission is started when bit 0 (tej flag: transmit enable bit) of uartj transmit/receive control register 1 is ?? bit 1 (tij flag) of one is ?? and ctsj input is ?? the tij flag indicates whether the trans- mit buffer register is empty or not. it is cleared to ??when data is written in the transmit buffer register ; it is set to ??when the con- tents of the transmit buffer register is transferred to the transmit reg- ister and the transmit buffer register becomes empty. when all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. as shown in figure 57, data is output from t x dj pin each time when transmission clock clkj changes from ? to ?? (in the clock synchronous serial i/o mode, the polarity of a transfer clock can be changed. for details, refer to the section on the selection of the transfer clock polarity.) the data is output from the least significant bit. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. the next transmission is performed succeedingly. once transmission has started, the tej flag, tij flag, and ctsj signals are ignored until data transmission completes. therefore, transmission is not interrupt when ctsj input is changed to ??during transmission. the transmission start condition indicated by tej flag, tij flag, and ctsj is checked while the t end j signal (shown in figure 57) is ?? therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tij flag is cleared to ??before thet end j signal goes ?? bit 3 (t x eptyj flag) of uartj transmit/receive control register 0 changes to ??at the next cycle just after the t end j signal goes ? and changes to ??when transmission starts. therefore, this flag can be used to determine whether data transmission has completed. when the tij flag changes from ??to ?? the interrupt request bit in the uartj transmit interrupt control register is set to ?? receive when bit 2 of the uart k transmit/receive control register 1 is set to ?? reception becomes enabled. in this case, when the clkk signal is input, the receive operation starts simultaneously with this signal. the rtsk output is ??when the rek flag is ?? when the rek flag is set to ?? the rtsk output becomes ?? this informs the transmit- ter side that reception becomes enabled. when the receive opera- tion starts, the rtsk output automatically becomes ?? when the receive operation starts, the receiver takes data from pin rxdk each time when the transmit clock (clkj) turns from ??to ?? simultaneously with reception, the contents of the receiver register is shifted bit by bit. (note that, in the clock synchronous serial communication, the polar- ity of a transfer clock can be inverted. for details, refer to the section on the polarity of the transfer clock.) when an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (rik flag) of uartk transmit/receive control regis- ter 1 is set to ?? in other words, the setting ??to the rik flag indi- cates that the receive buffer register contains the received data. at this time, if the low-order byte of the uartk receive buffer register is read out, the rtsk output turns back to ?? this indicates that the next data reception becomes enabled. bit 4 (oerk flag) of uartk transmit/receive control register 1 is set to ??when the next data is transferred from the receive register to the receive buffer register while rik flag is ?? and indicates that the next data was transferred to the receive register before the contents of the receive buffer regis- ter was read. (in other words, this indicates that an overrun error has occurred.) rik flag is automatically cleared to ??when the low-order byte of the receive buffer register is read or when the rek flag is cleared to ?? the oerk flag is cleared when the rek flag is cleared. bit 5 (ferk flag), bit 6 (perk flag), and bit 7 (sumk flag) are ignored in clock synchronous mode. as shown in figure 50, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating be- cause the receive clock is created from the transmission clock. therefore, the transmitter must be operating even when there is no need to sent data from uartk to uartj. 0 000000 76543210 cts/rts separate select bit (note) 0 : cts/rts are multiplexed. 1 : cts/rts are separate. must be 0 . cts/rts separate select register address ac 16 note: valid when the cts/rts enable bit (bit 4 at address 34 16 ) = 0 . fig. 56 bit configuration of cts/rts separate select register
61 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers transmission clock te j 1/f i (n + 1) 2 1/f i (n + 1) 2 ti j cts j write in transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 transmit register transmit buffer register stopped because te j = 0 clk j t endj t x d j t x epty j fig. 57 clock synchronous serial i/o timing interrupt request at completion of reception when the rik flag changes from 0 to 1 , in other words, when the receive operation is completed, the interrupt request bit of the uartk receive interrupt control register can be set to 1 . the timing when this interrupt request bit is to be set to 1 can be selected from the following: each reception when an error occurs at reception if bit 5 of the uartk transmit/receive control register 0 (uartk re- ceive interrupt mode select bit) is cleared to 0 , the interrupt request bit is set to 1 at each reception. if bit 5 is set to 1 , the interrupt re- quest bit is set to 1 only when an error occurs. (in the clock syn- chronous serial communication, only when an overrun error occurs, the interrupt request bit is set to 1 .) note that a dma request is affected by the uart receive interrupt mode select bit if the uarti reception is selected as a dma request source of the dma controller. when the uartk receive interrupt mode select bit is cleared to 0 , a dma request is generated at each uart reception. when the uartk receive interrupt mode select bit is set to 1 , a dma request is generated only at normal uart reception. (in other words, no dma request is generated when an error has occurred.) polarity of transfer clock in the clock synchronous serial communication, by bit 6 of the uartj transmit/receive control register 0 (cpl), the polarity of a transfer clock can be selected. as shown in figure 58, when bit 6 = 0 , the polarity is as follows: in transmission, transmit data is output at the falling edge of clkj. in reception, receive data is input at the rising edge of clkk. when not in transfer, clki is at h level. when bit 6 = 1 , the polarity is as follows: in transmission, transmit data is output at the rising edge of clkj. in reception, receive data is input at the rising edge of clkk. when not in transfer, clki is at l level.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 62 fig. 58 polarity of transfer clock clk polarity select bit = 0 clk i txd i rxd i d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ? transmit data is output to pin txdi at the falling edge of transfer clock, and receive data is input from pin rxdi at the rising edge of transfer clock. when not in transfer, pin clki s level is h . clk polarity select bit = 1 clk i txd i rxd i d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ? transmit data is output to pin txdi at the rising edge of transfer clock, and receive data is input from pin rxdi at the falling edge of transfer clock. when not in transfer, pin clki s level is l .
63 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers selection of transfer format in clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. when bit 7 is 0 , transfer format is lsb first. when bit 7 is 1 , transfer format is msb first. this function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writ- ing transmit data to the transmit buffer register or reading receive data from the receive buffer register. accordingly, the transmitter s operation is the same in both transfer formats. figure 59 shows the connection relation. fig. 59 connection relation between transmit buffer register, receive buffer register, and data bus bit 7 in transmit/receive control register 0 write to transmit buffer register read from receive buffer register 0 (lsb first) 1 (msb first) transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 64 fig. 60 transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected fig. 61 transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected asynchronous serial communication asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. the operation is the same for all data lengths. the following is the description for 8-bit asynchronous communication. with 8-bit asynchronous communication, bit 0 of uarti transmit/re- ceive mode register is 1 , bit 1 is 0 , and bit 2 is 1 . bit 3 is used to select an internal clock or an external clock. if bit 3 is 0 , an internal clock is selected and if bit 3 is 1 , then external clock is selected. if an internal clock is selected, bit 0 (cs 0 ) and bit 1 (cs 1 ) of uarti transmit/receive control register 0 are used to select the clock source. when an internal clock is selected for asynchronous serial communication, the clki pin can be used as a normal i/o pin. the selected internal or external clock is divided by (n + 1), then by 16, and is passed through a control circuit to create the uart trans- mission clock or uart receive clock. therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. if the selected clock is an inter- nal clock pfi or an external clock f ext , bit rate = (fi or f ext ) / {(n + 1) 16} bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits. bit 5 is a select bit of odd parity or even parity. in the odd parity mode, the parity bit is adjusted so that the sum of 1s in the data and parity bit is always odd. in the even parity mode, the parity bit is adjusted so that the sum of the 1s in the data and parity bit is always even. bit 6 is the parity bit select bit which indicates whether to add parity bit or not. bits 4 to 6 must be set or reset according to the data format used in the communicating devices. bit 7 is the sleep select bit. the sleep mode is described later. the function and select method of the cts/rts pin are the same as those of the clock synchronous serial communication mode. (1/f i or 1/f ext ) (n + 1) 16 written in transmit buffer register transmission clock te i ti i cts i t endi t x d i t x epty i d 0 d 1 st start bit parity bit stop bit d 2 d 3 d 4 d 5 d 6 d 7 pspstd 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 psp std 0 d 1 transmit register transmit buffer register stopped because te i = 0 (1/f i or 1/f ext ) (n + 1) 16 written in transmit buffer register transmission clock te i ti i t endi t x d i t x epty i d 0 d 1 st d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp st d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp st d 0 d 2 d 1 transmit register transmit buffer register stopped because te i = 0 start bit stop bit stop bit
65 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers ________ once transmission has started, the tei flag, tii flag, and ctsi signal are ignored until data transmission is completed. therefore, transmission does not stop until it completes event if, dur- ing transmission, the tei flag is cleared to 0 or ctsi input is set to 1 . the transmission start condition indicated by tei flag, tii flag, and ________ ctsi is checked while the t end i signal shown in figure 60 is h . therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tii flag is cleared to 0 before the t end i signal goes h . bit 3 (t x eptyi flag) of uarti transmit/receive control register 0 changes to 1 at the next cycle just after the t end i signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission is completed. when the tii flag changes from 0 to 1 , the interrupt request bit of the uarti transmit interrupt control register is set to 1 . transmission transmission is started when bit 0 (tei flag transmit enable flag) of uarti transmit/receive control register 1 is 1 , bit 1 (tii flag) is 0 , ________ and ctsi input (in other words, transmit enable signal input from re- ceiver) is l. the tii flag indicates whether the transmit buffer is empty or not. it is cleared to 0 when data is written in the transmit buffer; it is set to 1 when the contents of the transmit buffer register is transferred to the transmit register. when all of the transmission conditions are satisfied, transmit data is transferred to the transmit register, and transmit operation starts. as shown in figures 60 and 61, data is output from the t x di pin with the stop bit or parity bit specified by bits 4 to 6 of uarti transmit/re- ceive mode register. the data is output from the least significant bit. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condi- tion is satisfied. then, the next transmission is performed succeedingly. fig. 62 receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected start bit stop bit start bit d 0 d 1 d 7 check to be l level starting at the falling edge of start bit data fetched f i or f ext re i r x d i receive clock ri i rts i
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 66 receive receive is enabled when bit 2 (rei flag) of uarti transmit/receive control register 1 is set to 1. as shown in figure 62, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received. if rtsi output is selected by setting bit 2 of uarti transmit/receive control register 0 to 1 , the rtsi output is h when the rei flag is 0 . when the rei flag changes to 1 , the rtsi output goes l to inform the receiver that reception has become enabled. when the receive operation starts, the rtsi output automatically becomes h . the entire transmission data bits are received when the start bit passes the final bit of the receive block shown in figure 52. at this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (rli flag) of uarti transmit/receive control register 1 is set to 1. in other words, the rii flag indicates that the receive buffer register contains data when it is set to 1. at this time, when the low-order byte of the uartk receive buffer register is read out, rtsi output goes back to l to indicate that the register is ready to receive the next data. bit 4 (oeri flag) of uarti transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while the rii flag is 1 , in other words, when an overrun error occurs. if the oeri flag is 1 , it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. bit 5 (feri flag) is set to 1 when the number of stop bits is less than required (framing error). bit 6 (peri flag) is set to 1 when a parity error occurs. bit 7 (sumi flag) is set to 1 when either the oeri flag, feri flag, or the peri flag is set to 1. therefore, the sumi flag can be used to determine whether there is an error. the rii, oeri, feri, and peri flags are set to 1 while transferring the contents of the receive register into the receive buffer register. the feri, peri, and sumi flags are cleared to 0 when the low-or- der byte of the receive buffer register has been read out or when 0 has been written to the rei flag. the oeri flag is cleared to 0 when 0 has been written to the rei flag. interrupt request at completion of reception when the rik flag changes from 0 to 1 , in other words, when the receive operation is completed, the interrupt request bit of the uartk receive interrupt control register can be set to 1 . the timing when this interrupt request bit is to be set to 1 can be selected from the following: each reception when an error occurs at reception if bit 5 of the uartk transmit/receive control register 0 (uart re- ceive interrupt mode select bit) is cleared to 0 , the interrupt request bit is set to 1 at each reception. if bit 5 is set to 1 , the interrupt re- quest bit is set to 1 only when an error occurs. (in the clock asyn- chronous serial communication, when an overrun error, framing error, or parity error occurs, the interrupt request bit is set to 1 .) sleep mode the sleep mode is used to communicate only between certain micro- computers when multiple microcomputers are connected through serial i/o. the microcomputer enters the sleep mode when bit 7 of uarti transmit/receive mode register is set to 1. the operation of the sleep mode for an 8-bit asynchronous commu- nication is described below. when sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn- chronous communication and bit 8 if 9-bit asynchronous communi- cation) of the received data is 0 . also the rii, oeri, feri, peri, and the sumi flags are unchanged. therefore, the interrupt request bit of the uarti receive interrupt control register is also unchanged. normal receive operation takes place when bit 7 of the received data is 1 . the following is an example of how the sleep mode can be used. the main microcomputer first sends data: bit 7 is 1 and bits 0 to 6 are set to the address of the subordinate microcomputer to be com- municated with. then all subordinate microcomputers receive this data. each subordinate microcomputer checks the received data, clears the sleep bit to 0 if bits 0 to 6 are its own address and sets the sleep bit to 1 if not. next, the main microcomputer sends data with bit 7 cleared. then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to 1 will not. in this way, the main microcomputer is able to com- municate only with the designated microcomputer.
67 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers a-d converter the a-d converter is a 10-bit successive approximation converter. figure 63 shows the block diagram of the a-d converter, figure 64 shows the bit configuration of the a-d control register 0 (address 1e 16 ), and the bit configuration of the a-d control register 1 (address 1f 16 ). a-d conversion accuracy bit 3 of a-d control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. the conversion result is regarded as 10-bit data when bit 3 is ??and as 8-bit data when bit 3 is ?? when the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result is stored in the even-numbered address of the corresponding a-d register and the high-order 2 bits are stored in bits 0 and 1 at the odd-numbered address of the corre- sponding a-d register. bits 2 to 7 of the a-d register odd-numbered fig. 63 block diagram of a-d converter address are ?00000 2 ?when read. when the conversion result is used as 8-bit data, the conversion re- sult are stored in even-numbered address of the corresponding a-d register. in this case, the value at the a-d registers odd-numbered address is ?0 16 ?when read. a-d conversion frequency an operation clock ( ad ) of an a-d converter can be selected with bit 7 of the a-d control register 0 and bit 4 of the a-d control register 1. when bit 4 of the a-d control register 1 is ?? ad becomes f 2 /4 when bit 7 of the a-d control register 0 is ?? ad becomes f 2 /2 when bit 7 of the a-d control register 0 is ?? when bit 4 of the a-d control register 1 is ?? ad becomes f 2 when bit 7 of the a-d control register 0 is ?? ad becomes f 1 when bit 7 of the a-d control register 0 is ?? note that ad = f 1 (in other words, the fastest speed) can be selected only in the 8-bit mode. ad during a-d conversion must be 250 khz or more because the comparator uses a capacity coupling amplifier. data bus (even) selector successive approximation register decoder a-d control register 0 (address 1e 16 ) resistor ladder network v ref av ss vref an 0 an 1 an 2 an 3 /ad trg comparator a-d register 0 (address 20 16 ) a-d register 1 (address 22 16 ) a-d register 2 (address 24 16 ) a-d register 3 (address 26 16 ) a-d register 0 (address 21 16 ) a-d register 1 (address 23 16 ) a-d register 2 (address 25 16 ) a-d register 3 (address 27 16 ) data bus (odd) a-d control register 1 (address 1f 16 ) 1/2 1/2 f 2 ad a-d conversion frequency selection f 1 v ref connection select bit
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 68 trigger a-d conversion can be started by software trigger or by an external input trigger. software trigger is selected when bit 5 of a-d control register 0 is 0 and an external trigger is selected when it is 1 . when a software trigger is selected, a-d conversion is started when bit 6 (a-d conver- sion start bit) is set to 1. when an external trigger is selected, the polarity of a trigger input can be selected by bit 5 of the a-d control register 1. when bit 5 = 0 , a falling edge is selected, and when bit 5 = 1 , a rising edge is selected. a-d conversion starts when the a-d conversion start bit is 1 and the ad trg input changes from h to l (or l to h. ) in this case, the pins that can be used for a-d conversion are an 0 to an 2 because the ad trg pin is multiplexed with an analog voltage input pin, an 3 . if an fig. 64 bit configuration of a-d control register 0 external trigger is selected, even when the a-d conversion is com- pleted, the a-d conversion start bit keeps 1 . also, a retrigger can be available even when a-d conversion is in progress. v ref connection whether to connect the reference voltage input (v ref ) with the resis- tor ladder network or not depends on bit 6 of the a-d control register 1. the v ref pin is connected when bit 6 is 0 and is disconnected when bit 6 is 1 (high impedance state). when a-d conversion is not performed, current from the v ref pin to the resistor ladder network can be cut off by disconnecting resistor ladder network from the v ref pin. before starting a-d conversion, wait for 1 s or more after clearing bit 6 to 0 . a-d control register 0 address 1e 16 76543210 analog input select bits (valid in the one-shot and repeat modes.) 0 0 : select an 0 0 1 : select an 1 1 0 : select an 2 1 1 : select an 3 must be 0. a-d operation mode select bits 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode trigger select bit 0 : software trigger 1 : external trigger due to ad trg input a-d conversion start bit (note 7) 0 : stop a-d conversion 1 : start a-d conversion a-d conversion frequency (
69 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers operation mode the operation mode is selected by bits 3 and 4 of a-d control regis- ter 0. the available operation modes are one-shot, repeat, single sweep, and repeat sweep. analog input port pins are multiplexed with port p7 pins. therefore, bits which correspond to pins for a-d conversion must be 0 (input mode). (1) one-shot mode one-shot mode is selected when bits 3 and 4 of a-d control register 0 are 0 is 0 . the a-d conversion pins are selected with bits 0 and 1 of a-d control register 0. when a software trigger is selected, a-d conversion is started when bit 6 (a-d conversion start bit) is set to 1 . when bit 3 of the a-d control register 1 is 1 , a-d conversion ends after 59 ad cycles, and the interrupt request bit of the a-d interrupt control register is set to 1 . at the same time, bit 6 of a-d control reg- ister 0 (a-d conversion start bit) is cleared to 0 and a-d conversion stops. the result of a-d conversion is stored in the a-d register cor- responding to the selected pin. if an external trigger is selected, a-d conversion starts when the a-d conversion start bit is 1 and a valid edge is input to the ad trg pin, this operation is the same as that for software trigger except that the a-d conversion start bit is not cleared after a-d conversion and a retrigger can be available during a-d conversion. (2) repeat mode repeat mode is selected when bit 3 of a-d control register 0 is 1 and bit 4 is 0 . the operation of this mode is the same as the operation of one-shot mode except that when a-d conversion of the selected pin is com- plete and the result is stored in the a-d register, conversion does not stop, but is repeated. no interrupt request is generated in this mode. furthermore, if a soft- ware trigger is selected, the a-d conversion start bit is not cleared. the contents of the a-d register can be read at any time. (3) single sweep mode single sweep mode is selected when bit 3 of a-d control register 0 is 0 and bit 4 is 1 . in the single sweep mode, the number of analog input pins to be swept can be selected. analog input pin is selected by bit 0 of the a- d control register 1 (address 1f 16 ). two pins, or four pins can be se- lected as analog input pins, depending on the contents of these bits. a-d conversion is performed only for selected input pins. after a-d conversion is performed for input of an 0 pin, the conversion result is stored in a-d register 0, and in the same way, a-d conversion is per- formed for selected pins one after another. after a-d conversion is performed for all selected pins, the sweep is stopped. a-d conversion can be started with a software trigger or with an ex- ternal trigger input. a software trigger is selected when bit 5 of the a- d control register 0 (address 1e 16 ) is 0 and an external trigger is selected when it is 1 . when a software trigger is selected, a-d conversion is started when bit 6 of a-d control register 0 (a-d conversion start bit) is set to 1 . when a-d conversion of all selected pins end, the interrupt request bit of the a-d conversion interrupt control register is set to 1 . at the same time, a-d conversion start bit is cleared to 0 and a-d conver- sion stops. when an external trigger is selected, a-d conversion starts when the a-d conversion start bit is 1 and a valid edge is input to the ad trg pin. in this case, the a-d conversion result which is stored in the a-d register 3 becomes invalid. the operation by external trigger is the same as that by a software trigger except that the a-d conversion start bit is not cleared to 0 after a-d conversion and that a retrigger can be available during a-d conversion. (4) repeat sweep mode repeat sweep mode is selected when bit 3 of a-d control register 0 is 1 and bit 4 is 1 . the difference from the single sweep mode is that a-d conversion does not stop after conversion for all selected pins, but repeats again from the an 0 pin. the repeat is performed among the selected pins. also, no interrupt request is generated. furthermore, if a software trigger is selected, the a-d convension start bit is not cleared. the a-d register can be read at any time. precautions for a-d conversion interrupt function clear the interrupt request bit of the a-d interrupt control register (bit 3 at address 70 16 ) before using an a-d interrupt. it is because this interrupt request bit is undefined just after reset.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 70 dma controller the dma (direct memory access) controller is a 4-channel controller which provides high-speed data transfers from memory to memory, memory to input/output ports of external devices (herein referred to as external i/o), and external i/o to memory without using the cpu. figure 65 shows the block diagram of the dma controller, figure 66 shows the dma control-related register memory map, and figure 67 shows the bit configuration of the dmac control registers l and h. dma transfers are performed by the dma control circuit via the bus interface unit (biu). each of dmac control registers l and h consists of 8 bits. for dmac control register l, bit 0 is the priority select bit, and bit 1 is the tc pin validity bit. bits 4 to 7 are dmai request bits (i = 0 to 3). read- ing these bits indicates whether a dma request for each channel has occurred or not. for dmac control register h, bits 0 to 3 are software dma request bits, and each of them is used to generate a dma re- quest by software. bits 4 to 7 are dma i enable bits (i = 0 to 3). the dma request is accepted only when the corresponding dmai enable bit is set to 1 . all of these dma i enable bits are cleared to 0 after reset removal. figure 68 shows the bit configuration of the dma i control register (i = 0 to 3). each channel of the dma i control register consists of 8 bits. bits 0 to 3 are dma request source select bits. bit 4 determines whether the edge or level sense function is to be used for selecting a request source from pin dmareq i (dma re- quest input). bit 5 is the dmaack i validity bit. when bit 5 is 0 , pin dmaack i (the dma acknowledge signal output pin) is invalid; when 1 , pin dmaack i is valid. figure 69 shows the bit configuration of the dma i mode registers l and h. each channel of both registers consists of 8 bits. refer to the corresponding section for more details. pin description pins dmareq i , dmaack i , tc are used for dma transfers. pin dmareq i is a dma request input pin. port pins p6 1 , p6 3 , p6 5 , and p6 6 are multiplexed with pins dmareq 0 , dmareq 1 , dmareq 2 and dmareq 3 , respectively. these pins are used in or- der to request a dma transfer from the external. when the dma request source select bits (bits 0 to 3) of the dma i control register are set to 0001 , the input signal from this pin be- comes the dma request signal. in order to use any of the above pin as pin dmareq i , be sure to set the corresponding bit of the port p6 direction register to the input mode. pin dmaack i is the dma acknowledge signal output pin. port pins p6 0 , p6 2 , p6 4 are multiplexed with pins dmaack 0 , dmaack 1 , and dmaack 2 , respectively. when bit 5 (dmaack i validity bit) of the dma i control register for each channel is set to 1 , pin dmaack i serves as the output-only pin for signal dmaack i . (dma3 is not equipped with pin dmaack i .) during dma transfer, the operating channel acknowledge signal is output regardless of the data transfer method (the 1-bus cycle transfer or 2-bus cycle transfer). when the acknowledge signal is not needed, clear the dmaack i validity bit to 0 , so that pin dmaack i can serve as an i/o pin. pin tc is a terminal count pin and is multiplexed with port pin p4 2 . pin tc is valid when 1 has been written to bit 1 of the dmac con- trol register l. at this time, pin tc serves as the n-channel open drain output pin. when the value of the transfer counter register or transfer block counter is 0 , pin tc outputs l level for 1 cycle of 1 . furthermore, when the tc pin validity bit is 1 , any ongoing channel dma transfer can be cancelled by changing the input level at pin tc from h to l .
71 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers tween an external i/o and the external memory, this method allows the memory to be read at the same time the data is written to the external i/o, and vice versa, resulting in fast data transfer. bit 0 of the dma i mode register h determines whether the 1-bus cycle transfer is to be made from the external memory to the external i/o or from the external i/o to the external memory. when the bit is 1 , the data transfer is made from the external i/o to the external memory. figure 71 shows an connection example with external memories and external i/os in 1-bus cycle transfer (the external data bus width = 16 bits and 1 transfer unit = 16 bits). for the transfer from the external memory to external i/o, the exter- nal-memory-side address (transfer source address) is output to the address bus, pin rd goes to l , and the read operation will be per- formed. this ensures that the data is read out from the external memory. at the same time, pin dmaack i corresponding to the operating dmai channel (i = 0 to 2) goes to l , the external i/o is selected, and the data read from the external memory is directly fetched at the rising of signal rd. in this manner, data is transferred from external memory to external i/o in 1 bus cycle. for the transfer from the external i/o to the external memory, the data is read out from the external i/o, selected by the acknowledge signal from pin dmaack i , to the data bus. at the same time, the ex- ternal-memory-side address (transfer destination address) is output to the address bus, pin blw (write signal for even-numbered ad- dresses) and pin bhw (write signal for odd-numbered addresses) go to l , and the write operation to the external memory is per- formed. the 1-bus cycle transfer cannot perform operations for a read from or a write to the internal memory. in order to perform the transfer from the internal memory to the external i/o or from the external i/o to the internal memory, be sure to select the 2-bus cycle transfer method. data transfer method two different data transfer methods are available: 2-bus cycle trans- fer, effective for memory-to-memory data transfer, and 1-bus cycle transfer, effective for memory-to-i/o or i/o-to-memory data transfer. both methods are described in detail below. (1) 2-bus cycle transfer when bit 1 of the dma i mode register l, as shown in figure 69, is cleared to 0 , the 2-bus cycle transfer method is selected. this method makes data to be transferred by the 1 transfer unit , by us- ing 1 read bus cycle and 1 write bus cycle. the 1 transfer unit re- fers to the number of bits which can be transferred in 1 dma transfer operation, and it is determined by bit 0 of the dma i mode register l. when bit 0 is cleared to 0 , 1 transfer unit consists of 16 bits (2 bytes); when 1 , 1 transfer unit consists of 8 bits (1 byte). in the 2-bus cycle transfer, be sure to clear bit 0 of the dma i mode register h to 0 . figure 70 shows an connection example with external memories in 2-bus cycle transfer. in the read cycle, the transfer source address is output to the address bus, and the data at this address is read out by the 1 transfer unit and then stored into the biu s data buffer. when 16-bit data is read out from an odd-numbered address or when 16- bit data is read out with the external data bus width = 8 bits, the mi- crocomputer will enter the write cycle after the above 16-bit data is stored into the biu s data buffer in 2 accesses. in the write cycle, the transfer destination address is output to the address bus, and the data which has been stored in the biu s data buffer is written to the transfer destination address. when 16-bit data is read out from an odd-numbered address or when 16-bit data is read out with the external data bus width = 8 bits, the microcomputer will preforms the write operation in 2 accesses. (2) 1-bus cycle transfer when bit 1 of the dma i mode register l is set to 1 , the 1-bus cycle transfer method is selected. when data transfer is to be made be- fig. 65 block diagram of dma controller internal address bus : internal bus : dma controller ? s bus internal address bus decrementer incrementer/decrementer source address register 0 (sar0) destination address register 0 (dar0) source address register 1 (sar1) destination address register 1 (dar1) source address register 2 (sar2) destination address register 2 (dar2) destination address register 3 (dar3) source address register 3 (sar3) transfer counter register 0 (tcr0) transfer counter register 1 (tcr1) transfer counter register 2 (tcr2) transfer counter register 3 (tcr3) bus interface unit (biu)
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 72 fig. 66 dma controll-related register memory map 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 address (hexadecimal notation) address (hexadecimal notation) dmac control register l dmac control register h dma0 interruput control register dma1 interruput control register dma2 interruput control register dma3 interruput control register source address register 0 destination address register 0 transfer counter register 0 dma0 mode register l dma0 mode register h dma0 control register source address register 1 destination address register 1 transfer counter register 1 dma1 mode register l dma1 mode register h dma1 control register source address register 2 destination address register 2 transfer counter register 2 dma 2 mode register l dma 2 mode register h dma 2 control register source address register 3 destination address register 3 transfer counter register 3 dma 3 mode register l dma 3 mode register h dma 3 control register l m h l m h l m h l m h l m h l m h l m h l m h l m h l m h l m h l m h
73 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 67 bit configuration of dmac control registers l and h 76543210 dmac control register l dma0 request bit 0: no request. 1: requested (note) . priority select bit 0: fixed. 1: rotating. address b0 16 dma1 request bit 0: no request. 1: requested (note) . note: even when ?? are written to bits 4 to 7 by software, these bits status do not change. 76543210 dmac control register h software dma0 request bit 1: dma request. valid when the software dma source is selected. the value is ??at reading. address b1 16 tc pin validity bit 0: invalid. pin p4 2 functions as a programmable i/o port (cmos) pin. 1: valid. pin p4 2 functions as pin tc (n-channel open-drain). dma2 request bit 0: no request. 1: requested (note) . dma3 request bit 0: no request. 1: requested (note) . software dma1 request bit 1: dma request. valid when the software dma source is selected. the value is ??at reading. software dma2 request bit 1: dma request. valid when the software dma source is selected. the value is ??at reading. software dma3 request bit 1: dma request. valid when the software dma source is selected. the value is ??at reading. dma0 enable bit 0: disabled. 1: enabled. dma1 enable bit 0: disabled. 1: enabled. dma2 enable bit 0: disabled. 1: enabled. dma3 enable bit 0: disabled. 1: enabled.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 74 fig. 68 bit configuration of dma i control register 76543210 dma0 control register dma1 control register dma2 control register dma3 control register dma request source select bits 0 0 0 0 : do not select. 0 0 0 1 : external source (dmareq i ) 0 0 1 0 : software dma source 0 0 1 1 : timer a0 0 1 0 0 : timer a1 0 1 0 1 : timer a2 0 1 1 0 : timer a3 0 1 1 1 : timer a4 1 0 0 0 : timer b0 1 0 0 1 : timer b1 1 0 1 0 : timer b2 1 0 1 1 : uart0 receive 1 1 0 0 : uart0 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : uart1 transmit 1 1 1 1 : a-d conversion address ce 16 de 16 ee 16 fe 16 edge sense/level sense select bit (note 1) (used when both of the external source and burst transfer mode are selected.) 0 : edge sense (rising edge) 1 : level sense ( l level) dmaack i validity bit (note 2) 0 : invalid. pin dmaack i functions as a programmable i/o port pin. 1 : valid. functions as pin dmaack i are valid. notes 1: be sure to fix this bit to 0 in any of the following cases: when the external source is selected by using bits 0 to 3 in the cycle steal transfer mode level sense can be selected only when both of the external source and burst transfer mode are selected. 2: dma3 is not equipped with the dmaack output function. for the dma3 control register, be sure to clear this bit to 0 . the value is 0 at reading. 00
75 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 69 bit configuration of dma i control registers l and h 76543210 transfer mode select bit 0 : burst transfer mode 1 : cycle steal transfer mode transfer-unit-bit-number select bit 0 : 16 bits 1 : 8 bits fix this bit to 0 . note: for the dma3 mode register l, be sure to fix this bit to 0 (2-bus cycle transfer). in this case, 1-bus cycle transfer cannot be used. additionally, be sure to fix this bit to 0 when either transfer source or transfer destination is in an internal area. in this case, also, 1-bus cycle transfer cannot be used. 76543210 transfer destination select bit (used in 1-bus cycle transfer.) (note) 0 : from memory to i/o 1 : from i/o to memory transfer method select bit 0 : 2-bus cycle transfer 1 : 1-bus cycle transfer (note) transfer-source-address-direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. transfer-destination-address-direction select bits 0 0 : fixed 0 1 : forward 1 0 : backward 1 1 : do not select. the value is 0 at reading. fix this bit to 0 . the value is 0 at reading. operating mode select bits 0 0 : single transfer 0 1 : repeat transfer 1 0 : array chain transfer 1 1 : link array chain transfer dma0 mode register l dma1 mode register l dma2 mode register l dma3 mode register l address cc 16 dc 16 ec 16 fc 16 0 dma0 mode register h dma1 mode register h dma2 mode register h dma3 mode register h address cd 16 dd 16 ed 16 fd 16 0 0 note: be sure to fix this bit to 0 in 2-bus cycle transfer. 0 0 0
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 76 fig. 70 connection example with external memories in 2-bus cycle transfer fig. 71 connection example with external memories and external i/os in 1-bus cycle transfer m37920 address bus data bus (d 8 to d 15 ) data bus (d 0 to d 7 ) rd bhw blw note: external circuits are not considered. address (transfer source) data (read) data (write) address (transfer destination) blw, bhw rd transfer source memory (even-numbered address) transfer destination memory (even-numbered address) transfer source memory (odd-numbered address) transfer destination memory (odd-numbered address) dmaack i address (memory) data (read) dmaack i rd i/o m37920 address bus data bus (d 8 to d 15 ) data bus (d 0 to d 7 ) rd bhw blw dmaack j dmareq j i/o notes 1: external circuits are not considered. 2: when the external data bus width = 16 bits and 1 transfer unit = 8 bits, 1-bus cycle transfer cannot be used for the transfer between a memory and i/o if they are connected to the different data buses (d 0 to d 7 , d 8 to d 15 ), one for one. write/read acknowledge dma dma request write/read acknowledge dma dma request j = 0 to 2 memory (even-number- ed address) memory (odd-numbered address)
77 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers dma request sources one out of fifteen dma request sources can be selected for each channel. there are a total of fifteen dma request sources. thirteen internal request sources (a-d conversion, uart0 transmit/receive, uart1 transmit/receive, timers a0 to a4, timers b0 to b2), one soft- ware dma source issued by programs, and one external source by input to pin dmareq i . for dma request source selection, use the dmai control register s dmai request source select bits (bits 0 to 3) as shown in figure 68. table 18 lists the relationship between dma request source select bits (bits 0 to 3) and dma request sources. the request timing is the same as that for interrupts. when the software dma request source is selected with the dma re- quest source select bits, by writing 1 to any of the dmac control register h s software dma request bits (bits 0 through 3), the correspomding dma request bit is set to 1 . when a dma request bit has been set to 1 , the software dma request bits are automati- cally cleared to 0 . when the external source is selected with the dma request source select bits, the input from pin dmareq i sets the correspomding dma request bit to 1 . the dma transfer request will not be accepted until both of the dma request bit and dma en- able bit of the dmac control registers l and h are 1 . therefore, if the dma enable bit is 0 , no dma request will be accepted even when the dma request bit is 1 . note that the dma enable bit is 0 at reset. therefore, after the dma transfer parameter and other data have been setup, be sure to set the dma enable bit of the dma channel to be rendered valid to 1 . this assures that the transfer request of that channel becomes valid, making the dma transfer enabled. transfer mode two dma transfer modes are available: burst transfer mode and cycle steal transfer mode. mode selection is made variously for each channele, using bit 2 of the dmai mode register l. when this bit is cleared to 0 , the burst transfer mode is selected. this mode is au- tomatically selected after reset removal. (1) burst transfer mode in the burst transfer mode, either the edge sense or level sense mode can be selected only when the input from pin dmareq i (ex- b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 dma request source do not select. external source (dmareq i ) software dma source timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 uart0 receive uart0 transmit uart1 receive uart1 transmit a-d conversion table 18. relationship between dma request source select bits (bits 3 to 0) and dma request sources ternal source) is selected as a request source. when the dmai control register s bit 4 is cleared to 0 , the edge sense mode is selected. the edge sense mode is automatically se- lected after reset removal. in the edge sense mode, the dma re- quest bit is set to 1 at the falling edge of the input from pin dmareq i . in the burst transfer s edge sense mode, the dma re- quest bit is cleared to 0 when any of the following conditions is sat- isfied. 1. channel i s dma enable bit is cleared to 0 (forced termination of transfer). 2. channel i s dma request bit is cleared to 0 . 3. all of channel i s dma transfers are completed (normal termination of transfer). 4. l level is input to pin tc during channel i s transfer (forced termi- nation of transfer). figure 72 shows a burst transfer example in edge sense mode. when a dma request is received from a certain channel in the edge sense mode s burst transfer, no dma request from the other chan- nels will be accepted until the dma transfer on the former channel is completed. in this example, pin dmareq i s input (external source) is selected as the dma request source. when pin dmareq i s input changes from the h to l level during cpu operation, the dma request bit will be set to 1 and the dma controller will acquire the right to use bus and initiate transfer. from high to low, the bus use priority is for dram refresh, hold, dma controller, and cpu. therefore, if a request is made by the dram refresh, which has a higher priority than the dma controller, the dma controller halts any ongoing transfer operation at the end of the current transfer bus cycle and passes the right to use bus to the dram controller as shown in figure 72. upon getting the right, the dram controller gen- erates the refresh cycle. when refreshing is terminated, the dma controller resumes the execution of the interrupted dma transfer at the point of interruption. once a dma request is accepted in the burst transfer mode, no request from the other channels is accepted until the dma transfer is entirely completed or the transfer operation is brought to a forced stop. therefore, even when the request bit of channel 0, which has a high priority, is set to 1 in the middle of transfer as shown in figure 72, such a request will not be accepted. (the priority is explained in the next section.)
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 78 fig. 72 burst transfer example (in edge sense mode) dmareq 0 dma0 request bit dma0 enable bit dma1 dma1 dma0 channel 0 entire data transfer channel 1 entire data transfer the above example applies on the following conditions : dma1 (cpu) (cpu) dmareq 1 dma1 request bit dma1 enable bit dram refresh request bus user refresh dram dma request sources of dma0 and dma1: external source (edge sense) channel priority : fixed (channel 0 > channel 1) fig. 73 burst transfer example (in level sense mode) dmareq 0 dma0 request bit dma0 enable bit (cpu) dma1 (cpu) dma1 (cpu) the above example applies on the following conditions : dma request sources of dma0 and dma1: external source (level sense) channel priority : fixed (channel 0 > channel 1) dma0 dmareq 1 dma1 request bit dma1 enable bit dram refresh request bus user refresh dram when channel 1 s dma transfer is entirely completed, the right to use bus is once passed to the cpu, and the dma transfer request from channel 0 is later accepted at the end of the current bus cycle. when bit 4 of the dmai control register is set to 1 , the level sense mode is selected. the level sense mode can be used only for the dma request from pin dmareq i . when selecting another source, be sure to select the edge sense mode. in the level sense mode, the dmai request bit is set to 1 to initiate the dma transfer only while pin dmareq i s input level is l . if pin dmareq i s input level returns to h in the middie of transfer, the dma operation is interrupted at the end of the current transfer bus cycle or next transfer bus cycle so that the right to use bus is re- turned to the cpu. at this time, the dma enable bit is not cleared. when pin dmareq i s input level returns to l , the transfer opera- tion is resumed at the address which is next to the point of interrup- tion. in the level sense mode, the dma request bit varies only with the input level at pin dmareq i . therefore, while pin dmareq i s in- put level is l , the dma request bit remains to be 1 even if the transfer is completed. figure 73 shows a burst transfer example in level sense mode. when pin dmareq i s input level for channel 1 changes from h to l during cpu operation, the dma1 request bit will be set to 1 so that the dma controller will acquire the right to use bus and initiate transfer. when pin dmareq i s input level returns to h , the dma1 request bit is cleared to 0 . this causes the dma transfer operation to be interrupted and returns the right to use bus to the cpu.
79 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 74 example of cycle steal transfer dmareq 0 dma0 request bit dma0 enable bit (cpu) dma1 (cpu) (cpu) the above example applies on the following conditions : ?dma request sources of dma0 and dma1: external source ?channel priority : fixed (channel 0 > channel 1) dma0 dma1 dma0 dma1 dma1 dmareq 1 dma1 request bit dma1 enable bit dram refresh request bus user dram refresh (2) cycle steal transfer mode when bit 2 of the dmai mode register l is set to ?? the cycle steal transfer mode is selected. in the cycle steal transfer mode, be sure to select the edge sense mode. when a dma request occurs in the cycle steal transfer mode, the corresponding dma request bit is set to ??as in the burst transfer mode. when the dma request from the channel is accepted, dma transfer starts. however, the dma request bit is automatically cleared to ??at the start of the first dma transfer cycle. therefore, if there is no dma request from any channel when 1-transfer-unit data has been transferred, the dma controller returns the right to use bus to the cpu. if there is a dma request from a channel, the dma con- troller continues to use the bus and initiates dma transfer for the channel. in the cycle steal transfer mode, the priorities of the chan- nels are detected at all times to assure that the dma request from a channel having the highest priority is accepted to initiate the dma transfer execution. the dma request bit is cleared to ?? at each time when 1-transfer-unit data has been transferred. at this time, however, the dma enable bit will not be cleared to ??although the dma request bit is cleared to ??at each transfer of 1 transfer unit. therefore, when the dma request bit is set to ??next, transfer is re- sumed at the point of interruption. when the transfer counter registers value is ??in the single transfer, or when both of the trans- fer counter registers value and transfer block counters value are ? in the array chain transfer, the dma enable bit will be cleared to ? to terminate the whole dma transfer operation. figure 74 shows an example of cycle steal transfer. when pin dmareq i s input level changes from ??to ?? the dma1 request bit will be set to ??and the dma controller will acquire the right to use bus and initiate dma transfer. the dma1 request bit is cleared to ??when the channel 1 transfer cycle starts. therefore, if there is no dma transfer request from the other channels, the dma control- ler returns the right to use bus to the cpu at the end of 1 transfer cycle. in the example shown in figure 74, however, dma0 transfer cycle execution continues because the channel 0s request bit is set to ?? when the dma0 transfer cycle is terminated, the dma re- quest bits of all channels are cleared to ??so that the dma control- ler returns the right to use bus to the cpu. when the dma1 request bit is set to ?? only one cycle of transfer operation is performed. even if the dma1 request bit is cleared to ??at this time, the dma1 request bit is set to ??again to perform continuous transfer, as long as pin dmareq i s input level goes ??before the end of the next transfer cycle. in the cycle steal transfer, the priorities of individual channels are detected at the end of each transfer cycle. therefore, if the request is issued from channel 0, which has a higher priority than channel 1, channel 0 transfer is executed first. furthermore, if a re- quest to use bus which has a higher priority (for example, a refresh request from the dram controller) is generated, this request takes the precedence.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 80 priority priorities are assigned to all dma channels. either the fixed or rota- tive priority can be selected. when bit 0 (priority select bit) of the dmac control register is cleared to ?? the fixed priority is selected. note that the fixed priority is automatically selected after the reset removal. in the fixed priority, the channels are given fixed priorities and dma transfer is executed in the order of priority. from high to low, the priorities are assigned to channels 0, 1, 2, and 3. as indi- cated in figure 76, the priorities are detected at each cycle in the cycle steal transfer mode or when the first dma request is accepted in the burst transfer mode. when bit 0 of the dmac control register is set to ?? the rotative pri- fig. 75 rotative priority channel 0 channel 0 channel 1 channel 1 channel 3 channel 1 channel 1 channel 2 channel 2 channel 0 channel 2 channel 2 channel 3 channel 3 channel 1 channel 3 channel 3 channel 0 channel 0 channel 2 (1) before start of transfer (after reset removal) (2) after completion of channel 0 s transfer (3) after completion of channel 2 s transfer ority is selected. from high to low, the initial priorities are assigned to channels 0, 1, 2, and 3 as is the case with the fixed priority. when a dma transfer for one channel is normally terminated with the rota- tive priority employed, the priorities are rotated in such a manner that the channel, for which transfer has just been completed, has the low- est priority. for example, when channel 0 s transfer is normally ter- minated as shown in figure 75, the priorities are rotated upon completion of transfer so that the new priorities are, in decreasing order, channel 1, channel 2, channel 3, and channel 0. the priorities remain unchanged when dma transfer is forcibly terminated by pin tc s input or the dma enable bit clearance, etc.
81 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 76 example of channel priority detection priority level: fixed dma0 request bit dma1 request bit dma2 request bit dma3 request bit channel priority : 0 > 1 > 2 > 3 dma-transfer-executing channel 12 0 13 (none) 021 1 03 priority level: rotating 1 dma0 request bit dma1 request bit dma2 request bit dma3 request bit channel priority dma-transfer-executing channel 12 3 13 (none) 023 1 33 0 > 1 > 2 > 3 2 > 3 > 0 > 1 3 > 0 > 1 > 2 0 > 1 > 2 > 3 2 > 3 > 0 > 1 0 > 1 > 2 > 3 0 > 1 > 2 > 3 1 > 2 > 3 > 0 3 > 0 > 1 > 2 0 > 1 > 2 > 3 2 > 3 > 0 > 1 0 > 1 > 2 > 3 the above applies on the following conditions : ?no dram refresh request, no hold request. ?all of dmai enable bits are ?? 1
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 82 transfer address direction the address direction in dma transfers can be designated indepen- dently for the transfer source and destination. these directions are available: forward , backward , and fixed . when the forward di- rection is selected, the address increments. when the backward di- rection is selected, the address decrements. when the fixed direction is selected, the address is fixed (2 bytes when 1 transfer unit consists of 16 bits, or 1 byte when 1 transfer unit consists of 8 bits) and does not change. use bits 4 and 5 of the dmai mode regis- ter l shown in figure 69 to specify the transfer address direction for the transfer source. for the transfer destination, use bits 6 and 7. figure 77 shows an example of transfer address direction in the 2- bus cycle transfer (1 transfer unit = 16 bits). figure 77-(1) shows an example when the transfer source address direction is forward and the destination addresses are fixed . in this setup, the transfer source memory s data is called up in the forward address direction and written to the transfer destination memory s fixed address by the 1 transfer unit . figure 77-(2) shows an example when both the transfer source and destination address directions are set to for- ward by using the dmai mode register l. in this type of setup, data are transferred from the transfer source memory to the transfer des- tination memory in the sequence of ? ? ? forward and the destination address direction is backward . figure 77-(4) shows an example when the transfer source address direction is backward and the destination address is fixed . in this setup, the transfer source memory s data is written to the fixed transfer desti- nation memory s address by the 1 transfer unit in the sequence of ? ? ? s address direction depends on the memory bits. for data transfer from memory to external i/o, therefore, use bits 4 and 5 (transfer-source-address-direction select bits) of the dmai mode register l to determine the memory side s (transfer source) address direction. this is not affected by bits 6 and 7 (transfer-destination-address-direction select bits). for data trans- fer from external i/o to memory, use bits 6 and 7 of the dmai mode register l to determine the memory side s (transfer destination) ad- dress direction. this is not affected by bits 4 and 5.
83 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 77 example of address directions and transfer results in 2-bus cycle transfer (1 transfer unit = 16 bits) transfer source address direction transfer destination transfer unit: 16 bits (note) transfer unit: 8 bits data arrangement in transfer destination memory (transfer result) data arrangement in transfer destination memory (transfer result) data arrangement in transfer source memory data arrangement in transfer source memory transfer order transfer order external data bus width: 16 bits or 8 bits (1) forward (2) forward forward (3) forward backward (4) backward fixed 1 high order low order high order low order data 1 high order low order data 2 high order low order data 3 high order low order data 1 high order low order data 2 high order low order data 3 high order low order data 1 high order low order data 2 high order low order data 3 high order low order data 3 high order low order data 2 high order low order data 1 high order low order data 3 high order low order data 2 high order low order data 1 high order low order data 1 high order low order data 2 high order low order data 3 high order low order data 1 to 6 data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 3 data 4 data 5 data 6 data 1 data 2 data 3 data 4 data 5 data 6 data 6 data 5 data 4 data 3 data 2 data 1 data 6 data 5 data 4 data 3 data 2 data 1 fixed data 1 to 6 note: the relationship of position between 16-bit data s high-order byte and its low-order byte is fixed, regardless of the address direction. (data is transferred by the 16 bits.) 2 3 1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 1 2 3 2 2 3 3 4 4 5 5 6 6 1 1 2 3 1 data 1 to 3 data 1 to 3
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 84 dma continuous transfer (1) single transfer mode in the single transfer mode, only the preselected number of bytes are transferred. as shown in figure 69, first, set up the number of bits per 1 transfer unit, transfer method, transfer mode, and transfer address direction by using the dmai mode registers l and h. then, write the transfer source block s first transfer address (the block s lowest ad- dress in the forward or fixed transfer address direction, or the block s highest address in the backward address direction) into the source address register (hereinafter referred to as sar). further, write the destination block s first transfer address (the lowest address in the forward or fixed transfer address direction, or the highest address in the backward transfer address direction) into the destination address register (hereinafter referred to as dar). also write the desired num- ber of bytes to be transferred, into the transfer counter register (here- inafter referred to as tcr). write the value 1 or more into tcr. each of sar, dar, and tcr consists of 24 bits, therefore, be sure to write into all these bits. the sar, dar, and tcr are located at the ad- dresses shown in figure 66. the next is to set a dma source and others by the dmai control register shown in figure 68. set up bit 0 (priority select bit) and bit 1 (tc pin validity bit) of the dmac control register l shown in figure 67, and finally set the dmac control reg- ister h s dma enable bit to 1 so as to make the dma request ac- ceptable. when the contents of tcr are cleared to 0 , the terminal count sig- nal (tc) is output, and at the same time, the interrupt request bit of the dma interrupt control register is set to 1 . to forcedly terminate the dma transfer, input l level to pin tc or write the value 0 to the dma enable bit. at this time, the interrupt request bit of the dma interrupt control register is not set to 1 . figure 78 shows a timing diagram example in the single transfer mode on the following conditions: transfer unit: 16 bits transfer method: 2-bus cycle transfer transfer mode: burst transfer mode (edge sense) transfer source address direction: forward. transfer destination address direction: forward. transfer source wait: 0 wait transfer destination wait: 0 wait as 2-bus cycle transfer mode is selected, a read operation is per- formed in the first bus cycle. first, the address written into the sar is output to the address bus and then inputted into the incrementor/ decrementor (hereinafter referred to as i/d). the i/d adds 1 or 2 to the inputted address and outputs the result back to the sar. if one 16-bit transfer operation is not enough to complete the read opera- tion, the read operation is performed within 2 bus cycles to achieve the purpose. the operation is performed in the next bus cycle. first, the address written in the dar is output to the address bus and then inputted into the i/d. the i/d adds 1 or 2 to the inputted address and outputs the result back to the dar. if one 16-bit transfer operation is not enough to complete the write operation, the write operation is performed within 2 bus cycles to achieve the purpose. the operation performed so far is called the write cycle. the data stored in the biu s data latch in the read cycle is output to the data bus in the write cycle and writ- ten into the destination memory or external i/o. the operations per- formed so far complete the transfer of 1 transfer unit. in the 2-bus cycle transfer, the read and write cycle combination is called the dma transfer cycle. dma transfer is executed by repeating the dma transfer cycle. in the 2-bus cycle transfer, the tcr varies in the read cycle. the re- maining transfer bytes are read from the tcr in concurrence with address output from sar in the read cycle and inputted into the decrementor (hereinafter referred to as d). the d subtracts 1 or 2 from the number of remaining bytes and outputs the result back to the tcr. in this manner, the contents of the tcr decrease each time when 1-transfer-unit data has been transferred. when the num- ber of remaining bytes, which was read from the tcr, becomes 0 , the dma controller outputs the terminal count signal (tc) to pin tc, and at the same time, sets the interrupt request bit of the dma inter- rupt control register to 1 . at this time, the dma enable bit is cleared to 0 . as the burst transfer mode is selected in this example, the dma request bit is also cleared to 0 . to forcedly terminate transfer, input l level to pin tc (p4 2 ) or write the value 0 to the dma enable bit. in the single transfer, the first values written in the sar, dar, and tcr are retained in the internal latches. therefore, if dma transfer is to be performed under the same conditions, it can be initiated sim- ply by setting the dma enable bit to 1 .
85 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers read cycle transfer of 1 transfer unit terminate processing sar dar sar + 2 dar + 2 sar + 4 dar + 4 data0 l data0 h write cycle a 23 d 0 d 7 dmaack i tc blw bhw (cpu) (cpu) d 15 data0 l data0 h data1 l data1 h data1 l data1 h data2 l data2 h data2 l data2 h external data bus width : 16 bits transfer unit : 16 bits transfer method : 2-bus cycle transfer transfer source address direction : forward transfer destination address direction : forward transfer source area s wait : 0 wait transfer destination area s wait sar dar value which has been set to tcr bus user : 0 wait : value which has been set to sari (even) : value which has been set to dari (even) : 6 : cpu
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 86 (2) repeat transfer mode in the repeat transfer mode, the single transfer is repeated. first, set up the number of bits per 1 transfer unit, transfer method, transfer mode, and transfer address direction by using the dmai mode regis- ter l. next, write the transfer source block s transfer start address in the sar and the transfer destination block s transfer start address in the dar. further, write the desired number of bytes to be trans- ferred, into the tcr, and set up the dmai control register and dmac control register. the dma request is now acceptable. when the dma request occurs in this state, dma transfer starts. even when the number of remaining bytes, which was read from the tcr, becomes 0, the dma enable bit is not cleared to 0 . when the burst transfer mode is selected, the dma request bit is not cleared to 0 , also. when the cycle steal transfer mode is selected, the dma request bit is cleared to 0 each time when 1-transfer-unit data has been trans- ferred. fig. 79 timing diagram example in repeat transfer mode (burst transfer mode) a 23 d 0 d 7 d 8 d 15 transfer of 1 transfer unit data0 l data0 h data0 l data0 h data2 l data2 h data2 l data2 h data0 l data0 h s wait : 0 wait transfer destination area s wait sar dar value which has been set to tcr bus user : 0 wait : value which has been set to sari (even) : value which has been set to dari (even) : 6 : cpu 1 . to forcedly terminate transfer, input l level to the pin tc or write the value 0 to the dma enable bit. in the repeat transfer mode, tc signal output and the setting the in- terrupt request bit of the dma interrupt control register to 1 are not performed. figure 78 shows the timing diagram example in the repeat transfer mode.
87 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers (3) array chain transfer mode in the array chain transfer mode, one channel is used for the data transfer for two or more memory blocks. three parameters necessary for transfer, that is, the transfer source s transfer start address, transfer destination s transfer start address, and the number of transfer bytes, must be sequentially writ- ten into the transfer parameter memory. the transfer parameter memory can be located in an arbitrary position in the memory space. figure 80 shows a transfer parameter memory map example in the array chain transfer mode. all of the transfer parameters of the memory blocks to be transferred must be written into the transfer pa- rameter memory. the transfer parameter memory format is shown in figure 81. for 1-bus cycle transfer, the external i/o side s param- eters are not needed. for transfer from external memory to external i/o, for instance, consecutively write the transfer source start ad- dresses and the number of transfer bytes only, as shown in figure 82. as the transfer destination s transfer start addresses need not be written, it is possible to save the transfer time and transfer parameter memory area. in the single and repeat transfer modes, the values written in the sar, dar, and tcr first are retained in the internal latches. in the array chain transfer and link array chain transfer modes, however, these latches perform different functions. the sar latch serves as the transfer parameter register (hereinafter referred to as tpr), which indicates the start address of the transfer parameter memory. the tcr latch serves as the transfer block counter (hereinafter referred to as tbc), which indicates the number of transfer blocks. in the array chain transfer and link array chain transfer modes, writing a value to an sar address causes that value to be written in the tpr, and writing a value to a tcr address causes that value to be written in the tbc. the array chain transfer operations are detailed below. in the array chain transfer mode, also, first, set up the dmai mode register, dmai control register, and dmac control register. write the start address of the transfer parameter memory into the sar. this value is then written into the tpr. be sure that an even-numbered address is set to the start address. nothing needs to be written into the dar. into the tcr, write the desired number of memory blocks to be transferred. this number is then written into the tbc. when the dma enable bit is set to 1 after completion of the above setup, dma transfer becomes enabled. fig. 80 parameter memory map example in array chain transfer mode 4 bytes 4 bytes 4 bytes transfer source s transfer start address 1 transfer destination s transfer start address 1 number of transfer bytes 1 transfer source s transfer start address 2 transfer destination s transfer start address 2 number of transfer bytes 2 transfer source s transfer start address 3 transfer destination s transfer start address 3 number of transfer bytes 3 transfer source s transfer start address 4 transfer destination s transfer start address 4 number of transfer bytes 4 transfer parameters for 1 block fig. 81 parameter memory format even-numbered address dummy byte necessary only in link array chain transfer. transfer source s transfer start address (l) transfer source s transfer start address (m) transfer source s transfer start address (h) transfer parameter address (l) transfer parameter address (m) transfer parameter address (h) transfer destination s transfer start address (l) transfer destination s transfer start address (m) transfer destination s transfer start address (h) transfer parameters for 1 block number of transfer bytes (l) number of transfer bytes (m) number of transfer bytes (h) (h) = high order, (m) = middle order, (l) = low order fig. 82 transfer parameter memory in 1 bus cycle transfer 4 bytes 4 bytes number of transfer bytes 1 transfer source s transfer start address 1 number of transfer bytes 2 transfer source s transfer start address 2 number of transfer bytes 3 transfer source s transfer start address 3 number of transfer bytes 4 transfer source s transfer start address 4 transfer parameters for 1 block
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 88 in the array chain transfer, the transfer parameters are first read from the transfer parameter memory and then written into the sar, dar, and tcr. this operations state is called the array state . figures 83 and 84 show timing diagram examples in the array chain transfer mode (burst transfer mode). the dma controller outputs the start ad- dress of the transfer parameter memory to the address bus, and se- quentially stores the read data into the sar, dar, and tcr. when the transfer parameters for 1 block are completely stored, the contents of the tbc are decremented by 1, and then, the first dma transfer starts in accordance with the stored parameters. these op- erations for storing parameters are called array state . in contrast to the array state, the state in which dma transfer is ac- tive is called transfer state . in the transfer state, the same opera- tions are performed as in the single transfer mode. each time when 1-transfer-unit data has been transferred, the contents of the tcr are decremented by 1 in 8-bit transfer or by 2 in 16-bit transfer. even when the contents of the tcr become 0, the dma request bit and dma enable bit are not cleared to 0 and the array state of the next block starts. when the contents of the tbc are 0 at the start of the array state, the entire transfer operation is considered to be completed, and l level is output into pin tc to clear the dma request bit and dma en- able bit and terminate array chain transfer. at the same time, the in- terrupt request bit of the dma interrupt control register is set to 1 . in the cycle steal transfer at the array chain transfer mode, one array state and transfer cycle of 1 transfer unit are made by one dma re- quest.
89 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 83 timing diagram example in array chain transfer mode (burst transfer mode) (1) fig. 84 timing diagram example in array chain transfer mode (burst transfer mode) (2) a 23 d 0 d 7 d 8 d 15 dmaack i tc blw bhw 1 , and is accepted. external data bus width transfer unit transfer method transfer source address direction transfer destination address direction transfer source area s wait transfer destination area s wait transfer parameter memory s wait sa1, sa2, da1, da2 tp transfer block s number bus user : 16 bits : 16 bits : 2-bus cycle transfer : forward : forward : 1 wait : 1 wait : 0 wait : transfer parameters (even) : start address of first block s transfer parameter memory : 2 : cpu s transfer parameters second block s transfer parameters tp + 4 tp + 8 tp + 12 tp + 16 tp + 20 sa1 sa1 + m - 1 sa1 + m sa2 + n - 1 sa2 + n sa2 da1 da1 + m - 1 da1 + m da2 + n - 1 da2 + n da2 continue to figure 84. tp tp + 2 tp + 4 tp + 6 tp + 8 tp + 10 sa1 da1 h transfer of 1 transfer parameter array state sa1 h da1 l da1 h m l m h transfer of 1 transfer unit transfer state data l data h data l data h sa1 l sa1 m dummy data dummy data dummy data da1 m m m da1 + m - 2 (cpu) data l data h array state transfer state terminate processing tp + 12 tp + 20 da2 + n - 4 sa2 + n - 2 sa2 from proceeding figure 83. tp + 22 a 23 d 0 d 7 d 8 d 15 dmaack i tc n l n h n m sa2 l data l data h data l data h data l data h data l data h sa2 m dummy data
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 90 (4) link array chain transfer mode figure 85 shows the perameter memory map in the link array chain transfer mode. as shown in this figure, not only the transfer source s transfer start address, transfer destination s transfer start address, and number of transfer bytes, but also the start address of the memory block which contains the next transfer parameters is stored. in the transfer parameter of the last block, be sure to set 000000 16 as the start address of the next transfer parameter. for 1-bus cycle transfer, the external i/o side s parameters are not needed. in the link array chain transfer, also, the dmai mode registers l and h, dmai control register, and dmac control registers l and h must be set up. into the sar, write the start address of the memory block that stores the parameters for the first transfer. this value is then written into the tpr. be sure that an even-numbered address is set to the start address. nothing needs to be written in the dar. write the value 1 or more into the tcr. when the dma enable bit is set to 1 after completion of the above setup, dma transfer becomes enabled. in the link array chain transfer, the transfer parameters are first read from the transfer parameter memory and then written into the sar, dar, and tcr. further, the start address of the memory block that contains the next parameters has been written into the tpr. in the link array chain transfer mode, the state so far is referred to as the array state. the dma controller sequentially outputs the transfer parameters to the address bus, beginning with the start address of the memory block, storing the transfer parameters. the read data are sequen- tially stored into the sar, dar, and tcr, and then the start address of the memory block, containing the next parameters, is written into the tpr. a dma transfer is made in accordance with the parameters read from the transfer parameter memory. the transfer state is the same as in the single transfer mode. the contents of the tcr are decremented by 1 or 2 each time when 1-transfer-unit data has been transferred. even when the contents of the tcr become 0, the dma request bit and dma enable bit are not cleared to 0 but the array state starts again. when the contents of the tpr are 0 at this time, however, l level is output into pin tc to clear the dma request bit and dma en- able bit to 0 and terminate the link array chain transfer. at the same timing, the interrupt request bit of the dma interrupt control register is set to 1 . in the cycle steal transfer at the link array chain transfer mode, one array state and the transfer cycle of 1 transfer unit are made by one dma request. figures 86 and 87 show timing diagram examples in the link array chain transfer mode (burst transfer mode). fig. 85 parameter memory map example in link array chain trans- fer mode transfer source s transfer start address 1 transfer destination s transfer start address 1 number of transfer bytes 1 transfer parameter address 2 transfer source s transfer start address 4 transfer destination s transfer start address 4 number of transfer bytes 4 transfer parameter address 5 transfer parameters for 1 block transfer parameter address 4 transfer source s transfer start address 3 transfer destination s transfer start address 3 number of transfer bytes 3 transfer parameter address 4 transfer parameter address 3 transfer source s transfer start address 2 transfer destination s transfer start address 2 number of transfer bytes 2 transfer parameter address 3 transfer parameter address 2
91 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 86 timing diagram example in link array chain transfer mode (burst transfer mode) (1) fig. 87 timing diagram example in link array chain transfer mode (burst transfer mode) (2) tp1 tp1 + 2 tp1 + 4 tp1 + 6 tp1 + 8 h h h tp1 + 10 (tp1+8) m tp1 + 12 continue to figure 87. tp1 + 14 (tp1 sa1 sa1 + m - 1 sa1 + m sa2 + n - 1 sa2 + n sa2 da1 da1 + m - 1 da1 + m da2 + n - 1 da2 + n da2 memory memory memory sa1 da1 m tp2 sa2 da2 n 000000 16 tp1 tp1 + 4 tp1 + 8 tp1 + 12 tp2 tp2 + 4 tp2 + 8 tp2 + 12 (cpu) a 23 d 0 d 7 d 8 d 15 dmaack i tc blw bhw sa1 h da1 l da1 h m l m h tp2 l tp2 h tp2 m sa1 l sa1 m dummy data dummy data dummy data dummy data da1 m m m transfer of 1 transfer parameter array state s wait transfer destination area s wait sa1, sa2, da1, da2 tp1 transfer block s number bus user : 16 bits : 16 bits : 2-bus cycle transfer : forward : forward : 0 wait : 0 wait : transfer parameters (even) : start address of first block s transfer parameter memory : 2 : cpu s transfer parameter second block s transfer parameter first block transfer second block transfer sa1 da1 + m - 2 tp2 tp2 + 14 sa2 da1 da2 + n - 4 from preceding figure 86. sa2 + n - 2 da2 + n - 2 00 16 (cpu) a 23 d 0 d 7 d 8 d 15 dmaack i tc data l data h data l data h data l data h data l data h data l data h data l data h data l data h sa2 l sa2 m dummy data array state transfer state transfer state transfer of 1 transfer unit terminate processing
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 92 dram controller the dram controller directly accesses the dram located in the ex- ternal chip select area (cs 1 , cs 2 , cs 3 ). figure 88 shows the block diagram of the dram controller. table 19 shows the functions of the dram-related signals, and table 20 shows the relationship between the external data bus width and the multiplexed addresses. the start address, block size, external data bus width, and dram space of the chip select area, which is to be accessed by the dram controller, are specified by the cs j control register l, cs j control reg- ister h, and the area cs j start address register in the chip select wait controller. for more details, refer to the section on the chip select wait controller. figure 89 shows the bit configuration of the cs j control register l with use of the dram controller. bit 4 is the dram space designa- tion bit. when bit 4 is set to ?? pins a 8 /ma 0 to a 16 /ma 8 , a 18 /ma 9 , a 20 /ma 10 , a 22 /ma 11 , and p9 4 to p9 6 , become the output pins for the dram control signals. figure 90 shows the bit configuration of the dram control register. bit 0 is the byte control select bit. when the device type of dram to be connected is 1cas/2w, be sure to clear this bit to ?? and when the device type of dram to be connected is 2cas/1w, be sure to set this bit to ?? when the external data bus width = 8 bits, however, be sure to clear this bit to ?? table 21 shows the relationship between the byte control select bit and the pin functions. each of figures 91 and 92 shows an operating waveform example of the dram control signals, address bus, and data buses with 1cas/2w or 2cas/1w selected. bit 4 of the dram control register is the self-refresh operation select bit and controls the dram self-refresh operation in the stop mode; ??disables the self-refresh operation in the stop mode, and ??en- ables the self-refresh operation. bit 7 is the refresh timer count start bit. the refresh timer starts counting when this bit is set to ?? figure 94 shows an operating waveform example of the dram con- trol signals at refresh. this refreshing method, as shown in figure 94, is the ?as before ras refresh? this method makes signal cas falls before signal ras falls. the refresh interval is determined by the refresh timer (address a9 16 ). the refresh timer is an 8-bit timer performing a repetitive count with the reload register. the clock source is internal clock f 32 . the refresh time issues a refresh request to the biu each time when the refresh timers count value reaches 00 16 . therefore, the relation- ship between the value to be loaded into the refresh timer, n (n = 01 16 to ff 16 ), and dram refresh interval, m (?), is as follows: n = { m ? f(x in ) / 32 } ?1 once the biu accepts a refresh request, it performs the bus arbitra- tion for the cpu and dmac and outputs the refresh enable signal to the dram controller. accordingly, the dram controller makes the re- fresh cycle (cas before ras refresh). in the stop mode, since the refresh timer stops counting and the dram controller cannot perform the refresh operation (cas before ras refresh). for dram supporting the self-refresh operation, by setting the self- refresh operation select bit to ??before going into the stop mode, the self-refresh operation in the stop mode can be enabled. figure 95 shows an operating waveform example of the dram con- trol signals at self-refresh.
93 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 88 block diagram of dram controller table 19. functions of dram-related signals table 20. relationship between external data bus width and multiplexed addresses bus interface unit (biu) chip select wait controller dram control signal generating circuit ras j cas (ucas/lcas) w (wrh/wrl) ma 0 ma 11 dram space designation bit address refresh request dram control register dram controller address multiplexer refresh timer 1/ (n + 1) 1/2 dram space designation bit: bit 4 at addresses 82 16 , 84 16 , 86 16 j = 1 to 3 b7 b0 1/16 (address a9 16 ) (address a8 16 ) valid/invalid external data bus width = 16 bits l when a column address at an odd-numbered address is output. l when a row address is output. l when a column address at an even-numbered address is output. external data bus width = 8 bits l when a row address is output. h output (fixed) l when data at an even-numbered address is written. l when data is written. signal multiplexed address output l when data at an odd-numbered address is written. h output (fixed) functions ma 0 ma 11 ras j (j = 1 to 3) cas lcas ucas wrl wrh w pin name external data bus width = 8 bits row address column address row address column address external data bus width = 16 bits output signal a 8 /ma 0 a 9 /ma 1 a 10 /ma 2 a 11 /ma 3 a 12 /ma 4 a 13 /ma 5 a 14 /ma 6 a 15 /ma 7 a 16 /ma 8 a 18 /ma 9 a 20 /ma 10 a 22 /ma 11 a 8 a 0 a 8 a 0 : these signals are not used. a 9 a 1 a 9 a 1 a 10 a 2 a 10 a 2 a 11 a 3 a 11 a 3 a 12 a 4 a 12 a 4 a 13 a 5 a 13 a 5 a 14 a 6 a 14 a 6 a 15 a 7 a 15 a 7 a 16 a 17 a 16 a 8 a 18 a 19 a 18 a 17 a 20 a 21 a 20 a 19 a 22 a 23 a 22 a 21
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 94 fig. 89 bit configuration of cs j control register l with use of dram controller (j = 1 to 3) 76543210 cs 1 control register l cs 2 control register l cs 3 control register l area cs j wait number select bits 0 1 : 1 wait address 82 16 84 16 86 16 cs j output select bit 1 : cs j output is enabled. (port pin p9 j functions as pin cs j . ras output is enabled.) note: in order to use the dram controller, setup for bits 0, 1, 4 to 7 are necessary as above. 1 0 1 0 1 0 external data bus width select bit 0 : 16-bit width 1 : 8-bit width invalid. (it may be 0 or 1 .) dram space designation select bit 1: dram space burst rom access select bit 0 : normal access recovery cycle insert select bit 0 : no recovery cycle is inserted at access to area cs j . x
95 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 90 bit configuration of dram control register table 21. relationship between byte control select bit and pin functions byte control select bit 0 (1cas/2w) cas ucas wrh wrl w lcas 1 (2cas/1w) pin p9 4 p9 5 p9 6 76543210 self-refresh operation select bit (self-refresh operation in the stop mode is controlled.) 0 : disabled. 1 : enabled. byte control select bit (note) 0 : 1cas/2w 1 : 2cas/1w fix this bit to 0 . refresh timer count start bit 0 : counting stopped. 1 : counting started. dram control register address a8 16 note: when the external data bus width = 8 bits, be sure to set this bit to 0 (1cas/2w). the value is 0 at reading. the value is 0 at reading. the value is 0 at reading. 0000 0
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 96 fig. 91 operating waveform example of dram control signals, address bus, and data buses with 1cas/2w selected operating waveform example when 16-bit data is accessed with the external data bus width = 16 bits, starting at an even-numbered address column 1 d 0 d 7 d 8 d 15 ras j (cs j ) cas wrl at reading at writing row address address wrh address rd (odd) rd (even) wd (even) wd (odd) (note) note: when dram is continuously accessed with the fast page access off, 1 cycle of 1 will be inserted between bus cycles. row address column address fig. 92 operating waveform example of dram control signals, address bus, and data buses with 2cas/1w selected operating waveform example when 16-bit data is accessed with the external data bus width = 16 bits, starting at an even-numbered address 1 ras j (cs j ) w lcas ucas address (note) note: when dram is continuously accessed with the fast page access off, 1 cycle of 1 will be inserted between bus cycles. d 0 d 7 d 8 d 15 address row column address row address column address rd (odd) rd (even) wd (even) wd (odd) at reading at writing
97 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 95 operating waveform example of dram control signals at self-refresh 1 ras j h cas w refresh cycle (preceding bus cycle) bus request (dramc) sampled j = 1 to 3 (next bus cycle) ras j cas value of watchdog timer 7ff 16 interrupt request to be used for stop mode termination (interrupt request bit) fff 16 wf 32 ? 2048 counts stop mode biu f(x in ) 1 refresh cycle (interrupt request which has been used for stop mode termination) (preceding bus cycle) w h fig. 94 operating waveform example of dram control signals at cas before ras refresh
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 98 real-time output each of these microcomputers is equipped with the 8-bit real-time output function. whether to use the real-time output function is decided by the wave- form output select bits of the 8-bit real-time output control register (bits 0 and 1 at address a0 16 ). (see figure 96.) also, the real-time output controlled by the pulse output mode select bit of the real-time output control register (bit 2 at address a0 16 ) and is used in one of the following ways: ?4 bits ? 2 channels ?6 bits ? 1 channel + 2 bits ? 1 channels (1) pulse mode 0 when the pulse output mode select bit is cleared to ?? the micro- computer enters pulse output port is controlled by 2 groups of 4 bits. figures 97 and 98 show the pulse output data register 0/1 (address a2 16 /a4 16 ) bit configuration and real-time output structure in pulse mode 0, respectively. when the waveform output select bits are set to ?1?(bit 1 = ??and bit 0 = ??, rtp0 3 to rtp0 0 become pulse output port pins, in other words, rtp0 is selected. when the waveform output select bits are set to ?0?(bit 1 = ??and bit 0 = ??, rtp1 3 to rtp1 0 become pulse output port pins, in other words, rtp1 is selected. when the waveform output select bits are set to ?1?(bit 1 = ??and bit 0 = ??, two groups consisting of rtp1 3 to rtp1 0 and rtp0 3 to rtp0 0 become pulse output port pins, in other words, rtp1 and rtp0 are selected. when the waveform output select bits are set to ?0?(bit 1 = bit 0 = ??, port p5 pins become normal programmable i/o port pins. the contents of the pulse output data register 1 (high-order 4 bits at address a4 16 ), which corresponds to rtp1 3 to rtp1 0 , is output to these ports each time when the contents of timer a1 counter be- comes ?000 16 ? the contents of the pulse output data register 0 fig. 96 bit configuration of real-time output control register fig. 97 bit configuration of pulse output data register real-time output register a0 16 waveform output select bits 00 : programmable i/o port 01 : rtp0 selected when pulse mode 0 is selected: rtp0 when pulse mode 1 is selected: rtp0 1 , rtp0 0 10 : rtp1 selected when pulse mode 0 is selected: rtp1 when pulse mode 1 is selected: rtp1, rtp0 3 , rtp0 2 11 : rtp1 and rtp0 selected when pulse mode 0 is selected: rtp1 and rtp0 when pulse mode 1 is selected: rtp1, rtp0 3, rtp0 2 and rtp0 1, rtp0 0 pulse output mode select bit 0 : pulse mode 0 1 : pulse mode 1 0 at read. 76543210 address 00000 note 1: used only in pulse mode 0 2: used only in pulse mode 1 pulse output data register 0 rtp0 0 pulse output data bit rtp0 1 pulse output data bit rtp0 2 pulse output data bit (note 1) rtp0 3 pulse output data bit (note 1) 76543210 address a2 16 pulse output data register 1 rtp0 2 pulse output data bit (note 2) rtp0 3 pulse output data bit (note 2) rtp1 0 pulse output data bit rtp1 1 pulse output data bit rtp1 2 pulse output data bit rtp1 3 pulse output data bit 76543210 address a4 16 (low-order 4 bits at address a2 16 ), which corresponds to rtp0 3 to rtp0 0 , is output to these ports each time when the contents of timer a0 counter becomes 0000 16 . when 0 is written to a specified bit of the pulse output data register, a low-level signal is output to a pulse output port if the counter con- tents of the timer which corresponds to the bit becomes 0000 16 : when 1 is written to the bit, a high-level signal is output to a pulse output port which corresponds to the bit at the same timing.
99 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 98 real-time output structure in pulse mode 0 (2) pulse mode 1 when the pulse output mode select bit is set to ?? the microcom- puter enters pulse mode 1, and a pulse output port pins are sepa- rately controlled (6 bits and 2 bits). figure 99 shows the real-time output structure in pulse mode 1. when the waveform output select bits are set to ?1?(bit 1 = ??and bit 0 = ??, rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 become program- mable i/o port pins. simultaneously, rtp0 1 and rtp0 0 become pulse output port pins. when the waveform output select bits are set to ?0?(bit 1 = ??and bit 0 = ??, rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 become pulse out- put port pins. at this time, rtp0 1 and rtp0 0 become programmable i/o port pins. when the waveform output select bits are set to ?1?(bit 1 = bit 0 = t dq dq dq dq t dq dq dq d 6 d 5 d 4 d 3 d 2 d 1 d 0 timer a0 timer a2 p5 3 /rtp0 3 p5 2 /rtp0 2 p5 1 /rtp0 1 p5 0 /rtp0 0 port p5 i latch waveform output select bit (address a0 16 ) bit 1 pulse output data register 0 (address a2 16 ) pulse output data register 1 (address a4 16 ) data bus (even) pulse output mode select bit (address a0 16 ) 0 d 7 t t t dq t t t a a a a a a a a waveform output select bit (address a0 16 ) bit 0 p5 7 /rtp1 3 p5 6 /rtp1 2 p5 5 /rtp1 1 p5 4 /rtp1 0 port p5 i direction register 1 0 (i = 7 to 0) a (address d 16 ) (address b 16 ) 1 ), pulse output port pins are divided into two groups; one consists of rtp1 3 to rtp1 0 , rtp0 3 , rtp0 2 and the other consists of rtp0 1 and rtp0 0 . when the waveform output select bits are set to 00 (bit 1 = bit 0 = 0 ), port p5 pins become normal programmable i/o port pins. rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 are controlled by timer a2. also, rtp0 1 and rtp0 0 are controlled by timer a0. the contents of the pulse output data register 1 (high-order 6 bits at address a4 16 ), which corresponds to rtp1 3 to rtp1 0 , rtp0 3 , and rtp0 2 , are output to this port each time when the contents of timer a2 counter becomes 0000 16 . the contents of the pulse output data register 0 (low-order 2 bits at address a2 16 ), which corresponds to rtp0 1 and rtp0 0 , are output to this port each time when the con- tents of timer a0 counter become 0000 16 .
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 100 fig. 99 real-time output structure in pulse mode 1 table 22 lists the port p5/rtp pin output when all of the port p5 di- rection registers are set to the output mode. precautions for real-time output function after reset, the port p5 direction register is set to the input mode, and port p5i (i = 0 to 7) pins function as normal i/o port pins. when using these pins as real-time output port pins, set the corre- sponding bits of the port p5 direction register to the output mode. additionally, by reading the real-time output port s value from the port p5 register, output level of pins can be read out. real-time output control register (address a0 16 ) store address for port p5/rtp pin output data 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 1 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b 0b a4 a4 0b a2 0b a2 0b 0b a4 a4 0b a2 0b a2 0b 0b a4 a4 0b a2 0b a2 0b a2 0b a2 0b a2 0b a2 0b a2 0b a2 table 22. port p5/rtp pin output dq dq dq dq t dq dq dq d 6 d 5 d 4 d 3 d 2 d 1 d 0 timer a0 timer a2 p5 3 /rtp0 3 p5 2 /rtp0 2 p5 1 /rtp0 1 p5 0 /rtp0 0 port p5 i latch waveform output select bit (address a0 16 ) bit 1 pulse output data register 0 (address a2 16 ) pulse output data register 1 (address a4 16 ) data bus (even) pulse output mode select bit (address a0 16 ) 1 d 7 t t t dq t t a a a a a a a a waveform output select bit (address a0 16 ) bit 0 p5 7 /rtp1 3 p5 6 /rtp1 2 p5 5 /rtp1 1 p5 4 /rtp1 0 port p5 i direction register 1 0 (i = 7 to 0) a t t (address d 16 ) (address b 16 ) address 0b 16 : port p5 address a2 16 : pulse output data register 0 address a4 16 : pulse output data register 1
101 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers watchdog timer frequency select bit writing to watchdog timer register watchdog timer ?ff16?is set. 1/16 1/16 wf 32 wf 512 f 2 hlda wait mode dma transfer watchdog timer interrupt request access to external area reset stp instruction 1 0 ? 1 0 external clock input select bit ?watchdog timer register : address 60 16 ?watchdog timer frequency select register : bit 0 at address 61 16 ? when the most significant bit of the watchdog timer becomes ?? this signal will be generated. at the stp instruction execution, however, wf 32 is selected compulsorily. disables watchdog timer watchdog timer the watchdog timer is used to detect unexpected execution se- quence caused by software runaway and others. figure 100 shows the block diagram of the watchdog timer. the watchdog timer consists of a 12-bit binary counter. the watchdog timer counts clock wf 32 , which is obtained by dividing the peripheral devices?clock f 2 by 16; or clock wf 512 , which is ob- tained by doing it by 256. the watchdog timer frequency select reg- ister (bit 0 = watchdog timer frequency select bit) shown in figure 101 selects which clock is to be counted. wf 512 is selected when this bit 0 is ?? and wf 32 is selected when this bit 0 is ?? this bit 0 is cleared to ??after reset. fff 16 is set in the watchdog timer when ??level voltage is applied to pin reset, stp instruction is executed, data is written to the watchdog timer register (address 60 16 ), or the most significant bit of the watchdog timer becomes ?? after fff 16 is set in the watchdog timer, when the watchdog timer counts wf 32 or wf 512 by 2048 counts, the most significant bit of watchdog timer becomes ?? the watchdog timer interrupt request bit is set to ?? and fff 16 is set again in the watchdog timer. in program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes ?? if this routine is not executed owing to unexpected program ex- ecution or others, the most significant bit of the watchdog timer be- fig. 100 block diagram of watchdog timer fig. 101 bit configuration of watchdog timer frequency select register 76543210 watchdog timer frequency select register watchdog timer frequency select bit 0 : w f 512 is selected. 1 : w f 32 is selected. 76543210 address 61 16 comes 0 and an interrupt is generated. the microcomputer can generate a reset pulse by writing 1 to bit 6 (software reset bit) of processor mode register 0 in an interrupt rou- tine and can be restarted. the watchdog timer can also be used to return from the stp state, where a clock has stopped its operation owing to the stp instruction execution. for details, refer to the sections on the clock generating circuit. the watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled: when the external area is accessed in the hold state in the wait mode in the stop mode
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 102 how to disable watchdog timer when not using the watchdog timer, it can be disabled. when the watchdog timer is disabled, it s operation stops and no watchdog timer interrupt has been generated. setting for disabling the watchdog timer is possible by writing 79 16 and 50 16 to the particular function select register 2 (address 64 16 ) sequentially with the following instructions: movmb/stab instruction, or movm/sta instruction (m = 1) if any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is per- formed. (also, reset is the only one method to remove the setting for disabling the watchdog timer.)
103 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers stop and wait mode the stop (hereafter called stp) and the wait (hereafter called wit) modes are used to save the power dissipation of the system, by stopping oscillation or system clock in the case that the cpu needs not be operating. the microcomputer enters the stp or wit mode by executing the stp or wit instruction, and either mode is terminated by acceptance of an interrupt request or reset. to terminate the stp or wit mode by an interrupt request, the inter- rupt to be used for termination of the stp or wit mode must be en- abled in advance to execution of the stp or wit instruction. the interrupt priority level of this interrupt is required to be higher than the processor interrupt priority level (ipl) of the routine where the stp or wit instruction will be executed. figures 102 and 103 show the bit configurations of the particular function select registers 0, 1. setting the stp instruction invalidity select bit (bit 0 of the particular function select register 0) to 1 invali- dates the stp instruction, and the stp instruction will be ignored. after reset is removed, since the above bit is cleared to 0 , however, the stp instruction is valid. the stp- or the wit-instruction-execution status bit (bit 0 or 1 of the particular function select register 1) is set to 1 by the execution of the stp or the wit instruction, and so, after the stp or wit mode has been terminated, each bit will indicate that the stp or wit in- struction has been executed. accordingly, each of these bits must be cleared to 0 by software at termination of the stp or the wit mode. table 23 lists the microcomputer s operation in the stp and wit modes. stp mode the execution of the stp instruction stops the oscillation circuit. it also stops clock source , 1 , biu , cpu , and divide clocks f 1( ) to f 4096 , wf 32 and wf 512 in the l state. in the watchdog timer, fff 16 is automatically set, and regardless the contents of watchdog timer frequency select bit (bit 0 at address 61 16 ), the count source of the watchdog timer becomes wf 32 . this setting is terminated by clear- ance of the most significant bit of the watchdog timer or reset, and the count source is back to the one which was selected with the watchdog timer frequency select bit. in the stp mode, the a-d converter, dma controller, dram control- ler (reflesh timer is also stopped.), and watchdog timer, which use divide clocks f 1( ) to f 4096 , wf 32 and wf 512 , are stopped. at this time, timers a and b operate only in the event counter mode, and serial i/o communication is active only while an external clock is selected. the stp mode is terminated by acceptance of an interrupt request or reset, and the oscillation restarts. supply of clock source , 1 , di- vide clocks f 1( ) to f 4096 , wf 32 and wf 512 is also restarted. when the oscillation is restarted by the interrupt request acceptance, biu and cpu are stopped at l level until the most significant bit of the watchdog timer, which is counted down with divide clock wf 32 , is cleared to 0 . note that, when the oscillation is restarted, supply of biu and cpu starts immediately after the oscillation restarts. there- fore, the reset input must be raised to h after the enough oscilla- tion-stabilizing time has elapsed. the system where a stable clock is input from the external to pin x in is equipped with the mode where an instruction can be executed immediately after the stp mode termination. for details, refer to the section on stop of oscillation circuit of the power saving function. wit mode when the wit instruction is executed with the internal clock stop se- lect bit at wit (bit 3 of the particular function select register 1 in fig- ure 103) = 0 , biu , cpu , and divide clocks wf 32 and wf 512 are stopped in the l state. however, the oscillation circuit, clock source , 1 , and divide clocks f 1( ) to f 4096 remain operating. therefore, biu, cpu, and dma controller are stopped, whereas timers a and b, serial i/o, and the a-d converter, which use the divide clocks f 1( ) to f 4096 , are still operating. because the reflesh timer of the dram con- instruction wit internal clock stop select bit at wit active oscillation circuit operations in wit and stp modes 0 , 1 , f 1( ) to f 4096 active stp wf 32 , wf 512 biu , cpu stopped ( l ) stopped ( l ) peripheral devices using f 1( ) to f 4096 , wf 32 , wf 512 timers a, b, serial i/o, a-d converter: operation is enabled. dram controller: reflesh timer is operated. dma controller: stopped. (watchdog timer: stopped.) timers a, b: operation is enabled only in the event counter mode. serial i/o: operation is enabled only while an external clock is selected. a-d converter, dma controller: stopped. dram controller: reflesh timer is operated. (watchdog timer: stopped.) stopped ( l ) stopped ( l ) stopped ( l ) active 1 stopped ( l ) stopped ( l ) stopped ( l ) stopped timers a, b: operation is enabled only in the event counter mode. serial i/o: operation is enabled only while an external clock is selected. a-d converter, dma controller: stopped. dram controller: stopped. (reflesh timer is also stopped.) (watchdog timer: stopped.) table 23. microcomputer s operation in stp and wit modes
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 104 fig. 103 bit configuration of particular function select register 1 76543210 particular function select register 1 stp-instruction-execution status bit (note 1) 0: normal operation. 1: stp instruction has been executed. wit-instruction-execution status bit (note 1) 0: normal operation. 1: wit instruction has been executed. standby state select bit 0: external bus 1: programmable i/o port internal clock stop select bit at wit (note 2) 0: in wait mode, internal peripheral devices operation clock is active. 1: in wait mode, internal peripheral devices operation clock is stopped. 0 at read. address 63 16 notes 1: at power-on reset, this bit becomes 0 . at hardware reset or software reset, this bit retains the status just before reset. even when 1 is written, the bit status will not change. 2: setting this bit to 1 must be performed just before execution of the wit instruction. also, after the wit state is terminated, this bit must be cleared to 0 immediately. fig. 102 bit configuration of particular function select register 0 76543210 particular function select register 0 external clock input select bit (note) 0: oscillation circuit is active. (oscillator is connected.) watchdog timer is used at stop mode termination. 1: oscillation circuit is inactive. (clock which is generated in the external is input.) watchdog timer is not used at stop mode termination. 0 at read. stp instruction invalidity select bit 0: stp instruction is valid. 1: stp instruction is invalid. address 62 16 note: writing to these bits requires the following procedure: write 55 16 to this register. (the bit status does not change only by this writing.) succeedingly, write 0 or 1 to each bit. troller is operating, dram reflesh is performed. note that the watch- dog timer is stopped. on the other hand, when the wit instruction is executed with the in- ternal clock stop select bit at wit = 1 , the oscillation circuit is oper- ating, while 1 immediately before execution of the wit instruction and cleared to 0 immediately after the wit mode is terminated. the wit state is terminated by acceptance of an interrupt request, and then, supply of
105 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers power saving function the following functions can save the power dissipation of the whole system. (1) bus fixation in stp and wit modes by setting the standby state select bit (bit 2 of the particular function select register 1) to 1 , in the stop or wait state, the i/o pins of the external buses and bus control signals can be switched to program- mable i/o port pins. by setting these pins state with the correspond- ing port registers and port direction registers, unnecessary current will not flow between the microcomputer and external devices. as a result, in the stop or wait mode, the power dissipation of the whole system can be saved. table 24 lists the correspondence between the external buses, bus control signals, and programmable i/o port pins. this function is valid only in the stop or wait state. at termination of the stop or wait mode, the original functions of external buses and bus control signals become valid. table 24. correspondence between external buses, bus control sig- nals, and programmable i/o port pins external buses, bus control signals a 0 to a 7 , a 8 to a 15 , a 16 to a 23 0 standby state select bit a 0 to a 7 , a 8 to a 15 , a 16 to a 23 1 d 0 to d 7 , d 8 to d 15 (note 1) d 0 to d 7 , d 8 to d 15 p10 0 to p10 7 (note 2) , p11 0 to p11 7 (note 2) , p0 0 to p0 7 (note 2) p1 0 to p1 7 (note 2) , p2 0 to p2 7 rd, blw, bhw rd, blw, bhw (note 1) p3 1 , p3 2 (note 2) , p3 3 cs 0 cs 0 p9 0 (note 2) notes 1: when the external data bus width = 8 bits (byte = v cc level), this becomes a programmable i/o port pin, regardless of the standby state select bit s contents. 2: pin functions of port pins p0, p1, p3 1 , p3 2 , p9 0 , p10, p11 are not shown in the pin configuration. however, relationship with corresponding bus signals and ports is listed in table 24. for the addresses of these port s registers and direction registers, refer to the location of the perpheral devices control register (figures 4 and 5). (2) stop of internal clock in wait mode in the wit mode, if the internal peripheral devices need not to be operated, be sure to set the internal clock stop select bit at wit (bit 3 of the particular function select register 1) to 1 . as a result, the clock source for each internal peripheral device is stopped, and the power dissipation of the microcomputer can be saved. for details, refer to the section on the stop and wait modes. (3) stop of oscillation circuit when an externally-generated-stable clock is input to pin x in , the power dissipation can be saved if both of the following conditions are met: the external clock input select bit (bit 1 of the particular function select register 0) = 1 . the oscillation driver circuit between pins x in and x out stops its operation. at this time, the output level at pin x out is fixed to h . when the stp mode is terminated by an interrupt request occurrence, the watch- dog timer is not used. therefore, an instruction can be executed just after the termination of the stp mode. for details, refer to the sec- tion on the clock generating circuit and stop and wait modes. (4) disconnection from pin v ref when not using the a-d converter, by setting the v ref connection select bit (bit 6 of the a-d control register 1) to 1 , the ladder network of the a-d converter will be disconnected from the reference voltage input pin (v ref ). in this case, no current flows from pin v ref to the ladder network, and the power dissipation can be saved. note that, after the v ref connection select bit changes from 1 (v ref discon- nected) to 0 (v ref connected), be sure that the a-d conversion starts a period of 1 ? or more has elapsed. for details, refer to the section on the a-d converter.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 106 fig. 104 microcomputer internal register s status just after reset (1) 00 00 ( 04 16 ) address port p0 direction register 00 16 ( 05 16 ) port p1 direction register ( 08 16 ) port p2 direction register ( 09 16 ) port p3 direction register ( 15 16 ) port p9 direction register 00 16 ( 0c 16 ) port p4 direction register ( 0d 16 ) port p5 direction register 00 16 ( 10 16 ) port p6 direction register ( 11 16 ) port p7 direction register ( 14 16 ) port p8 direction register ( 56 16 ) timer a0 mode register 00 16 ( 57 16 ) timer a1 mode register 00 16 ( 58 16 ) timer a2 mode register 00 16 ( 59 16 ) timer a3 mode register 00 16 ( 5a 16 ) timer a4 mode register 00 16 ( 18 16 ) port p10 direction register 00 16 ( 19 16 ) port p11 direction register 00 16 notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: the status just after reset depends on the voltage level applied to pin md0. 3: at power-on reset, these bits are clear to 0 . at hardware or software reset, on the other hand, these bits retain the state just before reset. 0 000 0 ??? ( 1e 16 ) a-d control register 0 0 000 001 ( 1f 16 ) a-d control register 1 1 0 0 000 ( 34 16 ) uart 0 transmit/receive control register 0 1 0 0 000 ( 3c 16 ) uart 1 transmit/receive control register 0 0 000 0 010 ( 35 16 ) uart 0 transmit/receive control register 1 0 000 0 010 ( 3d 16 ) uart 1 transmit/receive control register 1 0 0 000 ( 42 16 ) one-shot start register 00 ( 45 16 ) timer a clock division select register ( 1c 16 ) port p12 direction register ( 30 16 ) uart 0 transmit/receive mode register 00 16 ( 38 16 ) uart 1 transmit/receive mode register 00 16 0 000 0 0 000 ( 44 16 ) up-down register ( 40 16 ) count start register 00 16 0 0? 0 000 ( 5b 16 ) timer b0 mode register 0 0? 0 000 ( 5c 16 ) timer b1 mode register 0 0? 0 000 ( 5d 16 ) timer b2 mode register 1 000 (note 2) 0 (note 2) 0 ( 5e 16 ) processor mode register 0 ( 5f 16 ) processor mode register 1 ( 60 16 ) address watchdog timer (note 3) 0 1 0 0 000 0000 0 fff 16 ( 61 16 ) watchdog timer frequency select register ( 62 16 ) particular function select register 0 ( 63 16 ) particular function select register 1 ( 66 16 ) debug control register 0 ( 67 16 ) debug control register 1 int 2 interrupt control register processor status register ps 00 16 00 16 program bank register pg contents at address ffff 16 program counter pc h contents at address fffe 16 program counter pc l 0000 16 ( 6e 16 ) int 3 interrupt control register ( 6f 16 ) int 4 interrupt control register 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ( 72 16 ) uart 0 receive interrupt control register ( 73 16 ) uart 1 transmit interrupt control register ( 74 16 ) uart 1 receive interrupt control register ( 77 16 ) timer a2 interrupt control register ( 78 16 ) timer a3 interrupt control register ( 79 16 ) timer a4 interrupt control register ( 7a 16 ) timer b0 interrupt control register 0 00 000 ( 7c 16 ) timer b2 interrupt control register 000 ( 7e 16 ) int 1 interrupt control register ( 70 16 ) a-d conversion interrupt control register ( 71 16 ) uart 0 transmit interrupt control register ( 75 16 ) timer a0 interrupt control register ( 76 16 ) timer a1 interrupt control register 0 00 000 ( 7d 16 ) int 0 interrupt control register ( 7b 16 ) timer b1 interrupt control register direct page registers dpr0 to dpr3 ( 7f 16 ) 0 00 1?? 0 00 ?? 0 00 data bank register dt 00 16 00 00 (note 2) 0 (note 2) 1 000 (note 3) 0000 0 0 000 0 000 000 0000 0 000 000 0 000 000 fff 16 stack pointer 000 (note 3) (note 3)
107 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 105 microcomputer internal register s status just after reset (2) ( 80 16 ) address cs 0 control register l ( 81 16 ) cs 0 control register h ( 82 16 ) cs 1 control register l ( 83 16 ) cs 1 control register h ( 8c 16 ) area cs 1 start address register ( 84 16 ) cs 2 control register l ( 85 16 ) cs 2 control register h ( 86 16 ) cs 3 control register l ( 87 16 ) cs 3 control register h ( 8a 16 ) area cs 0 start address register ( dc 16 ) dma1 mode register l ( dd 16 ) dma1 mode register h ( de 16 ) dma1 control register ( ec 16 ) dma2 mode register l ( ed 16 ) dma2 mode register h ( 8e 16 ) area cs 2 start address register ( 90 16 ) area cs 3 start address register notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: the status just after reset depends on the voltage level applied to pin md0. 3: while vss level voltage is applied to pin byte, these bits are 0 . while vcc level voltage is applied to pin byte, on the other hand, these bits are 1 . 0 000 0 ( a8 16 ) dram control register ( b2 16 ) dma0 interrupt control register 0000 ( b3 16 ) dma1 interrupt control register 0000 ( b4 16 ) dma2 interrupt control register ( cc 16 ) dma0 mode register l 000 ( ce 16 ) dma0 control register ( a0 16 ) real-time output control register ( ac 16 ) cts/rts separate select register ( b0 16 ) dmac control register l 0 0 00 0 000 ( cd 16 ) dma0 mode register h ( b5 16 ) dma3 interrupt control register 0 0 000 ( ee 16 ) dma2 control register ( fc 16 ) dma3 mode register l ( fd 16 ) dma3 mode register h ( fe 16 ) address dma3 control register 0 00 0 0 00 0 000 0 10 (note 2) (note 3) 10 0 100 0 (note 3) 10 0 100 0 (note 3) 10 0 100 0 (note 3) 10 000 0000 0000 0 0 00 0 000 000 0 00 0 0 00 0 000 0 0 00 000 0 001 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0 0 000 0 00 0 0 000 0 00 0 0 00 000 0 00 00 0 0 0 0 000 0 0 0 0 0 001 0 000 0 000 000 0 000 0 000 0 000 0 000 ( 9e 16 ) flash memory control register 0 00 001 0 000 00 ( b1 16 ) dmac control register h 00 reset circuit while the power source voltage satisfies the recommended operat- ing condition, reset state is removed if pin reset s level returns from the stabilized l level to the h level. as a result, program ex- ecution starts from the reset vector address. this reset vector ad- dress is expressed as shown below: a 23 to a 16 = 00 16 a 15 to a 8 = contents at address ffff 16 a 7 to a 0 = contents at address fffe 16 figures 104 and 105 show the microcomputer internal register s sta- tus just after reset, and figure 106 shows an operation example of the reset circuit. apply l level voltage to pin reset for a period (2 ? or more) under the following conditions: pin vcc s level satisfies the recommended operating condition. oscillator s operation has been stabilized. fig. 106 operation example of reset circuit (note that proper evalu- ation is necessary in the system development stage.) v cc reset power on v cc level 0.2v cc level oscillation stabilized 2
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 108 input/output pins each of ports p0 to p12 has an direction register, and each bit can be programmed for input or output. a pin becomes an output pin when the corresponding bit of direction register is 1 , and an input pin when it is 0 . when a pin is programmed as an output pin, the data written to its port latch is output to the output pin. when a pin is programmed as an output pin, the contents of the port latch are read out instead of the value of the pin. accordingly, a previously output value can be read out correctly even when the output h voltage is lowered or the output l voltage is raised, owing to an external load, etc. a pin programmed as an input pin is placed in the flooting state, and the value input to the pin can be read out correctly. when a pin is pro- grammed as an input pin, the data can be written only in the port latch, and the pin remains floating. each of figures 107 and 108 shows the block diagram for each port pin.
109 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 107 block diagram for each port pin (1) [inside dotted-line not included] p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 1 to p3 3 , p10 0 to p10 7 , p11 0 to p11 7 [inside dotted-line included] p3 0 /rdy, p4 3 /hold, p6 1 /ta1 in /dmareq 0 , p6 3 /ta3 in /dmareq 1 , p6 5 /ta4 in /dmareq 2 , p6 6 /dmareq 3 , p8 1 /rxd 1 , p8 5 /rxd 0 , p12 0 /int 0 /tb0 in , p12 1 /int 1 /tb1 in , p12 2 /int 2 /tb2 in data bus direction register port latch p4 0 /ale, p4 1 / 1 , p4 4 /hlda, p6 0 /ta1 out /dmaack 0 , p6 2 /ta3 out /dmaack 1 , p6 4 /ta4 out /dmaack 2 , p8 0 /txd 1 , p8 4 /txd 0 , p9 0 /cs 0 , p9 1 /cs 1 /ras 1 , p9 2 /cs 2 /ras 2 , p9 3 /cs 3 /ras 3 , p9 4 /cas/w, p9 5 /wrl/lcas, p9 6 /wrh/ucas data bus direction register port latch ? output (internal peripheral devices) [inside dotted-line not included] p5 2 /rtp0 2 , p5 3 /rtp0 3 , p5 4 /rtp1 0 , p5 5 /rtp1 1 [inside dotted-line included] p5 1 /ta0 in /rtp0 1 , p5 7 /ta2 in /rtp1 3 data bus direction register port latch latch t q ck timer underflow signal p5 0 /ta0 out /rtp0 0 , p5 6 /ta2 out /rtp1 2 data bus direction register port latch 1 latch t q ck timer underflow signal output (internal peripheral devices)
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 110 [inside dotted-line not included] p7 0 /an 0 , p7 1 /an 1 [inside dotted-line included] p7 2 /an 2 /int 3 , p7 3 /an 3 /ad trg /int 4 data bus direction register port latch analog input p8 2 /cts 0 /clk 1 , p8 3 /cts 0 /rts 0 , p8 6 /clk 0 data bus direction register port latch 1 0 output (internal peripheral devices) p4 2 /tc data bus direction register port latch 0 output (tc) fig. 108 block diagram for each port pin (2)
111 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers clock generating circuit in the clock generating circuit, the basic clock which is used to oper- ate the cpu and each internal peripheral device is made by a clock input from pin x in . figure 111 shows the block diagram of the clock generating circuit. the clock which is input from the external clock in- put pin, x in , generates the following; f 2 indicates that this clock is f 1( l state. the stp mode is terminated by acceptance of an interrupt, and the oscillation is started. simultaneously, supply of 0 , supply of l state. however, s recommended values. figure 110 shows a circuit e example with an external clock source. fig. 109 circuit example with external ceramic resonator or quartz crystal oscillator fig. 110 circuit example with external clock source x in r f x out r d c in c out x in x out left open. external oscillation circuit vcc vss
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 112 fig. 111 block diagram of clock generating circuit f 2 f 64 f 512 wit instruction f 4096 r sq q r s q r s stp instruction interrupt request biu cpu cpu wait request from biu 1/4 1/8 1/8 reset watchdog timer frequency select bit : bit 0 at address 61 16 external clock input select bit : bit 1 at address 62 16 internal clock stop select bit at wit : bit 3 at address 63 16 cpu : central processing unit biu : bus interface unit : signal generated when the watchdog timer? most significant bit becomes ?? operating clock for serial i/o, timer b 1/8 1/2 1/16 watchdog timer wf 32 wf 512 f 16 f 1(
113 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig. 112 block diagram of debug function address compare register 0 address compare register 1 debug control register 0 matching compare register matching compare register address matching detect circuit debug control register 1 internal data bus (db 0 to db 15 ) cpu bus (address) address matching detection interrupt debug function when the cpu fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of pg and pc). the decision whether this condition is satisfied or not is called ad- dress matching detection, and the interrupt generated by this detec- tion is called an address matching detection interrupt. (for interrupt vector addresses, refer to the section on interrupts.) in the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. the debug function provides the following two modes: the address matching detection mode, which is used to avoid the area where program exists or modify a program. the out-of-address-area detection mode, which is used to detect a program runaway. figure 112 shows the block diagram of the debug function. figures 113 and 114 show the bit configurations of the debug control regis- ters 0, 1, and address compare registers 0,1, respectively. the detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. when the selected address condition is satisfied, an address matching detec- tion interrupt request will be generated: (1) address matching detection 0 the contents of pg and pc match with the address which has been set in the address compare register 0. (2) address matching detection 1 the contents of pg and pc match with the address which has been set in the address compare register 1. (3) address matching detection 2 the contents of pg and pc match with the address which has been set in either of the address compare register 0 or address compare register 1. (4) out-of-address-area detection the contents of pg and pc are less than the address which has been set in the address compare register 0 or larger than the ad- dress which has been set in the address compare register 1. by setting the detect enable bit of the debug control register 0 to 1 , an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. clearing the detect enable bit to 0 generates no interrupt request even if any of the above address conditions is satisfied. the address compare register access enable bit of the debug con- trol register 1 must be set to 1 by the instruction just before the ac- cess operation (read/write). then, this bit must be cleared to 0 (disabled) by the next instruction. while this bit = 0 , the address compare registers 0, 1 cannot be accessed. the address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of pg, pc, when the address matching detection 2 is selected. the con- tents of this bit is invalid when address matching detection 0 or 1 is selected. in order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. as a result, the contents of pg, pc, ps at acceptance of an address matching detection inter- rupt request (i.e. the address at which an address matching detec- tion condition is satisfied) have been pushed on to the stack. if a return destination address after the interrupt processing is to be al- tered, rewrite the contents of the stack, and then return by the rti instruction. to use the debug function to detect a program runaway, set an ad- dress area where no program exists into the address compare regis- ters 0 and 1 by using the out-of-address-area detection. when the cpu fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be gener- ated. the above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is run- ning.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 114 fig. 113 bit configuration of debug control register 0, 1 fig. 114 bit configuration of address compare register 0, 1 76543210 debug control register 0 detect condition select bits (note 1) 000: do not select. 001: address matching detection 0 010: address matching detection 1 011: address matching detection 2 100: do not select. 101: out-of-address-area detection 110: do not select. 111: do not select. fix this bit to 0 (note 1) . detect enable bit (note 1) 0: detection disabled. 1: detection enabled. fix this bit to 0 (note 1) . 1 at read. address 66 16 76543210 debug control register 1 fix this bit to 0 (note 1) . 0 at read (note 1) . address compare register access enable bit (note 2) 0: disabled 1: enabled fix this bit to 1 when using the debug function. fix this bit to 0 (note 1) . while debugger is not used, 0 at read. while debugger is used, 1 at read. address-matching-detection 2 decision bit valid when address matching detection 2 is selected. 0: matches with the contents of the address compare register 0. 1: matches with the contents of the address compare register 1. 0 at read. address 67 16 0 0 0 0 1 0 1 0 notes 1: at power-on reset, these bits = 0 ; at hardware reset or software reset, these bits retain the value just before reset. 2: set this bit to 1 with the instruction just before the address compare register 0, 1 (addresses 68 16 to 6d 16 ) is accessed. and then, clear this bit to 0 with the instruction just after the access. 0 address compare register 0 address compare register 1 the address to be detected (in other words, the start address of instruction) is set here. address 68 16 , 69 16 , 6a 16 6b 16 , 6c 16 , 6d 16 (23) 7 (8) (15) (16) 0 7 0 7
115 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers flash memory mode these microcomputers contain the dinor (divided bit line nor)- type flash memory; and single-power-supply reprogramming is avail- able to this. these microcomputers have the following three modes, enabling reading/programming/erasure for the flash memory: ?flash memory parallel i/o mode and flash memory serial i/o mode, where the flash memory is handled by using an external pro- grammer. ?cpu reprogramming mode, where the flash memory is handled by the central processing unit (cpu). as shown in figures 116 and 117, the flash memory is divided into several blocks, and erasure per block is possible. each of these blocks is provided with a lock bit, which determines the validity of erasure/program execution. therefore, data protection per block is possible. this internal flash memory has the boot rom area storing the repro- gramming control software for reprogramming in the cpu repro- gramming mode and flash memory serial i/o mode, as well as the user rom area storing a certain control software for the normal op- eration in the microcomputer mode. although our reprogramming control firmware for the flash memory serial i/o mode has been stored into this boot rom area on ship- ment, the user-original reprogramming control software which is more appropriate for the users system is reprogrammable into this area, instead. note that the reprogramming for the boot rom area is enabled only in the flash memory parallel i/o mode. fig. 116 M37920FCCGP, m37920fcchp: block configuration of internal flash memory 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 8 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 002000 16 004000 16 001000 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 120 kbytes notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 00ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ffbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 116 fig. 117 m37920fgcgp, m37920fgchp: block configuration of internal flash memory notes 1: in the flash memory mode, the read/programming/erase operation cannot be performed for areas except for the internal flash memory area. 2: the boot rom area can be reprogrammed only in the flash memory parallel i/o mode. when the boot rom area is read out by the cpu, these addresses are shifted to addresses 00c000 16 00ffff 16 (byte addresses). 3: the reserved area for the serial programmer is assigned to addresses ffb0 16 ffbf 16 (byte addresses). when the flash memory serial i/o mode is used, do not program to this area. 16 kbytes 001fff 16 boot rom area user rom area 32 kbytes 8 kbytes 8 kbytes 8 kbytes 01ffff 16 003fff 16 005fff 16 006000 16 007fff 16 00ffff 16 010000 16 008000 16 00ffff 16 001fff 16 002fff 16 003000 16 003fff 16 007fff 16 008000 16 004000 16 002000 16 004000 16 001000 16 002000 16 byte address word address 000000 16 003fff 16 000000 16 byte addresses word addresses 64 kbytes total 248 kbytes 64 kbytes 64 kbytes 02ffff 16 020000 16 017fff 16 010000 16 03ffff 16 030000 16 01ffff 16 018000 16
117 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers flash memory parallel i/o mode the flash memory parallel i/o mode is used to manipulate the inter- nal flash memory with a parallel programmer. this parallel program- mer uses the software commands listed in table 25 to do the flash memory manipulations, such as read/programming/erase opera- tions. in the flash memory parallel i/o mode, each block can be protected from erasing/programming (in other words, block lock). table 25. software commands (flash memory parallel i/o mode) software command read array read status register clear status register page programming (note) block erase erase all unclocked block lock bit programming read lock bit status note: programming is performed in a unit of 256 bytes, with the low-order address assigned in the range of 00 16 ff 16 (byte addresses). user rom area and boot rom area the user rom area and boot rom area can be reprogrammed in the flash memory parallel i/o mode. the programming and block erase operations can be performed only to these areas. the boot rom area, 16 kbytes in size, is assigned to addresses 0000 16 3fff 16 (byte addresses), so that programming and block erase operations can be performed only to this area. (access to any address out of this area is prohibited). the erasable block in the boot rom area is only one block, consist- ing of 16 kbytes. the reprogramming control firmware to be used in the flash memory serial i/o mode has been stored to this boot rom area on our shipment. therefore, do not reprogram the boot rom area if the user uses the flash memory serial i/o mode. addresses ffb0 16 to ffbf 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area. note that, when the boot rom area is read out from the cpu in the cpu reprogramming mode, described later, its addresses will be shifted to c000 16 ffff 16 (byte addresses).
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 118 pin description (flash memory serial i/o mode) v cc , v ss md0 md1 reset x in x out byte avcc, avss v ref p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 3 p4 0, p4 1 p4 2 p4 3 p4 4 p5 0 p5 7 p6 0 p6 6 p7 0 p7 3 p8 0 p8 6 p9 0 p9 6 p10 0 p10 7 p11 0 p11 7 p12 0 p12 2 nmi pin power supply input md0 md1 reset input clock input clock output byte analog supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 sda i/o busy output sclk input input port p5 input port p6 input port p7 input port p8 input port p9 input port p10 input port p11 input port p12 non-maskable interrupt name input input input input output input input input input input input input i/o output input input input input input input input input input input input /output functions apply 5 v 0.5 v to vcc, and 0 v to vss. connect this pin to vss. connect this pin to vss via a resistor of 10 k ? to 100 k ? . the reset input pin. connect a ceramic resonator between the x in and x out pins, or input an external clock from the x in pin with the x out pin left open. connect this pin to vcc or vss. (this is not used in the flash memory serial i/o mode.) connect avcc to vcc, and avss to vss. input an arbitrary level within the range of v ss v cc . (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) this is an i/o pin for serial data. connect this pin to v cc via a resistor (about 1 k ? ). this is an output pin for the busy signal. this is an input pin for a serial clock. input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h or l , or leave them open. (this is not used in the flash memory serial i/o mode.) input h , or leave this pin open.
119 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers flash memory serial i/o mode in the flash memory serial i/o mode, addresses, data, and software commands, which are required to read/program/erase the internal flash memory, are serially input and output with a fewer pins and the dedicated serial programmer. in this mode, being different from the flash memory parallel i/o mode, the cpu controls reprogramming of the flash memory (using the cpu reprogramming mode), serial input of the reprogramming data, etc. the reprogramming control firmware for the flash memory serial i/o mode has been stored in the boot rom area on shipment of the product from us. note that, then, the flash memory serial i/o mode will become unavailable if the boot rom area has been repro- grammed in the flash memory parallel i/o mode. note that, also, this reprogramming control firmware for the flash memory serial i/o mode is subject to change. figures 118 and 119 show the pin connections in the flash memory serial i/o mode. the three pins, sclk, sda, and busy, are used to input and output serial data. the sclk pin is the input pin of external transfer clocks. the sda pin is the i/o pin of transmit and receive data, and its output acts as the n-channel open-drain output. to the sda pin, connect an exter- nal pullup resistor (about 1 k ? ). the busy pin is the output pin of the busy flag (cmos output) and goes h during busy periods owing to a certain operation, such as transmit, receive, erase, program- ming, etc. transmit and receive data are serially transferred 8 bits at a time. in the flash memory serial i/o mode, only the user rom area can be reprogrammed; the boot rom area is not accessible. addresses ffb0 16 to ffbf 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 120 fig.118 pin connection of m37920fxcgp in flash memory serial i/o mode output 100p6s-a ? : connect to the ceramic oscillation circuit. sclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p6 6 /dmareq 3 ? p6 5 /ta4 in /dmareq 2 ? p6 4 /ta4 out /dmaack 2 ? p6 0 /ta1 out /dmaack 0 ? p5 7 /ta2 in /rtp1 3 ? p5 6 /ta2 out /rtp1 2 ? p5 5 /rtp1 1 ? p5 4 /rtp1 0 ? p5 3 /rtp0 3 ? p5 2 /rtp0 2 ? p5 1 /ta0 in /rtp0 1 ? p5 0 /ta0 out /rtp0 0 ? p9 6 /wrh/ucas ? p9 5 /wrl/lcas ? p9 4 /cas/w ? p9 3 /cs 3 /ras 3 ? p9 2 /cs 2 /ras 2 ? p9 1 /cs 1 /ras 1 ? p9 0 /cs 0 ? p4 4 /hlda ? p4 3 /hold ? p4 2 /tc ? p4 1 / 1 ? p4 0 /ale ? p3 3 /bhw ? p3 2 /blw ? p3 1 /rd ? 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p6 3 /ta3 in /dmareq 1 ? p6 2 /ta3 out /dmaack 1 ? p6 1 /ta1 in /dmareq 0 ? ? p3 0 /rdy byte nmi reset md0 v ss x in x out v cc ? p2 7 /d 15 ? p2 6 /d 14 ? p2 5 /d 13 ? p2 4 /d 12 ? p2 3 /d 11 ? p2 2 /d 10 ? p2 1 /d 9 ? p2 0 /d 8 ? p1 7 /d 7 ? p1 4 /d 4 ? p1 3 /d 3 ? p1 2 /d 2 ? p1 1 /d 1 ? p1 0 /d 0 md1 v ss ? p0 7 /a 23 ? p0 6 /a 22 /ma 11 ? p0 5 /a 21 ? p0 4 /a 20 /ma 10 ? p0 3 /a 19 ? p0 2 /a 18 /ma 9 ? p0 1 /a 17 ? p0 0 /a 16 /ma 8 ? p11 7 /a 15 /ma 7 ? p11 6 /a 14 /ma 6 ? p11 5 /a 13 /ma 5 ? p11 4 /a 12 /ma 4 ? p11 3 /a 11 /ma 3 ? p11 2 /a 10 /ma 2 ? p11 1 /a 9 /ma 1 ? p11 0 /a 8 /ma 0 ? p10 7 /a 7 ? p10 6 /a 6 ? p10 5 /a 5 ? p10 4 /a 4 ? p10 3 /a 3 ? p10 2 /a 2 ? p10 1 /a 1 ? p1 6 /d 6 ? p1 5 /d 5 p10 0 /a 0 ? p8 6 /clk 0 ? p8 5 /r x d 0 ? p8 4 /t x d 0 ? p8 3 /cts 0 /rts 0 ? p8 2 /cts 0 /clk 1 ? p8 1 /r x d 1 ? v cc av cc v ref av ss v ss p7 3 /an 3 /ad trg /int 4 ? p7 2 /an 2 /int 3 ? p7 1 /an 1 ? p7 0 /an 0 ? p12 2 /int 2 /tb2 in ? p12 1 /int 1 /tb1 in ? p12 0 /int 0 /tb0 in ? p8 0 /t x d 1 ? M37920FCCGP m37920fgcgp ? v ss reset v cc busy sda
121 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig.119 pin connection of m37920fxchp in flash memory serial i/o mode output 100p6q-a sclk v ss reset v cc busy sda 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p6 6 /dmareq 3 ? p6 5 /ta4 in /dmareq 2 ? p6 4 /ta4 out /dmaack 2 ? p6 0 /ta1 out /dmaack 0 ? p5 7 /ta2 in /rtp1 3 ? p5 6 /ta2 out /rtp1 2 ? p5 5 /rtp1 1 ? p5 4 /rtp1 0 ? p5 3 /rtp0 3 ? p5 2 /rtp0 2 ? p5 1 /ta0 in /rtp0 1 ? p5 0 /ta0 out /rtp0 0 ? p9 6 /wrh/ucas ? p9 5 /wrl/lcas ? p9 4 /cas/w ? p9 3 /cs 3 /ras 3 ? p9 2 /cs 2 /ras 2 ? p9 1 /cs 1 /ras 1 ? p9 0 /cs 0 ? p4 4 /hlda ? p4 3 /hold ? p4 2 /tc ? p4 1 / 1 ? p4 0 /ale ? 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 p6 3 /ta3 in /dmareq 1 ? p6 2 /ta3 out /dmaack 1 ? p6 1 /ta1 in /dmareq 0 ? ? p3 0 /rdy 30 29 28 ? p3 1 /rd 27 ? p3 2 /blw 26 ? p3 3 /bhw byte nmi reset md0 v ss x in x out v cc ? p2 7 /d 15 ? p2 6 /d 14 ? p2 5 /d 13 ? p2 4 /d 12 ? p2 3 /d 11 ? p2 2 /d 10 ? p2 1 /d 9 ? p2 0 /d 8 ? p1 7 /d 7 ? p1 4 /d 4 ? p1 3 /d 3 ? p1 2 /d 2 ? p1 1 /d 1 ? p1 0 /d 0 md1 v ss ? p0 7 /a 23 ? p0 6 /a 22 /ma 11 ? p0 5 /a 21 ? p0 4 /a 20 /ma 10 ? p0 3 /a 19 ? p0 2 /a 18 /ma 9 ? p0 1 /a 17 ? p0 0 /a 16 /ma 8 ? p11 7 /a 15 /ma 7 ? p11 6 /a 14 /ma 6 ? p11 5 /a 13 /ma 5 ? p11 4 /a 12 /ma 4 ? p11 3 /a 11 /ma 3 ? p11 2 /a 10 /ma 2 ? p11 1 /a 9 /ma 1 ? p11 0 /a 8 /ma 0 ? p10 7 /a 7 ? p10 6 /a 6 ? p10 5 /a 5 ? p10 4 /a 4 ? p1 6 /d 6 ? p1 5 /d 5 p10 0 /a 0 ? 80 p10 1 /a 1 ? 79 p10 2 /a 2 ? 78 p10 3 /a 3 ? 77 76 p8 6 /clk 0 ? p8 5 /r x d 0 ? p8 4 /t x d 0 ? p8 3 /cts 0 /rts 0 ? p8 2 /cts 0 /clk 1 ? p8 1 /r x d 1 ? v cc av cc v ref av ss v ss p7 3 /an 3 /ad trg /int 4 ? p7 2 /an 2 /int 3 ? p7 1 /an 1 ? p7 0 /an 0 ? p12 2 /int 2 /tb2 in ? p12 1 /int 1 /tb1 in ? p12 0 /int 0 /tb0 in ? p8 0 /t x d 1 ? m37920fcchp m37920fgchp : connect to the ceramic oscillation circuit.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 122 cpu reprogramming mode the cpu reprogramming mode is used to perform the operations for the internal flash memory (reading, programming, erasing) under control of the cpu. in this mode, only the user rom area can be reprogrammed; the boot rom area cannot be reprogrammed. the user-original reprogramming control software for the cpu repro- gramming mode can be stored in either the user rom area or the boot rom area. because the cpu cannot read out the flash memory in the cpu reprogramming mode, the above software must be trans- ferred to the internal ram in advance to be executed. boot mode the user-original reprogramming control software for the cpu re- programming mode must be stored into the user rom area or the boot rom area in the flash memory parallel i/o mode in advance. (if this program has been stored into the boot rom area, the flash memory serial i/o mode will become unavailable). note that addresses of the boot rom area depend on the accessing ways to the boot rom area, when accessing in the flash memory parallel i/o mode, these addresses will be shifted to 0000 16 to 3fff 16 (byte address). on the other hand, when accessing with the cpu, these addresses will be shifted to c000 16 to ffff 16 (byte address). reset removal with both of the md0 and md1 pins held ??invokes the normal microcomputer mode, and the cpu operates using the control software stored in the user rom area. in this case, the boot rom area is not accessible. removing reset with the md0 pin held ??and the md1 pin ?? the cpu starts its operation using the reprogramming control software stored in the boot rom area. this mode is called the boot mode. the reprogramming control software in the boot rom area can also re- program the user rom area. after reset removal, be sure not to change the status at pins md0 and md1. fig. 120 bit configuration of flash memory control register flash memory control register ry/by status bit 0: busy (programming or erasing is active.) 1: ready cpu reprogramming mode select bit (note 2) 0: normal mode (software commands are ignored.) 1: cpu reprogramming mode (software commands are acceptable.) lock bit invalidity select bit (note 3) 0: block lock by lock bit data is valid. 1: block lock by lock bit data is invalid. flash memory reset bit (note 4) 0: normal operation 1: reset must be 0 . user rom area select bit (note 5) (valid only in the boot mode.) 0: boot rom area access 1: user rom area access address 9e 16 76543210 0 notes 1: the contents of the flash memory control register after reset is removed are xx000001 2 . 2: to set 1 , writing of 0 to bit 1 and subsequent writing of 1 to bit 1 are necessary. writing to bit 1 must be performed by the user-original reprogramming control software in the internal ram. 3: to set 1 , writing of 0 to bit 2 and subsequent writing of 1 to bit 2 are necessary while bit 1 = 1 . 4: valid only when bit 1 = 1 . set bit 3 to 1 (reset), and then clear to 0 . this bit 3 must be controlled with the cpu reprogramming mode select bit (bit 1) = 1 . 5: writing to bit 5 must be performed by the user-original reprogramming control software in the internal ram.
123 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers function overview (cpu reprogramming mode) the cpu reprogramming mode is available in the single-chip mode, memory expansion mode, and boot mode to reprogram the user rom area only. in the cpu reprogramming mode, the cpu erases, programs, and reads the internal flash memory by writing software commands. note that the user-original reprogramming control software must be trans- ferred to the internal ram in advance to be executed. the cpu reprogramming mode becomes active when 1 is written into the flash memory control register s bit 1 (the cpu reprogram- ming mode select bit) shown in figure 120, and software commands become acceptable. in the cpu reprogramming mode, software commands and data are all written to and read from even addresses (note that address a 0 in byte addresses = 0 .) 16 bits at a time. therefore, a software com- mand consisting of 8 bits must be written to an even address; there- fore, any command written to an odd address will be invalid. since the write data at the 2nd cycle of a programming command consists of 16 bits, this data must be written to even and odd addresses. the write state machine (wsm) in the flash memory controls the erase and programming operations. what the status of the wsm operation is and whether the programming or erase operation has been completed normally or terminated by an error can be examined by reading the status register. figure 120 shows the bit configuration of the flash memory control register. bit 0 (the ry/by status bit) is a read-only bit for indicating the wsm operation. this bit goes to 0 (busy) while the automatic program- ming/erase operation is active and goes to 1 (ready) during the other operations. bit 1 serves as the cpu reprogramming mode select bit. writing of 1 to this bit selects the cpu reprogramming mode, and software commands will be acceptable. because the cpu cannot directly ac- cess the internal flash memory in the cpu reprogramming mode, writing to this bit 1 must be performed by the user-original repro- gramming control software which has been transferred to the inter- nal ram in advance. to set bit 1 to 1 , it is necessary to write 0 and 1 to this bit 1 successively. on the other hand, to clear this bit to 0 , it is sufficient only to write 0 . bit 2 serves as the lock bit invalidity select bit, and setting this bit to 1 invalidates the protection by a lock bit against erasing and pro- gramming (block lock). the lock bit invalidity select bit can invali- dates the lock bit function but set no lock bit itself. however, if erasing is performed with this bit = 1 , a lock bit with value 0 (the locked state) will be set to 1 (the unlocked state) after the erasing has been completed. to set the lock bit invalidity select bit to 1 , write 0 and 1 to this bit 2 successively with the cpu reprogramming mode select bit = 1 . the manipulation of bit 2 is allowed only when the cpu reprogramming mode select bit = 1 . bit 3 (the flash memory reset bit) resets the control circuit of the in- ternal flash memory and is used when the cpu reprogramming mode is terminated or when an abnormal access to the flash memory happens. writing of 1 to bit 3 with the cpu reprogramming mode select bit = 1 preforms the reset operation. to remove the reset, write 0 to bit 3 subsequently. bit 5 serves as the user rom area select bit and is valid only in the boot mode. setting this bit to 1 in the boot mode switches an acces- sible area from the boot rom area to the user rom area. to use the cpu reprogramming mode in the boot mode, set this bit to 1 . note that when the microcomputer is booted up in the user rom area, only the user rom area is accessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid in- dependent of the cpu reprogramming mode. to rewrite bit 5, ex- ecute the user-original reprogramming control software transferred to the internal ram in advance. figure 121 shows the cpu reprogramming mode set/termination flowchart, and be sure to follow this flowchart. as shown in note 1 of figure 121, before selecting the cpu reprogramming mode, set the processor mode register 1 s bit 7 (the internal rom bus cycle select bit) to 0 and set flag i to 1 to avoid an interrupt request input. when an nmi interrupt or a watchdog timer interrupt request is gen- erated in the cpu reprogramming mode, when an input to the reset pin is l , or when the software reset is performed, the flash memory control circuit and flash memory control register will be re- set. when the flash memory is reset during the erase or programming operation, this operation is cancelled and the target block s data will be invalid. just before writing a software command related to the erase/programming operation, be sure to write to the watchdog timer. also, be sure to set the nmi pin to h to avoid an nmi interrupt request occurrence. in the cpu reprogramming mode, be sure not to use the stp and wit instructions.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 124 fig. 121 cpu reprogramming mode set/termination flowchart software commands table 26 lists the software commands. by writing a software command after the cpu reprogramming select bit has been set to ?? erasing, programming, etc. can be specified. note that, at software commands?input, the high-order byte (d 8 d 15 ) is ignored. (except for the write data at the 2nd cycle of a page programming command.) software commands are explained as below. read array command (ff 16 ) by writing command code ?f 16 ?at the 1st bus cycle, the microcom- puter enters the read array mode. if an address to be read is input in the next or the following bus cycles, the contents at the specified ad- dress are output to the data bus (d 0 to d 15 ) in a unit of 16 bits. the read array mode is maintained until writing of another software command. read status register command (70 16 ) writing command code ?0 16 ?at the 1st bus cycle outputs the con- tents of the status register to the data bus (d 0 -d 7 ) by a read at the 2nd bus cycle. the status register is explained later. clear status register command (50 16 ) this command clears three status bits (sr.3?) each of which is set to ??to indicate that the operation has been terminated by an error. to clear these bits, write command code ?0 16 ?at the 1st bus cycle. page programming command (41 16 ) page programming facilitates quick programming of 128 words (a page = 256 bytes) at a time. to initiate page programming, write command code ?1 16 ?at the 1st bus cycle; then, program a series of data, in a unit of 16 bits, sequentially from the 2nd to the 129th bus cycle. it is necessary, at this time, to increment address a 0 ? 7 from ?0 16 ?to ?e 16 ?by +2. (programmed to even addresses.) upon completion of data loading, automatic programming (data pro- gramming and verification) operation is started. the completion of the automatic programming operation is recog- nized by a read of the status register or a read of the flash memory control register. as the automatic programming operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. bit 7 of the sta- tus register (sr.7) is cleared to ??simultaneously with the start of the automatic programming operation; and also, bit 7 returns to ? by the end of it. until writing of the read array command (ff 16 ), writ- ing of the read lock bit status command (71 16 ), or performing the re- set operation with the flash memory reset bit, this read status register mode is maintained. in continuous programming, if there is no pro- gramming error, page programming commands can be executed with the read status register mode kept. completed start read array command is executed, or reset is performed by setting the flash memory reset bit. (writing of 1 writing of 0 ) (note 2) single-chip mode, memory expansion mode, or boot mode the processor mode register is set (note 1) . flag i is set to 1 . operations such as erasing, programming are executed by using software commands. (if necessary, the lock bit invalidity select bit is set.) jump to the above software in the internal ram. (the operations shown below will be executed by the above software in this ram.) the user-original reprogramming control software for the cpu reprogramming mode is transferred to the internal ram. (only in the boot mode.) writing of 0 to user rom area select bit (note 3) . writing of 0 to the cpu reprogramming mode select bit. (only in the boot mode.) the user rom area select bit is set to 1 . writing of 1 to the cpu reprogramming mode select bit. (writing of 0 writing of 1 ) notes 1: the processor mode register 1 s bit 7 (address 5f 16 , the internal rom access wait bit) must be 0 (1 wait). 2: to terminate the cpu reprogramming mode after the erase and programming operations have been completed, be sure to execute the read array command or perform the flash memory reset operation. 3: this bit may remain 1 . however, if this bit is 1 , the user rom area access is specified.
125 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers table 26. software commands (cpu reprogramming mode) command read array read status register clear status register page programming (note 3) block erase erase all unclocked block lock bit programming read lock bit status address x (note 2) x x x x x x x ff 16 70 16 50 16 41 16 20 16 a7 16 77 16 71 16 1st cycle 2nd cycle notes 1: at software commands input, the high-order byte of data (d 8 d 15 ) is ignored. 2: x = an arbitrary address in the user rom area. (note that a 0 = 0 .) 3: srd = status register data. 4: wa = write address, wd = write data (16 bits). wa and wd must be set from 00 16 to fe 16 . (byte addresses. incremented by +2. address a 0 = 0 .) page size = 128 words (128 16 bits). 5: block address: the maximum address of each block must be input. note that address a 0 = 0 . 6: d 6 indicates the block lock status. 1 = unlocked. 0 = locked. mode write write write write write write write write 3rd cycle (d 0 to d 7 ) data address x wa0 (note 4) ba (note 5) x ba ba srd (note 3) wd0 (note 4) d0 16 d0 16 d0 16 d 6 (note 6) mode read write write write write read data address wa1 mode write the ry/by status bit of the flash memory control register goes 0 during the automatic programming operation; and also, it goes 1 af- ter the end of it, the same way as bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of the status register (sr.7) or the ry/by status bit is set to 1 (ready). during the automatic programming operation, writing of commands and access to the flash memory must not be performed. reading out the status register after the automatic programming op- eration is completed reports the result of it. for details, refer to the section on the status register. figure 122 shows an example of the page programming flowchart. note that each block can be protected from programming by using a lock bit. for details, refer to the section on the data protect function. additional programming to any page that has already been pro- grammed is prohibited. block erase command (20 16 /d0 16 ) writing command code "20 16 " at the 1st bus cycle and writing verify command code "d0 16 " and the maximum address of the block (note that address a 0 = 0 .) at the subsequent 2nd bus cycle initiate the automatic erase (erasing and erase verification) operation for the specified block. the completion of the automatic erase operation is verified by a read of the status register or a read of the flash memory control register. as the automatic erase operation starts, the microcomputer enters the read status register mode automatically to allow reading out the contents of the status register. bit 7 of the status register (sr.7) is cleared to 0 simultaneously with the start of the automatic erase operation; and also, it returns to 1 by the end of it. the read status register mode is maintained until writing of the read array command (ff 16 ), writing of the read lock bit status command (71 16 ), or per- forming the reset operation with the flash memory reset bit. the ry/by status bit of the flash memory control register goes 0 during the automatic erase operation; and also, it goes 1 after the end of it, the same way as bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of data wd1 the status register (sr.7) or the ry/by status bit is set to 1 (ready). during the automatic erase operation, writing of com- mands and access to the flash memory must not be performed. reading out the status register after the automatic erase operation is completed reports the result of it. for details, refer to the section on the status register. figure 123 shows an example of the block erase flowchart. note that each block can be protected from erasing by using a lock bit. for details, refer to the section on the data protect function.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 126 fig.122 page programming flowchart fig.123 block erase flowchart fig.125 read lock bit status flowchart fig.124 lock bit programming flowchart n = fe 16 start write 41 16 n = 0 write address n , data n sr.7 = 1? status register read full status check page programming completed n = n + 2 no yes no yes write 20 16 write d0 16 status register read sr.7 = 1? full status check block erase completed no yes block address start sr.7 = 1? write 77 16 write d0 16 no yes sr.4 = 0? no lock bit programming completed block address lock bit programming error yes start block: unlocked write 71 16 d 6 = 0? block: locked no yes block address start
127 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers erase all unlocked block command (a7 16 /d0 16 ) writing command code a7 16 at the 1st bus cycle and writing verify command code d0 16 at the subsequent 2nd bus cycle initiate the continuous block erase (chip erase) operations for all the blocks. the completion of the chip erase operation, as well as of the block erase operation, is verified by a read of the status register or a read of the flash memory control register. the result of the automatic erase operation is also reported by a read of the status register. during the automatic erase operation (when the ry/by status bit = 0 ), writing of commands and access to the flash memory must not be performed. when the lock bit invalidity select bit = 1 , all the blocks are erased regardless of the status of their lock bits. when the lock bit invalidity select bit = 0 , on the contrary, the status of each lock bit becomes valid, so only the blocks in the unlocked state (lock bit = 1 ) are erased. lock bit programming command (77 16 /d0 16 ) by writing of command code 77 16 at the 1st bus cycle and writing of verify command code d0 16 and the block s maximum address (note that address a 0 = 0 .) at the subsequent 2nd bus cycle, 0 (the locked state) is written into the lock bit of the specified block. figure 124 shows an example of the lock bit programming flowchart. the status of the lock bit can be read out by the read lock bit status command. the completion of the lock bit programming operation, as well as of the page programming operation, is verified by a read of the status register or a read of the flash memory control register. for details of the lock bit s function and the method of reset, refer to the section on the data protect function. read lock bit status command (71 16 ) by writing of command code 71 16 at the 1st bus cycle and writing of the block s maximum address (note that address a 0 = 0 .) at the subsequent 2nd bus cycle, the status of the lock bit of the specified block is output to the data bus (d 6 ). figure 125 shows an example of the read lock bit programming flowchart. data protect function (block lock) each block is implemented with a nonvolatile lock bit to protect the block from erasing/programming (block lock). a 0 (the locked state) can be written to a lock bit using the lock bit programming command, and the lock bit of each block can be read out by using the read lock bit status command. whether a block lock is valid or invalid is determined by the status of the lock bit and the lock bit invalidity select bit of the flash memory control register. (1) when the lock bit invalidity select bit = 0 , a lock bit determines whether to lock or unlock the corresponding block. a block with its lock bit = 0 is locked and inhibited from erasing and pro- gramming. on the other hand, a block with its lock bit = 1 re- mains unlocked and allows to be erased/programmed. (2) when the lock bit invalidity select bit = 1 , all the blocks are un- locked and allows to be erased/programmed regardless of the values of their lock bits. in this case, a lock bit with a value 0 (the locked state) is set to 1 (the unlocked state) after completion of the erase operation, and the locked state by the lock bit is terminated. to perform erase or programming, be sure to do one of the following. by executing the read lock bit status command, verify that the lock of the target block is invalid. set the lock bit invalidity select bit to 1 to invalidate the lock. when the block erase or programming is performed with the lock valid, the erase status bit (sr.5) and programming status bit (sr.4) are set to 1 (terminated by error). status register the status register is used to indicate what the status of the write state machine (wsm) operation is and whether the programming/ erase operation has been completed normally or terminated by an error. by writing the read status register command (70 16 ), the con- tents of the status register can be read out; by writing the clear sta- tus register command (50 16 ), the contents of the status register can be cleared. table 27 lists the definition of each bit of the status register. the status register outputs 80 16 after reset is removed. the status of each bit is described below.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 128 busy terminated normally. terminated normally. terminated normally. ready terminated by error. terminated by error. terminated by error. table 27. bit definition of status register sr.7 (d 7 ) sr.6 (d 6 ) sr.5 (d 5 ) sr.4 (d 4 ) sr.3 (d 3 ) sr.2 (d 2 ) sr.1 (d 1 ) sr.0 (d 0 ) write state machine (wsm) status reserved erase status programming status block status after programming reserved reserved reserved symbol status definition 1 0 write state machine (wsm) status bit (sr.7) this bit reports the operation status of the wsm. this bit is set to 1 (ready) after the system power is turned on or after reset is re- moved. during the automatic programming or erase operation, this bit is cleared to 0 (busy), however, set to 1 upon completion of them. erase status bit (sr.5) this bit reports the status of the automatic erase operation. this bit is set to 1 if an erase error occurs and returns to 0 if one of the following conditions is satisfied: the system power is turned on. reset is removed. the clear status register command (50 16 ) is executed. programming status bit (sr.4) this bit reports the status of the automatic programming operation. this bit is set to 1 if a programming error occurs and returns to 0 if one of the following conditions is satisfied: the system power is turned on. reset is removed. the clear status register command (50 16 ) is executed. block status after programming bit (sr.3) this bit is set to 1 , upon completion of the page programming op- eration, if the excessive programming (note) occurs. that is, the sta- tus register becomes 80 16 when the programming operation is terminated normally, 90 16 when the programming operation is failed, and 88 16 when the excessive programming occurs. under the condition that any of sr.5, sr.4 and sr.3 = 1 , none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. to execute these commands, in advance, execute the clear status register command (50 16 ) to clear the status register. both of sr.4 and sr.5 are set to 1 under the following conditions (command sequence error): (1) when data other than d0 16 and ff 16 is written to the data in the 2nd bus cycle of the lock bit programming command (77 16 / d0 16 ) (2) when data other than d0 16 and ff 16 is written to the data in the 2nd bus cycle of the block erase command (20 16 /d0 16 ) (3) when data other than d0 16 and ff 16 is written to the data in the 2nd bus cycle of the erase all unlocked block command (a7 16 /d0 16 ) note that, writing of ff 16 forces the microcomputer into the read array mode. simultaneously with this, the command written in the 1st bus cycle will be canceled. note: the excessive programming means the status that memory cells are too depleted, so data cannot be read out correctly. full status check the full status check reports the results of the erase or programming operation. figure 126 shows the full status check flowchart and actions to be taken if an error has occurred.
129 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers fig.126 full status check flowchart and actions to be taken if an error has ocurred status register read sr.4 = 1 no command sequence error yes sr.5 = 0? yes block erase error no sr.4 = 0? yes programming error (page, lock bit) no sr.3 = 0? yes programming error (block) no end (block erase, programming) and sr.5 = 1 ? execute the clear status register command (50 16 ) to clear the status register. after verifying the command to be correctly input, start the operation again. examine whether a lock is active or not by executing the read lock bit status command (71 16 ). after removing the lock, perform block erase again. if the same error still occurs, this page cannot be used. examine whether a lock is active or not by executing the read lock bit status command (71 16 ). after removing the lock, perform programming again. if the same error still occurs, this page cannot be used. after erasing the block where an error has occured, perform programming again. if the same error still occurs, this block cannot be used. note: under the condition that any of sr.5, sr.4 and sr.3 = 1 , none of the page programming, block erase, erase all unlocked block, and lock bit programming commands can be accepted. to execute these commands, in advance, execute the clear status register command (50 16 ). ac electrical characteristics (v cc = 5 v ?0.5 v, ta = 0 to 60 c? f(x in ) = 20 mhz (note)) the limits of parameters other than the above are same as those in the microcomputer mode. note: f(x in ) indicates the system clock (x in ) frequency. symbol parameter limits unit i cc1 i cc2 i cc3 i cc4 min. typ. max. v cc power source current (at read) v cc power source current (at write) v cc power source current (at programming) v cc power source current (at erasing) 30 48 48 54 54 dc electrical characteristics (v cc = 5 v ?0.5 v, ta = 0 to 60 c? f(x in ) = 20 mhz (note)) limits of v ih , v il , v oh , v ol , i ih , and i il for each pin are the same as those in the microcomputer mode. note: f(x in ) indicates the system clcok (x in ) frequency. ma ma ma ma parameter page programming time block erase time erase all unlocked block time lock bit programming time limits unit min. typ. max. 8 50 50 n 8 120 600 600 n 120 ms ms ms ms n = number of blocks to be erased
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 130 power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage high-level input voltage high-level input voltag low-level input voltage low-level input voltage low-level input voltage high-level peak output current high-level average output current low-level peak output current low-level average output current external clock input frequency p0 0 ?0 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 1 ?9 6 , p10 1 ?10 7 , p11 1 ?11 7 , p12 0 ?12 2 , x in , reset, byte, md0, md1, nmi p1 0 ?1 7 , p2 0 ?2 7 (in single-chip mode) p1 0 ?1 7 , p2 0 ?2 7 (in memory expansion and microprocessor modes) p0 0 ?0 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 1 ?9 6 , p10 1 ?10 7 , p11 1 ?11 7 , p12 0 ?12 2 , x in , reset, byte, md0, md1, nmi p1 0 ?1 7 , p2 0 ?2 7 (in single-chip mode) p1 0 ?1 7 , p2 0 ?2 7 (in memory expansion and microprocessor modes) p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 0 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 p12 2 p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 0 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 p12 2 p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 0 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 p12 2 p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 0 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 p12 2 v cc av cc v ss av ss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (avg) f(x in ) parameter power source voltage analog power source voltage input voltage d 0 ? 7 , d 8 /p2 0 ? 15 /p2 7 , p3 0 , p3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 1 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 ?12 2 , v ref , x in , reset, byte, md0, md1, nmi output voltage d 0 ? 7 , d 8 /p2 0 ? 15 /p2 7 , p3 0 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 1 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 ?12 2 , x out power dissipation operating ambient temperature storage temerature symbol v cc av cc v i v o p d t opr t stg absolute maximum ratings recommended operating conditions (vcc = 5 v, ta = ?0 to 85 ?, unless otherwise noted) notes 1: average output current is the average value of an interval of 100 ms. 2: the sum of i ol(peak) for ports p0?2, p8, p10, and p11 must be 80 ma or less, the sum of i oh(peak) for ports p0?2, p8, p10, and p11 must be 80 ma or less, the sum of i ol(peak) for ports p3?7, p9, and p12 must be 80 ma or less, the sum of i oh(peak) for ports p3?7, p9, and p12 must be 80 ma or less. unit v v v v mw ? ? ratings ?.3 to 6.5 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to v cc +0.3 300 ?0 to 85 ?0 to 150 unit v v v v v v v v v v ma ma ma ma mhz 4.5 0.8v cc 0.8v cc 0.5v cc 0 0 0 5.5 v cc v cc v cc 0.2v cc 0.2v cc 0.16v cc ?0 ? 10 5 20 parameter symbol max. typ. min. limits 5 v cc 0 0
131 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers unit v v v v v v v v v a a v ma a f(x in ) = 20 mhz. ta = 25 c when clcock is stopped. ta = 80 c when clcock is stopped. test conditions i oh = ?0 ma i oh = ?00 a i oh = ?0 ma i oh = ?00 a i ol = 10 ma i ol = 2 ma i ol = 10 ma i ol = 2 ma v i = 5.0 v v i = 0 v when clock is stoped. parameter high-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 0 ?9 3 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 ?12 2 high-level output voltage p0 0 ?0 7, p1 0 ?1 7 , p2 0 ?2 7 , p4 0 , p4 4 , p9 0 ?9 3 , p10 0 ?10 7 , p11 0 ?11 7 high-level output voltage p3 1 ?3 3 , p9 4 ?9 6 low-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 0 ?9 3 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 ?12 2 low-level output voltage p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p4 0 , p4 4 , p9 0 ?9 3 , p10 0 ?10 7 , p11 0 ?11 7 low-level output voltage p3 1 ?3 3 , p9 4 ?9 6 hysteresis ta0 in ?a4 in , tb0 in ?b2 in , int 0 ?nt 4 , dmareq 0 ?mareq 3 , ad trg , cts 0 , clk 0 , clk 1 , rxd 0 , rxd 1 , nmi, rdy, hold hysteresis reset hysteresis x in high-level input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 1 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 ?12 2 , x in , reset, byte, md0, md1, nmi low-level input current p0 0 ?0 7 , p1 0 ?1 7 , p2 0 ?2 7 , p3 0 ?3 3 , p4 0 ?4 4 , p5 0 ?5 7 , p6 0 ?6 6 , p7 0 ?7 3 , p8 0 ?8 6 , p9 1 ?9 6 , p10 0 ?10 7 , p11 0 ?11 7 , p12 0 ?12 2 , x in , reset, byte, md0, md1, nmi ram hold voltage power source current symbol v oh v oh v oh v ol v ol v ol v t+ vt v t+ vt v t+ vt i ih i il v ram i cc dc electrical characteristics (vcc = 5 v, vss = 0 v, ta = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted) min. 3 4.7 3.4 4.8 0.4 0.5 0.1 2 limits typ. 25 max. 2 0.45 1.6 0.4 1 1.5 0.3 5 ? 50 1 20 at reset in micro- processor mode, output-only pins are open, and the other pins are con- nected to vss.
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 132 resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(x in ) 20 mhz max. a-d converter characteristics (v cc = av cc = 5 v ?0.5 v, v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode 10-bit resolution mode 8-bit resolution mode 5 5.9 2.45 (note) 2.7 0 10 ?3 ?2 v cc v ref bits lsb lsb k ? s v v note: this is applied when a-d conversion freguency ( ad ) = f 1( ) .
133 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers t c(ta) t w(tah) t w(tal) f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz peripheral device input/output timing (v cc = 5 v ?0.5 v, v cc = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz unless otherwise noted) ? for limits depending on f(x in ), their calculation formulas are shown below. also, the values at f(x in ) = 20 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(x in ) (400) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) (800) (400) (400) t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of a count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(x in ) 20 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(x in ) 20 mhz
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 134 t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) tai in input cycle time taj in input setup time taj out input setup time tai in input tai out input (up-down input) tai out input (up-down input) tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il = 1.0 v, v ih = 4.0 v ?up-down and count input in event counter mode ?two-phase pulse input in event counter mode ?gating input in timer mode ?count input in event counter mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tc (ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(taj in -taj out ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj out -taj in ) t c(ta) t su(up-t in )
135 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz f(x in ) 20 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(x in ) 20 mhz. limits symbol parameter min. max. unit 16 10 9 f(x in ) 8 10 9 f(x in ) 8 10 9 f(x in ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(x in ) 20 mhz. t c(ad) t w(adl) symbol ad trg input cycle time (minimum allowable trigger) ad trg input low-level pulse width parameter min. 1000 125 limits max. ns ns unit a-d trigger input
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 136 t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit t w(inh) t w(inl) symbol int i input/nmi input high-level pulse width int i input/nmi input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input, nmi input t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t h(c - q) t d(c - q) t su(d - c) t w(inh) t w(inl) t h(c - d) t c(ad) t w(adl) tbi in input inti input, ad trg input clki input txdi output rxdi input nmi input test conditions vcc = 5 v 20 to 85 input timing voltage : v il = 1.0 v, v ih = 4.0 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf
137 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers t d( 1-hldal) t d(rdh-hldal) t d(bxwh-hldal) t pxz(hldal-rdz) t pxz(hldal-bxwz) t pxz(hldal-csiz) t pxz(hldal-alez) t pxz(hldal-az) t pzx(hldal-rdz) t pzx(hldal-bxwz) t pzx(hldal-csiz) t pzx(hldal-alez) t pzx(hldal-az) ready, hold timing timing requirements (v cc = 5 v ?0.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted) t su(rdy- 1) t su(hold- 1) t h( 1-rdy) t h( 1-hold) symbol rdy input setup time hold input setup time rdy input hold time hold input hold time parameter limits min. 40 40 0 0 max. ns ns ns ns unit switching characteristics (v cc = 5 v ?0.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted) symbol hlda output delay time hlda low-level output delay time after read hlda low-level output delay time after write floating start delay time floating start delay time floating start delay time floating start delay time floating start delay time floating release delay time floating release delay time floating release delay time floating release delay time floating release delay time parameter min. tc ?5 (note) tc ?5 (note) ?5 ?5 ?5 ?5 ?5 0 0 0 0 0 limits max. 20 10 10 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns unit note: tc = 1/f(x in ).
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 138 v cc = 5 v 20 to 85 rdy input, hold input : v il = 1.0 v, v ih = 4.0 v hlda output : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf a 23 output t d (rdh-hldal) t d (bxwh-hldal) t pxz (hldal-alez) ale
139 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers when ale expansion wait is selected w = 0 (0 wait) w = 1 (1 wait) w = 2 (2 wait) tc = 1/f(x in ). external bus timing for limits depending on f(x in ), their calculation formulas are shown below. external clock input test conditions vcc = 5 v 20 to 85 input timing voltage : v il = 1.0 v, v ih = 4.0 v (t w(h) , t w(l) , t r , t f ) output timing voltage : 2.5 v ( t c , t w(half) ) t r t f t w(l) t w(h) t w(half) f(x in ) t c timing requirements (v cc = 5 v ?0.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted) ns ns ns ns ns ns ns ns ns ns ns ns ns 50 0.45tc 0.5tc-8 0.5tc-8 15 0 0 0.55tc 8 8 (2 + w)tc-45 (1.5 + w)tc-35 (1 + w)tc-30 (1 + w)tc-35 50 0.45 tc 0.5tc-8 0.5tc-8 15 0 0 limits external clock input cycle time external clock input pulse width with half input-volage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time address access time chip select access time read access time read data setup time data input hold time after read address access time at burst rom access data hold time after address at burst rom access parameter max. min. t c t w(half) t w(h) t w(l) t r t f t a(a-d) t a(csil-d) t a(rdl-d) t su(d-rdl) t h(rdh-d) t a(ba-d) t h(ba-d) unit symbol max. min. when 0/1/2 wait is selected 0.55tc 8 8 4tc-45 3.5tc?5 2tc-30 2tc-35
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 140 switching characteristics (v cc = 5 v ?0.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted) 15 10 15 10 0.5tc+10 read low-level output delay time read high-level output delay time write low-level output delay time write high-level output delay time ale pulse width ale completion delay time after address stabilization read output pulse width read output high-level width (note 1) write disable valid time after read (note 2) address valid time before read address hold time after read (note 3) ale completion delay time after read start read disable valid time after ale completion chip select valid time before read chip select output valid time before read completion chip select hold time after read next write cycle data output delay time after read (note 2) write output pulse width write output high-level width (note 1) read disable valid time after write (note 2) address valid time before write address hold time after write (note 3) ale completion delay time after write start write disable valid time after ale completion chip select valid time before write chip select output valid time before write completion chip select hold time after write data output valid time before write completion data hold time after write floating start delay time after write ?0 ?0 ?0 ?0 tc-20 1.5tc-30 2tc-15 2tc-15 tc-15 2tc-30 8 0.5tc-20 1.5tc-20 3.5tc-20 0.5tc-20 tc-15 2tc-15 2tc-15 tc-15 2tc-30 8 0.5tc-20 1.5tc-20 3.5tc-20 0.5tc-20 2tc-20 0.5tc-10 15 10 15 10 20 20 0.5tc+10 ?0 ?0 ?0 ?0 0.5tc-20 tc-30 (1+w)tc-15 tc-15 tc-15 tc-30 8 0.5tc-20 (1.5 + w)tc-20 0.5tc-20 tc-15 (1 + w)tc-15 tc-15 tc-15 tc-30 8 0.5tc-20 (1.5 + w)tc-20 0.5tc-20 (1 + w)tc-20 0.5tc-10 t d( 1-rdl) t d( 1-rdh) t d( 1-bxwl) t d( 1-bxwh) t w(aleh) t d(a-alel) t w(rdl) t w(rdh) t d(rdh-bxwh) t d(a-rdh) t h(rdh-a) t d(rdh-alel) t d(alel-rdh) t d(csil-rdh) t d(csil-rdl) t h(rdh-csil) t d(rdh-d) t w(bxwl) t w(bxwh) t d(bxwh-rdh) t d(a-bxwh) t h(bxwh-a) t d(bxwh-alel) t d(alel-bxwh) t d(csil-bxwh) t d(csil-bxwl) t h(bxwh-csil) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter max. min. unit symbol limits max. min. when 0/1/2 wait is selected when ale expansion wait is selected notes 1: when the bus cycle just before this parameter is for the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 2: when accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). 3: when accessing the area where the recovery cycle insertion is selected, this parameter is extended by tc (ns). however, except for the case at instruction prefetch.
141 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers bus cycle cs i a 0 ? 23 d 0 ? 7 , d 8 ? 15 t h(rdh-d) t h(rdh-a) t h(rdh-csil) rd t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t d(a-rdh) t d(csil-rdl) t d(csil-rdh) t su(d-rdl) ale t w(aleh) t d(rdh-alel) t d(rdh-bxwh) 1 t c f(x in ) cs i t h(bxwh-a) t h(bxwh-csil) rd t d(a-bxwh) t d(csil-bxwl) t d(csil-bxwh) ale t d(bxwh-rdh) t w(bxwl) t d(bxwh-alel) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) normal access : 0/1/2 wait t d(a-alel) t d(a-alel) t w(rdh) t d(rdh-d) t w(bxwh) blw bhw blw bhw t d( 1-rdl) t d( 1-rdh) t w(aleh) 1 bus cycle t d( 1-bxwl) t d( 1-bxwh) a 0 ? 23 d 0 ? 7 , d 8 ? 15 test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il =0.8 v, v ih =2.5 v ?output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) ?output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 142 bus cycle cs i rd ale blw bhw f(x in ) cs i rd ale blw bhw t d(csil-bxwl) t d(csil-rdl) t d(a-alel) t h(rdh-d) t h(rdh-a) t h(rdh-csil) t w(rdl) t a(csil-d) t a(rdl-d) t a(a-d) t d(a-rdh) t d(csil-rdh) t su(d-rdl) t w(aleh) t d(rdh-bxwh) t c t h(bxwh-a) t h(bxwh-csil) t d(a-bxwh) t d(csil-bxwh) t w(aleh) t d(bxwh-rdh) t w(bxwl) t d(d-bxwl) t h(bxwh-d) t pxz(bxwh-dz) t d(a-alel) t w(rdh) t d(rdh-d) t w(bxwh) t d(alel-rdh) t d(alel-bxwh) 1 normal access : ale expansion wait t d( 1-rdl) t d( 1-rdh) bus cycle 1 t d( 1-bxwl) t d( 1-bxwh) a 0 a 23 d 0 d 7 , d 8 d 15 a 0 a 23 d 0 d 7 , d 8 d 15 test conditions v cc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il =0.8 v, v ih =2.5 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
143 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers burst rom access : 0/1/2 wait at instruction prefetch t h(ba-d) t d(rdh-bxwh) blw bhw rd t a(rdl-d) t d(a-rdh) cs i t h(rdh-a) t a(csil-d) t a(a-d) t a(ba-d) t h(ba-d) t h(ba-d) t h(rdh-d) t a(ba-d) t a(ba-d) t h(rdh-csil) t d(csil-rdh) t d(a-alel) t w(aleh) ale t d(rdh-alel) t w(rdh) a 0 a 23 d 0 d 7 , d 8 d 15 test conditions v cc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il =0.8 v, v ih =2.5 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (cs i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for cs i )
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 144 t w(rash) t d(cash-rash) t h(rasl-cash) t h(casl-rasl) t w(casl) t d(ra-rash) t h(rasl-ra) t d(ca-cash) t h(cash-ca) t d(wh-cash) t d(wl-cash) t h(casl-wl) t d(d-cash) t h(casl-d) t pxz(cash-d) t pxz(wh-d) t a(rasl-d) t a(casl-d) t h(cash-d) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.5tc-20 1.5tc-20 1.5tc-20 tc-15 tc-15 0.5tc-25 tc-40 0.5tc-20 0 3tc-15 tc-15 tc-15 tc-20 1.5tc-15 0.5tc+10 dram access timing requirements (v cc = 5 v 0.5 v, v ss = 0 v, t a = 0 to 70 c, f(x in ) = 20 mhz, unless otherwise noted) limits ras access time cas access time data input hold time after cas parameter max. min. unit symbol ns ns ns 0 2.5tc-35 tc-30 limits ras high-level pulse width cas high-level valid time before ras cas high-level hold time after ras s low level ras hold time after cas s low level cas low-level pulse width row address valid time before ras row address hold time after ras s low level column address valid time before cas column address hold time after cas s high level w high-level valid time before cas w low-level valid time before cas w hold time after cas s low level data output valid time before cas data output hold time after cas s low level floating start delay time after cas floating start delay time after write parameter max. min. unit symbol switching characteristics (v cc = 5 v 0.5 v, v ss = 0 v, t a = 0 to 70 c, f(x in ) = 20 mhz, unless otherwise noted) 0.5tc+10
145 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers t h(rasl-ra) dram access 1 ras i lcas,ucas (cas) w (wrl,wrh) column t h(casl-rasl) t a(casl-d) t h(cash-d) t w(rash) w (wrl,wrh) ras i t d(ra-rash) t h(cash-ca) t w(casl) t d(wh-cash) t a(rasl-d) lcas,ucas (cas) t h(rasl-ra) t d(ca-cash) t d(cash-rash) row address column address row address t h(rasl-cash) t h(casl-d) t w(rash) t d(ra-rash) t h(cash-ca) t w(casl) t d(d-cash) t d(wl-cash) t h(casl-wl) t d(ca-cash) t d(cash-rash) t pxz(cash-d) t h(casl-rasl) t h(rasl-cash) row address column address row address a 0 a 23 d 0 d 7 , d 8 d 15 a 0 a 23 d 0 d 7 , d 8 d 15 test conditions v cc = 5 v 0.5 v, ta = 0 to 70 c input timing voltage : v il =0.8 v, v ih =2.5 v output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (ras i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for ras i ) address column address
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 146 t w(ras cbr l) t w(cas cbr l) t d(cas cbr l-ras cbr h) t d(ras cbr l-cas cbr l) t d(cas slfr l-ras slfr h) t h(ras slfr h-cas slfr l) 2tc?5 2tc?5 tc?5 tc?5 tc?5 ?5 ns ns ns ns ns ns dram refresh switching characteristics (v cc = 5 v ?0.5 v, v ss = 0 v, t a = 0 to 70 ?, f(x in ) = 20 mhz, unless otherwise noted) limits ras low-level pulse width (at cas before ras refresh) cas low-level pulse width (at cas before ras refresh) ras high-level valid time after cass low level start (at cas before ras refresh) cas low-level valid time after rass low level start (at cas before ras refresh) ras high-level valid time after cass low level start (at selfrefresh) cas low-level hold time after rass high level (at selfrefresh) parameter max. min. unit symbol 15
147 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers t d(cas cbr l-ras cbr h) dram refresh : cas before ras refresh 1 t d(ras cbr l-cas cbr l) t w(ras cbr l) w (wrl,wrh) ras i t w(cas cbr l) lcas,ucas (cas) refresh cycle t d(cas slfr l-ras slfr h) t h(ras slfr h-cas slfr l) w (wrl,wrh) ras i lcas,ucas (cas) refresh cycle dram refresh : selfrefresh 1 test conditions v cc = 5 v 0.5 v, ta = 0 to 70 c output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =15 pf (ras i ) output timing voltage: v ol =0.8 v, v oh =2.0 v, c l =50 pf (except for ras i )
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 148 t w(tcl) t d(rdh-tcl) t d(bxwh-tcl) t d(tcl-dmaackl) unit tc input setup time tc input pulse width dmareq i input setup time dmareq i input pulse width dma transfer timing timing requirements (v cc = 5 v 0.5 v, v ss = 0 v, t a = 20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) max. parameter symbol unit min. limits t su(tc in l- 1) t w(tc in l) t su(drql- 1) t w(drql) ns ns ns ns 40 tc + 20 40 tc tc output pulse width tc output start delay time after read tc output start delay time after write dmaack low-level output valid time after tc output start switching characteristics (v cc = 5 v 0.5 v, v ss = 0 v, t a = 20 to 85 c, f(x in ) = 20 mhz, unless otherwise noted) max. parameter symbol min. limits ns ns ns ns tc-20 tc-15 tc-15 2.5tc-20 tc 50 pf 3 k ? test circuit for tc output
149 M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers tc input 1 tc input t su(tc in l- 1) dmareq i input 1 dmareq i input t su(drql- 1) t w(drql) t w(tc in l) test conditions vcc = 5 v 0.5 v, ta = 20 to 85 c input timing voltage : v il = 1.0 v, v ih = 4.0 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf cs i rd blw bhw ale t w(tcl) tc dmaack i t d(rdh-tcl) t d(bxwh-tcl) t d(tcl-dmaackl) final transfer cycle terminate processing (next bus cycle) transfer terminate timing a 0 a 23 d 0 d 7 , d 8 d 15 test conditions v cc = 5 v 0.5 v, ta = 20 to 85 c output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers 150 qfp100-p-1420-0.65 1.58 weight(g) jedec code eiaj package code lead material alloy 42 100p6s-a plastic 100pin 14 20mm body qfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.35 i 2 1.3 m d 14.6 m e 20.6 10 0 0.1 1.4 0.8 0.6 0.4 23.1 22.8 22.5 17.1 16.8 16.5 0.65 20.2 20.0 19.8 14.2 14.0 13.8 0.2 0.15 0.13 0.4 0.3 0.25 2.8 0 3.05 e e e e c h e 1 30 31 81 50 80 51 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100 package outline lqfp100-p-1414-0.50 weight(g) jedec code eiaj package code lead material cu alloy 100p6q-a plastic 100pin 14 14mm body lqfp 0.1 0.2 symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.225 i 2 1.0 m d 14.4 m e 14.4 10 0 0.1 1.0 0.7 0.5 0.3 16.2 16.0 15.8 16.2 16.0 15.8 0.5 14.1 14.0 13.9 14.1 14.0 13.9 0.175 0.125 0.105 0.28 0.18 0.13 1.4 0 1.7 e e e e c h e 1 76 75 51 50 26 25 h d d m d m e a f b a 1 a 2 l 1 l y b 2 i 2 recommended mount pad detail f 100
M37920FCCGP, m37920fcchp m37920fgcgp, m37920fgchp preliminar y notice: this is not a final specification. some parametric limits are subject to change. single-chip 16-bit cmos microcomputer flash memory version mitsubishi microcomputers ? 2000 mitsubishi electric corp. new publication, effective jun., 2000. specifications subject to change without notice. notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product be st suited to the customer s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents info rmation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommen ded that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibilit y for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used unde r circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these ma terials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licens e from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detail s on these materials or the products contained therein. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
rev. rev. no. date 1.0 first edition 990602 2.0 refer to corrections and supplementary explanation for ?37920fxcgp/hp datasheet (rev.a) . 000628 revision history M37920FCCGP/hp, m37920fgcgp/hp datasheet (1/1) revision description
corrections and supplement ar y explanation for m37920fxc dat asheet (rev. a) no.1 page erro r correction (1/6) page 4 , bl o c k diagra m no t e : note: ram 2048 bytes 4096 bytes 6144 bytes m37920f8 cgp ,m37920f8 c h p M37920FCCGP,m37920fcchp m37920fgcgp,m37920fgchp flash memory 60 kbytes 120 kbytes 248 kbytes note: all pages, h eade r page 3 , pin confi gur at io n page 121 , fig . 119 , pi n conne ct i on o f m3792 0f xc hp i n f l ash m emor y m37920f8 c g p , m37920f 8 c hp , m37920f c cg p, m37920fc chp , m37920fgcgp, m 3 7920fgchp m37920f c cg p, m37920f cc h p, m37920f g c g p , m37920fgch p page 1 disti n cti ve feat u res ; m emory [m 379 20f8 cg p , m37920f8 c hp] fl ash memor y (user r o m ar ea ) .. .... .... ... .... .... .60 kbytes ra m ... .... .... .... ... .... .... .... ... .... .... .... .... ... .... .... .... .2048 bytes (deleted) m37920f8 c hp m37920fc chp m37920fgch p m37920f cc hp m37920fgchp (type) (type) page 5, chip-selec t wait control c hip select area 4 ( c s 0 c s 3 ). a wait number and bus width can be set for each chip select area. c hip select area 4 ( c s 0 c s 3 ). a bus cycle type and bus width can be set for each chip select area. page 2 , pin configuratio n page 120 , fig. 118 , pin connection o f m37920fxcgp in flash memor y m37920f8 c g p m37920fc cgp m37920fgcgp m37920f ccg p m37920fgcgp (type) (type) ram 4096 bytes 6144 bytes m37920f ccgp ,m37920f cc h p m37920fgcgp,m37920fgchp flash memory 120 kbytes 248 kbytes pa ge 5, paramete r oper a t i ng temperat ure r a nge operating ambient temperature range page 5 , no t e : note: ram 2048 bytes 4096 bytes 6144 bytes m37920f8 c g p ,m37920f8 c h p m37920fc cgp ,m3792 0f c chp m37920fgcgp, m 37920fg c hp flash memory (user rom area) 60 kbytes 120 kbytes 248 kbytes m37920f8 c g p ,m37920f8 c h p m37920fc cgp ,m3792 0f c chp m37920fgcgp, m 37920fg c hp note: ram 4096 bytes m37920f ccgp ,m37920f cc h p flash memory (user rom area) 120 kbytes m37920f ccgp ,m37920f cc h p m37920f gcgp ,m37920f gc h p 248 kbytes m37920f gcgp ,m37920f gc h p 6144 bytes pa ge 6 , n o t e user r o m area m37920f8c g p, m 37920f8ch p 4 bl ocks m37920fc cgp , m37920fcc hp 5 bl ocks m37920fgcgp, m37920 f gch p 7 bl ocks note: user r o m area m37920fc cgp , m37920fcc hp 5 bl ocks m37920fgcgp, m37920 f gch p 7 bl ocks note: page 1 descripti on; li nes 1 1, 12 these microcom p ut ers includ e the 4-channel dma contr o ller a nd the dr am con t rolle r with enhanced fast page mode. these microcomputers include the 4-channel dma controller and the dram controller. page 1 disti n cti ve feat u res ; i nterrupts inter rupts ... .... .... ... .... .... 6 external sources, 17 internal sources, 7 leve ls interrupts ......................6 external sources, 20 internal sources, 7 levels page 5, dram controlle r 1 channel supports fast page access mode. incorparates 8-bit refresh timer. supports cas before ras refresh method 1 channel incorparates 8-bit refresh timer. supports cas before ras refresh method page 5, interrupt s 6 external types, 17 internal types. each interrupt 6 external types, 20 internal types. each interrupt
corrections and supplement ar y explanation for m37920fxc dat asheet (rev. a) no.2 page erro r correction (2/6) page 9, fig. 1 fig. 2. memory map of m37920f ccg p and m37920fcchp (single-chip mode) fig. 1. memory map of m37920f ccg p and m37920fcchp (single-chip mode) mem ory m ap of m 379 20f8 cg p and m37920f 8 c hp (singl e- chi p m ode) (deleted) fi g. 3. m emory map of m37920f g c g p and m37920fgch p ( s ingle-chip mode) fig. 2. memory map of m37920f gcg p and m37920fgchp (single-chip mode) page 10, fig. 2 page 11, fig. 4; addres s 00 16 , 01 1 6 000000 16 000001 16 000000 16 000001 16 reserved area (note) reserved area ( note ) b31 b0 db data bu ff er b31 b0 d q data bu ff er page 18, fig. 8 data buff e r temporarity stores data which has been , and external areas by the biu or which is to be writeen to internal memory, . temporarily stores data which has been , and external areas by the biu; or temporarily stores data which is to be written to internal memory, . page 18, table 1 instructio n queue buffe r temporarity stores an instruction which . temporarily stores an instruction which . (this contents is published f or one page) ale is an addr ess latch enabl e si gnal. no t e: the chip select wait contr ol ler, by the chip select wait contr o ller. (deleted) t he f i nal page of s election of p r ocessor m ode p rocessor mode register 1 10 2 43 5 6 7 recovery cycle insert select bit h o ld input, hlda output select bit 0: (p4 0 and p4 4 function as ) 1: 0 0 ale output select bit rdy input select bit direct page register switch bit page 28, fig. 1 2 p rocessor mode register 1 10 2 43 5 6 7 recovery cycle insert select bit (notes 2 and 3) h o ld input, hlda output select bit (notes 2 to 4) 0: (p4 3 and p4 4 function as ) 1: 0 0 ale output select bit (notes 2 and 3) rdy input select bit (notes 2 to 4) direct page register switch bit (note 1) internal r o m access wait bit internal r o m access wait bit (note 5)
corrections and supplement ar y explanation for m37920fxc dat asheet (rev. a) no.3 page erro r correction (3/6) page 3 5 , fig. 17, area csx st ar t address regi st er (x = 0 to 3) area c s x start address r eg ister (x = 1, 2) 0 1 0 1 when mode 0 is area c s x start address r eg ister (x = 1, 2) when mode 0 is ? at read. 2 2 area c s x start address r eg ister (x = 0, 3) 0 1 0 1 these bi t s determ i ne area c s 3 start address r e gister (x = 0, 3) ? at read. 2 2 these bits determine page 61, interrup t request a t completion o f reception ?control register 0 (uart receive interrupt mode select bit) ?control register 0 (uartk receive interrupt mode select bit) page 51, left column, lines 14, 17, 2 2 ? timer a i st a r t bit ? coun t star t bit (line 9) (line 9) ?uarti receive interrupt mode select bit (lines 18, 20) ?uartk receive interrupt mode select bit (lines 18, 20) ladder n et w or k resistor ladder network page 67, fig. 6 3 page 68, v r e f c o n n e c t i o n the ladder network or not the r esi st o r ladder network or not the ladder net w or k can be cut off by disconnecting ladd er network the r esi st or ladder net w or k can be cut o f f by disconnect- ing resistor la dder network (lines 2, 3) (lines 2, 3) (li ne 7) (line 7) notes 1: after reset, this bit? contents can be switched only once. during the software execution, be sure not to switch this bit? contents. 2: in the single-chip mode, these bits?functions are disabled regardless of these bits?contents . 3: while v ss level voltage is applied to pin md0, each of these bits is ? at reset. while v cc level voltage is applied to pin md0, on the other hand, each of these bits is ? at reset. 4: in the memory expansion or microprocessor mode, if this bit? contents is switched from ? to 0? this bit will be cleared to ?. after this clearance, this bit cannot return to ?. if it is necessary to set this bit to 1? be sure to reset the microcomputer. 5: in the microprocessor mode, this bit is invalid. when the internal flash memory is reprogram- med in the cpu reprogramming mode, be sure to clear this bit to ?. page 28, fig. 1 2
corrections and supplement ar y explanation for m37920fxc dat asheet (rev. a) no.4 page erro r correction (4/6) page 92, left column, lines 28, 29 sel ect ed. bi t 2 of the dr am con t rol register is the access m ode select bit. whe n bi t 2 is ? , nor mal access is selected, when it is ? , f a st page access is selected. when t he fast page access is selected, t h e access suppo r ting the f ast page access mode o f dr am i s perfor med, if the range whi ch can be speci f i ed with t he same r ow ad dr ess is continuousl y a ccessed. if the row address cha nges during the f ast page access, the new row addresses will be output ag ain aft er t ha t fast pag e acce ss i s term i nat ed . then , the f ast page access wil l r estart . fi gur e 93 shows an operating waveform example of the dr am control signal s and add r ess bus in the f ast page access. bi t 4 of the dr am ? sel ect ed. bi t 4 of the dr am ? dr am control r eg ister 0 1 access mode select bit 0: nor mal access 1: fast pa ge a ccess 2 page 95, fig. 90 dr am control r eg ister 0 1 fi x this bit to ?? 2 00 0 operating waveform example of dram control signals and address bus in fast page access (deleted) page 117, right column, lines 15 to 1 7 area if the user use s the flash m emory se r ial i/o mode. note that, when the boot rom area i s read area if the user uses the flash memory serial i/o mode. addresses ffb0 16 to ffbf 16 are the reserved area for the serial programmer. therefore, when the user uses the flash memory serial i/o mode, do not program to this area. note that, when the boot rom area is read m37920f8 c g p , m37920f 8 c hp : block configuration of internal flash m emory (deleted) page 11 8 reset; [function] the reset i nput pi n. input h aft e r l is input. the reset input pin. p4 2 ; [function] this is an i/o pin for serial data. this is an i/o pin for serial data. c onnect this pin to v cc via a resistor (about 1 k ? ). thi s i s an i nput pi n for a serial cl ock. c o nnect this pin to v c c via a resistor (about 1 k ? ) . this is an input pin for a serial clock. p4 4 ; [function] nmi; [function] input ?? input ?? or leave this pin open. page 122, boot mod e progr am the u ser rom area. program the user rom area. after reset removal, be sure not to change the status at pins md0 and md1. (li nes 22, 23) (li nes 22, 23) page 122, fig. 120, note 4 4: v alid onl y w hen bit 1 = 1? set b it 3 to 1?( reset) , and then clear to ? . 4: valid only when bit 1 = 1? set bit 3 to 1?(reset), and then clear to ?. this bit 3 must be controlled with the cpu reprogramming mode select bit (bit 1) = ?? page 99, right column, lines 1 to 3 when the wavefor m output sel ect bits are set to ?1?( bit 1 = bit 0 = 1?, rt p1 3 to r tp1 0 , rt p0 3 , and rtp 0 2 become pulse output po r t pins. when the wavefor m output when the waveform output select bits are set to ?1?(bit 1 = bit 0 = 1?, pulse output port pins are divided into two groups; one consists of rtp1 3 to rtp1 0 , rtp0 3 , rtp0 2 and the other consists of rtp0 1 and rtp0 0 . when the waveform output
corrections and supplement ar y explanation for m37920fxc dat asheet (rev. a) no.5 page erro r correction (5/6) page 123, right column, after line 2 4 request occu r rence. request occu r rence. in the c pu reprogr amming m od e, be sure no t to use the st p and wit instr uction s. page 124, fig. 121 the c p u r e pr ogramm i ng mode select bit is set to 1? (wr iting of 0? writing of ?? writing of ? to t h e c pu repr og r amm i ng m ode sele ct bit. (wr iting of 0? writing of ?? page 124, software commands (d 8 ? 1 5 ) is ignored. (li nes 6, 7) (d 8 ? 1 5 ) is ignored. ( e xcept for the write data at the 2nd cycle of a page progr a m ming comm and.) (li nes 6, 7) page 125, page program command , the same way as bit 7 of the status register. reading out the (lines 4 to 7) , the same wayas bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of the status register (sr.7) or the ry/by status bit is set to ??(ready). during the automatic programming operation, writing of commands and access to the flash memory must not be performed. reading out the page 125, block erase command (li nes 20 to 2 3) , the same way as bit 7 of the status register. reading out the (li nes 20 to 2 3) , the same way as bit 7 of the status register. before execution of the next command, be sure to verify that bit 7 of the status register (sr.7) or the ry/by status bit is set to ??(ready). during the automatic erase operation, writing of commands and access to the flash memory must not be performed. reading out the page 127, e r ase al l unlocked b loc k co m mand (lines 9 to 11) is also reported by a read of the status register. when the lock bit (lines 9 to 11) is also reported by a read of the status register. during the automatic erase execution (when the ry/by status bit = 0?), writing of commands and access to the flash memory must not be performed. when the lock bit (lines 4 to 7) page 124, page program command (a f ter line 20) mode is m ai nt a ined. (a f ter line 20) mode is m ai nt a ined. i n continuou s program ming, if t h er e is no progr amming er ror, page program ming comm ands can be executed with the r ead status regi st er mode kept . page 123, left column, lines 15 to 1 9 therefore, a soft w ar e comm a nd co nsists of 8-bit un its must be written only t o an even address; therefor e, any data writt en to an odd addr ess wi ll be inval id. the write stat e therefore, a soft w ar e comm a nd co nsisting of 8 bits must be writt e n to an even address; theref o r e, any com mand written to an odd address will be in valid. since the write data at the 2nd cycle of a program ming comm an d con si- sts o f 16 bits, thi s data must be written to even and odd addresses. the write stat e page 127, d ata p r otec t f unction (blo ck lock) (a f t er li ne 20) lock bit is ter minated. (a f t er li ne 20) lock bit is ter minated. to perfor m er ase or pr ogramm i ng, be sure t o do one of the f ol lowi ng. ?by executing the r ead lock bi t status command, verify that the lock of t he target bl ock i s i nvalid. ?set t he lo ck bi t inva lidity select bit t o ? to invali date the lock. when the block er ase or pr ogramm i ng i s p er form ed wi t h the lock va lid, t he erase stat us bit (sr.5) an d program - ming st a t us bit (sr.4) are set to 1 ( term i nated by error ). (titll e) pag e p r og r am c om mand (41 16 ) (titlle) page programming c ommand (41 16 )
corrections and supplement ar y explanation for m37920fxc dat asheet (rev. a) no.6 page erro r correction (6/6) page 144, swi t ch ing ch ar acteristic s mi n. 0.5tc?0 lim its max. s ymbol t d(c af-ca sh) tc?0 p arameter unit t d(wfl-c ash ) t d(df-cash) t pxz(wh-d) co lumn address vali d time bef ore ca s ( when fast page a ccess on is sel ect ed) w l ow-l evel vali d time bef ore cas (when fast page access o n i s sel ect ed) data output valid time before cas (when fast page access on is selected) fl oat i ng start dela y time after wri t e t pxz(c ash-d ) fl oat i ng start dela y time after ca s 0.5tc?0 0.5t c+10 0.5tc+10 ns ns ns ns ns mi n. lim its max. s ymbol p arameter uni t t pxz(wh-d) floating start delay time after write t pxz(cash-d) floating start delay time after cas 0.5t c+10 0.5t c+10 ns ns page 145, dram access dr am access : f ast page access off (title) dr am access (title) timing of dram access : fast page access off (deleted) page 130, ab solut e max im um ra tings; t opr oper a t i ng temperat ure oper a t i ng a m bie nt tem p er ature

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