IRLI540N preliminary hexfet ? power mosfet pd - 9.1497a s d g v dss = 100v r ds(on) = 0.044 w i d = 23a l logic-level gate drive l advanced process technology l isolated package l high voltage isolation = 2.5kvrms ? l sink to lead creepage dist. = 4.8mm l fully avalanche rated to-220 fullpak 3/16/98 parameter typ. max. units r q jc junction-to-case CCC 2.8 r q ja junction-to-ambient CCC 65 thermal resistance parameter max. units i d @ t c = 25c continuous drain current, v gs @ 10v 23 i d @ t c = 100c continuous drain current, v gs @ 10v 16 a i dm pulsed drain current ?? 120 p d @t c = 25c power dissipation 54 w linear derating factor 0.36 w/c v gs gate-to-source voltage 16 v e as single pulse avalanche energy ?? 310 mj i ar avalanche current ?? 18 a e ar repetitive avalanche energy ? 5.4 mj dv/dt peak diode recovery dv/dt ?? 5.0 v/ns t j operating junction and -55 to + 175 t stg storage temperature range soldering temperature, for 10 seconds 300 (1.6mm from case ) c mounting torque, 6-32 or m3 screw 10 lbf?in (1.1n?m) absolute maximum ratings c/w description fifth generation hexfets from international rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. this benefit, combined with the fast switching speed and ruggedized device design that hexfet power mosfets are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. the to-220 fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. the moulding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. this isolation is equivalent to using a 100 micron mica barrier with standard to-220 product. the fullpak is mounted to a heatsink using a single clip or by a single screw fixing.
IRLI540N parameter min. typ. max. units conditions v (br)dss drain-to-source breakdown voltage 100 CCC CCC v v gs = 0v, i d = 250a d v (br)dss / d t j breakdown voltage temp. coefficient CCC 0.11 CCC v/c reference to 25c, i d = 1ma ? CCC CCC 0.044 v gs = 10v, i d = 12a ? CCC CCC 0.053 w v gs = 5.0v, i d = 12a ? CCC CCC 0.063 v gs = 4.0v, i d = 10a ? v gs(th) gate threshold voltage 1.0 CCC 2.0 v v ds = v gs , i d = 250a g fs forward transconductance 14 CCC CCC s v ds = 25v, i d = 18a ? CCC CCC 25 a v ds = 100v, v gs = 0v CCC CCC 250 v ds = 80v, v gs = 0v, t j = 150c gate-to-source forward leakage CCC CCC 100 na v gs = 16v gate-to-source reverse leakage CCC CCC -100 v gs = -16v q g total gate charge CCC CCC 74 i d = 18a q gs gate-to-source charge CCC CCC 9.4 nc v ds = 80v q gd gate-to-drain ("miller") charge CCC CCC 38 v gs = 5.0v, see fig. 6 and 13 ?? t d(on) turn-on delay time CCC 11 CCC v dd = 50v t r rise time CCC 81 CCC ns i d = 18a t d(off) turn-off delay time CCC 39 CCC r g = 5.0 w, v gs = 5.0v t f fall time CCC 62 CCC r d = 2.7 w, see fig. 10 ?? between lead, 6mm (0.25in.) from package and center of die contact c iss input capacitance CCC 1800 CCC v gs = 0v c oss output capacitance CCC 350 CCC v ds = 25v c rss reverse transfer capacitance CCC 170 CCC ? = 1.0mhz, see fig. 5 ? c drain to sink capacitance CCC 12 CCC ? = 1.0mhz electrical characteristics @ t j = 25c (unless otherwise specified) i gss i dss drain-to-source leakage current s d g l d internal drain inductance CCC 4.5 CCC l s internal source inductance CCC 7.5 CCC r ds(on) static drain-to-source on-resistance nh pf s d g notes: ? repetitive rating; pulse width limited by max. junction temperature. ( see fig. 11 ) ? starting t j = 25c, l = 1.9mh r g = 25 w , i as = 18a. (see figure 12) ? t=60s, ?=60hz ? i sd 18a, di/dt 180a/s, v dd v (br)dss , t j 175c ? uses irl540n data and test conditions ? pulse width 300s; duty cycle 2%. parameter min. typ. max. units conditions i s continuous source current mosfet symbol (body diode) CCC CCC showing the i sm pulsed source current integral reverse (body diode) ?? CCC CCC p-n junction diode. v sd diode forward voltage CCC CCC 1.3 v t j = 25c, i s = 18a, v gs = 0v ? t rr reverse recovery time CCC 190 290 ns t j = 25c, i f = 18a q rr reverse recoverycharge CCC 1.1 1.7 c di/dt = 100a/s ?? t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by l s +l d ) source-drain ratings and characteristics a 23 120
IRLI540N fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 1. typical output characteristics fig 3. typical transfer characteristics 1 10 100 1000 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source volta g e ( v ) ds a 20 s pulse width t = 25c j vgs top 15v 12v 10v 8.0v 6.0v 4.0v 3.0v bottom 2.5v 2.5v 1 10 100 1000 0.1 1 10 100 i , drain-to-source current (a) d v , drain-to-source volta g e ( v ) ds a 20 s pulse width t = 175c vgs top 15v 12v 10v 8.0v 6.0v 4.0v 3.0v bottom 2.5v 2.5v j 1 10 100 1000 246810 t = 25c j gs v , gate-to-source volta g e (v) d i , drain-to-source current (a) t = 175c j a v = 50v 20s pulse width ds 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 j t , junction temperature (c) r , drain-to-source on resistance ds(on) (normalized) v = 10v gs a i = 30a d
IRLI540N fig 6. typical gate charge vs. gate-to-source voltage fig 8. maximum safe operating area fig 5. typical capacitance vs. drain-to-source voltage fig 7. typical source-drain diode forward voltage 0 1000 2000 3000 1 10 100 c, capacitance (pf) ds v , drain-to-source volta g e ( v ) a v = 0v, f = 1mhz c = c + c , c shorted c = c c = c + c gs iss gs gd ds rss gd oss ds gd c iss c oss c rss 0 3 6 9 12 15 0 20406080100 q , total gate char g e ( nc ) g v , gate-to-source voltage (v) gs v = 80v v = 50v v = 20v ds ds ds a for test circuit see figure 13 i = 18a d 1 10 100 1000 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 t = 25c j v = 0v gs v , source-to-drain voltage (v) i , reverse drain current (a) sd sd a t = 175c j 1 10 100 1000 1 10 100 1000 v , drain-to-source volta g e ( v ) ds i , drain current (a) operation in this area limited by r d ds(on) 10s 100s 1ms 10ms a t = 25c t = 175c sin g le pulse c j
IRLI540N fig 10a. switching time test circuit v ds 90% 10% v gs t d(on) t r t d(off) t f fig 10b. switching time waveforms v ds pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 5.0v + - v dd fig 11. maximum effective transient thermal impedance, junction-to-case fig 9. maximum drain current vs. case temperature 25 50 75 100 125 150 175 0 5 10 15 20 25 t , case temperature ( c) i , drain current (a) c d 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 notes: 1. duty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectangular pulse duration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 single pulse (thermal response)
IRLI540N q g q gs q gd v g charge d.u.t. v ds i d i g 3ma v gs .3 m f 50k w .2 m f 12v current regulator same type as d.u.t. current sampling resistors + - 5.0 v fig 13b. gate charge test circuit fig 13a. basic gate charge waveform fig 12c. maximum avalanche energy vs. drain current fig 12b. unclamped inductive waveforms fig 12a. unclamped inductive test circuit t p v (br)dss i as 0 200 400 600 800 25 50 75 100 125 150 175 j e , single pulse avalanche energy (mj) as a startin g t , junction temperature ( c ) i top 7.3a 13a bottom 18a d r g i as 0.01 w t p d.u.t l v ds + - v dd driver a 15v 10v
IRLI540N p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period + - + + + - - - fig 14. for n-channel hexfets * v gs = 5v for logic level devices peak diode recovery dv/dt test circuit ? ? ? r g v dd dv/dt controlled by r g driver same type as d.u.t. i sd controlled by duty factor "d" d.u.t. - device under test d.u.t circuit layout considerations low stray inductance ground plane low leakage inductance current transformer ? *
IRLI540N part marking information to-220 fullpak package outline to-220 fullpak outline dimensions are shown in millimeters (inches) lead assignments 1 - g a te 2 - d r ain 3 - s o u rc e notes: 1 dimensioning & tolerancing per ansi y14.5m, 1982 2 controlling dimension: inch. d c a b minimum creepage distance between a-b-c-d = 4.80 (.189) 3x 2.85 (.112) 2.65 (.104) 2.80 (.110) 2.60 (.102) 4.80 (.189) 4.60 (.181) 7.10 (.280) 6.70 (.263) 3.40 (.133) 3.10 (.123) ? - a - 3.70 (.145) 3.20 (.126) 1.15 (.045) m in. 3.30 (.130) 3.10 (.122) - b - 0.90 (.035) 0.70 (.028) 3x 0.25 (.010) m a m b 2.54 (.100) 2x 3x 13.70 (.540) 13.50 (.530) 16.00 (.630) 15.80 (.622) 1 2 3 10.60 (.417) 10.40 (.409) 1.40 (.055) 1.05 (.042) 0.48 (.019) 0.44 (.017) part number international rectif ier logo date code (yyww) yy = year ww = week assembly lot co de e401 9245 irfi840g example : this is an irfi840g w ith assembly lo t co de e401 a world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 322 3331 european headquarters: hurst green, oxted, surrey rh8 9bb, uk tel: ++ 44 1883 732020 ir canada: 15 lincoln court, brampton, ontario l6t 3z2, tel: (905) 453 2200 ir germany: saalburgstrasse 157, 61350 bad homburg tel: ++ 49 6172 96590 ir italy: via liguria 49, 10071 borgaro, torino tel: ++ 39 11 451 0111 ir far east: 171 (k&h bldg.) 30-4 nishi-ikebukuro 3-chome, toshima-ku, tokyo japan tel: 81 33 983 0086 ir southeast asia: 315 outram road, #10-02 tan boon liat building, singapore 16907 tel: 65 221 8371 data and specifications subject to change without notice. 3/98
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