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integrated circuit systems, inc. ics94241 0453c?10/26/04 pin configuration recommended application: via pl133-t style chipset with intel differential piii processor output features: 2 - cpus @2.5v 13 - sdram @ 3.3v 7 - pci @3.3v, 1 - 48mhz, @3.3v 1 - 24mhz @ 3.3v 2 - ref @3.3v, 14.318mhz. features: programmable ouput frequency programmable ouput rise/fall time programmable output to output skew programmable spread spectrum for emi control real time system reset output watchdog timer technology to reset system if over-clocking causes malfunction uses external 14.318mhz crystal key specifications: cpu ? cpu: <175ps sdram - sdram: <500ps pci ? pci: <500ps cpu-sdram: <500ps cpu(early)-pci: min=1.0ns, typ=2.0ns, max=4.0ns programmable tch? for differential piii? processor block diagram 48-pin 300mil ssop vddref gndref x1 x2 vddpci * fs4/pciclk0 * fs3/pciclk1 gndpci pciclk2 pciclk3 pciclk4 pciclk5 pciclk6 vddpci buffer_in gndsdr sdram12 sdram11 vddsdr sdram10 sdram9 gnd48 s data sclk vtt_pwrgd# ref0 ref1/fs2 ** gndcpu cpuclk_cs cpuclk0 vddlcpu reset# sdram0 gndsdr sdram1 sdram2 vddsdr sdram3 sdram4 gndsdr sdram5 sdram6 vddsdr sdram7 sdram8 avdd48 48mhz/fs0 ** 24mhz/fs1 ** 1 ics94241 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 * internal pull-up resistor of 120k to vdd ** internal pull-down resistor of 120k to gnd 1. this output has 1.5 to 2x drive strength functionality for additional margin testing frequencies refer to pg 5 frequency table. bit2 bit7 bit6 bit5 bit4 fs4 fs3 fs2 fs1 fs0 0 0 0 0 0 66.67 33.33 +/- 0.25 center spread 0 0 0 0 1 66.67 33.33 0 to -0.5% down spread 0 0 0 1 0 68.67 34.33 0.25 center spread 0 0 0 1 1 71.34 35.66 +/- 0.25 center spread 0 1 0 0 0 100.00 33.33 +/- 0.25 center spread 0 1 0 0 1 100.00 33.33 0 to -0.5% down spread 0 1 0 1 0 103.00 34.33 +/- 0.25 center spread 0 1 0 1 1 107.00 35.67 +/- 0.25 center spread 1 0 0 0 0 200.00 33.33 +/- 0.25 center spread 1 0 0 0 1 200.00 33.33 0 to -0.5% down spread 1 0 0 1 0 206.00 34.33 +/- 0.25 center spread 1 0 0 1 1 214.00 35.67 +/- 0.25 center spread 1 1 0 0 0 133.33 33.33 +/- 0.25 center spread 1 1 0 0 1 133.33 33.33 0 to -0.5% down spread 1 1 0 1 0 137.33 34.33 +/- 0.25 center spread 1 1 0 1 1 142.67 35.67 +/- 0.25 center spread spread percentage cpuclk pciclk
2 ics94241 0453c?10/26/04 pin configuration notes: 1: internal pull-up resistor of 120k to 3.3v on indicated inputs 2: internal pull-down to gnd on indicated inputs 3: bidirectional input/output pins, input logic levels are latched at internal power-on-reset. use 10kohm resistor to program logic hi to vdd or gnd for logic low. general description the ics94241 is a single chip timing control hub for desktop designs using via pl133-t style chipset with intel differential piii processor. it provides all necessary clock signals for such a system. the ics94241 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). ics is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. this part incorporates ics's newest clock technology which more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. tch also incorporates ics's watchdog timer technology in having a frequency reset feature to provide a safe setting under unstable system conditions. r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 6 3 , 0 3 , 9 1 , 4 1 , 5 , 1d d vr w pv 3 . 3 l a n i m o n , y l p p u s r e w o p 5 4 , 9 3 , 3 3 , 2 2 , 6 1 , 8 , 2d n gr w pd n u o r g 31 xn i k c a b d e e f d n a ) f p 6 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 42 xt u o p a c d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 6 3 ( 6 4 s f 3 , 1 n id n g o t n w o d - l l u p l a n r e t n i . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 0 k l c i c pt u o w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 7 3 s f 3 , 1 n id n g o t n w o d - l l u p l a n r e t n i . t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 1 k l c i c pt u o w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 9 , 0 1 , 1 1 , 2 1 , 3 1) 2 : 6 ( k l c i c pt u o w e k s s n 4 - 1 h t i w s k c o l c u p c o t s u o n o r h c n y s . s t u p t u o k c o l c i c p ) y l r a e u p c ( 5 1n i r e f f u bn i. s t u p t u o m a r d s r o f s r e f f u b t u o n a f o t t u p n i , 9 2 , 8 2 , 1 2 , 0 2 , 8 1 , 7 1 , 7 3 , 5 3 , 4 3 , 4 3 , 2 3 , 1 3 0 4 , 8 3 ) 0 : 2 1 ( m a r d st u o n i p n i r e f f u b m o r f s t u p t u o r e f f u b t u o n a f , s t u p t u o k c o l c m a r d s ) t e s p i h c y b d e l l o r t n o c ( 3 2a t a d so / ii r o f n i p a t a d 2 t n a r e l o t v 5 y r t i u c r i c c 4 2k l c sn ii f o n i p k c o l c 2 t n a r e l o t v 5 y r t i u c r i c c 5 2 1 s f 3 , 2 n i. t u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f z h m 4 2t u ok c o l c t u p t u o z h m 4 2 6 2 z h m 8 4t u ok c o l c t u p t u o z h m 8 4 0 s f 3 , 2 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 7 28 4 d d v ar w ps t u p t u o z h m 8 4 r o f r e w o p g o l a n a 1 4t e s e rt u o r o e g n a h c o i t a r y c n e u q e r f r o f l a n g i s t e s e r m e t s y s e m i t l a e r . w o l e v i t c a s i l a n g i s s i h t . t u o e m i t r e m m i t g o d h c t a w 2 4u p c l d d vr w pl a n i m o n v 5 . 2 s k c o l c u p c r o f y l p p u s 3 40 k l c u p ct u os t u p t u o k c o l c u p c 4 4s c _ k l c u p ct u ok c o l c t s o h t e s p i h c r o f t u p t u o k c o l c u p c 6 4 2 s f 3 , 2 n it u p n i d e h c t a l . n i p t c e l e s y c n e u q e r f 1 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 7 40 f e rt u o. k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 8 4# d g r w p _ t t vn i e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i l t t v l v 3 . 3 s i h t d e l p m a s e b o t y d a e r e r a d n a d i l a v e r a s t u p n i s f n e h w ) w o l e v i t c a (
3 ics94241 0453c?10/26/04 general i 2 c serial interface information for the ics94241 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending byte 0 through byte 20 (see note) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends byte 0 through byte 8 (default) ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8). ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 18 ack byte 19 ack byte 20 ack stop bit how to write: *see notes on the following page . controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 12 h has been written to b6 byte18 ack if 13 h has been written to b6 byte 19 ack if 14 h has been written to b6 byte 20 ack stop bit how to read:
4 ics94241 0453c?10/26/04 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. readback will support standard smbus controller protocol. the number of bytes to readback is defined by writing to byte 8. 2. when writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. if for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. 3. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 4. the input is operating at 3.3v logic levels. 5. the data byte format is 8 bit bytes. 6. to simplify the clock generator i 2 c interface, the protocol is set to use only block-writes from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 7. at power-on, all registers are set to a default condition, as shown. notes: brief i 2 c registers description for ics94241 programmable system frequency generator register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1-6 active / inactive output control registers/latch inputs read back. see individual byte description vendor id & revision id registers 7 byte 7 bit (7:4) is ics vendor id - 001. other bits in this register designate device revision id of this part. see individual byte description byte count read back register 8 w r iti ng t o thi s reg i s t er w ill con fi gure byte count and how many byte will be read back. do not write 00 h to this byte 08 h watchdog timer count register 9 writing to this register will configure the number of seconds for the watchdog timer to reset. 10 h watchdog control registers 10 bit [6:0] watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 vco control selection bit 10 bit [7] this bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 0 vco frequency control registers 11-12 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depended on hardware/byte 0 configuration spread spectrum control registers 13-14 these registers control the spread percentage amount. depended on hardware/byte 0 configuration group skews control registers 15-16 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 17-20 these registers will control the output rise and fall time. see individual byte description
5 ics94241 0453c?10/26/04 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. bit pwd bit2 bit7 bit6 bit5 bit4 fs4 fs3 fs2 fs1 fs0 0 0 0 0 0 66.67 33.33 center spread +/- 0.25% 0 0 0 0 1 66.67 33.33 down spread 0 to - 0.5% 0 0 0 1 0 68.67 34.33 center spread +/- 0.25% 0 0 0 1 1 71.34 35.66 center spread +/- 0.25% 0 0 1 0 0 73.34 36.66 center spread +/- 0.25% 0 0 1 0 1 76.67 38.33 center spread +/- 0.25% 0 0 1 1 0 150.00 30.00 center spread +/- 0.25% 0 0 1 1 1 166.67 33.33 center spread +/- 0.25% 0 1 0 0 0 100.00 33.33 center spread +/- 0.25% 0 1 0 0 1 100.00 33.33 down spread 0 to - 0.5% 0 1 0 1 0 103.00 34.33 center spread +/- 0.25% 0 1 0 1 1 107.00 35.67 center spread +/- 0.25% 0 1 1 0 0 110.00 36.67 center spread +/- 0.25% 0 1 1 0 1 115.00 38.33 center spread +/- 0.25% 0 1 1 1 0 100.90 33.63 center spread +/- 0.25% 0 1 1 1 1 90.00 30.00 center spread +/- 0.25% 1 0 0 0 0 200.00 33.33 center spread +/- 0.25% 1 0 0 0 1 200.00 33.33 down spread 0 to - 0.5% 1 0 0 1 0 206.00 34.33 center spread +/- 0.25% 1 0 0 1 1 214.00 35.67 center spread +/- 0.25% 1 0 1 0 0 220.00 36.67 center spread +/- 0.25% 1 0 1 0 1 230.00 38.33 center spread +/- 0.25% 1 0 1 1 0 201.80 33.63 center spread +/- 0.25% 1 0 1 1 1 180.00 30.00 center spread +/- 0.25% 1 1 0 0 0 133.33 33.33 center spread +/- 0.25% 1 1 0 0 1 133.33 33.33 down spread 0 to - 0.5% 1 1 0 1 0 137.33 34.33 center spread +/- 0.25% 1 1 0 1 1 142.67 35.67 center spread +/- 0.25% 1 1 1 0 0 146.67 36.67 center spread +/- 0.25% 1 1 1 0 1 153.33 38.33 center spread +/- 0.25% 1 1 1 1 0 133.90 33.48 center spread +/- 0.25% 1 1 1 1 1 120.00 30.00 center spread +/- 0.25% bit 3 0 bit 1 1 bit 0 0 note 1 0=frequency selected by hardware; 1=frequency selected by bit2, (7:4) 0=spread off; 1=spread spectrum enable 0=running; 1=tristate description bit 2, (7:4) cpuclk pciclk spread percentage
6 ics94241 0453c?10/26/04 byte 1: cpu, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x # 2 s f d e h c t a l 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b0 41 0 m a r d s 2 t i b-1 ) d e v r e s e r ( 1 t i b3 41 0 k l c u p c 0 t i b4 41 s c _ k l c u p c byte 2: pci, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b61 0 k l c i c p 5 t i b3 11 6 k l c i c p 4 t i b2 11 5 k l c i c p 3 t i b1 11 4 k l c i c p 2 t i b0 11 3 k l c i c p 1 t i b91 2 k l c i c p 0 t i b71 1 k l c i c p notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b-x # 1 s f d e h c t a l 2 t i b-x # 4 s f d e h c t a l 1 t i b-x # 3 s f d e h c t a l 0 t i b-1 ) d e v r e s e r ( byte 4: reserved , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b-1 ) d e v r e s e r ( 2 t i b-1 ) d e v r e s e r ( 1 t i b6 41 1 f e r 0 t i b7 41 0 f e r byte 5: peripheral , active/inactive register (1= enable, 0 = disable) byte 3: sdram, active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-1 ) e t o n ( d e v r e s e r 5 t i b-x ) e t o n ( d e v r e s e r 4 t i b-x ) e t o n ( d e v r e s e r 3 t i b-x ) e t o n ( d e v r e s e r 2 t i b-x ) e t o n ( d e v r e s e r 1 t i b-x ) e t o n ( d e v r e s e r 0 t i b-x ) e t o n ( d e v r e s e r byte 6: peripheral , active/inactive register (1= enable, 0 = disable) note: this is an unused register writing to this register will not affect device performance or functinality. t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-x # 0 s f d e h c t a l 5 t i b6 21 z h m 8 4 4 t i b5 21 z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b , 8 1 , 7 1 1 2 , 0 2 1) 9 : 2 1 ( m a r d s 1 t i b , 9 2 , 8 2 2 3 , 1 3 1) 5 : 8 ( m a r d s 0 t i b , 5 3 , 4 3 8 3 , 7 3 1) 1 : 4 ( m a r d s
7 ics94241 0453c?10/26/04 byte 7: vendor id and revision id register byte 8: byte count and read back register notes: 1. pwd = power on default t i bd w pn o i t p i r c s e d 7 t i b0 d e v r e s e r 6 t i b0 d e v r e s e r 5 t i b0 d e v r e s e r 4 t i b0 d e v r e s e r 3 t i b1 d e v r e s e r 2 t i b0 d e v r e s e r 1 t i b0 d e v r e s e r 0 t i b0 d e v r e s e r t i bd w pn o i t p i r c s e d 7 t i b0 d i r o d n e v 6 t i b0 d i r o d n e v 5 t i b1 d i r o d n e v 4 t i bx d i n o i s i v e r 3 t i bx d i n o i s i v e r 2 t i bx d i n o i s i v e r 1 t i bx d i n o i s i v e r 0 t i bx d i n o i s i v e r byte 11: vco frequency control register note: the decimal representation of these 7 bits (byte 11 [6:0]) + 2 is equal to the ref divider value . t i bd w pn o i t p i r c s e d 7 t i bx 0 t i b r e d i v i d o c v 6 t i bx 6 t i b r e d i v i d f e r 5 t i bx 5 t i b r e d i v i d f e r 4 t i bx 4 t i b r e d i v i d f e r 3 t i bx 3 t i b r e d i v i d f e r 2 t i bx 2 t i b r e d i v i d f e r 1 t i bx 1 t i b r e d i v i d f e r 0 t i bx 0 t i b r e d i v i d f e r byte 12: vco frequency control register note: the decimal representation of these 9 bits (byte 12 bit [7:0] & byte 11 bit [7] ) + 8 is equal to the vco divider value. for example if vco divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7. t i bd w pn o i t p i r c s e d 7 t i bx 8 t i b r e d i v i d o c v 6 t i bx 7 t i b r e d i v i d o c v 5 t i bx 6 t i b r e d i v i d o c v 4 t i bx 5 t i b r e d i v i d o c v 3 t i bx 4 t i b r e d i v i d o c v 2 t i bx 3 t i b r e d i v i d o c v 1 t i bx 2 t i b r e d i v i d o c v 0 t i bx 1 t i b r e d i v i d o c v byte 9: watchdog timer count register t i bd w pn o i t p i r c s e d 7 t i b0 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t s m 1 r o s m 0 9 2 o t d n o p s e r r o c s t i b 8 e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t e h t t e s e r d n a e d o m m r a l a o t s e o g t i t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f 6 . 4 = s m 0 9 2 x 6 1 s i p u r e w o p t a . s d n o c e s 6 t i b0 5 t i b0 4 t i b1 3 t i b0 2 t i b0 1 t i b0 0 t i b0 note: fs values in bit (4:0) will correspond to byte 0 fs values. default safe frequency is same as 00000 entry in byte0. byte 10: vco control selection bit & watchdog timer control register t i bd w pn o i t p i r c s e d 7 t i b0 q e r f 2 1 & 1 1 b = 1 / q e r f 0 b / w h = 0 6 t i b0 e l b a n e = 1 / e l b a s i d = 0 e l b a n e d w 5 t i b0 m r a l a = 1 / l a m r o n = 0 s u t a t s d w 4 t i b1 4 s f , y c n e u q e r f e f a s d w 3 t i b1 3 s f , y c n e u q e r f e f a s d w 2 t i b0 2 s f , y c n e u q e r f e f a s d w 1 t i b0 1 s f , y c n e u q e r f e f a s d w 0 t i b0 0 s f , y c n e u q e r f e f a s d w
8 ics94241 0453c?10/26/04 byte 13: spread sectrum control register byte 14: spread sectrum control register note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b m u r t c e p s d a e r p s 6 t i bx 6 t i b m u r t c e p s d a e r p s 5 t i bx 5 t i b m u r t c e p s d a e r p s 4 t i bx 4 t i b m u r t c e p s d a e r p s 3 t i bx 3 t i b m u r t c e p s d a e r p s 2 t i bx 2 t i b m u r t c e p s d a e r p s 1 t i bx 1 t i b m u r t c e p s d a e r p s 0 t i bx 0 t i b m u r t c e p s d a e r p s t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx 2 1 t i b m u r t c e p s d a e r p s 3 t i bx 1 1 t i b m u r t c e p s d a e r p s 2 t i bx 0 1 t i b m u r t c e p s d a e r p s 1 t i bx 9 i b m u r t c e p s d a e r p s 0 t i bx 8 t i b m u r t c e p s d a e r p s note: please utilize software utility provided by ics application engineering to configure spread spectrum. incorrect spread percentage may cause system failure. byte 15: output skew control byte 16: output skew control t i bd w pn o i t p i r c s e d 7 t i b0 l o r t n o c w e k s 0 k l c i c p 6 t i b1 5 t i b1 4 t i b0 3 t i b0 l o r t n o c w e k s ) 1 : 6 ( k l c i c p 2 t i b1 1 t i b1 0 t i b0 byte 17: output rise/fall time select register byte 18: output rise/fall time select register t i bd w pn o i t p i r c s e d 7 t i b1 l o r t n o c e t a r w e l s ) 1 : 6 ( k l c i c p 6 t i b0 5 t i b1 l o r t n o c e t a r w e l s 0 k l c i c p 4 t i b0 3 t i b1 l o r t n o c e t a r w e l s z h m 8 4 2 t i b0 1 t i b1 l o r t n o c e t a r w e l s z h m 4 2 0 t i b0 notes: 1. pwd = power on default 2. the power on default for byte 13-20 depends on the harware (latch inputs fs[0:4]) or i 2 c (byte 0 bit [1:7]) setting. be sure to read back and re-write the values of these 8 registers when vco frequency change is desired for the first pass. t i bd w pn o i t p i r c s e d 7 t i b0 l o r t n o c w e k s ) 1 : 2 1 ( m a r d s 6 t i b0 5 t i b0 l o r t n o c w e k s s c _ k l c u p c 4 t i b0 3 t i b0 l o r t n o c w e k s 0 k l c u p c 2 t i b0 1 t i b0 l o r t n o c w e k s 0 m a r d s 0 t i b0 t i bd w pn o i t p i r c s e d 7 t i b1 l o r t n o c e t a r w e l s s c _ k l c u p c 6 t i b0 5 t i b1 l o r t n o c e t a r w e l s 0 k l c u p c 4 t i b0 3 t i b1 l o r t n o c e t a r w e l s 0 m a r d s 2 t i b0 1 t i b1 l o r t n o c e t a r w e l s ) 1 : 2 1 ( m a r d s 0 t i b0
9 ics94241 0453c?10/26/04 vco programming constrains vco frequency ...................... 150mhz to 500mhz vco divider range ................ 8 to 519 ref divider range ................. 2 to 129 phase detector stability .......... 0.3536 to 1.4142 useful formula vco frequency = 14.31818 x vco/ref divider value phase detector stabiliy = 14.038 x (vco divider value) -0.5 note: 1. user needs to ensure step 3 & 7 is carried out. systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. step 3 & 7 assure the correct spread and skew relationship. 2. if vco, ref divider values or phase detector stability are out of range, the device may fail to function correctly. 3. follow min and max vco frequency range provided. internal pll could be unstable if vco frequency is too fast or too slow. use 14.31818mhz x vco/ref divider values to calculate the vco frequency (mhz). 4. ics recommends users, to utilize the software utility provided by ics application engineering to program the vco frequency. 5. spread percent needs to be calculated based on vco frequency, spread modulation frequency and spread amount desired. see application note for software support. to program the vco frequency for over-clocking. 0. before trying to program our clock manually, consider using ics provided software utilities for easy programming. 1. select the frequency you want to over-clock from with the desire gear ratio (i.e. cpu:sdram:3v66:pci ratio) by writing to byte 0, or using initial hardware power up frequency. 2. write 0001, 1001 (19 h ) to byte 8 for readback of 21 bytes (byte 0-20). 3. read back byte 11-20 and copy values in these registers. 4. re-initialize the write sequence. 5. write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired vco & ref divider values. 6. write to byte 13 to 20 with the values you copy from step 3. this maintains the output spread, skew and slew rate. 7. the above procedure is only needed when changing the vco for the 1st pass. if vco frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx d e v r e s e r 3 t i bx d e v r e s e r 2 t i bx d e v r e s e r 1 t i bx d e v r e s e r 0 t i bx d e v r e s e r byte 19: reserved register note: byte 19 and 20 are reserved registers, these are unused registers writing to these registers will not affect device performance or functionality. t i bd w pn o i t p i r c s e d 7 t i bx d e v r e s e r 6 t i bx d e v r e s e r 5 t i bx d e v r e s e r 4 t i bx d e v r e s e r 3 t i bx d e v r e s e r 2 t i bx d e v r e s e r 1 t i bx d e v r e s e r 0 t i bx d e v r e s e r byte 20: reserved register
10 ics94241 0453c?10/26/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply volta g e v dd , v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in = v dd 5ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with no pull-up resistors -200 ma operating i dd3.3op66 c l = 0 pf; select @ 66mhz 90 supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 90 input frequency f i v dd = 3.3 v 12 16 mhz input capacitance 1 c in logic inputs 5 pf c inx x1 & x2 pins 27 45 pf clk stabilization1 t stab from v dd = 3.3 v to 1% target freq. 3ms 1 guaranteed by design, not 100% tested in production. ma 180 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 10 72 supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 15 100 skew 1 t cpu-pci v t = 1.5 v; vtl = 1.25 v 1.5 4 ns 1 guaranteed by design, not 100% tested in production. ma
11 ics94241 0453c?10/26/04 electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12.0ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v output high current i oh2b v oh = 1.7 v -19 ma output low current i ol2b v ol = 0.7 v 19 ma rise time t r2b 1 v ol = 0.5v, v oh = 2.0 v 0.95 1.3 ns fall time t f2b 1 v oh = 2.0v, v ol = 0.5 v 0.95 1.3 ns duty cycle d t2b 1 v t = 1.25 v 45 49 55 % skew t sk2b 1 v t = 1.25 v 145 175 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 225 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 v output low voltage v ol1 i ol = 9.4 ma 0.4 v output high current i oh1 v oh = 2.0 v -22 ma output low current i ol1 v ol = 0.8 v 25 ma rise time 1 t r1 v ol = 0.4 v,v oh = 2.4 v 1.6 2 ns fall time 1 t f1 v oh = 2.4 v,v ol = 0.4 v 1.9 2 ns d uty c ycle 1 d t1 v t = 1.5 v 45 52 55 % skew 1 t sk1 v t = 1.5 v 50 500 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.5 v 240 250 ps 1 guaranteed by design, not 100% tested in production.
12 ics94241 0453c?10/26/04 electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -28ma 2.4 v output low voltage v ol3 i ol = 23 ma 0.4 v output high current i oh3 v oh = 2.0 v -54 ma output low current i ol3 v oh = 0.8 v 41 ma rise time t r31 v ol = 0.4v, v oh = 2.4 v 0.85 2 ns fall time t f31 v oh = 2.4v, v ol = 0.4 v 0.85 2 ns duty cycle d t31 v t = 1.5 v 45 50 55 % skew1 t sk1 v t = 1.5 v 200 500 ps propagation delay t prop v t = 1.5 v 5ns 1guarenteed by design, not 100% tested in production. electrical characteristics - 24mhz, 48mhz, ref t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -16 ma 2.4 v output low voltage v ol5 i ol = 9 ma 0.4 v output high current i oh5 v oh = 2.0 v -22 ma output low current i ol5 v ol = 0.8 v 16 ma rise time 1 t r5 v ol = 0.4 v, voh = 2.4 v 1.5 4 ns fall time 1 t f5 v oh = 2.4 v, vol = 0.4 v 1.5 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % jiter, cycle-to-cycle (24, 48mhz) t jcyc-cyc2b 1 v t = 1.5 v 250 500 ps 1 guaranteed by design, not 100% tested in production.
13 ics94241 0453c?10/26/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
14 ics94241 0453c?10/26/04 group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.5v 66mhz pci 33mhz apic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns
15 ics94241 0453c?10/26/04 ordering information ics94241 y flf-t designation for tape and reel packaging lead free (optional) package type f=ssop revision designator (will not correlate with datasheet revision) device type prefix ics, av = standard device example: ics xxxx y f lf - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n
16 ics94241 0453c?10/26/04 revision history rev. issue date description page # c 10/26/2004 added lead free ordering information 15

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