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| voice mask mcu HT83B60 revision: v1.00 date: de ? e ?? e ? 1 ?? ? 011 de ? e ?? e ? 1 ?? ? 011
rev. 1.00 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 3 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu table of contents eates eneal eston lo aam n ssnment n eston bsolte amm atns c caatests c caatests oeon eset caatests caatests ces r vs. f (exte ? nal rc) cha ? t cha ? a ? te ? isti ? s cu ? ve at ? 5c ................................................... 11 t vs. f (exte ? nal rc) cha ? t cha ? a ? te ? isti ? s cu ? ve ............. ................................................... 11 v vs. f (hirc) chart characteristics curve at 25c ? trimmed at 5v ................................. 1 ? sste? a??hite?tu?e ...................................................................................... 13 clocking and pipelining ......................................................................................................... 13 program counter ................................................................................................................... 14 sta ? k ..................................................................................................................................... 15 arithmetic and logic unit ? alu ........................................................................................... 15 ?og?a? e?o? ........................................................................................... 16 st ? u ? tu ? e ................................................................................................................................ 16 special vectors ..................................................................................................................... 16 look-up table ............. ........................................................................................................... 17 table program example ........................................................................................................ 18 data e?o? .................................................................................................. 1? st ? u ? tu ? e ................................................................................................................................ 1 ? general purpose data memory ............................................................................................ ? 0 special purpose data memory ............................................................................................. ? 0 se?ial fun?tion registe?s ........... ................................................................ ?0 indirect addressing registers ? iar0 ............. ...................................................................... ? 0 memory pointers ? mp0 ............ ........................................................................................... ?? accumulator ? acc ............................................................................................................... ?? program counter low register ? pcl .................................................................................. ? 3 look-up table registers - tblp, tblh ................................................................................. ? 3 watchdog timer register - wdts ........................................................................................ ? 3 status register ? status .................................................................................................... ? 3 interrupt control register - intc, intch ............................................................................. ? 4 ti ? e ? registe ? s ..................................................................................................................... ? 4 input/output ports and control registers ............. ................................................................ ? 5 port c pull-high control register - pcphc .......................................................................... ? 5 rev. 1.00 ? de?e??e? 1?? ? 011 rev. 1.00 3 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu voice control and audio output registers - dal, dah, vol ................................................ ? 5 pulse width modulator registers - pwmc, pwml, pwmh ................................................. ? 5 serial interface module (sim) registers - simc0a/b, simc1a/b, simc2a/b, simara/b, simdra/b .......................................................................................................... ? 5 input/output ports ......................................................................................... 26 pull-high resistors ................................................................................................................ ? 6 port a wake-up ............. ........................................................................................................ ? 6 i/o port control registers ..................................................................................................... ? 6 pin-shared functions ............. ............................................................................................... ? 8 programming considerations ............. ................................................................................... ? 8 timers ... .......................................................................................................... 29 confguring the timer input clock source ............................................................................ ?? timer registers - tmr0, tmr1 ............................................................................................ ?? timer control registers - tmr0c, tmr1c .......................................................................... 30 confguring the timer ............................................................................................................ 31 prescaler ............................................................................................................................... 31 programming considerations ............. ................................................................................... 31 timer program example ....................................................................................................... 3 ? time base ....................................................................................................... 33 time base operation ............................................................................................................ 33 time base example ............. ................................................................................................. 33 serial interface ............................................................................................... 34 spi interface ......................................................................................................................... 34 i ? c inte ? fa ? e ............ .............................................................................................................. 40 voice rom access ......................................................................................... 47 voice rom spi modes ......................................................................................................... 47 voice rom read commands ............................................................................................... 48 voice output ................................................................................................... 50 voi ? e cont ? ol ......................................................................................................................... 50 audio output and volume control - dal, dah, vol ............................................................ 50 pulse width modulation output ................................................................... 51 pulse width modulator operation ......................................................................................... 51 interrupts ........................................................................................................ 53 interrupt register .................................................................................................................. 53 interrupt operation ................................................................................................................ 54 interrupt priority ..................................................................................................................... 55 time base interrupt ............................................................................................................... 55 timer interrupt ............. .......................................................................................................... 55 serial interface module - sim - interrupt ............. .................................................................. 55 programming considerations ............. ................................................................................... 56 rev. 1.00 4 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 5 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu reset and initialisation .................................................................................. 56 reset fun ? tions ............. ....................................................................................................... 57 reset initial conditions ......................................................................................................... 58 oscillator ........................................................................................................ 60 external crystal/resonator oscillator ................................................................................... 60 external rc oscillator ........................................................................................................... 61 internal rc oscillator ............................................................................................................ 61 watchdog timer oscillator .................................................................................................... 61 power down mode and wake-up .................................................................. 62 power down mode ................................................................................................................ 6 ? entering the power down mode ........................................................................................... 6 ? standby current considerations ........................................................................................... 6 ? wake-up ................................................................................................................................ 63 low voltage reset - lvr ............................................................................... 63 low voltage detector - lvd .......................................................................... 64 operation .............................................................................................................................. 64 watchdog timer ........... .................................................................................. 64 confguration options ................................................................................... 66 application circuits ........... ............................................................................ 67 instruction set ................................................................................................ 68 introduction ........................................................................................................................... 68 inst ? u ? tion ti ? ing .................................................................................................................. 68 moving and transferring data ............................................................................................... 68 arithmetic operations ............................................................................................................ 68 logical and rotate operations ............. ................................................................................. 6 ? branches and control transfer ............................................................................................. 6 ? bit operations ....................................................................................................................... 6 ? table read operations ......................................................................................................... 6 ? other operations ............. ...................................................................................................... 6 ? instruction set summary ....................................................................................................... 70 instruction defnition ..................................................................................... 72 package information ..................................................................................... 81 28-pin sop (300mil) outline dimensions ............................................................................. 81 reel di ? ensions ................................................................................................................... 8 ? carrier tape dimensions ....................................................................................................... 83 rev. 1.00 4 de?e??e? 1?? ? 011 rev. 1.00 5 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu features ? operating voltage: 2.2v~5.5v ? system clock: 4mhz~12mhz ? three oscillators: ? external crystal-hxt ? external rc-erc ? internal rc-hirc ? fully integrated internal hirc 4mhz, 8mhz and 12mhz oscillators require no external components ? up to 15 i/o pins ? serial interface module- sim for spi or i 2 c , shared with pb ? mask rom: 2kx16 ? data memory: 208x8 ? voice rom: 8m bits ? two 8-bit programmable timer counter with 8-stage prescaler and one time base counter ? 12-bit high quality voltage type d/a output ? pwm circuit can directly drive speaker ? watchdog t imer function ? 8-level subroutine nesting ? 2.7v low voltage detection, tolerance 5% ? 2.2v low voltage reset, tolerance 5% ? power-down function and wake-up functions reduce power consumption ? 63 powerful instructions ? 28-pin sop package general description the HT83B60 is the mask version of the ht83f02 but also includes an integrated 8m bits of v oice rom, connected to the mcu by an internal spi serial interface. this 8-bit high performance microcontroller includes a wide range of functions and special audio features which include a voice synthesizer and tone generator. this device is des igned for applications w hich require multiple i/o s and sound ef fects, such as voice and melody . it also includes an integrated high quality , voltage type dac as well as a pwm generator. this device will form an excellent solution for versatile voice and sound ef fect product applications with their effcient mcu instructions providing the user with programming capability for powerful custom applications. the system frequency can be up to 12mhz at an operating voltage of 5v and includes power -down functions to reduce power consumption. a full choice of oscillator functions are provi ded i ncluding a ful ly i ntegrated syst em osc illator whi ch re quires no e xternal c omponents for its implementation. rev. 1.00 6 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 7 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu block diagram the following block diagram illustrates the main functional blocks. ?? ? ? ?? ? ?? ? ? ? ?? - ? ? ? ? ?? ? pin assignment *: no te t hat t he p ins, sdoa, sdi a, sc ka a nd sc sab, a re de dicated fo r c ontrol o f t he i nternal voice memory and should not be used for other functions. care should be taken regarding these pin- shared i/o pin settings and no external connections should be made to these pins. rev. 1.00 6 de?e??e? 1?? ? 011 rev. 1.00 7 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu pin description pin name function opt i/t o/t description pa0~pa7 pan co st cmos general purpose i/o. c onfiguration option determined pull-high resistors and wake up fun ? tion . pb0/sdob/sdab pb0 co st cmos general purpose i/o. c onfiguration option determined pull-high resistors . sdob co - cmos simb spi data output pin sdab co st cmos simb i ? c data pin pb1/sckb/sclb pb1 co st cmos general purpose i/o. configuration option enabled pull-up. software instructions determine if the pin is a cmos output or schmitt trigger input. sckb co st cmos simb spi clock pin sclb co st cmos simb i ? c clock pin pb2/sdib pb2 co st cmos general purpose i/o. configuration option enabled pull-up. software instructions determine if the pin is a cmos output or schmitt trigger input. sdib co st - simb spi data input pin pb4/sdoa/sdaa pb4 co st cmos internal voice memory control pin. pb4 should be selected as input pin by software instructions and disable the internal pull up by confguration option and select as sima spia data output pin, sdoa. should be left no external connection. sdoa co - cmos sdaa co sti cmos pb5/scka/scla pb5 co st cmos internal voice memory control pin. pb5 should be selected as input pin by software instructions and enable the internal pull up by confguration option and select sima spi clock output pin, scka. should be left no external connection. scka co st cmos scla co st cmos pb6/sdia pb6 co st cmos internal voice memory control pin. pb6 should be selected as input pin by software instructions and enable the internal pull up by confguration option and select sima spi data input pin, sdia. should be left no external connection. sdia co st - pb7/scsab pb7 co st cmos internal voice memory control pin. pb7 should be selected as input pin by software instructions and enable the internal pull up by configuration option and select sima spi slave select pin, scsab. should be left no external connection. scsab co st - pc0/res pc0 pcphc st cmos general purpose i/o. register enabled pull-up. res co st - reset pin pc1/osc1 pc1 pcphc st cmos general purpose i/o. register enabled pull-up osc1 co hxt - pc2/osc2 pc2 pcphc st cmos general purpose i/o. register enabled pull-up osc2 co - hxt aud dac output - - cmos dac output pwm1,pwm2 pwmn - - cmos pwm circuit direct drive speaker vdd_pbio pb power supply - pwr - pb i/o external positive power supply, determine by option. rev. 1.00 8 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 ? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu pin name function opt i/t o/t description vdda dac power supply - pwr - positive dac circuit power supply vddp pwm power supply - pwr - pwm positive power supply vssa ground - pwr - negative dac circuit power supply, ground vssp pwm ground - pwr - pwm negative power supply, ground note: i/t: input type o/t: output type opt: optional by confguration option (co) or register option pwr: power co: confguration option st: schmitt t rigger input cmos: cmos output absolute maximum ratings supply v oltage ........................ v ss -0.3v to v ss +6.0v input v oltage ........................... v ss -0.3v to v dd +0.3v i ol t otal ............................................................. 100ma total power dissipation ................................... 500mv storage t emperature .......................... -50c to 125c operating t emperature ........................ -40c to 85c i oh t otal ........................................................... -100ma note: these are stress ratings only. stresses exceeding the range specifed under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd1 operating voltage (crystal osc) f sys =8mhz ? . ? 5.5 v f sys =10mhz ? .7 5.5 v f sys =12mhz 3.3 5.5 v v dd ? operating voltage (external rc osc) f sys =6mhz ? . ? 5.5 v f sys =8mhz ? .7 5.5 v f sys =12mhz ? .7 5.5 v v dd3 operating voltage (high frequency internal rc osc) f sys =8mhz ? . ? 5.5 v f sys =12mhz ? .7 5.5 v i dd1 operating current (crystal osc, f sys =f h ) 3v no load, f h =8mhz, wdt ena ? le 1.0 ? .0 ? a 5v ? .7 4.5 ? a 3v no load, f h =10mhz, wdt ena ? le 1. ? ? .5 ? a 5v 3.3 6.5 ? a 3v no load, f h =12mhz, wdt ena ? le 1.4 3.5 ? a 5v 3. ? 10.0 ? a rev. 1.00 8 de?e??e? 1?? ? 011 rev. 1.00 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu symbol parameter test conditions min. typ. max. unit v dd conditions i dd ? operating current (erc osc, f sys =f h ) 3v no load, f h =6mhz, wdt ena ? le 0. ? ? .0 ? a 5v ? . ? 4.0 ? a 3v no load, f h =8mhz, wdt ena ? le 1.1 ? .5 ? a 5v ? . ? 6.5 ? a 3v no load, f h =12mhz, wdt ena ? le 1.5 3.5 ? a 5v 4.1 8.0 ? a i dd3 operating current (hirc osc, f sys =f h ) 3v no load, f h =4mhz, wdt ena ? le 0.7 ? .0 ? a 5v 1.6 3.5 ? a 3v no load, f h =8mhz, wdt ena ? le 1. ? ? .5 ? a 5v 3. ? 7.0 ? a 3v no load, f h =12mhz, wdt ena ? le 1.8 4.0 ? a 5v 4.3 8.5 ? a i stb1 standby current (idle) (crystal, erc, hirc osc) 3v no load, system halt, wdt ena ? le ? f sys =12mhz 1. ? 5.5 a 5v 4.5 11.0 a i stb2 standby current (idle) (crystal, erc, hirc osc) 3v no load, system halt, wdt disable, f sys =12mhz 0. ? 1.0 a 5v 0.6 ? .0 a i ol1 i/o port sink current 3v v ol = 0.1v dd 5.5 10 ? a 5v ? .5 ? 0 ? a i oh1 i/o port source current 3v v oh = 0. ? v dd -2.5 -5 ? a 5v -10 -15 ? a i ol2 pwm1/pwm2 sink current 3v v ol = 0.1v dd 60 85 ? a 5v 135 1 ? 5 ? a i oh2 pwm1/pwm2 source cu ?? ent 3v v oh = 0. ? v dd -38 -55 ? a 5v -80 -115 ? a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage( res) 0 0.4v dd v v ih ? input high voltage( res) 0. ? v dd v dd v r ph pull-high resistance 3v 30 100 170 k w 5v 10 35 60 k w i aud aud current source 3v v oh =0. ? v dd -4.5 ? a 5v v oh =0. ? v dd -10 ? a v lvr low voltage reset voltage lvr 2.2v option ? .0 ? 0 ? . ? ? .310 v v lvd low voltage reset voltage lvd 2.7v option ? .565 ? .7 ? .835 v rev. 1.00 10 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 11 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu a.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.2~5.5v ? 8 mhz 2.7~5.5v ? 10 mhz 3.3~5.5v ? 1 ? mhz f sys ? system clock (external rc osc) 5.0v ta= ? 5 c ? exte ? nal r erc =1 ? 0k : * -2%typ. 8 +2%typ. mhz f sys3 system clock (hi rc osc) 5.0v ta= ? 5 c -2%typ. 8 +2%typ. mhz t res external reset low pulse width 1 s t sst system start-up time period (wake-up from halt) f sys =xtal 10 ? 4 t sys f sys =erc or hirc osc 15~16 t sys 1 t sys t int interrupt pulse width 7 8 t sub t lvr low voltage width to reset 350 880 1300 s t lvd lvd time 15 s note: t sys =1/f sys ; t sub =1/f sub power-on reset characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd sta ? t voltage to ensu ? e power-on reset 100 ? v rr vdd vdd rise rate to ensu ? e power-on reset 0.035 v/ms t por minimum time for vdd to remain at v por to ensure power-on reset 1 ? s rev. 1.00 10 de?e??e? 1?? ? 011 rev. 1.00 11 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu characteristics curves r vs. f (external rc) chart characteristics curve at 25 c t vs. f (external rc) chart characteristics curve rev. 1.00 1 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 13 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu v vs. f (hirc) chart characteristics curve at 25 c ? trimmed at 5v rev. 1.00 1? de?e??e? 1?? ? 011 rev. 1.00 13 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu system architecture a key factor in the high-performan ce features of the holtek range of microcontrollers is attributed to the internal system architecture. the range of devices take advantag e of the usual features found within ris c microcontrollers providing increas ed s peed of operation and enhanced performance. the pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call ins tructions. a n 8-bit w ide a lu is us ed in practically all operations of t he i nstruction se t. it c arries out a rithmetic ope rations, l ogic ope rations, rot ation, i ncrement, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. cert ain internal re gisters are im plemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o control system with maximum reliability and fexibility. clocking and pipelining the main system clock, derived from either a crystal, erc or irc oscillator , is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way , one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle t o frst obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ? ? ? ? ? system clocking and pipelining rev. 1.00 14 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 15 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as "jmp" or "call" that demand a jump to a non-consecutive program memory address. note that the program counter width varies with the program memory capacity dependin g upon which device is selected. however , it must be noted that only the lower 8 bits, known as the program counter low register, are directly addressable by user. when executi ng instructions re quiring jumps to non-consecutive addresses such as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the program counter . for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. the lower byte of the program counter , known as the program counter low register or pcl, is available for program control and is a readable and writable register . by transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly, h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory , that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. the lower byte of the program counter is fully accessible under program control. manipulating the pcl might cause program branchin g, so an extra cycle is needed to pre-fetch. further information on the pcl register can be found in the special function register section. mode program counter bits *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial ? eset 0 0 0 0 0 0 0 0 0 0 0 timer base overfow 0 0 0 0 0 0 0 0 1 0 0 timer counter 0 overfow 0 0 0 0 0 0 0 1 0 0 0 timer counter 1 overfow 0 0 0 0 0 0 0 1 1 0 0 sima interrupt 0 0 0 0 0 0 1 0 0 0 0 simb interrupt 0 0 0 0 0 0 1 0 0 0 0 skip program counter+2 loading pcl *10 * ? *8 @7 @6 @5 @4 @3 @ ? @1 @0 jump, call branch #10 # ? #8 #7 #6 #5 #4 #3 # ? #1 #0 retu ? n (ret ? reti) s10 s ? s8 s7 s6 s5 s4 s3 s ? s1 s0 program counter note: *10~*0: program counter bits @7~@0: pcl bits #11~#0: instruction code address bits s10~s0: stack register bits rev. 1.00 14 de?e??e? 1?? ? 011 rev. 1.00 15 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu stack this is a special part of the memory which is used to save the contents of the program counter only . the stack has 8 levels and is neither part of the data nor part of the program space, and can neither be read from nor written to. the activated level is indexed by the stack pointer , sp , which can also neither be read from nor written to. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allo wing the programmer to use the struct ure more easily . however , when the stack is full, a call subroutine instruction can still be executed which will result in a stack overfow . precautions should be taken to avoid such cases, which might cause unpredictable program branching. arithmetic and logic unit ? alu the arith metic-logic unit or alu is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. connected to the main micro controller data bus, the alu receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register . as these alu calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: ? arithmetic operations add, addm, adc, adcm, sub, subm, sbc, sbcm, daa ? logic operations and, or, xor, andm, orm, xorm, cpl, cpla ? rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc ? increment and decrement inca, inc, deca, dec branch decision jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.00 16 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 17 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu program memory the program memory is the location where the user code or program is stored. for this device, the program memory is mask type. structure the program memory has a capacity of 2k by 16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. t able data, which can be set up i n a ny l ocation wi thin t he progra m me mory, i s a ddressed by separat e t able poi nter registers. special vectors within t he progra m me mory, c ertain l ocations a re re served for spe cial usa ge suc h a s re set a nd interrupts. reset vector this vector is reserved for use by the device reset for program initialis ation. after a device reset is initiated, the program will jump to this location and begin execution. external interrupt vector this vect or is used by the external interrupt. if the external interrupt pin on the device goes low , the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. timer counter 0 interrupt vector this vect or is used by the 8-bit t imer 0. if a overfow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. timer counter 1 interrupt vector this vect or is used by the 8-bit t imer 1. if a overfow occurs, the program will jump to this location and begin execution if the timer interrupt is enabled and the stack is not full. rev. 1.00 16 de?e??e? 1?? ? 011 rev. 1.00 17 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu sima interrupt vector this vect or is used by the sima bus interrupt service program. if the sima bus interrupt resulting from a slave address is matched or if 8 bits of data have been receive d or transmitted successfully from the i 2 c interface, or 8 bits of data have been received or transmitted successful from spi interface, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full. simb interrupt vector this vect or is used by the simb bus interrupt service program. if the simb bus interrupt resulting from a slave address is matched or if 8 bits of data have been receive d or transmitted successfully from the i 2 c interface, or 8 bits of data have been received or transmitted successful from spi interface, the program will jump to this location and begin execution if the interrupt is enabled and the stack is not full. look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. t o use the look-up table, the table pointers are used to setup the address of the data that is to be accessed from the program memory . however , as some devices possess only a low byte table pointer and other devices possess both a high and low byte pointer it should be noted that depending upon which device is used, accessing look-up table data is implemented in slightly different ways. there are two t able pointer registers known as tblp and tbhp in which the lower order and higher orde r a ddress of t he l ook-up da ta t o be re trieved m ust be re spectively fi rst wri tten. t he additional tbhp register allows the complete address of the look-up table to be defined and consequently allow table data from any address and any page to be directly accessed. for this device, after settin g up both the low and high byte table pointers, the table data can then be retrieved from a ny a rea o f pr ogram me mory u sing t he "t abrdc [ m]" i nstruction o r f rom t he l ast p age of the p rogram m emory us ing the " tabrdl [m]" ins truction. when either of thes e ins tructions are executed, the lower order table byte from the program memory will be transferred to the user defned data memory regis ter [m] as specifed in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as "0". rev. 1.00 18 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 1? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu the following diagram illustrates the addressing/data fow of the look-up table. look-up table table program example the following example shows how the table pointer and table data is defned and retrieved from the devices. this example uses raw table data located in the last page which is stored there using the org statement. the value at this org statement is "700h" which refers to the start address of the last page within the 2048x16-bit program memory of the microcontroller . the table pointer is setup here to have an initial value of "06h" this will ensure that the frst data read from the data table will be at the program memory address "706h" or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the frst address of the present page if the "tabrdc[m]" instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the "t abrdl [m]" instruction is executed. instruction table location bits *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] pc10 pc9 pc8 @7 @6 @5 @4 @3 @ ? @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @ ? @1 @0 table location note: *10~*0: current program rom table p10~p8: w rite p12~p8 to tbhp pointer register @7~@0: w rite @7~@0 to tblp pointer register rev. 1.00 18 de?e??e? 1?? ? 011 rev. 1.00 1 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a ,06h ; initialise table pointer - note that this address is referenced mov t blp,a ; to the last page or present page : : tabrdl t empreg1 ; transfers value in table referenced by table pointer to tempregl ; data at prog. memory address "706h" transferred to tempreg1 and tblh dec t blp ; reduce value of table pointer by one tabrdl t empreg2 ; transfers value in table referenced by table pointer to tempreg2 ; data at prog.memory address "705h" transferred to tempreg2 and tblh ; in this example the data "1ah" is transferred to ; tempreg1 and data "0fh" to register tempreg2 ; the value "00h" will be transferred to the high byte register tblh : : org 7 00h ; sets initial address of the last page dc 00 ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary i nformation i s st ored. di vided i nto t wo se ctions, t he fi rst of t hese i s a n a rea of ram where special function registers are located. these registers have fxed locations and are necessary for correct operati on of the device. many of these registers can be read from and written to directly under program control, however , some remain protected from user manipulation. the second area of ram data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. structure the data memory has a bank, known as bank, which is implemented in 8-bit wide ram. the ram data memory is located in bank 0 which is also subdivided into two sections, the special purpose data memory and the general purpose data memory . the length of these sections is dictated by the type of microcontroller chosen. the start address of the ram data memory for all devices is the address "00h" and the last data memory address is "ffh" register s which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. rev. 1.00 ? 0 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 ?1 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ram data memory structure note: most of the data memory bits can be directly manipulated using the set [m].i and clr [m].i with the exception of a few dedicated bits. the data memory can also be accessed through the memory pointer registers. general purpose data memory all microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . it is this area of ram memory that is known as general purpose data memory . this area of data memory is fully accessible by the user program for both read and write operations. by using the "set [m].i" and "clr [m].i" instructio ns individual bits can be set or reset under program control giving the user a lar ge range of fexibility for bit manipulation in the data memory. special purpose data memory this area of data memory , is locat ed in bank, where registers, necessary for the correct operation of the microcontro ller, are stored. most of the registers are both readable and writable but some are protected and are readable only , the details of which are located under the relevant special function register section. note that for locat ions that are unused, any read instruction to these addresses will return the value "00h". special function registers to ensure successful operation of the microcontroller , certain internal registers are implemented in the data memory area. these registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as i/o data control. the location of these registers within the data memory begins at the address "00h". any unused data memory locations between these special function registers and the point where the general purpose memory begins is reserved and attempting to read data from these locations will return a value of "00h". indirect addressing registers ? iar0 the indirect a ddressing registers , ia r0, although having their locations in normal ra m regis ter space, do not a ctually physi cally e xist a s norm al re gisters. t he m ethod of i ndirect a ddressing for ram data manipu lation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding memory pointer , mp0. as the indire ct addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of "00h" and writing to the registers indirectly will result in no operation. rev. 1.00 ?0 de?e??e? 1?? ? 011 rev. 1.00 ? 1 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ?? ? ? ? ?? ??? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - ? ? ?? ?? ? ?? ?? ? ? ? ? ? - ? ?? ? special purpose data memory structure rev. 1.00 ?? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 ?3 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu indirect addressing program example the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. data .section ' data' adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: m ov a,04h ; setup size of block m ov block,a mov a ,offset ad res1 ; a ccumulator l oaded w ith f rst r am ad dress mov m p0,a ; s etup m emory po inter wi th f rst r am a ddress loop: clr i ar0 ; c lear t he d ata a t ad dress d efned b y m p0 i nc mp0 ; increment memory pointer s dz block ; check if last memory location has been cleared jm p loop continue: the important point to note here is that in the example shown above, no reference is made to specifc data memory addresses. memory pointers ? mp0 for all devices, two memory pointers, known as mp0 is provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the releva nt indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. accumulator ? acc the a ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. w ithout the accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he da ta me mory resulting i n highe r program ming and t iming overheads. da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. rev. 1.00 ?? de?e??e? 1?? ? 011 rev. 1.00 ? 3 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu program counter low register ? pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory . by manipulating this register , direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. look-up table registers - tblp, tblh these tw o s pecial function regis ters are us ed to control operation of the look-up table, w hich is stored in the program memory . tblp is the table pointer and indicates the location where the table data is located. its value must be setup before any table read commands are executed. its value can be changed, for example using the "inc" or "dec" instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. watchdog timer register - wdts the w atchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect program memory addresses. t o implement this, a time r is provided within the microcontr oller which will issue a reset command when its value overfows. t o provide variable w atchdog t imer reset times, the w atchdog timer clock source can be divi ded by va rious di vision ratios, the va lue of which is set using the wdts register . by writing directly to this register , the appropriate division ratio for the w atchdog timer clock s ource can be s etup. n ote that only the low er 3 bits are us ed to s et divis ion ratios between 1 and 128. status register ? status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (t o). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller. with the exceptio n of the t o and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the t o or pdf fag. in addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. the t o fag can be af fected only by a system power -up, a wdt time-out or by executing the "clr wdt" or "hal t" instruction. the pdf fag is af fected only by executing the "halt" or "clr wdt" instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. in additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . if the contents of the status registers are important and if the interrupt routine can change the status register, precautions must be taken to correctly save it. rev. 1.00 ? 4 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 ?5 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x unknown bit 7, 6 unimplemented, read as "0" bit 5 to : w atchdog t ime-out fag 0: after power up or executing the "clr wdt" or "halt" instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the "clr wdt" instruction 1: by executing the "halt" instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zero 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. interrupt control register - intc, intch two 8-bit register , known as the intc and intch registers, controls the operation of both external and i nternal t imer i nterrupts. by set ting va rious bi ts wi thin t hese re gisters usi ng sta ndard bi t manipulation i nstructions, t he e nable/disable func tion of t he e xternal a nd t imer i nterrupts c an be independently controlled. a master interrupt bit within this register , the emi bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or of f. this bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the "reti" instruction. note: in situations where other interrupts may require servicing within present interrupt service routines, the emi bit can be manually set by the program after the present interrupt service routine has been entered. timer registers all d evices c ontain t wo 8 -bit t imers wh ose a ssociated r egisters a re k nown a s t mr0 a nd t mr1 which is the location where the associated timer's 8-bit value is located. their associated control registers, known as tmr0c and tmr1c, contain the setup information for these timers. note that all timer registers can be directly written to in order to preload their contents with fxed data to allow different time intervals to be setup. rev. 1.00 ?4 de?e??e? 1?? ? 011 rev. 1.00 ? 5 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu input/output ports and control registers within the area of special function registers, the i/o registers and their associated control registers play a prominent role. all i/o ports have a designated register correspondingly labeled as p a, pb and p c. thes e labeled i/o regis ters are mapped to s pecifc addres ses w ithin the d ata m emory as shown in the data memory table, which are used to transfer the appropriate output or input data on that port. w ith eac h i/o port there is an associated control register labe led p ac, pbc and pcc, also mapped to speci fc addresses wit h the dat a mem ory. the control regi ster speci fes which pins of that port are set as inputs and which are set as outputs. t o setup a pin as an input, the corresponding bit of t he c ontrol re gister m ust be se t hi gh, for a n out put i t m ust be se t l ow. during progra m initialization, it is important to frst setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the i/o ports. one fexible feature of these registers is the ability to directly program single bits using the "set [m].i" and "clr [m]. i" instructions. the ability to change i/o pins from output to input and vice versa by manipulating specifc bits of the i/o control registers during normal program operation is a useful feature of these devices. port c pull-high control register - pcphc port c pull-high control register, pcphc, is used to set the port c pull high function. voice control and audio output registers - dal, dah, vol the devices inclu de a single 12-bit current type dac function for driving an external 8w speaker through an external npn transistor or power amplifer . the programmer must writer the voice data to t hese dal /dah re gisters. t he progra mmer c an c ontrol t he dac vol ume wi th 8-l evels vi a t he vol register. pulse width modulator registers - pwmc, pwml, pwmh each device contains a single 12-bit pwm function for driving an external 8w speaker . the programmer must writer the voice data to pwml/pwmh register . the programmer can control the pwm volume with 9-levels via the vol register. serial interface module (sim) registers - simc0a/b, simc1a/b, simc2a/b, simara/b, simdra/b each sim contains spi and i 2 c function for communicating with other microcontroller or spi flash memory. all devices contain an integrated i 2 c and spi bus which interf aces to the external shared pins sda, scl and scsb, sck, sdi, sdo with pb on the microcon troller. the i 2 c correct setup and data transfer operation of this 2-line bidirectional bus utilizes 4 special function registers. the simara/b register sets the slave address of the device while the simc0a/b is the control register that enables or disables the device as well as select whether it is in i 2 c or spi mode. the simc1a/ b re gister i s t he i 2 c st atus re gister whi le t he simdr a/b re gister i s t he i nput/output da ta re gister. the spi c orrect se tup a nd d ata t ransfer o peration o f t his 3 -line b idirectional b us u tilizes 3 sp ecial function registers. the simc0a/b is the control register that enables or disables the device as well as select wh ether i t i s in i 2 c o r spi m ode. t he si mc2a/b r egister i s t he spi st atus register wh ile t he simdra/b register is the input/output data register. rev. 1.00 ? 6 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 ?7 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu input/output ports holtek m icrocontrollers of fer c onsiderable fe xibility on t heir i/ o port s. w ith t he i nput or out put designation of every pin fully under user program control, pull-high options for all ports and wake- up options on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. depending upon which device or package is chosen, the microcontroller range provides from 15 bidirectional input/output lines labeled with port names p a, pb, pc etc . these i/o ports are mapped to the data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction "mov a,[m]" where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . t o eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor . these pull-high resistors are selectable via confguration or software options and are implemented using a weak pmos transistor . note that if the pull-high option is selected, then all i/o pins on that port will be connected to pull-high resistors, individual pins can be selected for pull-high resistor options. port a wake-up each device has a hal t instruction enabling the microcontroller to enter a power down mode and preserve power , a feature that is important for battery and other low-power applications. v arious methods exis t to w ake-up the microcontroller , one of which is to change the logic condition on one of the port a pins from high to low . after a "hal t" instruction forces the microcontroller into entering a hal t condition, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on port a changes from high to low . this function is especially suitable for applications that can be woken up via external switches. note that each pin on port a can be selected individually to have this wake-up feature. i/o port control registers each i/o port has its own control register p ac, pbc and pcc, to control the input/output configuration. w ith t his c ontrol re gister, e ach cmos out put or i nput wi th or wi thout pul l-high resistor st ructures c an be re configured dyna mically unde r soft ware c ontrol. e ach pi n of t he i/ o ports is directly mapped to a bit in its associated port control register . for the i/o pin to function as an input, the corresponding bit of the control register must be written as a "1". this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a "0", the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register . however , it should be noted t hat t he pro gram wi ll i n fa ct onl y re ad t he st atus of t he out put da ta l atch a nd not t he a ctual logic status of the output pin. rev. 1.00 ?6 de?e??e? 1?? ? 011 rev. 1.00 ? 7 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ? ? ? ? ? pa input/output port ? ? ? ?? ? ?? ? - ?? ? ?? ?? ? ?? ? - ?? ? ?? ?? ? ?? ? - ?? ? ?? ?? ? ?? ? - ?? ? ?? pb input/output port rev. 1.00 ? 8 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 ?? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu pin-shared functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these diffculties can be overcome. for some pins, the chosen fu nction o f t he m ulti-function i/ o p ins i s se t b y c onfguration o ptions wh ile f or o thers t he function is set by application program control. serial interface module the d evice p ins, pb 0~pb3, a re p in-shared wi th p ins sdab , sc lb, scsb , sc kb, sdi b, sdob . the choice of which function is used is selected using the simc0b register. serial interface module the de vice pi ns, pb4~pb7, a re pi n-shared wi th pi ns sdaa, scl a, scsa , scka, sdia, sdoa. the choice of which function is used is selected using the simc0a register. this serial interfa ce module should be selected as spi function which is used for the internal v oice rom access control, and should be left no external connection. i/o pin structures the following diagrams illustrate the i/o pin internal structures. as the exact logical construction of the i/o pin may dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. note also that the specifed pins refer to the lar gest device package, therefore not all pins specifed will exist on all devices. programming considerations within the user program, one of the frst things to consider is port initi alization. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an i nput st ate, t he l evel of whi ch de pends on t he ot her c onnected c ircuitry a nd whe ther pul l-high options have been selected. if the port control registers, p ac, pbc, pcc etc., are then programmed to s etup s ome pins as outputs, these output pins w ill have an initial high output value unles s the associated port data registers, p a, pb, pc etc., are frst programmed. selecting which pins are inputs and which are outputs can be achie ved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "set [m]. i" and "clr [m].i" instructions. note that when using these bit control instructions, a read-modify- write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. read/write timing port a has the additional capability of providing wake-up functions. when the device is in the power down mode, various method s are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. rev. 1.00 ?8 de?e??e? 1?? ? 011 rev. 1.00 ?? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu timers the provision of timers form an important part of any microcontroller , giving the designer a means of carrying out tim e related functio ns. these devices contain two count up timers of 8-bit capacity . the provision of an internal prescaler to the clock circuitry of the timer gives added range to the timer. there are two types of register relat ed to each t imer. the frst is the register that contains the actual value of the timer and into which an initial value can be preloaded. reading from this register retrieves the contents of the t imer. all devices can have the timer clock confgured to come from the internal clock source. ? ? ?? ? ? ? - ? - ??? 8-bit timer structure confguring the timer input clock source the clock source for the 8-bit timers is the system clock divided by four . the 8-bit timer clock source is also frst divided by a, the division ratio of which is conditioned by the three lower bits of the associated timer control register. timer registers - tmr0, tmr1 the time r register s are special function registers located in the special purpose data memory and is the place where the actual timer value is stored. all devices contain two 8-bit timers, whose registers are known as tmr0 and tmr1. the value in the timer registers increases by one each time an internal c lock pul se i s re ceived. t he t imer wi ll c ount from t he i nitial va lue l oaded by t he pre load register to the full count of ffh for the 8-bit timer at which point the timer overfows and an internal interrupt signal is generated. the timer value will then be reset with the initial preload register value and continue counting. note t hat t o a chieve a m aximum ful l ra nge c ount of ffh for t he 8-bi t t imer, t he pre load re gisters must frst be clear ed to all zeros. it should be noted that after power -on, the preload registers will be in an unknown condition. note that if the t imer counters are in an off condition and data is written to their preload registers, this data will be immediately written into the actual counter . however , if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overfow occurs. note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however , as this may result in certain timing errors, programmers must take this into account. rev. 1.00 30 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 31 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu timer control registers - tmr0c, tmr1c each tim er has its respective timer control register , known as tmr0c and tmr1c. it is the timer control register together with their corresponding timer registers that control the full operation of the timers. before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. bits 7 and 6 of the t imer control register , must be set to the required logic levels. bit 6 of the registers must always be written with a "1", and bit 7 must always be wr itten wi th a "1". t he t imer-on b it, wh ich i s b it 4 o f t he t imer c ontrol r egister a nd k nown as t0on/t1on, depending upon which timer is used, provides the basic on/of f control of the respective timer . setting the bit high allows the timer to run, clearing the bit stops the timer . for the 8-bit timers, which have prescalers, bits 0~2 of the t imer control register determines the division ratio of the input clock prescaler. ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - ? ? ? ?? ? ?? timer control register (n=0 or 1) rev. 1.00 30 de?e??e? 1?? ? 011 rev. 1.00 31 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu confguring the timer the t imer is used to measure fxed time intervals, providing an intern al interrupt signal each time the t imer overfows. t o do this the operating mode select bit pair in the t imer control register must be set to the correct value as shown. control register operating mode select bits bit7 bit6 1 0 the internal clock, f sys , is used as the t imer clock. however , this clock source is further divided by a prescaler , the value of which is determined by the prescaler rate select bits, which are bits 0~2 in the t imer control register . after the other bits in the t imer control register have been setup, the enable bit, which is bit 4 of the t imer control register , can be set high to enable the t imer to run. each time an internal clock cycle occurs, the t imer increments by one. when it is full and overfows, an interrupt signal is generated and the t imer will reload the value already loaded into the preload register and continue counting. the interrupt can be disable d by ensuring that the t imer interrupt enable bit in the interrupt control register, intc, is reset to zero. timer mode timing diagram prescaler all of the 8-bit timers possess a prescaler . bits 0~2 of their associated timer control register , defne the pre-scaling stages of the internal clock source of the t imer. the t imer overfow signal can be used to generate signals for the t imer interrupt. programming considerations the inter nal system clock is used as the timer clock source and is therefore synchronized with the overall operation of the microcontro ller. in this mode, when the appropriate timer register is full, the microcontroller will generate an inte rnal interrupt signal directing the program fow to the respective internal interrupt vector. when t he t imer i s r ead, t he c lock i s b locked t o a void e rrors, h owever a s t his m ay r esult i n a counting error , this should be taken into account by the programmer . care must be taken to ensure that the timers are properly initialized before using them for the first time. the associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remai n inactive. the edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly confgured for the required application. it is also important to ensure that an initia l value is frst loaded into the timer registers before the timer is switched on; this is because after power -on the initial values of the timer registers are unknown. after the timer has been initialized the tim er can be turned on and of f by controlling the enable bit in the timer control register. rev. 1.00 3 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 33 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu timer program example the following example program section is based on the device, which contain two 8-bit timers. programming t he t imer f or o ther d evices i s c onducted i n a v ery si milar wa y. t he p rogram sh ows how the timer registers are setup along with how the interrupts are enabled and managed. points to note in the examp le are how , for the 8-bit timer . note how the timer is turned on by setting bit 4 of the respective timer control regis ter. the timer can be turned of f in a s imilar w ay by clearing the same bit. this example program sets the timer to be in the timer mode which uses the internal f sys as their clock source, and produce a timer 0 interrupt per 1ms. jmp t mr0int ; j ump h ere w hen t imer 0 o verfows e very 1 ms mov tmr0,a ; fo w b yte m ust b e s etup b efore h igh b yte rev. 1.00 3? de?e??e? 1?? ? 011 rev. 1.00 33 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu time base the t ime base function will generate a regular interrupt signal synchronised to the system clock which can be used by the application as a time base signal. time base operation the t ime base operation is a very simple function for the generation of a regular time signal. this is implem ented by generating a regular interrupt signal whose enable/d isabled and request fags are in the intc register . the clock source for the time bas e is the internal f sys /4 clock source, which is t hen di vided i nternally by a va lue of 1024. it i s t his di vided si gnal t hat ge nerates t he i nternal interrupt. the t ime base interrupt is enabled by the etbi bit in the intc register and interrupt request fag is the tbf fag in the same register . a time base of 1ms will therefor be generated from a system clock of 4mhz and a time base of 0.5ms will be generated from a system clock source of 8mhz. time base example the following example program section is based on the device. the program shows how the t ime base registers are setup along with how the interrupts are enabled and managed. the points to note in the example are how the t ime base is turned on by setting bit 4 of the intc register . the t ime base can be turned of f in a similar way by clearing the same bit. this example program sets the time base which uses the internal system clock as their clock source, and produces a time base interrupt every 0.5ms from a system source clock of 8mhz. jmp time_base_int ; j ump h ere wh en t ime b ase o verfows p er 0 .5ms rev. 1.00 34 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 35 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu serial interface the device contains both spi and i 2 c serial interface functions, which allows two methods of easy communication with external peripheral hardware. as the spi and i 2 c function share the same external pins and internal regis ters their function must first be chosen by s electing the correct confguration option. spi interface the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. spi interface operation the spi interface is a full duplex synchronous serial data link. communication betw een devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemente d by the master . multiple slave devices can be connected to the spi serial bus with each device controlled using its slave select line. the spi is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi inter face pins are pin-shared with segment pins and with the i 2 c function pins, the spi interface must frst be enabled by selecting the correct confgurati on option. after the spi confguration option has been selected it can then also be selected using the simen bit in the simc0 register. the spi function in this device offers the following features: ? full duplex synchronous data transfer ? both master and slave modes ? lsb frst or msb frst data transmission modes ? transmission complete fag several other confguration options also exist to setup various spi interface options as follows: ? spi pin enabled ? wcol bit enabled or disabled ? csen bit enabled or disabled rev. 1.00 34 de?e??e? 1?? ? 011 rev. 1.00 35 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu the status of the spi interface pins is determined by a number of fact ors, whether the device is in master or slave mode and upon the condition of certain control bits such as csen and simen. ? ? ? ? ? ? ? ?? ? ? - ?? ? ? ?? ? ? ??? ? ? ? ? ? ? ?? ? ? ? ?? ? ? ? ? ? ? ? ? ? ?? ?? ? ? ? ? ??? ?? ? ?? ? ? ? ?? ? ? ? ? ? ? block diagram master/salve (simen=0) master (=1) slave (=1) csen=1 csen=0 csen=0 scs line=0 (csen=1) scs line=1 (csen=1) scs z l z z i ? z i ? z sdo z o o o o z sdi z i ? z i ? z i ? z i ? z z sck z l(cpol=1) h(cpol=0) l(cpol=1) h(cpol=0) i ? z i ? z z "z" foating, "h" output high, "l"output low, "i"input, "o" output level, "i,z" input foating (no pull-high) spi interface pin status rev. 1.00 36 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 37 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu spi registers the sim dr a /b regis ter is used to store the data being trans mitted and received. there are tw o control registers associated with the spi interface, simc0 a/b and simc2 a/b and one data register known as simdra/b. the simc1 a/b register is not used by the spi function. register simc0 a/b is used to control the enable/disable function, the power down control and to set the data transmission clock frequency . register simc2 a/b is used for other control functions such as lsb/ msb selection, write collision fag etc. the following gives further explanation of each bit: ? simen a/b the a/ b bi t i s t he ove rall on/ off c ontrol for t he spi i nterface. w hen t he a/ b bi t i s c leared t o zero t o di sable t he spi i nterface, t he sdi, sdo a/ b, sck a/ b a nd scs a/ b l ines wi ll be i n a foating condition and the spi operating current will be reduced to <0.1ma at 5v . when the bit is high the spi inter face is enabled. note that when the simen a/b bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be initialised by the application program. ? sim0 a/b~sim2 a/b these three bits control the master/slave selection and also setup the spi interface clock speed when in the master mode. the spi clock is a function of the system clock whether it be rc type or crystal type. if the slave mode is selected then the clock will be supplied by the external master device. the following gives further explanation of each bit: ? trf a/b the t rf a/ b b it i s t he t ransmit/receive c omplete f lag a nd i s c leared b y t he a pplication program and can be us ed to generate an interrupt. when the bit is high the data has been transmitted or rec eived. if t he bi t i s l ow t he da ta i s be ing t ransmitted or ha s not ye t be en received. ? wcol a/b the wcol a/b bit is used to detect if a data collision has occurred. if this bit is high it means that da ta ha s be en a ttempted t o be wri tten t o t he smdr a/ b re gister duri ng a da ta t ransfer operation. t his wr iting o peration wi ll b e i gnored i f d ata i s b eing t ransferred. t he b it c an b e cleared by t he a pplication progra m. not e t hat usi ng t he cse n a/ b bi t c an be di sabled or enabled via confguration option. ? csen a/b the csen a/b bit is used as an on/of f control for the scs a/b pin. if this bit is low then the scs a/b pin will be disabled and placed into a foating condition. if the bit is high the scs a/b pin will be enabled and used as a select pin. ? mls a/b the ml s a/ b i s use d t o se lect how t he da ta i s t ransferred, e ither msb or lsb first. set ting the bit high wil l sel ect msb first and low for lsb first. note t hat t he simc2 a/ b regi ster i s t he sa me as t he simar a/ b regi ster use d by t he i 2 c interface. rev. 1.00 36 de?e??e? 1?? ? 011 rev. 1.00 37 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? spi communication after the spi interface is enabled by setting the simen a/b bit high, then in the master mode, when data is written to the simdr a/b register , transmission/reception will begin simultaneously. when the data transfer is complete, the trf a/b fag will be set automatically. in the slave mode, when the clock signal from the master has been received, any data in the simdr register will be transmitted and any data on the sdi a/b pin will be shifted into the simdr a/b register. the master should output an scs a/b signal before a clock signal is provided and slave data transfers should be enabled/disabled before/after an scs a/b signal is received. ? ? ? ? ? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ? ? ? spi master mode timing ? ? ? ? ??? ? - ? ? ?? spi slave mode timing - ckeg=0 rev. 1.00 38 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 3? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ??? ? ? ? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ? ? ? ?? ?? ?? ? ? ?? ?? ??? ? ?? ? ? ? ? ? ? ?? spi slave mode timing - ckeg=1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - ? ? ? ? ? ? spi control register - simc0a/b ? ? ? ? ? ? ? ? ? - ? ? ? ? ? ? ?? ? ?? ?? ? ?? ? ?? ? spi control register - simc2a/b rev. 1.00 38 de?e??e? 1?? ? 011 rev. 1.00 3 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ? ? ? ? ? ?- ?? ?? ? ? ??? ????? ?? ?? ?? ? ? spi transfer control flowchart rev. 1.00 40 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 41 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu i 2 c interface the i 2 c b us i s a b idirectional 2 -line c ommunication i nterface o riginally d eveloped b y ph ilips. the possibility of transmitting and receiving data on only 2 lines of fers many new application possibilities for microcontroller based applications. i 2 c interface operation as the i 2 c interfa ce pins are pin-shared with segment pins and with the spi function pins, the i 2 c interface must frst be enabled by selecting the correct confguration option. there are two lines associated with the i 2 c bus, the frst is known as sda and is the serial data line, the second is known as scl line and is the serial clock line. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pul l-high resist ors are conne cted to these out puts. note that no chip sel ect li ne exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two device s communicate with each other on the bidirectional i 2 c bus, one is known as the master de vice a nd one a s t he sl ave de vice. bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, i t i s t he m aster de vice t hat ha s ove rall c ontrol of t he bus. for t his de vice, wh ich onl y operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. i 2 c registers there are three control registers associated with the i 2 c bus, simc0a/b, simc1a/b and simara/ b and one data register, simdra/b. the simdra/b register is used to store the data being transmitted and received on the i 2 c bus. before t he m icrocontroller wr ites d ata t o t he i 2 c b us, t he a ctual d ata t o b e t ransmitted m ust b e placed in the simdra/b register . after the data is received from the i 2 c bus, the microcontroller can read it from the simdra/b register. any transmission of data to the i 2 c bus or reception of data from the i 2 c bus must be made via the simdra/b register. the simara/b register is the locat ion where the slave address of the microcontroller is stored. bits 1~7 of the simara/b register defne the microcontroller slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the simara/b register, the microcontroller slave device will be selected. note t hat t he simara/ b re gister i s t he sam e re gister a s simc2a/ b whi ch i s use d by t he spi interface. the simc0a/b register is used for the i 2 c overall on/off control. ? slave address register - simara/b rev. 1.00 40 de?e??e? 1?? ? 011 rev. 1.00 41 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i 2 c control register - simc0a/b ? ? ? ? ? ? ? ? ? ? -? ? -??? ? ? ?? ? - ? ?? ? ? ??? ? ?? ??? ? ??? ? ? ? ? i 2 c control register - simc1a/b rev. 1.00 4 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 43 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu i 2 c confguration option there are several configuration options associated with the i 2 c interface. one of these is to enable the rnica/b bit function which selects the rnica/b bit in simc1a/b register . another confguration option determines the debounce time of the i 2 c interface . this add a debounce delay time to the external clock to reduce the poss ibility of glitches on the clock line caus ing erroneous operation. the debounce time if selected can be chosen to be either 1 or 2 system clocks. the following gives further explanation of each bit: ? simena/b the simena/b bit determines if the i 2 c bus is enabled or disabled. if data is to be transferred or received on the i 2 c bus then this bit must be set high. the following gives further explanation of each bit: ? hcfa/b the hcf a/b fag is the data transfer fag. this fag will be zero when data is being transferred. upon completion of an 8-bit data transfer the fag will go high and an interrupt will be generated. ? hassa/b the hassa/b fag is the address match fag. this fag is used to dete rmine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low. ? hbba/b the hbba/b fag is the i 2 c busy fag. this fag will be high when the i 2 c bus is busy which will occur when a st art signal is detec ted. the fag will be reset to zero when the bus is free which will occur when a stop signal is detected. ? htxa/b the htxa/b fag is the transmit/receive mode bit. this fag should be set high to set the transmit mode and low for the receive mode. ? txaka/b the txaka/b fag is the transmit acknowledge fag. after the receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock. t o continue receiving more data, this bit has to be reset to zero before further data is received. ? srwa/b the sr wa/b b it i s t he sl ave r ead/write b it. t his b it d etermines wh ether t he m aster d evice wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address match, that is when the haasa/b bit is set high, the device will check the sr wa/b bit to determ ine whether it should be in transmit mode or receive mode. if the sr wa/b bit is high, the master is requesting to read data from the bus, so the device should be in transmit mode. when the sr wa/b bit is zero, the master will write data to the bus, therefore the device should be in receive mode to read this data. ? rnica/b the rnica/b bit is used as i 2 c running clock from internal or external clock. if this bit is low then i 2 c runni ng usi ng i nternal c lock a nd i t wi ll not wa ke-up whe n i 2 c i nterrupts i n t he powe r down mode. if the bit is high i 2 c running using external clock and it will wake-up when i 2 c interrupts in the power down mode. rev. 1.00 4? de?e??e? 1?? ? 011 rev. 1.00 43 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? rxaka/b the rxaka/b fag is the receive acknowledge fag. when the rxaka/b bit has been reset to zero it means that a correct acknow ledge s ignal has been received at the 9th clock, after 8 bits of data have been transmitted. when in the transmit mode, the transmitter checks the rxaka/ b bit to determine if the receiver wishes to receive the next byte. the transmitter will therefore continue sending out data until the rxaka/b bit is set to "1". when this occurs, the transmitter will release the sdaa/b line to allow the master to send a stop signal to release the bus. i 2 c bus communication communication on the i 2 c bus requires four separate steps, a st art signal, a slave device address transmission, a data transmission and fnally a st op signal. when a st art signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the microcontroller matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the microcontroller slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer . during a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the sr w bit. this bit will be checked by the mic rocontroller to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 write the slave address of the microcontroller to the i 2 c bus address register simar. step 2 set the simen bit in the simc0 register to "1" to enable the i 2 c bus. step 3 set the ehi bit of the interrupt control register to enable the i 2 c bus interrupt. rev. 1.00 44 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 45 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ? ? ? - ? - ? ? i 2 c communication timing diagram ? start signal the st art signal can only be generated by the master device connected to the i 2 c bus and not by the microcontroller , which is only a slave device. this st art signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a st art condition occurs when a high to low transition on the sda line takes place when the scl line remains high. ? slave address the t ransmission o f a st art si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he i 2 c bus. t o determine which slave device the master wishes to communica te with, the address of the slave device will be sent out immediately following the st art signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt s ignal w ill be generated. the next bit follow ing the addres s, w hich is the 8th bit, defnes the read/write status and will be saved to the sr w bit of the simc1 register . the device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the microcontroller slave device will also set the status fag haas when the addresses match. as a n i 2 c b us i nterrupt c an c ome f rom t wo so urces, wh en t he p rogram e nters t he i nterrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matchin g slave address or from the completion of a data byte transfer . when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simdr register, or in the receive mode where it must implement a dummy read from the simdr register to release the scl line. rev. 1.00 44 de?e??e? 1?? ? 011 rev. 1.00 45 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? srw bit the sr w bi t i n t he simc1 regi ster de fines whe ther t he m icrocontroller sl ave de vice wi shes to r ead d ata f rom t he i 2 c b us o r wr ite d ata t o t he i 2 c b us. t he m icrocontroller sh ould e xamine this bit to determi ne if it is to be a transmitter or a receiver . if the sr w bit is set to "1" then this indicates that the master wishes to read data from the i 2 c bus, therefore the microcontroller slave device must be setup to send data to the i 2 c bus as a transmitter . if the sr w bit is "0" then this indicates t hat t he m aster wi shes t o se nd da ta t o t he i 2 c bu s, t herefore t he m icrocontroller sl ave device must be setup to read data from the i 2 c bus as a receiver. ? acknowledge bit after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. this acknowledge signal will inform the master that a slave device has acce pted its calling address. if no acknowledge signal is received by the master then a st op signal must be transmitted by the master to end the communication. when the haas bit is high, the addresses have matched and the micro controller slave device must check the sr w bit to determine if it is to be a transmitter or a re ceiver. if t he sr w bi t i s hi gh, t he m icrocontroller sl ave de vice shoul d be se tup t o be a transmitter so the htx bit in the simc1 register should be set to "1" if the sr w bit is low then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". ? data byte the t ransmitted d ata i s 8 -bits wi de a nd i s t ransmitted a fter t he sl ave d evice h as a cknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before i t c an re ceive t he ne xt da ta byt e. if t he t ransmitter doe s not re ceive a n a cknowledge bi t signal from the receiver , then it will release the sda line and the master will send out a st op signal to release control of the i 2 c bus. the corresponding data will be stored in the simdr register. if setup as a transmitter , the microcontroller slave device must frst write the data to be transmitted into the simdr register . if setup as a receiver , the microcontroller slave device must read the transmitted data from the simdr register. data timing diagram ? receive acknowledge bit when the receiver wishes to continue to receive the next data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the microcontro ller slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a st op signal from the master. rev. 1.00 46 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 47 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? i 2 c bus isr flow chart ? ? ? ? ? ? ? - ? ? ? ? ? ?? - ? ? - ? i 2 c bus initialisation flow chart rev. 1.00 46 de?e??e? 1?? ? 011 rev. 1.00 47 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu voice rom access the device provides two serial interface modules, called sima and simb. sima is dedicated to access the internal voice rom while simb can be used as an independent spi or i 2 c function to communicate with external devices. as sima communicates with the v oice rom using its spi interface, it must be setup to activate the spia function by the simc0a register . the pb4~pb7 pins are pin shared with the spia interface, sdoa, scka, sdia and scsa pins respectively . in order not to interfere spia function, the pin-shared i/o pins, pb4~pb7, should be set as input pins using the applic ation program, while pb5, pb6 and pb7 should also have pull high resistors enabled using confguration option. the accompan ying diagram illustrates the spi interface with the v oice rom block diagram. voice rom sdoa sdia scka scsa spi to voice rom interface sima spi interface with voice rom voice rom spi modes the device provides the spi mode 0 and mode 3 to access the interna l voice rom. the dif ference between these two modes is the setting on the spi clock edge and polarity selections. the designer should follow the v oice rom spi modes to select the spia clock pin, namely scka, input edge and polarity by the ckpola and ckega bits in the simc2a register . the following diagram illustrates the timing diagram. rev. 1.00 48 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 4? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu voice rom read commands the de vice ha s re ad a nd f ast_read c ommands t o a ccess da ta from t he i nternal v oice rom. the read comm and code is "03h" while the f ast_read command code is 0bh. both of the read and fast_read commands can be used to read one byte or bulk data from the v oice rom. the f ast_read command is used to access the v oice rom data using a higher speed spi clock rate. the clock rate can be up to 85mhz, however , as the maximum system clock is 12mhz, these two commands will have the same performance. read command the rea d command is us ed to read data from the v oice ro m. the addres s is latched on the rising edge of the spi clock pin, namely scka, and the data will be shifted out on the falling edge of scka. the first address byte can point to any location in the v oice rom. the address is automatically incremented to the next address after each byte data is shifted out, so the whole memory can be read out using a single read command. the address will roll over to 0 when the highest address has been reached. the accompanying fowchart and diagram illustrate the read data command setting procedure and the timing diagram. clear scsab pin =0 send read command code = 03 to sdoa pin send 3 bytes address to sdoa pin read data on sdia pin set scsab pin = 1 read command procedure end read command procedure rev. 1.00 48 de?e??e? 1?? ? 011 rev. 1.00 4 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu scsa scka sdoa sdia ?1???3 01?3 0 1 ? 3 4 5 6 7 8 ? 10 ?8 ?? 30 31 3? 33 34 35 36 37 38 3? ?4 - bit address command 01?3 56 7 4 data out ? data out 1 msb msb hign - z 03 7 read command procedure timing diagram fast_read command the f ast_read command provides a higher speed to access the v oice rom data. the address is latched on the rising edge of the s pi clock pin, namely s cka, and each bit of the data w ill be shifted out on the falling edge of scka. the frst address byte can point to any location in the voice rom. the address is automatically incremented to the next address after each byte data is shifted out, so the whole memory can be read out by a single f ast_read command. the address will roll over to 0 when the highest address has been reached. the accompanying fowchart and diagram illustrate the fast_read data instruction setting procedure and the timing diagram. clear scsab pin =0 send fast _read command code = 0bh to sdoa pin send 3 bytes address to sdoa pin send 1 byte dummy byte address to sdoa pin set scsab pin = 1 fast_read command procedure end read data on sdia pin fast_read command procedure rev. 1.00 50 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 51 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu scsa scka sdoa sdia 46 47 command 01?3 56 7 4 data out ? data out 1 msb msb 7 scsa scka sdoa sdia ?1???3 01?3 0 1 ? 3 4 5 6 7 8 ? 10 ?8 ?? 30 31 ?4 - bit address command hign - z 0 b 3? 33 34 35 36 37 38 3? 40 41 4? 43 44 45 567 01?3 4 567 01?3 4 msb fast_read command procedure timing diagram voice output the device contains an internal 12-bit dac function which can be used for audio signal generation. voice control two internal registers dal and dah contain the 12-bit digital value for conversion by the internal dac. there is also a dac enable/disable control bit in the pwmc control register for overall on/ off control of the dac circuit. if the dac circuit is not enabled, the dah/dal value outputs will be invalid. w riting a "1" to the dac bit in bit1 of pwmc will enable the enable dac circuit, while writing a "0" to the dac bit will disable the dac circuit. audio output and volume control - dal, dah, vol the audio output is 12-bits wide whose highest 8-bits are written into the dah register and whose lowest four bits are written into the highest four bits of the dal register . bits 0~3 of the dal register are always read as zero. there are 8 levels of volume which are setup using the vol register. only the lowest 3-bits of this register are used for volume control. ? ? ? ? ?? -? ? -? ? -? ? rev. 1.00 50 de?e??e? 1?? ? 011 rev. 1.00 51 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu vol[2:0] dac volume control 111 high volu ? e low volume 110 101 100 011 010 001 000 pulse width modulation output oo ghlfhv lfoxgh d vljoh elw 3:0 ixfwlr zklfk fd gluhfwo gulh h[whudo dxglr frpsrhwv vxfk dv vshdnhuv pulse width modulator operation 7kh 3:0 rxwsxw lv surlghg r wzr frpsolphwdu rxwsxwv r wkh 3:0 dg 3:0 slv surlglj d gli ihuhwldo rxwsxw sdlu dg wkxv fdsdeoh ri kljkhu gulh srzhu 7khvh wzr slv fd gluhfwo gulh d slh]r ex]]hu ru d rkp vshdnhu zlwkrxw xvlj h[whudo frpsrhwv 7kh 3:0 rxwsxwv f d d ovr eh xvh g vl joh h ghg zkh uh w kh vl jdo l v sur lghg r w kh 3: 0 rx wsxw d g djdl fd dovr eh xvhg e lwvhoi dorh wr gulh d slh]r ex]]hu ru d rkp vshdnhu zlwkrxw h[whudo frpsrhwv 7klv vljoh hg rxwsxw gulh wsh lv fkrvh xvlj wkh 6,1*/(b3:0 elw l wkh 3:0& uhjlvwhu ,i wkh 06b6,*1 elw lv orz wkh wkh vljdo wkdw lv surlghg r 3:0dg 3:0 zloo rewdl d *1 ohho rowdjh diwhu vhwwlj wkh 3:0&& elw kljk ,i wkh 06b6,*1 elw lv kljk wkh wkh vljdo wkdw lv surlghg r 3:0 dg 3:0 zloo kdh d *1 ohho rowdjh zkh wkh 3:0&& elw lv vhw kljk 7kh wzr 3:0 rxwsxwv zloo llwldoo eh dw orz ohhov dg li wkh 3:0 ixfwlr lv vwrsshg zloo dovr uhwxu wr d orz ohho ,i wkh 3:0&& elw fkdjhv iurp orz wr kljk wkh wkh 3:0 ixfwlr zloo vwduw uxlj dg odwfk hz gdwd ,i wkh gdwd lv rw xsgdwhg wkh wkh rog doxh zloo uhpdl ,i wkh 3:0&& elw fkdjhv iurp kljk wr orz dw wkh hg ri wkh gxw ffoh wkh 3:0 rxwsxw zloo vwrs vol[3:0] pwm volume control 1xxx high volu ? e low volume 0111 0110 0101 0100 0011 0010 0001 0000 rev. 1.00 5 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 53 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ?? ? ? ? ? ? ??? ? ??? ? ? ?? ?? ? - ? ? ? ? ? ? ? ? ? ? ? ? pulse width modulator control register rev. 1.00 5? de?e??e? 1?? ? 011 rev. 1.00 53 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu interrupts interrupts a re a n i mportant p art o f a ny m icrocontroller sy stem. w hen a n i nternal f unction su ch a s a t ime base or t imer requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. each device contains a t ime base interrupt and two internal timer interrupt functions. t he t ime ba se i nterrupt i s c ontrolled by bi t 1 of int c re gister, whi le t he i nternal interrupt is controlled by the t imer counter overfow. ? ? ? ? ? ? ? ? ? ? ? ? - ? - ? - ? ? ? ? interrupt structure interrupt register overall interrupt control, which means interrupt enabling and fag setting, is controlled using two registers, known as intc and intch, which are located in the data memory . by controlling the appropriate enable bits in these registers each individual interrupt can be enabled or disabled. also when an interrupt occurs, the corresponding request flag will be set by the microcontroller . the global enable fag if cleared to zero will disable all interrupts. ? ? ? interrupt control register rev. 1.00 54 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 55 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ? ? ? ? ? ? intch register interrupt operation a t imer or t ime ba se ove rfow or by se tting t heir c orresponding re quest fa g, i f t heir a ppropriate interrupt enable bit is set. when this happens , the program counter , w hich stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . the microcontroller will then fetch its next instruction from this interrupt vector . the instruction at this ve ctor wi ll usua lly be a jmp st atement whi ch wi ll t ake progra m e xecution t o a nother se ction of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a reti statement, which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagram with their order of priority. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the emi bit will be cleared automatically . this will prevent any further interrupt nesting from occurring. however , if other interrupt requests occur during this interval, although the inter rupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. rev. 1.00 54 de?e??e? 1?? ? 011 rev. 1.00 55 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu interrupt priority interrupts, occurri ng in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in case of simultaneous requests, the accompanying table shows the priority that is applied. interrupt source interrupt vector HT83B60 priority time base interrupt 04h 1 timer 0 overfow 08h ? timer 1 overfow 0ch 3 sim a interrupt 10h 4 sim b interrupt 14h 5 suitable masking of the individual interrupts using the intc and intch registers can prevent simultaneous occurrences. time base interrupt each device contains a t ime base whose corresponding interrupt enable bits are known as etbi and is located in the intc register . for a t ime base generated interrupt to occur , the corresponding time base interrupt enable bit must be frst set. t ime base also has a corresponding t ime base interrupt request fag, which is known as tbf , also located in the intc register . when the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overfows a subroutine call to the corresponding t ime base interrupt vector will o ccur. t he c orresponding pr ogram me mory v ector l ocations f or t he t ime b ase i s 0 4h. af ter entering the interrupt execution routine, the corresponding interrupt request fag, tbf will be reset and the emi bit will be cleared to disable other interrupts. timer interrupt for a timer generated interrupt to occur , the corresponding timer interrupt enable bit must be frst set. each device contains two 8-bit timers whose corresponding interrupt enable bits are known as et0 and et1and are located in the intc register . each timer also has a corresponding timer interrupt request fag, which are known as t0f and t1f , also located in the intc register . when the master interrupt and corresponding timer interrupt enable bits are enabled, the stack is not full, and when the corresponding timer overfows a subroutine call to the corresponding timer interrupt vector will occur . the corresponding program memory vector locations for t imer 0 and t imer1 are 08h and 0ch . a fter entering the interrupt execution routine, the corres ponding interrupt reques t f ags, t0f or t1f will be reset and the emi bit will be cleared to disable other interrupts. serial interface module - sim - interrupt sima/b interrupt s include both the spi and i 2 c interrupts. the sima/b mode is determined by the sim2a/b, sim1a/b and sim0a/b bits in the simc0a/b register. for a spi i nterrupt t o o ccur, t he g lobal i nterrupt e nable b it, e mi, a nd t he c orresponding si ma/ b interrupt enable bit, esii, must be frst set. the simena/b bit in the simc0a/b register must also be set. an actual spi interrupt will take place when the fag, sif a/b, is set, a situation that will occur when 8-bits of data are transferred or received from either of the spi interfaces. when the interrupt is enabled, the stack is not full and an sima/b interrupt occurs, a subroutine call to the sima/b interrupt vector at location 10h, will take place. when the interrupt is serviced, the spia/ b interrupt request fag, sif a/b, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. rev. 1.00 56 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 57 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu for an i 2 c interrupt to occur , the corresponding interrupt enable bit esiia/b must be frst set. an actual i 2 c int errupt wi ll be ini tialized when the sima/ b int errupt reque st flag, sif a/b, is se t, a situation that will occur when a matching i 2 c slave address is received or from the completion of an i 2 c data byte transfer . when the inter rupt is enabled, the stack is not full and a sima/b interrupt occurs, a su broutine c all t o t he si ma/b i nterrupt v ector a t l ocation 1 4h, wi ll t ake p lace w hen a n i 2 c interrupt occurs, the interrupt request fag sifa/b will be reset and the emi bit will be cleared to disable other interrupts. programming considerations by disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request fag is set, it will remain in this condition in the intc or intch register until the corresponding inte rrupt is serviced or until the request fag is cleared by a software instruction. it is recommended that programs do not use the "call subroutine" instruction within the interrupt subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a "call subroutine" is executed in the interrupt subroutine. all of these interrupts have the capability of waking up the processor when in the power down mode. only t he program counte r i s pushed ont o t he sta ck. if t he c ontents of t he re gister or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller . in this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and ready to execute t he fr st p rogram i nstruction. af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in a ddition t o t he p ower-on r eset, si tuations m ay a rise wh ere i t i s n ecessary t o f orcefully a pply a reset condition when the microcontroller is running. one example of this is where after power has be en a pplied a nd t he m icrocontroller i s a lready ru nning, t he res l ine i s fo rcefully pu lled l ow. in such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the w atchdog t imer overfows and resets the microcontroller. all types of reset operations result in different register conditions being setup. rev. 1.00 56 de?e??e? 1?? ? 011 rev. 1.00 57 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu reset functions there are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally. power-on reset the m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s frst a pplied t o the microcontroller . as well as ensuring that the program memory begins execution from the frst memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. although t he m icrocontroller ha s a n i nternal rc re set func tion, i f t he v dd powe r suppl y ri se t ime is not fas t enough or does not s tabilise quickly at pow er-on, the internal res et function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay , normal operation of the microcontroller will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the microcontroller will begin normal operation. the abbreviation sst in the fgures stands for system start-up t imer. power-on reset timing chart for most applicati ons a resistor connected between vdd and the res pin and a capacitor connected between v ss and the res pin will provide a suitable external reset circ uit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. basic reset circuit for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. enhanced reset circuit more information regarding external reset circuits is located in application note ha0075e on the holtek website. rev. 1.00 58 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 5? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu res pin reset this type of reset occurs when the microcontroller is already running and the res pin is forcefully pulled low by exte rnal hardware such as an external switch. in this case as in the case of other reset, the program counter will reset to zero and program execution initiated from this point. res reset timing chart watchdog time-out reset during normal operation the w atchdog time-out reset during normal operation is the same as a hardware res pin reset except that the w atchdog time-out fag t o will be set to "1". wdt time-out reset during normal operation timing chart watchdog time-out reset during power down the w atchdog time-out reset during power down is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the t o fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during power down timing chart reset initial conditions the dif ferent types of reset described af fect the reset fags in dif ferent ways. these fags, known as p df and t o are located in the s tatus register and are controlled by various microcontroller operations, such as the power down function or w atchdog t imer. the reset fags are shown in the table: to pdf reset conditions 0 0 res reset during power-on u u res or lvr reset during normal operation 1 u wdt time-out reset during normal operation 1 1 wdt time-out reset during power down note: "u" stands for unchanged rev. 1.00 58 de?e??e? 1?? ? 011 rev. 1.00 5 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clea ? afte ? ? eset ? wdt ? egins ? ounting ti ? e ? all timer will be turned off prescaler the timer prescaler will be cleared input/output ports i/o ports will be setup as inputs stack pointer stack pointer will point to the top of the stack the dif ferent kinds of resets all af fect the internal registers of the microcontroller in dif ferent ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. register reset (power-on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out from halt mp0 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u acc x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u pcl 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tblp x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u tblh x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u wdts 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 u u u u u u u u status - - 0 0 x x x x 1 u u u u u u u u u u u 0 1 u u u u 1 1 u u u u intc - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u tmr0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u tmr0c 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 u u u u u u u u tmr1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u tmr1c 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 u u u u u u u u pa 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pac 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pbc 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 u u u u u u u u pc - 1 1 1 1 1 1 1 1 1 1 1 1 u u u pcc - 1 1 1 1 1 1 1 1 1 1 1 1 u u u intch - - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u dal x x x x u u u u u u u u u u u u u u u u dah x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u pwmc 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u pwml x x x x u u u u u u u u u u u u u u u u pwmh x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u vol x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u u u u simc0a 1 1 1 x x x 0 1 1 1 x x x 0 1 1 1 x x x 0 1 1 1 x x x 0 u u u x x x u simc1a 1 0 0 x x 0 x 1 1 0 0 x x 0 x 1 1 0 0 x x 0 x 1 1 0 0 x x 0 x 1 u u u x x u x u simdra x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x simara/ simc2a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u simc0b 1 1 1 x x x 0 1 1 1 x x x 0 1 1 1 x x x 0 1 1 1 x x x 0 u u u x x x u simc1b 1 0 0 x x 0 x 1 1 0 0 x x 0 x 1 1 0 0 x x 0 x 1 1 0 0 x x 0 x 1 u u u x x u x u simdrb x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x simarb/ simc2b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u pcphc - 0 0 0 0 0 0 0 0 0 0 0 0 u u u note: "u" stands for unchanged "x" stands for unknown "-" stands for undefned rev. 1.00 60 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 61 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu oscillator various oscillator options of fer the user a wide range of functions according to their various application requirements. three types of system clocks can be selecte d while various clock source options fo r t he w atchdog t imer a re pr ovided fo r m aximum fl exibility. al l o scillator o ptions a re selected through the confguration options. the three methods of generating the system clock are: ? external crystal/resonator oscillator ? external rc oscillator ? internal rc oscillator one of these three methods must be selected using the confguration options. more information regarding the oscillator is located in application note ha0075e on the holtek website. external crystal/resonator oscillator the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. however , for some crystals and most resona tor types, to ensure osci llation and accurate frequenc y ge neration, it may be necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specifcation. the external parallel feedback resistor , rp, is normally not required but in some cases may be needed to assist with oscillation start up. internal ca, cb, rf typical values @ 5v, 25 c ca c ? rf 11~13pf 13~15pf 800k : oscillator internal component values ? ? ? ? ? crystal/resonator oscillator rev. 1.00 60 de?e??e? 1?? ? 011 rev. 1.00 61 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu external rc oscillator using the external system rc oscillator requires that a resistor , with a value between 150k w and 300k w , is connected between osc1 and vss. the generated system clock divided by 4 will be provided on osc2 as an output which can be used for external synchronization purposes. note that as the osc2 output is an nmos open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency . although this is a cost ef fective oscillator confguration, the oscil lation frequenc y can vary wit h vdd, te mperature and process vari ations and is therefore not s uitable for applications w here timing is critical or w here accurate oscillator frequencies are required. for the value of the external resistor r osc refer to the holtek website for typical rc oscillator vs. t emperature and vdd characteristics graphics. note that it is the only microcontroller internal circuitry together with the external resistor , that determine the frequency of the oscillator . the external capacitor shown on the diagram does not infuence the frequency of oscillation. external rc oscillator internal rc oscillator the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz selected by confguration options. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3.3v or 5v and at a temperature of 25 degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pc1 and pc2 are free for use as normal i/o pins. internal rc oscillator -- hirc watchdog timer oscillator the wdt oscillator is a fully self-contained free running on-chip rc oscillator with a typical period of 65 s at 5v requiring no external components. when the device enters the power down mode, the system clock will stop running but the wdt oscillator continues to free-run and to keep the watchdog active. h owever, to pres erve pow er in certain applications the wd t os cillator can be disabled via a confguration option. rev. 1.00 6 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 63 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu power down mode and wake-up power down mode all of the holtek microcontrollers have the ability to enter a power down mode, also known as the "halt" mode or sleep mode. when the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. this occurs because when the device enters the po wer do wn mo de, t he sy stem o scillator i s st opped wh ich r educes t he p ower c onsumption to extremely low levels, however , as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. this feature is extremely important in application areas where the mcu must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. entering the power down mode there is only one way for the device to enter the power down mode and that is to execute the "halt" instructio n in the applicatio n program. when this instruction is executed, the following will occur: ? the system oscillator will stop running and the application program will stop at the "halt" instruction. ? the data memory contents and registers will maintain their present condition. ? the wdt will be cleared and resume counting if the wdt clock source is selected to come from the wdt oscillator. the wdt will stop if its clock source originates from the system clock. ? the i/o ports will maintain their present condition. ? in the status register, the power down fag, pdf, will be set and the w atchdog time-out fag, t o, will be cleared. standby current considerations as the main reason for entering the power down mode is to keep the current consumption of the mcu to as low a value as possible, perhaps only in the order of several micro-amps, there are other conside rations whic h m ust al so be ta ken int o ac count by the ci rcuit desi gner i f t he power consumption is to be minimized. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins c ould c reate i nternal osc illations a nd result i n i ncreased c urrent c onsumption. ca re m ust a lso be taken with the loads, which are connected to i/os, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the w atchdog t imer internal oscillator. rev. 1.00 6? de?e??e? 1?? ? 011 rev. 1.00 63 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu wake-up after the system enters the power down mode, it can be woken up from one of various sources listed as follows: ? an external reset ? an external falling edge on port a ? a system interrupt ? a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow , a w atchdog t imer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the t o and pdf flags. the pdf flag is cleared by a system power -up or executing the clear w atchdog t imer instructions and is set when executing the "halt" instructio n. the t o fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup via an individual confguration option to permit a negative transition on the pin to w ake-up the s ystem. when a p ort a pin w ake-up occurs , the program w ill resume execution at the instruction following the "halt" instruction. if the system is woken up by an inte rrupt, then two possible situations may occur . the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "hal t" instruction. in this situation, the interrupt which woke-up the device will not be immediately service d, but will rather be serviced later wh en t he r elated i nterrupt i s f inally e nabled o r wh en a st ack l evel b ecomes f ree. t he o ther situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set to "1" before entering the power down mode, the wake-up function of the related interrupt will be disabled. no matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation res umes. however, if the wake-up has originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or more cycles. if the wake-up results in the execution of the next instruction following the "hal t" instruction, this will be execute d immediately after the 1024 system clock period delay has ended. low voltage reset - lvr the mi crocontroller cont ains a low volt age reset circuit in order to moni tor the supply volt age of the de vice, whi ch is selected via a confgurat ion option. if the suppl y voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery , the l vr will automatically reset the device internally. rev. 1.00 64 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 65 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu low voltage detector - lvd this l ow v oltage de tect i nternal f unction p rovides a m eans f or t he u ser t o m onitor wh en t he power supply voltage falls below a certain fxed level as specifed in the dc characteristics. bit 2 of pwmc registe r and low v oltage detector option are used to control the overall function of the lvd. low v oltage detector option is the enable/disable control bit, when select disable the overall function of the lvd will be disabled. bit 2 is the l vd detector output bit and is known as l vdf. under normal operation, and when the power supply voltage is above the specifed vl vd value in the dc characteristic section, the l vdf bit will remain at a zero value. if the power supply voltage should fall below this vl vd value then the l vdf bit will change to a high value indicating a low voltage condition. note that the l vdf bit is a read-only bit. by polling the l vdf bit in the pwmc register , the application program can therefore determine the presence of a low voltage condition. operation the low v oltage detector must frst be enabled using a confguration option. the l vd control bit is bit 2 of the pwmc regsiter and is known as l vdf. under normal operation, and when the power supply voltage is above the specified vl vd value in the dc characteristic section, the l vdf bit will remain at a zero value. if the power supply voltage should fall below this vlvd value then the l vdf bit will change to a high value indicating a low voltage condition. note that the l vdf bit is a read-only bit. by polling the l vdf bit in the pwmc register , the application program can therefore determine the presence of a low voltage condition. watchdog timer the w atchdog t imer is provided to prevent program malfunctions or sequences from jumping to unknown location s, due to certain uncontrollable external events such as electrical noise. it operates by providing a device reset when the wdt counter overfows. the wdt clock is supplied by one of tw o s ources s elected by configuration option: its ow n s elf-contained dedicated internal wd t oscillator, or the instruction clock which is the system clock divided by 4. note that if the wdt confguration option has been disabled, then any instruction relating to its operation will result in no operation. the internal wdt oscillator has an approximate period of 65 s at a supply voltage of 5v . if selected, i t i s fr st d ivided b y 2 56 v ia a n 8 -stage c ounter t o g ive a n ominal p eriod o f 1 7ms. no te that this period can vary with vdd, temperature and process variations. for longer wdt time- out peri ods t he w dt presca ler c an be ut ilized. by wri ting t he requi red val ue t o bi ts 0, 1 a nd 2 of the wdts registe r, known as ws0, ws1 and ws2, longer time-out periods can be achieved. w ith ws0, ws1 and ws2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s. a confguration option can select the instruction clock, which is the system clock divided by 4, as the wdt clock source instead of the internal wdt oscillator . if the instruction clock is used as the clock source , i t m ust be note d t hat whe n t he system ent ers t he power down mode, as t he syst em clock i s st opped, t hen t he w dt c lock sou rce wi ll a lso b e st opped. t herefore t he w dt wi ll l ose its protec ting purposes. in such cases the system cannot be restarted by the wdt and can only be restarted using external signals. for systems that operate in noisy environments, using the internal wdt oscillator is therefore the recommended choice. rev. 1.00 64 de?e??e? 1?? ? 011 rev. 1.00 65 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu under normal program operation, a wdt time-out will initialise a device reset and set the status bit to. howe ver, i f t he syst em i s i n t he powe r down mode , whe n a w dt t ime-out oc curs, onl y t he program c ounter a nd st ack po inter wi ll b e r eset. t hree m ethods c an b e a dopted t o c lear t he c ontents of the wdt and the wdt prescaler . the frst is an external hardware reset, which means a low level on the res pin, the second is using the watchdog software instructions and the third is via a "hal t" instruction. there are two methods of using software instructions to clear the w atchdog t imer, one of which must be chosen by confguration option. the frst option is to use the single "clr wdt" instruction while the second is to use the two commands "clr wdt1" and "clr wdt2". for the frst option, a s imple execution of " clr wd t" w ill clear the wd t w hile for the s econd option, both " clr wdt1" and "clr wdt2" must both be executed to successfully clear the wdt . note that for this second option, if "clr wdt1" is used to clear the wdt , successive executions of this instruction will have no ef fect, only the execution of a "clr wdt2" instruction will clear the wdt . similarly , after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the w atchdog t imer. watchdog timer register ?? ? ?? ? - ?? ?? ? - ?? ? - ? ?? ?? ? ? ?? ? ? ? - ?? watchdog timer rev. 1.00 66 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 67 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu confguration options confguration options refer to certa in options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht -ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software. no. options i/o options 1 3a3zdhxshdehrgvdeh ? 3a3sxjhdehrgvdeh 3 3a3sxjhdehrgvdeh oscillator options 4 ?6wshvhhfwr(5fvwdr?5 hirc options 5 ?5rswr000 watchdog options 6 :'7hdehrgvdeh 7 :'7frfvrxfh:'7?6r7 pb i/o port output voltage options 8 ?''3???''wshvhhfwr?''3??r?''ir3rw63?? ? ??shew lvr option ? ?5ixfwrhdehrgvdeh lvd option 10 ?'ixfwrhdehrgvdeh reset options 11 5hvhwixfwr3rhvhws sima options 1 ? 6?0)xfwrhdehrgvdeh 13 63?6:6(1hdehrgvdeh 14 63?6::?hdehrgvdeh 15 i ? 51?hdehrgvdeh 16 i ? gherxfhwhvvwhfrfv simb options 17 6?0)xfwrhdehrgvdeh 18 63?6:6(1hdehrgvdeh 1 ? 63?6::?hdehrgvdeh ? 0 i ? 51?hdehrgvdeh ? 1 i ? gherxfhwhvvwhfrfv rev. 1.00 66 de?e??e? 1?? ? 011 rev. 1.00 67 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu application circuits vdd1 vdd1 vdd ? vdd vdd1 vdd vdd ? vdd vdd v33 v33 sp+ sp- pw m1 pw m2 pb2 aud_in sp- vref vol pb2 sp+ pa2 pa6 pa7 pa4 vdd ? vss1 vss1 vss1 pa4 pa6 aud pa7 pb2 pa3 pa5 vss1 vss1 pw m2 vss1 pa0 aud pa3 vdd pa1 pa2 vdd1 pw m1 resb pa5 pa1 pa0 vss vss d1 power led c11 0.01u vr1 50k 1 3 ? u2 ht8 ? v73 ? 1 ? 3 4 8 7 6 5 ou tn audin v?ef vss vdd ou tp nc ceb c10 0.1uf c? 10uf c8 100uf sw1 ? 1 3 5 4 6 r8 330 d4 play led r11 10 c1 ? 10u c ?? 0.1u r5 100k ja1 mini usb con 1 ? 3 4 5 vdd usb- usb+ vss vss sw ? 4 power switch ? 1 3 + c1 100u ls1 speaker c? 0.1u bt1 battery 1 ? d? 1n5817 r1 ? 0 r? 330 s3 1 ? s1 1 ? s? 1 ? s4 1 ? s6 1 ? s7 1 ? c ? 0 10u s8 1 ? c3 0.1u sw ? 1 ? s5 1 ? c ? 3 0.1u c ? 5 0.1u c1 ? 0.1u u3 ht7 ? 33 ? 3 1 vin vout gnd u1 HT83B60 1 ? 4 ? ? 3 3 ?? 4 ? 1 5 ? 0 6 1 ? 7 18 8 17 ? 16 10 15 11 14 1 ? 13 ? 5 ? 6 ? 7 ? 8 pa1 pa6 pa0 pa7 pb0 vss pb1 vdd pb2 vdd_pbio pb4/sdoa pc0/res pb5/sclka vssp pb6/sdia pw m2 pb7/scsa pw m1 pc1/osc1 vddp pc2/osc2 vdda vssa aud pa5 pa4 pa3 pa2 8-sop (150 mil) on off key5 key2 key3 key7 key4 key6 key1 key8 reset power circuit power amplifier led & key rev. 1.00 68 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 6? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator , most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp , call, ret , reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. e xamples of suc h i nstructions would be clr pcl or mov pcl, a. for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the ac cumulator. one of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. w ithin t he hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. rev. 1.00 68 de?e??e? 1?? ? 011 rev. 1.00 6 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within t he hol tek m icrocontroller i nstruction se t. as wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he ac cumulator wh ich m ay i nvolve a dditional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. dif ferent rotate instructions exist depending on program requirements. rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he ca rry bit from where it can be examined and the necessary serial bit set high or low . another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they dif fer in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping of f poi nt as in the case of the call instruct ion. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the abili ty to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively . the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data st orage i s norm ally i mplemented by usi ng re gisters. howeve r, whe n working wi th l arge amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory . t o overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the hal t instruction for power -down operations and instructions to control the operation of the w atchdog t imer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.00 70 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 71 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a ? x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1note 1note 1 1 1 1note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1note z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none rev. 1.00 70 de?e??e? 1?? ? 011 rev. 1.00 71 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu mnemonic description cycles flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a ? x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc su ?? outine ? all retu ? n f ? o ? su ?? outine return from subroutine and load immediate data to acc return from interrupt ? 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note ? ? ? ? none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory ? note ? note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the t o and pdf fags may be affected by the execution status. the t o and pdf fags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the t o and pdf fags remain unchanged. rev. 1.00 7 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 73 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu instruction defnition adc a,[m] add d ata m emory to a cc w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] + c affected f ag(s) ov, z , a c, c adcm a,[m] add a cc to d ata m emory w ith carry description the c ontents o f t he s pecifed d ata m emory, a ccumulator a nd t he c arry f ag a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] + c affected f ag(s) ov, z , a c, c add a,[m] add d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + [ m] affected f ag(s) ov, z , a c, c add a,x add im mediate data to a cc description the c ontents o f t he a ccumulator a nd t he s pecifed im mediate data a re a dded. the re sult is s tored in t he a ccumulator. operation acc a cc + x affected f ag(s) ov, z , a c, c addm a,[m] add a cc to d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he a ccumulator a re a dded. the re sult is s tored in t he sp ecifed d ata m emory. operation [m] a cc + [ m] affected f ag(s) ov, z , a c, c and a,[m] logical a nd d ata m emory t o a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd [ m] affected f ag(s) z and a,x logical a nd im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b it w ise l ogical a nd operation. t he re sult is s tored in t he a ccumulator. operation acc a cc a nd x affected f ag(s) z andm a,[m] logical a nd a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical a nd operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc and [ m] affected f ag(s) z rev. 1.00 7? de?e??e? 1?? ? 011 rev. 1.00 73 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu call addr subroutine c all description unconditionally c alls a s ubroutine a t t he s pecifed a ddress. th e p rogram c ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. t he sp ecifed a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. a s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. operation stack p rogram counter + 1 program c ounter a ddr affected f ag(s) none clr [m] clear d ata m emory description each b it o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m] 00h affected f ag(s) none clr [m].i clear bi t o f d ata m emory description bit i o f t he s pecifed d ata m emory i s cl eared t o 0 . operation [m].i 0 affected f ag(s) none clr wdt clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re al l c leared. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt1 pre-clear w atchdog t imer description the t o, p df f ags a nd t he w dt a re a ll c leared. n ote t hat t his instruction w orks in conjunction w ith c lr w dt2 a nd m ust b e e xecuted al ternately w ith c lr w dt2 to h ave effect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt2 w ill have no e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df clr wdt2 pre-clear w atchdog t imer description the t o, p df f ags and t he w dt are all cleared. n ote t hat t his i nstruction w orks i n conjunction with c lr w dt1 a nd m ust b e e xecuted al ternately w ith c lr w dt1 to h ave e ffect. r epetitively e xecuting t his i nstruction w ithout al ternately e xecuting c lr w dt1 w ill h ave n o e ffect. operation wdt cl eared to 0 pdf 0 affected f ag(s) to, p df cpl [m] complement d ata m emory description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. operation [m] [m] affected f ag(s) z rev. 1.00 74 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 75 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu cpla [m] complement d ata m emory w ith r esult i n a cc description each b it of t he s pecifed d ata m emory i s l ogically complemented ( 1s complement). b its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. th e c omplemented r esult i s s tored i n the a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] affected f ag(s) z daa [m] decimal-adjust a cc f or addition w ith r esult i n d ata m emory description convert t he c ontents o f t he a ccumulator v alue to a b cd ( binary c oded d ecimal) v alue resulting f rom t he p revious a ddition o f t wo b cd v ariables. i f t he low n ibble is greater t han 9 or i f a c f ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. o therwise t he l ow n ibble remains u nchanged. i f t he h igh n ibble i s g reater t han 9 o r i f t he c f ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. e ssentially, t he decimal c onversion i s p erformed b y a dding 00h, 0 6h, 6 0h o r 6 6h depending o n t he a ccumulator a nd f ag c onditions. o nly t he c f ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal b cd s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. operation [m] a cc + 00h or [m] a cc + 06 h o r [m] a cc + 60h o r [m] a cc + 66h affected f ag(s) c dec [m] decrement d ata m emory description data i n t he s pecifed d ata m emory i s d ecremented b y 1 . operation [m] [ m] ? 1 affected f ag(s) z deca [ m] decrement d ata m emory wi th r esult i n a cc description data in t he sp ecifed d ata m emory is d ecremented b y 1 . t he re sult is s tored in t he accumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] ? 1 affected f ag(s) z halt enter p ower down m ode description this i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. th e c ontents o f the d ata m emory a nd r egisters a re r etained. th e w dt a nd p rescaler a re c leared. th e p ower down f ag p df i s s et a nd t he w dt t ime-out f ag t o i s c leared. operation to 0 pdf 1 affected f ag(s) to, p df inc [m] increment d ata m emory description data in t he sp ecifed d ata m emory is incremented b y 1 . operation [m] [ m] + 1 affected f ag(s) z inca [m] increment d ata m emory wi th r esult i n a cc description data i n t he sp ecifed d ata m emory i s i ncremented b y 1 . th e re sult i s s tored i n t he a ccumulator. the c ontents o f t he d ata m emory r emain u nchanged. operation acc [ m] + 1 affected f ag(s) z rev. 1.00 74 de?e??e? 1?? ? 011 rev. 1.00 75 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu jmp addr jump u nconditionally description the c ontents o f t he p rogram c ounter a re re placed w ith t he sp ecifed a ddress. p rogram execution t hen c ontinues f rom t his n ew a ddress. a s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. operation program counter addr affected f ag(s) none mov a,[m] move d ata m emory t o a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. operation acc [ m] affected f ag(s) none mov a,x move im mediate data to a cc description the im mediate data s pecifed i s l oaded i nto t he a ccumulator. operation acc x affected f ag(s) none mov [m],a move a cc to d ata m emory description the c ontents o f t he a ccumulator a re c opied to t he s pecifed d ata m emory. operation [m] a cc affected f ag(s) none nop no o peration description no o peration i s p erformed. e xecution c ontinues w ith t he n ext i nstruction. operation no operation affected f ag(s) none or a,[m] logical o r d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise logical o r op eration. t he re sult is s tored in t he a ccumulator. operation acc a cc or [ m] affected f ag(s) z or a,x logical or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical o r operation. t he re sult is s tored in t he a ccumulator. operation acc a cc or x affected f ag(s) z orm a,[m] logical or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical o r operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc or [ m] affected f ag(s) z ret return from s ubroutine description the p rogram c ounter is re stored f rom t he s tack. p rogram e xecution c ontinues a t t he re stored a ddress. operation program counter s tack affected f ag(s) none rev. 1.00 76 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 77 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu ret a,x return f rom su broutine and l oad im mediate data to a cc description the p rogram c ounter i s r estored f rom t he s tack a nd t he a ccumulator l oaded w ith t he s pecifed immediate data. p rogram e xecution c ontinues a t t he r estored a ddress. operation program counter s tack acc x affected f ag(s) none reti return from i nterrupt description the p rogram c ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he emi b it. e mi i s t he m aster i nterrupt g lobal e nable b it. i f a n i nterrupt w as p ending w hen t he reti instruction is e xecuted, t he p ending in terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. operation program counter s tack emi 1 affected f ag(s) none rl [m] rotate d ata m emory l eft description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 [ m].7 affected f ag(s) none rla [m] rotate d ata m emory left w ith re sult in a cc description the c ontents o f t he s pecifed d ata m emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . the r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 [ m].7 affected f ag(s) none rlc [m] rotate d ata m emory l eft t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated l eft b y 1 b it. b it 7 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 0 . operation [m].(i+1) [ m].i; (i = 0 ~6) [m].0 c c [ m].7 affected f ag(s) c rlca [m] rotate d ata m emory left t hrough c arry w ith re sult in a cc description data i n t he s pecifed d ata m emory and t he carry f ag are r otated l eft b y 1 b it. b it 7 r eplaces t he carry b it a nd t he o riginal c arry f ag i s r otated i nto t he b it 0 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.(i+1) [ m].i; (i = 0 ~6) acc.0 c c [ m].7 affected f ag(s) c rr [m] rotate d ata m emory r ight description the contents of t he s pecifed d ata m emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 [ m].0 affected f ag(s) none rev. 1.00 76 de?e??e? 1?? ? 011 rev. 1.00 77 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu rra [m] rotate d ata m emory right with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . th e r otated r esult i s s tored i n t he a ccumulator a nd t he c ontents o f t he data m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 [ m].0 affected f ag(s) none rrc [m] rotate d ata m emory r ight t hrough carry description the c ontents o f t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 replaces t he c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . operation [m].i [ m].(i+1); ( i = 0 ~6) [m].7 c c [ m].0 affected f ag(s) c rrca [m] rotate d ata m emory right th rough c arry with result i n a cc description data i n t he s pecifed d ata m emory a nd t he c arry f ag a re r otated r ight b y 1 b it. b it 0 r eplaces the c arry b it a nd t he o riginal c arry f ag i s r otated i nto b it 7 . th e r otated r esult i s s tored i n t he accumulator a nd t he c ontents o f t he d ata m emory r emain u nchanged. operation acc.i [ m].(i+1); (i = 0 ~6) acc.7 c c [ m].0 affected f ag(s) c sbc a,[m] subtract d ata m emory from a cc wi th c arry description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he a ccumulator. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sbcm a,[m] subtract d ata m emory from a cc wi th c arry a nd r esult i n d ata m emory description the c ontents o f t he s pecifed d ata m emory a nd t he c omplement o f t he c arry f ag a re subtracted f rom t he a ccumulator. t he re sult is s tored in t he d ata m emory. n ote t hat if t he result o f s ubtraction is n egative, t he c f ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] ? c affected f ag(s) ov, z , a c, c sdz [m] skip i f decrement d ata m emory i s 0 description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] ? 1 skip if [ m] = 0 affected f ag(s) none rev. 1.00 78 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 7? de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu sdza [m] skip i f decrement d ata m emory i s z ero w ith r esult i n a cc description the c ontents o f t he s pecifed d ata m emory a re fr st decremented b y 1 . i f t he r esult i s 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] ? 1 skip if a cc = 0 affected f ag(s) none set [m] set d ata m emory description each b it o f t he s pecifed d ata m emory i s s et t o 1 . operation [m] f fh affected f ag(s) none set [m].i set b it o f d ata m emory description bit i o f t he s pecifed d ata m emory i s s et t o 1 . operation [m].i 1 affected f ag(s) none siz [m] skip i f i ncrement d ata m emory i s 0 description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. operation [m] [ m] + 1 skip if [ m] = 0 affected f ag(s) none siza [m] skip if increment d ata m emory is z ero w ith re sult in a cc description the c ontents o f t he sp ecifed d ata m emory a re f rst incremented b y 1 . i f t he re sult is 0 , t he following instruction is s kipped. t he re sult is s tored in t he a ccumulator b ut t he sp ecifed data m emory c ontents r emain u nchanged. a s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation acc [ m] + 1 skip if a cc = 0 affected f ag(s) none snz [m].i skip i f b it i of d ata m emory i s n ot 0 description if b it i o f t he sp ecifed d ata m emory is n ot 0 , t he f ollowing instruction is s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i 0 affected f ag(s) none sub a,[m] subtract d ata m emory from a cc description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? [ m] affected f ag(s) ov, z , a c, c rev. 1.00 78 de?e??e? 1?? ? 011 rev. 1.00 7 ? de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu subm a,[m] subtract d ata m emory from a cc wi th r esult i n d ata m emory description the s pecifed d ata m emory i s s ubtracted f rom t he c ontents o f t he a ccumulator. th e r esult i s stored in t he d ata m emory. n ote t hat if t he re sult o f s ubtraction is n egative, t he c f ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation [m] a cc ? [ m] affected f ag(s) ov, z , a c, c sub a,x subtract im mediate data f rom a cc description the im mediate data s pecifed b y t he c ode i s s ubtracted f rom t he c ontents o f t he a ccumulator. the re sult is s tored in t he a ccumulator. n ote t hat if t he re sult o f s ubtraction is n egative, t he c fag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he c f ag w ill b e s et to 1 . operation acc a cc ? x affected f ag(s) ov, z , a c, c swap [m] swap ni bbles of d ata m emory description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. operation [m].3~[m].0 ? [ m].7 ~ [ m].4 affected f ag(s) none swapa [m] swap ni bbles of d ata m emory w ith r esult i n a cc description the l ow-order a nd h igh-order n ibbles o f t he s pecifed d ata m emory a re i nterchanged. th e result i s s tored i n t he a ccumulator. th e c ontents o f t he d ata m emory r emain u nchanged. operation acc.3 ~ a cc.0 [ m].7 ~ [ m].4 acc.7 ~ a cc.4 [ m].3 ~ [ m].0 affected f ag(s) none sz [m] skip i f d ata m emory i s 0 description if t he contents of t he s pecifed d ata m emory i s 0, t he following i nstruction i s s kipped. a s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. i f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m] = 0 affected f ag(s) none sza [m] skip i f d ata m emory i s 0 w ith data m ovement to a cc description the c ontents o f t he s pecifed d ata m emory a re c opied to t he a ccumulator. i f t he v alue i s z ero, the f ollowing instruction is s kipped. a s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. operation acc [ m] skip if [ m] = 0 affected f ag(s) none sz [m].i skip i f b it i of d ata m emory i s 0 description if b it i o f t he sp ecifed d ata m emory is 0 , t he f ollowing instruction is s kipped. a s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. i f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. operation skip i f [ m].i = 0 affected f ag(s) none rev. 1.00 80 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 81 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu tabrdc [m] read ta ble ( current p age) to t blh a nd d ata m emory description the low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( tblp) is moved t o t he s pecifed d ata m emory a nd t he h igh by te mo ved t o t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none tabrdl [m] read t able (last p age) t o t blh a nd d ata m emory description the l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (tblp) i s mo ved to t he s pecifed d ata m emory a nd t he h igh b yte m oved to t blh. operation [m] pr ogram c ode (low by te) tblh pr ogram c ode (high by te) affected f ag(s) none xor a,[m] logical x or d ata m emory to a cc description data i n t he a ccumulator a nd t he s pecifed d ata m emory p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or [ m] affected f ag(s) z xorm a,[m] logical x or a cc to d ata m emory description data i n t he s pecifed d ata m emory a nd t he a ccumulator p erform a b itwise l ogical x or operation. t he re sult is s tored in t he d ata m emory. operation [m] a cc xor [ m] affected f ag(s) z xor a,x logical x or im mediate data to a cc description data i n t he a ccumulator a nd t he s pecifed im mediate data p erform a b itwise l ogical x or operation. t he re sult is s tored in t he a ccumulator. operation acc a cc x or x affected f ag(s) z rev. 1.00 80 de?e??e? 1?? ? 011 rev. 1.00 81 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu package information note that the package information provided here is for consultation purposes only . as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the package information. 28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.3 ? 3 D 0.41 ? b 0. ? 56 D 0.300 c 0.01 ? D 0.0 ? 0 c' 0.6 ? 7 D 0.713 d D D 0.104 e D 0.050 D f 0.004 D 0.01 ? g 0.016 D 0.050 h 0.008 D 0.013 0 D 8 symbol dimensions in mm min. nom. max. a ? . ? 8 D 10.64 b 6.50 D 7.6 ? c 0.30 D 0.51 c' 17.70 D 18.11 d D D ? .64 e D 1. ? 7 D f 0.10 D 0.30 g 0.41 D 1. ? 7 h 0. ? 0 D 0.33 0 D 8 rev. 1.00 8 ? de ? e ?? e ? 1 ?? ? 011 rev. 1.00 83 de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inne ? dia ? ete ? 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width ? .00.5 t1 space between flang ? 4.8 +0.3/-0.2 t ? reel thi ? kness 30. ? 0. ? rev. 1.00 8? de?e??e? 1?? ? 011 rev. 1.00 83 de ? e ?? e ? 1 ?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width ? 4.000.30 p cavity pitch 1 ? .000.10 e perforation position 1.750.10 f cavity to perforation(width direction) 11.500.10 d perforation diameter 1.50 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation(length direction) ? .00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth ? . ? 70.10 t carrier tape thickness 0.350.01 c cover tape width ? 1.30.1 rev. 1.00 84 de ? e ?? e ? 1 ?? ? 011 rev. 1.00 pb de?e??e? 1?? ? 011 HT83B60 voice mask mcu HT83B60 voice mask mcu holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at h ttp://www.holtek.com.tw. |
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