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ics for communication equipment 1 publication date: october 2002 sdm00007beb AN6591FJM transmission / reception, single chip pll ic for phs, cordless telephone overview AN6591FJM is a single chip ic optimum for phs, and a quadrature modulator, reception if and pll are inte- grated in it. as this ic is housed in a qfn package (quad flat non- leaded pkg), realization of compact equipment through this super-small package is possible. features ? transmission and reception pll block on a single chip ? transmission block: a quadrature modulator, a phase shifter apc (auto power control) and an up-converter ? reception block: a down-mixer (to 300 mhz), an if amplifier and an rssi circuit ? pll block: plls for 1st and 2nd local oscillators. ? 6 mm 6 mm small package applications ? phs, digital cordless telephone, etc. unit: mm 3-c 0.50 r0.30 (1.10) (1.10) 0.80 max. (6.00) (6.00) seating plane 1 11 12 22 23 33 34 44 44 34 33 23 22 12 11 1 5.00 0.10 0.16 0.06 6.20 0.10 5.00 0.10 0.20 0.10 6.20 0.10 (0.48) (0.48) 0.10 m 0.10 0.40 qfn044-p-0606a (lead-free package)
AN6591FJM 2 sdm00007beb application circuit example 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 p 0 v cc1 v cc2 43 44 33 31 32 30 29 28 27 26 25 24 23 11 9 2 10 8 7 5 6 4 3 1 18-bit 1st a / n counter lock detection 2nd n counter (291) a counter (7) 2nd prescaler (1 / 16, 1 / 17) 23-bit shift register 1st r counter latch 14-bit 1st r counter 1st phase comparator 300 khz 50 khz 2nd phase comparator 2nd r counter (384) 1st charge pump 2nd charge pump 1st prescaler controller lpf2 lpf1 vco1 f rfin lo1 vco2 i o i o i o i o i o i o 1st n counter latch rssi i q i q data strobe clock ld psrf psif v cc v cc 0 ? 0 ? 560 ? 560 ? 47 ? 100 pf 1 000 pf 2 200 pf 4 700 pf 1 649.7 mhz to 1 686.3 mhz 1 000 pf 5 f ld f refin 1 000 pf 1 000 pf 5 f 47 ? 223.15 mhz 223.15 mhz 47 ? 47 ? 47 ? 0 ? 330 ? 330 ? 100 pf 100 pf lo3 v li lo2 v lm v s v mi 2 200 pf 1 000 pf 100 pf 100 pf 100 pf 100 pf 100 pf 1 k ? 1 k ? 1 k ? 1 k ? 560 pf 2 200 pf 2 200 pf 22 nf 22 nf 5 f mixo ceramic filter (maker: murata) v cc1 f ifin v cc
AN6591FJM 3 sdm00007beb pin descriptions pin no. symbol description 1 rxmxin rx mix. in 2 rxloin rx local in 3v cc2 v cc mix. 4 mxo mix. out 5 lmdec1 lim. decouple1 6 lmin lim. in 7 lmdec2 lim. decouple2 8v cc2 v cc lim. 9 lmo lim. out 10 txlo2 tx local2 in 11 rso rssi out 12 gnd gnd 13 q-in q-input 14 q-in q-input 15 i-in i-input 16 i-in i-input 17 v cc1 v cc tx mod. 18 gndm gnd tx mod. 19 ifin 2nd prescaler in 20 n.c. ? 21 gnd2 gnd 2nd cmos 22 v cc v cc 1st 2nd bip pin no. symbol description 23 n.c. ? 24 n.c. ? 25 n.c. ? 26 v cc v cc 2nd cmos 27 cp2 2nd charge pump out 28 psif 2nd power save in 29 psrf 1st power save in 30 ref. reference in 31 ld lock detect out 32 clock clock in 33 data serial data in 34 strobe strobe in 35 gnd gnd 1st / 2nd cmos 36 cp1 1st charge pump out 37 v cc v cc 1st cmos 38 rfin 1st prescaler in 39 txlo1 tx local 1 40 txlo1r tx local 1ref. 41 apc / bs apc / bs 42 v cc1 v cc tx out 43 txo tx output 44 gndo gnd tx out note) * 1: except for the operating ambient temperature and storage temperature, all ratings are for t a = 25 c. * 2: the above power dissipation p d shows the power dissipation of the package without heat sink. refer to " technical data " when mounting this ic to a pcb and check that the ic will operate within the package power dissipation range. absolute maximum ratings parameter symbol rating unit supply voltage v cc 3.5 v v cc1 v cc2 supply current * 2 i cc 54 ma power dissipation * 2 p d 194 mw operating ambient temperature * 1 t opr ? 20 to + 70 c storage temperature * 1 t stg ? 55 to + 125 c recommended operating range parameter symbol range unit supply voltage v cc , v cc1 , 2.7 to 3.3 v v cc2
AN6591FJM 4 sdm00007beb electrical characteristics at t a = 25 c parameter symbol test conditions min typ max unit circuit current consumption (reception) i ccrx 2 no signal input ? 5.3 6.8 ma mix. conversion gain g mx 1v mi = 70 db filter loss excluded. 13 16 19 db mix. max. output level v mx 1v mi = 105 db filter loss excluded. 105 110 ? db lim. voltage gain g lm 1v mi = 20 db 63 68 73 db lim. max. output amplitude v lm 1v li = 80 db 350 400 ? mv[p-p] rssi output voltage (1) v s (1) 1 v li : no signal input 0 0.2 0.5 v rssi output voltage (2) v s (2) 1 v li = 115 db 1.60 1.80 ? v change in rssi output d s 1v s (v is ) = v s (1) + 0.15 v 1.0 1.25 1.5 v d s (1) = v s (v is + 65 db ) ? v s (v is ) gradient of rssi output ? d s(n) 1? d s (n) = 5 (v s (v is + n13 db ) ? 0.75 1.0 1.25 ? v s (v is + (n ? 1) 13 db )) / d s (1) n = 1 to 5 current consumption i cctx 1 lo1 = 233.15 mhz, ? 10 dbm ? 28 37 ma (transmission) lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.75 v sleep current in transmission isl 2 no signal input, v apc = 0 v ? 010 a transmission output level 1 * p01 1 lo1 = 233.15 mhz, ? 10 dbm ? 13 ? 9 ? dbm lo2 = 1 660 mhz, ? 10 dbm, v apc = 2.2 v transmission output level 2 * p02 1 lo1 = 233.15 mhz, ? 10 dbm ? 13 ? 9 ? dbm lo2 = 1 687 mhz, ? 10 dbm, v apc = 2.2 v image leakage suppression il1 1 lo1 = 233.15 mhz, ? 10 dbm ?? 35 ? 30 dbc lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.75 v, i / q: no level adjusted f lo1 + f lo2 cl 1 lo1 = 233.15 mhz, ? 10 dbm ?? 35 ? 30 dbc leakage suppression lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.75 v, i / q: dc offset adjusted proximity spurious du 1 lo1 = 233.15 mhz, ? 10 dbm ?? 55 ? 51 dbc suppression lo2 = 1 672.5 mhz, ? 10 dbm make v apc adjustments so that the po value will be ? 13 dbm. note) 1. unless otherwise specified, at reception: v cc2 = 3.0 v, v lo3 = ? 10 dbm, f = 233.15 mhz, v mi : f = 243.95 mhz, sw1 = a, v li : f = 10.8 mhz (the input level of pin 6, except the signal attenuation at the matching circuit and filter circuit.) the v mo and v lo values are at high impedance. (v lm shall be measured at probe load conditions of 27 pf and 1 m ? .) 2. the v is is the input level v li where the rssi output voltage is v s (1) + 0.15 v. at transmission: v cc1 = 3.0 v, i / q signal amplitude: 0.5 v[p-p] in both phases, dc bias: 1.5 v, sw1: a i cctx , il1, cl: / 4 qpsk-modulated wave, p01, p02, du: pn9-level-modulated wave i / q signal input condition: make an amplitude adjustment of / 4 qpsk modulation signal 0000 to 0.5 v[p-p] with an oscilloscope and change the signal wave to a pn9-level continuous wave. spectrum analyzer setting conditions for transmission output level measurement: span = 2 mhz, rbw = 3 mhz, vbw = 3 mhz, swpt = 5 s det.: pose. peak * : p01 output frequency: 1 893.15 mhz, p02 output frequency: 1 920.15 mhz
AN6591FJM 5 sdm00007beb parameter symbol test conditions min typ max unit circuit 1st local leakage suppression cl1 1 lo1 = 233.15 mhz, ? 10 dbm ?? 25 ? 20 dbc lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.75 v 2nd local leakage suppression cl2 1 lo1 = 233.15 mhz, ? 10 dbm ?? 15 ? 10 dbc lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.75 v in-band output level deviation ?? p ? 1 lo1 = 233.15 mhz, ? 10 dbm ?? 1.0 db lo2 = 1 660 mhz to 1 687 mhz, ? 10 dbm, v apc = 2.2 v adjacent channel leakage bl1 1 lo1 = 233.15 mhz, ? 10 dbm ?? 60 ? dbc power suppression lo2 = 1 672.5 mhz, ? 10 dbm (600 khz detuning) v apc = 2.75 v modulation accuracy evm 1 lo1 = 233.15 mhz, ? 10 dbm ? 3 5 %[rms] lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.2 v min. output level pmin 1 lo1 = 233.15 mhz, ? 10 dbm ?? 30 ? 25 dbm lo2 = 1 672.5 mhz, ? 10 dbm v apc = 1.0 v rf + 233.15 mhz iil 1 lo1 = 233.15 mhz, ? 10 dbm ?? 36 ? dbc leakage suppression lo2 = 1 672.5 mhz, ? 10 dbm v apc = 2.75 v mixer output resistance rmix 2 no signal input ? 330 ?? electrical characteristics at t a = 25 c (continued) parameter symbol test conditions min typ max unit circuit current consumption 1 (pll) i cc1 1 1st pll and 2nd pll blocks are 3.7 5.4 7.0 ma simultaneously turned on. current consumption 2 (pll) i cc2 1 1st pll block is turned on while the 3.0 4.4 5.7 ma 2nd pll block is turned off. current consumption 3 (pll) i cc3 1 1st pll block is turned off while the 1.2 1.7 2.2 ma 2nd pll block is turned on. current consumption 4 (pll) i cc4 1 power save mode ? 010 a 1st rf input level v rfin 1f rfin = 1 500 mhz to 1 800 mhz ? 15 ?? 2dbm 2nd if input level v ifin 1f ifin = 120 mhz to 300 mhz ? 10 ?+ 6dbm reference signal input level v refin 1f refin = 10 mhz to 25 mhz 0.2 ? 1.2 v[p-p] note) unless otherwise specified, v cc is 3.0 v and reference signal input level v refin is 0.6 v[p-p] at f refin = 19.2 mhz. note) unless otherwise specified, v cc = v cc1 = v cc2 = 3.0 v i / q signal: 0.5 v[p-p] in both phases, dc bias: 1.5 v cl1, cl2, ?? p ?, bl1, evm, pmin, iil : pn9-level modulated wave. ? design reference data note) the characteristics listed below are theoretical values based on the ic design and are not guaranteed.
AN6591FJM 6 sdm00007beb electrical characteristics at t a = 25 c (continued) ? design reference data (continued) note) the characteristics listed below are theoretical values based on the ic design and are not guaranteed. parameter symbol test conditions min typ max unit circuit high-level input voltage v ih 2 2.4 ?? v low-level input voltage v il 2 ?? 0.6 v high-level output voltage v oh 2 2.4 ?? v low-level output voltage v ol 2 ?? 0.6 v high-level input current 1 i ih1 2v ih of 3.0 v applied ? 010 a low-level input current 1 i il1 2v il of 0 v applied ? 010 a high-level input current 2 i ih2 2v ih of 3.0 v applied ? 010 a low-level input current 2 i il2 2v il of 0 v applied ? 010 a high-level output current i oh1h,2h 2 high power with v oh of 2.4 v applied. ? 3.2 ? 2.6 ? 1.9 ma 1 / 2 (high power) low-level output current i ol1h,2h 2 high power with v ol of 0.6 v applied. 2.8 3.5 4.4 ma 1 / 2 (high power) high-level output current i oh1l,2l 2 low power with v oh of 2.4 v applied. ? 0.74 ? 0.6 ? 0.46 ma 1 / 2 (low power) low-level output current i ol1l,2l 2 low power with v ol of 0.6 v applied. 0.53 0.7 0.87 ma 1 / 2 (low power) output leakage current i oz 2v oz of 0 v / 3.0 v applied ? 10 1 a high-level output current 3 i oh3l 2v oh of 2.4 v applied ? 3.6 ? 2.6 ? 1.5 ma low-level output current 3 i ol3l 2v ol of 0.6 v applied 1.9 3.3 4.6 ma lockup time (1st) rockt1 1 1st pll block and 2nd pll block are ?? 600 s simultaneously turned on for all chan- nels with rx-to-tx and tx-to-rx burst. lockup time (2nd) rockt2 1 1st pll block and 2nd pll block are ?? 600 s simultaneously turned on intermit- tently (during ps triggering) 1st spurious 50 khz lspu1 1 1st pll block and 2nd pll block are ??? 40 dbc simultaneously turned on. l-channel to h-channel 1st proximity c / n lspu2 1 1st pll block and 2nd pll block are ??? 70 dbc / simultaneously turned on. hz df = 1 khz, l-channel to h-channel 1st reference leakage lspu3 1 1st pll block and 2nd pll block are ??? 67 dbc simultaneously turned on. df = 600 khz, bw192 khz note) unless otherwise specified, v cc is 3.0 v and reference signal input level v refin is 0.6 v[p-p] at f refin of 19.2 mhz.
AN6591FJM 7 sdm00007beb 1. test circuit 1 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 p 0 v cc1 v apc/bs v cc2 43 44 33 31 32 30 29 28 27 26 25 24 23 11 9 2 10 8 7 5 6 4 3 1 18-bit 1st a / n counter lock detection 2nd n counter (291) a counter (7) 2nd prescaler (1 / 16, 1 / 17) 23-bit shift register 1st r counter latch 14-bit 1st r counter 1st phase comparator 300 khz 50 khz 2nd phase comparator 2nd r counter (384) 1st charge pump 2nd charge pump 1st prescaler controller lpf2 lpf1 vco1 f rfin lo1 vco2 i o i o i o i o i o i o 1st n counter latch rssi i q i q data strobe clock ld psrf psif v cc v cc 0 ? 0 ? 560 ? 560 ? 47 ? 100 pf 1 000 pf 2 200 pf 4 700 pf 1 651.2 mhz to 1 684.8 mhz 1 651.2 mhz to 1 684.8 mhz 1 000 pf 5 f ld f refin 1 000 pf 1 000 pf 5 f 47 ? 223.15 mhz 223.15 mhz 223.15 mhz 47 ? 47 ? 47 ? 0 ? 330 ? 330 ? 100 pf 100 pf lo3 v li lo2 v lm v s v mi 2 200 pf 1 000 pf 2 200 pf 100 pf 100 pf 100 pf 100 pf 100 pf 1 k ? 1 k ? 1 k ? 1 k ? 560 pf 2 200 pf 22 nf 22 nf 5 f mixo ceramic filter (maker: murata) v cc1 f ifin f out2 (lo2, lo3) fout1 (lo1) v cc electrical characteristics at t a = 25 c (continued) ? design reference data (continued) note) the characteristics listed below are theoretical values based on the ic design and are not guaranteed. parameter symbol test conditions min typ max unit circuit 2nd reference leakage lspu4 1 1st pll block and 2nd pll block are ??? 40 dbc 50 khz simultaneously turned on. rw 1 khz, vw 1 khz 2nd proximity c / n lspu5 1 1st pll block and 2nd pll block are ??? 76 dbc / simultaneously turned on. hz df = 1 khz note) unless otherwise specified, v cc is 3.0 v and reference signal input level v refin is 0.6 v[p-p] at f refin of 19.2 mhz.
AN6591FJM 8 sdm00007beb electrical characteristics at t a = 25 c (continued) 2. test circuit 2 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 p 0 v cc1 v apc/bs v cc2 43 44 33 31 32 30 29 28 27 26 25 24 23 11 9 2 10 8 7 5 6 4 3 1 18-bit 1st a / n counter lock detection 2nd n counter (291) a counter (7) 2nd prescaler (1 / 16, 1 / 17) 23-bit shift register 1st r counter latch 14-bit 1st r counter 1st phase comparator 300 khz 50 khz 2nd phase comparator 2nd r counter (384) 1st charge pump 2nd charge pump 1st prescaler i o i o i o i o i o i o 1st n counter latch rssi data strobe vih, vil, iih1, iil1 vih, vil, iih1, iil1 voh, vol, ioh1, iol1, 10 z vih, vil, iih1, iil1 vih, vil, iih2, iil2 vih, vil, iih2, iil2 voh, vol, ioh2, iol2, 10 z voh, vol, ioh3, iol3 clock ld psrf psif v cc v cc 0 ? 100 pf 1 000 pf 5 f 1 000 pf 5 f lo3 lo2 v lm v s v mi 2 200 pf 1 000 pf 100 pf 100 pf 1.5 v 100 pf 100 pf 100 pf 1 k ? 1 k ? 1 k ? 1 k ? 560 pf 2 200 pf 22 nf 5 f mixo limin 22 nf 100 pf 100 pf v cc1 v cc
AN6591FJM 9 sdm00007beb pin no. equivalent ci rcuit description i / o 1 rxmixin: i reception mixer input pin with an input impedance of approx. 16 k ? . 2 rxloin: i local input pin. 3 ? v cc2 : mixer power supply pin. ? 4 mxo: o mixer output pin. 5 lmdec1, 2: ? coupling pin for limiter amplifier feed- back. ground this pin through an ex- ternal capacitor. 7 6 lmin: i limiter amplifier input pin with an input impedance of approx. 330 ? . 8 ? v cc2 : ? pin to provide power supply to the limiter amplifier and rssi. 9 lmo: o limiter amplifier output pin. terminal equivalent circuits 1 2 4 6 5 7 9
AN6591FJM 10 sdm00007beb pin no. equivalent ci rcuit description i / o 10 txlo2: i quadrature modulator local input pin 11 rso: o rssi output pin with dc output ac- cording to the input signal level of the limiter amplifier. 12 ? gndr: ground pin. ? 13 q-in: i q signal input pin with the following relationship between the input dc bias and amplitude. 14 q-in: i q signal input pin with the following relationship between the input dc bias and amplitude. 15 i-in: i i signal input pin with the following relationship between the input dc bias and amplitude. 16 i-in: i i signal input pin with the following relationship between the input dc bias and amplitude. terminal equivalent circuits (continued) 10 42 11 13 17 14 15 42 16 dc bias (v) amplitude v[p-p] 1.5 0.5 (both phases) dc bias (v) amplitude v[p-p] 1.5 0.5 (both phases) dc bias (v) amplitude v[p-p] 1.5 0.5 (both phases) dc bias (v) amplitude v[p-p] 1.5 0.5 (both phases)
AN6591FJM 11 sdm00007beb pin no. equivalent ci rcuit description i / o 17 ? v cc1 :i pin to provide supply voltage to the quadrature modulator. the pin is con- nected to the built-in band gap regu- lator, thus providing stable bias volt- age without being affected by v cc or temperature changes as much as pos- sible. 18 ? gndm: ? ground pin for the quadrature modu- lator. keep the grounding surface wide to lower the impedance. 19 2nd prescaler in: i 2nd pll prescaler input pin. 21 ? gnd 2nd cmos: ? ground pin for the 2nd pll. 22 ? v cc : bip power supply pin for the ? pll. 26 ? v cc : 2nd cmos power supply pin ? for the pll. 27 2nd chargepump out: o 2nd pll charge pump output pin. 28 28: 2nd power save in: i 29 29: 1st power save in: 2nd pll and 1st pll power save control input pins. 30 reference in: i reference signal input pin. 19 27 28 29 30 terminal equivalent circuits (continued)
AN6591FJM 12 sdm00007beb pin no. equivalent ci rcuit description i / o 31 lock detect out: o lock detection output pin. 32 32: clock in: i clock input pin. 33 33: serial data in: data input pin. 34 34: strobe in: strobe input pin. 35 ? gnd 1st / 2nd cmos: ? 1st and 2nd pll ground pin. 36 1st charge pump out: o 1st pll charge pump output pin. 37 ? v cc : ? 1st pll cmos power supply pin. 38 1st prescaler in: i 1st pll prescaler input pin. 39 tx lo1: i local input pin for the up-mixer. the use of an external balancer is recom- mended to apply balanced input. 40 tx lo1r: i local input pin for the up-mixer. the use of an external balancer is recom- mended to apply balanced input. 31 32 33 34 36 38 terminal equivalent circuits (continued) 39 40 42
AN6591FJM 13 sdm00007beb pin no. equivalent ci rcuit description i / o 41 apc / bs: i pin used for the battery save of the transmission circuit block and the power control of rf output. the impedance is a minimum of 5 k ? . 42 ? v cc1 : ? pin to provide power supply to the up- mixer and output amplifier circuit. this pin is connected to the built-in stabilized power supply circuit and provides stable bias voltage without being affected by v cc or temperature changes as much as possible. 43 txo: o rf output pin connected to the output amplifier circuit and has emitter fol- lower output. 44 ? gndo: ? ground pin for the up-mixer and out- put amplifier circuit. this pin is a high- frequency ground pin. therefore, keep the grounding surface wide to lower the impedance. v apc (v) status 0 to 0.3 off 1.0 to v cc on (apc control) 41 regulator (apc control) 43 42 terminal equivalent circuits (continued)
AN6591FJM 14 sdm00007beb technical data 1. serial data interface specifications carrier data is transferred in 23-bit serial data transfer. the serial data is set at the clock falling edge and latched onto the synthesizer at the clock rising edge. it is necessary to input a single strobe pulse when the 23-bit serial data transfer is completed. 1) serial interface of 1st synthesizer 1st synthesizer serial data input format n10 msb lsb x: don't care n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 a6 a5 a4 a3 a2 a1 a0 pd p tc c1 c0 x x x to x r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 t1 t0 c1 c0 n data input direction f out = (p n + a) f in / r possible set range: 1st a = 0 to 127 or 63, n = 5 to 2 047 (n > a) r = 5 to 16 383 c0 c1 10 11 1st synthesizer r counter frequency dividing ratio setting 1st synthesizer a / n counter frequency dividing ratio setting pd phase comparator polarity selection p prescaler frequency dividing ratio tc counter test mode setting to output pin test 0 negative 1 positive 128 / 129 64 / 65 ld output counter output normal test t0 t1 00 01 2nd synthesizer r counter output 2nd synthesizer n counter output 10 11 1st synthesizer r counter output 1st synthesizer n counter output data clock strobe 22 21 20 19 18 2 (t 1 , t 2 50 ns) 10 t 1 t 2 2) serial transfer timing timing chart (1) control bit (2) test contents (3) data contents
AN6591FJM 15 sdm00007beb technical data (continued) 2. 2nd synthesizer frequency dividing ratio set frequency (frequency dividing ratio) f out2 = 233.15 mhz, f r = 50 khz, (p = 16, n = 291, a = 7, r = 384 fixed) reference frequency f refin = 19.2 mhz n10 msb lsb n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 x x x a3 a2 a1 a0 pd p x 001001000110000111100 xxxxxr13r12r11r10r9r8r7r6r5r4r3r2r1r0xx 000000000011000000000 ld output high low lock or power save mode lock or power save mode 1st synthesizer 2nd synthesizer unlock lock or power save mode low low lock or power save mode unlock unlock unlock x: don't care 3. unlock detection and ld output specifications 1) the and of the ld signal (2) of the 1st synthesizer block and the ld signal (3) of the 2nd synthesizer block is output. 2) 1st synthesizer block when the synthesizer block is locked, the ld output level will be high. when the synthesizer block is unlocked, the ld output level will be low. the detection time is 3.3 s. as for the precision of detection, unlock output turns on if the devided frequency output of the circuit is (52 4) ns slower or faster than it should be at the frequency f ref of 300 khz. the lock signal is output in power save mode. 3) 2nd synthesizer block when the synthesizer block is locked, the ld output level will be high. when the synthesizer block is unlocked, the ld output level will be low. the detection time is 20 s. as for the precision of detection, unlock output turns on if the devided frequency output of the circuit is (52 4) ns slower or faster than it should be at the frequency f ref of 50 khz. the lock signal is output in power save mode. 4. other specifications 1) clock, data, and strobe all are high-active logics. 2) when the ic is turned on, set the ic to power save mode by setting both ps1 and ps2 to low-level. after serial data is input, set the ic to operating mode by setting both ps1 and ps2 to high-level.
AN6591FJM 16 sdm00007beb technical data (continued) 3. tx-rx burst / intermittent reception lockup time lockup time ( s) 255 5 15 20 10 25 30 35 40 45 50 55 60 65 75 70 80 max. inter- mittent channel ( ch) 250 350 450 rx tx tx rx unless otherwise specified, v cc = 3.0 v, and f ref = 19.2 mhz. the lockup time means converging time into 1 khz. 1) test circuit 2) serial control timing (1) at tx-rx burst (2) at intermittent reception 33 pf tcx03v tcx03v pll3v pll3v tcx03v 22 pf 68 pf 0.68 f 0.68 f 0.68 f 56 pf 680 pf 100 pf 39 pf 47 pf 2.5 pf 33 pf 1.5 pf 68 pf 4 700 pf 1 000 pf 5 600 pf 1 000 pf 1 000 pf 1 000 pf 1 000 pf 1 000 pf 2.2 k ? 15 k ? 12 nh xn06543 1.5 k ? 47 ? 470 ? 47 ? 8.2 k ? 5.6 k ? 10 k ? 180 ? 27 ? AN6591FJM vco enfvj1g 2s03 time-98 data generator ifin cp2 ref. v cc1/2/b cp1 rfin ps2 ps1 data clock strobe 15 nh ma2z331 1.25 ms ps1 ps2 data clock strobe tcx03v pll3v ps2 ps1 channel setting rx tx 27 s 15.2 s 1.25 ms 1.25 ms 1.25 ms 1.2 s 13.5 ms 4 ms2 ms 1 ms 3.5 ms
AN6591FJM 17 sdm00007beb technical data (continued) 4. oscillator frequency by channel (f rfin ) ch f rfin (mhz) f rfin (mhz) 251 1 660.5 1 649.7 252 1 660.8 1 650.0 253 1 666.1 1 650.3 254 1 666.4 1 650.6 255 1 666.7 1 650.9 11 662.0 1 651.2 21 662.3 1 651.5 31 662.6 1 651.8 41 662.9 1 652.1 51 663.2 1 652.4 61 663.5 1 652.7 71 663.8 1 653.0 81 664.1 1 653.3 91 664.4 1 653.6 10 1 664.7 1 653.9 11 1 665.0 1 654.2 12 1 665.3 1 654.5 13 1 665.6 1 654.8 14 1 665.9 1 655.1 15 1 666.2 1 655.4 16 1 666.5 1 655.7 17 1 666.8 1 656.0 18 1 667.1 1 656.3 19 1 667.4 1 656.6 20 1 667.7 1 656.9 21 1 668.0 1 657.2 22 1 668.3 1 657.5 23 1 668.6 1 657.8 24 1 668.9 1 658.1 25 1 669.2 1 658.4 26 1 669.5 1 658.7 27 1 669.8 1 659.0 28 1 670.1 1 659.3 29 1 670.4 1 659.6 30 1 670.7 1 659.9 ch f rfin (mhz) f rfin (mhz) 31 1 671.0 1 660.2 32 1 671.3 1 660.5 33 1 671.6 1 660.8 34 1 671.9 1 661.1 35 1 672.2 1 661.4 36 1 672.5 1 661.7 37 1 672.8 1 662.0 38 1 673.1 1 662.3 39 1 673.4 1 662.6 40 1 673.7 1 662.9 41 1 674.0 1 663.2 42 1 674.3 1 663.5 43 1 674.6 1 663.8 44 1 674.9 1 664.1 45 1 675.2 1 664.4 46 1 675.5 1 664.7 47 1 675.8 1 665.0 48 1 676.1 1 665.3 49 1 676.4 1 665.6 50 1 676.7 1 665.9 51 1 677.0 1 666.2 52 1 677.3 1 666.5 53 1 677.6 1 666.8 54 1 677.9 1 667.1 55 1 678.2 1 667.4 56 1 678.5 1 667.7 57 1 678.8 1 668.0 58 1 679.1 1 668.3 59 1 679.4 1 668.6 60 1 679.7 1 668.9 61 1 680.0 1 669.2 62 1 680.3 1 669.5 63 1 680.6 1 669.8 64 1 680.9 1 670.1 65 1 681.2 1 670.4
AN6591FJM 18 sdm00007beb technical data (continued) 4. oscillator frequency by channel (f rfin ) (continued) ch f rfin (mhz) f rfin (mhz) 66 1 681.5 1 670.7 67 1 681.8 1 671.0 68 1 682.1 1 671.3 69 1 682.4 1 671.6 70 1 682.7 1 671.9 71 1 683.0 1 672.2 72 1 683.3 1 672.5 73 1 683.6 1 672.8 74 1 683.9 1 673.1 75 1 684.2 1 673.4 76 1 684.5 1 673.7 ch f rfin (mhz) f rfin (mhz) 77 1 684.8 1 674.0 78 1 685.1 1 674.3 79 1 685.4 1 674.6 80 1 685.7 1 674.9 81 1 686.0 1 675.2 82 1 686.3 1 675.5 max. 1 686.3 1 649.7 (1st) (2nd) inter- 1 662.6 233.15 mittent 5. p d ? t a curves of qfn044-p-0606a p d ? t a power dissipation p d (w) 025 ambient temperature t a ( c) 50 75 100 125 0.000 0.400 0.353 0.500 0.600 0.700 0.900 1.000 1.100 0.800 0.300 0.100 0.200 1.200 1.300 1.400 1.392 1.500 independent ic without a heat sink r th(j-a) = 282.9 c/w mounted on standard board (glass epoxy: 50 mm 50 mm t0.8 mm) r th(j-a) = 71.8 c/w
AN6591FJM 19 sdm00007beb technical data (continued) 6. main characteristics AN6591FJM mix.i / o characteristics AN6591FJM lim. characteristics apc control voltage characteristics wideband spurious characteristics transmission output level (dbm) / adjacent channel leakage suppression (dbc) / 8 lo (dbc) modulation accuracy (%) ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 20 18 16 14 12 10 8 6 4 2 0 3 2.2 2 0.4 0.2 0.6 1.2 1.4 1 0.8 1.6 1.8 2.8 2.6 2.4 0 apc control voltage (v) transmission output adjacent channel at 300 khz adjacent channel at 600 khz 8 lo modulation accuracy lo1:1 672.5 mhz, ? 10 dbm lo2: 233.15 mhz, ? 10 dbm i / q signal dc bias: 1.5 v, amplitude: 500 mv[p-p], pn9-level continuous wave mix. output level (db ) 0 10 20 30 40 50 60 80 90 70 100 110 120 0 10203040 60 50 70 90 80 100 120 110 mix. input level (db ) 60 c ? 20 c 25 c lim. output level (db ) 0 10 20 30 40 50 60 80 90 70 100 110 120 0 10203040 60 50 70 90 80 100 120 110 limiter input level (db ) 25 c 60 c ? 20 c ? 100 ? 90 ? 80 ? 70 ? 60 ? 50 ? 40 ? 30 ? 20 ? 10 0 rlv: 0.0 dbm at 15 db rb 1 mhz st 200 ms vb 1mhz spurious (dbm) 0.6 6k 600 60 6 60k 60m 6m 600k 600m 6g (hz) note) 1. unless otherwise specified, the test conditions conform to electrical characteristics. 2. the values in the above are reference values for designing and not guaranteed.
AN6591FJM 20 sdm00007beb technical data (continued) 6. main characteristics (continued) mix. cg (db) nf (db) 0 2 4 6 8 12 14 10 16 18 20 ? 20 ? 18 ? 16 ? 14 ? 10 ? 12 ? 8 ? 4 ? 6 ? 20 local input level (dbm) cg nf note) 1. unless otherwise specified, the test conditions conform to electrical characteristics. 2. the values in the above are reference values for designing and not guaranteed. AN6591FJM mix. characteristics AN6591FJM rssi characteristics AN6591FJM mix. characteristics rssi output level (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.4 1.6 1.2 1.8 2.0 2.2 0 10203040 60 50 70 90 80 100 110 120 limiter input level (db ) 25 c 60 c ? 20 c im / mix. output level (db ) 0 20 10 30 40 50 60 70 90 100 80 110 120 130 10 020304060 50 70 90 80 100 110 130 120 mix. input level (db ) output level im
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