fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 100v p-ch an nel mosfet genera l des cription these p- channel enhanc ement mode power field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for low voltage applications such as audio amplifier, high efficiency switching dc/dc converters, and dc motor control. featur es ? -6.6a , -100v, r ds(o n) = 0.53 ? @v gs = -10 v ? low gat e charge ( t ypical 12 nc) ? low crss ( typical 30 pf) ? fast switching ? 100% avalanche tested ? improved dv/dt capability absolu t e maximum ratings t c = 25c unl ess otherwise noted ther m al characteristics symbol p aramet er ratings u nits v dss drain-source vo lt age -100 v i d drain current - cont inuous (t c = 25c) -6.6 a - cont inuous (t c = 100c) -4.2 a i dm drain current - p u lsed (note 1) -26.4 a v gss gate -s ource voltage 30 v e as single pulsed a v alanche energy (note 2) 150 mj i ar avalanche curr ent (note 1) -6.6 a e ar repetitiv e avalanche energy (note 1) 4.4 mj dv/d t peak diode recovery dv/dt (note 3) -6.0 v/ns p d power dissipation (t a = 25c) * 2.5 w power dissipation (t c = 25c) 44 w - de rat e above 25c 0.35 w/c t j , t stg operat ing and storage temperature range -55 to +150 c t l maximum lead t e mperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter typ max units r jc thermal re sist ance, junction-to-case -- 2.84 c / w r ja thermal re sist ance, junction-to-ambient * -- 50 c / w r ja thermal re sist ance, junction-to-ambient -- 110 c / w * when mount ed on the minimum pad size recommended (pcb mount) d-pak gs d s d g december 2 0 10 ?2010 fairchild s emicondu ctor corporation FQD8P10TM_f085 rev. c1 www.fairchildsemi.com 1 ? qualified to aec q101 ? rohs compliant
(note 4) ( note 4, 5) (note 4, 5) (note 4) elec trical characteristics t c = 25c unless otherwise noted notes: 1. repetitive rating : pulse width limited by maximum junction temperature 2. l = 5.2mh, i as = -6.6a , v dd = -25v, r g = 25 ?, starting t j = 25c 3. i sd -8.0a, di/dt 300a/ s, v dd bv dss, star ting t j = 25c 4. pulse test : pulse width 300 s, duty cycle 2% 5. essentially independent of operating temperature sy m bol parameter test conditions min typ max units of f characteristics bv dss drain-source breakdown v oltage v gs = 0 v , i d = -250 a -100 -- -- v ? bv dss / ? t j breakdown v o ltage temperature coefficient i d = -250 a, referenced to 25c -- -0.1 -- v/c i dss ze ro g ate voltage drain current v ds = -1 00 v, v gs = 0 v -- -- -1 a v ds = - 8 0 v, t c = 125c - - -- -10 a i gssf ga t e-body leakage current, forward v gs = -30 v , v ds = 0 v - - -- -100 na i gssr ga t e-body leakage current, reverse v gs = 30 v , v ds = 0 v - - -- 100 na on ch aracteristics v gs( t h) gat e t hreshold voltage v ds = v gs , i d = -250 a -2.0 -- -4.0 v r ds( o n) stat ic drain-source on-resistance v gs = -10 v , i d = - 3 .3 a -- 0.41 0.53 ? g fs forward t ransconductance v ds = - 4 0 v, i d = - 3 .3 a -- 4.1 -- s dyna mi c characteristics c iss in p ut capacitance v ds = - 2 5 v, v gs = 0 v , f = 1.0 mhz -- 360 470 pf c oss out put capacitance -- 120 155 pf c rss revers e t ransfer capacitance -- 30 40 pf switch ing characteristics t d(on ) turn- on delay time v dd = -50 v , i d = - 8 .0 a, r g = 25 ? -- 1 1 30 ns t r tu rn- on rise time -- 110 230 ns t d(of f) tu r n-off delay time -- 20 50 ns t f tu r n-off fall time -- 35 80 ns q g to ta l gate charge v ds = - 8 0 v, i d = - 8 .0 a, v gs = -10 v -- 12 15 nc q gs gat e- source charge -- 3.0 -- nc q gd gat e- drain charge -- 6.4 -- nc dr ai n-source diode characteristics and maximum ratings i s maxi mum continuous drain-source diode forward current -- -- -6.6 a i sm maxi mum pulsed drain-source diode forward current -- -- -26.4 a v sd drain-source diode f orward voltage v gs = 0 v , i s = - 6 .6 a -- -- -4.0 v t rr re ver se recovery time v gs = 0 v , i s = - 8 .0 a, di f / dt = 100 a/ s -- 98 -- ns q rr revers e recover y charge -- 0.35 -- c fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 rev. c1 www .fairchildsemi.com 2
0.0 0.5 1. 0 1.5 2.0 2.5 3.0 10 -1 10 0 10 1 150 notes : 1. v gs = 0v 2. 250 s p ul se test 25 -i dr , rev e rse drain current [a] -v sd , sourc e- drain voltage [v] 0 5 10 15 20 25 0. 0 0. 3 0.6 0.9 1.2 1.5 note : t j = 25 v gs = - 20v v gs = - 10v r ds(on) [ ? ], drain - source on-resistance -i d , drai n current [a] 2 4681 0 10 -1 10 0 10 1 150 25 -55 notes : 1. v ds = -40v 2. 250 s p ulse test -i d , drai n c urrent [a] -v gs , gat e -source voltage [v] 10 -1 10 0 10 1 10 -2 10 -1 10 0 10 1 v gs top : -15.0 v -10.0 v -8.0 v -7.0 v -6.5 v -5.5 v -5.0 v bottom : -4.5 v notes : 1. 250 s pulse test 2. t c = 25 -i d , drai n c urrent [a] -v ds , drai n- source voltage [v] 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 v ds = -50v v ds = -20v v ds = -80v note : i d = -8.0 a -v gs , gat e- source voltage [v] q g , total g a te charge [nc] 10 -1 10 0 10 1 0 100 200 300 40 0 50 0 600 700 800 900 c iss = c gs + c gd (c ds = short ed) c oss = c ds + c gd c rss = c gd notes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capaci t ance [pf] -v ds , drain- source voltage [v] typical chara cteristics figure 5. c ap acitance characteristics figure 6. gate charge characteristics figure 3. on-resistance variation vs. drain current and gate voltage figure 4. body diode forward voltage variation vs. source current and temperature figure 2. transfer characteristics figure 1. on-region characteristics fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 rev. c1 www.fairchil dsemi.c om 3
10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -1 10 0 n o te s : 1 . z jc (t ) = 2.84 /w m a x. 2 . d uty f acto r, d = t 1 /t 2 3 . t jm - t c = p dm * z jc (t) singl e pulse d=0 . 5 0.0 2 0.2 0.0 5 0.1 0.01 z jc (t ) , therm al response t 1 , s q uare w ave pulse duration [sec] 25 50 75 100 125 150 0 1 2 3 4 5 6 7 -i d , d r ain current [a] t c , c a se temperature [ ] 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 dc 10 ms 1 ms 100 s ope r ation in this area is limited by r ds( o n) not e s : 1. t c = 25 o c 2. t j = 15 0 o c 3. s ingle pulse -i d , dr a in current [a] -v ds , d r ain-source voltage [v] -100 - 50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 not e s : 1. v gs = -10 v 2 . i d = - 3 .3 a r ds( o n) , ( n ormalized) drain-source on-resistance t j , ju nc tion temperature [ o c] -100 - 50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 not e s : 1. v gs = 0 v 2 . i d = -2 5 0 a -bv dss , (n o rmalized) drain-source breakdown voltage t j , j un ction temperature [ o c] typical c haracteristics (conti nued) fi g ure 9. maximum safe operating area figure 10. maximum drain current vs. case temperature figure 7. breakdown voltage variation vs. temperature figure 8. on-resistance variation vs. temperature figure 11. transient thermal response curve t 1 p dm t 2 fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 rev. c1 www .fairchildsemi.com 4
cha r ge v gs -10v q g q gs q gd -3ma v gs dut v ds 300nf 50k 200nf 12 v same ty pe as dut cha r ge v gs -10v q g q gs q gd -3ma v gs dut v ds 300nf 50k 200nf 12 v same ty pe as dut v ds v gs 10% 90% t d(on ) t r t on t off t d(of f) t f v dd -10v v ds r l dut r g v gs v ds v gs 10% 90% t d(on ) t r t on t off t d(of f) t f v dd -10v v ds r l dut r g v gs e as =li as 2 ---- 2 1 -- -- ---------------- bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) ti m e -10v dut r g l i d t p e as =li as 2 ---- 2 1 e as =li as 2 ---- 2 1 -- -- 2 1 -- ------------------ bv dss -v dd bv dss v dd v ds bv dss t p v dd i as v ds (t) i d (t) ti m e -10v dut r g l l i d i d t p ga t e charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 rev. c1 www .fairchildsemi.com 5
peak di ode recovery dv/dt test circuit & waveforms dut v ds + _ drive r r g comp l iment of dut (n-channel) v gs ? dv / dt controlled by r g ?i sd cont r olled by pulse period v dd l i sd 10v v gs ( dr i ver ) i sd ( dut ) v ds ( dut ) v dd body d iode forward voltage drop v sd i fm , bo dy di ode forward current body diode reverse current i rm body d iode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ drive r r g comp l iment of dut (n-channel) v gs ? dv / dt controlled by r g ?i sd cont r olled by pulse period v dd l l i sd 10v v gs ( dr i ver ) i sd ( dut ) v ds ( dut ) v dd body d iode forward voltage drop v sd i fm , bo dy di ode forward current body diode reverse current i rm body d iode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period -------------------------- fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 rev. c1 www .fairchildsemi.com 6
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fqd8p10 tm_f085 100v p-channel mosfet FQD8P10TM_f085 rev. c1 www .fairchil dsemi.com 7
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