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ds07-16303-2e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos fr30 series MB91121 MB91121 n description the MB91121 is a microcontroller with a 32-bit risc cpu (fr family *) as the core, incorporating a variety of i/o resources, a bus control facility, and a multiplier-accumulator (simplified dsp) with internal program ram for built-in control applications which require advanced, high-speed cpu processing. while being based on external bus access for supporting a vast address space accessed by the 32-bit cpu, it contains 1 k bytes of instruction cache memory and 4 k bytes of ram (8 k bytes when the dsp is not used) for speeding up the execution of instructions by the cpu. in this way, the device is designed for built-in applications which require high performance and processing power of the cpu, such as digital camera, navigation system, and high-performance fax, and printer controls. * : fr family stands for fujitsu risc controller. n features 1. fr cpu ? 32-bit risc, load/store architecture, 5-stage pipeline ? operating clock frequency : internal 50 mhz/external 25 mhz (pll used at source oscillation 12.5 mhz) ? general purpose registers : 32 bits 16 ? 16-bit fixed length instructions (basic instructions) , 1 instruction/1 cycle ? memory to memory transfer, bit processing, barrel shifter processing : optimized for embedded applications (continued) n pac k ag e 120-pin plastic lqfp (fpt-120p-m21)
MB91121 2 (continued) ? function entrance/exit instructions, multiple load/store instructions of register contents, instruction systems supporting high level languages ? register interlock functions, efficient assembly language coding ? branch instructions with delay slots : reduced overhead time in branch executions ? internal multiplier/supported at instruction level signed 32-bit multiplication : 5 cycles signed 16-bit multiplication : 3 cycles ? interrupt (push pc and ps) : 6 cycles, 16 priority levels 2. bus interface ? clock doublure : internal 50 mhz, external bus 25 mhz operation ? 25-bit address bus (32 mbytes memory space) ? 8/16-bit data bus ? basic external bus cycle : 2 clock cycles ? chip select outputs for setting down to a minimum memory block size of 64 kbytes : 6 ? interface supported for various memory technologies dram interface (area 4 and 5) ? automatic wait cycle insertion : flexible setting, from 0 to 7 for each area ? unused data/address pins can be configured us input/output ports ? little endian mode supported (select 1 area from area 1 to 5) 3. dram interface ? 2 banks independent control (area 4 and 5) ? double cas dram (normal dram i/f) /single cas dram/hyper dram ? basic bus cycle : normally 5 cycles, 2-cycle access possible in high-speed page mode ? programmable waveform : automatic 1-cycle wait insertion to ras and cas cycles ?dram refresh cbr refresh (interval time configurable by 6-bit timer) self-refresh mode ? supports 8/9/10/12-bit column address width ? 2cas/1we, 2we/1cas selective 4. dsp macros (simplified dsp) ? high-speed multiply-accumulate operation (1 machine cycle) ? data format : 16-bit fixed-point (16 16 + 40 bits) ? instruction area : 256 words 16 bits ? data area : 64 words 16 bits 1 set, 1024 words 16 bits 2 sets (banks) ? capable of rounding and saturation processing ? number of terms in addition : up to 32 terms ? instructions : mac, str, and jmp instructions ? delay processing : capable of free transfer within 32 words ? fixed-point system : capable of selection from among q12 to q15 ? program execution control : capable of externally selecting eight calculation programs ? variable monitoring : capable of monitoring calculation results of up to 4 words without stopping the program ? efficient data variable areas : two banks of data variable areas provided, enabling the cpu to execute a dsp calculation program using one bank while accessing a data variable in the other. 5. cache memory ? 1 k-byte instruction cache ? 2-way set-associative configuration ? 32 blocks/way, 4 entries (4 words) /block
MB91121 3 (continued) ? lock feature: keeping a specific program code resident in the cache 6. dmac (dma controller) ? 8 channels ? transfer incident/external pins/uart interrupt requests/dsp macros/software start ? transfer sequence : step transfer/block transfer/burst transfer/continuous transfer ? transfer data length : 8 bits/16 bits/32 bits selective ? interrupt request enables temporary stop operation 7. uart ? 3 independent channels ? full-duplex double buffer ? data length : 7 bits to 9 bits (non-parity) , 6 bits to 8 bits (parity) ? asynchronous (start-stop system) , clk-synchronized communication selective ? multi-processor mode ? internal 16-bit timer (u-timer) operating as a proprietary baud rate generator : generates any given baud rate ? use external clock can be used as a transfer clock ? error detection : parity, frame, overrun 8. a / d converter ( successive approximation conversion type ) ? 10-bit resolution, 8 channels ? successive approximation type : conversion time of 5.6 m s at 25 mhz ? internal sample and hold circuit ? conversion mode : single conversion/scanning conversion/repeated conversion selective ? start : software/external trigger/internal timer selective 9. reload timer ? 16-bit timer : 3 channels ? internal clock : 2 clock cycle resolution, divide by 2/8/32 selective 10. other interval timers ? 16-bit timer : 3 channels (u-timer) ? pwm timer : 4 channels ? watchdog timer : 1 channel 11. bit search module ? first bit transition 1 or 0 from msb can be detected in 1 cycle 12. interrupt controller ? external interrupt input : non-maskable interrupt (nmi ) , normal interrupt 8 (int0 to int7) ? internal interrupt incident : uart, dma controller (dmac) , a/d converter, u-timer, delayed interrupt module and dsp macros ? priority levels of interrupts are programmable except for non-maskable interrupt (in 16 steps) others 1. reset cause ? power-on reset/watchdog timer/software reset/external reset 2. low-power consumption mode ? sleep mode/stop mode 3. clock control ? gear function : operating clocks for cpu and peripherals are independently selective gear clock can be selected from 1/1, 1/2, 1/4 and 1/8 (or 1/2, 1/4, 1/8 and 1/16) however, operating frequency for peripherals is less than 25 mhz.
MB91121 4 (continued) 4. packages : lqfp-120 5. cmos technology (0.35 m m) 6. power supply voltage 3.3 v 0.3 v
MB91121 5 n pin assignment 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pb5/cs1l pb6/cs1h pb7/dw1 v cc cs0 pa1/cs1 pa2/cs2 pa3/cs3 pa4/cs4 pa5/cs5 pa6/clk nmi md3 rst v ss md0 md1 md2 p80/rdy p81/bgrnt p82/brq rd wr0 p85/wr1 p20/d16 p21/d17 p22/d18 p23/d19 p24/d20 p25/d21 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 pg5/int5/trg1 pg4/int4/trg0 pg3/int3 pg2/int2 pg1/int1 pg0/int0 v cc ph7/ocpa3 ph6/ocpa2 ph5/ocpa1 ph4/ocpa0 an7 an6 an5 an4 an3 an2 an1 an0 av ss /avrl avrh av cc a24 a23/p67 a22/p66 a21/p65 a20/p64 a19/p63 a18/p62 a17/p61 p26/d22 p27/d23 d24 d25 d26 d27 d28 d29 d30 d31 v ss a00 a01 a02 a03 a04 a05 a06 a07 v cc a08 a09 a10 a11 a12 a13 a14 a15 v ss p60/a16 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 ras1/pb4 dw0/pb3 csoh/pb2 csol/pb1 ras0/pb0 v cc x0 x1 v ss pi1/eop2/atg pi0/dack2 pe7/dreq2 pe6/eop1 pe5/dack1 pe4/dreq1 pe3/eop0 pe2/dack0 pe1/dreq0 pe0/sc2 pf7/so2 pf6/si2 pf5/sc1 pf4/so1 pf3/si1 pf2/sc0 pf1/so0 v ss pf0/si0 pg7/int7/trg3 pg6/int6/trg2 (top view) (fpt-120p-m21)
MB91121 6 n pin description pin no. pin name circuit type function 1 2 3 4 5 6 7 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 f bits 16 to 23 for the external address bus. when not used for the address bus, these pins serve as ports (p60 to p67) . 8 a24 m bit 24 for the external address bus 9av cc ? a/d converter v cc power supply 10 avrh ? a/d converter reference voltage (high potential side) the v cc pin must be applied with voltage equal to or higher than the voltage at this pin (avrh) when the avrh pin is turned on or off. 11 av ss /avrl ? a/d converter v ss power supply or reference voltage (low potential side) 12 to 19 an0 to an7 n [an0 to an7] a/d converter analog input. this function is enabled with the aic register set for the analog input. 20 to 23 ocpa0/ph4 ocpa1/ph5 ocpa2/ph6 ocpa3/ph7 f [ocpa0 to ocpa3] pwm timer output. this function is enabled with the pwm timer output flag set to enabled. [ph4 to ph7] general-purpose i/o port 25 to 32 int0/pg0 int1/pg1 int2/pg2 int3/pg3 int4/pg4/trg0 int5/pg5/trg1 int6/pg6/trg2 int7/pg7/trg3 f [int0 to int7] external inter- rupt request input since these inputs are used dur- ing their respective input opera- tions, the output by the other function must remain off unless used intentionally. [trg0 to trg3] pwm timer external trigger input [pg0 to pg7] general-purpose i/o port 33 si0/pf0 f [si0] uart0 data input. since this input is used whenever uart0 is in input operation, the output by the other function must remain off unless used intentionally. [pf0] general-purpose i/o port 35 so0/pf1 f [so0] uart0 data output. this function is enabled with the uart0 data output flag set to enabled. [pf1] general-purpose i/o port. this function is enabled with the uart0 data output flag set to disabled. 36 sc0/pf2 f [sc0] uart0 clock input/output. the clock output is enabled with the uart0 clock output flag set to enabled. [pf2] general-purpose i/o port. this function is enabled with the uart0 clock output flag set to disabled. (continued)
MB91121 7 37 si1/pf3 f [si1] uart1 data input. since this input is used whenever uart1 is in input operation, the output by the other function must remain off unless used intentionally. [pf3] general-purpose i/o port 38 so1/pf4 f [so1] uart1 data output. this function is enabled with the uart1 data output flag set to enabled. [pf4] general-purpose i/o port. this function is enabled with the uart1 data output flag set to disabled. 39 sc1/pf5 f [sc1] uart1 clock input/output. the clock output is enabled with the uart1 clock output flag set to enabled. [pf5] general-purpose i/o port. this function is enabled with the uart1 clock output flag set to disabled. 40 si2/pf6 f [si2] uart2 data input. since this input is used whenever uart2 is in input operation, the output by the other function must remain off unless used intentionally. [pf6] general-purpose i/o port 41 so2/pf7 f [so2] uart2 data output. this function is enabled with the uart2 data output flag set to enabled. [pf7] general-purpose i/o port. this function is enabled with the uart2 data output flag set to disabled. 42 sc2/pe0 f [sc2] uart2 clock input/output. the clock output is enabled with the uart2 clock output flag set to enabled. [pe0] general-purpose i/o port. this function is enabled with the uart2 clock output flag set to disabled. 43 dreq0/pe1 f [dreq0] dma external transfer request input (ch0) . since this input is used whenever the dma external transfer request has been selected as a dma transfer trigger event, the output by the other function must remain off unless used intentionally. [pe1] general-purpose i/o port 44 dack0/pe2 f [dack0] dmac external transfer request acknowledge output (ch0) . this function is enabled with the dmac transfer request ac- knowledge output flag set to enabled. [pe2] general-purpose i/o port. this function is enabled with the dmac transfer request acknowledge output flag or dack0 output flag set to disabled. 45 eop0/pe3 f [eop0] dmac eop output (ch0) . this function is enabled with the eop output flag set to enabled. [pe3] general-purpose i/o port 46 dreq1/pe4 f [dreq1] dma external transfer request input (ch1) . since this input is used whenever the dma external transfer request has been selected as a dma transfer trigger event, the output by the other function must remain off unless used intentionally. [pe4] general-purpose i/o port (continued) pin no. pin name circuit type function (continued)
MB91121 8 47 dack1/pe5 f [dack1] dmac external transfer request acknowledge output (ch1) . this function is enabled with the dmac transfer request ac- knowledge output flag set to enabled. [pe5] general-purpose i/o port. this function is enabled with the dmac transfer request acknowledge output flag or dack0 output flag set to disabled. 48 eop1/pe6 f [eop1] dmac eop output (ch1) . this function is enabled with the eop output flag set to enabled. [pe6] general-purpose i/o port 49 dreq2/pe7 f [dreq2] dma external transfer request input (ch2) . since this input is used whenever the dma external transfer request has been selected as a dma transfer trigger event, the output by the other function must remain off unless used intentionally. [pe7] general-purpose i/o port 50 dack2/pi0 f [dack2] dmac external transfer request acknowledge output (ch2) . this function is enabled with the dmac transfer request ac- knowledge output flag set to enabled. [pi0] general-purpose i/o port. this function is enabled with the dmac transfer request acknowledge output flag or dack0 output flag set to "disabled". 51 eop2/atg /pi1 f [eop2] dmac eop output (ch2) . this function is enabled with the eop output flag set to enabled. [atg ] a/d converter external trigger input. since this input is used whenever the a/d converter external trigger signal has been se- lected as an a/d trigger event, the output by the other function must remain off unless used intentionally. [pi1] general-purpose i/o port. this function is enabled with the dmac transfer termination signal output flag set to disabled. 53 54 x1 x0 a clock (oscillation) input. clock (oscillation) output. 56 57 58 59 60 ras0/pb0 csol/pb1 csoh/pb2 dw0 /pb3 ras1/pb4 f ras output of dram bank 0 casl output of dram bank 0 cash output of dram bank 0 we output of dram bank 0 (low active) ras output of dram bank 1 [pb0 to pb3] can serve as a port when not used for signal output. 61 62 63 cs1l/pb5 cs1h/pb6 dw1 /pb7 f casl output of dram bank 1 cash output of dram bank 1 we output of dram bank 1 (low active) [pb5 to pb7] can serve as a port when not used for signal output. 65 cs0 m chip select 0 output (low active) . (continued) pin no. pin name circuit type function (continued)
MB91121 9 66 67 68 69 70 cs1 /pa1 cs2 /pa2 cs3 /pa3 cs4 /pa4 cs5 /pa5 f chip select 1 output (low active) . chip select 2 output (low active) . chip select 3 output (low active) . chip select 4 output (low active) . chip select 5 output (low active) . [pa1 to pa5] can serve as a port when not used for signal output. 71 clk/pa6 f system clock output. this pin outputs the same clock frequency as the external bus operating frequency. [pa6] can serve as a port when not used for signal output. 72 nmi h nmi (non maskable interrupt) input (low active) . 73 md3 g mode pin 3. connect this pin directly to the v cc or v ss pin. 74 rst b external reset input. 76 77 78 md0 md1 md2 g mode pins 0 to 2. these pins are set to mcu basic operation modes. connect this pin directly to the v cc or v ss pin. 79 rdy/p80 c external ready signal input. this pin inputs 0 when the bus cycle being executed is not completed. it can serve as a port when not used for that input. 80 bgrnt /p81 f external bus release request acknowledge output. this pin out- puts the l signal when the eternal bus has been released. the pin can serve as a port when not used for that output. 81 brq/p82 c external bus release request input. input 1 to this pin to release the external bus. the pin can serve as a port when not used for that input. 82 rd m external bus read strobe. 83 wr0 m external bus write strobe. the control signals and data bus byte locations have the following relationships. note : wr1 remains in the hi-z state during a reset. for use with a 16-bit bus width, add an external pull-up resistor. 84 wr1 /p85 f 85 86 87 88 89 90 91 92 d16/p20 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 c external data bus bits 16 to 23. these pins can be used as ports (p20 to p27) when the external bus width has been set to 8 bits. pin no. pin name circuit type function 16-bit bus width 8-bit bus width d31 to d24 wr0 wr0 d23 to d16 wr1 (usable as port) (continued) (continued)
MB91121 10 note : in most of the above pins, i/o port and resource i/o are multiplexed xxxx/pxx. in case of conflict between output of i/o port and resource i/o, priority is always given to the output of resource i/o. 93 94 95 96 97 98 99 100 d24 d25 d26 d27 d28 d29 d30 d31 c external data bus bits 24 to 31. 102 103 104 105 106 107 108 109 111 112 113 114 115 116 117 118 a00 a01 a02 a03 a04 a05 a06 a07 a08 a09 a10 a11 a12 a13 a14 a15 f external address bus bits 00 to 15. 120 a16/p60 external address bus bit 16. this pin can serve as a port (p60) when not used as the address bus. 24 55 64 110 v cc ? power supply pin for digital circuit. 34 52 75 101 119 v ss ? earth level for digital circuit. pin no. pin name circuit type function (continued)
MB91121 11 n dram control pin pin name data bus 16-bit mode data bus 8-bit mode remarks 2cas/1wr mode 1cas/2wr mode ? ras0 area 4 ras area 4 ras area 4 ras correspondence of l h to lower address 1 bit (a0) in data bus 16-bit mode l : 0 h : 1 casl : cas which a0 corresponds to 0 area cash : cas which a0 corresponds to 1 area wel : we which a0 corresponds to 0 area weh : we which a0 corresponds to 1 area ras1 area 5 ras area 5 ras area 5 ras cs0l area 4 casl area 4 cas area 4 cas cs0h area 4 cash area 4 wel area 4 cas cs1l area 5 casl area 5 cas area 5 cas cs1h area 5 cash area 5 wel area 5 cas dw0 area 4 we area 4 weh area 4 we dw1 area 5 we area 5 weh area 5 we
MB91121 12 n i/o circuit type circuit type circuit remarks a oscillation feedback resistance 1 m w approx. b cmos level hysteresis input without standby control with pull-up resistance c cmos level i/o with standby control n analog input (continued) x1 x0 standby control signal clock input v ss v cc digital input p-channel type tr n-channel type tr diffuse resistor standby control digital output digital output digital input analog input
MB91121 13 f cmos level output cmos level hysteresis input with standby control g cmos level input without standby control h cmos level hysteresis input without standby control m cmos level output circuit type circuit remarks standby control digital output digital output digital input digital input digital input digital output digital output (continued)
MB91121 14 n handling devices ? preventing latchup in cmos ics, applying voltage higher than v cc or lower than v ss to input/output pin or applying voltage over rating across v cc and v ss may cause latchup. this phenomenon rapidly increases the power supply current, which may result in thermal breakdown of the device. make sure to prevent the voltage from exceeding the maximum rating. take care that the analog power supply (av cc avr) and the analog input do not exceed the digital power supply (v cc ) when the analog power supply turned on or off. ? treatment of unused pins unused pins left open may cause malfunctions. make sure to connect them to pull-up or pull-down resistors. ? external reset input it takes at least 5 machine cycle to input l level to the rst pin and to ensure inner reset operation properly. ? remarks for external clock operation when external clock is selected, supply it to x0 pin generally, and simultaneously the opposite phase clock to x0 must be supplied to x1 pin. however, in this case the stop mode must not be used (because x1 pin stops at h output in stop mode) . and can be used to supply only to x0 pin with 5 v power supply at 12.5 mhz and less than. ?power supply pins when there are several v cc and v ss pins, each of them is equipotentially connected to its counterpart inside of the device, minimizing the risk of malfunctions such as latch up. to further reduce the risk of malfunctions, to prevent emi radiation, to prevent strobe signal malfunction resulting from creeping-up of ground level and to observe the total output current standard, connect all v cc and v ss pins to the power supply or gnd. it is preferred to connect v cc and v ss of MB91121 to power supply with minimal impedance possible. it is also recommended to connect a ceramic capacitor as a bypass capacitor of about 0.1 m f between v cc and v ss at a position as close as possible to MB91121. x0 x1 open MB91121 x0 x1 MB91121 using an external clock (normal) note: can not be used stop mode (oscillation stop mode). using an external clock (can be used at 12.5 mhz and less than.) ? using an external clock
MB91121 15 ? crystal oscillator circuit noises around x0 and x1 pins may cause malfunctions of MB91121. in designing the pc board, layout x0, x1 and crystal oscillator (or ceramic oscillator) and bypass capacitor for grounding as close as possible. it is strongly recommended to design pc board so that x1 and x0 pins are surrounded by grounding area for stable operation. ? treatment of n.c. pins make sure to leave n.c. pins open. ? mode setting pins (md0 to md3) connect mode setting pins (md0 to md3) directly to v cc or v ss . arrange each mode setting pin and v cc or v ss patterns on the printed circuit board as close as possible and make the impedance between them minimal to prevent mistaken entrance to the test mode caused by noises. ? turning on the power supply when turning on the power supply, never fail to start from setting the rst pin to l level. and after the power supply voltage goes to v cc level, at least after ensuring the time for 5 machine cycle, then set to h level. ? pin condition at turning on the power supply the pin condition at turning on the power supply is unstable. the circuit starts being initialized after turning on the power supply and then starting oscillation and then the operation becomes stable. ? source oscillation input at turning on the power supply at turning on the power supply, never fail to input the clock before cancellation of the oscillation stabilizing waiting. ? the device contains registers which are initialized only at a power-on reset. when it is expected to initialize them, recycle the power to execute a power-on reset. ? even when the a/d converter is not used, make the connections : av cc = v cc , av ss = v ss .
MB91121 16 n block diagram bit search module instruction cache (1 kb) d -bus (32 bit) i -bus (16 bit) c-bus (32 bit) r -bus (16 bit) clock control unit (watct dog timer) interrupt control unit 10 bit a/d converter (8 ch) reload timer (3 ch) port bus converter (32 bit ? 16 bit) port 0 to port b uart (3 ch) with baud rate timer pwm timer (4 ch) dmac (8 ch) (harvard ? princeton) fr cpu x0 x1 rst dreq0 to dreq2 dack0 to dack2 eop0 to eop2 d16 to d31 a00 to a24 rdy wr0 to wr1 rdy clk cs0 to cs5 brq bgrnt si0 to si2 so0 to so2 sc0 to sc2 int0 to int7 nmi 8 ras0 ras1 cs0l cs0h cs1l cs1h dw0 dw1 an0 to an7 av cc avrh av ss / avrl 8 dram controller 3 3 3 ocpa0 to ocpa3 trg0 to trg3 4 4 bus controller 6 2 25 16 ram (4 kb) (embedded ram 4 ) soft dma start circuit 3 3 3 strg dsp macro bus converter note : pins are display for functions (actually some pins are multiplexer) . when using realos, time control should be done by using external interrupt or inner timer.
MB91121 17 n cpu core 1. memory space the fr family has a logical address space of 4 gbytes (2 32 bytes) and the cpu linearly accesses the memory space. ? direct addressing area the following areas on the memory space are assigned to direct addressing area for i/o. in these areas, an address can be specified in a direct operand of a code. direct areas consists of the following areas dependent on accessible data sizes. byte data access : 000 h to 0ff h half word data access : 000 h to 1ff h word data access : 000 h to 3ff h ? memory space external rom/external bus mode i/o i/o access inhibited embedded ram 4 kb y-ram1 y-ram1 access inhibited dsp macros access inhibited external area direct addressing area see n i/o map 0000 0000 h 0000 0400 h 0000 0800 h 0000 1000 h 0000 2000 h 0000 2800 h 0000 3000 h 0000 f000 h 0000 f300 h 0001 0000 h ffff ffff h ? usable as ram in the dsp macros ybank unused mode. ? usable as ram when dsp macros is not used.
MB91121 18 2. registers the fr family has two types of registers; dedicated registers embedded on the cpu and general-purpose registers on memory. ? dedicated registers program counter (pc) : 32-bit length, indicates the location of the instruction to be executed. program status (ps) : 32-bit length, register for storing register pointer or condition codes table base register (tbr) : holds top address of vector table used in eit (exceptional/interrupt/trap) processing. return pointer (rp) : holds address to resume operation after returning from a subroutine. system stack pointer (ssp) : indicates system stack space. users stack pointer (usp) : indicates users stack space. multiplication/division result register (mdh/mdl) : 32-bit length, register for multiplication/division ? program status (ps) the ps register is for holding program status and consists of a condition code register (ccr) , a system condition code register (scr) and a interrupt level mask register (ilm) . 32 bit initial value pc program counter xxxx xxxx h indeterminate ps program status tbr table base register 0 0 0 f fc0 0 h rp return pointer xxxx xxxx h indeterminate ssp system stack pointer 0000 0000 h usp users stack pointer xxxx xxxx h indeterminate mdh xxxx xxxx h indeterminate multiplication/division result register mdl xxxx xxxx h indeterminate 312019181716 109876543210 ps ? ilm4 ilm3 ilm2 ilm1 ilm0 ? d1 d0 t ?? sinzvc ilm scr ccr
MB91121 19 ? condition code register (ccr) s-flag : specifies a stack pointer used as r15. i-flag : controls user interrupt request enable/disable. n-flag : indicates sign bit when division result is assumed to be in the 2s complement format. z-flag : indicates whether or not the result of division was 0. v-flag : assumes the operand used in calculation in the 2s complement format and indicates whether or not overflow has occurred. c-flag : indicates if a carry or borrow from the msb has occurred. ? system condition code register (scr) t-flag : specifies whether or not to enable step trace trap. ? interrupt level mask register (ilm) ilm4 to ilm0 : register for holding interrupt level mask value. the value held by this register is used as a level mask. when an interrupt request issued to the cpu is higher than the level held by ilm, the interrupt request is accepted. ilm4 ilm3 ilm2 ilm1 ilm0 interrupt level high-low 00000 0 high : : : : 01000 15 : : : : 11111 31 low
MB91121 20 n general-purpose registers r0 to r15 are general-purpose registers embedded on the cpu. these registers functions as an accumulator and a memory access pointer (field for indicating address) . of the above 16 registers, following registers have special functions. to support the special functions, part of the instruction set has been sophisticated to have enhanced functions. r13 : virtual accumulator (ac) r14 : frame pointer (fp) r15 : stack pointer (sp) upon reset, values in r0 to r14 are not fixed. value in r15 is initialized to be 0000 0000 h (ssp value) . ? register bank structure 32 bits initial value r0 xxxx xxxx h r1 r12 r13 ac (accumulator) r14 fp (frame pointer) xxxx xxxx h r15 sp (stack pointer) 0000 0000 h
MB91121 21 n setting mode 1. pin ? mode setting pins and modes * : MB91121 does not support single-chip mode. 2. registers ? mode setting registers (modr) and modes ? bus mode setting bits and functions note : because of without internal rom, MB91121 allows 10 b setting value only. mode setting pins mode name reset vector access area external data bus width bus mode md3 md2 md1 md0 1000external vector mode 0external 8 bits external rom/external bus mode 1001external vector mode 1external 16 bits 1010 ??? inhibited 1011internal vector mode internal (mode register) single-chip mode* 11 ?? ? ? ? inhibited 0 ??? ? ? ? inhibited m1 m0 functions note 0 0 single-chip mode 0 1 internal rom/external bus mode 1 0 external rom/external bus mode 11 ? inhibited w : write only x : indeterminate * : always write 0 except for m1 and m0. m1 m0 ****** initial value access xxxx xxxx b w address 0000 07ff h bus mode setting bit
MB91121 22 n i/o map address register name (abbreviated) register name read/write initial value 0000 h (vacancy) 0001 h pdr2 port 2 data register r/w xxxxxxxx b 0002 h to 0004 h (vacancy) 0005 h pdr6 port 6 data register r/w xxxxxxxx b 0006 h (vacancy) 0007 h 0008 h pdrb port b data register r/w xxxxxxxx b 0009 h pdra port a data register r/w - xxxxxx - b 000a h (vacancy) 000b h pdr8 port 8 data register r/w -- x -- xxx b 000c h to 0011 h (vacancy) 0012 h pdre port e data register r/w xxxxxxxx b 0013 h pdrf port f data register r/w xxxxxxxx b 0014 h pdrg port g data register r/w xxxxxxxx b 0015 h pdrh port h data register r/w xxxx ---- b 0016 h pdri port i data register r/w ------ xx b 0017 h to 001b h (vacancy) 001c h ssr0 serial status register 0 r/w 00001 - 00 b 001d h sidr0/sodr0 serial input register 0/serial output register 0 r/w xxxxxxxx b 001e h scr0 serial control register 0 r/w 00000100 b 001f h smr0 serial mode register 0 r/w 0 0 -- 0 - 00 b 0020 h ssr1 serial status register 1 r/w 00001 - 00 b 0021 h sidr1/sodr1 serial input register 1/serial output register 1 r/w xxxxxxxx b 0022 h scr1 serial control register 1 r/w 00000100 b 0023 h smr1 serial mode register 1 r/w 0 0 -- 0 - 00 b 0024 h ssr2 serial status register 2 r/w 00001 - 00 b 0025 h sidr2/sodr2 serial input register 2/serial output register 2 r/w xxxxxxxx b 0026 h scr2 serial control register 2 r/w 00000100 b 0027 h smr2 serial mode register 2 r/w 0 0 -- 0 - 00 b (continued)
MB91121 23 0028 h tmrlr0 16-bit reload register ch. 0 w xxxxxxxx b 0029 h xxxxxxxx b 002a h tmr0 16-bit timer register ch. 0 r xxxxxxxx b 002b h xxxxxxxx b 002c h (vacancy) 002d h 002e h tmcsr0 16-bit reload timer control status register ch. 0 r/w ---- 0000 b 002f h 00000000 b 0030 h tmrlr1 16-bit reload register ch. 1 w xxxxxxxx b 0031 h xxxxxxxx b 0032 h tmr1 16-bit timer register ch. 1 r xxxxxxxx b 0033 h xxxxxxxx b 0034 h (vacancy) 0035 h 0036 h tmcsr1 16-bit reload timer control status register ch. 1 r/w ---- 0000 b 0037 h 00000000 b 0038 h adcr a/d converter data register r ------ xx b 0039 h xxxxxxxx b 003a h adcs a/d converter control status register r/w 00000000 b 003b h 00000000 b 003c h tmrlr2 16-bit reload register ch. 2 w xxxxxxxx b 003d h xxxxxxxx b 003e h tmr2 16-bit timer register ch. 2 r xxxxxxxx b 003f h xxxxxxxx b 0040 h (vacancy) 0041 h 0042 h tmcsr2 16-bit reload timer control status register ch. 2 r/w ---- 0000 b 0043 h 00000000 b 0044 h to 004f h (vacancy) 0050 h strg soft dma start r/w ------ 00 b 0051 h to 0077 h (vacancy) (continued) address register name (abbreviated) register name read/write initial value
MB91121 24 0078 h utim0/utimr0 u-timer register ch. 0/reload register ch. 0 r/w 00000000 b 0079 h 00000000 b 007a h (vacancy) 007b h utimc0 u-timer control register ch. 0 r/w 0 -- 00001 b 007c h utim1/utimr1 u-timer register ch. 1/reload register ch. 1 r/w 00000000 b 007d h 00000000 b 007e h (vacancy) 007f h utimc1 u-timer control register ch. 1 r/w 0 -- 00001 b 0080 h utim2/utimr2 u-timer register ch. 2/reload register ch. 2 r/w 00000000 b 0081 h 00000000 b 0082 h (vacancy) 0083 h utimc2 u-timer control register ch. 2 r/w 0 -- 00001 b 0084 h to 0093 h (vacancy) 0094 h eirr external interrupt cause register r/w 00000000 b 0095 h enir interrupt enable register r/w 00000000 b 0096 h to 0097 h (vacancy) 0098 h elvr external interrupt request level setting register 0099 h r/w 00000000 b 009a h to 00d1 h (vacancy) 00d2 h ddre port e data direction register w 00000000 b 00d3 h ddrf port f data direction register w 00000000 b 00d4 h ddrg port g data direction register w 00000000 b 00d5 h ddrh port h data direction register w 0000 ---- b 00d6 h ddri port i data direction register w ------ 00 b 00d7 h to 00db h (vacancy) 00dc h gcn1 general control register 1 r/w 00110010 b 00dd h 00010000 b 00de h (vacancy) 00df h gcn2 general control register 2 r/w 00000000 b (continued) address register name (abbreviated) register name read/write initial value
MB91121 25 00e0 h ptmr0 pwm timer register r 11111111 b 00e1 h 11111111 b 00e2 h pcsr0 pwm cycle setting register w xxxxxxxx b 00e3 h xxxxxxxx b 00e4 h pdut0 pwm duty setting register w xxxxxxxx b 00e5 h xxxxxxxx b 00e6 h pcnh0 pwm control status register h r/w 0000000 - b 00e7 h pcnl0 pwm control status register l r/w 00000000 b 00e8 h ptmr1 pwm timer register r 11111111 b 00e9 h 11111111 b 00ea h pcsr1 pwm cycle setting register w xxxxxxxx b 00eb h xxxxxxxx b 00ec h pdut1 pwm duty setting register w xxxxxxxx b 00ed h xxxxxxxx b 00ee h pcnh1 pwm control status register h r/w 0000000 - b 00ef h pcnl1 pwm control status register l r/w 00000000 b 00f0 h ptmr2 pwm timer register r 11111111 b 00f1 h 11111111 b 00f2 h pcsr2 pwm cycle setting register w xxxxxxxx b 00f3 h xxxxxxxx b 00f4 h pdut2 pwm duty setting register w xxxxxxxx b 00f5 h xxxxxxxx b 00f6 h pcnh2 pwm control status register h r/w 0000000 - b 00f7 h pcnl2 pwm control status register l r/w 00000000 b 00f8 h ptmr3 pwm timer register r 11111111 b 00f9 h 11111111 b 00fa h pcsr3 pwm cycle setting register w xxxxxxxx b 00fb h xxxxxxxx b 00fc h pdut3 pwm duty setting register w xxxxxxxx b 00fd h xxxxxxxx b 00fe h pcnh3 pwm control status register h r/w 0000000 - b 00ff h pcnl3 pwm control status register l r/w 00000000 b 0100 h to 01ff h (vacancy) (continued) address register name (abbreviated) register name read/write initial value
MB91121 26 0200 h dpdp dmac parameter descriptor pointer r/w xxxxxxxx b 0201 h xxxxxxxx b 0202 h xxxxxxxx b 0203 h x0000000 b 0204 h dacsr dmac control status register r/w 00000000 b 0205 h 00000000 b 0206 h 00000000 b 0207 h 00000000 b 0208 h datcr dmac pin control register r/w xxxxxxxx b 0209 h xxxx0 0 0 0 b 020a h xxxx0 0 0 0 b 020b h xxxx0 0 0 0 b 020c h to 020f h (vacancy) 0210 h ofas dsp macro register r/w ---- 0000 b 0211 h 00000000 b 0212 h strs ---- 0000 b 0213 h 00000000 b 0214 h ofsc 0000 --- 0 b 0215 h (vacancy) 0216 h ofss dsp macro register r/w 00000000 b 0217 h y-bankc r/w 0 -- 00000 b 0218 h ofsd r/w 00000000 b 0219 h 00000000 b 021a h dsp-pc r/w xxxxxxxx b 021b h dsp-csr r/w 00000000 b 021c h dsp-ly r/w xxxxxxxx b 021d h xxxxxxxx b 021e h dsp-ot0 r xxxxxxxx b 021f h xxxxxxxx b 0220 h dsp-ot1 r xxxxxxxx b 0221 h xxxxxxxx b 0222 h dsp-ot2 r xxxxxxxx b 0223 h xxxxxxxx b (continued) address register name (abbreviated) register name read/write initial value
MB91121 27 0224 h dsp-ot3 dsp macro register r xxxxxxxx b 0225 h xxxxxxxx b 0226 h to 03e3 h (vacancy) 03e4 h ichcr instruction cache control register r/w -------- b 03e5 h -------- b 03e6 h -------- b 03e7 h -- 000000 b 03e8 h to 03ef h (vacancy) 03f0 h bsd0 bit search module 0-detection data register w xxxxxxxx b 03f1 h xxxxxxxx b 03f2 h xxxxxxxx b 03f3 h xxxxxxxx b 03f4 h bsd1 bit search module 1-detection data register r/w xxxxxxxx b 03f5 h xxxxxxxx b 03f6 h xxxxxxxx b 03f7 h xxxxxxxx b 03f8 h bsdc bit search module transition-detection data register w xxxxxxxx b 03f9 h xxxxxxxx b 03fa h xxxxxxxx b 03fb h xxxxxxxx b 03fc h bsrr bit search module detection result register r xxxxxxxx b 03fd h xxxxxxxx b 03fe h xxxxxxxx b 03ff h xxxxxxxx b 0400 h icr00 interrupt control register 0 r/w --- 11111 b 0401 h icr01 interrupt control register 1 r/w --- 11111 b 0402 h icr02 interrupt control register 2 r/w --- 11111 b 0403 h icr03 interrupt control register 3 r/w --- 11111 b 0404 h icr04 interrupt control register 4 r/w --- 11111 b 0405 h icr05 interrupt control register 5 r/w --- 11111 b 0406 h icr06 interrupt control register 6 r/w --- 11111 b 0407 h icr07 interrupt control register 7 r/w --- 11111 b (continued) address register name (abbreviated) register name read/write initial value
MB91121 28 0408 h icr08 interrupt control register 8 r/w --- 11111 b 0409 h icr09 interrupt control register 9 r/w --- 11111 b 040a h icr10 interrupt control register 10 r/w --- 11111 b 040b h icr11 interrupt control register 11 r/w --- 11111 b 040c h icr12 interrupt control register 12 r/w --- 11111 b 040d h icr13 interrupt control register 13 r/w --- 11111 b 040e h icr14 interrupt control register 14 r/w --- 11111 b 040f h icr15 interrupt control register 15 r/w --- 11111 b 0410 h icr16 interrupt control register 16 r/w --- 11111 b 0411 h icr17 interrupt control register 17 r/w --- 11111 b 0412 h icr18 interrupt control register 18 r/w --- 11111 b 0413 h icr19 interrupt control register 19 r/w --- 11111 b 0414 h icr20 interrupt control register 20 r/w --- 11111 b 0415 h icr21 interrupt control register 21 r/w --- 11111 b 0416 h icr22 interrupt control register 22 r/w --- 11111 b 0417 h icr23 interrupt control register 23 r/w --- 11111 b 0418 h icr24 interrupt control register 24 r/w --- 11111 b 0419 h icr25 interrupt control register 25 r/w --- 11111 b 041a h icr26 interrupt control register 26 r/w --- 11111 b 041b h icr27 interrupt control register 27 r/w --- 11111 b 041c h icr28 interrupt control register 28 r/w --- 11111 b 041d h icr29 interrupt control register 29 r/w --- 11111 b 041e h icr30 interrupt control register 30 r/w --- 11111 b 041f h icr31 interrupt control register 31 r/w --- 11111 b 0420 h to 042e h icr32 to icr46 interrupt control register 32 to 46 r/w --- 11111 b 042f h icr47 interrupt control register 47 r/w --- 11111 b 0430 h dicr delayed interrupt control register r/w ------- 0 b 0431 h hrcl hold request cancel request level setting register r/w --- 11111 b 0432 h to 047f h (vacancy) 0480 h rsrr/wtcr reset cause register/ watchdog peripheral control register r/w 1xxxx - 00 b 0481 h stcr standby control register r/w 000111 -- b 0482 h pdrr dma controller request squelch register r/w ---- 0000 b (continued) address register name (abbreviated) register name read/write initial value
MB91121 29 0483 h ctbr timebase timer clear register w xxx xxxxx b 0484 h gcr gear control register r/w 110011 - 1 b 0485 h wpr watchdog reset occurrence postpone register w xxx xxxxx b 0486 h (vacancy) 0487 h 0488 h pctr pll control register r/w 0 0 -- 0 --- b 0489 h to 0600 h (vacancy) 0601 h ddr2 port 2 data direction register w 00000000 b 0602 h to 0604 h (vacancy) 0605 h ddr6 port 6 data direction register w 00000000 b 0606 h (vacancy) 0607 h 0608 h ddrb port b data direction register w 00000000 b 0609 h ddra port a data direction register w - 000000 - b 060a h (vacancy) 060b h ddr8 port 8 data direction register w -- 0 -- 000 b 060c h asr1 area select register 1 w 00000000 b 060d h 00000001 b 060e h amr1 area mask register 1 w 00000000 b 060f h 00000000 b 0610 h asr2 area select register 2 w 00000000 b 0611 h 00000010 b 0612 h amr2 area mask register 2 w 00000000 b 0613 h 00000000 b 0614 h asr3 area select register 3 w 00000000 b 0615 h 00000011 b 0616 h amr3 area mask register 3 w 00000000 b 0617 h 00000000 b 0618 h asr4 area select register 4 w 00000000 b 0619 h 00000100 b 061a h amr4 area mask register 4 w 00000000 b 061b h 00000000 b (continued) address register name (abbreviated) register name read/write initial value
MB91121 30 (continued) address register name (abbreviated) register name read/write initial value 061c h asr5 area select register 5 w 00000000 b 061d h 00000101 b 061e h amr5 area mask register 5 w 00000000 b 061f h 00000000 b 0620 h amd0 area mode register 0 r/w --- 00111 b 0621 h amd1 area mode register 1 r/w 0 -- 00000 b 0622 h amd32 area mode register 32 r/w 00000000 b 0623 h amd4 area mode register 4 r/w 0 -- 00000 b 0624 h amd5 area mode register 5 r/w 0 -- 00000 b 0625 h dscr dram signal control register w 00000000 b 0626 h rfcr refresh control register r/w -- xxxxxx b 0627 h 00 --- 000 b 0628 h epcr0 external pin control register 0 w ---- 1100 b 0629 h - 1111111 b 062a h (vacancy) 062b h epcr1 external pin control register 1 w 11111111 b 062c h dmcr4 dram control register 4 r/w 00000000 b 062d h 0000000 - b 062e h dmcr5 dram control register 5 r/w 00000000 b 062f h 0000000 - b 0630 h to 07fd h (vacancy) 07fe h ler little endian register w ----- 000 b 07ff h modr mode register w xxxxxxxx b 002000 h to 002fff h y-ram (variable ram) 4096 byte (max.) dsp macro ram 00f000 h to 00f07f h x-ram (coefficient ram) 128 byte 00f100 h to 00f2ff h i-ram (instruction ram) 512 byte note : do not use (vacancy) .
MB91121 31 n interrupt causes, interrupt vectors and interrupt control register allocations interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset reset 0 00 ? 3f4 h 000ffffc h reserved for system 1 01 ? 3f8 h 000ffff8 h reserved for system 2 02 ? 3f4 h 000ffff4 h reserved for system 3 03 ? 3f0 h 000ffff0 h reserved for system 4 04 ? 3ec h 000fffec h reserved for system 5 05 ? 3e8 h 000fffe8 h reserved for system 6 06 ? 3e4 h 000fffe4 h reserved for system 7 07 ? 3e0 h 000fffe0 h reserved for system 8 08 ? 3dc h 000fffdc h reserved for system 9 09 ? 3d8 h 000fffd8 h reserved for system 10 0a ? 3d4 h 000fffd4 h reserved for system 11 0b ? 3d0 h 000fffd0 h reserved for system 12 0c ? 3cc h 000fffcc h reserved for system 13 0d ? 3c8 h 000fffc8 h exception for undefined instruction 14 0e ? 3c4 h 000fffc4 h nmi request 15 0f f h fixed 3c0 h 000fffc0 h external interrupt 0 16 10 icr00 3bc h 000fffbc h external interrupt 1 17 11 icr01 3b8 h 000fffb8 h external interrupt 2 18 12 icr02 3b4 h 000fffb4 h external interrupt 3 19 13 icr03 3b0 h 000fffb0 h uart0 receive complete 20 14 icr04 3ac h 000fffac h uart1 receive complete 21 15 icr05 3a8 h 000fffa8 h uart2 receive complete 22 16 icr06 3a4 h 000fffa4 h uart0 transmit complete 23 17 icr07 3a0 h 000fffa0 h uart1 transmit complete 24 18 icr08 39c h 000fff9c h uart2 transmit complete 25 19 icr09 398 h 000fff98 h dmac0 (complete, error) 26 1a icr10 394 h 000fff94 h dmac1 (complete, error) 27 1b icr11 390 h 000fff90 h dmac2 (complete, error) 28 1c icr12 38c h 000fff8c h dmac3 (complete, error) 29 1d icr13 388 h 000fff88 h dmac4 (complete, error) 30 1e icr14 384 h 000fff84 h dmac5 (complete, error) 31 1f icr15 380 h 000fff80 h dmac6 (complete, error) 32 20 icr16 37c h 000fff7c h (continued)
MB91121 32 dmac7 (complete, error) 33 21 icr17 378 h 000fff78 h a/d converter (successive approxima- tion conversion type) 34 22 icr18 374 h 000fff74 h 16-bit reload timer 0 35 23 icr19 370 h 000fff70 h 16-bit reload timer 1 36 24 icr20 36c h 000fff6c h 16-bit reload timer 2 37 25 icr21 368 h 000fff68 h pwm 0 38 26 icr22 364 h 000fff64 h pwm 1 39 27 icr23 360 h 000fff60 h pwm 2 40 28 icr24 35c h 000fff5c h pwm 3 41 29 icr25 358 h 000fff58 h u-timer 0 42 2a icr26 354 h 000fff54 h u-timer 1 43 2b icr27 350 h 000fff50 h u-timer 2 44 2c icr28 34c h 000fff4c h external interrupt 4 45 2d icr29 348 h 000fff48 h external interrupt 5 46 2e icr30 344 h 000fff44 h external interrupt 6 47 2f icr31 340 h 000fff40 h external interrupt 7 48 30 icr32 33c h 000fff3c h dsp macros soft interrupt 49 31 icr33 338 h 000fff38 h dsp macros offset interrupt 50 32 icr34 334 h 000fff34 h reserved for system 51 33 icr35 330 h 000fff30 h reserved for system 52 34 icr36 32c h 000fff2c h reserved for system 53 35 icr37 328 h 000fff28 h reserved for system 54 36 icr38 324 h 000fff24 h reserved for system 55 37 icr39 320 h 000fff20 h reserved for system 56 38 icr40 31c h 000fff1c h reserved for system 57 39 icr41 318 h 000fff18 h reserved for system 58 3a icr42 314 h 000fff14 h reserved for system 59 3b icr43 310 h 000fff10 h reserved for system 60 3c icr44 30c h 000fff0c h reserved for system 61 3d icr45 308 h 000fff08 h reserved for system 62 3e icr46 304 h 000fff04 h delayed interrupt cause bit 63 3f icr47 300 h 000fff00 h reserved for system (used in realos*) 64 40 ? 2fc h 000ffefc h reserved for system (used in realos*) 65 41 ? 2f8 h 000ffef8 h (continued) interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset
MB91121 33 used in int instructions 66 to 255 42 to ff ? 2f4 h to 000 h 000ffef4 h to 000ffc00 h * : when using in realos/fr, interrupt 0x40, 0x41 for system code. interrupt causes interrupt number interrupt level tbr default address decimal hexadecimal register offset (continued)
MB91121 34 n peripheral resources 1. i/o ports there are 2 types of i/o port register structure; port data register (pdr2, 6, 8, a, b, e to i) and data direction register (ddr2, 6, 8, a, b, e to i) , where bits pdr2, 6, 8, a, b, e to i and bits ddr2, 6, 8, a, b, e to i corresponds respectively. each bit on the register corresponds to an external pin. in port registers input/output register of the port configures input/output function of the port, while corresponding bit (pin) configures input/output function in data direction registers. bit 0 specifies input and 1 specifies output. ? for input (ddr = 0) setting; pdr reading operation : reads level of corresponding external pin. pdr writing operation : writes set value to pdr. ? for output (ddr = 1) setting; pdr reading operation : reads pdr value. pdr writing operation : outputs pdr value to corresponding external pin. ? block diagram pdr ddr 1 0 1 0 (port data register) (data direction register) resource output enable resource output pdr read resource input pin data bus
MB91121 35 ? register explanation ? port data register (pdr) 76543210 p27 p26 p25 p24 p23 p22 p21 p20 76543210 p67 p66 p65 p64 p63 p62 p61 p60 76543210 ?? p85 ?? p82 p81 p80 76543210 ? pa6 pa5 pa4 pa3 pa2 pa1 ? 76543210 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 76543210 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 76543210 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 76543210 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 76543210 ph7 ph6 ph5 ph4 ???? 76543210 ?????? pi1 pi0 pdr2 address : 000001 h pdr6 address : 000005 h pdr8 address : 00000b h pdra address : 000009 h pdrb address : 000008 h pdre address : 000012 h pdrf address : 000013 h pdrg address : 000014 h pdrh address : 000015 h pdri address : 000016 h initial value access xxxxxxxx b r/w initial value access xxxxxxxx b r/w initial value access -- x -- xxx b r/w initial value access - xxxxxx - b r/w initial value access xxxxxxxx b r/w initial value access xxxxxxxx b r/w initial value access xxxxxxxx b r/w initial value access xxxxxxxx b r/w initial value access xxxx ---- b r/w initial value access ------ xx b r/w pdr2 to pdri is the i/o port input/output data register. the associated register, ddr2 to ddri, controls the input/output.
MB91121 36 ? data direction register (ddr) 76543210 p27 p26 p25 p24 p23 p22 p21 p20 76543210 p67 p66 p65 p64 p63 p62 p61 p60 76543210 ?? p85 ?? p82 p81 p80 76543210 ? pa6 pa5 pa4 pa3 pa2 pa1 ? 76543210 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 76543210 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 76543210 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 76543210 pg7 pg6 pg5 pg4 pg3 pg2 pg1 pg0 76543210 ph7 ph6 ph5 ph4 ???? 76543210 ?????? pi1 pi0 ddr2 address : 000601 h ddr6 address : 000605 h ddr8 address : 00060b h ddra address : 000609 h ddrb address : 000608 h ddre address : 0000d2 h ddrf address : 0000d3 h ddrg address : 0000d4 h ddrh address : 0000d5 h ddri address : 0000d6 h initial value access 00000000 b w initial value access 00000000 b w initial value access -- 0 -- 000 b w initial value access - 000000 - b w initial value access 00000000 b w initial value access 00000000 b w initial value access 00000000 b w initial value access 00000000 b w initial value access 0000 ---- b w initial value access ------ 00 b w ddr2 to ddri controls the i/o port input/output direction bit by bit. 0 : input 1 : output
MB91121 37 2. dma controller (dmac) the dma controller is a module embedded in fr family devices, and performs dma (direct memory access) transfer. dma transfer performed by the dma controller transfers data without intervention of cpu, contributing to enhanced performance of the system. ? 8 channels ? mode : single/block transfer, burst transfer and continuous transfer : 3 kinds of transfer ? transfer all through the area ? max. 65536 of transfer cycles ? interrupt function right after the transfer ? selectable for address transfer increase/decrease by the software ? external transfer request input pin, external transfer request accept output pin, external transfer complete output pin three pins for each ? block diagram dreq0 to dreq2 dack0 to dack2 eop0 to eop2 interrupt request dpdp dacsr datcr blk dec inc / dec blk dmact sadr dadr 3 3 3 3 8 5 sequencer edge/level detection circuit inner resource transfer request data buffer switcher data bus mode
MB91121 38 address initial value bit 31 bit 16 bit 0 00000200 h xxxxxxxx b 00000201 h dpdp xxxxxxxx b (r/w) 00000202 h xxxxxxxx b 00000203 h x0000000 b 00000204 h 00000000 b 00000205 h dacsr 00000000 b (r/w) 00000206 h 00000000 b 00000207 h 00000000 b 00000208 h xxxxxxxx b 00000209 h datcr xxxx0 0 0 0 b (r/w) 0000020a h xxxx0 0 0 0 b 0000020b h xxxx0 0 0 0 b ? registers (dmac internal registers) ( ) : access r/w : readable and writable x : indeterminate ? registers (dma descriptor) address bit 31 bit 0 dpdp + 0 h dma ch.0 descriptor dpdp + 0c h dma ch.1 descriptor dpdp + 54 h dma ch.7 descriptor
MB91121 39 3. uart the uart is a serial i/o port for supporting asynchronous (start-stop system) communication or clk synchronous communication, and it has the following features. the MB91121 consists of 3 channels of uart. ? full double double buffer ? both a synchronous (start-stop system) communication and clk synchronous communication are available. ? supporting multi-processor mode ? perfect programmable baud rate any baud rate can be set by internal timer (refer to section 4. u-timer) . ? any baud rate can be set by external clock. ? error checking function (parity, framing and overrun) ? transfer signal : nrz code ? enable dma transfer start by interrupt.
MB91121 40 ? block diagram sidr sodr md1 md0 cs0 scke soe pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie control signals from external clock si (receive data) clock select circuit receive interrupt (to cpu) transmit interrupt (to cpu) receive control circuit start bit detect circuit receive bit counter receive parity counter transmit control circuit transmit start circuit transmit bit counter transmit parity counter transmit clock receive clock sc (clock) from u-timer sc receive status judge circuit receive shifter receive complete transmit shifter transmit start receive error generate signal for dma (to dmac) r-bus smr register scr register ssr register control signals so (transmit data)
MB91121 41 ? register configuration address initial value bit 15 bit 8 bit 0 0000001e h scr0 00000100 b (r/w) 00000022 h scr1 00000100 b (r/w) 00000026 h scr2 00000100 b (r/w) 0000001f h smr0 0 0 -- 0 - 00 b (r/w) 00000023 h smr1 0 0 -- 0 - 00 b (r/w) 00000027 h smr2 0 0 -- 0 - 00 b (r/w) 0000001c h ssr0 00001 - 00 b (r/w) 00000020 h ssr1 00001 - 00 b (r/w) 00000024 h ssr2 00001 - 00 b (r/w) 0000001d h sidr0/sodr0 xxxxxxxx b (r/w) 00000021 h sidr1/sidr1 xxxxxxxx b (r/w) 00000002 h sidr2/sidr2 xxxxxxxx b (r/w) ( ) : access r/w : readable and writable ? : unused x : indeterminate
MB91121 42 4. u-timer (16-bit timer for uart baud rate generation) the u-timer is a 16-bit timer for generating uart baud rate. combination of chip operating frequency and reload value of u-timer allows flexible setting of baud rate. the u-timer operates as an interval timer by using interrupt issued on counter underflow. the MB91121 has 3 channel u-timer embedded on the chip. an interval of up to 2 16 f can be counted. ? block diagram ? register configuration bit 15 bit 0 bit 15 bit 0 f f.f. utimr (reload register) utim ( u-timer register) clock underflow to uart (peripheral clock) control load address initial value bit 15 bit 0 00000078 h utim0/utimr0 00000000 b (r/w) 00000079 h 00000000 b 0000007c h utim1/utimr1 00000000 b (r/w) 0000007d h 00000000 b 00000080 h utim2/utimr2 00000000 b (r/w) 00000081 h 00000000 b 0000007b h utimc0 0 -- 00001 b (r/w) 0000007f h utimc1 0 -- 00001 b (r/w) 00000083 h utimc2 0 -- 00001 b (r/w) ( ) : access r/w : readable and writable ? : unused
MB91121 43 5. pwm timer the pwm timer can output high accurate pwm waves efficiently. MB91121 has inner 4-channel pwm timers, and has the following features. ? each channel consists of a 16-bit down counter, a 16-bit data resister with a buffer for cycle setting, a 16-bit compare resister with a buffer for duty setting, and a pin controller. ? the count clock of a 16-bit down counter can be selected from the following four inner clocks. inner clock f , f /4, f /16, f /64 ? the counter value can be initialized ffff h by the resetting or the counter borrow. ? pwm output (each channel) ? resister description ? block diagram (general construction) 4 4 pwm0 pwm1 pwm2 pwm3 16-bit reload timer ch.0 16-bit reload timer ch.1 general control register 2 trg input pwm timer ch.0 trg input pwm timer ch.1 trg input pwm timer ch.2 trg input pwm timer ch.3 general control register 1 (cause selection) external trg0 to trg3
MB91121 44 ? block diagram (for one channel) 1 / 1 1 / 4 1 / 16 1 / 64 ck pcsr pdut cmp s r q irq peripheral clock prescaler start borrow load 16-bit down counter ppg mask reverse bit interrupt selection enable soft trigger edge detect trg input pwm output
MB91121 45 ? register configuration address initial value bit 15 bit 8 bit 0 000000dc h gcn1 00110010 b (r/w) 000000dd h 00010010 b 000000df h gcn2 00000000 b (r/w) 000000e0 h ptmr0 11111111 b (r) 000000e1 h 11111111 b 000000e2 h pcsr0 xxxxxxxx b (w) 000000e3 h xxxxxxxx b 000000e4 h pdut0 xxxxxxxx b (w) 000000e5 h xxxxxxxx b 000000e6 h pcnh0 0000000 - b (r/w) 000000e7 h pcnl0 00000000 b (r/w) 000000e8 h ptmr1 11111111 b (r) 000000e9 h 11111111 b 000000ea h pcsr1 xxxxxxxx b (w) 000000eb h xxxxxxxx b 000000ec h pdut1 xxxxxxxx b (w) 000000ed h xxxxxxxx b 000000ee h pcnh1 0000000 - b (r/w) 000000ef h pcnl1 00000000 b (r/w) 000000f0 h ptmr2 11111111 b (r) 000000f1 h 11111111 b 000000f2 h pcsr2 xxxxxxxx b (w) 000000f3 h xxxxxxxx b 000000f4 h pdut2 xxxxxxxx b (w) 000000f5 h xxxxxxxx b 000000f6 h pcnh2 0000000 - b (r/w) 000000f7 h pcnl2 00000000 b (r/w) 000000f8 h ptmr3 11111111 b (r) 000000f9 h 11111111 b 000000fa h pcsr3 xxxxxxxx b (w) 000000fb h xxxxxxxx b 000000fc h pdut3 xxxxxxxx b (w) 000000fd h xxxxxxxx b 000000fe h pcnh3 0000000 - b (r/w) 000000ff h pcnl3 00000000 b (r/w) ( ) : access r/w : readable and writable r : read only w : write only ? : unused x : indeterminate
MB91121 46 6. 16-bit reload timer the 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload timer, a prescaler for generating internal count clock and control registers. internal clock can be selected from 3 types of internal clocks (divided by 2/8/32 of machine clock) . the dma transfer can be started by the interruption. the MB91121 consists of 3 channels of the 16-bit reload timer. ? block diagram reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl. fff 222 135 3 exck gate 2 irq pwm (ch0, ch1) a/d (ch2) 16-bit reload register 16-bit down counter uf clock selector reload internal clock prescaler clear retrigger r-bus
MB91121 47 ? register configuration address initial value bit 15 bit 0 0000002e h tmcsr0 ---- 0000 b (r/w) 0000002f h 00000000 b 00000036 h tmcsr1 ---- 0000 b (r/w) 00000037 h 00000000 b 00000042 h tmcsr2 ---- 0000 b (r/w) 00000043 h 00000000 b 0000002a h tmr0 xxxxxxxx b (r) 0000002b h xxxxxxxx b 00000032 h tmr1 xxxxxxxx b (r) 00000033 h xxxxxxxx b 0000003e h tmr2 xxxxxxxx b (r) 0000003f h xxxxxxxx b 00000028 h tmrlr0 xxxxxxxx b (w) 00000029 h xxxxxxxx b 00000030 h tmrlr1 xxxxxxxx b (w) 00000031 h xxxxxxxx b 0000003c h tmrlr2 xxxxxxxx b (w) 0000003d h xxxxxxxx b ( ) : access r/w : readable and writable r : read only w : write only ? : unused x : indeterminate
MB91121 48 7. bit search module the bit search module detects transitions of data (0 to 1/1 to 0) on the data written on the input registers and returns locations of the transitions. ? block diagram ? register configuration input latch single-detection data recovery bit search circuit search result address decoder detection mode d-bus address initial value bit 31 bit 16 bit 0 000003f0 h xxxxxxxx b 000003f1 h bsd0 xxxxxxxx b (w) 000003f2 h xxxxxxxx b 000003f3 h xxxxxxxx b 000003f4 h xxxxxxxx b 000003f5 h bsd1 xxxxxxxx b (w) 000003f6 h xxxxxxxx b 000003f7 h xxxxxxxx b 000003f8 h xxxxxxxx b 000003f9 h bsdc xxxxxxxx b (w) 000003fa h xxxxxxxx b 000003fb h xxxxxxxx b 000003fc h xxxxxxxx b 000003fe h bsrr xxxxxxxx b (w) 000003fd h xxxxxxxx b 000003ff h xxxxxxxx b ( ) : access r/w : readable and writable r : read only w : write only x : indeterminate
MB91121 49 8. 10-bit a/d converter (successive approximation conversion type) the a/d converter is the module which converts an analog input voltage to a digital value, and it has following features. ? minimum converting time : 5.6 m s/ch. (system clock : 25 mhz) ? inner sample and hold circuit ? resolution : 10 bits ? analog input can be selected from 4 channels by program. single convert mode : 1 channel is selected and converted. scan convert mode : converting continuous channels. maximum 4 channels are programmable. continuous convert mode : converting the specified channel repeatedly. stop convert mode : after converting one channel then stop and wait till next activation synchronising at the beginning of conversion can be peformed. ? dma transfer operation is available by interruption. ? operating factor can be selected from the software, the external trigger (falling edge) , and 16-bit reroad timer (rising edge) .
MB91121 50 ? block diagram ? register configuration av cc avr av ss mpx an0 an1 an2 an3 atg f successive approximation register internal voltage generator comparator sample & hold circuit data register (adcr) a/d control register (adcs) prescaler operating clock trigger start tim0 (internal connection) (16-bit reload timer ch.2) timer start (peripheral clock) r-bus input circuit decoder address initial value bit 15 bit 0 0000003a h adcs 00000000 b (r/w) 0000003b h 00000000 b 00000038 h adcr ------ xx b (r) 00000039 h xxxxxxxx b ( ) : access r/w : readable and writable r : read only ? : unused x : indeterminate
MB91121 51 9. interrupt controller the interrupt controller processes interrupt acknowledgments and arbitration between interrupts. ? block diagram level0 4 im int0 2 or nmi ri00 ri47 (dlyirq) dlyi 1 icr00 icr47 4 5 5 6 6 level4 to hldcan 3 vct0 5 vct5 to r-bus priority judgment nmi processing level judgment vector judgment level vector generation hldreq cancel request *1 : dlyi stands for delayed interrupt module (delayed interrupt generation block) (refer to the section 11. delayed interrupt module for detail) . *2 : int0 is a wake-up signal to clock control block in the sleep or stop status. *3 : hldcan is a bus release request signal for bus masters other than cpu. *4 : level5 to level0 are interrupt level outputs. *5 : vct5 to vct0 are interrupt vector outputs.
MB91121 52 ? register configuration address initial value address initial value bit 7 bit 0 bit 7 bit 0 00000400 h icr00 --- 11111 b (r/w) 00000411 h icr17 --- 11111 b (r/w) 00000401 h icr01 --- 11111 b (r/w) 00000412 h icr18 --- 11111 b (r/w) 00000402 h icr02 --- 11111 b (r/w) 00000413 h icr19 --- 11111 b (r/w) 00000403 h icr03 --- 11111 b (r/w) 00000414 h icr20 --- 11111 b (r/w) 00000404 h icr04 --- 11111 b (r/w) 00000415 h icr21 --- 11111 b (r/w) 00000405 h icr05 --- 11111 b (r/w) 00000416 h icr22 --- 11111 b (r/w) 00000406 h icr06 --- 11111 b (r/w) 00000417 h icr23 --- 11111 b (r/w) 00000407 h icr07 --- 11111 b (r/w) 00000418 h icr24 --- 11111 b (r/w) 00000408 h icr08 --- 11111 b (r/w) 00000419 h icr25 --- 11111 b (r/w) 00000409 h icr09 --- 11111 b (r/w) 0000041a h icr26 --- 11111 b (r/w) 0000040a h icr10 --- 11111 b (r/w) 0000041b h icr27 --- 11111 b (r/w) 0000040b h icr11 --- 11111 b (r/w) 0000041c h icr28 --- 11111 b (r/w) 0000040c h icr12 --- 11111 b (r/w) 0000041d h icr29 --- 11111 b (r/w) 0000040d h icr13 --- 11111 b (r/w) 0000041e h icr30 --- 11111 b (r/w) 0000040e h icr14 --- 11111 b (r/w) 0000041f h icr31 --- 11111 b (r/w) 0000040f h icr15 --- 11111 b (r/w) 0000042f h icr47 --- 11111 b (r/w) 00000410 h icr16 --- 11111 b (r/w) 00000431 h hrcl --- 11111 b (r/w) 00000430 h dicr ------- 0 b (r/w) ( ) : access r/w : readable and writable ? : unused
MB91121 53 10. external interrupt/nmi control block the external interrupt/nmi control block controls external interrupt request signals input to nmi pin and int0 to int3 pins. detecting levels can be selected from h, l, rising edge and falling edge (not for nmi pin) . ? block diagram ? register configuration 8 8 8 9 5 int0 to int7 nmi interrupt enable register interrupt cause register request level setting register gate cause f/f edge detection circuit interrupt request r-bus address initial value bit 15 bit 8 bit 0 00000095 h enir 00000000 b (r/w) 00000094 h eirr 00000000 b (r/w) 00000099 h elvr 00000000 b (r/w) ( ) : access r/w : readable and writable
MB91121 54 11. delayed interrupt module delayed interrupt module is a module which generates a interrupt for changing a task. by using this delayed interrupt module, an interrupt request to cpu can be generated/cancelled by the software. refer to the section 9. interrupt controller for delayed interrupt module block diagram. ? register configuration address initial value bit 7 bit 0 00000430 h dicr ------- 0 b (r/w) ( ) : access r/w : readable and writable ? : unused
MB91121 55 12. clock generation (low-power consumption mechanism) the clock control block is a module which undertakes the following functions. ? cpu clock generation (including gear function) ? peripheral clock generation (including gear function) ? reset generation and cause hold ? standby function (including hardware standby) ? dma request prohibit ? pll (multiplier circuit) embedded
MB91121 56 ? block diagram x0 x1 pll 1 / 2 gear control register (gcr) [gear control block] pctr register cpu gear peripheral gear oscillator circuit internal clock generation circuit cpu clock internal bus clock external bus clock peripheral dma clock internal peripheral clock [stop/sleep control block] internal interrupt request internal reset standby control register (stcr) stop state sleep state cpu hold request internal reset reset generation f/f cpu hold enable hst pin r-bus selection circuit status transition control circuit dma request power on sel rst pin dma request prohibit register (pdrr) [dma prohibit circuit] reset cause register (rsrr) timebase timer count clock watchdog reset postpone register [watchdog control block] timebase timer clear register (ctbr) watchdog reset generation postpone register (wpr) [reset cause circuit] dsp macros clock
MB91121 57 ? register configuration address initial value bit 15 bit 8 bit 0 00000480 h rsrr/wtcr 1 x x x x - 00 b (r/w) 00000481 h stcr 000111 -- b (r/w) 00000482 h pdrr ---- 0000 b (r/w) 00000483 h cdbr xxxxxxxx b (w) 00000484 h gcr 110011 - 1 b (r/w) 00000485 h wpr xxxxxxxx b (w) ( ) : access r/w : readable and writable r : read only ? : unused x : indeterminate
MB91121 58 13. external bus interface the external bus interface controls the interface between the device and the external memory and also the external i/o, and has the following features. ? 25-bit (32 mbytes) address output ? 6 independent banks owing to the chip select function. can be set to anywhere on the logical address space for minimum unit 64 kbytes. total 32 mbytes 6 area setting is available by the address pin and the chip select pin. ? 8/16-bit bus width setting are available for every chip select area. ? programmable automatic memory wait (max. for 7 cycles) can be inserted. ? dram interface support three kinds of dram interface : double cas dram (normally dram i/f) single cas dram hyper dram 2 banks independent control (ras, cas, etc. control signals) dram select is available from 2cas/1we and 1cas/2we. hi-speed page mode supported cbr/self refresh supported programmable wave form ? unused address/data pin can be used for i/o port. ? little endian mode supported ? clock doublure : internal bus 50 mhz, external bus 25 mhz
MB91121 59 ? block diagram a-out write buffer read buffer switch mux switch + 1 or + 2 inpage dmcr dram control refresh counter asr amr data block address block address buffer shifter comparator cs0 to cs5 ras0, ras1 cs0l, cs1l cs0h, cs1h dw0, dw1 underflow registers & control rd wr0, wr1 brq bgrnt clk rdy 32 6 8 3 4 32 address bus data bus external data bus external address bus to tbt external pin control block all blocks control
MB91121 60 ? register configuration address initial value bit 31 bit 16 bit 0 0000060c h asr1 00000000 b (w) 0000060d h 00000001 b 0000060e h amr1 00000000 b (w) 0000060f h 00000000 b 00000610 h asr2 00000000 b (w) 00000611 h 00000010 b 00000612 h amr2 00000000 b (w) 00000613 h 00000000 b 00000614 h asr3 00000000 b (w) 00000615 h 00000011 b 00000616 h amr3 00000000 b (w) 00000617 h 00000000 b 00000618 h asr4 00000000 b (w) 00000619 h 00000100 b 0000061a h amr4 00000000 b (w) 0000061b h 00000000 b 0000061c h asr5 00000000 b (w) 0000061d h 00000101 b 0000061e h amr5 00000000 b (w) 0000061f h 00000000 b 00000620 h amd0 --- 00111 b (r/w) 00000621 h amd1 0 -- 00000 b (r/w) 00000622 h amd32 00000000 b (r/w) 00000623 h amd4 0 -- 00000 b (r/w) 00000624 h amd5 0 -- 00000 b (r/w) 00000625 h dscr 00000000 b (w) 00000626 h rfcr -- xxxxxx b (r/w) 00000627 h 00 --- 000 b 00000628 h epcr0 --- 11000 b (w) 00000629 h - 1111111 b 0000062b h epcr1 11111111 b (w) 0000062c h dmcr4 00000000 b (r/w) 0000062d h 0000000 - b 0000062e h dmcr5 00000000 b (r/w) 0000062f h 0000000 - b 000007fe h ler ----- 000 b (w) 000007ff h modr xxxxxxxx b (w) ( ) : access r/w : readable and writable w : write only ? : unused x : indeterminate
MB91121 61 n electrical characteristics 1. absolute maximum ratings *1 : make sure that the voltage does not exceed v cc 5 + 0.3 v, such as when turning on the device. *2 : maximum output current is a peak current value measured at a corresponding pin. *3 : average output current is an average current for a 100 ms period at a corresponding pin. *4 : average total output current is an average current for a 100 ms period for all corresponding pins. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. (v ss = av ss = 0.0 v) parameter symbol value unit remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 3.6 v analog supply voltage av cc v ss - 0.3 v ss + 3.6 v *1 analog reference voltage avrh v ss - 0.3 v ss + 3.6 v *1 input voltage v i v ss - 0.3 v cc + 0.3 v analog pin input voltage v ia v ss - 0.3 av cc + 0.3 v output voltage v o v ss - 0.3 v cc + 0.3 v l level maximum output current i ol ? 10 ma *2 l level average output current i olav ? 4ma*3 l level maximum total output current s i ol ? 100 ma l level average total output current s i olav ? 50 ma *4 h level maximum output current i oh ?- 10 ma *2 h level average output current i ohav ?- 4ma*3 h level maximum total output current s i oh ?- 50 ma h level average total output current s i ohav ?- 20 ma *4 power consumption p d ? 600 mw operating temperature t a 0 + 70 c storage temperature tstg - 55 + 150 c
MB91121 62 2. recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. (v ss = av ss = 0.0 v) parameter symbol value unit remarks min. max. power supply voltage v cc 3.0 3.6 v analog supply voltage av cc v ss + 0.3 v ss + 3.6 v analog reference voltage avrh av ss av cc v operating temperature t a 0 + 70 c
MB91121 63 3. dc characteristics *1 : hysteresis input pin : nmi , rst , p60 to p67, pa1 to pa6, pb0 to pb7, pe0 to pe7, pf0 to pf7, pg0 to pg7, pi0, pi1 *2 : v cc 3 = 3.3 0.2 v (internal regulator output voltage) when using 5 v power supply, v cc 3 = power supply voltage when using 3v power supply (internal regulator unused) (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih input pin except for hysteresis input ? 0.65 v cc ? v cc + 0.3 v *2 v ihs *1 ? 0.8 v cc ? v cc + 0.3 v hysteresis input*2 l level input voltage v il input pin except for hysteresis input ? v ss - 0.3 ? 0.25 v cc v*2 v ils *1 ? v ss - 0.3 ? 0.2 v cc v hysteresis input*2 h level output voltage v oh d16 to d31 a00 to a24 p6 to pf v cc = 3.0 v i oh = - 4.0 ma v cc - 0.5 ?? v l level output voltage v ol d16 to d31 a00 to a24 p6 to pf v cc = 3.0 v i ol = 4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li d00 to d31 a00 to a23 p8 to pf v cc = 3.6 v 0.45 v< v i < v cc - 5 ?+ 5 m a pull-up resistance r pull rst v cc = 3.6 v v i = 0.45 v 25 50 100 k w power supply current i cc v cc f c = 12.5 mhz v cc = 3.3 v ? 130 180 ma (4 multipli- cation) operation at 50 mhz i ccs f c = 12.5 mhz v cc = 3.3 v ? 85 120 ma sleep mode i cch t a = + 25 c v cc = 3.3 v ? 15 150 m a stop mode input capacitance c in except for v cc , av cc , av ss , v ss ?? 10 ? pf
MB91121 64 4. ac characteristics (1) measurement conditions the following conditions apply to ac characteristics unless otherwise specified. v cc 0 v h ih v il v oh v ol input output output pin c = 50 pf (v cc : 3.0 v to 3.6 v) ? measurement conditions for ac standards v cc : 3.0 v to 3.6 v (the input rise/fall time is 10 ns or less.) v ih 1/2 * v cc v oh 1/2 * v cc v il 1/2 * v cc v ol 1/2 * v cc ? load condition
MB91121 65 (2) clock timing rating *1 : frequency shift ratio stands for deviation ratio of the operating clock from the center frequency in the clock multiplication system. *2 : these values are for a minimum clock of 10 mhz input to x0, a divide-by-2 system of the source oscillation and a 1/8 gear. *3 : values when using the doublure and cpu operation at 50 mhz. (v cc = 3.0 v to 3.6 v, v ss = av ss = 0 .0v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. clock frequency (1) f c x0, x1 ? 10 12.5 mhz when using pll clock cycle time t c x0, x1 80 100 ns frequency shift ratio* 1 (when locked) d f ? 5% clock frequency (2) f c x0, x1 ? 10 25 mhz self-oscillation (divide-by-2 input) clock frequency (3) f c x0, x1 10 25 mhz external clock (divide-by-2 input) clock cycle time t c x0, x1 40 100 ns input clock pulse width p wh , p wl x0, x1 25 ? ns input to x0 only 10 ? ns input to x0, x1 input clock rising/falling time t cr , t cf x0, x1 ? 8ns (t cr + t cf ) internal operating clock frequency f cp ? 0.625* 2 50 mhz cpu system f cpb 0.625* 2 25* 3 mhz bus system f cpp 0.625* 2 25 mhz peripheral system internal operating clock cycle time t cp 20 1600* 2 ns cpu system t cpb 40* 3 1600* 2 ns bus system t cpp 40 1600* 2 ns peripheral system d f = 100 (%) | a | f 0 f 0 +a -a + - center frequency
MB91121 66 ? clock timing rating measurement conditions ? guaranteed operating range ? external/internal clock setting range 0.8 v cc 0.2 v cc t cf t cr t c p wh p wl 3.3 v 0.3 v guaranteed operating range (t a = 0 c to + 70 c) f cpp falls within the shaded range. internal clock power supply v cc (v) 3.6 3.0 0 0.625 25 50 f cp / f cpp [mhz] cpu external clock internal oscillation oscillation input clock pll system (4 multiplication) divide-by-2 system peripheral internal clock setting upper limit f cp f cpp 50 40 25 20 12.5 5 0 0 10 12.5 25 50 f c [mhz] note1 : if the pll is used, the external clock input should be 10.0 mhz to 12.5 mhz. note2 : the pll oscillation settling time must be longer than 300 m s. note3 : the internal clock gear setting must fall within the above range.
MB91121 67 (3) clock output timing *1 : t cyc is a frequency for 1 clock cycle including a gear cycle. use the doublure when cpu frequency is above 25 mhz. *2 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. min. : (1 - n / 2) t cyc - 10 max. : (1 - n / 2) t cyc + 10 select a gear cycle of 1 when using the doublure. *3 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equations with 1/2, 1/4, 1/8, respectively. min. : n / 2 t cyc - 10 max. : n / 2 t cyc + 10 select a gear cycle of 1 when using the doublure. (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. cycle time t cyc clk ? t cp ns *1 t cpb using the doublure clk - ? clk t chcl clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *2 clk ? clk - t clch clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *3 clk v oh v ol v oh t cyc t clch t chcl
MB91121 68 the relation between source oscillation input and clk pin for configured by chc/cck1/cck0 settings of gcr (gear control register) is as follows: however, in this chart source oscillation input means x0 input clock. t cyc t cyc t cyc t cyc t cyc t cyc cck1/0: ?0 source oscillation input (when using the doublure) source oscillation input (1) pll system (chc bit of gcr set to ?? (2) 2 dividing system (chc bit of gcr set to ?? (a) gear 1 clk pin cck1/0: ?0 (b) gear 1/2 clk pin cck1/0: ?1 (c) gear 1/4 clk pin cck1/0: ?0 (d) gear 1/8 clk pin cck1/0: ?1 (a) gear 1 clk pin
MB91121 69 ? ceramc oscillator applications ? discrete type *1 : feedback resistor rf is built in the lsi. *2 : no dumping resistor is required. ( ) : c 1 and c 2 integrated oscillation frequency [mhz] model name circuit constants pin type c1[pf] c1[pf] rf[ w ]* 1 rd[ w ]* 2 10.00 to 13.00 csa mtz 30 30 ? 0two-pin cst mtw (30) (30) ? 0three-pin 13.01 to 15.99 csa mxz040 15 15 ? 0two-pin cst mxw0c3 (15) (15) ? 0three-pin 16.00 to 19.99 csa mxz040 (10) (10) ? 0two-pin * * * * * * * * * * * * * * * * * * * * * * * * * * * three-pin 20.00 to 25.00 csa mxz004 none none ? 0two-pin * * * * * * * * * * * * * * * * * * * * * * * * * * * three-pin c 2 c 1 x0 x1 x0 x1 c 1 c 2 * recommended circuit (2 contacts) recommended circuit (3 contacts) * c 1 , c 2 internally connected. * : murata mfg. co., ltd.
MB91121 70 ? smd type *1 : feedback resistor rf is built in the lsi. *2 : no dumping resistor is required. ( ) : c 1 and c 2 integrated oscillation frequency [mhz] model name circuit constants pin type c1[pf] c1[pf] rf[ w ]* 1 rd[ w ]* 2 10.00 to 13.00 csacs mt 30 30 ? 0two-pin cstcs mt (30) (30) ? 0three-pin 13.01 to 15.99 csacs mx040 15 15 ? 0two-pin cstcs mx0c3 (15) (15) ? 0three-pin 16.00 to 19.99 csacs mx040 10 10 ? 0two-pin cstcs mx0c2 (10) (10) ? 0three-pin 20.00 to 25.00 csacs mx040 none none ? 0two-pin * * * * * * * * * * * * * * * * * * * * * * * * * * * three-pin
MB91121 71 (4) reset input ratings (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst ? t cp 5 ? ns rst 0.2 v cc t rstl , t hstl
MB91121 72 (5) power-on reset (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. power supply rising time t r v cc v cc = 3.3 v 50 m s18ms v cc < 0.2 v before the power supply rising power supply shut off time t off v cc ? 1 ? ms repeated operations oscillation stabilizing time t osc ?? 2 t c 2 21 + 300 m s ? ns 0.2 v t r 0.9 v cc v cc v ss v cc rst v cc t off t osc t rstl a voltage rising rate of 50 mv/ms or less is recommended. sudden change in supply voltage during operation may initiate a power-on sequence. to change supply voltage during operation, it is recommended to smoothly raise the voltage to avoid rapid fluctuations in the supply voltage. note: (oscillation stabilizing time) note: set rst pin to ??level when turning on the device, at least the described above duration after the supply voltage reaches vcc is necessary before turning the rst to ??level. 336 ms approx. (@12.5 mhz)
MB91121 73 (6) normal bus access read/write operation *1 : when bus timing is delayed by automatic wait insertion or rdy input, add (t cyc extended cycle number for delay) to this rating. *2 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation : (2 - n / 2) t cyc - 40 (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. cs0 to cs5 delay time t chcsl clk cs0 to cs5 ? ? 15 ns t chcsh ? 15 ns address delay time t chav clk a24 to a00 ? 15 ns data delay time t chdv clk d31 to d16 ? 15 ns rd delay time t clrl clk rd ? 10 ns t clrh ? 10 ns wr0 , wr1 delay time t clwl clk wr0 , wr1 ? 10 ns t clwh ? 10 ns valid address ? valid data input time t avdv a24 to a00 d31 to d16 ? 3 / 2 t cyc - 40 ns *1 *2 rd ? valid data input time t rldv rd d31 to d16 ? t cyc - 25 ns *1 data set up ? rd - time t dsrh 25 ? ns rd -? data hold time t rhdx 0 ? ns
MB91121 74 v oh v ol v oh v ol ba2 v oh t chav v ol v oh v ol t clrl v ol t clwl t clwh v ol t chdv v ol v oh v ol v oh t clrh v oh v ih v il v ih v il t dsrh t rhdx v oh v oh v ol t chcsh v oh ba1 t cyc t chcsl t rldv t avdv clk write read cs0 to cs5 a24 to a00 rd d31 to d16 wr0 , wr1 d31 to d16
MB91121 75 (7) ready input timing (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. rdy set up time ? clk t rdys rdy clk ? 20 ? ns clk ? rdy hold time t rdyh clk rdy 0 ? ns v oh v oh v ol v ol v il v ih v ih v il t rdyh t rdyh t cyc t rdys t rdys clk rdy when wait(s) is inserted. rdy when no wait is inserted.
MB91121 76 (8) hold timing note : there is a delay time of more than 1 cycle from brq input to bgrnt change. (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. bgrnt delay time t chbgl clk bgrnt ? ? 10 ns t chbgh ? 10 ns pin floating ? bgrnt time t xhal bgrnt t cyc - 10 t cyc + 10 ns bgrnt -? pin valid time t hahv t cyc - 10 t cyc + 10 ns v oh t chbgl v ol v oh v oh v oh v oh t chbgh t cyc t hahv t xhal clk each pin high impedance brq bgrnt
MB91121 77 (9) normal dram mode read/write cycle *1 : when q1 cycle or q4 cycle is extended for 1 cycle, add t cyc time to this rating. *2 : rating at a gear cycle of 1. when a gear cycle of 1/2, 1/4, 1/8 is selected, substitute n in the following equation with 1/2, 1/4, 1/8, respectively. equation : (3 - n / 2) t cyc - 20 (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk ras ? ? 10 ns t chral ? 10 ns cas delay time t clcasl clk cas ? 10 ns t clcash ? 10 ns row address delay time t chrav clk a24 to a00 ? 15 ns column address delay time t chcav ? 15 ns dw delay time t chdwl clk dw ? 15 ns t chdwh ? 15 ns output data delay time t chdv1 clk d31 to d16 ? 15 ns ras ? valid data input time t rldv ras d31 to d16 ? 5 / 2 t cyc - 20 ns *1 *2 cas ? valid data input time t cldv cas d31 to d16 ? t cyc - 17 ns *1 cas - ? data hold time t cadh 0 ? ns
MB91121 78 v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v oh v ol q2 q1 q3 q4 q5 v oh v oh v ol v ol v ol v oh t chral v ol t clcasl v oh t chrav v il v ih v il v ih t cadh v ol v oh t chdwl t chdwh t chdv1 t cyc t clrah t chcav t clcash t rldv t cldv v ol v oh write d31 to d16 column address clk row address read d31 to d16 ras cas a24 to a00 dw
MB91121 79 (10) normal dram mode fast page read/write cycle * : when q4 cycle is extended for 1 cycle, add t cyc time to this rating. (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk, ras ? ? 10 ns cas delay time t clcasl clk cas ? 10 ns t clcash ? 10 ns column address delay time t chcav clk a24 to a00 ? 15 ns dw delay time t chdwh clk, dw ? 15 ns output data delay time t chdv1 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv cas d31 to d16 ? t cyc - 17 ns * cas -? data hold time t cadh 0 ? ns
MB91121 80 v ol v oh v ol v oh t clcash v ol v oh v oh v ol v oh v ol v oh t chdwh t chdv1 v il v ih q4 q5 v oh v ol q5 v ol q4 q5 v oh v ol t clrah v oh v oh v ol t clcasl v il v ih t cadh t chcav t cldv column address column address column address write read read read d31 to d16 clk d31 to d16 ras cas a24 to a00 dw write
MB91121 81 (11) single dram timing (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah2 clk ras ? ? 10 ns t chral2 ? 10 ns cas delay time t chcasl2 clk cas ? n / 2 t cyc + 8 ns t chcash2 ? 10 ns row address delay time t chrav2 clk a24 to a00 ? 15 ns column address delay time t chcav2 ? 15 ns dw delay time t chdwl2 clk dw ? 15 ns t chdwh2 ? 15 ns output data delay time t chdv2 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv2 cas d31 to d16 ? (1 - n / 2) t cyc - 17 ns cas - ? data hold time t cadh2 0ns
MB91121 82 column-2 t chcash2 t chral2 t chdwh2 t chdwl2 t chdv2 t chdv2 q2 q3 v oh v oh v oh v oh v oh v oh v oh v oh v ol v ol v ol v ol v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol q1 q4s q4s q4s t cadh2 t cldv2 t chrav2 t chcav2 t chcasl2 t cyc v oh v oh t clrah2 v oh v ol v ol v ih v il v ih v il column-0 row address column-1 * 1 2 write-0 write-1 write-2 read-1 read-2 read-0 d31 to d16 clk d31 to d16 ras cas a24 to a00 dw * *1 : q4s indicates q4sr (read) of single dram cycle or q4sw (write) cycle. *2 : indicates the timing when the bus cycle begins from the high spead page mode.
MB91121 83 (12) hyper dram timing (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah3 clk ras ? ? 10 ns t chral3 ? 10 ns cas delay time t chcasl3 clk cas ? n / 2 t cyc + 8ns t chcash3 ? 10 ns row address delay time t chrav3 clk a24 to a00 ? 15 ns column address delay time t chcav3 ? 15 ns rd delay time t chrl3 clk rd ? 15 ns t chrh3 ? 15 ns t clrl3 ? 15 ns dw delay time t chdwl3 clk dw ? 15 ns t chdwh3 ? 15 ns output data delay time t chdv3 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv3 cas d31 to d16 ? t cyc - 20 ns cas ? data hold time t cadh3 0 ? ns
MB91121 84 t chcash3 t chral3 t chdwh3 t chdwl3 t chdv3 t chdv3 q2 q3 v oh v oh v oh v oh v oh v oh v oh v oh v ol v ol v ol v ol v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol v oh v ol q1 q4h q4h q4h v ol t cadh3 t cldv3 t chrav3 t clrl3 v ol t chrl3 t chcasl3 t cyc v oh v ol t clrah3 v oh v ol v ol v ih v il v ih v il column-0 column-1 *1 v oh v ol column-2 t chrh3 t chcav3 *2 *2 row address write-0 write-1 write-2 read-1 read-0 d31 to d16 clk d31 to d16 ras cas a24 to a00 dw rd *1 : q4h indicates q4hr (read) of hyper dram cycle or q4hw (write) cycle. *2 : indicates the timing when the bus cycle begins from the high spead page mode.
MB91121 85 (13) cbr refresh (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk ras ? ? 10 ns t chral ? 10 ns cas delay time t clcasl clk cas ? 10 ns t clcash ? 10 ns t clcash clk ras cas v ol v ol r4 v oh v ol t clrah r3 r2 r1 v ol v oh v oh v oh v ol t chral t clcasl dw t cyc
MB91121 86 (14) self refresh (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. ras delay time t clrah clk ras ? ? 10 ns t chral ? 10 ns cas delay time t clcasl clk cas ? 10 ns t clcash ? 10 ns clk ras cas v ol t chral sr1 v oh t chcasl t clrah v oh sr2 v oh sr3 v ol v ol sr3 v ol v oh v oh t clcash t cyc
MB91121 87 (15) uart timing note : this rating is for ac characteristics in clk synchronous mode. t cycp is a cycle time of peripheral system clock (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc internal shift clock mode 8t cycp ? ns sclk ? sout delay time t slov - 80 80 ns valid sin ? sclk - t ivsh 100 ? ns sclk - ? valid sin hold time t shix 60 ? ns serial clock h pulse width t shsl external shift clock mode 4t cycp ? ns serial clock l pulse width t slsh 4t cycp ? ns sclk ? sout delay time t slov ? 150 ns valid sin ? sclk - t ivsh 60 ? ns sclk - ? valid sin hold time t shix 60 ? ns sclk sout sin sclk sout sin t scyc t slov t ivsh t shix t slov t slsh t shsl t ivsh t shix v ol v oh v ol v il v il v ih v ih v oh v ol v ih v il v oh v ol v ih v il v ih v il v ih v il ? internal shift clock mode ? external shift clock mode
MB91121 88 (16) trigger system input timing note : t cycp is a cycle time of peripheral system clock (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. a/d start trigger input time t trgh t trgl at g ? 5t cycp ? ns external interrupt input time trg0 to trg3 atg trg0 to trg3 t trgh t trgl v il v il v ih v ih
MB91121 89 (17) dma controller timing (v cc = 3.0 v to 3.6 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name condition value unit remarks min. max. dreq input pulse width t drwh dreq0 to dreq2 ? 2t cyc ? ns dack delay time (normal bus) (normal dram) t cldl clk dack0 to dack2 ? 6ns t cldh ? 6ns eop delay time (normal bus) (normal dram) t clel clk eop0 to eop2 ? 6ns t cleh ? 6ns dack delay time (single dram) (hyper dram) t chdl clk dack0 to dack2 ? n / 2 t cyc ns t chdh ? 6ns eop delay time (single dram) (hyper dram) t chel clk eop0 to eop2 ? n / 2 t cyc ns t cheh ? 6ns clk dreq0 to dreq2 v oh v oh v ih v ih v ol v ol v ol v ol v oh v oh dack0 to dack2 eop0 to eop2 (normal bus) (normal dram) dack0 to dack2 eop0 to eop2 (single dram) (hyper dram) t cyc t drwh t cldl t clel t chdl t chel t cldh t cleh t chdh
MB91121 90 5. a/d converter block electrical characteristics *1 : machine clock = 25 mhz *2 : current value for a/d converters not in operation, cpu stop mode (v cc = av cc = avrh = 3.3 v) note : as the absolute value of avrh decreases, relative error increases. output impedance of external circuit of analog input under following conditions; output impedance of external circuit < 5 k w if output impedance of external circuit is too high, analog voltage sampling time may be too short for accurate sampling. analog input circuit example (v cc = av cc = avrh = 3.3 v, av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name value unit min. typ. max. resolution ?? ? 10 10 bit total error ?? ? ? 5.0 lsb linearity error ?? ? ? 3.5 lsb differentiation linearity error ?? ? ? 2.0 lsb zero transition voltage v ot an0 to an7 - 1.5 + 0.5 + 2.5 lsb full-scale transition voltage v fst an0 to an7 avrh - 4.5 avrh - 1.5 avrh + 0.5 lsb conversion time ?? 5.6* 1 ??m s analog port input current i ain an0 to an7 ? 0.1 10 m a analog input voltage v ain an0 to an7 av ss ? avrh v reference voltage ? avrh av ss ? av cc v power supply current i a av cc ? 4 ? ma i ah ?? 5* 2 m a reference voltage supply current i r avrh ? 200 ?m a i rh ?? 5* 2 m a conversion variance between channels ? an0 to an7 ?? 5lsb r on1 r on1 : 0. 2 k w r on2 : 1. 4 k w r on3 : 1. 4 k w r on4 : 0. 2 k w c 0 : 16.6 pf c 1 : 4.0 pf r on2 r on3 r on4 c 1 c 0 sample-and-hold circuit analog input comparator note : these values are given for reference purposes.
MB91121 91 6. a/d converter glossary ? resolution the smallest change in analog voltage detected by a/d converter. ? linearity error a deviation of actual conversion characteristic from a line connecting the zero-traction point (between 00 0000 0000 ? 00 0000 0001) to the full-scale transition point (between 11 1111 1110 ? 11 1111 1111) . ? differential linearity error a deviation of a step voltage for changing the lsb of output code from ideal input voltage. 3ff 3fe 3fd 004 003 002 001 avrl avrh {1 lsb (n - 1) + v ot } v nt v fst n - 1 avrl avrh n - 2 n n + 1 v nt v (n + 1)t linearity error analog input actual conversion characteristic actual conversion characteristic ideal characteristic (measured value) (measured value) v ot (measured value) differential linearity error analog input actual conversion characteristic ideal characteristic actual conversion characteristic (measured value) (measured value) digital output digital output 1 lsb = [v] v fst - v ot 1022 linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb v ot : a voltage for causing transition of digital output from (000) h to (001) h [lsb] differential linearity error of digital output n = v (n + 1)t - v nt 1 lsb [lsb] - 1 v fst : a voltage for causing transition of digital output from (3fe) h to (3ff) h v nt : a voltage for causing transition of digital output from (n - 1) h to n
MB91121 92 ? total error a difference between actual value and theoretical value. the overall error includes zero-transition error, full- scale transition error and linearity error. 3ff 3fe 3fd 004 003 002 001 avrl avrh 1.5 lsb 0.5 lsb v nt {1 lsb (n - 1) + 0.5 lsb} v nt : a voltage for causing transition of digital output from (n - 1) to n total error analog input actual conversion characteristic (measured value) actual conversion characteristic ideal characteristic (ideal value) = avrl + 0.5 lsb [lsb] v ot (ideal value) = avrl - 1.5 lsb [v] [v] v fst total error of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb digital output 1 lsb (ideal value) = [v] avrh - avrl 1024
MB91121 93 n ordering information part number package remarks MB91121pfv 120-pin plastic lqfp (fpt-120p-m21)
MB91121 94 n package dimension c 1998 fujitsu limited f120033s-2c-2 1 30 60 31 90 61 120 91 16.00?.10(.630?004)sq 18.00?.20(.709?008)sq 0.50(.020) 0.22?.05 (.009?002) m 0.08(.003) index .006 ?001 +.002 ?.03 +0.05 0.145 "a" 0.08(.003) lead no. .059 ?004 +.008 ?.10 +0.20 1.50 details of "a" part 0~8 (mounting height) 0.45/0.75 (.018/.030) 0.25(.010) (.004?002) 0.10?.05 (stand off) dimensions in mm (inches) 120-pin plastic lqfp (fpt-120p-m21)
MB91121 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9909 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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