? semiconductor components industries, llc, 2008 september, 2008 ? rev. 0 1 publication order number: nss40300d/d NSS40300DDR2G dual 40 v, 6.0 a, low v ce(sat) pnp transistor on semiconductor?s e 2 poweredge family of low v ce(sat) transistors are surface mount devices featuring ultra low saturation voltage (v ce(sat) ) and high current gain capability. these are designed for use in low voltage, high speed switching applications where affordable efficient energy control is important. typical applications are low voltage motor controls in mass storage products such as disc drives and tape drives. in the automotive industry they can be used in air bag deployment and in the instrument cluster. the high current gain allows e 2 poweredge devices to be driven directly from pmu?s control outputs, and the linear gain (beta) makes them ideal components in analog amplifiers. features ? halide free ? this is a pb ? free device maximum ratings (t a = 25 c) rating symbol max unit collector-emitter voltage v ceo ? 40 vdc collector-base voltage v cbo ? 40 vdc emitter-base voltage v ebo ? 7.0 vdc collector current ? continuous i c ? 3.0 a collector current ? peak i cm ? 6.0 a electrostatic discharge esd hbm class 3b mm class c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. device package shipping ? ordering information NSS40300DDR2G soic ? 8 (pb ? free) 2500 / tape & reel device marking soic ? 8 case 751 style 16 http://onsemi.com 40 volts 6.0 amps pnp low v ce(sat) transistor equivalent r ds(on) 80 m ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. collector 7,8 2 base 1 emitter collector 5,6 4 base 3 emitter 1 8 40300 ayww 1 8 40300 = specific device code a = assembly location y = year ww = work week = pb ? free package (note: microdot may be in either location)
NSS40300DDR2G http://onsemi.com 2 thermal characteristics characteristic symbol max unit single heated total device dissipation (note 1) t a = 25 c derate above 25 c p d 576 4.6 mw mw/ c thermal resistance, junction ? to ? ambient (note 1) r ja 217 c/w total device dissipation (note 2) t a = 25 c derate above 25 c p d 676 5.4 mw mw/ c thermal resistance, junction ? to ? ambient (note 2) r ja 185 c/w dual heated (note 3) total device dissipation (note 1) t a = 25 c derate above 25 c p d 653 5.2 mw mw/ c thermal resistance, junction ? to ? ambient (note 1) r ja 191 c/w total device dissipation (note 2) t a = 25 c derate above 25 c p d 783 6.3 mw mw/ c thermal resistance, junction ? to ? ambient (note 2) r ja 160 c/w junction and storage temperature range t j , t stg ? 55 to +150 c 1. fr ? 4 @ 10 mm 2 , 1 oz. copper traces, still air. 2. fr ? 4 @ 100 mm 2 , 1 oz. copper traces, still air. 3. dual heated values assume total power is the sum of two equally powered devices.
NSS40300DDR2G http://onsemi.com 3 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics collector ? emitter breakdown voltage (i c = ? 10 madc, i b = 0) v (br)ceo ? 40 ? ? vdc collector ? base breakdown voltage (i c = ? 0.1 madc, i e = 0) v (br)cbo ? 40 ? ? vdc emitter ? base breakdown voltage (i e = ? 0.1 madc, i c = 0) v (br)ebo ? 7.0 ? ? vdc collector cutoff current (v cb = ? 40 vdc, i e = 0) i cbo ? ? ? 0.1 adc emitter cutoff current (v eb = ? 6.0 vdc) i ebo ? ? ? 0.1 adc on characteristics dc current gain (note 4) (i c = ? 10 ma, v ce = ? 2.0 v) (i c = ? 500 ma, v ce = ? 2.0 v) (i c = ? 1.0 a, v ce = ? 2.0 v) (i c = ? 2.0 a, v ce = ? 2.0 v) h fe 250 220 180 150 380 340 300 230 ? ? ? ? collector ? emitter saturation voltage (note 4) (i c = ? 0.1 a, i b = ? 0.010 a) (i c = ? 1.0 a, i b = ? 0.100 a) (i c = ? 1.0 a, i b = ? 0.010 a) (i c = ? 2.0 a, i b = ? 0.200 a) v ce(sat) ? ? ? ? ? 0.013 ? 0.075 ? 0.130 ? 0.135 ? 0.017 ? 0.095 ? 0.170 ? 0.170 v base ? emitter saturation voltage (note 4) (i c = ? 1.0 a, i b = ? 0.01 a) v be(sat) ? ? 0.780 ? 0.900 v base ? emitter turn ? on voltage (note 4) (i c = ? 0.1 a, v ce = ? 2.0 v) v be(on) ? ? 0.660 ? 0.750 v cutoff frequency (i c = ? 100 ma, v ce = ? 5.0 v, f = 100 mhz) f t 100 ? ? mhz input capacitance (v eb = ? 0.5 v, f = 1.0 mhz) cibo ? 250 300 pf output capacitance (v cb = ? 3.0 v, f = 1.0 mhz) cobo ? 50 65 pf switching characteristics delay (v cc = ? 30 v, i c = ? 750 ma, i b1 = ? 15 ma) t d ? ? 60 ns rise (v cc = ? 30 v, i c = ? 750 ma, i b1 = ? 15 ma) t r ? ? 120 ns storage (v cc = ? 30 v, i c = ? 750 ma, i b1 = ? 15 ma) t s ? ? 400 ns fall (v cc = ? 30 v, i c = ? 750 ma, i b1 = ? 15 ma) t f ? ? 130 ns 4. pulsed condition: pulse width = 300 sec, duty cycle 2%.
NSS40300DDR2G http://onsemi.com 4 typical characteristics figure 1. collector emitter saturation voltage vs. collector current figure 2. collector emitter saturation voltage vs. collector current i c , collector current (a) i c , collector current (a) 10 1 0.1 0.01 0.001 0 0.05 0.10 0.15 0.20 0.25 10 1 0.1 0.01 0.001 0 0.05 0.10 0.15 0.20 0.25 0.30 figure 3. dc current gain vs. collector current figure 4. base emitter saturation voltage vs. collector current i c , collector current (a) i c , collector current (a) 10 1 0.1 0.01 0.001 0 100 200 300 500 600 700 800 10 1 0.1 0.01 0.001 0.3 0.4 0.5 0.6 0.7 0.8 1.0 1.1 figure 5. base emitter turn ? on voltage vs. collector current figure 6. saturation region i c , collector current (a) i b , base current (a) 10 1 0.1 0.01 0.001 0.2 0.3 0.4 0.5 0.7 0.8 0.9 1.0 0.1 0.01 0.001 0.0001 0 0.2 0.6 0.8 1.0 1.4 1.8 2.0 v ce(sat) , collector ? emitter saturation voltage (v) v ce(sat) , collector ? emitter saturation voltage (v) h fe , dc current gain v be(sat) , base ? emitter saturation voltage (v) v be(on) , base ? emitter turn ? on voltage (v) v ce(sat) , collector ? emitter voltage (v) i c /i b = 10 150 c 25 c ? 55 c i c /i b = 100 150 c 25 c ? 55 c 400 150 c (5.0 v) 150 c (2.0 v) 25 c (5.0 v) 25 c (2.0 v) ? 55 c (5.0 v) ? 55 c (2.0 v) 0.9 i c /i b = 10 150 c 25 c ? 55 c 0.6 v ce = ? 2.0 v 150 c 25 c ? 55 c 0.4 1.2 1.6 100 ma 1 a 2 a 3 a
NSS40300DDR2G http://onsemi.com 5 typical characteristics figure 7. input capacitance figure 8. output capacitance v eb , emitter base voltage (v) v cb , collector base voltage (v) 6 5 4 3 2 1 0 100 150 200 250 300 350 35 30 25 20 15 10 5 0 30 40 50 60 70 80 90 100 c ibo , input capacitance (pf) c obo , output capacitance (pf) 40 c obo (pf) c ibo (pf) figure 9. safe operating area 10 ms 100 ms 1 s thermal limit 1 ms v ce (v dc ) 100 1.0 0.1 0.01 0.001 0.1 10 i c (a) 1.0 10 single pulse test at t a = 25 c 0.01
NSS40300DDR2G http://onsemi.com 6 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* style 16: pin 1. emitter, die #1 2. base, die #1 3. emitter, die #2 4. base, die #2 5. collector, die #2 6. collector, die #2 7. collector, die #1 8. collector, die #1 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nss40300d/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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