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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit march 2005 rev. 1.0.1 general description the xrt83sl314 is a fully integrated 14-channel short-haul line interface unit (liu) that operates from a single 3.3v power supply. using internal termination, the liu provides one bill of materials to operate in t1, e1, or j1 mode independently on a per channel basis with minimum external components. the liu features are programmed through a standard microprocessor interface. exar?s liu has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the liu is powered off. key design features within the liu optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. the on-chip clock synthesizer generates t1/e1/j1 clock rates from a selectable external clock frequency and has five output clock refe rences that can be used for external timing (8khz, 1.544mhz, 2.048mhz, nxt1/j1, nxe1). additional features include rlos, a 16-bit lcv counter for each channel, ais, qrss generation/ detection, network loop c ode generation/detection, taos, dmo, and diagnostic loopback modes. applications ? t1 digital cross connects (dsx-1) ? isdn primary rate interface ? csu/dsu e1/t1/j1 interface ? t1/e1/j1 lan/wan routers ? public switching syst ems and pbx interfaces ? t1/e1/j1 multiplexer and channel banks ? integrated multi-service access platforms (imaps) ? integrated access devices (iads) ? inverse multiplexing for atm (ima) ? wireless base stations f igure 1. b lock d iagram of the xrt83sl314 hdb3/b8zs encoder tx jitter attenuator timing control tx pulse shaper & pattern gen hdb3/b8zs decoder rx jitter attenuator clock & data recovery peak detector & slicer rx equalizer nlcd detection nlcd generation qrss generation & detection rx equalizer control ais & los detector driver monitor 1 of 14 channels test microprocessor interface programmable master clock synthesizer line driver remote loopback digital loopback analog loopback tclk tpos tneg rclk rpos rneg [7:0] [10:0] addr data ale u pclk mclkin 8khzout mclke1out mclkt1out mclke1nout mclkt1nout rtip rring tring ttip txon rxon ict reset u pts2 u pts1 rxtsel test u pts0 dmo rlos int cs rdy_ta rd_we wr_r/w cs[5:1]
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 2 features ? fully integrated 14-channel short haul transceivers for t1/j1 (1.5 44mhz) and e1 (2.048mhz) applications. ? t1/e1/j1 short haul and clock rate are per port selectable through software without changing components. ? internal impedance matching on both receive and transmit for 75 ? (e1), 100 ? (t1), 110 ? (j1), and 120 ? (e1) applications are per port selectable through software without changing components. ? power down on a per channel basis with independent receive and transmit selection. ? five pre-programmed transmit pulse settings for t1 short haul applications. ? arbitrary pulse generators for both t1 and e1 modes. ? on-chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis. ? independent crystal-less digital jitter attenuators (ja) with 32-bit or 64-bit fifo for the receive and transmit paths ? on-chip frequency multiplier generates t1 or e1 master clocks from a variety of external clock sources (8, 16, 56, 64, 128, 256khz and 1x, 2x, 4x, 8x t1 or e1) ? driver failure monitor output (dmo) alerts of possible system or external component problems. ? transmit outputs and receive inputs may be "high" impedance for protection or redundancy applications on a per channel basis. ? support for automatic protection switching. ? 1:1 and 1+1 protection without relays. ? receive monitor mode handles 0 to 29db resistive attenuation (flat loss) along with 0 to 6db cable loss for both t1 and e1. ? receiver line attenuation indication output in 1db steps. ? loss of signal (rlos) according to itu-t g.775/ ets300233 (e1) and ansi t1.403 (t1/j1). ? programmable receive slicer threshold (45%, 50%, 55%, or 68%) for improved receiver interference immunity. ? programmable data stream muting upon rlos detection. ? on-chip hdb3/b8zs encoder/decoder with an internal 16-bit lcv counter for each channel. ? on-chip digital clock recovery circuit for high input jitter tolerance. ? qrss pattern generator and detection for testing and monitoring. ? error and bipolar violation insertion and detection. ? transmit all ones (taos) and in-band network loop up and loop down code generation. ? automatic loop code detection for remote loopback activation. ? supports local analog, remote, digital, and dual loopback modes. ? low power dissipation: 170mw per channel (50% density). ? 250mw per channel maximum power dissipation (100% density). ? single 3.3v supply operation (3v to 5v i/o tolerant). ? 304-pin tbga package ? -40c to +85c temperature range ? supports gapped clocks for mapper/multiplexer applications. product ordering information p roduct n umber p ackage t ype o perating t emperature r ange xrt83sl314ib 304 lead tbga -40c to +85c
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 3 pin out of the xrt83sl314 a b c d e f g h j k l m n p r t u v w y aa ab ac 1 unnamed.12 unnamed.17 rgnd_5 rring_5 rtip_5 rvdd_4 rtip_4 rring_4 rgnd_4 unnamed.16 unnamed.10 rgnd_3 rring_3 rtip_3 rvdd_3 rtip_2 rring_2 rgnd_2 rring_1 rtip_1 unnamed.9 rlos unnamed.0 2 ictb dgnd_drv tring_5 tvdd_5 rvdd_5 rclk_5 rclk_4 tring_4 dvdd_3_4_5 unnamed.14 dgnd_3_4_5 tring_3 tvdd_3 rclk_3 rclk_2 rvdd_2 tring_2 dvdd_1_2 rgnd_1 rvdd_1 rclk_1 upclk dvdd_drv 3 tclk_5 intb dvdd_pre unnamed.13 ttip_5 rneg_5 rneg_4 ttip_4 tvdd_4 dvdd_drv agnd_bias ttip_3 rneg_3 rneg_2 ttip_2 tvdd_2 dgnd_drv tring_1 ttip_1 rneg_1 rdy_dtackb d[6] d[5] 4 mclke1xn tpos_4 tpos_5 test unnamed.11 tgnd_5 rpos_5 rpos_4 tgnd_4 avdd_bias dgnd_pre tgnd_3 rpos_3 rpos_2 tgnd_2 dgnd_1_2 tvdd_1 tgnd_1 rpos_1 dmo d[7] d[2] d[1] 5 mclkout_e1 tclk_4 tneg_4 tneg_5 bottom view dvdd_pre d[4] d[0] tclk_1 6 mclkin tclk_3 tneg_3 tpos_3 d[3] tpos_1 tpos_2 tclk_2 7 mclkout_t1 tpos_6 tneg_6 tclk_6 tneg_1 tneg_2 tneg_0 tclk_0 8 rvdd_6 mclkt1xn gndpll_21 eight_khz tpos_0 dgnd_drv dgnd_pre gndpll_11 9 rtip_6 rclk_6 gndpll_22 dvdd_drv gndpll_12 rclk_0 rvdd_0 rtip_0 10 rring_6 tvdd_6 rneg_6 rpos_6 rpos_0 rneg_0 tvdd_0 rring_0 11 rgnd_6 tring_6 ttip_6 tgnd_6 tgnd_0 ttip_0 tring_0 rgnd_0 12 rgnd_7 tring_7 dgnd_6_7 dvdd_6_7 dgnd_13_0 dvdd_13_0 tring_13 rgnd_13 13 rring_7 tvdd_7 ttip_7 tgnd_7 tgnd_13 ttip_13 tvdd_13 rring_13 14 rtip_7 rclk_7 rneg_7 rpos_7 rpos_13 rneg_13 rclk_13 rtip_13 15 rvdd_7 vddpll_21 vddpll_22 dgnd_pre rxtsel dvdd_up dgnd_up rvdd_13 16 dgnd_drv tclk_7 tneg_7 tclk_10 tclk_13 dvdd_drv vddpll_12 vddpll_11 17 tpos_7 tneg_10 tclk_9 tpos_9 tclk_12 tneg_11 tpos_13 tneg_13 18 tpos_10 tneg_9 tneg_8 rdb_dsb a[7] tpos_12 tpos_11 tclk_11 19 tclk_8 tpos_8 ale_as csb2 a[1] a[6] rxoff tneg_12 20 wrb_rwb csb5 csb3 dvdd_pre a[9] tgnd_8 rpos_8 rpos_9 tgnd_9 unnamed.4 dgnd_pre tgnd_10 rpos_10 rpos_11 tgnd_11 tring_11 dgnd_11_12 tgnd_12 rpos_12 dvdd_pre a[2] a[5] txoff 21 csb4 csb1 dvdd_drv unnamed.7 tvdd_8 ttip_8 rneg_8 rneg_9 ttip_9 unnamed.3 dgnd_drv ttip_10 rneg_10 rneg_11 ttip_11 tvdd_11 dvdd_11_12 tvdd_12 ttip_12 rneg_12 upts0 a[3] a[4] 22 csb resetb a[8] tring_8 rvdd_8 rclk_8 rclk_9 tvdd_9 tring_9 unnamed.1 unnamed.6 tring_10 tvdd_10 rclk_10 rclk_11 rvdd_11 dvdd_drv tring_12 rgnd_12 rclk_12 unnamed.5 upts1 a[0] 23 a[10] unnamed.2 rgnd_8 rring_8 rtip_8 rvdd_9 rtip_9 rring_9 rgnd_9 dvdd_8_9_10 dgnd_8_9_10 rgnd_10 rring_10 rtip_10 rvdd_10 rtip_11 rring_11 rgnd_11 rring_12 rtip_12 rvdd_12 dgnd_drv upts2
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit i table of contents general description............................................................................................................ .. 1 applications ....... .............. .............. .............. .............. .............. .............. .............. .......... ....................................... 1 f igure 1. b lock d iagram of the xrt83sl314.................................................................................................................... .............. 1 features ............................................................................................................................... ...................................... 2 product ordering information ..................................................................................................2 p in o ut of the xrt83sl314 .............. .............. .............. .............. .............. .............. ........... ........... .......... ................. 3 t able of c ontents ................ ................. ................ ................ ............... .............. .............. i pin descriptions by funct ion ......................................... ................................ .................... 4 m icroprocessor ............................................................................................................................... ......................... 4 r eceiver s ection ............................................................................................................................... ........................ 5 t ransmitter s ection ............................................................................................................................... ................... 8 c ontrol f unction ............................................................................................................................... ..................... 10 c lock s ection ............................................................................................................................... ........................... 10 p ower and g round ............................................................................................................................... ................... 11 n o c onnects ............................................................................................................................... ............................. 13 1.0 clock synthesizer ....................................................................................................... ................14 t able 1: i nput c lock s ource s elect ............................................................................................................................... ............... 14 f igure 2. s implified b lock d iagram of the c lock s ynthesizer ................................................................................................... 15 1.1 all t1/e1 mode .......................................................................................................... ................................. 15 2.0 receive path line interface ............................................................................................. ........15 f igure 3. s implified b lock d iagram of the r eceive p ath ............................................................................................................ 15 2.1 line termination (rtip/rring) ........................................................................................... ................... 16 2.1.1 case 1: internal termination........................................................................................... ............................... 16 t able 2: s electing the i nternal i mpedance ............................................................................................................................... ..... 16 f igure 4. t ypical c onnection d iagram u sing i nternal t ermination .......................................................................................... 16 2.1.2 case 2: internal termination with one external fixed resistor for all modes..................... 17 t able 3: s electing the v alue of the e xternal f ixed r esistor .................................................................................................... 17 f igure 5. t ypical c onnection d iagram u sing o ne e xternal f ixed r esistor .............................................................................. 17 2.2 equalizer control ....................................................................................................... .......................... 18 f igure 6. s implified b lock d iagram of the e qualizer and p eak d etector ................................................................................. 18 2.3 cable loss indicator ...... .............. .............. .............. .............. .............. .............. .......... ......................... 18 f igure 7. s implified b lock d iagram of the c able l oss i ndicator ................................................................................................ 18 2.4 equalizer attenuation flag .............................................................................................. ................ 19 f igure 8. s implified b lock d iagram of the e qualizer a ttenuation f lag .................................................................................... 19 2.5 peak detector and slicer ................................................................................................ ................... 19 t able 4: s electing the s licer l evel for the p eak d etector ....................................................................................................... 19 2.6 clock and data recovery ................................................................................................. .................. 20 f igure 9. r eceive d ata u pdated on the r ising e dge of rclk..................................................................................................... 20 f igure 10. r eceive d ata u pdated on the f alling e dge of rclk................................................................................................. 20 t able 5: t iming s pecifications for rclk/rpos/rneg................................................................................................................ .21 2.6.1 receive sensitivity .................................................................................................... .......................................... 21 f igure 11. t est c onfiguration for m easuring r eceive s ensitivity ............................................................................................ 21 2.6.2 interference margin .................................................................................................... ..................................... 22 f igure 12. t est c onfiguration for m easuring i nterference m argin ......................................................................................... 22 2.6.3 general alarm detection and interrupt generation ....................................................................... . 22 f igure 13. i nterrupt g eneration p rocess b lock ......................................................................................................................... 22 2.6.3.1 rlos (r eceiver l oss of s ignal ) ..................................................................................................................... 22 f igure 14. a nalog r eceive l os of s ignal for t1/e1/j1................................................................................................................ 23 t able 6: a nalog rlos d eclare /c lear (t ypical v alues ) for t1/e1 ............................................................................................. 23 2.6.3.2 exlos (e xtended l oss of s ignal ) .................................................................................................................. 23 2.6.3.3 ais (a larm i ndication s ignal ) ......................................................................................................................... 23 2.6.3.4 nlcd (n etwork l oop c ode d etection ) .......................................................................................................... 24 f igure 15. p rocess b lock for a utomatic l oop c ode d etection ................................................................................................ 24 2.6.3.5 flsd (fifo l imit s tatus d etection ) ............................................................................................................... 25 2.6.3.6 lcvd (l ine c ode v iolation d etection ) ........................................................................................................... 25 2.7 receive jitter attenuator . .............. .............. .............. .............. .............. .............. .......... ................... 25 2.8 hdb3/b8zs decoder .............. .............. .............. .............. .............. ........... ........... ........... ........................... 25 2.9 rpos/rneg/rclk .......................................................................................................... .............................. 26 f igure 16. s ingle r ail m ode w ith a f ixed r epeating "0011" p attern ......................................................................................... 26 f igure 17. d ual r ail m ode w ith a f ixed r epeating "0011" p attern ............................................................................................ 26
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 ii 2.10 rxmute (receiver los with data muting) ................................................................................. .... 26 f igure 18. s implified b lock d iagram of the r x mute f unction ................................................................................................... 26 3.0 t1/e1 applications ...................................................................................................... .................. 27 3.1 loopback diagnostic s ............. .............. .............. .............. ........... ........... ............ ........... ...................... 27 3.1.1 local analog loopback .................................................................................................. ................................ 27 f igure 19. s implified b lock d iagram of l ocal a nalog l oopback ................................................................................................ 27 3.1.2 remote loopback ........................................................................................................ ........................................ 27 f igure 20. s implified b lock d iagram of r emote l oopback .......................................................................................................... 27 3.1.3 digital loopback ....................................................................................................... .......................................... 28 f igure 21. s implified b lock d iagram of d igital l oopback ........................................................................................................... 28 3.1.4 dual loopback .......................................................................................................... ........................................... 28 f igure 22. s implified b lock d iagram of d ual l oopback ............................................................................................................... 28 3.2 84-channel t1/e1 multiplexer/mapper applications ............ .............. ........... ............ ........... ..... 29 f igure 23. s implified b lock d iagram of an 84-c hannel a pplication ........................................................................................... 29 t able 7: c hip s elect a ssignments ............................................................................................................................... ................... 29 3.3 line card redundancy .......... .............. .............. .............. .............. ........... ............ ........... ...................... 30 3.3.1 1:1 and 1+1 redundancy without relays .................................................................................. .................. 30 3.3.2 transmit interface with 1:1 and 1+1 redundancy ......................................................................... ......... 30 f igure 24. s implified b lock d iagram of the t ransmit i nterface for 1:1 and 1+1 r edundancy ................................................ 30 3.3.3 receive interface with 1:1 and 1+1 redundancy.......................................................................... ........... 30 f igure 25. s implified b lock d iagram of the r eceive i nterface for 1:1 and 1+1 r edundancy .................................................. 31 3.3.4 n+1 redundancy using external relays ................................................................................... ................ 31 3.3.5 transmit interface with n+1 redundancy ................................................................................. ............... 32 f igure 26. s implified b lock d iagram of the t ransmit i nterface for n+1 r edundancy ............................................................ 32 3.3.6 receive interface with n+1 redundancy .................................................................................. ................. 33 f igure 27. s implified b lock d iagram of the r eceive i nterface for n+1 r edundancy .............................................................. 33 3.4 power failure protection ................................................................................................ .................. 34 3.5 overvoltage and overcurrent pr otection ......... .............. .............. .............. ............ ........... ..... 34 3.6 non-intrusive monitoring ................................................................................................ .................... 34 f igure 28. s implified b lock d iagram of a n on -i ntrusive m onitoring a pplication ..................................................................... 34 4.0 transmit path line interface ............................................................................................ ..... 35 f igure 29. s implified b lock d iagram of the t ransmit p ath ......................................................................................................... 35 4.1 tclk/tpos/tneg digital inputs ........................................................................................... ................. 35 f igure 30. t ransmit d ata s ampled on f alling e dge of tclk...................................................................................................... 35 f igure 31. t ransmit d ata s ampled on r ising e dge of tclk........................................................................................................ 35 t able 8: t iming s pecifications for tclk/tpos/tneg................................................................................................................ .. 36 4.2 hdb3/b8zs encoder ............. .............. .............. .............. .............. .............. ........... ......... ........................... 36 t able 9: e xamples of hdb3 e ncoding ............................................................................................................................... ............. 36 t able 10: e xamples of b8zs e ncoding ............................................................................................................................... ............ 36 4.3 transmit jitter attenuator .............................................................................................. ................. 37 t able 11: m aximum g ap w idth for m ultiplexer /m apper a pplications ......................................................................................... 37 4.4 taos (transmit all ones) ................................................................................................ ..................... 37 f igure 32. taos (t ransmit a ll o nes ) .............................................................................................................................. .............. 37 4.5 transmit diagnostic features ............................................................................................ .............. 37 4.5.1 ataos (automatic transmit all ones).................................................................................... ..................... 38 f igure 33. s implified b lock d iagram of the ataos f unction ..................................................................................................... 38 4.5.2 network loop up code................................................................................................... ................................... 38 f igure 34. n etwork l oop u p c ode g eneration ............................................................................................................................ 38 4.5.3 network loop down code ................................................................................................. .............................. 38 f igure 35. n etwork l oop d own c ode g eneration ....................................................................................................................... 38 4.5.4 qrss generation........................................................................................................ .......................................... 39 t able 12: r andom b it s equence p olynomials ............................................................................................................................... .39 4.6 transmit pulse shaper and filter ........................................................................................ ........... 39 4.6.1 t1 short haul line build out (lbo) ..................................................................................... .......................... 40 t able 13: s hort h aul l ine b uild o ut ............................................................................................................................... ............... 40 4.6.2 arbitrary pulse generator for t1 and e1................................................................................ ............... 40 f igure 36. a rbitrary p ulse s egment a ssignment ......................................................................................................................... 40 4.7 dmo (digital monitor output) ............................................................................................ ................. 40 4.8 line termination (ttip/tring) ........................................................................................... .................... 41 f igure 37. t ypical c onnection d iagram u sing i nternal t ermination ......................................................................................... 41 5.0 microprocessor interface block ............. ................ ................ ................. ................ ......... 42 t able 14: s electing the m icroprocessor i nterface m ode .......................................................................................................... 42 f igure 38. s implified b lock d iagram of the m icroprocessor i nterface b lock ........................................................................ 42 5.1 the microprocessor in terface block signals ...... .............. .............. ........... ............ ........... ..... 43
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit iii t able 15: xrt84l314 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes 43 t able 16: i ntel mode : m icroprocessor i nterface s ignals ........................................................................................................... 43 t able 17: m otorola m ode : m icroprocessor i nterface s ignals ................................................................................................. 44 5.2 intel mode programmed i/o access (asynchronous ) ........... .............. .............. ............... ......... 45 f igure 39. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations .................................................. 46 t able 18: i ntel m icroprocessor i nterface t iming s pecifications .............................................................................................. 46 5.3 motorola mode programmed i/o access (synchro nous) ............... ........... ........... ........... ....... 47 f igure 40. m otorola p ower pc p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations ....................... 48 t able 19: m otorola p ower pc m icroprocessor i nterface t iming s pecifications ................................................................... 48 f igure 41. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations .................................. 49 t able 20: m otorola 68k m icroprocessor i nterface t iming s pecifications .............................................................................. 49 t able 21: m icroprocessor r egister a ddress (addr[7:0]) .......................................................................................................... 50 t able 22: m icroprocessor r egister c hannel d escription .......................................................................................................... 50 t able 23: m icroprocessor r egister g lobal d escription ............................................................................................................ 51 t able 24: m icroprocessor r egister 0 x 00 h b it d escription ........................................................................................................ 52 t able 25: e qualizer c ontrol and t ransmit l ine b uild o ut .......................................................................................................... 52 t able 26: m icroprocessor r egister 0 x 01 h b it d escription ........................................................................................................ 53 t able 27: m icroprocessor r egister 0 x 02 h b it d escription ........................................................................................................ 54 t able 28: m icroprocessor r egister 0 x 03 h b it d escription ........................................................................................................ 55 t able 29: m icroprocessor r egister 0 x 04 h b it d escription ........................................................................................................ 56 t able 30: m icroprocessor r egister 0 x 05 h b it d escription ........................................................................................................ 57 t able 31: m icroprocessor r egister 0 x 06 h b it d escription ........................................................................................................ 59 t able 32: m icroprocessor r egister 0 x 07 h b it d escription ........................................................................................................ 60 t able 33: m icroprocessor r egister 0 x 08 h b it d escription ........................................................................................................ 60 t able 34: m icroprocessor r egister 0 x 09 h b it d escription ........................................................................................................ 61 t able 35: m icroprocessor r egister 0 x 0a h b it d escription ....................................................................................................... 61 t able 36: m icroprocessor r egister 0 x 0b h b it d escription ....................................................................................................... 61 t able 37: m icroprocessor r egister 0 x 0c h b it d escription ....................................................................................................... 61 t able 38: m icroprocessor r egister 0 x 0d h b it d escription ....................................................................................................... 62 t able 39: m icroprocessor r egister 0 x 0e h b it d escription ....................................................................................................... 62 t able 40: m icroprocessor r egister 0 x 0f h b it d escription ........................................................................................................ 62 t able 41: m icroprocessor r egister 0 x e0 h b it d escription ....................................................................................................... 63 t able 42: m icroprocessor r egister 0 x e1 h b it d escription ....................................................................................................... 64 t able 43: m icroprocessor r egister 0 x e2 h b it d escription ....................................................................................................... 64 t able 44: m icroprocessor r egister 0 x e3 h b it d escription ....................................................................................................... 65 t able 45: m icroprocessor r egister 0 x e4 h b it d escription ....................................................................................................... 66 t able 46: m icroprocessor r egister 0 x e5 h b it d escription ....................................................................................................... 66 t able 47: m icroprocessor r egister 0 x e6 h b it d escription ....................................................................................................... 67 t able 48: m icroprocessor r egister 0 x e7 h b it d escription ....................................................................................................... 68 t able 49: m icroprocessor r egister 0 x e8 h b it d escription ....................................................................................................... 69 clock select register ....................................................................................................... 70 f igure 42. r egister 0 x e9 h s ub r egisters ............................................................................................................................... ...... 70 t able 50: m icroprocessor r egister 0 x e9 h b it d escription ....................................................................................................... 70 t able 51: m icroprocessor r egister 0 x ea h b it d escription ....................................................................................................... 72 t able 52: m icroprocessor r egister 0 x eb h b it d escription ....................................................................................................... 72 t able 53: e1 a rbitrary s elect ............................................................................................................................... ......................... 73 t able 54: m icroprocessor r egister 0 x ff h b it d escription ....................................................................................................... 74 electrical characteristic s................................. .......................................... .................. 75 t able 55: a bsolute m aximum r atings ............................................................................................................................... .............. 75 t able 56: dc d igital i nput and o utput e lectrical c haracteristics ........................................................................................... 75 t able 57: ac e lectrical c haracteristics ............................................................................................................................... ....... 75 t able 58: p ower c onsumption ............................................................................................................................... ......................... 76 t able 59: e1 r eceiver e lectrical c haracteristics ...................................................................................................................... 76 t able 60: t1 r eceiver e lectrical c haracteristics ...................................................................................................................... 77 t able 61: e1 t ransmitter e lectrical c haracteristics ................................................................................................................. 78 t able 62: t1 t ransmitter e lectrical c haracteristics ................................................................................................................. 78 ordering information ......................................................................................................... 79 p ackage d imensions (d ie down ).............................................................................................................................. 79 r evision h istory ............................................................................................................................... ....................... 80
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 4 pin descriptions by function microprocessor n ame p in t ype d escription cs a22 i chip select input active low signal. this signal enables the microprocessor interface by pulling chip select "low". the microprocessor interface is disabled when the chip select signal returns "high". ale_ts c19 i address latch enable input (transfer start) see the microprocessor section of this datasheet for a description. wr _r/ w a20 i write strobe input (read/write) see the microprocessor section of this datasheet for a description. rd _ we d18 i read strobe input (write enable) see the microprocessor section of this datasheet for a description. rdy _ ta aa3 o ready output (transfer acknowledge) see the microprocessor section of this datasheet for a description. int b3 o interrupt output active low signal. this signal is asserted "low" when a change in alarm status occurs. once the status registers have been read, the interrupt pin will return "high". gie (global interrupt enable) must be set "high" in the appropriate global register to enable interrupt generation. n ote : this pin is internally pulled "high" with a 50k ? resistor. pclk ab2 i micro processor clock input in a synchronous microproce ssor interface, pclk is used as the internal tim - ing reference for programming the liu. addr10 addr9 addr8 addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 a23 e20 c22 y18 aa19 ab20 ac21 ab21 aa20 y19 ac22 i address bus input addr[10:8] is used as a chip select deco der. the liu has 5 chip select output pins for enabling up to 5 additional devices for accessing internal registers. the liu has the option to select itself (master device), up to 5 additional devices, or all 6 devices simultaneousl y by setting the a ddr[10:8] pins speci - fied below. addr[7:0] is a direct address bus for permitting access to the internal registers. addr[10:8] 000 = master device 001 = chip select output 1 (pin b21) 010 = chip select output 2 (pin d19) 011 = chip select output 3 (pin c20) 100 = chip select output 4 (pin a21) 101 = chip select output 5 (pin b20) 110 = reserved 111 = all chip selects active including the master device
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 5 data7 data6 data5 data4 data3 data2 data1 data0 aa4 ab3 ac3 aa5 y6 ab4 ac4 ab5 i/o bi-directional data bus data[7:0] is a bi-directional data bus used for read and write operations. pts2 pts1 pts0 ac23 ab22 aa21 i microprocessor type select input pts[2:0] are used to select the microprocessor type interface. 000 = intel 68hc11, 8051, 80c188 (asynchronous) 001 = motorola 68k (asynchronous) 111 = motorola mpc8260, mp c860 power pc (synchronous) reset b22 i hardware reset input active low signal. when this pin is pulled "low" for more than 10s, the inter - nal registers are set to their default state. see the register description for the default values. n ote : internally pulled "high" with a 50k ? resistor. cs5 cs4 cs3 cs2 cs1 b20 a21 c20 d19 b21 o chip select output the xrt83sl314 can be used to provide the necessary chip selects for up to 5 additional devices by using the 3 msbs addr[10:8] from the 11-bit address bus. the liu allows up to 84-channel applications with only using one chip select. see the addr[10:0] definition in the pin description. receiver section n ame p in t ype d escription rxon ab19 i receive on/off input upon power up, the receivers are powered off. turning the receivers on or off can be selected through the microprocessor interface by programming the appropriate channel register if the hardwa re pin is pulled "high". if the hard - ware pin is pulled "low", all c hannels are automatically turned off. n ote : internally pulled "low" with a 50k ? resistor. rxtsel y15 i receive termination control upon power up, the receivers are in "hi gh" impedance. switching to internal termination can be selected through th e microprocessor interface by program - ming the appropriate channel register. however, to switch control to the hard - ware pin, rxtcntl must be programmed to "1" in the appropriate global register. once control has been granted to the hardware pin, it must be pulled "high" to switch to internal termination. n ote : internally pulled "low" with a 50k ? resistor. microprocessor n ame p in t ype d escription
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 6 rlos ab1 o receive loss of signal (gl obal pin for all 14-channels) when a receive loss of signal occurs for any one of the 14-channels according to itu-t g.775, the rlos pin will go "high" for a minimum of one rclk cycle. rlos will remain "high" until the loss of signal condition clears. see the receive loss of signal section of this datasheet for more details. n ote : this pin is for redundancy applications to initiate an automatic switch to the backup card. for individual channel rlos, see the register map. rclk13 rclk12 rclk11 rclk10 rclk9 rclk8 rclk7 rclk6 rclk5 rclk4 rclk3 rclk2 rclk1 rclk0 ab14 y22 r22 p22 g22 f22 b14 b9 f2 g2 p2 r2 aa2 aa9 o receive clock output rclk is the recovered clock from the incoming data stream. if the incoming signal is absent or rxon is pulled "low", rclk maintains its timing by using an internal master clock as its reference. rpos/rneg data can be updated on either edge of rclk selected by rclke in the appropriate global register. n ote : rclke is a global setting that applies to all 14 channels. rpos13 rpos12 rpos11 rpos10 rpos9 rpos8 rpos7 rpos6 rpos5 rpos4 rpos3 rpos2 rpos1 rpos0 y14 w20 p20 n20 h20 g20 d14 d10 g4 h4 n4 p4 w4 y10 o rpos/rdata output receive digital output pin. in dual rail mode, this pin is the receive positive data output. in single rail mode, this pin is the receive non-return to zero (nrz) data output. receiver section n ame p in t ype d escription
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 7 rneg13 rneg12 rneg11 rneg10 rneg9 rneg8 rneg7 rneg6 rneg5 rneg4 rneg3 rneg2 rneg1 rneg0 aa14 y21 p21 n21 h21 g21 c14 c10 f3 g3 n3 p3 y3 aa10 o rneg/lcv_of output in dual rail mode, this pin is the receive negative data output. in single rail mode, this pin is a line code violation / counter overflow indicator. if lcv is selected by programming the appropriate global register and if a line code vio - lation, a bi-polar violation, or excessive zeros occur, the lcv pin will pull "high" for a minimum of one rclk cycle. lcv will remain "high" until there are no more violations. however, if of is selected the lcv pin will pull "high" if the internal lcv counter is saturated. the lcv pin will remain "high" until the lcv counter is reset. rtip13 rtip12 rtip11 rtip10 rtip9 rtip8 rtip7 rtip6 rtip5 rtip4 rtip3 rtip2 rtip1 rtip0 ac14 y23 t23 p23 g23 e23 a14 a9 e1 g1 p1 t1 y1 ac9 i receive differential tip input rtip is the positive differential input fr om the line interface. along with the rring signal, these pins should be coupled to a 1:1 transformer for proper operation. rring13 rring12 rring11 rring10 rring9 rring8 rring7 rring6 rring5 rring4 rring3 rring2 rring1 rring0 ac13 w23 u23 n23 h23 d23 a13 a10 d1 h1 n1 u1 w1 ac10 i receive differential ring input rring is the negative differ ential input from the line interface. along with the rtip signal, these pins should be coupled to a 1:1 transformer for proper oper - ation. receiver section n ame p in t ype d escription
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 8 transmitter section n ame p in t ype d escription txon ac20 i transmit on/off input upon power up, the transmitters are powe red off. turning the transmitters on or off is selected through the micropr ocessor interface by programming the appropriate channel register if this pin is pulled "high". if the txon pin is pulled "low", all 14 transmitters are powered off. n ote : txon is ideal for redundancy applications. see the redundancy applications section of this datasheet for more details. internally pulled "low" with a 50k ? resistor. dmo y4 o digital monitor output (global pin for all 14-channels) when no transmit outpu t pulse is detected for more than 128 tclk cycles on one of the 14-channels, the dmo pin will go "high" for a minimum of one tclk cycle. dmo will remain "high" until the transmitter sends a valid pulse. n ote : this pin is for redundancy applications to initiate an automatic switch to the backup card. for individual channel dmo, see the register map. tclk13 tclk12 tclk11 tclk10 tclk9 tclk8 tclk7 tclk6 tclk5 tclk4 tclk3 tclk2 tclk1 tclk0 y16 y17 ac18 d16 c17 a19 b16 d7 a3 b5 b6 ac6 ac5 ac7 i transmit clock input tclk is the input facility clock used to sample the incoming tpos/tneg data. if tclk is absent, pulled "low", or pu lled "high", the transmitter outputs at ttip/tring can be selected to send an all ones or an all zero signal by pro - gramming tclkcnl in the appropriate global register. tpos/tneg data can be sampled on either edge of tclk sele cted by tclke in the appropriate glo - bal register. n ote : tclke is a global setting that applies to all 14 channels. tpos13 tpos12 tpos11 tpos10 tpos9 tpos8 tpos7 tpos6 tpos5 tpos4 tpos3 tpos2 tpos1 tpos0 ab17 aa18 ab18 a18 d17 b19 a17 b7 c4 b4 d6 ab6 aa6 y8 i tpos/tdata input transmit digital input pin. in dual rail mode, this pin is the transmit positive data input. in single rail mode, this pin is the transmit non-return to zero (nrz) data input. n ote : internally pulled "low" with a 50k ? resistor.
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 9 tneg13 tneg12 tneg11 tneg10 tneg9 tneg8 tneg7 tneg6 tneg5 tneg4 tneg3 tneg2 tneg1 tneg0 ac17 ac19 aa17 b17 b18 c18 c16 c7 d5 c5 c6 aa7 y7 ab7 i transmit negative data input in dual rail mode, this pin is the transmit negative data input. in single rail mode, this pin can be left unconnected. n ote : internally pulled "low" with a 50k ? resistor. ttip13 ttip12 ttip11 ttip10 ttip9 ttip8 ttip7 ttip6 ttip5 ttip4 ttip3 ttip2 ttip1 ttip0 aa13 w21 r21 m21 j21 f21 c13 c11 e3 h3 m3 r3 w3 aa11 o transmit differential tip output ttip is the positive differential output to the line interface. along with the tring signal, these pins should be coupled to a 1:2 step up transformer for proper operation. tring13 tring12 tring11 tring10 tring9 tring8 tring7 tring6 tring5 tring4 tring3 tring2 tring1 tring0 ab12 v22 t20 m22 j22 d22 b12 b11 c2 h2 m2 u2 v3 ab11 o transmit differential ring output tring is the negative differential output to the line interface. along with the ttip signal, these pins should be coupled to a 1:2 step up transformer for proper operation. transmitter section n ame p in t ype d escription
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 10 control function n ame p in t ype d escription test d4 i factory test mode for normal operation, the test pin should be tied to ground. n ote : internally pulled "low" with a 50k ? resistor. ict a2 i in circuit testing when this pin is tied "low", all output pins are forced to "high" impedance for in circuit testing. n ote : internally pulled "high" with a 50k ? resistor. clock section n ame p in t ype d escription mclkin a6 i master clock input the master clock input can accept a wide range of inputs that can be used to generate t1 or e1 clock rates on a per ch annel basis. see the register map for details. 8khzout d8 o 8khz output clock mclke1out a5 o 2.048mhz output clock mclke1nout a4 o 2.048mhz, 4.096mhz, 8.192mhz, or 16.384mhz output clock see the register map for programming details. mclkt1out a7 o 1.544mhz output clock mclkt1nout b8 o 1.544mhz, 3.088mhz, 6.176mhz, or 12.352mhz output clock see the register map for programming details.
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 11 power and ground n ame p in t ype d escription tvdd13 tvdd12 tvdd11 tvdd10 tvdd9 tvdd8 tvdd7 tvdd6 tvdd5 tvdd4 tvdd3 tvdd2 tvdd1 tvdd0 ab13 v21 t21 n22 h22 e21 b13 b10 d2 j3 n2 t3 u4 ab10 pwr transmit analog power supply (3.3v 5%) tvdd can be shared with dvdd. however, it is recommended that tvdd be isolated from the analog power supply rvdd. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through an external 0.1 f capacitor. rvdd13 rvdd12 rvdd11 rvdd10 rvdd9 rvdd8 rvdd7 rvdd6 rvdd5 rvdd4 rvdd3 rvdd2 rvdd1 rvdd0 ac15 aa23 t22 r23 f23 e22 a15 a8 e2 f1 r1 t2 y2 ab9 pwr receive analog power supply (3.3v 5%) rvdd should not be shared with other power supplies. it is recommended that rvdd be isolated from the digital power supply dvdd and the analog power supply tvdd. for best results, use an inte rnal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through an external 0.1 f capacitor. dvdd dvdd dvdd dvdd dvdd dvdd j2 v2 d12 aa12 u21 k23 pwr digital power supply (3.3v 5%) dvdd should be isolated from the analog power supplies. for best results, use an internal power plane for isolation. if an internal power plane is not avail - able, a ferrite bead can be used. every two dvdd power supply pins should be bypassed to ground through at least one 0.1 f capacitor. dvdd_drv dvdd_drv dvdd_drv dvdd_drv dvdd_drv dvdd_drv dvdd_pre dvdd_pre dvdd_pre dvdd_pre dvdd_up c21 ac2 k3 d9 aa16 u22 c3 y5 d20 y20 aa15 pwr digital power supply (3.3v 5%) dvdd should be isolated from the analog power supplies. for best results, use an internal power plane for isolation. if an internal power plane is not avail - able, a ferrite bead can be used. every two dvdd power supply pins should be bypassed to ground through at least one 0.1 f capacitor.
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 12 avdd_bias avdd_pll22 avdd_pll21 avdd_pll12 avdd_pll11 k4 c15 b15 ab16 ac16 pwr analog power su pply (3.3v 5%) avdd should be isolated from the digital po wer supplies. for best results, use an internal power plane for isolation. if an internal power plane is not available, a ferrite bead can be used. each power supply pin should be bypassed to ground through at least one 0.1 f capacitor. tgnd13 tgnd12 tgnd11 tgnd10 tgnd9 tgnd8 tgnd7 tgnd6 tgnd5 tgnd4 tgnd3 tgnd2 tgnd1 tgnd0 y13 v20 r20 m20 j20 f20 d13 d11 f4 j4 m4 r4 v4 y11 gnd transmit analog ground it?s recommended that all ground pins of this device be tied together. rgnd13 rgnd12 rgnd11 rgnd10 rgnd9 rgnd8 rgnd7 rgnd6 rgnd5 rgnd4 rgnd3 rgnd2 rgnd1 rgnd0 ac12 w22 v23 m23 j23 c23 a12 a11 c1 j1 m1 v1 w2 ac11 gnd receive analog ground it?s recommended that all ground pins of this device be tied together. dgnd dgnd dgnd dgnd dgnd dgnd l2 t4 c12 y12 u20 l23 gnd digital ground it?s recommended that all ground pins of this device be tied together. power and ground n ame p in t ype d escription
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 13 dgnd_drv dgnd_drv dgnd_drv dgnd_drv dgnd_drv dgnd_drv dgnd_pre dgnd_pre dgnd_pre dgnd_pre dgnd_up b2 u3 a16 aa8 l21 ab23 l4 d15 ab8 l20 ab15 gnd digital ground it?s recommended that all ground pins of this device be tied together. agnd_bias agnd_pll22 agnd_pll21 agnd_pll12 agnd_pll11 l3 c9 c8 y9 ac8 gnd analog ground it?s recommended that all ground pins of this device be tied together. no connects n ame p in t ype d escription nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc a1 b1 k1 l1 aa1 ac1 k2 d3 e4 k20 d21 k21 k22 l22 aa22 b23 nc no connect this pin can be left floating or tied to ground. power and ground n ame p in t ype d escription
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 14 1.0 clock synthesizer in system design, fewer clocks on the network card could reduce noise and interference. common clock references such as 8khz are readily available to netw ork designers. network card s that support both t1 and e1 modes must be able to produce 1.544mhz and 2. 048mhz transmission data. the xrt83sl314 has a built in clock synthesizer that requires only one inpu t clock reference by programming cl ksel[3:0] in the appropriate global register. a list of the input clock options is shown in table 1 . the single input clock reference is used to generate mult iple timing references. the first objective of the clock synthesizer is to generate 1.544mhz and 2.048mhz for each of the 14 channels. this allows each channel to operate in either t1 or e1 mode independent from the ot her channels. the state of the equalizer control bits in the appropriate channel registers determine whether the li u operates in t1 or e1 mode. the second objective is to generate additional output cl ock references for system use. the available output clock references are shown in figure 2 . t able 1: i nput c lock s ource s elect clksel[3:0] i nput c lock r eference 0h (0000) 2.048 mhz 1h (0001) 1.544mhz 2h (0010) 8 khz 3h (0011) 16 khz 4h (0100) 56 khz 5h (0101) 64 khz 6h (0110) 128 khz 7h (0111) 256 khz 8h (1000) 4.096 mhz 9h (1001) 3.088 mhz ah (1010) 8.192 mhz bh (1011) 6.176 mhz ch (1100) 16.384 mhz dh (1101) 12.352 mhz eh (1110) 2.048 mhz fh (1111) 1.544 mhz
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 15 f igure 2. s implified b lock d iagram of the c lock s ynthesizer 1.1 all t1/e1 mode to reduce system noise and power consumption, the xrt83sl314 offers an all t1/e1 mode. since most line card designs are configured to operate in t1 or e1 only, the liu can be selected to shut off the timing references for the mode not being used by programming the appropriate global register. by default the all t1/e1 mode is enabled (allt1/e1 bit = "0"). if the liu is configured for t1, all e1 clock references and the 8khz reference are shut off internally to the chip. this reduces the amount of internal cloc ks switching within the liu, hence reducing noise and pow er consumption. in e1 mode, the t1 clock references are internally shut off, however the 8khz reference is available. to di sable this feature, the allt1/e1 bit must be set to a "1" in the appropriate global register. 2.0 receive path line interface the receive path of the xrt83sl314 liu consists of 14 independent t1/e1/j1 receivers. the following section describes the complete re ceive path from rtip/rring inputs to rclk/rpos/rneg outputs. a simplified block diagram of the receive path is shown in figure 3 . f igure 3. s implified b lock d iagram of the r eceive p ath clock synthesizer internal reference 1.544mhz 2.048mhz input clock 8khz 1.544mhz 2.048mhz 2.048/4.096/8.192/16.384 mhz 1.544/3.088/6.176/12.352mhz 8khzout mclke1out mclkt1out mclkt1nout mclke1nout programmable programmable hdb3/b8zs decoder rx jitter attenuator clock & data recovery peak detector & slicer rx equalizer rx equalizer control rtip rring rclk rneg rpos
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 16 2.1 line termination (rtip/rring) 2.1.1 case 1: internal termination the input stage of the receive path accepts standard t1/e 1/j1 twisted pair or e1 coaxial cable inputs through rtip and rring. the physical interface is optimized by placing the terminating impedance inside the liu. this allows one bill of materials for all modes of operat ion reducing the number of external components necessary in system design. the receive termination (along with the transmit termination) impedance is selected by programming tersel[1:0] to match the lin e impedance. selecting the internal impedance is shown in ta b l e 2 . the xrt83sl314 ha s the ability to switch the in ternal termination to "high" impedance by programming rxtsel in the appropriate channel register. for internal termination, set rxtsel to "1". by default, rxtsel is set to "0" ("high" impedance). for redundancy ap plications, a dedicated hardware pin (rxtsel) is also available to control the receive termination for all chan nels simultaneously. this hardware pin takes priority over the register setting if rxtcntl is se t to "1" in the appropriate global register. if rxtcntl is set to "0", the state of this pin is ignored. see figure 4 for a typical connection diagram using the internal termination. f igure 4. t ypical c onnection d iagram u sing i nternal t ermination t able 2: s electing the i nternal i mpedance tersel[1:0] r eceive t ermination 0h (00) 100 ? 1h (01) 110 ? 2h (10) 75 ? 3h (11) 120 ? r tip r ring xrt83sl314 liu 1:1 internal impedance line interface t1/e1/j1 one bill of materials receiver input
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 17 2.1.2 case 2: internal termination with one external fixed resistor for all modes along with the internal termination, a high precision exte rnal fixed resistor can be used to optimize the return loss. this external resistor can be used for all modes of operation ensu ring one bill of materials. there are three resistor values that can be used by setting th e rxres[1:0] bits in the ap propriate channel register. selecting the value for the external fixed resistor is shown in table 3 . by default, rxres[1:0] is set to "none" for no external fi xed resistor. if an external fixed resistor is used, the xrt83sl314 uses the parallel combination of the external fixed resistor and the in ternal termination as the input impedance. see figure 5 for a typical connection diagram using the external fixed resistor. n ote : without the external resistor, the xrt83sl314 meets all retu rn loss specifications. this mode was created to add flexibility for optimizing return loss by using a high precision external resistor. f igure 5. t ypical c onnection d iagram u sing o ne e xternal f ixed r esistor t able 3: s electing the v alue of the e xternal f ixed r esistor r x res[1:0] e xternal f ixed r esistor 0h (00) none 1h (01) 240 ? 2h (10) 210 ? 3h (11) 150 ? r tip r ring xrt83sl314 liu 1:1 internal impedance line interface t1/e1/j1 r r=240 ? , 210 ? , or 150 ? receiver input
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 18 2.2 equalizer control the main objective of the equalizer is to amplify an input attenuated signal to a pre-determined amplitude that is acceptable to the peak detector circuit. using feed back from the peak detector, the equalizer will gain the input up to the maximum value specified by the equaliz er control bits, in the appropriate channel register, normalizing the signal. once the signal has reached the pre-determined amplitud e, the signal is then processed within the peak detector and slicer circuit. a simplified block diagram of the equalizer and peak detector is shown in figure 6 . f igure 6. s implified b lock d iagram of the e qualizer and p eak d etector 2.3 cable loss indicator the ability to monitor the cable loss atte nuation of the receiver inputs is a valuable fe ature. the xrt83sl314 contains a per channel, read only register for cable loss indication. clos[5:0] is a 6-bit binary word that reports the value of cable loss in 1db steps. an example of -15db cable loss attenuation is shown in figure 7 . f igure 7. s implified b lock d iagram of the c able l oss i ndicator peak detector & slicer rx equalizer rx equalizer control rtip rring -15db of cable loss equalizer and peak detector clos[5:0] = 0x0fh (15dec = 0fhex) -15db attenuated signal read only xrt83sl314
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 19 2.4 equalizer attenuation flag the ability to detect the amo unt of cable loss on the receiver inpu ts is enhanced by having the ability to generate an interrupt by programming a pre-determin ed value for cable loss into the eqflag[5:0] global register. this is particularly useful in applications where it is necessary for the liu to generate an interrupt for a cable loss which is lower than the de claration of the rlos feature (see the rlos section in this datasheet). if the contents of the eqflag[5:0] register bits are equal to or less than the contents in the cable loss indicator bits clos[5:0] for a given channel, an interrupt will be gener ated (if enabled in the appropriate channel register and gie is to "1"). using the same example in figure 7 , a simplified block diagram of the equalizer flag is shown in figure 8 . f igure 8. s implified b lock d iagram of the e qualizer a ttenuation f lag 2.5 peak detector and slicer the peak detector provides feedback to the equalizer cont rol circuit until the amplitude of the incoming signal is at an appropriate level. once this le vel is obtained, the slicer identifies the incoming signal as a "1" and passes the raw data to the clock and data recovery circuit. th e slicer threshold is selected by programming sl[1:0] in the appropriate global register. sele cting the slicer level is shown in table 4 . t able 4: s electing the s licer l evel for the p eak d etector sl[1:0] s licer l evel 0h (00) 50% 1h (01) 45% 2h (10) 55% 3h (11) 68% xrt83sl314 -15db of cable loss equalizer and peak detector clos[5:0] = 0x0fh eqflag[5:0] = 0x0fh programmable if (clos = eqflag) generate an interrupt receiver inputs rtip/rring read only
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 20 2.6 clock and data recovery the receive clock (rclk) is recovered by the clock and data recovery circuitry. an internal pll locks on the incoming data stream and outputs a clock that?s in p hase with the incoming signal . this allows for multi- channel t1/e1/j1 signals to arrive from different timing sources and remain independent. in the absence of an incoming signal, rclk maintains its timing by using the internal master clock as its reference. the recovered data can be updated on either edge of rclk. by default , data is updated on the rising edge of rclk. to update data on the falling edge of rclk, set rclke to "1" in the appropriate global register. figure 9 is a timing diagram of the receive data updated on the rising edge of rclk. figure 10 is a timing diagram of the receive data updated on the fallin g edge of rclk. the timing specifications are shown in ta b l e 5 . f igure 9. r eceive d ata u pdated on the r ising e dge of rclk f igure 10. r eceive d ata u pdated on the f alling e dge of rclk rclk rpos or rneg r dy rclk r rclk f r oh rclk rpos or rneg r dy rclk f rclk r r oh
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 21 n ote : vdd=3.3v 5%, t a =25c, unless otherwise specified 2.6.1 receive se nsitivity to meet short haul requirements, the xrt83sl314 can ac cept t1/e1/j1 signals that have been attenuated by 12db of flat loss in e1 mode or by 655 feet of cable loss along with 6db of flat loss in t1 mode. however, the xrt83sl314 can tolerate cable loss and flat loss beyond th e industry specifications. the receive sensitivity in the short haul mode is approximately 4,000 feet without experiencing bit errors, lof, pattern synchronization, etc. although data integr ity is maintained, the rlos function (i f enabled) will report an rlos condition according to the receiver loss of sign al section in this datasheet. the test configuration for measuring the receive sensitivity is shown in figure 11 . f igure 11. t est c onfiguration for m easuring r eceive s ensitivity t able 5: t iming s pecifications for rclk/rpos/rneg p arameter s ymbol m in t yp m ax u nits rclk duty cycle r cdu 45 50 55 % receive data setup time r su 150 - - ns receive data hold time r ho 150 - - ns rclk to data delay r dy - - 40 ns rclk rise time (10% to 90%) with 25pf loading rclk r - - 40 ns rclk fall time (90% to 10%) with 25pf loading rclk f - - 40 ns network analyzer e1 = prbs 2 15 - 1 t1 = prbs 2 23 - 1 external loopback xrt83sl314 14-channel long haul liu cable loss flat loss tx tx rx rx w&g ant20
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 22 2.6.2 interference margin the interference margin for the xrt83s l314 will be added when the first revision of silicon arrives. the test configuration for measuring the interference margin is shown in figure 12 . f igure 12. t est c onfiguration for m easuring i nterference m argin 2.6.3 general alarm detection and interrupt generation the receive path detects eqflag, rl os, ais, qrpd, ncld, and fls. th ese alarms can be individually masked to prevent the alarm from triggering an interrup t. to enable interrupt generation, the global interrupt enable (gie) bit must be set "high" in the appropriate gl obal register. any time a change in status occurs (it the alarms are enabled), the interrupt pin will pull "low" to indicate an alarm has occurred. once the status registers have been read , the int pin will return "high". the stat us registers are rese t upon read (rur). the interrupts are categorized in a hierarchical process block. figure 13 is a simplified block diagram of the interrupt generation process. f igure 13. i nterrupt g eneration p rocess b lock n ote : the interrupt pin is internally pulled "high" with a 50k ? resistor. 2.6.3.1 rlos (receiver loss of signal) sinewave generator flat loss w&g ant20 network analyzer cable loss xrt83sl314 14-channel liu e1 = 1,024khz t1 = 772khz e1 = prbs 2 15 - 1 t1 = prbs 2 23 - 1 tx tx rx rx external loopback global interrupt enable (gie="1") global channel interrupt status (indicates which channel(s) experienced a change in status) individual alarm status change (indicates which alarm experienced a change) individual alarm indication (indicates the alarm condition active/inactive)
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 23 in t1 mode, rlos is declared if an incoming signal ha s no transitions over a perio d of 175 +/-75 contiguous pulse intervals. however, the xrt83sl314 liu has a built in analog rlos so that the user can be notified when the amplitude of the incoming signal has been atte nuated -9db below the equalizer gain setting. for example: in t1 or e1 short haul mode, the equalizer gain setting is 15db. once the input reaches an amplitude of -24db below nominal, the liu will declare rlos. the rlos circuitry clears when the input reaches +3db relative to where it was declared. this +3db value is a pre-determined hysteresis so that transients will not cause the rlos to clear. in e1 mode, rlos is decl ared if an incoming signal has no transitions for n consecutiv e pulse intervals, where 10 n 255. according to g.775, no transitions in e1 mode is defined between -9db and -35db below nominal. figure 14 is a simplified block diagram of the analog rlos function. ta b l e 6 summarizes the analog rlos values fo r the different equalizer gain settings. f igure 14. a nalog r eceive l os of s ignal for t1/e1/j1 n ote : for programming the equalizer gain setting on a per channel basis, see the micr oprocessor register map for details. 2.6.3.2 exlos (extended loss of signal) by enabling the extended loss of signal by programming the appropriate channel register, the digital rlos is extended to count 4,096 consecutive zeros before declar ing rlos in t1 and e1 mode. by default, exlos is disabled and rlos operates in normal mode. 2.6.3.3 ais (alarm indication signal) the xrt83sl314 adheres to the itu-t g.775 specificatio n for an all ones pattern. the alarm indication signal is set to "1" if an all ones pattern (at least 99.9% ones d ensity) is present for t, where t is 3ms to 75ms in t1 mode. ais will clear when the ones dens ity is not met within the same time period t. in e1 mode, the ais is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. ais will clear when th e incoming signal has 3 or more zeros in the 512-bit window. t able 6: a nalog rlos d eclare /c lear (t ypical v alues ) for t1/e1 g ain s etting d eclare c lear 15db (short haul mode) -24db -21db 29db (monitoring gain mode) -38db -35db normalized up to eqc[4:0] setting declare los clear los -9db +3db clear los declare los +3db -9db normalized up to eqc[4:0] setting
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 24 2.6.3.4 nlcd (network loop code detection) the network loop code detection can be programmed to detect a loop-up, loop-down, or automatic loop code. if the network loop code detection is programmed for loop-up, the nlcd will be set "high" if a repeating pattern of "00001" occurs for more than 5 seconds. if the network loop code detection is programmed for loop-down, the nlcd will be set "high" if a repeating pattern of "001" occurs for more than 5 seconds. if the network loop code detection is progra mmed for automatic loop code, the liu is configured to detect a loop-up code. if a lo op-up code is detected for more than 5 seconds, the xrt83sl314 will automatically program the ch annel into a remote loopback mode. the liu will rema in in remote loopback even if the loop-up code disappears. the channel will continue in remote lo op back until a loop-down code is detected for more than 5 seconds (or, if the automatic lo op code is disabled) and then automatically return to normal operation with no loop back. the process of the automatic loop code detection is shown in figure 15 . f igure 15. p rocess b lock for a utomatic l oop c ode d etection automatic remote loopback loop-up code for 5 sec? yes no loop-down code for 5 sec? no yes disable remote loopback
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 25 2.6.3.5 flsd (fifo limit status detection) the purpose of the fifo limit status is to indicate when the read and write fifo pointers are within a pre- determined range (over-flow or under-flow indication). the flsd is set to "1" if the fifo read and write pointers are within 3-bits. 2.6.3.6 lcvd (line code violation detection) the liu contains 14 independent, 16 -bit lcv counters. when the counters reach full-scale, they remain saturated at ffffh until they are reset globally or on a per channel basis. for performance monitoring, the counters can be updated globally or on a per channel ba sis to place the contents of the counters into holding registers. the liu uses an indirect address bus to acce ss a counter for a given channel. once the contents of the counters have been placed in holdin g registers, they can be individually read out from register 0xe8h 8-bits at a time according to the bytesel bit in the appropriat e global register. by default, the lsb is in register 0xe8h until the bytesel is pulled " high" where upon the msb will be placed in the register for read back. once both bytes have been read, the next channel may be selected for read back. by default, the lvc/ofd will be set to a "1" if the receiver is currently detecting line code violations or excessive zeros for hdb3 (e1 mode) or b8zs (t1 mode). in ami mode, t he lcvd will be set to a "1" if the receiver is currently detecting bipola r violations or excessive zeros. however, if the liu is configured to monitor the 16-bit lcv counter by programming the appr opriate global register, the lcv/ofd will be set to a "1" if the counter saturates. 2.7 receive jitter attenuator the receive path has a dedicated jitter attenuator that reduces phase and frequency jitter in the recovered clock. the jitter attenuator uses a data fifo (first in first out) with a programmable depth of 32-bit or 64-bit. if the liu is used for line synchronization (loop timi ng systems), the ja should be enabled. when the read and write pointers of the fifo are within 2-bits of ov er-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corrup tion. when this condition occurs, the jitter attenuator will not attenuate input jit ter until the read/wri te pointer?s position is outside the 2- bit window. in t1 mode, the bandwidth of the ja is always set to 3hz. in e1 mode, the bandwidth is programmable to either 10hz or 1.5hz (1.5hz automati cally selects the 64-bit fifo depth). the ja has a clock delay equal to ? of the fifo bit depth. n ote : if the liu is used in a multiplexer/mapper application where stuffing bits are typically re moved, the transmit path has a dedicated jitter attenuator to smooth out the gapped clock. see the transmit section of this datasheet. 2.8 hdb3/b8zs decoder in single rail mode, rpos can decode ami or hdb3/b8z s signals. for e1 mode, hdb3 is defined as any block of 4 successive zeros replaced with ooov or boov, so that two successive v pulses are of opposite polarity to prevent a dc component. in t1 mode, 8 successive zeros are replaced with ooovbovb. if the hdb3/b8zs decoder is selected, the re ceive path removes the v and b pulses so that the original data is output to rpos.
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 26 2.9 rpos/rneg/rclk the digital output data can be programmed to either single rail or dual rail formats. figure 16 is a timing diagram of a repeating "0011" pattern in single-rail mode. figure 17 is a timing diagram of the same fixed pattern in dual rail mode. f igure 16. s ingle r ail m ode w ith a f ixed r epeating "0011" p attern f igure 17. d ual r ail m ode w ith a f ixed r epeating "0011" p attern 2.10 rxmute (receiver los with data muting) the receive muting function can be selected by setting rx mute to "1" in the appropriate global register. if selected, any channel that experiences an rlos c ondition will automatically pu ll rpos and rneg "low" to prevent data chattering. if rlos does not occur, the rxmute will remain inactive until an rlos on a given channel occurs. the default setting for rxmute is "0" which is disabled . a simplified block diagram of the rxmute function is shown in figure 18 . f igure 18. s implified b lock d iagram of the r x mute f unction rclk rpos 00 0 1 1 rclk rpos 00 0 1 1 rneg rlos rxmute rpos rneg
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 27 3.0 t1/e1 applications this applications section describes common t1/e1 system considerations along with references to application notes available for reference where applicable. 3.1 loopback diagnostics the xrt83sl314 supports several loopback modes for diagnostic testing. the following section describes the local analog loopback, remote loopback, digital loopback, and dual loopback modes. 3.1.1 local analog loopback with local analog loopback activated, the transmit outpu t data at ttip/tring is intern ally looped back to the analog inputs at rtip/rring. external inputs at rtip/rring are ignored while valid transmit output data continues to be sent to the line. a simplified bl ock diagram of local analog loopback is shown in figure 19 . f igure 19. s implified b lock d iagram of l ocal a nalog l oopback n ote : the transmit diagnostic features such as taos, nlc gener ation, and qrss take priority over the transmit input data at tclk/tpos/tneg. 3.1.2 remote loopback with remote loopback activated, the receive input data at rtip/rring is internally lo oped back to the transmit output data at ttip/tring. the remote loopback incl udes the receive ja (if enabled). the transmit input data at tclk/tpos/tneg are ignored while valid receive output data continues to be sent to the system. a simplified block diagram of remote loopback is shown in figure 20 . f igure 20. s implified b lock d iagram of r emote l oopback encoder decoder timing control data and clock recovery ja ja tx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg rx encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 28 3.1.3 digital loopback with digital loopback activated, the transmit input da ta at tclk/tpos/tneg is looped back to the receive output data at rclk/rpos/rneg. the digital loopback mode includes the transmit ja (if enabled). the receive input data at rtip/rri ng is ignored while va lid transmit output data continues to be sent to the line. a simplified block diagram of digital loopback is shown in figure 21 . f igure 21. s implified b lock d iagram of d igital l oopback 3.1.4 dual loopback with dual loopback activated, the remote loopback is combined with the digital loopback. a simplified block diagram of dual loopback is shown in figure 22 . f igure 22. s implified b lock d iagram of d ual l oopback encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg encoder decoder timing control data and clock recovery ja ja tx rx taos nlc/prbs/qrss ttip tring rtip rring tclk tpos tneg rclk rpos rneg
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 29 3.2 84-channel t1/e1 multipl exer/mapper applications the xrt83sl314 has the capability of providing the necessary chip sele cts for multiple 14-channel liu devices. the liu is responsible fo r selecting itself, up to 5 additional liu devices, or all 6 devices simultaneously for permitting access to internal register s. the state of the chip select output pins is determined by a chip select decoder controlled by the 3 msbs of the address bus addr[10:8]. only one liu (master) requires the addr[10:8]. the other 5 liu devices use the 8 lsbs for the direct address bus addr[7:0]. figure 23 is a simplified block diagram of connecti ng six 14-channel liu devices for 84-channel applications. selection of the chip sele ct outputs using addr[10:8] is shown in ta b l e 7 . f igure 23. s implified b lock d iagram of an 84-c hannel a pplication t able 7: c hip s elect a ssignments addr[10:8] a ctive c hip s elect 0h (000) current device (master) 1h (001) chip 1 2h (010) chip 2 3h (011) chip 3 4h (100) chip 4 5h (101) chip 5 6h (110) reserved 7h (111) all devices active chip address a[10:8] address a[7:0] data [7:0] cs[4:0] cs cs cs cs cs 1 23456 master slave slave slave slave slave xrt83sl314 xrt83sl314 xrt83sl314 xrt83sl314 xrt83sl314 xrt83sl314
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 30 3.3 line card redundancy telecommunication system design requires signal integrity and reliability. when a t1/e1 prim ary line card has a failure, it must be swapped with a backup line card while maintaining connectivi ty to a backplane without losing data. system designers can achieve this by implementing common redundancy schemes with the xrt83sl314 liu. exar offers featur es that are tailored to redundancy app lications while reducing the number of components and providing system designers with solid reference designs. rlos and dmo if an rlos or dmo condition occurs, the xrt83sl314 repor ts the alarm to the individual status registers on a per channel basis. however, for redundancy applicatio ns, an rlos or dmo alarm can be used to initiate an automatic switch to the back up card. for this application, two global pins rlos and dmo are used to indicate that one of the 14-channels has an rlos or dmo condition. typical redundancy schemes ? 1:1 one backup card for every primary card (facility protection) ? 1+1 one backup card for every primary card (line protection) ? n+1 one backup card for n primary cards 3.3.1 1:1 and 1+1 redundancy without relays the 1:1 facility protection and 1+1 lin e protection have one backup card fo r every primary card. when using 1:1 or 1+1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. this eliminates the need for external relays and provides one bill of materials for all interface m odes of operation. for 1+1 line protection, the receiver in puts on the backup card have the ab ility to monitor the line for bit errors while in high impedance. the transmit and receive se ctions of the liu device are described separately. 3.3.2 transmit interface with 1:1 and 1+1 redundancy the transmitters on the backup card should be tri-stated. select the appropriate impedance for the desired mode of operation, t1/e1/j1. a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 24 . for a simplified block diagram of the transmit section for a 1:1 and 1+1 redundancy. f igure 24. s implified b lock d iagram of the t ransmit i nterface for 1:1 and 1+1 r edundancy 3.3.3 receive interface with 1:1 and 1+1 redundancy the receivers on the backup card should be programmed for "high" impedance. since there is no external resistor in the circuit, the receiver s on the backup card will not load down the line interface. this key design feature eliminat es the need for relays a nd provides one bill of materials fo r all interface mo des of operation. select the impedance for the desired mode of operation, t1/e1/j1. to swap the primary card, set the backup card to internal impedance, then the primary card to "high" impedance. see figure 25 . for a simplified block diagram of the receive section for a 1:1 redundancy scheme. t1/e1 line backplane interface primary card backup card xrt83sl314 tx tx 0.68uf 0.68uf internal impedence 1:2 1:2 xrt83sl314 internal impedence
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 31 f igure 25. s implified b lock d iagram of the r eceive i nterface for 1:1 and 1+1 r edundancy 3.3.4 n+1 redundancy using external relays n+1 redundancy has one backup card for n primar y cards. due to impedance mismatch and signal contention, external relays are necessary when using th is redundancy scheme. the relays create complete isolation between the primary cards and the backup card. this allows all transmit ters and receivers on the primary cards to be configured in in ternal impedance, providing one bill of material s for all interf ace modes of operation. the transmit and receive sections of the liu device are described separately. "high" impedence internal impedence backplane interface primary card backup card xrt83sl314 rx t1/e1 line rx 1:1 1:1 xrt83sl314
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 32 3.3.5 transmit interface with n+1 redundancy for n+1 redundancy, the transmitters on all cards should be programmed for internal impedance. the transmitters on the backup card do not have to be tri-stated. to swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. a 0.68uf capacitor is used in series with ttip for blocking dc bias. see figure 26 for a simplified block diagram of the transmit section for an n+1 redundancy scheme. f igure 26. s implified b lock d iagram of the t ransmit i nterface for n+1 r edundancy backplane interface primary card xrt83sl314 tx line interface card 0.68uf t1/e1 line 0.68uf primary card tx 0.68uf primary card tx 0.68uf backup card tx t1/e1 line t1/e1 line internal impedence 1:2 1:2 1:2 xrt83sl314 xrt83sl314 xrt83sl314 internal impedence internal impedence internal impedence
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 33 3.3.6 receive interface with n+1 redundancy for n+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. the receivers on the backup card should be programmed for "high" impedance mode. to swap the primary card, set the backup card to internal impedance, then the primary card to "high" impedance. see figure 27 for a simplified block diagram of the receive section for a n+1 redundancy scheme. f igure 27. s implified b lock d iagram of the r eceive i nterface for n+1 r edundancy backplane interface primary card xrt83sl314 rx line interface card primary card rx primary card rx backup card rx internal impedence t1/e1 line t1/e1 line t1/e1 line 1:1 1:1 1:1 xrt83sl314 xrt83sl314 xrt83sl314 internal impedence internal impedence "high" impedence
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 34 3.4 power failure protection for 1:1 or 1+1 line card redundancy in t1/e1 applicatio ns, power failure could cause a line card to change the characteristics of the line impedance, causing a degrad ation in system performance. the xrt83sl314 was designed to ensure reliability during power failures. the liu has patented high imp edance circuits that allow the receiver inputs and the transmitter outputs to be in "high" impedance when the liu experiences a power failure or when the liu is powered off. n ote : for power failure protection, a transformer must be used to c ouple to the line interface. see the tan-56 application note for more details. 3.5 overvoltage and overcurrent protection physical layer devices such as lius that interface to telecommunications lines are exposed to overvoltage transients posed by environmental threats. an overvolt age transient is a pulse of energy concentrated over a small period of time, usually under a few milliseconds. these pulses are random and exceed the operating conditions of cmos transceiver ics. electronic equi pment connecting to data lines are susceptible to many forms of overvoltage transients such as lightning, ac power faults and electrostati c discharge (esd). there are three important standards when designing a te lecommunications system to withstand overvoltage transients. ? ul1950 and fcc part 68 ? telcordia (bellcore) gr-1089 ? itu-t k.20, k.21 and k.41 n ote : for a reference design and performance, see the tan-54 application note for more details. 3.6 non-intrusive monitoring in non-intrusive monitoring applications, the transmitters are shut off by setting txon "low". the receivers must be actively receiving data wit hout interfering with the line impedance. the xrt83sl314?s internal termination ensures that the line termi nation meets t1/e1 specifications for 75 ?, 100 ? or 120 ? while monitoring the data stream. system integrity is maintained by placing the non-intrusive receiver in "high" impedance, equivalent to that of a 1+1 redundancy app lication. a simplified blo ck diagram of non-intrusive monitoring is shown in figure 28 . f igure 28. s implified b lock d iagram of a n on -i ntrusive m onitoring a pplication line card transceiver non-intrusive receiver node xrt83sl314 xrt83sl314 data traffic
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 35 4.0 transmit path line interface the transmit path of the xrt83sl314 liu consists of 14 independent t1/e1/j1 transmitters. the following section describes the complete trans mit path from tclk/tpos/tneg inputs to ttip/tring outputs. a simplified block diagram of the transmit path is shown in figure 29 . f igure 29. s implified b lock d iagram of the t ransmit p ath 4.1 tclk/tpos/tneg digital inputs in dual rail mode, tpos and tneg are the digital inputs for the transmit path. in single rail mode, tneg has no function and can be left unconnected. the xrt83sl314 can be programmed to sample the inputs on either edge of tclk. by default, data is sampled on the falling edge of tclk. to sample data on the rising edge of tclk, set tclke to "1" in the appropriate global register. figure 30 is a timing diagram of the transmit input data sampled on the falling edge of tclk. figure 31 is a timing diagram of the transmit input data sampled on the rising edge of tclk. the timing specifications are shown in table 8 . f igure 30. t ransmit d ata s ampled on f alling e dge of tclk f igure 31. t ransmit d ata s ampled on r ising e dge of tclk hdb3/b8zs encoder tx jitter attenuator timing control tx pulse shaper & pattern gen line driver ttip tring tclk tneg tpos tclk tpos or tneg tclk r tclk f t ho t su tclk tpos or tneg tclk f tclk r t ho t su
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 36 n ote : vdd=3.3v 5%, t a =25c, unless otherwise specified 4.2 hdb3/b8zs encoder in single rail mode, the liu can encode the tpos input signal to ami or hdb3/b8zs data. in e1 mode and hdb3 encoding selected, any sequence with four or more consecutive ze ros in the input w ill be replaced with 000v or b00v, where "b" indicates a pulse conforming to the bipolar rule and "v" representing a pulse violating the rule. an example of hdb3 encoding is shown in table 9 . in t1 mode and b8zs encoding selected, an input data sequence with eight or mo re consecutive zeros will be replaced using the b8zs encoding rule. an example with bipolar with 8 zero substitution is shown in ta b l e 10 . t able 8: t iming s pecifications for tclk/tpos/tneg p arameter s ymbol m in t yp m ax u nits tclk duty cycle t cdu 30 50 70 % transmit data setup time t su 50 - - ns transmit data hold time t ho 30 - - ns tclk rise time (10% to 90%) tclk r - - 40 ns tclk fall time (90% to 10%) tclk f - - 40 ns t able 9: e xamples of hdb3 e ncoding n umber of p ulses b efore n ext 4 z eros input 0000 hdb3 (case 1) odd 000v hdb3 (case 2) even b00v t able 10: e xamples of b8zs e ncoding c ase 1 p receding p ulse n ext 8 b its input + 00000000 b8zs 000vb0vb ami output + 000+-0-+ case 2 input - 00000000 b8zs 000vb0vb ami output - 000-+0+-
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 37 4.3 transmit jitter attenuator the xrt83sl314 liu is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. as the higher data rates are de-multiple xed down to t1 or e1 data, stuffing bits are typically removed which can leave gaps in th e incoming data stream. the transmit path has a dedicated jitter attenuator with a 32-bit or 64-bit fifo that is used to smooth the gapped clock into a steady t1 or e1 output. the maximum gap width of the 14-channel liu is shown in ta b l e 11 . n ote : if the liu is used in a lo op timing system, the receive pa th has a dedicated jitter attenuator. see the receive section of this datasheet. 4.4 taos (transmit all ones) the xrt83sl314 has the ability to transmit all ones on a per channel basis by pr ogramming the appropriate channel register. this function takes priority over th e digital data present on the tpos/tneg inputs. for example: if a fixed "0011" pattern is present on tpos in single rail mode and taos is enabled, the transmitter will output all ones. in addition, if di gital or dual loopback is selected, the data on the rpos output will be equal to the data on the tpos input. figure 32 is a diagram showing the all ones signal at ttip and tring. f igure 32. taos (t ransmit a ll o nes ) 4.5 transmit diagnostic features in addition to taos, the xrt83sl314 offers multiple diagnostic features for analyzing network integrity such as ataos, network loop code generation, and qrss on a per channel basis by programming the appropriate registers. these diagnos tic features take priority over th e digital data present on tpos/tneg inputs. the transmitters will send the diagnostic code to the line and will be maintained in the digital loopback if selected. when the liu is responsi ble for sending diagnostic patterns, the liu is automatically placed in the single rail mode. t able 11: m aximum g ap w idth for m ultiplexer /m apper a pplications fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui taos 111
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 38 4.5.1 ataos (automatic transmit all ones) if ataos is selected by programming the appropriate global register, an ami all ones signal will be transmitted for each channel that experiences an rlos condition. if rlos does not occur, the ataos will remain inactive until an rlos on a given channel occurs. a simplifie d block diagram of the atao s function is shown in figure 33 . f igure 33. s implified b lock d iagram of the ataos f unction 4.5.2 network loop up code by setting the liu to gener ate a nluc, the transmitters will send out a repeating "00001" pa ttern. the output waveform is shown in figure 34 . f igure 34. n etwork l oop u p c ode g eneration 4.5.3 network loop down code by setting the liu to generate a nldc, the transmitters will send ou t a repeating "001" pa ttern. the output waveform is shown in figure 35 . f igure 35. n etwork l oop d own c ode g eneration rlos ataos taos ttip tring tx network loop-up code 1 1 0 0 0 0 0 0001 network loop-down code 1111 0 000000
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 39 4.5.4 qrss generation the xrt83sl314 can transmit a qrss random sequence to a remote location from ttip/tring. the polynomial is shown in ta b l e 12 . 4.6 transmit pulse shaper and filter if tclk is not present, pulled "low", or pulled "high" the transmitter outputs at ttip/tring will automatically send an all ones or an all zero signal to the line by pr ogramming the appropriate global register. by default, the transmitters will send a ll zeros. to send all ones, the tclkcnl bit must be set "high". t able 12: r andom b it s equence p olynomials r andom p attern t1 e1 qrss 2 20 - 1 2 15 - 1
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 40 4.6.1 t1 short haul line build out (lbo) the short haul transmitter output pulses are generated usin g a 7-bit internal dac (6-bit plus the msb sign bit). the line build out can be set to interface to five di fferent ranges of cable attenuation by programming the appropriate channel register. the pulse shape is divided into eight discrete time segments which are set to fixed values to comply with the pulse template. to program the eight segments individually to optimize a special line build out, see the arbitrary pulse section of this datasheet. the short haul lbo settings are shown in table 13 . 4.6.2 arbitrary pulse generator for t1 and e1 the arbitrary pulse generator divides the pulse into eight individual segments. each segment is set by a 7-bit binary word by programming the appropriate channel regi ster. this allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build ou t. the msb (bit 7) is a sign-bit. if the sign-bit is set to "0", the segment will move in a positive direction relative to a flat lin e (zero) condition. if this sign-bit is set to "1", the segment will move in a n egative direction relative to a flat lin e condition. the resolution of the dac is typically 60mv per lsb. th us, writing 7-bit = 1111111 will clamp the output at either voltage rail corresponding to a maximum amplitude. a pulse with numbered segments is shown in figure 36 . f igure 36. a rbitrary p ulse s egment a ssignment n ote : by default, the arbitrary segments are programmed to 0x00h. the transmitter outputs will result in an all zero pattern to the line interface. 4.7 dmo (digital monitor output) the driver monitor circuit is used to detect transmit dr iver failures by monitoring t he activities at ttip/tring outputs. driver failure may be caused by a short circui t in the primary transformer or system problems at the transmit inputs. if the transmitter of a channel has no output for more than 128 clock cycles, dmo goes "high" until a valid transmit pulse is detected . if the dmo interrupt is enabled, t he change in status of dmo will cause t able 13: s hort h aul l ine b uild o ut lbo setting eqc[4:0] r ange of c able a ttenuation 08h (01000) 0 - 133 feet 09h (01001) 133 - 266 feet 0ah (01010) 266 - 399 feet 0bh (01011) 399 - 533 feet 0ch (01100) 533 - 655 feet 1 2 3 4 5 6 7 8 segment register 1 0xn8 2 0xn9 3 0xna 4 0xnb 5 0xnc 6 0xnd 7 0xne 8 0xnf
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 41 the interrupt pin to go "low". once th e status register is read , the interrupt pin will retu rn "high" and the status register will be reset (rur). 4.8 line termination (ttip/tring) the output stage of the transmit path generates standard return-to-zero (rz) signals to the line interface for t1/ e1/j1 twisted pair or e1 coaxial cable. the physica l interface is optimized by placing the terminating impedance inside the liu. this allows one bill of materials for all modes of operation re ducing the number of external components necessary in system design. the transmitter outputs only require one dc blocking capacitor of 0.68 f. for redundancy applications (or simply to tri- state the transmitters), set txtsel to a "1" in the appropriate channel register. a ty pical transmit interface is shown in figure 37 . f igure 37. t ypical c onnection d iagram u sing i nternal t ermination t tip t ring xrt83sl314 liu 1:2 internal impedance line interface t1/e1/j1 c=0.68uf one bill of materials transmitter output
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 42 5.0 microprocessor interface block the microprocessor interface section supports communi cation between the local microprocessor (p) and the liu. the xrt83sl314 supports an intel asynchronous interface, motorola 68k asynchronous, and a motorola power pc interface. the microprocessor interface is selected by the state of the pts[2:0] input pins. selecting the microprocessor interface is shown in ta b l e 14 . the xrt83sl314 uses multipurpose pins to configure the device appropriately. the local p configures the liu by writing data into specific addressable, on-chip read/write registers. the microprocessor interface provides the signals which are required for a general purpose microprocessor to read or write data into these registers. the microprocessor interface also supports polled and interrupt driven environments. a simplified block diagram of the microprocessor is shown in figure 38 . t able 14: s electing the m icroprocessor i nterface m ode pts[2:0] m icroprocessor m ode 0h (000) intel 68hc11, 8051, 80c188 (asynchronous) 1h (001) motorola 68k (asynchronous) 7h (111) motorola mpc8260, mpc860 power pc (synchronous) f igure 38. s implified b lock d iagram of the m icroprocessor i nterface b lock microprocessor interface wr_r/w rd_we ale ptype [2:0] rdy_ta reset pclk cs int addr[10:0] data[7:0] cs5 cs4 cs3 cs2 cs1
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 43 5.1 the microprocessor interface block signals the liu may be configured into different operating mo des and have its performance monitored by software through a standard microprocessor using data, address and control signals. these interface signals are described below in ta b l e 15 , ta b l e 16 , and ta b l e 17 . the microprocessor interface can be configured to operate in intel mode or motorola mode. when the microprocessor interface is operating in intel mode, some of the control signals function in a manner required by the intel 80xx family of microprocessors. likewise, when the microprocessor interface is operating in motorola m ode, then these control signals function in a manner as required by the motorola power pc family of microprocessors. (for using a motorola 68k asynchronous processor, see figure 41 and ta b l e 20 ) ta b l e 15 lists and describes those microprocessor interface signals whose role is constant across the two modes. ta b l e 16 describes the role of some of these signals when the microprocessor interface is operating in the intel mode. likewise, ta b l e 17 describes the role of these signals when the microprocessor interface is operating in the motorola power pc mode. t able 15: xrt84l314 m icroprocessor i nterface s ignals that exhibit constant roles in both i ntel and m otorola m odes p in n ame t ype d escription pts[2:0] i microprocessor interface mode select input pins these three pins are used to specify the micr oprocessor interface mode. the relationship between the state of these thre e input pins, and the corresponding microprocessor mode is presented in table 14 . data[7:0] i/o bi-directional data bus for register "read" or "write" operations. addr[10:8] i three-bit addr ess bus inputs the 3 msbs of the address bits are used as a ch ip select decoder. the state of these 3 pins enable the chip selects for additional liu devices. n ote : see the 84-channel application section of this datasheet. addr[7:0] i eight-bit address bus inputs the xrt83sl314 liu microprocessor interface uses a direct address bus. this address bus is provided to permit the user to select an on-chip register for read/write access. cs i chip select input this active low signal selects the microprocessor interface of the xrt83sl314 liu and enables read/write operations with the on-chip register locations. t able 16: i ntel mode : m icroprocessor i nterface s ignals xrt83sl314 p in n ame i ntel e quivalent p in t ype d escription ale_ts ale i address-latch enable: this active high signal is used to latch the contents on the address bus addr[7:0]. the contents of the address bus are latched into the addr[7:0] inputs on the falling edge of ale. rd _ we rd i read signal: this active low input functions as the read signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a read oper - ation has been requested and begins the process of the read cycle. wr _r/ w wr i write signal: this active low input functions as the write signal from the local p. when this pin is pulled ?low? (if cs is ?low?) the liu is informed that a write operation has been requested and begi ns the process of the write cycle. rdy _ ta rdy o ready output: this active low signal is provided by the liu device. it indicates that the current read or write cycle is co mplete, and the liu is waiting for the next command.
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 44 t able 17: m otorola m ode : m icroprocessor i nterface s ignals xrt83sl314 p in n ame m otorola e quivalent p in t ype d escription ale_ts ts i transfer start: this active high signal is used to latch the contents on the address bus addr[7:0]. the contents of the address bus are latched into the addr[7:0] inputs on the falling edge of ts. wr _r/ w r/ w i read/write: this input pin from the local p is used to inform the liu whether a read or write operation has been requested. when this pin is pulled ?high?, we will initiate a read operation. when this pin is pulled ?low?, we will initiate a write operation. rd _ we we i write enable: this active low input functions as the read or write signal from the local p dependent on the state of r/ w . when we is pulled ?low? (if cs is ?low?) the liu begins the read or write operation. no pin oe i output enable: this signal is not necessary for the xrt83sl314 to interface to the mpc8260 or mpc860 power pcs. pclk clkout i synchronous processor clock: this signal is used as the timing reference for the power pc synchronous mode. rdy _ ta ta o transfer acknowledge: this active low signal is provided by the liu device. it indicates that the cu rrent read or write cycle is co mplete, and the liu is waiting for the next command.
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 45 5.2 intel mode programmed i/o access (asynchronous) if the liu is interfaced to an intel type p, then it should be configured to operate in the intel mode. intel type read and write operations are described below. intel mode read cycle whenever an intel-type p wishes to read the contents of a register, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[10:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproces - sor interface block of the liu. 4. the p should then toggle the ale pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. next, the p should indicate that this current bus cycle is a read operation by toggling the rd input pin "low". this action also enables the bi-direc tional data bus output drivers of the liu. 6. after the p toggles the read signal "low", the liu will toggle the rdy output pin "low". the liu does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next com - mand. 7. after the p detects the rdy signal and has read the data, it can terminate the read cycle by toggling the rd input pin "high". n ote : ale can be tied ?high? if this signal is not available. the intel mode write cycle whenever an intel type p wishes to write a byte or word of data into a register within the liu, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[10:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. toggle the ale input pin "high". this step enables the address bus input drivers, within the microproces - sor interface block of the liu. 4. the p should then toggle the ale pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 5. the p should then place the byte or word that it in tends to write into the target register, on the bi-direc - tional data bus data[7:0]. 6. next, the p should indicate th at this current bus cycle is a write operation by toggling the wr input pin "low". this action also enables the bi-direc tional data bus input drivers of the liu. 7. after the p toggles the write sign al "low", the liu will toggle the rdy output pin "low". the liu does this in order to inform the p that the data has been written into the internal register location, and that it is ready for the next command. n ote : ale can be tied ?high? if this signal is not available. the intel read and write timing diagram is shown in figure 39. the timing specif ications are shown in ta b l e 18 .
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 46 f igure 39. i ntel p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 18: i ntel m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to rd assert 30 - ns t 2 rd assert to rdy assert - 150 ns na rd pulse width (t 2 ) 150 - ns t 3 cs falling edge to wr assert 30 - ns t 4 wr assert to rdy assert - 150 ns na wr pulse width (t 4 ) 150 - ns cs addr[10:0] ale = 1 data[7:0] rd wr rdy valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 4 t 2 t 3 valid address valid address
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 47 5.3 motorola mode programmed i/o access (synchronous) if the liu is interfaced to a motorola type p, it should be configured to operate in the motorola mode. motorola type programmed i/o read and write operations are described below. motorola mode read cycle whenever a motorola type p wishes to read the contents of a register, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[10:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. the p should then toggle the ts pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate that this current bus cycle is a read operation by pulling the r/ w input pin "high". 5. toggle the we input pin "low". this action enables the bi-d irectional data bus output drivers of the liu. 6. after the p toggles the we signal "low", the liu will toggle the ta output pin "low". the liu does this in order to inform the p that the data is available to be read by the p, and that it is ready for the next com - mand. 7. after the p detects the ta signal and has read the data, it can terminate the read cycle by toggling the we input pin "high". motorola mode write cycle whenever a motorola type p wishes to write a byte or word of data into a register within the liu, it should do the following. 1. place the address of the targ et register on the addre ss bus input pins addr[10:0]. 2. while the p is placing this address value on the address bus, the address decoding circuitry should assert the cs pin of the liu, by toggling it "low". this action enables further communication between the p and the liu microprocessor interface block. 3. the p should then toggle the ts pin "low". this step causes the liu to latch the contents of the address bus into its internal circuitry. at this point, the address of the register has now been selected. 4. next, the p should indicate that this current bus cycle is a write operation by pulling the r/ w input pin "low". 5. toggle the we input pin "low". this action enables the bi-d irectional data bus output drivers of the liu. 6. after the p toggles the we signal "low", the liu will toggle the ta output pin "low". the liu does this in order to inform the p that the data has been written into the internal register location, and that it is ready for the next command. 7. after the p detects the ta signal and has read the data, it can terminate the read cycle by toggling the we input pin "high". the motorola read and write timing diagram is shown in figure 40. the timing specifications are shown in ta b l e 19 .
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 48 f igure 40. m otorola p ower pc p i nterface s ignals d uring p rogrammed i/o r ead and w rite o pera - tions t able 19: m otorola p ower pc m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to we assert 0 - ns t 2 we assert to ta assert - 150 ns na we pulse width (t 2 ) 150 - ns t 3 cs falling edge to ts falling edge 0 - ns t dc pclk duty cycle 40 60 % t cp pclk clock period 20 - ns cs addr[10:0] data[7:0] we r/w ta valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 valid address valid address t 3 t 3 t 1 t 2 ts upclk t cp t dc
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 49 f igure 41. m otorola 68k p i nterface s ignals d uring p rogrammed i/o r ead and w rite o perations t able 20: m otorola 68k m icroprocessor i nterface t iming s pecifications s ymbol p arameter m in m ax u nits t 0 valid address to cs falling edge 0 - ns t 1 cs falling edge to ds (pin rd _ we ) assert 30 - ns t 2 ds assert to dtack assert - 150 ns na ds pulse width (t 2 ) 150 - ns t 3 cs falling edge to as (pin ale_ts) falling edge 0 - ns cs addr[10:0] ale _ts data[7:0] rd _we wr _r/w rdy _dtack valid data for readback data available to write into the liu read operation write operation t 0 t 0 t 1 t 2 motorola asychronous mode valid address valid address t 3 t 3 t 1 t 2
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 50 t able 21: m icroprocessor r egister a ddress (addr[7:0]) r egister n umber a ddress (h ex ) f unction 0 - 15 0x00 - 0x0f channel 0 control registers 16 - 31 0x10 - 0x1f channel 1 control registers 32 - 47 0x20 - 0x2f channel 2 control registers 48 - 63 0x30 - 0x3f channel 3 control registers 64 - 79 0x40 - 0x4f channel 4 control registers 80 - 95 0x50 - 0x5f channel 5 control registers 96 - 111 0x60 - 0x6f channel 6 control registers 112 - 127 0x70 - 0x7f channel 7 control registers 128 - 143 0x80 - 0x8f channel 8 control registers 144 - 159 0x90 - 0x9f channel 9 control registers 160 - 175 0xa0 - 0xaf channel 10 control registers 176 - 191 0xb0 - 0xbf channel 11 control registers 192 - 207 0xc0 - 0xcf channel 12 control registers 208 - 223 0xd0 - 0xdf channel 13 control registers 224 - 227 0xe0 - 0xeb global control registers applied to all 14 channels 228 - 243 0xec - 0xf3 r/w registers reserved for testing 244 0xf4 e1 arbitrary select 245 - 253 0xf5 - 0xfd r/w registers reserved for testing 254 0xfe device "id" 255 0xff device "revision id" t able 22: m icroprocessor r egister c hannel d escription r eg addr t ype d7 d6 d5 d4 d3 d2 d1 d0 channel 0 control registers (0x00 - 0x0f) 0 0x00 r/w qrss/prbs reserved rxon eqc4 eqc3 eqc2 eqc1 eqc0 1 0x01 r/w rxtsel txtsel tersel1 tersel0 rxjasel txjasel jabw fifos 2 0x02 r/w invqrss txtest2 txtest1 txtest0 txon loop2 loop1 loop0 3 0x03 r/w nlcde1 nlcde0 codes rxres1 rxres0 insbpv insber reserved 4 0x04 r/w eqflage dmoie flsie lcvi/ofe nlcdie aisdie rlosie qrpdie 5 0x05 ro eqflag dmo fls lcv/of nlcd ais rlos qrpd 6 0x06 rur eqflags dmois flsis lcv/ofis nlcdis aisis rlosis qrpdis
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 51 7 0x07 ro reserved flsdet clos5 clos4 clos3 clos2 clos1 clos0 8 0x08 r/w reserved 1seg6 1seg5 1seg4 1seg3 1seg2 1seg1 1seg0 9 0x09 r/w reserved 2seg6 2seg5 2seg4 2seg3 2seg2 2seg1 2seg0 10 0x0a r/w reserved 3seg6 3seg5 3seg4 3seg3 3seg2 3seg1 3seg0 11 0x0b r/w reserved 4seg6 4seg5 4seg4 4seg3 4seg2 4seg1 4seg0 12 0x0c r/w reserved 5seg6 5seg5 5seg4 5seg3 5seg2 5seg1 5seg0 13 0x0d r/w reserved 6seg6 6seg5 6seg4 6seg3 6seg2 6seg1 6seg0 14 0x0e r/w reserved 7seg6 7seg5 7seg4 7seg3 7seg2 7seg1 7seg0 15 0x0f r/w reserved 8seg6 8seg5 8seg4 8seg3 8seg2 8seg1 8seg0 channel (1 - 13) control registers (0xn0 - 0xnf) see channel 0 t able 23: m icroprocessor r egister g lobal d escription r eg addr t ype d7 d6 d5 d4 d3 d2 d1 d0 global control registers for all 14 channels 224 0xe0 r/w sr/dr ataos rclke tclke datap reserved gie sreset 225 0xe1 r/w reserved reserved gauge1 gauge0 reserved rxmute exlos ict 226 0xe2 r/w reserved rxtcntl eqflag5 eqflag4 eqflag3 eqflag2 eqflag1 eqflag0 227 0xe3 r/w reserved reserved reserved reserved sl1 sl0 eqg1 eqg0 228 0xe4 r/w mclkt1out1 mclkt1out0 mclke1out1 mclke1out0 reserved reserved reserved reserved 229 0xe5 r/w lcv/oflw cntrden reserved reserved lcvch3 lcvch2 lcvch1 lcvch0 230 0xe6 r/w reserved reserved reserved allrst allupdate bytesel chupdate chrst 231 0xe7 r/w reserved reserved reserved reserved reserved reserved reserved reserved 232 0xe8 ro lcvcnt7 lcvcnt6 lcvcnt5 lcvcnt4 lcvcnt3 lcvcnt2 lcvcnt1 lcvcnt0 233 0xe9 r/w reserved reserved allt1e1 tclkcnl clksel3 clksel2 clksel1 clksel0 234 0xea rur gchis7 gchis6 gchis5 gchis4 gchis3 gchis2 gchis1 gchis0 235 0xeb rur reserved reserved gchis13 gchis12 gchis11 gchis10 gchis9 gchis8 244 0xf4 r/w reserved reserved reserved reserved reserved reserved reserved e1arben r/w registers reserved for testing (0xec - 0xfd), excluding 0xf4h 254 0xfe ro device "id" 255 0xff ro device "revision id" t able 22: m icroprocessor r egister c hannel d escription r eg addr t ype d7 d6 d5 d4 d3 d2 d1 d0
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 52 t able 24: m icroprocessor r egister 0 x 00 h b it d escription c hannel 0-13 (0 x 00 h -0 x d0 h ) b it n ame f unction register type default value (hw reset) d7 qrss/ prbs qrss/prbs select bits these bits are used to select between qrss and prbs. 0 = qrss 1 = prbs r/w 0 d6 reserved this register bit is not used. d5 rxon receiver on/off upon power up, the receiver is powered off. rxon is used to turn the receiver on or off if the hardware pin rxon is pulled "high". if the hardware pin is pulled "low", all receivers are turned off. 0 = receiver is powered off 1 = receiver is powered on r/w 0 d4 d3 d2 d1 d0 eqc4 eqc3 eqc2 eqc1 eqc0 equalizer control bits the equalizer control bits are shown in table 25 below. r/w 0 0 0 0 0 t able 25: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1/e1 m ode /r eceive s ensitivity t ransmit lbo c able c oding 0x08h t1 short haul/15db 0 to 133 feet (0.6db) 100 ? tp b8zs 0x09h t1 short haul/15db 133 to 266 feet (1.2db) 100 ? tp b8zs 0x0ah t1 short haul/15db 266 to 399 feet (1.8db) 100 ? tp b8zs 0x0bh t1 short haul/15db 399 to 533 feet (2.4db) 100 ? tp b8zs 0x0ch t1 short haul/15db 533 to 655 feet (3.0db) 100 ? tp b8zs 0x0dh t1 short haul/15db arbitrary pulse 100 ? tp b8zs 0x0eh t1 gain mode/29db 0 to 133 feet (0.6db) 100 ? tp b8zs 0x0fh t1 gain mode/29db 133 to 266 feet (1.2db) 100 ? tp b8zs 0x10h t1 gain mode/29db 266 to 399 feet (1.8db) 100 ? tp b8zs 0x11h t1 gain mode/29db 399 to 533 feet (2.4db) 100 ? tp b8zs 0x12h t1 gain mode/29db 533 to 655 feet (3.0db) 100 ? tp b8zs 0x13h t1 gain mode/29db arbitrary pulse 100 ? tp b8zs 0x1ch e1 short haul/15db itu g.703 75 ? coax hdb3
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 53 0x1dh e1 short haul/15db itu g.703 120 ? tp hdb3 0x1eh e1 gain mode/29db itu g.703 75 ? coax hdb3 0x1fh e1 gain mode/29db itu g.703 120 ? tp hdb3 t able 26: m icroprocessor r egister 0 x 01 h b it d escription c hannel 0-13 (0 x 01 h -0 x d1 h ) b it n ame f unction register type default value (hw reset) d7 rxtsel receive termination select upon power up, the receiver is in "high" impedance. rxtsel is used to switch between the internal termination and "high" imped - ance. 0 = "high" impedance 1 = internal termination r/w 0 d6 txtsel transmit termination select upon power up, the transmitter is in "high" impedance. txtsel is used to switch between the internal termination and "high" imped - ance. 0 = "high" impedance 1 = internal termination r/w 0 d5 d4 tersel1 tersel0 receive line impedance select tersel[1:0] are used to select the line impedance for t1/j1/e1. 00 = 100 ? 01 = 110 ? 10 = 75 ? 11 = 120 ? r/w 0 0 d3 rxjasel receive jitter attenuator select rxjasel is used to enable the re ceiver jitter attenuator. by default, rxjasel is disabled. 0 = disabled 1 = enabled r/w 0 d2 txjasel transmit jitter attenuator select txjasel is used to enable the trans mitter jitter attenuator. by default, txjasel is disabled. 0 = disabled 1 = enabled r/w 0 t able 25: e qualizer c ontrol and t ransmit l ine b uild o ut eqc[4:0] t1/e1 m ode /r eceive s ensitivity t ransmit lbo c able c oding
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 54 d1 jabw jitter bandwidth (e1 mode only, t1 is permanently set to 3hz) the jitter bandwidth is a global setting that is applied to both the receiver and transmitter jitter attenuator. 0 = 10hz 1 = 1.5hz r/w 0 d0 fifos fifo depth select the fifo depth select is used to configure the part for a 32-bit or 64-bit fifo (within the jitter atte nuator blocks). the delay of the fifo is equal to ? the fifo depth. this is a global setting that is applied to both the receiver and transmitter fifo. 0 = 32-bit 1 = 64-bit r/w 0 t able 27: m icroprocessor r egister 0 x 02 h b it d escription c hannel 0-13 (0 x 02 h -0 x d2 h ) b it n ame f unction register type default value (hw reset) d7 invqrss qrss inversion invqrss is used to invert the transmit qrss pattern set by the txtest[2:0] bits. by default, invqrss is disabled and the qrss will be transmitted with normal polarity. 0 = disabled 1 = enabled r/w 0 d6 d5 d4 txtest2 txtest1 txtest0 test code pattern txtest[2:0] are used to select a diagnostic test pattern to the line (transmit outputs). 0xx = no pattern 100 = tx qrss 101 = tx taos 110 = tx tluc 111 = tx tldc r/w 0 0 0 t able 26: m icroprocessor r egister 0 x 01 h b it d escription c hannel 0-13 (0 x 01 h -0 x d1 h ) b it n ame f unction register type default value (hw reset)
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 55 d3 txon transmit on/off upon power up, the transmitters are powered off. this bit is used to turn the transmitter for this channel on or off if the txon pin is pulled "high". if the txon pin is pulled "low", all 14 transmitters are powered off. 0 = transmitter is powered off 1 = transmitter is powered on r/w 0 d2 d1 d0 loop2 loop1 loop0 loopback diagnostic select loop[2:0] are used to select the loopback mode. 0xx = no loopback 100 = dual loopback 101 = analog loopback 110 = remote loopback 111 = digital loopback r/w 0 0 0 t able 28: m icroprocessor r egister 0 x 03 h b it d escription c hannel 0-13 (0 x 03 h -0 x d3 h ) b it n ame f unction register type default value (hw reset) d7 d6 nlcde1 nlcde0 network loop code detection enable nlcde[1:0] are used to select the loop code detection. 00 = disabled 01 = detect loop up code 10 = detect loop down code 11 = automatic loop code detection r/w 0 0 d5 codes encoding/decoding select (single rail mode only) 0 = hdb3 (e1), b8zs (t1) 1 = ami coding r/w 0 d4 d3 rxres1 rxres0 receive external fixed resistor rxres[1:0] are used to select the value for a high precision exter - nal resistor to improve return loss. 00 = none 01 = 240 ? 10 = 210 ? 11 = 150 ? r/w 0 0 t able 27: m icroprocessor r egister 0 x 02 h b it d escription c hannel 0-13 (0 x 02 h -0 x d2 h ) b it n ame f unction register type default value (hw reset)
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 56 d2 insbpv insert bipolar violation when this bit transitions from a "0" to a "1", a bipolar violation will be inserted in the transmitted qrss/prbs pattern. the state of this bit will be sampled on the rising edge of tclk. to ensure proper operation, it is recommended to write a "0" to this bit before writing a "1". r/w 0 d1 insber insert bit error when this bit transitions from a "0" to a "1", a bit error will be inserted in the transmitted qrss/pr bs pattern. the state of this bit will be sampled on the rising edge of tclk. to ensure proper operation, it is recommended to writ e a "0" to this bit before writing a "1". r/w 0 d0 reserved this register bit is not used. t able 29: m icroprocessor r egister 0 x 04 h b it d escription c hannel 0-13 (0 x 04 h -0 x d4 h ) b it n ame f unction register type default value (hw reset) d7 eqflage equalizer attenuation flag enable 0 = masks the eqflag function 1 = enables interrupt generation r/w 0 d6 dmoie digital monitor output interrupt enable 0 = masks the dmo function 1 = enables interrupt generation r/w 0 d5 flsie fifo limit status interrupt enable 0 = masks the fls function 1 = enables interrupt generation r/w 0 d4 lcv/ofie line code violation / counter overflow interrupt enable 0 = masks the lcv/of function 1 = enables interrupt generation r/w 0 d3 nlcdie network loop code detection interrupt enable 0 = masks the nlcd function 1 = enables interrupt generation r/w 0 d2 aisie alarm indication signal interrupt enable 0 = masks the ais function 1 = enables interrupt generation r/w 0 t able 28: m icroprocessor r egister 0 x 03 h b it d escription c hannel 0-13 (0 x 03 h -0 x d3 h ) b it n ame f unction register type default value (hw reset)
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 57 d1 rlosie receiver loss of signal interrupt enable 0 = masks the rlos function 1 = enables interrupt generation r/w 0 d0 qrpdie quasi random signal source interrupt enable 0 = masks the qrpd function 1 = enables interrupt generation r/w 0 n ote : the gie bit in the global register 0xe0h must be set to "1" in addition to the individual register bits to enable the interrupt pin. t able 30: m icroprocessor r egister 0 x 05 h b it d escription c hannel 0-13 (0 x 05 h -0 x d5 h ) b it n ame f unction register type default value (hw reset) d7 eqflag equalizer attenuation flag the equalizer attenuation flag is always active regardless if the interrupt generation is disabled. this bit indicates the eqflag activity. an interrupt will not occur unless the eqflage is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = equalizer attenuation flag is set ro 0 d6 dmo digital monitor output the digital monitor output is always active regardless if the inter - rupt generation is disabled. this bit indicates the dmo activity. an interrupt will not occur unless the dmoie is set to "1" in the chan - nel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = transmit output driver has failures ro 0 d5 fls fifo limit status the fifo limit status is always active regardless if the interrupt generation is disabled. this bit indicates whether the rd/wr pointers are within 3-bits. an interrupt will not occur unless the flsie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = rd/wr fifo pointers are within 3-bits ro 0 t able 29: m icroprocessor r egister 0 x 04 h b it d escription c hannel 0-13 (0 x 04 h -0 x d4 h ) b it n ame f unction register type default value (hw reset)
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 58 d4 lcv/of line code violation / counter overflow this bit serves a dual purpose. by default, this bit monitors the line code violation activity. however, if bit 7 in register 0xe5h is set to a "1", this bit monitors the overflow status of the internal lcv counter. an interrupt will not occur unless the lcv/ofie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = a line code violation, bipolar violation, or excessive zeros has occurred ro 0 d3 nlcd network loop code detection the network loop code detection is always active regardless if the interrupt generation is disabled. this bit indicates the nlcd activ - ity. an interrupt will not occur unless the nlcdie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = network loop code detected according to the mode selected in channel register 0x03h ro 0 d2 aisd alarm indication signal the alarm indication signal detection is always active regardless if the interrupt generation is disabled. this bit indicates the ais activity. an interrupt will not occur unless the aisie is set to "1" in the channel register 0x04h and gie is set to "1" in the global regis - ter 0xe0h. 0 = no alarm 1 = an all ones signal is detected ro 0 d1 rlos receiver loss of signal the receiver loss of signal detection is always active regardless if the interrupt generation is disabled. this bit indicates the rlos activity. an interrupt will not occur unless the rlosie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = an rlos condition is present ro 0 d0 qrpd quasi random pattern detection the quasi random pattern detection is always active regardless if the interrupt generation is disabled. this bit indicates that a qrpd has been detected. an interrupt will not occur unless the qrpdie is set to "1" in the channel register 0x04h and gie is set to "1" in the global register 0xe0h. 0 = no alarm 1 = a qrp is detected ro 0 n ote : the gie bit in the global register 0xe0h must be set to "1" in addition to the individual register bits to enable the interrupt pin. t able 30: m icroprocessor r egister 0 x 05 h b it d escription c hannel 0-13 (0 x 05 h -0 x d5 h ) b it n ame f unction register type default value (hw reset)
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 59 n ote : any change in status will generate an interrupt (if enabled in channel register 0x04h and gie is set to "1" in the global register 0xe0h). the status registers are reset upon read (rur). t able 31: m icroprocessor r egister 0 x 06 h b it d escription c hannel 0-13 (0 x 06 h -0 x d6 h ) b it n ame f unction register type default value (hw reset) d7 eqflags equalizer attenuation flag status 0 = no change 1 = change in status occurred rur 0 d6 dmois digital monitor output status 0 = no change 1 = change in status occurred rur 0 d5 flsis fifo limit status 0 = no change 1 = change in status occurred rur 0 d4 lcv/ofis line code violation / overflow status 0 = no change 1 = change in status occurred rur 0 d3 nlcdis network loop code detection status 0 = no change 1 = change in status occurred rur 0 d2 aisdis alarm indication signal status 0 = no change 1 = change in status occurred rur 0 d1 rlosis receiver loss of signal status 0 = no change 1 = change in status occurred rur 0 d0 qrpdis quasi random pattern detection status 0 = no change 1 = change in status occurred rur 0
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 60 t able 32: m icroprocessor r egister 0 x 07 h b it d escription c hannel 0-13 (0 x 07 h -0 x d7 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used. d6 flsdet fifo limit status detect the flsdet is used to determine whether the receiver or trans - mitter fifo has reached its limit status. if both fifos reach their limit capacity, this bit will be set to "1". 0 = receive ja 1 = transmit ja ro 0 d5 d4 d3 d2 d1 d0 clos5 clos4 clos3 clos2 clos1 clos0 cable loss indication this 6-bit binary word indicates the cable attenuation on the receiver inputs rtip/rring within 1db with bit 5 being the msb. ro 0 t able 33: m icroprocessor r egister 0 x 08 h b it d escription c hannel 0-13 (0 x 08 h -0 x d8 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d6 d5 d4 d3 d2 d1 d0 1seg6 1seg5 1seg4 1seg3 1seg2 1seg1 1seg0 arbitrary pulse generation the transmit output pulse is divided into 8 individual segments. this register is used to program the first segment which corre - sponds to the overshoot of the pulse amplitude. there are four segments for the top portion of the pulse and four segments for the bottom portion of the pulse. segment number 5 corresponds to the undershoot of the pulse. the msb of each segment is the sign bit. bit 6 = 0 = negative direction bit 6 = 1 = positive direction r/w 0 0 0 0 0 0 0
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 61 t able 34: m icroprocessor r egister 0 x 09 h b it d escription c hannel 0-13 (0 x 09 h -0 x d9 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 2seg[6:0] segment number two, same description as register 0x08h r/w t able 35: m icroprocessor r egister 0 x 0a h b it d escription c hannel 0-13 (0 x 0a h -0 x da h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 3seg[6:0] segment number three, same description as register 0x08h r/w t able 36: m icroprocessor r egister 0 x 0b h b it d escription c hannel 0-13 (0 x 0b h -0 x db h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 4seg[6:0] segment number four, same description as register 0x08h r/w t able 37: m icroprocessor r egister 0 x 0c h b it d escription c hannel 0-13 (0 x 0c h -0 x dc h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 5seg[6:0] segment number five, same description as register 0x08h r/w
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 62 t able 38: m icroprocessor r egister 0 x 0d h b it d escription c hannel 0-13 (0 x 0d h -0 x dd h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 6seg[6:0] segment number six, same description as register 0x08h r/w t able 39: m icroprocessor r egister 0 x 0e h b it d escription c hannel 0-13 (0 x 0e h -0 x de h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 7seg[6:0] segment number seven, same description as register 0x08h r/w t able 40: m icroprocessor r egister 0 x 0f h b it d escription c hannel 0-13 (0 x 0f h -0 x df h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used x 0 d[6:0] 8seg[6:0] segment number eight, same description as register 0x08h r/w
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 63 t able 41: m icroprocessor r egister 0 x e0 h b it d escription g lobal r egister (0 x e0 h ) b it n ame f unction register type default value (hw reset) d7 sr/dr single rail/dual rail mode this bit sets the liu to receive and transmit digital data in a single rail or a dual rail format. 0 = dual rail mode 1 = single rail mode r/w 0 d6 ataos automatic transmit all ones if ataos is selected, an all ones pattern will be transmitted on any channel that experiences an rlos condition. if an rlos condi - tion does not occur, taos will remain inactive. 0 = disabled 1 = enabled r/w 0 d5 rclke receive clock data 0 = rpos/rneg data is updated on the rising edge of rclk 1 = rpos/rneg data is updated on the falling edge of rclk r/w 0 d4 tclke transmit clock data 0 = tpos/tneg data is sampled on the falling edge of tclk 1 = tpos/tneg data is sampled on the rising edge of tclk r/w 0 d3 datap data polarity 0 = transmit input and receive output data is active "high" 1 = transmit input and receive output data is active "low" r/w 0 d2 reserved this register bit is not used r/w 0 d1 gie global interrupt enable the global interrupt enable is used to enable/disable all interrupt activity for all 14 channels. this bit must be set "high" for the inter - rupt pin to operate. 0 = disable all interrupt generation 1 = enable interrupt generation to the individual channel registers r/w 0 d0 sreset software reset writing a "1" to this bit for more than 10s initiates a device reset for all internal circuits except the microprocessor register bits. to reset the registers to their default setting, use the hardware reset pin (see the pin description for more details). r/w 0
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 64 t able 42: m icroprocessor r egister 0 x e1 h b it d escription t able 43: m icroprocessor r egister 0 x e2 h b it d escription g lobal r egister (0 x e1 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0 d6 reserved this register bit is not used r/w 0 d5 d4 gauge1 gauge0 wire gauge select 00 = 22 and 24 gauge 01 = 22 gauge 10 = 24 gauge 11 = 26 gauge r/w 0 0 d3 reserved this register bit is not used r/w 0 d2 rxmute receiver output mute enable if rxmute is selected, rpos/rneg will be pulled "low" for any channel that experiences an rlos condition. if an rlos condi - tion does not occur, rxmute will remain inactive. 0 = disabled 1 = enabled r/w 0 d1 exlos extended loss of zeros the number of zeros required to declare a digital loss of signal is extended to 4,096. 0 = normal operation 1 = enables the exlos function r/w 0 d0 ict in circuit testing 0 = normal operation 1 = sets all output pins to "high" impedance for in circuit testing r/w 0 g lobal r egister (0 x e2 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 65 t able 44: m icroprocessor r egister 0 x e3 h b it d escription d6 rxtcntl receive termination select control this bit sets the liu to control th e rxtsel function with either the individual channel register bit or the global hardware pin. 0 = control of the receive termination is set to the register bits 1 = control of the receive termination is set to the hardware pin r/w 0 d5 d4 d3 d2 d1 d0 eqflag5 eqflag4 eqflag3 eqflag2 eqflag1 eqflag0 equalizer attenuation flag eqflag[5:0] is used to generate an interrupt condition for an rlos other than the default setting described in the datasheet. a desired value can be programmed in to this register. if eqflage is enabled in register 0x04h and if th is 6-bit binary word is equal to the 6-bit cable loss indicator, an interrupt will be generated. r/w 0 0 0 0 0 0 g lobal r egister (0 x e3 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0 d6 reserved this register bit is not used r/w 0 d5 reserved this register bit is not used r/w 0 d4 reserved this register bit is not used r/w 0 d3 d2 sl1 sl0 slicer level select 00 = 50% 01 = 45% 10 = 55% 11 = 68% r/w 0 0 d1 d0 eqg1 eqg0 equalizer gain control 00 = normal 01 = reduce gain by 1db 10 = reduce gain by 3db 11 = normal r/w 0 g lobal r egister (0 x e2 h ) b it n ame f unction register type default value (hw reset)
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 66 t able 45: m icroprocessor r egister 0 x e4 h b it d escription t able 46: m icroprocessor r egister 0 x e5 h b it d escription g lobal r egister (0 x e4 h ) b it n ame f unction register type default value (hw reset) d7 d6 mclkt1out1 mclkt1out0 mclkt1out select mclkt1out[1:0] is used to program the mclkt1out pin. by default, the output clock is 1.544mhz. 00 = 1.544mhz 01 = 3.088mhz 10 = 6.176mhz 11 = 12.352mhz r/w 0 0 d5 d4 mclke1out1 mclke1out0 mclke1out select mclke1out[1:0] is used to program the mclke1out pin. by default, the output clock is 2.048mhz. 00 = 2.048mhz 01 = 4.096mhz 10 = 8.192mhz 11 = 16.384mhz r/w 0 0 d3 reserved this register bit is not used r/w 0 d2 reserved this register bit is not used r/w 0 d1 reserved this register bit is not used r/w 0 d0 reserved this register bit is not used r/w 0 g lobal r egister (0 x e5 h ) b it n ame f unction register type default value (hw reset) d7 lcv/oflw line code violation / counter overflow monitor select this bit is used to select the monitoring activity between the lcv and the counter overflow status. when the 16-bit lcv counter sat - urates, the counter overflow condition is activated. by default, the lcv activity is monitored by bit d4 in register 0x05h. 0 = monitoring lcv 1 = monitoring the counter overflow status r/w 0 d6 cntrden line code violation counter read enable this bit enables the 16-bit lcv counter contents to be read from bits d[7:0] in register 0xe8h. if a counter reaches full scale, it sat - urates and remains at ffffh until a reset is initiated in register 0xe6h. by default, the lcv counter readback function is disabled. 0 = disabled 1 = enables the 16-bit lcv counters for readback r/w 0 d5 reserved this register bit is not used r/w 0
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 67 t able 47: m icroprocessor r egister 0 x e6 h b it d escription d4 reserved this register bit is not used r/w 0 d3 d2 d1 d0 lcvch3 lcvch2 lcvch1 lcvch0 line code violation counter select these bits are used to select wh ich channel is to be addressed for reading the contents in register 0x e8h. it is also used to address the counter for a given channel when performing an update or reset on a per channel basis. by default, channel 0 is selected. 0000 = none 0001 = channel 0 0010 = channel 1 0011 = channel 2 0100 = channel 3 0101 = channel 4 0110 = channel 5 0111 = channel 6 1000 = channel 7 1001 = channel 8 1010 = channel 9 1011 = channel 10 1100 = channel 11 1101 = channel 12 1110 = channel 13 r/w 0 0 0 0 g lobal r egister (0 x e6 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0 d6 reserved this register bit is not used r/w 0 d5 reserved this register bit is not used r/w 0 d4 allrst lcv counter reset for all channels this bit is used to reset all inte rnal lcv counters to their default state 0000h. this bit must be set to "1" for 1 s. 0 = normal operation 1 = resets all counters r/w 0 d3 allupdate lcv counter update for all channels this bit is used to latch the contents of all 14 counters into holding registers so that the value of each counter can be read. the chan - nel is addressed by using bits d[3:0] in register 0xe5h. 0 = normal operation 1 = updates all counters r/w 0 g lobal r egister (0 x e5 h ) b it n ame f unction register type default value (hw reset)
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 68 t able 48: m icroprocessor r egister 0 x e7 h b it d escription d2 bytesel lcv counter byte select this bit is used to select the msb or lsb for reading the contents of the lcv counter for a given channel. the channel is addressed by using bits d[3:0] in register 0x e5h. by default, the lsb byte is selected. 0 = low byte 1 = high byte r/w 0 d1 chupdate lcv counter update per channel this bit is used to latch the contents of the counter for a given channel into a holding register so that the value of the counter can be read. the channel is addressed by using bits d[3:0] in register 0xe5h. 0 = normal operation 1 = updates the selected channel r/w 0 d0 reserved lcv counter reset per channel this bit is used to reset the lcv counter of a given channel to its default state 0000h. the channel is addressed by using bits d[3:0] in register 0xe5h. this bi t must be set to "1" for 1 s. 0 = normal operation 1 = resets the selected channel r/w 0 g lobal r egister (0 x e7 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0 d6 reserved this register bit is not used r/w 0 d5 reserved this register bit is not used r/w 0 d4 reserved this register bit is not used r/w 0 d3 reserved this register bit is not used r/w 0 d2 reserved this register bit is not used r/w 0 d1 reserved this register bit is not used r/w 0 d0 reserved this register bit is not used r/w 0 g lobal r egister (0 x e6 h ) b it n ame f unction register type default value (hw reset)
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 69 t able 49: m icroprocessor r egister 0 x e8 h b it d escription g lobal r egister (0 x e8 h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 lcvcnt7 lcvcnt6 lcvcnt5 lcvcnt4 lcvcnt3 lcvcnt2 lcvcnt1 lcvcnt0 line code violation byte contents these bits contain the lcv counter contents of the byte selected by bit d2 in register 0xe6h for a given channel. the channel is addressed by using bits d[3:0] in register 0xe5h. by default, the contents contain the lsb, ho wever no channel is selected.. r/w 0 0 0 0 0 0 0 0
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 70 clock select register the input clock source is used to generate all the ne cessary clock references internally to the liu. the microprocessor timing is derived from a pll output whic h is chosen by programming the clock select bits in register 0xe9h. therefore, if the clock selection bits are being programmed, the frequency of the pll output will be adjusted accordingly. during this adjustment, it is import ant to "not" write to any other bit location within the same register while selecting the input/output clock frequency. for best results, register 0xe9h can be broken down into two sub-registers with the msb being bi ts d[7:4] and the lsb being bits d[3:0] as shown in figure 42 . note: bits d[7:6] are reserved. f igure 42. r egister 0 x e9 h s ub r egisters programming examples: example 1: changing bits d[7:4] if bits d[7:4] are the only values wit hin the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 2: changing bits d[3:0] if bits d[3:0] are the only values wit hin the register that will change in a write process, th e microprocessor only needs to initiate one write operation. example 3: changing bits within the msb and lsb in this scenario, one must initiate two write operations such that th e msb and lsb do not change within one write cycle. it is recommended that th e msb and lsb be treated as two in dependent sub-registers. one can either change the clock selection (lsb) and then change bits d[5:4] (msb) on the second write, or vice- versa. no order or sequence is necessary. t able 50: m icroprocessor r egister 0 x e9 h b it d escription g lobal r egister (0 x e9 h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used r/w 0 d6 reserved this register bit is not used r/w 0 d0 d1 d2 d3 d4 d5 d6 d7 msb lsb clock selection bits allt1/e1, clkcntl
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 71 d5 allt1/e1 t1/e1 control this bit is used to reduce system noise and power consumption. if the all t1/e1 mode is enabled, all output clock references (excluding the 8khzout in e1 mode only) are internally shut off. by default, the all t1/e1 mode is enabled. 0 = enabled (reduce clock switching and power consumption) 1 = disabled (all clock references are available) r/w 0 d4 tclkcnl transmit clock control this bit is used to select the tran smit output activity at ttip/tring when tclk is either pulled "low", pulled "high", or missing. 0 = transmit all zeros 1 = taos (transmit all ones) r/w 0 d3 d2 d1 d0 clksel3 clksel2 clksel1 clksel0 clock input select clksel[3:0] is used to select t he input clock sour ce used as the internal timing reference. 0000 = 2.048 mhz 0001 = 1.544 mhz 0010 = 8 khz 0011 = 16 khz 0100 = 56 khz 0101 = 64 khz 0110 = 128 khz 0111 = 256 khz 1000 = 4.096 mhz 1001 = 3.088 mhz 1010 = 8.192 mhz 1011 = 6.176 mhz 1100 = 16.384 mhz 1101 = 12.352 mhz 1110 = 2.048 mhz 1111 = 1.544 mhz r/w 0 0 0 0 g lobal r egister (0 x e9 h ) b it n ame f unction register type default value (hw reset)
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 72 t able 51: m icroprocessor r egister 0 x ea h b it d escription t able 52: m icroprocessor r egister 0 x eb h b it d escription g lobal r egister (0 x ea h ) b it n ame f unction register type default value (hw reset) d7 gchis7 global channel interrupt status for channel 7 0 = no interrupt activity from channel 7 1 = interrupt was generated from channel 7 rur 0 d6 gchis6 global channel interrupt status for channel 6 0 = no interrupt activity from channel 6 1 = interrupt was generated from channel 6 rur 0 d5 gchis5 global channel interrupt status for channel 5 0 = no interrupt activity from channel 5 1 = interrupt was generated from channel 5 rur 0 d4 gchis4 global channel interrupt status for channel 4 0 = no interrupt activity from channel 4 1 = interrupt was generated from channel 4 rur 0 d3 gchis3 global channel interrupt status for channel 3 0 = no interrupt activity from channel 3 1 = interrupt was generated from channel 3 rur 0 d2 gchis2 global channel interrupt status for channel 2 0 = no interrupt activity from channel 2 1 = interrupt was generated from channel 2 rur 0 d1 gchis1 global channel interrupt status for channel 1 0 = no interrupt activity from channel 1 1 = interrupt was generated from channel 1 rur 0 d0 gchis0 global channel interrupt status for channel 0 0 = no interrupt activity from channel 0 1 = interrupt was generated from channel 0 rur 0 g lobal r egister (0 x eb h ) b it n ame f unction register type default value (hw reset) d7 reserved this register bit is not used rur 0 d6 reserved this register bit is not used rur 0 d5 gchis13 global channel interrupt status for channel 13 0 = no interrupt activity from channel 13 1 = interrupt was generated from channel 13 rur 0
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 73 t able 53: e1 a rbitrary s elect d4 gchis12 global channel interrupt status for channel 12 0 = no interrupt activity from channel 12 1 = interrupt was generated from channel 12 rur 0 d3 gchis11 global channel interrupt status for channel 11 0 = no interrupt activity from channel 11 1 = interrupt was generated from channel 11 rur 0 d2 gchis10 global channel interrupt status for channel 10 0 = no interrupt activity from channel 10 1 = interrupt was generated from channel 10 rur 0 d1 gchis9 global channel interrupt status for channel 9 0 = no interrupt activity from channel 9 1 = interrupt was generated from channel 9 rur 0 d0 gchis8 global channel interrupt status for channel 8 0 = no interrupt activity from channel 8 1 = interrupt was generated from channel 8 rur 0 e1 a rbitrary s elect r egister (0 x f4 h ) b it n ame f unction register type default value (hw reset) d[7:1] reserved d0 e1arben e1 arbitrary pulse enable this bit is used to enable the arbitrary pulse generators for shap - ing the transmit pulse shape when e1 mode is selected. if this bit is set to "1", all 14 channels will be configured for the arbitrary mode. however, each channel is individually controlled by pro - gramming the channel registers 0xn8 through 0xnf, where n is the number of the channel. "0" = disabled (normal e1 pulse shape itu g.703) "1" = arbitrary pulse enabled r/w 0 g lobal r egister (0 x eb h ) b it n ame f unction register type default value (hw reset)
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 74 microprocessor register 0xfeh bit description t able 54: m icroprocessor r egister 0 x ff h b it d escription d evice "id" r egister (0 x fe h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 device "id" the device "id" of the xrt83sl31 4 short haul liu is 0xfeh. along with the revision "id", the device "id" is used to enable soft - ware to identify the silicon adding flexibility for system control and debug. ro 1 1 1 1 1 1 1 0 r evision "id" r egister (0 x ff h ) b it n ame f unction register type default value (hw reset) d7 d6 d5 d4 d3 d2 d1 d0 revision "id" the revision "id" of the xrt83sl314 liu is used to enable soft - ware to identify which revision of silicon is currently being tested. the revision "id" for the first revision of silicon will be 0x01h. ro 0 0 0 0 0 0 0 1
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 75 electrical characteristics n ote : input leakage current excludes pins that are internally pulled "low" or "high" t able 55: a bsolute m aximum r atings storage temperature -65c to +150c operating temperature -40c to +85c supply voltage -0.5v to +3.8v vin -0.5v to +5.5v t able 56: dc d igital i nput and o utput e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter s ymbol m in t yp m ax u nits power supply voltage vdd 3.13 3.3 3.46 v input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage ioh=2.0ma v oh 2.4 - v output low voltage iol=2.0ma v ol - - 0.4 v input leakage current i l - - 10 a input capacitance c i - 5.0 pf output lead capacitance c l - - 25 pf t able 57: ac e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter s ymbol m in t yp m ax u nits mclkin clock duty cycle 40 - 60 % mclkin clock tolerance - 50 - ppm
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 76 t able 58: p ower c onsumption vdd=3.3v 5%, t a =25c, i nternal i mpedance , u nless o therwise s pecified m ode s upply v oltage i mpedance r eceiver t ransmitter t yp m ax u nit t est c ondition e1 3.3v 75 ? 1:1 1:2 2.80 3.29 w 100% ones e1 3.3v 120 ? 1:1 1:2 2.52 2.96 w 100% ones t1 3.3v 100 ? 1:1 1:2 2.81 3.31 w 100% ones - 3.3v - 1:1 1:2 620 730 mw all trans - mitters turned off t able 59: e1 r eceiver e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition receiver loss of signal number of consecutive zeros before rlos is declared input signal level at rlos rlos clear 10 15 12.5 175 20 - 255 - - db db cable attenuation @ 1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 - - db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? with -18db interference signal added. input impedance - 13 - k ? input jitter tolerance 1hz 10khz - 100khz 37 0.2 - - - - ui p-p ui p-p itu-g.823 recovered clock jitter transfer corner frequency peaking amplitude - - 36 - - -0.5 khz db itu-g.736
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 77 jitter attenuator corner fre - quency jabw = 0 jabw = 1 - - 10 1.5 - - hz hz itu-g.736 return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 14 20 16 - - - - - - db db db itu-g.703 t able 60: t1 r eceiver e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition receiver loss of signal number of consecutive zeros before rlos is declared input signal level at rlos rlos clear 100 15 12.5 175 20 - 250 - - db % ones cable attenuation @ 772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - - db with nominal pulse amplitude of 3.0v for 100 ? termination. input impedance - 13 - k ? input jitter tolerance 1hz 10khz - 100khz 138 0.4 - - - - ui p-p ui p-p at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 9.8 - - 0.1 khz db tr-tsy-000499 jitter attenuator corner fre - quency - 6 - hz at&t pub 62411 return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 20 25 25 - - - db db db t able 59: e1 r eceiver e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition
xr xrt83sl314 14-channel t1/e1/j1 short-haul line interface unit rev. 1.0.1 78 t able 61: e1 t ransmitter e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition ami output pulse amplitude 75 ? 120 ? 2.185 2.76 2.37 3.00 2.555 3.24 v v 1:2 transformer output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 itu-g.703 output pulse amplitude ratio 0.95 - 1.05 itu-g.703 jitter added by the transmitter output - 0.025 0.05 ui p-p broad band with jitter free tclk applied to the input. output return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 8 14 10 - - - - - - db db db etsi 300 166, chptt t able 62: t1 t ransmitter e lectrical c haracteristics vdd=3.3v 5%, t a =25c, u nless o therwise s pecified p arameter m in t yp m ax u nit t est c ondition ami output pulse amplitude 2.5 3.0 3.5 v 1:2 transformer measured at dsx-1 output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 ansi t1.102 output pulse amplitude imbal - ance - - 200 mv ansi t1.102 jitter added by the transmitter output - 0.025 0.05 ui p-p broad band with jitter free tclk applied to the input. output return loss 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 15 15 15 - - - db db db
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 79 ordering information package dimensions (die down) p roduct n umber p ackage o perating t emperature r ange xrt83sl314ib 304 lead tbga -40 0 c to +85 0 c symbol min max min max a 0.051 0.067 1.30 1.70 a1 0.018 0.028 0.45 0.70 a2 0.031 0.071 0.80 1.80 p 0.004 0.012 0.10 0.30 d 1.213 1.228 30.80 31.20 d1 1.100 bsc 27.94 bsc b 0.024 0.035 0.60 0.90 e 0.050 bsc 1.27 bsc inches millimeters note: the control dimension is in millimeter. p d d1 d d1 a1 feature/mark 1 a (a1 corner feature is mfger option) a1 a seating plane ac e c j l n g r u w aa b d f h k m p t v y ab 23 3 5 7 9 11 15 17 13 19 21 2 4 6 8 10 12 14 16 18 20 22 e b a2
xrt83sl314 xr rev. 1.0.1 14-channel t1/e1/j1 short-haul line interface unit 80 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2005 exar corporation datasheet march 2005. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. revision history r evision # d ate d escription p1.0.0 01/22/03 first release of the 14-channel liu preliminary datasheet p1.0.1 01/28/03 added the motorola 68k asynchronous mode timing p1.0.2 02/14/03 edited the microprocessor timing specifications p1.0.3 03/27/03 added the 16-bit lcv counter details for revision b silicon p1.0.4 09/19/03 changed the microprocessor access timing parameters p1.0.5 11/12/03 added new e1 arbitrary pulse feature. added descriptions to the global registers. 1.0.0 05/04/04 final release. 1.0.1 03/17/05 modified int pad description from open-drain to internal pulled-up.

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