ds023 (v1.4) august 27, 2001 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? lowest power 32 macrocell cpld 5.0 ns pin-to-pin logic delays system frequencies up to 200 mhz 32 macrocells with 800 usable gates available in small footprint packages - 48-ball cs bga (36 user i/o pins) - 44-pin vqfp (36 user i/o) - 44-pin plcc (36 user i/o) optimized for 3.3v systems - ultra-low power operation - 5v tolerant i/o pins with 3.3v core supply - advanced 0.35 micron five layer metal eeprom process - fzp? cmos design technology advanced system features - in-system programming - input registers - predictable timing model - up to 23 available clocks per function block - excellent pin retention during design changes - full ieee standard 1149.1 boundary-scan (jtag) - four global clocks - eight product term control terms per function block fast isp programming times port enable pin for dual function of jtag isp pins 2.7v to 3.6v supply voltage at industrial temperature range programmable slew rate control per macrocell security bit prevents unauthorized access refer to xpla3 family data sheet (ds012) for architecture description description the XCR3032XL is a 3.3v, 32-macrocell cpld targeted at power sensitive designs that require leading edge program- mable logic solutions. a total of two function blocks provide 800 usable gates. pin-to-pin propagation delays are 5.0 ns with a maximum system frequency of 200 mhz. totalcmos? design technique for fast zero power xilinx offers a totalcmos cpld, both in process technol- ogy and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate imple- mentation allows xilinx to offer cplds that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 1 and table 1 showing the i cc vs. frequency of our XCR3032XL totalcmos cpld (data taken with two up/down, loadable 16-bit counters at 3.3v, 25 c). 0 XCR3032XL 32 macrocell cpld ds023 (v1.4) august 27, 2001 014 preliminary product specification r figure 1: i cc vs. frequency at v cc = 3.3v, 25 c 5 0 1 0 1 5 2 0 0 2 0 4 0 60 80 1 00 12 0 14 0 1 60 1 80 2 00 frequenc y (mhz ) ds023 _ 01 _ 08010 1 ty pical i cc ( ma ) table 1: i cc vs. frequency (v cc = 3.3v, 25 c) frequency (mhz) 0 1 5 10 20 50 100 200 ty p ic a l i cc (ma) 0.02 0.13 0.54 1.06 2.09 5.2 10.26 20.3
XCR3032XL 32 macrocell cpld 2 www.xilinx.com ds023 (v1.4) august 27, 2001 1-800-255-7778 preliminary product specification r dc electrical characteristics over recommended operating conditions (1) symbol parameter test conditions min. max. unit v oh ( 2 ) output high voltage v cc = 3.0v to 3.6v, i oh = ? 8 ma 2.4 - v v cc = 2.7v to 3.0v, i oh = ? 8 ma 2.0 ( 3 ) -v i oh = ? 500 a 90% v cc -v v ol output low voltage i ol = 8 ma - 0.4 v i il ( 4 ) input leakage current v in = gnd or v cc ? 10 10 a i ih ( 4 ) i/o high-z leakage current v in = gnd or v cc ? 10 10 a i ccsb standby current v cc = 3.6v - 100 a i cc dynamic current ( 5 , 6 ) f = 1 mhz - 0.25 ma f = 50 mhz - 7.5 ma c in input pin capacitance ( 7 ) f = 1 mhz - 8 pf c clk clock input capacitance ( 7 ) f = 1 mhz - 12 pf c i/o i/o pin capacitance ( 7 ) f = 1 mhz - 10 pf notes: 1. see xpla3 family data sheet (ds012) for recommended operating conditions 2. see figure 2 for output drive characteristics of the xpla3 family. 3. this parameter guaranteed by design and characterization, not by testing. 4. typical leakage current is less than 1 a. 5. see table 1 , figure 1 for typical values. 6. this parameter measured with a 16-bit, loadable up/down counter loaded into every function block, with all outputs disabled a nd unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 7. typical values, not tested. figure 2: typical i/v curve for the xpla3 family 0 0 1 0 2 0 30 4 0 50 60 7 0 80 90 1 00 0 . 5 1 1. 5 2 2. 5 3 3 . 5 4 4. 5 5 volt s i o l ( 3.3v ) i o h ( 3.3v ) i o h ( 2.7v ) m a ds012 _ 10 _ 04190 1
XCR3032XL 32 macrocell cpld ds023 (v1.4) august 27, 2001 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r ac electrical characteristics over recommended operating conditions (1,2) symbol parameter -5 -7 -10 unit min. max. min. max. min. max. t pd1 propagation delay time (single p-term) 4.5 - 7.0 - 9.1 ns t pd2 propagation delay time (or array) (3) 5.0 - 7.5 - 10.0 ns t co clock to output (global synchronous pin clock) 3.5 5.0 - 6.5 ns t suf setup time fast 2.5 - 3.0 - 3.0 - ns t su setup time 3.5 - 4.8 - 6.3 - ns t h (4) hold time 0-0-0-ns t wlh (4) global clock pulse width (high or low) 2.5 - 3.0 - 4.0 - ns t plh (4) p-term clock pulse width 4.0 - 5.0 - 6.0 - ns t r (4) input rise time - 20 - 20 - 20 ns t l (4) input fall time - 20 - 20 - 20 ns f system (4) maximum system frequency - 200 - 119 - 95 mhz t config (4) configuration time (5) - 30.0 - 30.0 - 30.0 s t init (4) isp initialization time - 30.0 - 30.0 - 30.0 s t poe (4) p-term oe to output enabled - 7.2 - 9.3 - 11.2 ns t pod (4) p-term oe to output disabled (6) -7.2-9.3-11.2ns t pco (4) p-term clock to output - 5.5 - 8.3 - 10.7 ns t pao (4) p-term set/reset to output valid - 6.5 - 9.3 - 11.2 ns notes: 1. specifications measured with one output switching. 2. see xpla3 family data sheet (ds012) for recommended operating conditions. 3. see figure 4 for derating. 4. these parameters guaranteed by design and/or characterization, not testing. 5. typical current draw during configuration is 7 ma at 3.6v. 6. output c l = 5 pf.
XCR3032XL 32 macrocell cpld 4 www.xilinx.com ds023 (v1.4) august 27, 2001 1-800-255-7778 preliminary product specification r internal timing parameters (1,2) symbol parameter -5 -7 -10 unit min. max. min. max. min. max. buffer delays t in input buffer delay - 0.7 - 1.6 - 2.2 ns t fin fast input buffer delay - 2.2 - 3.0 - 3.1 ns t gck global clock buffer delay - 0.7 - 1.0 - 1.3 ns t out output buffer delay - 1.8 - 2.7 - 3.6 ns t en output buffer enable/disable delay - 4.5 - 5.0 - 5.7 ns internal register and combinatorial delays t ldi latch transparent delay - 1.3 - 1.6 - 2.0 ns t sui register setup time 1.0 - 1.0 - 1.2 - ns t hi register hold time 4.0 - 5.5 - 6.7 - ns t ecsu register clock enable setup time 2.0 - 2.5 - 3.0 - ns t echo register clock enable hold time 3.0 - 4.5 - 5.5 - ns t coi register clock to output delay - 1.0 - 1.3 - 1.6 ns t aoi register async. s/r to output delay - 2.0 - 2.3 - 2.1 ns t rai register async. recovery - 3.5 - 5.0 - 6.0 ns t logi1 internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns t logi2 internal logic delay (pla or term) - 2.5 - 3.2 - 4.2 ns feedback delays t f zia delay - 0.5 - 2.9 - 3.5 ns time adders t logi3 fold-back nand delay - 2.0 - 2.5 - 3.0 ns t uda universal delay - 1.2 - 2.0 - 2.5 ns t slew slew rate limited delay - 4.0 - 5.0 - 6.0 ns notes: 1. these parameters guaranteed by design and characterization, not testing. 2. see xpla3 family data sheet (ds012) for timing model.
XCR3032XL 32 macrocell cpld ds023 (v1.4) august 27, 2001 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r switching characteristics figure 3: ac load circuit v cc v out v in c1 r1 r2 s1 s2 ds023_04_050200 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t poe (high) t poe (low) t p open closed closed open closed closed note: for t pod , c1 = 5 pf figure 4: derating curve for t pd2 3 . 0 3 . 5 4. 0 4. 5 1 2 4 8 1 6 d s023 _ 05 _ 06110 1 output s t pd ( ns ) figure 5: voltage waveform 90% 10% 1.5 ns 1.5 ns ds023_06_042800 +3.0v 0v measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. t r t l
XCR3032XL 32 macrocell cpld 6 www.xilinx.com ds023 (v1.4) august 27, 2001 1-800-255-7778 preliminary product specification r pin descriptions table 2: XCR3032XL user i/o pins pc44 vq44 cs48 total user i/o pins 36 36 36 table 3: XCR3032XL i/o pins function block macrocell pc44 vq44 cs48 1 1 442a2 1 2 543a1 13644c4 147 (1) 1 (1) b1 (1) 1 5 82c2 1 6 93c1 17115d3 18126d1 1913 (1) 7 (1) d2 (1) 110148e1 1 111610f1 1121711g1 1131812e4 1 141913f2 1152014g2 1 162115f3 2 1 41 35 c5 2 2 40 34 a6 2 3 39 33 b6 2438 (1) 32 (1) b7 (1) 2 5 37 31 d4 2 6 36 30 c6 2 7 34 28 d6 2 8 33 27 d7 2932 (1) 26 (1) e5 (1) 2103125e7 2 112923f7 2122822g7 2132721g6 2 142620f5 2152519g5 2162418f4 notes: 1. jtag pins ta ble 4 : XCR3032XL global, jtag, port enable, power, and no connect pins pin type pc44 vq44 cs48 in0 / clk0 2 40 a3 in1 / clk1 1 39 b4 in2 / clk2 44 38 a4 in3 / clk3 43 37 b5 tck 32 26 e5 tdi 7 1 b1 tdo 38 32 b7 tms 13 7 d2 port_en 10 (1) 4 (1) c3 (1) v cc 3, 15, 23, 35 9, 17, 29, 41 b3, c7, e2, g4 gnd 22, 30, 42 16, 24, 36 a5, e3, e6 no connects - - a7, b2, f6, g3 notes: 1. port enable is brought high to enable jtag pins when jtag pins are used as i/o. see family data sheet for full explanation. ta ble 3 : XCR3032XL i/o pins function block macrocell pc44 vq44 cs48
XCR3032XL 32 macrocell cpld ds023 (v1.4) august 27, 2001 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r ordering information component availability revision history the following table shows the revision history for this document. pins 44 44 48 type plastic plcc plastic vqfp plastic bga code pc44 vq44 cs48 XCR3032XL -5 c c c -7 c,i c,i c,i -10 c, i c, i c, i date version revision 11/18/00 1.0 initial xilinx release. 02/05/01 1.1 removed timing model. 04/11/01 1.2 update tsuf spec to meet umc characterization data. added icc vs. freq. numbers, ta b l e 1 and updated figure 1 . added typical i/v curve, figure 2 ; added ta ble 2 : total user i/o; changed v oh spec. 04/19/01 1.3 updated typical i/v curve, figure 2 : added voltage levels. 08/27/01 1.4 changed from advance to preliminary; updated dc electrical characteristics; ac electrical characteristics; internal timing parameters; added derating curve; added -10 industrial packages. added 200 mhz to figure 1 and ta ble 1 . changed -5 f system to 200 mhz, -5 t f to 0.5 ns. XCR3032XL -5 vq 44 c example: temperature range number of pins package type device type speed grade device ordering options speed package temperature -10 10 ns pin-to-pin delay pc44 44-pin plastic lead chip carrier (plcc) c = commercial t a = 0 c to +70 c v cc = 3.0v to 3.6v -7 7.5 ns pin-to-pin delay vq44 44-pin very thin quad flat pack (vqfp) i = industrial t a = ? 40 c to +85 c v cc = 2.7v to 3.6v -5 5 ns pin-to-pin delay cs48 48-ball chip scale package
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