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? semtech corporation 1 sc9301 10a ecospeed ? integrated fet regulator with 5v ldo and hiccup restart features power system input voltage 3v to 28v bias voltage 5v ldo or 3v to 5.5v external up to 96% peak effi ciency integrated bootstrap switch ldo output current up to 200ma reference tolerance 1% t j = -40 to +125 c ecospeed ? architecture with pseudo-fi xed fre- quency adaptive on-time control pre-bias start-up logic input and output control independent enable control for ldo and switcher programmable v in uvlo threshold power good output programmable soft-start time all protection: automatic restart on fault over-voltage and under-voltage tc compensated r ds(on) sensed current limit thermal shutdown smart gate drive reduces emi capacitor types: sp, poscap, oscon, and ceramic package 5 x 5(mm), 32-pin mlpq lead-free and halogen-free rohs and weee compliant applications networking and telecommunication equipment printers, dsl, and stb applications point-of-load power supplies and module replacement ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? description the sc9301 is a stand-alone synchronous ec ospeed ? buck regulator with adaptive on-time control architecture. it features integrated power mosfets, a bootstrap switch, and a fi xed 5v ldo in a 5x5mm package. the device is highly effi cient and uses minimal pcb area. the sc9301 supports using standard capacitor types such as electro- lytic or specialty polymer, in addition to ceramic, at switch- ing frequencies up to 1mhz. additional features include programmable cycle-by-cycle current limit protection, programmable soft-start, under and over-voltage protection, automatic fault recovery (hiccup restart), and soft shutdown. the device also pro- vides separate enable inputs for the pwm controller and ldo as well as a power good output for the pwm controller. rev. 2.0 power management typical application circuit rton sc9301 fb vout vdd vin ss bst lx pgood ilim lxs en enl lxbst rilim cbst + rfb1 rfb2 vout cout l1 cin vin pgood ton 1 f csoft
sc9301 2 pin confi guration ordering information marking information 9301 yyww xxxx agnd pad 1 vin pad 2 lx pad 3 enl 32 ton 31 agnd 30 en 29 lxs 28 ilim 27 pgood 26 lx 25 24 lx lx 23 pgnd 22 pgnd 21 pgnd 20 pgnd 19 pgnd 18 pgnd 17 pgnd 16 pgnd 15 dl 14 lxbst 13 dh 12 vin 11 vin 10 vin 9 bst 8 vldo 5 ss 7 vin 6 vdd 3 agnd 4 fb 1 top view vout 2 notes: 1) available in tape and reel only. a reel contains 3000 devices. 2) lead-free packaging only. device is weee and rohs compliant and halogen-free. yyww = date code xxxx = semtech lot number mlpq-ut32 device package sc9301mltrt (1)(2) mlpq-32, 5 x 5(mm) SC9301EVB evaluation board
sc9301 3 absolute maximum ratings (1) lx to pgnd (v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 lx to pgnd (v) (transient 100ns max.) . . . . . . -2 to +30 dh, bst to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +35 dh, bst to lx (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 dl to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6 vin to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +30 en, fb, ilim, pgood to agnd (v) . . . . . . -0.3 to +(vdd + 0.3) ss, vldo, vout to agnd (v) . . . . . . . . . -0.3 to +(vdd + 0.3) ton to agnd (v). . . . . . . . . . . . . . . . . . . . . -0.3 to +(vdd -1.5) enl to agnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to vin vdd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 to +6 agnd to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3 to +0.3 esd protection level (1) (kv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 recommended operating conditions input voltage (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 to 28 vdd to pgnd (v) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 to 5.5 vout to pgnd (v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 to 5.5 thermal information storage temperature (c) . . . . . . . . . . . . . . . . . . . . -60 to +150 maximum junction temperature (c) . . . . . . . . . . . . . . . . 150 operating junction temperature (c) . . . . . . . . -40 to +125 thermal resistance, junction to ambient (2) (c/w) high-side mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 low-side mosfet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pwm controller and ldo thermal resistance . . . . . 50 peak ir refl ow temperature (c) . . . . . . . . . . . . . . . . . . . . 260 exceeding the above specifi cations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters specifi ed in the electrical characteristics section is not recommended. notes: (1) tested according to jedec standard jesd22-a114. (2) calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer fr4 pcb with thermal vias under the exposed pad p er jesd51 standards. unless specifi ed: v in =12v, vdd = 5v, t a = +25c for typ, -40 to +85 c for min and max, t j < 125c, typical application circuit electrical characteristics parameter conditions min typ max units input supplies input supply voltage v in > vdd 3 28 v vdd voltage 3 5.5 v vin uvlo threshold (1) sensed at enl pin, rising edge 1.47 1.57 1.77 v sensed at enl pin, falling edge 1.15 1.35 vin uvlo hysteresis sensed at enl pin; en = 5v 0.3 v vdd uvlo threshold measured at vdd pin, rising edge 2.5 3.0 v measured at vdd pin, falling edge 2.4 2.9 vdd uvlo hysteresis 0.18 v vin supply current shutdown mode; enl , en = 0v 8.5 20 a standby mode; enl = vdd, en = 0v 130
sc9301 4 electrical characteristics (continued) parameter conditions min typ max units input supplies (continued) vdd supply current enl , en = 0v 3 7 a vdd =5v, f sw = 270khz, en = vdd, no load (2) 7.7 ma vdd =3.3v, f sw = 280khz, en = vdd, no load (2) 5.1 ma fb comparator threshold static v in and load, t j = 0 to +125 c 0.595 0.600 0.605 v static v in and load, t j = -40 to +125 c 0.594 0.600 0.606 v frequency range 1000 khz bootstrap switch resistance 17 timing on-time v in = 15v, v out = 3v, r ton = 300k, vdd = 5v 1395 1600 1805 ns minimum on-time (2) 80 ns minimum off -time (2) vdd =5v 250 ns vdd =3.3v 370 ns soft-start soft-start charge current 3.0 a soft-start voltage (2) when v out reaches regulation 1.5 v analog inputs/outputs vout input resistance 500 k power good power good threshold upper limit, v fb > internal 600mv reference +20 % lower limit, v fb < internal 600mv reference -10 % power good hysteresis 1.2 % start-up delay time (2) (between pwm enable and pgood high) vdd = 5v, c ss = 3.3nf 3.8 ms vdd = 3.3v, c ss = 3.3nf 2.6 ms fault (noise immunity) delay time (2) 5s leakage pgood = high impedance (open) 1 a power good on resistance 10
sc9301 5 electrical characteristics (continued) parameter conditions min typ max units fault protection valley current limit (3) vdd = 5v, r ilim = 7320, t j = 0 to +125 c 8.5 10 11.5 a vdd = 3.3v, r ilim = 7320, t j = 0 to +125 c 9 a i lim source current trimmed to match lower fet rdson 9 a i lim comparator off set with respect to agnd -8 0 +8 mv output under-voltage threshold v fb with respect to internal 600mv reference, 8 consecutive cycles -25 % smart power-save protection threshold (2) v fb with respect to internal 600mv reference +10 % over-voltage protection threshold v fb with respect to internal 600mv reference +20 % over-voltage fault delay (2) 5s over-temperature shutdown (2) 10c hysteresis 150 c logic inputs/outputs logic input high voltage en, enl 1.0 v logic input low voltage en, enl 0.4 v en input bias current en = vdd or agnd -10 +10 a enl input bias current enl = v in = 28v -1 11 +18 a fb input bias current fb = vdd or agnd -1 +1 a linear regulator (ldo) vldo accuracy vldo load = 10ma 4.90 5.0 5.10 v current limit short-circuit protection, v in = 12v, vldo < 1v 20 ma v in = 12v, 1v < vldo < 4.5v 115 operating, vldo > 4.5v 200 vldo drop out voltage (4) v in to vldo, vldo load = 100ma 1.9 v notes: (1) vin uvlo is programmable using a resistor divider from vin to enl to agnd. the enl voltage is compared to an internal refer ence. (2) typical value measured on standard evaluation board. (3) the device has fi rst order temperature compensation for over current. results vary based upon the pcb thermal layout. (4) the ldo drop out voltage is the voltage at which the ldo output drops 2% below the nominal regulation point.
sc9301 6 rton 130 k sc9301 fb 1 vout 2 vdd 3 agnd 4 vldo 5 vin 6 ss 7 bst 8 vin 9 vin 10 vin 11 pgnd 15 pgnd 16 17 18 19 20 21 pgnd 22 lx 23 lx 24 lx 25 pgood 26 ilim 27 lxs 28 en 29 agnd 30 to n 31 enl 32 dl 14 lxbst 13 dh 12 vin pad 2 agnd pad 1 lx pad 3 rilim 7.68k cin 2 x 10 f (see note) rgnd 0 cbst 1 f vin pgnd pgnd pgnd pgnd pgnd rfb1 10k l1 1.2 h rfb2 6.65k vout 1.5v @ 10a, 350khz en en ldo + cout 6m 330 f pgood 1 f component value manufacturer part number web cin (see note) 2 x 10 f/25v murata grm32dr71e106ka12l www.murata.com www.sanyo.com key components note: the quantity of 10 f input capacitors required varies with the application requirements. www.we-online.com 3.3nf 22 f 1 f cout 330 f/6m sanyo 2tpf330m6 744 325 120 1.2 h/1.8m wurth elektronik l1 rbst 0 detailed application circuit
sc9301 7 typical characteristics effi ciency/power loss vs. load 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 power loss (w) v in = 5v v in = 12v v in = 25v v in = 18v v in = 5v v in = 25v v in = 12v v in = 18v characteristics in this section are based upon using the typical application circuit on page 6. v out = 1v v out = 1.5v 50 55 60 65 70 75 80 85 90 95 100 0 12345678910 i out (a ) efficiency (%) v out = 3.3v v out = 5v v out = 2.5v 50 55 60 65 70 75 80 85 90 95 100 0 12345678910 i out (a) efficiency (%) -0.150 -0.100 -0.050 0.000 0.050 0.100 0.150 0.200 0.250 0.300 0.350 p loss (w) 3.3v bias 5v bias 3.3v minus 5v 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 p loss (w) v in = 5v v in = 12v v in = 5v v in = 25v v in = 25v v in = 12v v in = 18v v in = 18v 50 55 60 65 70 75 80 85 90 95 100 012345678910 i out (a) efficiency (%) 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 0.160 0.180 0.200 p loss (w) ext-bias ldo-bias ldo minus ext 0 50 100 150 200 250 300 350 400 012345678910 i out (a) switching frequency (khz) effi ciency/power loss vs. load effi ciency/power loss comparison effi ciency/power loss comparison effi ciency/power loss comparison switching frequency vs. load ldo bias, vdd = 5v, v out = 1.5v external bias, vdd = 5v, v out = 1.5v vdd = 5v, v out = 1.5v, v in = 12v external bias, v in = 12v, v out = 1.5v vdd = 5v, v in = 12v, l = 2.2uh (4.6m) for v out = 2.5v, 3.3v and 5v external bias, vdd = 5v, v out = 1.5v, v in = 12v
sc9301 8 typical characteristics load regulation 1.500 1.505 1.510 1.515 1.520 1.525 1.530 012345678910 i out (a) vout (v) v in = 25v v in = 18v v in = 12v characteristics in this section are based upon using the typical application circuit on page 6. v in = 25v 1.500 1.505 1.510 1.515 1.520 1.525 1.530 012345678910 i out (a) vout (v) v in = 12v v in = 18v load regulation load regulation vs. temperature external bias, vdd = 5v, v out = 1.5v ldo bias, vdd = 5v, v out = 1.5v external bias, vdd = 5v, v out = 1.5v t a = 85c v in = 12v 1.500 1.505 1.510 1.515 1.520 1.525 1.530 012345678910 i out (a) vout (v) t a = -40c v in = 5v t a = 85c v in = 5v t a = -40c v in = 12v 1.500 1.505 1.510 1.515 1.520 1.525 1.530 012345678910 i out (a) vout (v) v in = 12v v in = 5v load regulation load regulation vs. temperature external bias, vdd = 3.3v, v out = 1.5v external bias, vdd = 3.3v, v out = 1.5v 1.500 1.505 1.510 1.515 1.520 1.525 1.530 012345678910 i out (a) vout (v) t a = 85c v in = 12v v in = 18v t a = 85c t a = -40c v in = 18v t a = -40c v in = 25v t a = 85c v in = 25v t a = -40c v in = 12v
sc9301 9 start-up full load typical characteristics (continued) characteristics in this section are based upon using the typical application circuit on page 6. shutdown en time (50s/div) (5v/div) (5v/div) (500mv/div) (10v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 10a steady state no load time (5s/div) (50mv/div) (10v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 0a steady state full load time (5s/div) (50mv/div) (10v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 10a start-up prebias time (1ms/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 0a start-up no load time (1ms/div) (5v/div) (5v/div) (500mv/div) (10v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 10a time (1 ms/div) (5v/div) (500mv/div) (5v/div) vdd = 3.3v, v in = 12v, v out = 1.5v, i out = 0a (5v/div) lx v out en pgood lx v out en pgood lx v out en pgood v out v out lx lx lx v out en pgood (500mv/div) (5v/div) (10v/div) (5v/div)
sc9301 10 transient response typical characteristics (continued) characteristics in this section are based upon using the typical application circuit on page 6. protection ocp then uv time (2ms/div) (200mv/div) (5a/div) (500mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 10a to 12a protection ovp time (50ms/div) (200mv/div) (5v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 0a protection: ocp, uvp then hiccup time: above (20ms/div), bottom (1ms/div) (500mv/div) (2v/div) (5v/div) v in = 12v, v out = 1.5v, i out = 5a to 12a transient response time (20s/div) (5a/div) (50mv/div) (10v/div) vdd = 5v, v in = 12v, v out = 1.5v, i out = 9a to 0a to 9a time (20s/div) (50mv/div) (10v/div) vdd = 5v, v in = 18v, v out = 1.5v, i out = 9a to 0a to 9a zoom-in above (5a/div) (5a/div) 540mv 450mv (5v/div) (500mv/div) start-upshort & over current protection time (500s/div) v in = 12v, v out = 1.5v, i out = oc regulated at valley 10.2a lx v out i out lx v out i out v out i out soft-start pgood lx i out v out inductor current (100mv/div) (5a/div) (5v/div) (5a/div) v out soft-start dl fb v out fb i out pgood
sc9301 11 pin descriptions pin # pin name pin function 1fb feedback input for switching regulator used to program the output voltage connect to an external resis- tor divider from vout to agnd. 2 vout switcher output voltage sense pin. 3 vdd bias supply for the ic. 4, 30, pad 1 agnd analog ground 5 vldo ldo output. connect to vdd when using the internal ldo as a bias power supply. 6, 9-11, pad 2 vin input supply voltage 7 ss the soft-start ramp will be programmed by an internal current source charging a capacitor on this pin. 8 bst bootstrap pin connect a capacitor of at least 100nf from bst to lxbst to develop the fl oating supply for the high-side gate drive. 12 dh high-side gate drive 13 lxbst lx boost connect to the bst capacitor. 23-25, pad 3 lx switching (phase) node 14 dl low-side gate drive 15-22 pgnd power ground 26 pgood open-drain power good indicator high impedance indicates power is good. an external pull-up resistor is required. 27 ilim current limit sense pin used to program the current limit by connecting a resistor from ilim to lxs. 28 lxs lx sense connects to r ilim 29 en enable input for the switching regulator connect to agnd to disable the switching regulator, connect to vdd or fl oat to operate in forced continuous mode. 31 ton on-time programming input set the on-time by connecting through a resistor to agnd 32 enl enable input for the ldo connect enl to agnd to disable the ldo. drive with logic signal for logic con- trol, or program the vin uvlo with a resistor divider between vin, enl, and agnd.
sc9301 12 block diagram reference soft start fb agnd on- time generator control & status pgood gate drive control vin pgnd ton vout valley current limit ilim enl vldo 5v ldo vdd bst fb comparator - lx en dh dl a 12 8 27 14 32 5 3 2 31 1 26 29 a = connected to pins 6, 9-11, pad 2 b = connected to pins 23-25, pad 3 c = connected to pins 15-22 d = connect to pins 4, 30, pad 1 b c d v in vdd vdd v in bootstrap switch low mosfet high mosfet lxbst 13 lxs 28 dl dl vdd vdd vdd ss 7 v in uvlo v in uvlo v in uvlo detector
sc9301 13 synchronous buck converter the sc9301 is a step down synchronous dc-dc buck con- verter with integrated power mosfets and a 200ma capable 5v ldo. the device is capable of 10a operation at very high efficiency. a space saving 5x5 (mm) 32-pin package is used. the programmable operating frequency of up to 1mhz enables optimizing the confi guration for pcb area and effi ciency. the buck controller uses a pseudo-fi xed frequency adap- tive on-time control. this allows fast transient response which permits the use of smaller output capacitors. input voltage requirements the sc9301 requires two input supplies for normal opera- tion: v in and vdd. v in operates over the wide range of 3v to 28v. vdd requires a 3v to 5.5v supply which can be from an external source or from the internal fixed 5v ldo. power up sequence when the sc9301 uses an external power source at the vdd pin, the switching regulator initiates the start up when v in , vdd and en are above their respective thresh- olds. when en is at a logic high, vdd can be applied after v in rises. it is also recommended to use a10 resistor between an external power source and the vdd pin. to start up using the en pin when both vdd and v in are above their respective thresholds, apply en to enable the start- up process. for sc9301 in self-biased mode, refer to the ldo section for a full description. shutdown the sc9301 can be shutdown by pulling either vdd or en below its threshold. when vdd is active and en at low logic, the output voltage discharges through an internal fet. psuedo-fi xed frequency adaptive on-time control the pwm control method used by the sc9301 is pseudo- fi xed frequency, adaptive on-time, as shown in figure 1. the ripple voltage generated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trigger the on-time of the controller. q1 q2 l c out esr + c in v out fb threshold v fb v lx v lx ton fb v in figure 1 pwm control method, v out ripple the adaptive on-time is determined by an internal one- shot timer. when the one-shot is triggered by the output ripple, the device sends a single on-time pulse to the high- side mosfet. the pulse period is determined by v out and v in . the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time confi guration, the device automatically antici- pates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the advantages of adaptive on-time control are: predictable operating frequency compared to other variable frequency methods. reduced component count by eliminating the error amplifi er and compensation components. reduced component count by removing the need to sense and control inductor current. fast transient response the response time is controlled by a fast comparator instead of a typi- cally slow error amplifi er. reduced output capacitance due to fast tran- sient response. one-shot timer and operating frequency one-shot timer operation is shown in figure 2. the fb com- parator output goes high when v fb is less than the internal 600mv reference. this feeds into the dh gate drive and turns on the high-side mosfet, and also starts the one-shot ? ? ? ? ? applications information
sc9301 14 timer. the one-shot timer uses an internal comparator and a capacitor. one comparator input is connected to v out , the other input is connected to the capacitor. when the on- time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns off . gate drives fb comparator one-shot timer on-time = k x r ton x (v out /v in ) v out v in fb q1 q2 l c out v in esr + v out v lx fb dh dl r ton + - v ref figure 2 on-time generation this method automatically produces an on-time that is proportional to v out and inversely proportional to v in . under steady-state conditions, the switching frequency can be determined from the on-time by the following equation. in on out sw v t v f u the sc9301 uses an external resistor to set the on-time which indirectly sets the frequency. the on-time can be programmed to provide an operating frequency from 200khz to 1mhz using a resistor between the ton pin and ground. the resistor value is selected by the following equation. sw ton f pf 75 . 26 k r u the constant, k, equals 1 when vdd is greater than 4.5v. if vdd is less than 4.5v and v in is greater than (vdd -1.8) x 10, k is shown by the following equation. in v 10 8 . 1 vdd k u the maximum r ton value allowed is shown by the follow- ing equation. a 5 . 1 10 v r min _ in max _ ton p u v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 600mv reference voltage (see figure 3). r 1 to fb pin r 2 v out figure 3 output voltage selection note that this control method regulates the valley of the output ripple voltage, not the dc value. the dc value of v out is off set by the output ripple according to the follow- ing equation. ? 1 ? ? ? 1 ? u 2 v r r 1 0.6 v ripple 2 1 out when a large capacitor is placed in parallel with r1 (ctop) vout is shown by the following equation. 2 top 1 2 1 2 2 top 1 ripple 2 1 out & c r r r r 1 ) & c (r 1 2 v r r 1 0.6 v ? ? 1 ? u u ? 1 ? ? ? 1 ? u the switcher output voltage can be programmed higher than 5v with careful design. in this case the vout pin cannot connect directly to the switcher output due to its the maximum voltage rating. an additional resistor divider network is required to connect from the switcher output to the vout pin. when the sc9301 operates from an external 5v supply and the ldo is disabled by ground- ing the enl pin, the voltage at the vout pin can be as high as shown in the recommended operating conditions. note that rton must be adjusted higher by the same divider ratio to maintain the desired on-time; on-time is calculated according to the voltage at the vout pin. applications information (continued)
sc9301 15 forced continuous mode operation the sc9301 operates the switcher in fcm (forced continuous mode) as shown in figure 4. in this mode one of the power mosfets is always on, with no intentional dead time other than to avoid cross-conduction. this feature results in uniform frequency across the full load range. dh is the gate signal to drive upper mosfet. dl is the lower gate signal to drive lower mosfet. fb ripple voltage (v fb ) fb threshold dl dh inductor current dc load current dh on-time is triggered when v fb reaches the fb threshold. on-time (t on ) dl drives high when on-time is completed. dl remains high until v fb falls to the fb threshold. figure 4 forced continuous mode operation smartdrive tm for each dh pulse, the dh driver initially turns on the high-side mosfet at a slower speed, allowing a softer, smooth turn-off of the low-side diode. once the diode is off and the lx voltage has risen 0.5v above pgnd, the smartdrive circuit automatically drives the high-side mosfet on at a rapid rate. this technique reduces switch- ing noise while maintaining high effi ciency, reducing the need for snubbers or series resistors in the gate drive. enable input the en pin is used to enable or disable the switching regu- lator. when en is low, the switching regulator is off and in its lowest power state. when off , the output of the switch- ing regulator soft-discharges the output into a 15 inter- nal resistor via the vout pin. current limit protection the device features programmable current limiting, which is accomplished by using the rds on of the lower mosfet for current sensing. the current limit is set by r ilim resistor. the r ilim resistor connects from the ilim pin to the lxs pin which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~9a current flows from the ilim pin and through the r ilim resistor, creating a voltage drop across the resistor. while the low-side mosfet is on, the inductor current fl ows through it and creates a voltage across the rds on . the voltage across the mosfet is negative with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the ilim pin will be negative and current limit will acti- vate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the ilim voltage back up to zero. this method regulates the inductor valley current at the level shown by i oc in figure 5. time i peak i load i oc inductor current figure 5 valley current limit setting the valley current limit to 10a results in a peak inductor current of 10a plus the peak-to-peak ripple current. in this situation, the average (load) current through the inductor is 10a plus one-half the peak-to- peak ripple current. the internal 9a current source is temperature compen- sated at 4100ppm in order to provide tracking with the rds on . the r ilim value is calculated by the following equations. for vdd>4v; r ilim = 732 x i oc for vdd<4v; r ilim = 834 x i oc applications information (continued)
sc9301 16 when selecting a value for r ilim be sure not to exceed the absolute maximum voltage value for the ilim pin. note that because the low-side mosfet with low rds on is used for current sensing, the pcb layout, solder connections, and pcb connection to the lx node must be done care- fully to obtain good results. r ilim should be connected directly to lxs (pin 28). soft-start of pwm regulator sc9301 has a programmable soft-start time that is con- trolled by an external capacitor at the ss pin. after the controller meets both uvlo and en thresholds, the con- troller has an internal current source of 3a flowing through the ss pin to charge the capacitor. during the start up process (figure 6), 40% of the voltage at the ss pin is used as the reference for the fb comparator. the pwm comparator issues an on-time pulse when the voltage at the fb pin is less than 40% of the ss pin. as result, the output voltage follows the ss start voltage. the output voltage reaches and maintains regulation when the ss pin voltage is > 1.5v. the time between the fi rst lx pulse and when vout meets regulation is the soft-start time (t ss ). the calculation for the soft-start time is shown by the following equation. a 3 v 5 . 1 c t ss ss p u the voltage at the ss pin continues to ramp up and even- tually is equal to 67% of vdd. after soft-start completes, the fb pin voltage is compared to an internal reference of 600mv. the delay time between the vout regulation point and pgood going high is shown by the following equation. ? 1 ? u u p v 5 . 1 3 v 2 a 3 c t in ss pgood figure 6 soft-start timing diagram pre-bias startup sc9301 can start up as if in a soft-start condition with an existing output voltage level. the soft-start time is still the same as normal start up (when the output voltage starts from zero). the output voltage starts to ramp up when 40% of the voltage at ss pin meets the pre-charge fb voltage level. pre-bias startup is achieved by turning off the lower gate when the inductor current falls below zero. this method prevents the output voltage from decreasing. power good output the pgood (power good) output is an open-drain output which requires a pull-up resistor. when the voltage at the fb pin is 10% below the nominal voltage, pgood is pulled low. it remains low until the fb voltage returns above -8% of nominal. during start-up pgood is held low and will not be allowed to transition high until the pgood start- up delay time has passed and soft-start is completed (when v fb reaches 600mv). pgood will transition low if the fb voltage exceeds +20% of nominal (720mv), which is also the over-voltage shut- down threshold. pgood also pulls low if the en pin is low when vdd is present. applications information (continued)
sc9301 17 output over-voltage protection ovp (over-voltage protection) becomes active as soon as the device is enabled. the ovp threshold is set at 600mv + 20% (720mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the controller remains off until the over- voltage condition is removed. at this point a hiccup delay cycle initiates and the part will re-start. there is a 5s delay built into the ovp detector to prevent false transi- tions. pgood is also low after an ovp event. output under-voltage protection when v fb falls 25% below its nominal voltage (falls to 450mv) for eight consecutive clock cycles, the switcher is shut off and the dh and dl drives are pulled low to tri- state the mosfets and enters hiccup mode. hiccup cycling and automatic fault recovery the sc9301 includes an automatic recovery feature (hiccup mode upon fault). if the switcher output is shut down due to a fault condition, the device will use the ss capacitor as a timer. upon fault shutdown the ss pin is pulled low, and then will begin charging through the internal 3a current source. when the ss capacitor reaches 67% of vdd, the ss pin is again pulled low, after which the ss capacitor begins another charging cycle. the ss capacitor will be used for 15 cycles of charging from 0 to 67% of vdd. during this time, the switcher is off and there is no mosfet switching. during the 16th ss cycle, a normal soft-start cycle is imple- mented and the mosfets will start a switching cycle. switching continues until the soft-start delay time is reached. if the switcher output is still in a fault condition, the switcher will shut down again and wait another fi fteen soft-start cycles before attempting the next soft-start. the long delay between soft-start cycles reduce average power loss in the power components. vdd uvlo and por the vdd under-voltage lock-out (uvlo) circuitry inhibits switching and tri-states the dh/dl drivers until vdd rises above 2.5v. when vdd exceeds 2.5v, an internal por (power-on reset) resets the fault latch and the soft-start circuitry and then the sc9301 begins the soft-start cycle. the switcher will shut off if vdd falls below 2.4v. ldo regulator when the ldo is providing bias power to the device, a minimum 0.1f capacitor referenced to agnd is required, along with a minimum 1f capacitor referenced to pgnd to fi lter the gate drive pulses. refer to the pcb layout guidelines section. enl pin and vin uvlo the enl pin also acts as the v in under-voltage lockout for the switcher. the v in uvlo voltage is programmable via a resistor divider at the vin, enl and agnd pins. timing is important when driving enl with logic and not implementing v in uvlo. the enl pin must transition from high to low within 2 switching cycles to avoid the pwm output turning off . if enl goes below the v in uvlo thresh- old and stays above 1v, then the switcher will turn off but the ldo will remain on. the next table summarizes the function of the enl and en pins, with respect to the rising edge of enl. en enl ldo status switcher status low low, < 0.4v off off high low, < 0.4v off on low high, < 1.57v on off high high, < 1.57v on off low high, > 1.57v on off high high, > 1.57v on on figure 7 shows the enl voltage thresholds and their eff ect on ldo and switcher operation. applications information (continued)
sc9301 18 agnd enl low threshold (min 0.4v) 1.57v 1.57v ldo on ldo on ldo off vin uvlo hysteresis enl voltage switcher on if en = high switcher on if en = high switcher off by vin uvlo figure 7 enl thresholds enl logic control of pwm operation when the enl input exceeds the vin uvlo threshold of 1.57v, internal logic checks the pgood signal. if pgood is high, the switcher is already running and the ldo will start without aff ecting the switcher. if pgood is low, the device disables pwm switching until the ldo output has reached 90% of its fi nal value. this delay prevents the additional current needed by the dh and dl gate drives from overloading the ldo at start-up. ldo start-up before ldo start-up, the device checks the status of the following signals to ensure proper operation can be maintained. enl pin vldo output v in input voltage when the enl pin is high and v in is available, the ldo will begin start-up. during the initial phase, when vldo is below 1v, the ldo initiates a current-limited start-up (typically 20ma). this protects the ldo from thermal damage if the v ldo is shorted to ground. as v ldo exceeds 1v, the start-up current gradually increases to 115ma. when v ldo reaches 4.5v, the ldo current limit is increased to 200ma and the ldo output rises quickly to 5.0v. the ldo start-up is shown in figure 8. 1. 2. 3. 5v 4.5v 20ma constant current voltage regulating with 200ma current limit 1.0v vldo increasing current figure 8 ldo start-up using the internal ldo to bias the sc9301 the following steps must be followed when using the internal ldo to bias the device. connect vdd to vldo before enabling the ldo. during the initial start-up the ldo, when the ldo output is less than 1v, the external load should not exceed 20ma. above 1v, any exter- nal load on vldo should not exceed 115ma until the ldo voltage has reached 90% of fi nal value. ? ? applications information (continued)
sc9301 19 design procedure when designing a switch mode supply the input voltage range, load current, switching frequency, and inductor ripple current must be specifi ed. the maximum input voltage (v inmax ) is the highest specifi ed input voltage. the minimum input voltage ( v inmin ) is deter- mined by the lowest input voltage including the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters defi ne the design. nominal output voltage (v out ) static or dc output tolerance transient response maximum load current (i out ) there are two values of load current to evaluate con- tinuous load current and peak load current. continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and fi ltering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design. v in = 12v + 10% and ldo bias v out = 1.5v + 3% f sw = 300khz load = 10a maximum frequency selection selection of the switching frequency requires making a trade-off between the size and cost of the external fi lter components (inductor and output capacitor) and the power conversion effi ciency. the desired switching frequency is 300khz which results from using components selected for optimum size and cost. a resistor, r ton is used to program the on-time (indirectly setting the frequency) using the following equation. ? ? ? ? ? ? ? ? sw ton f pf 75 . 26 k r u substituting for r ton results in the following solution. r ton = 124.6k inductor selection in order to determine the inductance, the ripple current must fi rst be defi ned. low inductor values result in smaller size but create higher ripple current which can reduce effi ciency. higher inductor values will reduce the ripple current/voltage and for a given dc resistance are more effi cient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and effi ciency are all used in the selection process. the ripple current will also set the boundary for power- save operation. the switching will typically enter power- save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4a then power-save operation will typically start for loads less than 2a. if ripple current is set at 40% of maximum load current, then power-save will start for loads less than 20% of maximum current. the inductor value is typically selected to provide a ripple current that is between 25% to 50% of the maximum load current. this provides an optimal trade-off between cost, effi ciency, and transient performance. during the dh on-time, voltage across the inductor is (v in - v out ). the following equation for determining induc- tance is shown. ripple on out in i t ) v v ( l u example in this example, the inductor ripple current is set equal to 35% of the maximum load current. therefore ripple current will be 35% x 10a or 3.5a. to fi nd the minimum inductance needed, use the v in and t on values that corre- spond to v inmax . applications information (continued)
sc9301 20 applications information (continued) sw inmax out on f v v t u t on = 379 ns at 13.2v in , 1.5v out , 300khz h 27 . 1 a 5 . 3 ns 379 ) 5 . 1 2 . 13 ( l p u a slightly smaller value of 1.2h is selected. this will increase the maximum i ripple to 3.7a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. ns 451 v v r pf 25 t inmin out ton vinmin _ on u u l t ) v v ( i on out in ripple u a 5 . 3 h 2 . 1 ns 451 ) 5 . 1 8 . 10 ( i vinmin _ ripple p u capacitor selection the output capacitors are chosen based upon required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to- peak ripple. a change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal for output voltage ripple is 2% of 1.5v or 30mv. the maximum esr value allowed is shown by the following equations. a 7 . 3 mv 30 i v esr ripplemax ripple max esr max = 8.1 m the output capacitance is usually chosen to meet tran- sient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the required capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1s), the output capacitor must absorb all the inductors stored energy. this will cause a peak voltage on the capacitor according to the following equation. 2 out 2 peak 2 ripplemax out min v v i 2 1 i l cout ? 1 ? u assuming a peak voltage v peak of 1.65v (150mv rise upon load release), and a 10a load release, the required capaci- tance is shown by the next equation. f 357 2 5 . 1 2 65 . 1 2 7 . 3 2 1 10 h 2 . 1 min cout p ? 1 ? u p during the load release time, the voltage cross the induc- tor is approximately -v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the di/dt of the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed capaci- tance for a given di load /dt. peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 10 + 1/2 x 3.7 = 11.85a dt dl current load of change of rate load i max = maximum load release = 10a out pk load max out lpk lpk out v v 2 dt dl i v i l i c u u u
sc9301 21 applications information (continued) example s 1 a 5 . 2 dt dl load p this would cause the output current to move from 10a to 0a in 4s, giving the minimum output capacitance requirement shown in the following equation. 5 . 1 65 . 1 2 s 1 5 . 2 10 5 . 1 85 . 11 h 2 . 1 85 . 11 c out p u u p u c out = 216 f note that c out is much smaller in this example, 216f compared to 357f based on a worst-case load release. to meet the two design criteria of minimum 357f and maximum 8.1m esr, select one capacitor of 330f and 6m esr. it is recommended that an additional small capacitor be placed in parallel with c out in order to fi lter high frequency switching noise. stability considerations unstable operation is possible with adaptive on-time con- trollers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the 250ns minimum off -time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not aff ect opera- tion. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripple signal that is at least 10mvp-p, which may dictate the need to increase the esr of the output capacitors. it is also impera- tive to provide a proper pcb layout as discussed in the layout guidelines section. another way to eliminate doubling-pulsing is to add a small capacitor across the upper feedback resistor, as shown in figure 9. this capacitor should be left unpopu- lated unless it can be confirmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional con- nection on the pcb should be available for this capacitor. v out to fb pin r2 r1 c top figure 9 capacitor coupling to fb pin esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking sta- bility is to apply a zero-to-full load transient and observe the output voltage ripple envelope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple way to solve this problem is to add trace resis- tance in the high current output path. a side eff ect of adding trace resistance is decreased load regulation. esr requirements a minimum esr is required for two reasons. one reason is to generate enough output ripple voltage to provide 10mvp-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insuffi - cient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and dis- charging during the switching cycle. for most applica- tions the minimum esr ripple voltage is dominated by the output capacitors, typically sp or poscap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third the switching fre- quency. the formula for minimum esr is shown by the following equation.
sc9301 22 applications information (continued) sw out min f c 2 3 sr e u u s u using ceramic output capacitors when the system is using high esr value capacitors, the feedback voltage ripple lags the phase node voltage by 90 degrees. therefore, the converter is easily stabilized. when the system is using ceramic output capacitors, the esr value is normally too small to meet the above esr cri- teria. as a result, the feedback voltage ripple is 180 degrees from the phase node and behaves in an unstable manner. in this application it is necessary to add a small virtual esr network that is composed of two capacitors and one resistor, as shown in figure 10. r 1 r 2 fb pin c c c out l c l r l dcr d x v in + - v l figure 10 virtual esr ramp circuit the ripple voltage at fb is a superposition of two voltage sources: the voltage across c l and output ripple voltage. they are defi ned in the following equations. 1 c r s ) 1 dcr / l s ( dcr i vc l l l l u u u sw l out f c 8 i v u ' ' figure 11 shows the magnitude of the ripple contribution due to c l at the fb pin. r 1 r 2 fb pin c c l c l r l dcr d x v in + - v l figure 11 fb voltage by cl voltage it is shown by the following equation. 1 c s r // r c s r // r vc vfbc c 2 1 c 2 1 l l u u u u u figure 12 shows the magnitude of the ripple contribution due to the output voltage ripple at the fb pin. r 1 r 2 fb pin c c c out l c l r l dcr v l v out r 1 r 2 v out c c fb pin c out figure 12 fb voltage by output voltage it is shown by the following equation. 2 c 1 2 out out r c s 1 // r r v v vfb u u ' ' the purpose of this network is to couple the inductor current ripple information into the feedback voltage such that the feedback voltage has 90 degrees phase lag to the switching node similar to the case of using standard high esr capacitors. this is illustrated in figure 13.
sc9301 23 applications information (continued) v out lx i l fb contribution by c l fb contribution by output voltage ripple combined fb figure 13 fb voltage in phasor diagram the magnitude of the feedback ripple voltage, which is dominated by the contribution from c l , is controlled by the value of r 1 , r 2 and c c . if the corner frequency of (r 1 // r 2 ) x c c is too high, the ripple magnitude at the fb pin will be smaller, which can lead to double-pulsing. conversely, if the corner frequency of (r 1 // r 2 ) x c c is too low, the ripple magnitude at fb pin will be higher. since the sc9301 regulates to the valley of the ripple voltage at the fb pin, a high ripple magnitude is undesirable as it signifi cantly impacts the output voltage regulation. as a result, it is desirable to select a corner frequency for (r 1 // r 2 ) x c c to achieve enough, but not excessive, ripple magnitude and phase margin. the component values for r 1 , r 2 , and c c should be calculated using the following procedure. select c l (typical 10nf) and r l to match with l and dcr time constant using the following equation. l l c dcr l r u select c c by using the following equation. sw 2 1 c f 2 3 r // r 1 c u s u u | the resistor values (r 1 and r 2 ) in the voltage divider circuit set the v out for the switcher. the typical value for c c is from 10pf to 1nf. dropout performance the output voltage adjust range for continuous-conduc- tion operation is limited by the fixed 250ns (typical) minimum off -time of the one-shot. when working with low input voltages, the duty-factor limit must be calcu- lated using worst-case values for on and off times. the duty-factor limitation is shown by the following equation. ) max ( off ) min ( on ) min ( on t t t duty the inductor resistance and mosfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors aff ect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator off set is trimmed so that under static condi- tions it trips when the feedback pin is 600mv, + 1%. the on-time pulse from the sc9301 in the design example is calculated to give a pseudo-fi xed frequency of 250khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because adaptive on-time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regu- lation error. for example, if the output ripple is 50mv with v in = 6 volts, then the measured dc output will be 25mv above the comparator trip point. if the ripple increases to 80mv with v in = 25v, then the measured dc output will be 40mv above the comparator trip. the best way to mini- mize this eff ect is to minimize the output ripple. to compensate for valley regulation, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capaci- tor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capaci- tance because the voltage excursions due to load steps are reduced as seen at the load. the use of 1% feedback resistors contributes up to 1% error. if tighter dc accuracy is required, 0.1% resistors should be used.
sc9301 24 applications information (continued) the output inductor value may change with current. this will change the output ripple and therefore will have a minor eff ect on the dc output voltage. the output esr also aff ects the output ripple and thus has a minor eff ect on the dc output voltage. switching frequency variations the switching frequency will vary depending on line and load conditions. the line variations are a result of fi xed propagation delays in the on-time one-shot, as well as unavoidable delays in the external mosfet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net eff ect is that frequency tends to falls slightly with increasing input voltage. the switching frequency also varies with load current as a result of the power losses in the mosfets and the induc- tor. for a conventional pwm constant-frequency con- verter, as load increases the duty cycle also increases slightly to compensate for ir and switching losses in the mosfets and inductor. a adaptive on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from v in as losses increase). because the on-time is essentially constant for a given v out /v in combination, to off set the losses the off -time will reduce slightly as load increases. the net effect is that switching frequency increases slightly with increasing load. pcb layout guidelines the optimum layout for the sc9301 is shown in figure 16. this layout shows an integrated fet buck regulator with a maximum current of 10a. the total pcb area is approxi- mately 25 x 29 mm with single side components. critical layout guidelines the following critical layout guidelines must be followed to ensure proper performance of the device. ic decoupling capacitors pgnd plane agnd island fb, vout, and other analog control signals c ss bst, ilim, and lx c in and c out placement and current loops ic decoupling capacitors a 1 f capacitor must be located as close as pos- sible to the ic and directly connected to pins 3 (vdd) and 4 (agnd). another 1 f capacitor must be located as close as possible to the ic and directly connected to pins 3 (vdd) and pgnd plane. pgnd plane pgnd requires its own copper plane with no other signal traces routed on it. copper planes, multiple vias and wide traces are needed to connect pgnd to input capacitors, output capacitors, and the pgnd pins on the ic. the pgnd copper area between the input capacitors, output capacitors and pgnd pins must be as tight and compact as possible to reduce the area of the pcb that is exposed to noise due to current fl ow on this node. agnd island agnd should have its own island of copper with no other signal traces routed on this layer that connects the agnd pins and pad of the ic to the analog control components. all of the components for the analog control cir- cuitry should be located so that the connections to agnd are done by wide copper traces or vias down to agnd. ? ? ? ? ? ? ? ? ? ? ? ? ? ?
sc9301 25 applications information (continued) connect pgnd to agnd with a short trace or 0 resistor. this connection should be as close to the ic as possible. fb, vout, and other analog control signals the connection from the v out power to the analog control circuitry must be routed from the output capacitors and located on a quiet layer. the traces between vout and the analog control circuitry (vout, and fb pins) must be wide, short and routed away from noise sources, such as bst, lx, vin, and pgnd between the input capacitors, output capacitors, and the ic. the feedback components for the switcher and the ldo need to be as close to the fb and fbl pins of the ic as possible to reduce the possibil- ity of noise corrupting these analog signals. bst, ilim,ton,ss and lx the connections for the boost capacitor between the bst and lxbst must be short, wide and directly connected. ilim and ton nodes must be as short as possible to ensure the best accuracy in current limit and on time. r ilim should be close to the ic and connected between lxs (pin 28) and ilim (pin 27) only. r ton should be close to the ic and connected between ton (pin 31) and agnd (pin 30). c soft should be close to the ic and kept away from the boost capacitor. connect the agnd end of c soft to the agnd plane at pin 4. the lx node between the ic and the inductor should be wide enough to handle the inductor current and short enough to eliminate the pos- sibility of lx noise corrupting other signals. multiple vias should be used on the lx pad to provide good thermals and connection to an internal or bottom layer lx plane. capacitors and current loops figure 14 shows the placement of input/output capacitors and inductor. this placement shows the smallest current loops between the input/ output capacitors, the sc9301 and the inductor to reduce the ir drop across the copper. ? ? ? ? ? ? ? ? ? ? ? ?
sc9301 26 applications information (continued) vout plane on top and bottom layer l c in css rfb2 rfb1 rilim cbst lx plane on top and bottom layer agnd plane on inner layer v in plane on top and/or bottom layer rgnd ? agnd connects to pgnd close to ic pin 1 marking ic with vias for lx, agnd, vin c out pgnd on inner or bottom layer vout sense trace on inner layer vdd decoupling capacitor vdd cer. c in sp or poscap rton ctop pgnd on top layer figure 14 pcb layout
sc9301 27 outline drawing mlpq-ut32 5x5 b aaa c c seating plane 1 2 n bbb c a b coplanarity applies to the exposed pad as well as the terminals. controlling dimensions are in millimeters (angles in degrees). notes: 2. 1. a pin 1 indicator (laser mark) d e a2 bxn a a1 e lxn e1 0.76 0.76 3.48 1.05 d1 1.66 1.49 pin 1 identification r0.20 3.61 millimeters 0.50 bsc .002 - 0.00 .000 a1 .193 .193 .135 .076 .012 .007 e1 aaa bbb n e l a2 d1 d e b .020 bsc .137 .016 .003 .004 32 .197 (.008) .078 .197 .010 - 3.43 .139 .020 0.30 .201 .201 .080 - .012 4.90 4.90 1.92 - 0.18 .031 min dim a max dimensions inches - nom .039 0.80 min - 0.05 5.10 5.10 3.53 2.02 0.50 0.30 3.48 0.40 0.10 0.08 32 5.00 (0.20) 1.97 5.00 0.25 - 1.00 max - nom
sc9301 28 land pattern mlpq-ut32 5x5 1.74 3.48 h2 k 3.61 h1 k1 y h (c) g this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 2. dim x y h k p c g millimeters inches (4.95) .012 .030 .165 .020 .078 .137 (.195) 0.30 0.75 3.48 0.50 1.97 4.20 dimensions company's manufacturing guidelines are met. 5.70 .224 z failure to do so may compromise the thermal and/or functional performance of the device. shall be connected to a system ground plane. thermal vias in the land pattern of the exposed pad 3. 4. square package-dimensions apply in both x and y directions. controlling dimensions are in millimeters (angles in degrees). 1. x p z h1 .059 1.49 h2 .065 1.66 k1 .041 1.05 1.74
sc9301 29 contact information semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax: (805) 498-3804 www.semtech.com ? semtech 2011 all rights reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any conse- quence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellec- tual property rights. semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specifi ed maximum ratings or operation outside the specifi ed range. semtech products are not designed, intended, authorized or warranted to be suitable for use in life- support applications, devices or systems or other critical applications. inclusion of semtech products in such applications is understood to be undertaken solely at the customers own risk. should a customer purchase or use semtech products for any such unauthorized application, the customer shall indemnify and hold semtech and its offi cers, employees, subsidiaries, affi liates, and distributors harmless against all claims, costs damages and attorney fees which could arise. notice: all referenced brands, product names, service names and trademarks are the property of their respective owners.

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