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sy89840u precision lvpecl runt pulse eliminator 2:1 multiplexer precision edge is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? te l +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com february 2005 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 general description the sy89840u is a low jitter pecl, 2:1 differential input multiplexer (mux) optimized for redundant source switchover applications. un like standard multiplexers, the sy89840u unique 2:1 runt pulse eliminator (rpe) mux prevents any short cycles or ?runt? pulses during switchover. in addition, a unique fail-safe input protection prevents metast able conditions when the selected input clock fails to a dc voltage (voltage between the pins of the differential input drops below 100mv). the differential input includes micrel?s unique, 3-pin input termination architecture that allows customers to interface to any differential signal (ac or dc-coupled) as small as 100mv (200mv pp ) without any level shifting or termination resistor network s in the signal path. the output is 800mv, 100k comp atible lvpecl with fast rise/fall times guaranteed to be less than 190ps. the sy89840u operates from a 2.5v 5% or 3.3v 10% supply and is guaranteed over the full industrial temperature range of ?40c to +85c. the sy89840u is part of micrel?s high-speed, precision edge ? product line. all support documentation can be found on micrel?s web site at: www.micrel.com . precision edge ? features ? selects between two sources, and provides a glitch-free, stable lvpecl output ? guaranteed ac performance over temperature and supply voltage: ? wide operating frequency: 1khz to >1.5ghz ? < 880ps in-to-out t pd ? < 190ps t r /t f ? unique patent-pending input isolation design minimizes crosstalk ? fail-safe input prevents oscillations ? ultra-low jitter design: ? <1ps rms random jitter ? <1ps rms cycle-to-cycle jitter ? <10ps pp total jitter (clock) ? <0.7ps rms mux crosstalk induced jitter ? unique patent-pending input termination and vt pin accepts dc-coupled and ac-coupled inputs (cml, pecl, lvds) ? 800mv lvpecl output swing ? 2.5v 5% or 3.3v 10% supply voltage ? ?40c to +85c industrial temperature range ? available in 16-pin (3mm x 3mm) qfn package applications ? redundant clock switchover ? failsafe clock protection markets ? lan/wan ? enterprise servers ? ate ? test and measurement
micrel, inc. sy89840u february 2005 2 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 typical application simplified example illustrating rpe (runt pulse elimination) circuit when primary clock fails
micrel, inc. sy89840u february 2005 3 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 ordering information (1) part number package type operating range package marking lead finish sy89840umg qfn-16 industrial 840u with bar-line pb-free indicator nipdau pb-free sy89840umgtr (2) qfn-16 industrial 840u with bar-line pb-free indicator nipdau pb-free notes: 1. contact factory for die availability. dice are guaranteed at t a = 25c, dc electricals only. 2. tape and reel. pin configuration 16-pin qfn
micrel, inc. sy89840u february 2005 4 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 pin description pin number pin name pin function 4, 1, 16, 13 in0, /in0, in1, /in1 differential inputs: these input pairs are the differential signal inputs to the device. these inputs accept ac or dc-coupled signals as small as 100mv (200mv pp ). each pin of a pair internally terminates to a vt pin through 50 ? . please refer to the ?input interface ap plications? section for more details. 3, 15 vt0, vt1 input termination center-tap: each side of the differential input pair terminates to a vt pin. the vt0 and vt1 pins prov ide a center-tap to a termination network for maximum interface flexibility. see the ?input interface applications? section for more details. 2, 14 vref-ac0 vref-ac1 reference voltage: this output biases to v cc ?1.2v. it is used for ac-coupling inputs in and /in. connect vref-ac directly to the corresponding vt pin. bypass with 0.01f low esr capacitor to v cc . maximum sink/source current is 1.5ma. due to the limited drive capability, the vr ef-ac pin is only intended to drive its respective vt pin. see ?input interface applications? section. 10 sel this single-ended ttl/cmos-compatible input selects the inputs to the multiplexer. note that this inpu t is internally connected to a 25k ? pull-up resistor and will default to a logic high state if left open. 5, 8, 12 vcc positive power supply: bypass with 0.1f//0.01f low esr capacitors as close to vcc pins as possible. 6, 7 q, /q differential outputs: this differential lvpec l output is a logic f unction of the in0, in1, and sel inputs. please refer to the truth table below for details. 9 gnd exposed pad ground: ground pin and exposed pad must be connected to the same ground plane. 11 cap power-on reset (por) initialization capacitor. when using the multiplexer with rpe capability, this pin is tied to a capacitor to v cc . the purpose is to ensure the internal rpe logic starts up in a known state. see "power-on reset (por) description" section for more details regar ding capacitor selection. if this pin is tied directly to v cc , the rpe function will be disabled and the multiplexer will function as a normal multiplexer. the cap pin should never be left open. truth table inputs outputs in0 /in0 in1 /in1 sel q /q 0 1 x x 0 0 1 1 0 x x 0 1 0 x x 0 1 1 0 1 x x 1 0 1 1 0
micrel, inc. sy89840u february 2005 5 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc ).............................................. ?0.5v to +4.0v input voltage (v in ) ......................................................?0.5v to v cc lvpecl output current (i out ) continuou s ......................................................... 50ma surge................................................................ 100ma termination current source/sink current on v t ........................................ 100ma source/sink current on in, /in .................................... 50ma v ref-ac current source/sink current on v ref-ac ...................................... 2ma lead temperature (solde ring, 20 sec. ) ..............................+ 260c storage temperature (ts).................................... ?65c to 150 c operating ratings (2) supply voltage (v cc ) .............................+2.375v to +2.625v .............................................................. +3.0v to +3.6v ambient temperature (t a )........................... ?40c to +85c package thermal resistance (3) qfn ( ja ) still-ai r ............................................................... 60c/w qfn ( jb ) junction-to- board .............................................. 33c/w dc electrical characteristics (4) t a = ?40c to +85c; unless otherwise stated. symbol parameter condition min typ max units v cc power supply 2.375 3.0 2.625 3.6 v v i cc power supply current no load, max v cc . 65 95 ma r in input resistance (in-to-v t ) 45 50 55 ? r diff_in differential input resistance (in-to-/in) 90 100 110 ? v ih input high voltage (in, /in) 1.2 v cc v v il input low voltage (in, /in) 0 v ih ?0.1 v v in input voltage swing (in, /in) see figure 1a. note 5 0.1 v cc v v diff_in differential input voltage swing |in-/in| see figure 1b. 0.2 v v in_fsi input voltage threshold that triggers fsi 30 100 mv v t_in in-to-v t (in, /in) 1.28 v v ref-ac output reference voltage v cc ?1.3 v cc ?1.2 v cc ?1.1 v notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those deta iled in the operational sections of this data sheet. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. package thermal resistance assumes exposed pad is soldered (o r equivalent) to the devices most negative potential on the pcb . ja and jb values are determined for a 4-layer board in still air unless otherwise stated. 4. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d. 5. v in (max) is specified when v t is floating.
micrel, inc. sy89840u february 2005 6 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 lvpecl outputs dc electrical characteristics (6) v cc = 2.5v 5% or 3.3v 10%; t a = -40c to + 85c; r l = 50 ? to v cc -2v, unless otherwise stated. symbol parameter condition min typ max units v oh output high voltage q, /q v cc -1.145 v cc ?0.895 v v ol output low voltage q, /q v cc -1.945 v cc ?1.695 v v out output voltage swing q, /q see figure 1a 550 800 mv v diff-out differential output voltage swing q, /q see figure 1b 1100 1600 mv lvttl/cmos dc electri cal characteristics (6) v cc = 2.5v 5% or 3.3v 10%; t a = -40c to + 85c, unless otherwise stated. symbol parameter condition min typ max units v ih input high voltage 2.0 v v il input low voltage 0.8 v i ih input high current -125 30 a i il input low current -300 a note: 6. the circuit is designed to meet the dc specifications shown in the above table after thermal equilibrium has been establishe d.
micrel, inc. sy89840u february 2005 7 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics (7) v cc = 2.5v 5% or 3.3v 10%; t a = ?40c to + 85c, r l = 50 ? to v cc ?2v, unless otherwise stated. symbol parameter condition min typ max units f max maximum operating frequency clock 1.5 2.0 ghz 100mv < v in 200mv (8) 480 625 880 ps 200mv < v in 800mv (8) 460 600 820 ps rpe enabled, see timing diagram 17 cycles t pd differential propagation delay in-to-q in-to-q sel-to-q sel-to-q rpe disabled (v in = v cc /2) 550 900 ps t pd tempco differential propagation delay temperature coefficient 115 fs/ o c t skew part-to-part skew note 9 200 ps note 10 1 ps (rms) note 11 1 ps (rms) random jitter cycle-to-cycle jitter total jitter (tj) note 12 10 ps (pp) t jitter crosstalk-induced jitter note 13 0.7 ps (rms) t r, t f output rise/fall time (20% to 80%) at full output swing 70 130 190 ps notes: 7. high-frequency ac-parameters are guar anteed by design and characterization. 8. propagation delay is measured with input t r , t f 300ps (20% to 80%) and v il 800mv. 9. part-to-part skew is defined for two parts with identical pow er supply voltages at the same temperature and with no skew of the edges at the respective inputs. 10. random jitter is measured with a k 28.7 character pattern, measured at micrel, inc. sy89840u february 2005 8 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 functional description rpe mux and fail-safe input the sy89840u is optimized for clock switchover applications where switching from one clock to another clock without runt pulses (short cycles) is required. it features two unique circuits: runt-pulse eliminator (rpe) circuit: the rpe mux provides a ?glitchless? switchover between two clocks and prevents any runt pulses from occurring during the switchover transition. the design of both clock inputs is identical (i.e., the switchover sequence and protection is symmetrical for both input pair, in0 or in 1. thus, either input pair may be defined as the primary input). if not required, the rpe function can be permanently disabled to allow the switchover between inputs to occur immediately. if the cap pin is tied directly to v cc , the rpe function will be disabled and the multiplexer will function as a normal multiplexer. fail-safe input (fsi) circuit: the fsi function provides protection against a selected input pair that drops below the minimum amplitude requirement. if the selected input pair drops sufficiently below the 100mv minimum single- ended input amplitude limit (v in ), or 200mv differentially (v diff_in ), the output will latch to the last valid clock state. rpe and fsi functionality the basic operation of the rpe mux and fsi functionality is described with the following four case descriptions. all descriptions are related to the true inputs and outputs. the primary (or selected) clock is called clk1; the secondary (or alternate) clock is called clk2. due to the totally asynchronous relation of the in and sel signals and an additional internal protection agains t metastability, the number of pulses required for the operations described in cases 1-4 can vary within certain limits. refer to ?timing diagrams? for more detailed information. case #1 two normal clocks and rpe enabled in this case the frequency difference between the two running clocks in0 and in1 must not be greater than 1.5:1. for example, if the in0 clock is 500mhz, the in1 clock must be within the range of 334mhz to 750mhz. if the sel input changes state to select the alternate clock, the switchov er from clk1 to clk2 will occur in three stages. ? stage 1: the output will continue to follow clk1 for a limited number of pulses. ? stage 2: the output will remain low for a limited number of pulses of clk2. ? stage 3: the output follows clk2. timing diagram 1
micrel, inc. sy89840u february 2005 9 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 case #2 input clock failure: switching from a selected clock stuck high to a valid clock (rpe enabled). if clk1 fails high before the rpe mux selects clk2 (using the sel pin), the switchover will occur in three stages. ? stage 1: the output will remain high for a limited number of pulses of clk2. ? stage 2: the output will switch to low and then remain low for a limited number of falling edges of clk2. ? stage 3: the output will follow clk2 timing diagram 2 note: output shows extended clock cycle during switchover. pulse width for both high and low of this cycle will always be greater tha n 50% of the clk2 period. case #3 input clock failure: switching from a selected clock stuck low to a valid clock (rpe enabled). if clk1 fails low before the rpe mux selects clk2 (using the sel pin), the switchover will occur in two stages. ? stage 1: the output will remain low for a limited number of falling edges of clk2. ? stage 2: the output will follow clk2. timing diagram 3
micrel, inc. sy89840u february 2005 10 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 case #4 input clock failure: switching from the selected clock input stuc k in an undetermined state to a valid clock input (rpe enabled). if clk1 fails to an undetermined state (e.g., amplitude falls below the 100mv (v in ) minimum single-ended input limit, or 200mv differentially) before the rpe mux selects clk2 (using the sel pin), the switchover to the valid clock clk2 will occur either following case #2 or case #3, depending on the last valid state at the clk1. if the selected input clock fails to a floating, static, or extremely low signal swing, including 0mv, the fsi function will eliminate any metastable condition and guarantee a stable output signal. no ringing and no undetermined state will occur at the output under these conditions. please note that the fsi function will not prevent duty cycle distortions or runt pulses in case of a slowly deteriorating (but still toggling) input signal. due to the fsi function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. refer to ?typical operating characteristics? for more detailed information. timing diagram 4 power-on reset (por) description the sy89840u includes an internal power-on reset (por) function to ensure the rpe logic starts-up in a known logic state once the power-supply voltage is stable. an external capacitor connected between v cc and the cap pin (pin 11) controls the delay for the power-on reset function. calculation of the required capacitor value is based on the time the system power supply needs to power up to a minimum of 2.3v. the time constant for the internal power-on-reset must be greater than the time required for the power supply to ramp up to a minimum of 2.3v. the following equation describes this relationship: as an example, if the time required for the system power supply to power up past 2.3v is 12ms, the required capacitor value on pin 11 would be: c( f) ) / ( 12 ) ( f ms ms t dps c( f) ) / ( 12 12 f ms ms c( f) f 1
micrel, inc. sy89840u february 2005 11 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 3.3v, gnd = 0v, v in 400mv pk , t r /t f 300ps, r l = 50 ? to v cc ?2v, t a = 25c, unless otherwise stated.
micrel, inc. sy89840u february 2005 12 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 singled-ended and differential swings figure 1a. single-ended voltage swing figure 1b. differential voltage swing input and output stages figure 2a. simplified differential input stage figure 2b. simplified lvpecl output stage
micrel, inc. sy89840u february 2005 13 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 input interface applications figure 3a. lvpecl interface (dc-coupled) figure 3b. lvpecl interface (ac-coupled) option: may connect v t to v cc figure 3c. cml interface (dc-coupled) figure 3d. cml interface (ac-coupled) figure 3e. lvds interface
micrel, inc. sy89840u february 2005 14 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 lvpecl output interface applications lvpecl has a high input impedance, a very low output impedance (open emitter), and a small signal swing which results in low emi. lvpecl is ideal for driving 50 and 100 controlled impedance transmission lines. there are several techniques for terminating the lvpecl output: parallel termination-thevenin equivalent, parallel termination (3-resistor), and ac-coupled termination. unused output pairs may be left floating. however, single-ended outputs must be terminated, or balanced. figure 4a. parallel termination-thevenin equipment figure 4b. parallel termination (3-resistor) part number function data sheet link sy89841u precision lvds runt pulse eliminator 2:1 multiplexer www.micrel.com/product-info/products/sy89841u.shtml sy89842u precision cml runt pulse eliminator 2:1 multiplexer www.micrel.com/product-info/products/sy89842u.shtml hbw solutions new products and applications www.m icrel.com/product-info/products/solutions.shtml
micrel, inc. sy89840u february 2005 15 m9999-021705 hbwhelp@micrel.com or (408) 955-1690 qfn - 16 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to resul t in a significant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support applianc es, devices or systems is a pu rchaser?s own risk and purchaser agrees to fully indemnify micrel fo r any damages resulting from such use or sale. ? 2005 micrel, incorporated.

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