? semiconductor components industries, llc, 2002 may, 2002 rev. 2 1 publication order number: mmbta55lt1/d mmbta55lt1, mmbta56lt1 mmbta56lt1 is a preferred device driver transistors pnp silicon maximum ratings rating symbol value unit collectoremitter voltage mmbta55 mmbta56 v ceo 60 80 vdc collectorbase voltage mmbta55 mmbta56 v cbo 60 80 vdc emitterbase voltage v ebo 4.0 vdc collector current continuous i c 500 madc thermal characteristics characteristic symbol max unit total device dissipation fr5 board (note 1) t a = 25 c derate above 25 c p d 225 1.8 mw mw/ c thermal resistance, junction to ambient r ja 556 c/w total device dissipation alumina substrate, (note 2) t a = 25 c derate above 25 c p d 300 2.4 mw mw/ c thermal resistance, junction to ambient r ja 417 c/w junction and storage temperature t j , t stg 55 to +150 c 1. fr5 = 1.0 0.75 0.062 in. 2. alumina = 0.4 0.3 0.024 in. 99.5% alumina. device package shipping ordering information mmbta55lt1 sot23 sot23 case 318 style 6 3000/tape & reel 2 3 1 preferred devices are recommended choices for future use and best overall value. marking diagrams 2h x mmbta55lt1 collector 3 1 base 2 emitter 2gm x mmbta56lt1 mmbta55lt3 sot23 10,000/tape & reel http://onsemi.com 2h, 2gm = specific device code x = date code mmbta56lt1 sot23 3000/tape & reel mmbta56lt3 sot23 10,000/tape & reel
mmbta55lt1, mmbta56lt1 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics collectoremitter breakdown voltage (note 3) (i c = 1.0 madc, i b = 0) mmbta55 mmbta56 v (br)ceo 60 80 vdc emitterbase breakdown voltage (i e = 100 adc, i c = 0) v (br)ebo 4.0 vdc collector cutoff current (v ce = 60 vdc, i b = 0) i ces 0.1 adc collector cutoff current (v cb = 60 vdc, i e = 0) mmbta55 (v cb = 80 vdc, i e = 0) mmbta56 i cbo 0.1 0.1 adc on characteristics dc current gain (i c = 10 madc, v ce = 1.0 vdc) (i c = 100 madc, v ce = 1.0 vdc) h fe 100 100 collectoremitter saturation voltage (i c = 100 madc, i b = 10 madc) v ce(sat) 0.25 vdc baseemitter on voltage (i c = 100 madc, v ce = 1.0 vdc) v be(on) 1.2 vdc smallsignal characteristics currentgain bandwidth product (note 4) (i c = 100 madc, v ce = 1.0 vdc, f = 100 mhz) f t 50 mhz 3. pulse test: pulse width 300 s, duty cycle 2.0%. 4. f t is defined as the frequency at which |h fe | extrapolates to unity. figure 1. switching time test circuits output turn-on time -1.0 v v cc +40 v r l * c s 6.0 pf r b 100 100 v in 5.0 f t r = 3.0 ns 0 +10 v 5.0 s output turn-off time +v bb v cc +40 v r l * c s 6.0 pf r b 100 100 v in 5.0 f t r = 3.0 ns 5.0 s *total shunt capacitance of test jig and connectors for pnp test circuits, reverse all voltage polarities
mmbta55lt1, mmbta56lt1 http://onsemi.com 3 figure 2. currentgain e bandwidth product figure 3. capacitance figure 4. switching time i c , collector current (ma) -100 -200 -10 200 100 70 50 20 v r , reverse voltage (volts) -1.0 -100 -0.1 100 70 50 30 20 10 -2.0 v ce = -2.0 v t j = 25 c f t , current-gain - bandwidth product (mhz) c, capacitance (pf) -2.0 -3.0 -5.0 -7.0 -20 -30 -50 -70 30 7.0 5.0 -0.2 -0.5 -5.0 -10 -20 -50 t j = 25 c c ibo c obo i c , collector current (ma) -10 -5.0 500 200 100 50 20 10 -100 t, time (ns) -50 -200 -500 1.0 k 300 700 70 30 -7.0 -300 -70 -20 -30 v cc = -40 v i c /i b = 10 i b1 = i b2 t j = 25 c t s t f t r t d @ v be(off) = -0.5 v figure 5. dc current gain -2.0 -500 -0.5 i c , collector current (ma) 400 200 100 80 60 40 -10 , dc current gain t j = 125 c -1.0 -5.0 v ce = -1.0 v -20 -100 -50 -200 h fe 25 c -55 c figure 6. aono voltages v, voltage (volts) -10 -500 -1.0 i c , collector current (ma) -1.0 -0.8 -0.6 -0.4 -0.2 0 -100 t j = 25 c v be(sat) @ i c /i b = 10 v ce(sat) @ i c /i b = 10 v be(on) @ v ce = -1.0 v -0.5 -2.0 -5.0 -200 -20 -50
mmbta55lt1, mmbta56lt1 http://onsemi.com 4 figure 7. collector saturation region figure 8. baseemitter temperature coefficient i c , collector current (ma) i b , base current (ma) r vb , temperature coefficient (mv/ c) , collector-emitter voltage (volts) v ce -100 -500 -0.5 -0.8 -1.2 -1.6 -2.0 -2.4 -2.8 -10 r vb for v be -1.0 -2.0 -5.0 -20 -50 -200 -0.1 -10 -0.05 -1.0 -0.8 -0.6 -0.4 -0.2 0 -1.0 t j = 25 c -50 i c = -100 ma i c = -50 ma i c = -250 ma i c = -500 ma i c = -10 ma -20 -2.0 -5.0 -0.2 -0.5
mmbta55lt1, mmbta56lt1 http://onsemi.com 5 information for using the sot23 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. sot23 mm inches 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 sot23 power dissipation the power dissipation of the sot23 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sot23 package, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 225 milliwatts. p d = 150 c 25 c 556 c/w = 225 milliwatts the 556 c/w for the sot23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. there are other alternatives to achieving higher power dissipation from the sot23 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling. * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
mmbta55lt1, mmbta56lt1 http://onsemi.com 6 package dimensions case 31808 issue ah sot23 (to236) d j k l a c b s h g v 3 1 2 dim a min max min max millimeters 0.1102 0.1197 2.80 3.04 inches b 0.0472 0.0551 1.20 1.40 c 0.0350 0.0440 0.89 1.11 d 0.0150 0.0200 0.37 0.50 g 0.0701 0.0807 1.78 2.04 h 0.0005 0.0040 0.013 0.100 j 0.0034 0.0070 0.085 0.177 k 0.0140 0.0285 0.35 0.69 l 0.0350 0.0401 0.89 1.02 s 0.0830 0.1039 2.10 2.64 v 0.0177 0.0236 0.45 0.60 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. 318-03 and -07 obsolete, new standard 318-08. style 6: pin 1. base 2. emitter 3. collector
mmbta55lt1, mmbta56lt1 http://onsemi.com 7 notes
mmbta55lt1, mmbta56lt1 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mmbta55lt1/d thermal clad is a registered trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
|
