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ks57c 5616/p5616 product overview 1- 1 1 product overview overview the ks57c5616/p5616 single-chip cmos microcontroller is designed for high performance in the application for caller-id, telephone using samsung's newest 4 -bit cpu core, sam47 (samsung arrangable microcontrollers). featuring a dtmf generator, up-to-960-dot lcd direct drive capability, one 8-bit timer/counter and flexible two 8-bit timer/counters, and serial i/o interface, the ks57c5616/p5616 offer an excellent design solution for a wide variety of applications requiring dtmf, lcd support. up to 43 (including com/seg) pins in the 100-pin qfp package can be dedicated to i/o. nine vectored interrupts provide a fast response to internal and external events. in addition the advanced cmos technology a of the ks57c5616/p5616 ensures low power consumption with a wide operating voltage range. otp the ks57c5616 microcontroller is also available in otp (one time programmable) version, KS57P5616. KS57P5616 microcontroller has an on-chip 16k-byte one-time-programmable eprom instead of masked rom. the KS57P5616 is comparable to ks57c5616, both in function and in pin configuration.
product overview ks57c 5616/p5616 1 - 2 features summary memory ? 16k 8 -bit r o m ? 5,120 4 -bit r a m (excluding lcd ram) i/o pins ? input only: 4pins (not including com/seg) 6pins (including com/seg) ? i/o: 15pins (not i ncluding com/seg) 43pins (including com/seg) memory-mapped i/o structure ? data memory bank 15 8-bit basic timer ? four in terval timer functions ? watchdog timer 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider 16-bit timer/counter ? programmable 16-bit timer ? external event counter ? arbitrary clock frequency output ? external clock sig nal divider ? configurable as two 8-bit timers ? serial i/o interface clock generator watch timer ? time interval generation: 0.5 s, 3.9 ms at 32 . 768 k hz ? 4 frequency outputs to buz pin (0.5, 1, 2, 4 khz) at 32.768 khz comparator ? 4-channel mode: internal reference (4-bit resolution); 16-step variable reference voltage ? 3-channel mode: external reference dtmf generator ? 16 dual-tone for tone dialing 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first t ransmission selectable lcd controller/driver ? 60 seg x 16 com terminals ? 8, 12 and 16 com selectable ? com 8?15: shared with port ? seg40?59: shared with port ? two kinds of lcd bias resistor value bit sequential carrier ? supports 16-bit serial data transfer in arbitrary format interrupts ? four external interrupt vectors ? five internal interrupt vectors ? two quasi-interrupts power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) ? subsystem clock stop mode oscillation sources ? rc, crystal or ceramic for system clock ? oscillation frequency: 0.4?6.0 mhz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 1.12, 2.23, 17.88 s at 3.58 mhz ? 0. 67 , 1. 33 , 1 0.7 s at 6.0 mhz ? 122 s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v (except dtmf and comparator) ? 2 v to 5.5 v (include dtmf) ? 4.0 v to 5.5 v (include comparator) package type ? 100-pin qfp (1420c)
ks57c 5616/p5616 product overview 1- 3 block diagram program status word stack pointer arithmetic and logic unit instruction dcoder internal interrupts reset interrupt control block instruction register clock program counter p5.0-p5.3/ com12-com15 p4.0-p4.3/ com8-com11 i/o port 5 i/o port 4 comparator p7.0/seg55/cin0 p7.1/seg54/cin1 p7.2/seg53/cin2 p7.3/seg52/cin3 i/o port 2 p2.0/clo p2.1/vlc1 p2.2 i/o port 3 p3.0/tclo0 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 p6.0-p6.3 seg59-seg56/ ks4-ks7 p7.0/seg55/cin0 p7.1/seg54/cin1 p7.2/seg53/cin2 p7.3/seg52/cin3 i/o port 7 i/o port 6 p9.0-p9.3/ seg47-seg44 p8.0/seg51/lcdck p8.1/seg50/lcdsy p8.2/seg49 p8.3/seg48 i/o port 8 i/o port 9 i/o port 10 p10.0-p10.3/ seg43-seg40 8-bit timer/ counter 16kb rom 5k x 4-bit ram 16-bit timer/counter (two 8bit timer/counter) dtmf generator dtmf basic timer watchdog timer vlc1 com0-com7 p4.0-p5.3/ com8-com15 seg0-seg39 p10.3-p6.0/ seg40-seg59 lcd driver/ controller p0.0/ sck /ko p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 watch timer serial i/o i/o port 0 xt out x out xt in x in input port 1 p1.0-p1.3/ int0-int4 figure 1 -1 . ks57c5616 block diagram
product overview ks57c 5616/p5616 1 - 4 pin assignments seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 com0 com1 com2 com3 com4 com5 com6 com7 p4.0/com8 p4.1/com9 p4.2/com10 p4.3/com11 p5.0/com12 p5.1/com13 p5.2/com14 p5.3/com15 p6.0/seg59/k4 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 p10.3/seg40 p10.2/seg41 p10.1/seg42 p10.0/seg43 p9.3/seg44 p9.2/seg45 p9.1/seg46 p9.0/seg47 p8.3/seg48 p8.2/seg49 p8.1/seg50/lcdsy p8.0/seg51/lcdck p7.3/seg52/cin3 p7.2/seg53/cin2 p7.1/seg54/cin1 p7.0/seg55/cin0 p6.3/seg56/k7 p6.2/seg57/k6 p6.1/seg58/k5 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 dtmf p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd v ss x out x in test xt in xt out reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/clo p2.1/vlc1 p2.2 p3.0/tclo0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 ks57c5616 (100-qfp-1420c) figure 1 -2 . ks57c5616 pin assignments (100-qfp package)
ks57c 5616/p5616 product overview 1- 5 pin descriptions table 1 - 1. ks57c5616 pin descriptions pin name pin type description share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. sck /k0 so/k1 si/k2 buz/k3 p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 4 -bit pull-up resistors are software assignable . int0 int1 int2 int4 p2.0 p2.1 p2.2 i/o same as port 0 except that port 2 is a 3-bit i/o port. clo vlc1 p3.0 p3.1 p3.2 p3.3 i/o same as port 0 . tclo0 tclo1 tcl0 tcl1 p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. 1-, 4-bit or 8-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. com8?com11 com12?com15 p6.0?p6.3 p7.0?p7.3 i/o same as p4, p5. seg5 9 ? seg5 6 /k 4-k 7 seg5 5/cin0 ? seg 52/cin3 p8. 0 ?p8. 1 i/o input ports. 1-, 4-bit or 8-bit read and test is possible. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. these pins can not be used as push-pull output. refer to the notes of table 10-3. port mode group flags. seg 51/lcdck seg50/lcdsy p8. 2 ?p8.3 p9.0?p9.3 i/o same as p4, p5. seg4 9 seg48 seg47 ? seg44 p10.0?p10.3 i/o same as p4, p5. seg43?seg40 sck i/o serial i/o interface clock signal . p0.0/k0 so i/o serial data output . p0.1/k1
product overview ks57c 5616/p5616 1 - 6 table 1 - 1. ks57c5616 pin descriptions (continued) pin name pin type description share pin si i/o serial data input . p0.2/k2 buz i/o 0.5, 1, 2, or 4 khz frequency output for buzzer sound. p0.3/k3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. p1.0, p1.1 int2 i quasi-interrupt with detection of rising or falling edges . p1.2 int4 i external interrupt with a detection of rising and falling edge . p1.3 clo i/o clock output . p2.0 tclo0 i/o timer/counter 0 clock output . p3.0 tclo1 i/o timer/counter 1 clock output . p3.1 tcl0 i/o external clock input for timer/counter 0 . p3.2 tcl1 i/o external clock input for timer/counter 1 . p3.3 cin0 cin1 cin2 cin3 i/o 4-channel comparator input cin0?cin2: comparator input only cin3: comparator input or external reference input p7.0/seg55 p7.1/seg54 p7.2/seg53 p7.3/seg52 dtmf o dtmf output ? lcdck i/o lcd clock output p 8.0/seg51 lcdsy i/o lcd synchronization clock output . p8.1/seg50 com0?com7 o lcd common signal output . ? com8?com11 i/o p4.0?p4.3 com12?com15 p5.0?p5.3 seg0?seg39 o lcd segment signal output . ? seg40?seg 59 i/o p 10 .3?p 6 .0 k0?k3 i/o external interrupt (triggering edge is selectable) p0.0?p0.3 k4?k7 p6.0?p6.3 v dd ? main power supply . ? v ss ? ground . ? reset i reset signal . ? v lc 1 ? lcd power supply . p2.1 x in , x out ? crystal, c eramic or rc oscillator pins for system clock. ? xt in , xt out ? crystal oscillator pins for subsystem clock. ? test i chip test input pin. hold gnd when the device is operating. ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
ks57c 5616/p5616 product overview 1- 7 table 1 - 2. supplemental ks57c5616 pin data pin names share pins i/o type reset value circuit type p0. 0 ?p0.3 sck /k0, so/k1, si/k2, buz/k3 i/o input e-4 p1.0?p1. 3 int0 , int1 and int2 , int4 i input a- 4 p2.0 clo i/o input e-4 p2.1 vlc1 i/o input e-7 p2.2 ? i/o input e-4 p3.0?p3.1 tclo0, tclo1 i/o input e-2 p3.2?p3.3 tcl0, tcl1 i/o input e-4 p4.0?p4.3 p5.0?p5.3 com8?com11 com12?com15 i/o input h-24 p6.0?p6.3 seg5 9 /k4? seg5 6 /k7 i/o input h-25 p7.0?p7.2 seg5 5/cin0 ? seg5 3 /cin 2 i/o input h-26 p7.3 seg52/cin3 i/o input h-27 p8.0?p8. 1 seg 51 ?seg 50 i/o input h-28 p8. 2 ?p8.3 seg 49 ?seg4 8 i/o input h-24 p9.0?p9.3 seg4 7 ?seg4 4 i/o input h-24 p10.0?p10.3 seg43?seg40 i/o input h-24 com0?com7 ? o high h-3 seg0?seg39 ? o high h-3 dtmf ? o high impedance g-7 v dd ? ? ? ? v ss ? ? ? ? reset ? i ? b v lc1 ? ? ? ? x in , x out ? ? ? ? xt in , xt out ? ? ? ? test ? i ? ?
ks57c 5616/p5616 ( preliminary spec ) product overview 1 - 8 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a schmitt trigger pull-up resistor v dd pull-up resistor enable in figure 1 -4 . pin circuit type a- 4 schmitt trigger in v dd pull-up resistor figure 1 -5 . pin circuit type b p-ch n-ch v dd out output disable data figure 1 -6 . pin circuit type c
ks57c 5616/p5616 product overview 1- 9 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1 -7 . pin circuit type e -2 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data schmitt trigger figure 1 -8 . pin circuit type e-4
product overview ks57c 5616/p5616 1 - 10 n-ch v dd pull-up resistor enable v dd i/o pne pull-up resistor p-ch output disable data digital input vlcen vlc1 figure 1 -9 . pin circuit type e-7
ks57c 5616/p5616 product overview 1- 11 v lc3 com/seg v lc4 v lc5 v lc6 v lc2 v lc1 figure 1 -10 . pin circuit type h-3
product overview ks57c 5616/p5616 1 - 12 out output disable seg/com data v lc4 v lc5 v ss v lc3 v lc2 v lc1 figure 1 - 1 1 . pin circuit type h-23
ks57c 5616/p5616 product overview 1- 13 i/o v dd pull-up resistor pull-up resistor enable output disable data circuit type h-23 circuit type c com/seg lcd_on figure 1 - 1 2 . pin circuit type h-24 i/o v dd pull-up resistor pull-up resistor enable output disable data circuit type h-23 circuit type c com/seg lcd_on figure 1 - 1 3 . pin circuit type h-25
product overview ks57c 5616/p5616 1 - 14 i/o v dd p-ch pull-up resistor pull-up resistor enable output disable data circuit type h-23 circuit type c com/seg lcd_on analog input sel digital in analog in figure 1 - 1 4 . pin circuit type h-26
ks57c 5616/p5616 product overview 1- 15 i/o v dd p-ch pull-up resistor pull-up resistor enable output disable data circuit type h-23 circuit type c com/seg lcd out en analog input sel digital in analog in external ref in external ref sel figure 1 - 1 5 . pin circuit type h-27
product overview ks57c 5616/p5616 1 - 16 lcdck/lcdsy enable lcdck/cldsy i/o v dd pull-up resistor pull-up resistor enable output disable circuit type h-23 circuit type c com/seg lcd_on figure 1 - 1 6 . pin circuit type h-28 disable dtmf out + - figure 1 - 1 7 . pin circuit type g-7
ks57c5616/p5616 electrical data 1 6- 1 1 6 electrical data overview in this section, information on ks57c5616 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? ab solute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request miscellaneous timing waveforms ? a.c timing measurement point ? clock ti ming measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing
electrical data ks57c5616/p5616 1 6- 2 table 16- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i ports 0? 10 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o pins active ? 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for ports 0, 2? 10 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note : the values for output current low (i ol ) are calculated as peak value duty . table 16- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ?v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 2, 6, p3.2, p3.3, and reset 0.8 v dd v dd v ih3 x in , x out , and xt in v dd ? 0. 1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3v dd v v il2 ports 0, 1 , 2 , 6, p3.2, p3.3, and reset 0.2v dd v il3 x in , x out , and xt in 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 m a ports 0, 2? 10 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma p orts 0, 2? 10 ? ? 2.0 v
ks57c5616/p5616 electrical data 1 6- 3 table 16- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , xt in 20 input low leakage current i lil1 v i = 0 v all input pins except reset , x in , xt in ? ? ? 3 a i lil2 v i = 0 v x in , xt in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a pull-up resistor r l i v i = 0 v; v dd = 5 v , port 0? 10 25 47 100 k w v dd = 3 v 50 95 200 r l 2 v i = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing r lcd 1 ? 40 55 70 k w resistor (note) r lcd 2 20 28 35 | v dd - com i | voltage drop ( i = 0?15) v dc v dd = 2.7 v to 5.5 v ? 15 a per common pin ? ? 120 mv | v dd - segx| voltage drop (x = 0?5 9 ) v ds v dd = 2.7 v to 5.5 v ? 15 a per segment pin ? ? 120 v lc x output voltage v lc1 v dd = 2.7 v to 5.5 v lcd clock = 0 hz v dd ?0.2 v dd v dd +0.2 v v lc2 0. 8 v dd ?0.2 0. 8 v dd 0. 8 v dd +0.2 v lc3 0.6v dd ?0.2 0.6v dd 0.6v dd +0.2 v lc4 0.4v dd ?0.2 0.4v dd 0.4v dd +0.2 v lc5 0.2v dd ?0.2 0.2v dd 0.2v dd +0.2 note: r lcd1 is the lcd voltage dividing resistor when lcon.1 = ?0?, and r lcd2 when lcon.1 = ?1? .
electrical data ks57c5616/p5616 1 6- 4 table 16- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5 v 10% 3.58 mhz x- tal oscillator, c1 = c2 = 22pf ? 3.9 7.0 ma v dd = 3 v 10% ? 2.0 4.0 i dd2 (dtmf off) run mode; v dd = 5 v 10% crystal oscillator c1 = c2 = 22pf 6.0 mhz 3.58 mhz ? 4.1 2.7 8.0 5.0 v dd = 3 v 1 0% 6.0 mhz 3.58 mhz 1.9 1.2 4.0 2.3 i dd3 idle mode; v dd = 5 v 10% c rystal oscillator c1 = c2 = 22pf 6.0 mhz 3.58 mhz ? 1.2 0.9 2.5 1.8 v dd = 3 v 1 0% 6.0 mhz 3.58 mhz 0.5 0.4 1.5 1.0 i dd4 ( 2 ) run mode; v dd = 3 v 10% 32 khz c rystal oscillator ? 17.5 45 m a i dd5 (2) idle mode; v dd = 3 v 10% 32 khz c rystal oscillator ? 4.8 15 m a i dd6 stop mode; v dd = 5 v 10% v dd = 3 v 10% scmod = 0000 xt in = 0 v ? 2.0 0.6 5 3 m a stop mode; v dd = 5 v 10% v dd = 3 v 10% scmod = 0100 0.2 0.1 3 2 row tone level v row v dd = 2 to 5. 5 v rl = 12 k w ; temp = ? 30 to 60 c ? 16.0 ? 14.0 ? 11.0 dbv ratio of column to row tone dbcr v dd = 2 to 5. 5 v rl = 12 k w ; temp = ? 30 to 60 c 1 2 3 distortion (dual tone) thd v dd = 2 to 5. 5 v 1 mhz band rl = 12 k w ; temp = ? 30 to 60 c ? ? 5 % notes: 1. data includes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, is set to 1001b, the main system clock oscillation stops and the subsystem clock is used. 3. currents in the following circuits are not included: on-chip pull-up resistors, internal lcd voltage dividing resistors, and output port drive currents .
ks57c5616/p5616 electrical data 1 6- 5 table 16- 3. main system oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range; v dd = 3.0 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 stabilization time (2) v dd = 3 v ? ? 10 ms v dd = 1.8 v to 5.5 v ? ? 30 external clock x in x out x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1,250 ns rc oscillator x in x out r frequency r = 25 k w, v dd = 5 v ? 2 ? mhz r = 40 k w, v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data ks57c5616/p5616 1 6- 6 table 16-4 . recommended oscillator constants (t a = ? 40 c to + 85 c) manufacturer series number (1) frequency range load cap ( pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr ? e ? m5 3.58 mhz?6.0 mhz 33 33 2.0 5.5 leaded type fcr ? e ? mc5 3.58 mhz?6.0 mhz (2) (2) 2.0 5.5 on-chip c leaded type ccr ? e ? mc3 3.58 mhz?6.0 mhz (3) (3) 2.0 5.5 on-chip c smd type note s: 1. please specify normal oscillator frequency. 2. on-chip c: 30pf built in. 3. on-chip c: 38pf built in. table 16-5 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) v dd = 1.8 v to 5 .5 v 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5 .5 v ? ? 10 external clock xt in xt out open xt in input frequency (1) v dd = 1.8 v to 5 .5 v 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscill ating stabilization after a power-on occurs.
ks57c5616/p5616 electrical data 1 6- 7 table 16-6 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 16-7 . comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v ) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage accuracy v cin ? ? ? 150 mv input leakage current i cin , i ref ? ? 3 ? 3 m a
electrical data ks57c5616/p5616 1 6- 8 table 16-8 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time ( note ) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 1.8 v to 5 .5 v 1.33 64 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 1.8 v to 5 .5 v 1 tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v ex ternal sck source 800 ? ? ns internal sck source 650 v dd = 1.8 v to 5.5 v ex ternal sck source 3200 internal sck source ; output 3800
ks57c5616/p5616 electrical data 1 6- 9 table 16-8 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v ex ternal sck source 325 ? ? ns internal sck source t k cy / 2?50 v dd = 1.8 v to 5 .5 v ex ternal sck source 1600 internal sck source t kcy / 2?150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v ; input 100 ? ? ns v dd = 2.7 v to 5.5 v ; output 150 v dd = 1.8 v to 5.5 v ; input 150 v dd = 1.8 v to 5.5 v ; output 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v ; input 400 ? ? ns v dd = 2.7 v to 5.5 v ; output 400 v dd = 1.8 v to 5.5 v ; input 600 v dd = 1.8 v to 5.5 v ; output 500 output delay for sck to so t kso v dd = 2.7 v to 5.5 v ; input ? ? 300 ns v dd = 2.7 v to 5.5 v ; output 250 v dd = 1.8 v to 5.5 v ; input 1000 v dd = 2.7 v to 5.5 v ; output 1000 interrupt input high, low width t inth , t intl int0 ?int2, int4, ks 0?k s 7 10 ? ? s reset input low width t rsl input 10 ? ? s note: unless specified the otherwise, instruction cycle time condition values assume a main system clock ( fx) source.
electrical data ks57c5616/p5616 1 6- 10 1 2 3 4 5 6 7 15.625khz 0.75khz 1.05mhz 1.5mhz cpu clock 4.2mhz 3mhz 6mhz main os. freq. (divided by 4) supply voltage (v) cpu clock = 1/n x oscillator frequency (n =4, 8 or 64) 1.8 2.7 figure 16- 1. standard operating voltage range table 16-9 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during the oscillator stabilization wait time, all the cpu operations must be stopped to avoid instability that can occur during the oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay an execution of cpu instructions during the wait time.
ks57c5616/p5616 electrical data 1 6- 11 timing waveforms execution of stop instruction internal r eset operation ~ ~ v dddr ~ ~ stop mode idle mode operating mode data retention mode t srel t wait reset v dd figure 16-2 . stop mode release timing when initiated b y reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 16-3 . stop mode release timing when initiated b y interrupt request
electrical data ks57c5616/p5616 1 6- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 16-4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 16- 5. clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 16- 6. clock timing measurement at xt in
ks57c5616/p5616 electrical data 1 6- 13 tcl0 t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 16- 7. tcl timing reset t rsl 0.2 v dd figure 16- 8. input timing for reset signal
electrical data ks57c5616/p5616 1 6- 14 int0, 1, 2, 4 k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 16- 9. input timing for external interrupts and quasi-interrupts output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 16- 10. serial data transfer timing
ks57c5616/p5616 mechanical data 1 7- 1 1 7 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table 100-qfp-1420c 23.90 0.3 #100 20.00 0.2 14.00 0.2 17.00 0.3 #1 (0.83) note : dimensions are in millimeters. 0.30 0.1 0.65 (0.58) 0.10 max 0.80 0.20 2.65 0.10 3.00 max 0.10 max 0-8 0.15 +0.10 _0.05 0.05 min 0.80 0.20 o figure 1 7- 1. 100-qfp package dimensions
mechanical data ks57c5616/p5616 1 7- 2 notes
ks57c5616/p5616 ks5 7p5616 otp 18- 1 18 KS57P5616 otp overview the KS57P5616 single-chip cmos microcontroller is the otp (one time programmable) version of the ks57c5616 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the KS57P5616 is fully compatible with the ks57c5616, both in function and in pin configuration. because of its simple programming requirements, the KS57P5616 is ideal for use as an evaluation chip for the ks57c5616.
KS57P5616 otp ks57c5616/p5616 18- 2 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 p3.1/tclo1 p3.2/tcl0 p3.3/tcl1 com0 com1 com2 com3 com4 com5 com6 com7 p4.0/com8 p4.1/com9 p4.2/com10 p4.3/com11 p5.0/com12 p5.1/com13 p5.2/com14 p5.3/com15 p6.0/seg59/k4 seg29 seg30 seg31 seg32 seg33 seg34 seg35 seg36 seg37 seg38 seg39 p10.3/seg40 p10.2/seg41 p10.1/seg42 p10.0/seg43 p9.3/seg44 p9.2/seg45 p9.1/seg46 p9.0/seg47 p8.3/seg48 p8.2/seg49 p8.1/seg50/lcdsy p8.0/seg51/lcdck p7.3/seg52/cin3 p7.2/seg53/cin2 p7.1/seg54/cin1 p7.0/seg55/cin0 p6.3/seg56/k7 p6.2/seg57/k6 p6.1/seg58/k5 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 dtmf p0.0/ sck /k0 p0.1/so/k1 sdat /p0.2/si/k2 sclk /p0.3/buz/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset /reset p1.0/int0 p1.1/int1 p1.2/int2 p1.3/int4 p2.0/clo p2.1/v lc1 p2.2 p3.0/tclo0 KS57P5616 (100-qfp-1420c) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 figure 18-1. KS57P5616 pin assignments (100-qfp package)
ks57c5616/p5616 ks5 7p5616 otp 18- 3 table 18-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.2 sdat 13 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.3 sclk 14 i/o serial clock pin. input only pin. test v pp (test) 19 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. when otp is operating, hold gnd. (option) reset reset 22 i chip initialization v dd /v ss v dd /v ss 15/16 i logic power supply pin. v dd should be tied to +5 v during programming. table 18-2. comparison of KS57P5616 and ks57c5616 features characteristic KS57P5616 ks57c5616 program memory 16-kbyte eprom 16-kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 100 qfp 100 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the KS57P5616, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 18-3 below. table 18-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15?a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
KS57P5616 otp ks57c5616/p5616 18- 4 table 18-4 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i ports 0? 10 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o pins active ? 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) total for ports 0, 2? 10 + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note : the values for output current low (i ol ) are calculated as peak value duty .
ks57c5616/p5616 ks5 7p5616 otp 18- 5 table 18-5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ?v ih3 0.7v dd ? v dd v v ih2 ports 0, 1, 2, 6, p3.2, p3.3, and reset 0.8v dd v dd v ih3 x in , x out , and xt in v dd ? 0. 1 v dd input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3v dd v v il2 ports 0, 1 , 2 , 6, p3.2, p3.3, and reset 0.2v dd v il3 x in , x out , and xt in 0. 1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 0, 2? 10 v dd ? 1.0 ? ? v output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma p orts 0, 2? 10 ? ? 2.0 v input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in , xt in 20 input low leakage current i lil1 v i = 0 v all input pins except reset , x in , xt in ? ? ? 3 a i lil2 v i = 0 v x in, xt in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 a
KS57P5616 otp ks57c5616/p5616 18- 6 table 18-5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units pull-up resistor r l i v i = 0 v; v dd = 5 v , port 0? 10 25 47 100 k w v dd = 3 v 50 95 200 r l 2 v i = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing r lcd 1 ? 40 55 70 k w resistor (note) r lcd 2 20 28 35 | v dd - com i | voltage drop ( i = 0?15) v dc v dd = 2.7 v to 5.5 v ? 15 a per common pin ? ? 120 mv | v dd - segx| voltage drop (x = 0?5 9 ) v ds v dd = 2.7 v to 5.5 v ? 15 a per segment pin ? ? 120 v lc x output voltage v lc1 v dd = 2.7 v to 5.5 v lcd clock = 0 hz v dd ?0.2 v dd v dd +0.2 v v lc2 0. 8 v dd ?0.2 0. 8 v dd 0. 8 v dd +0.2 v lc3 0.6v dd ?0.2 0.6v dd 0.6v dd +0.2 v lc4 0.4v dd ?0.2 0.4v dd 0.4v dd +0.2 v lc5 0.2v dd ?0.2 0.2v dd 0.2v dd +0.2 note: r lcd1 is the lcd voltage dividing resistor when lcon.1 = ?0?, and r lcd2 is the one when lcon.1 = ?1? .
ks57c5616/p5616 ks5 7p5616 otp 18- 7 table 18-5 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v ) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; v dd = 5 v 10% 3.58 mhz x- tal oscillator, c1 = c2 = 22pf ? 3.9 7.0 ma vdd = 3 v 10% ? 2.0 4.0 i dd2 (dtmf off) run mode; v dd = 5 v 10% crystal oscillator c1 = c2 = 22pf 6.0 mhz 3.58 mhz 4.1 2.7 8.0 5.0 v dd = 3 v 1 0% 6.0 mhz 3.58 mhz 1.9 1.2 4.0 2.3 i dd3 idle mode; v dd = 5 v 10% c rystal oscillator c1 = c2 = 22pf 6.0 mhz 3.58 mhz ? 1.2 0.9 2.5 1.8 v dd = 3 v 1 0% 6.0 mhz 3.58 mhz 0.5 0.4 1.5 1.0 i dd4 ( 2 ) run mode; v dd = 3 v 10% 32 khz c rystal oscillator ? 17.5 45 m a i dd5 (2) idle mode; v dd = 3 v 10% 32 khz c rystal oscillator ? 4.8 15 m a i dd6 stop mode; v dd = 5 v 10% v dd = 3 v 10% scmod = 0000 xt in = 0 v ? 2.0 0.6 5 3 m a stop mode; v dd = 5 v 10% v dd = 3 v 10% scmod = 0100 0.2 0.1 3 2 row tone level v row v dd = 2 to 5.5 v rl = 12 k w ; temp = ? 30 to 60 c ? 16.0 ? 14.0 ? 11.0 dbv ratio of column to row tone dbcr v dd = 2 to 5.5 v rl = 12 k w ; temp = ? 30 to 60 c 1 2 3 distortion (dual tone) thd v dd = 2 to 5.5 v 1 mhz band rl = 12 k w ; temp = ? 30 to 60 c ? ? 5 % notes: 1. data includes power consumption for subsystem clock oscillation. 2 . when the system clock control register, scmod, i s set to 1001b, the main system clock oscillation stops and the subsystem clock is used. 3. currents in the following circuits are not included: on-chip pull-up resistors, internal lcd voltage dividing resistors, and output port drive currents .
KS57P5616 otp ks57c5616/p5616 18- 8 table 18-6 . main system oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3.0 stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range; v dd = 3.0 v ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3.0 stabilization time (2) v dd = 3 v ? ? 10 ms v dd = 1.8 v to 5.5 v ? ? 30 external clock x in x out x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 3.0 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1,250 ns rc oscillator x in x out r frequency r = 25 k w, v dd = 5 v ? 2 ? mhz r = 40 k w, v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when sto p mode is terminated.
ks57c5616/p5616 ks5 7p5616 otp 18- 9 table 18-7 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) v dd = 1.8 v to 5 .5 v 32 32.768 35 khz stabilization time (2) v dd = 2.7 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 5 .5 v ? ? 10 external clock xt in xt out open xt in input frequency (1) v dd = 1.8 v to 5 .5 v 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. table 18-8 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
KS57P5616 otp ks57c5616/p5616 18- 10 1 2 3 4 5 6 7 15.625khz 0.75khz 1.05mhz 1.5mhz cpu clock 4.2mhz 3mhz 6mhz main os. freq. (divided by 4) supply voltage (v) cpu clock = 1/n x oscillator frequency (n =4, 8 or 64) 1.8 2.7 figure 18-2 . standard operating voltage range

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