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?2004 integrated device technology, inc. may 2004 dsc 2654/9 1 i/o control address decoder memory array arbitration interrupt logic address decoder i/o control r/ w l ce l oe l busy l a 10l a 0l 2654 drw 01 i/o 0l -i/o 8l ce l oe l r/ w l int l busy r i/o 0r -i/o 8r a 10r a 0r int r ce r oe r (2) (1,2) (1,2) (2) r/ w r ce r oe r r/ w r 11 11 high-speed 2k x 9 dual-port static ram with busy & interrupt idt70121s/l idt70125s/l notes: 1. 70121 (master): busy is non-tri-stated push-pull output. 70125 (slave): busy is input. 2. int is non-tri-stated push-pull output. functional block diagram features ? high-speed access ? commercial: 25/35/45/55ns (max.) ? industrial: 35ns (max.) low-power operation ? idt70121/70125s active: 675mw (typ.) standby: 5mw (typ.) ? idt70121/70125l active: 675mw (typ.) standby: 1mw (typ.) fully asychronous operation from either port master idt70121 easily expands data bus width to 18 bits or more using slave idt70125 chip on-chip port arbitration logic (idt70121 only) busy output flag on master; busy input on slave int flag for port-to-port communication battery backup operation?2v data retention ttl-compatible, signal 5v (10%) power supply available in 52-pin plcc industrial temperature range (?40c to +85c) is available for selected speeds
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 2 . 05/27/04 a 9r g n d 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 7 6 5 4 3 2 5 2 5 1 5 0 4 9 4 8 4 7 3 3 8 9 10 11 12 13 14 15 16 17 18 idt70121/125j j52-1 (4) 19 a 6l a 7l a 1l a 2l a 3l a 4l a 5l a 8l i/o 0l i/o 1l i/o 2l i/o 3l 46 45 44 43 42 41 40 39 38 37 36 35 a 5r a 6r a 0r a 1r a 2r a 3r a 4r a 7r a 8r i/o 8r i/o 7r 1 index 34 20 oe r a 9l 2654 drw 02 52-pin plcc top view (5) a 1 0 r i n t r r / w r c e r v c c c e l i n t l a 1 0 l o e l a 0 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 8 l i / o 0 r i / o 1 r i / o 2 r i / o 3 r i / o 4 r i / o 5 r i / o 6 r b u s y r r / w l b u s y l pin configurations (1,2,3) description the idt70121/idt70125 are high-speed 2k x 9 dual-port static rams. the idt70121 is designed to be used as a stand-alone 9-bit dual- port ram or as a ?master? dual-port ram together with the idt70125 ?slave? dual-port in 18-bit-or-more word width systems. using the idt master/slave dual-port ram approach in 18-bit-or-wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. both devices provide two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power-down feature, controlled by ce , permits the on-chip circuitry of each port to enter a very low standby power mode. the idt70121/idt70125 utilizes a 9-bit wide data path to allow for data/control and parity bits at the user?s option. this feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 675mw of power. low-power (l) versions offer battery backup data retention capability with each port typically consuming 200w from a 2v battery. the idt70121/idt70125 devices are packaged in a 52-pin plcc. notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. package body is approximately .75 in x .75 in x .17 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
3 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges maximum operating temperature and supply voltage (1) recommended dc operating conditions absolute maximum ratings (1) capacitance (t a = +25c, f = 1.0mhz) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v cc + 10%. notes: 1. v il > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. note: 1. this parameter is determined by device characterization but is not production tested. dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 10%) note: 1. at vcc < 2.0v leakages are undefined. symbol rating commercial & industrial unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c i out dc output current 50 ma 2654 tbl 01 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 2654 tbl 02 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1 ) ____ 0.8 v 2654 tbl 03 symbol parameter conditions (1 ) max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 2654 tbl 04 symbol parameter test conditions 70121s 70125s 70121l 70125l unit min. max. min. max. |i li | input leakage current (1) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current v cc = 5.5v, ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2654 tbl 0 5
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 4 dc electrical characteristics over the operating temperature and supply voltage range (1,4) (v cc = 5v 10%) notes: 1. 'x' in part numbers indicates power rating (s or l). 2. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , and using ?ac test conditions? of input levels of gnd to 3v. 3. f = 0 means no address or control lines change. applies only to inputs at cmos level standby. 4. vcc=5v, t a =+25c for typ, and is not production tested. 5. port "a" may be either left or right port. port "b" is opposite from port "a". 70121x25 70125x25 com'l only 70121x35 70125x35 com'l & ind symbol parameter test condition version typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled f = f max (2) com'l s l 135 135 260 220 135 135 250 210 ma ind s l ___ ___ ___ ___ 135 135 275 250 i sb1 standby current (both ports - ttl level inputs) ce "a" = ce "b" = v ih f = f max (2) com'l s l 30 30 65 45 30 30 65 45 ma ind s l ___ ___ ___ ___ 30 30 80 65 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (2) com'l s l 80 80 175 145 80 80 165 135 ma ind s l ___ ___ ___ ___ 80 80 190 165 i sb3 full standby current (both ports - cmos level inputs) ce "a" and ce "b" > v cc - 0.2v v in > v cc - 0.2v or vin < 0.2v, f = 0 (3) com'l s l 1.0 0.2 15 5 1.0 0.2 15 5 ma ind s l ___ ___ ___ ___ 1.0 0.2 15 5 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (2) com'l s l 70 70 170 140 70 70 160 130 ma ind s l ___ ___ ___ ___ 70 70 185 160 2654 tbl 06a 70121x45 70125x45 com'l only 70121x55 70125x55 com'l only symbol parameter test condition version typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce = v il , outputs disabled f = f max (2) com'l s l 135 135 245 205 135 135 240 200 ma ind s l ___ ___ ___ ___ ___ ___ ___ ___ i sb1 standby current (both ports - ttl level inputs) ce "a" = ce "b" = v ih f = f max (2) com'l s l 30 30 65 45 30 30 65 45 ma ind s l ___ ___ ___ ___ ___ ___ ___ ___ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (2) com'l s l 80 80 160 130 80 80 155 125 ma ind s l ___ ___ ___ ___ ___ ___ ___ ___ i sb3 full standby current (both ports - cmos level inputs) ce "a" and ce "b" > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (3) com'l s l 1.0 0.2 15 5 1.0 0.2 15 5 ma ind s l ___ ___ ___ ___ ___ ___ ___ ___ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (2) com'l s l 70 70 155 125 70 70 150 120 ma ind s l ___ ___ ___ ___ ___ ___ ___ ___ 2654 tbl 06b
5 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges data retention characteristics (l version only) data retention waveform ac test conditions figure 1. ac output test load figure 2. output test load (for t lz , t hz , t wz , t ow ) *including scope and jig. notes: 1. v cc = 2v, t a = +25c, and are not production tested. 2. t rc = read cycle time. 3. this parameter is guaranteed but is not production tested. v dr 2v data retention mode vcc ce 4.5v t cdr t r v ih v dr v ih 4.5v 2654 drw 03 1250 ? 30pf 775 ? data out busy int 5v 5v 1250 ? 5pf* 775 ? data out 2654 drw 04 symbol parameter test condition min. typ. (1) max. unit v dr v cc for data retention 2.0 ___ ___ v i ccdr data retention current v cc = 2v, ce > v cc - 0.2v ind. ___ 100 4000 a t cdr (3 ) chip deselect to data retention time v in > v cc - 0.2v or v in < 0.2 com'l. ___ 100 1500 t r (3) operation recovery time t rc (2) ___ ___ v 2654 tb l 07 input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns 1.5v 1.5v figures 1 and 2 2654 tbl 08
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 6 ac electrical characteristics over the operating temperature and supply voltage range (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. this parameter guaranteed by device characterization, but is not production tested. 3. 'x' in part numbers indicates power rating (s or l). 70121x25 70125x25 com'l only 70121x35 70125x35 com'l & ind unit symbol parameter min. max. min. max. read cycle t rc re ad cycle time 25 ____ 35 ____ ns t aa address access time ____ 25 ____ 35 ns t ace chip enable access time ____ 25 ____ 35 ns t aoe output enable access time ____ 12 ____ 25 ns t oh output hold from address change 0 ____ 0 ____ ns t lz output lo w-z time (1,2) 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 10 ____ 15 ns t pu chip enable to power up time (2) 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 50 ____ 50 ns 2654 tbl 09a 70121x45 70125x45 com'l only 70121x55 70125x55 com'l only unit symbol parameter min. max. min. max. read cycle t rc re ad cycle time 45 ____ 55 ____ ns t aa address access time ____ 45 ____ 55 ns t ace chip enable access time ____ 45 ____ 55 ns t aoe output enable access time ____ 30 ____ 35 ns t oh output hold from address change 0 ____ 0 ____ ns t lz output lo w-z time (1,2) 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 20 ____ 30 ns t pu chip enable to power up time (2) 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 50 ____ 50 ns 2654 tbl 09b
7 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges timing waveform of read cycle no. 1, either side (1,2,4) notes: 1. timing depends on which signal is aserted last, oe or ce . 2. timing depends on which signal is deaserted first, oe or ce . 3. t bdd delay is required only in a case where the opposite port is completing a write operation to the same address location. for simu ltaneous read operations busy has no relationship to valid output data. 4. start of valid data depends on which timing becomes effective last, t aoe, t ace, t aa, or t bdd. 5. r/ w = v ih , ce = v il , and oe = v il , and the address is valid prior to other coincidental with ce transition low. timing waveform of read cycle no. 2, either side (5) address data out t rc t oh previous data valid t aa t oh data valid 2654 drw 05 t bdd (3,4) busy out ce t ace t hz t lz t pd valid data t pu 50% oe data out current i cc i ss 50% 2654 drw 06 (4) (1) (1) (2) (2) (4) t lz t hz t aoe
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 8 ac electrical characteristics over the operating temperature and supply voltage range (4) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). 2. this parameter guaranteed by device characterization, but is not production tested. 3. for master/slave combination, t wc = t baa + t wp, since r/w = v il must occur after t baa . 4. 'x' in part numbers indicates power rating (s or l). 5. the specified t dh must be met by the device supplying write date to the ram under all operating conditions. although t dh and t ow values will vary over voltage and temperature. the actual t dh will always be smaller than the actual t ow. 6. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . symbol parameter 70121x25 70125x25 com'l only 70121x35 70125x35 com'l & ind unit min. max. min. max. writ e cycle t wc write cycle time (4) 25 ____ 35 ____ ns t ew chip enable to end-of-write 20 ____ 30 ____ ns t aw address valid to end-of-write 20 ____ 30 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width (6 ) 20 ____ 30 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 12 ____ 20 ____ ns t hz output high-z time (1 , 2 ,3 ) ____ 10 ____ 15 ns t dh data ho ld time (5 ) 0 ____ 0 ____ ns t wz write enable to output in high-z (1,3) ____ 10 ____ 15 ns t ow output active from end-of-write (1,2,3,5) 0 ____ 0 ____ ns 2 654 tbl 10a symbol parameter 70121x45 70125x45 com'l only 70121x55 70125x55 com'l only unit min. max. min. max. writ e cycle t wc write cycle time (4 ) 45 ____ 55 ____ ns t ew chip enable to end-of-write 35 ____ 40 ____ ns t aw address valid to end-of-write 35 ____ 40 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width (6 ) 35 ____ 40 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 20 ____ 20 ____ ns t hz output high-z time (1 , 2 ,3 ) ____ 20 ____ 30 ns t dh data ho ld time (5 ) 0 ____ 0 ____ ns t wz write enable to output in high-z (1,3) ____ 20 ____ 30 ns t ow output active from end-of-write (1,2,3,5) 0 ____ 0 ____ ns 2654 tbl 10b
9 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il and a r/ w = v il 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. this parameter is determined be device characterization, but is not production tested. transition is measured 0mv from ste ady state with the output test load (figure 2). 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . timing waveform of write cycle no. 2, ce controlled timing (1,5) timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) r/ w t wc t hz t aw t hz t as t wp data out t dw t dh t ow oe address data in ce t wz (4) (4) t wr 2654 drw 07 (3) (7) (2) (6) (7) (7) ce t wc t as t wr t dw t dh address data in r/ w t aw t ew 2654 drw 08 (6) (2) (3)
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 10 ac electrical characteristics over the operating temperature and supply voltage range (6) notes : 1. port-to-port delay through ram cells from writing port to reading port, refer to ?timing waveform of write with port-to-port read and busy . 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that a write cycle is inhibited on port 'b' during contention on port 'a'.. 5. to ensure that a write cycle is completed on port 'b' after contention on port 'a'. 6. 'x' in part numbers indicates power rating (s or l). 70121x25 70125x25 com'l only 70121x35 70125x35 com'l & ind symbol parameter min.max.min.max.unit busy timing (for master idt70121) t baa busy access time from address ____ 20 ____ 20 ns t bda busy disable time from address ____ 20 ____ 20 ns t bac busy access time from chip enable ____ 20 ____ 20 ns t bdc busy disable time from chip enable ____ 20 ____ 20 ns t wdd write pulse to data delay (1) 50 60 t ddd write data valid to read data delay (1) 35 45 t aps arbitration prio rity se t-up time (2) 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 30 ____ 30 ns t wh write hold after busy (5) 15 ____ 20 ____ ns busy input timing (for slave idt70125) t wb write to busy inp ut (4) 0 ____ 0 ____ ns t wh write hold after busy (5) 15 ____ 20 ____ ns t wdd write pulse to data delay (1) ____ 50 ____ 60 ns t ddd write data valid to read data delay (1) ____ 35 ____ 45 ns 2654 tbl 11a 70121x45 70125x45 com'l only 70121x55 70125x55 com'l only symbol parameter min.max.min.max.unit busy timing (for master idt 70121) t baa busy access time from address ____ 20 ____ 30 ns t bda busy disable time from address ____ 20 ____ 30 ns t bac busy access time from chip enable ____ 20 ____ 30 ns t bdc busy disable time from chip enable ____ 20 ____ 30 ns t wdd write pulse to data delay (1) 70 80 t ddd write data valid to read data delay (1) 55 65 t aps arbitration priority set-up time (2) 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 35 ____ 45 ns t wh write hold after busy (5) 20 ____ 20 ____ ns busy input timing (for slave idt 70125) t wb write to busy inp ut (4) 0 ____ 0 ____ ns t wh write hold after busy (5) 20 ____ 20 ____ ns t wdd write pulse to data delay (1) ____ 70 ____ 80 ns t ddd write data valid to read data delay (1) ____ 55 ____ 65 ns 2654 tbl 11b
11 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges t aps addr 'a' data in'a' match t wc t wp r/ w 'a' addr 'b' data out 'b' match busy 'b' t bda t dw t dh valid valid t ddd (4) t wdd t bdd 2654 drw 09 (1) timing waveform of busy arbritration controlled by ce timing (1) timing waveform of write with port-to-port read and busy (1,2,3) timing waveform of write with busy (3) notes: 1. t wh must be met for both busy input (slave) and output (master). 2. busy is asserted on port 'b' blocking r/ w 'b', until busy 'b' goes high. 3. all timing is the same for left and right ports. port"a" may be either left or right port. port "b" is the opposite from port "a". notes: 1. to ensure that the earlier of the two ports wins. t aps is ignored for slave (idt70125). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for the left and right ports. port 'a' may be either the left or right port. port "b" is oppsite from port "a". 2654 drw 10 r/ w "a" busy "b" t wp t wb r/ w "b" t wh (1) (2) , t bdc addr "a and b" busy "b" ce "a" t aps (2) t bac addresses match ce "b" 2654 drw 11 (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted (70121 only).
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 12 timing waveform of busy arbritration controlled by address (1) ac electrical characteristics over the operating temperature and supply voltage range (1) notes : 1. 'x' in part numbers indicates power rating (s or l). t baa addr 'a' busy 'b' addresses match addresses do not match t rc or t wc t aps (2) t bda addr 'b' 2654 drw 12 70121x25 70125x25 com'l only 70121x35 70125x35 com'l & ind symbol parameter min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins inte rrupt se t time ____ 25 ____ 35 ns t inr interrupt reset time ____ 25 ____ 35 ns 2 654 tbl 12a 70121x45 70125x45 com'l only 70121x55 70125x55 com'l only symbol parameter min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins inte rrupt se t time ____ 40 ____ 45 ns t inr interrupt reset time ____ 40 ____ 45 ns 2654 tbl 12b notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted (70121 only).
13 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges timing waveform of interrupt mode (1) truth tables truth table ii. interrupt flag (1,4) truth table i. non-contention read/write control (4) notes: 1. a 0l ? a 10l a 0r ? a 10r . 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. 'h' = v ih , 'l' = v il , 'x' = don?t care, 'z' = high impedance notes : 1. assumes busy l = busy r = v ih 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. 'h' = high,' l' = low,' x' = don?t care t ins addr 'a' int 'b' interrupt set address t wc t as r/ w 'a' t wr 2654 drw 13 (3) (3) (2) (4) left or right port (1 ) function r/ w ce oe d 0-8 x h x z port disab le and in power-down mode, i sb2 or i sb4 xhx z ce r = ce l = h, power-downmode, i sb1 or i sb3 llxdata in data on port written into memory (2 ) hl ldata out data in memory output on port (3 ) h l h z high-impedance outputs 2654 tbl 13 left port right port function r/ w l ce l oe l a 10l -a 0l int l r/ w r ce r oe r a 10r -a 0r int r llx7ffxxxx x l (2) se t rig ht int r flag xxxxxxll7ffh (3) re se t right int r flag xxx x l (3 ) l l x 7fe x se t left int l flag xll7feh (2) x x x x x re se t left int l flag 2654 tbl 14 notes: . 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. see interupt truth table. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first.
6.42 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges 14 functional description the idt70121/125 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70121/125 has an automatic power down feature controlled by ce . the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce high). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7fe (hex), where a write is defined as the ce = r/ w = v il per truth table ii. the left port clears the interrupt by access address location 7fe access when ce r = oe r = v il , r/ w is a "don't care". likewise, the right port interrupt flag (int r ) is asserted when the left port writes to memory location 7ff (hex) and to clear the interrupt flag (int r ), the right port must access the memory location 7ff. the message (9 bits) at 7fe or 7ff is user- defined, since it is an addressable sram location. if the interrupt function is not used, address locations 7fe and 7ff are not used as mail boxes, but as part of the random access memory. refer to table ii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applications. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. if the write inhibit function of busy logic is not desirable, the busy logic can be disabled by using the idt70125 (slave). in the idt70125, the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. once in slave mode the busy pin operates solely as a write inhibit input pin. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt70121/125 ram in master mode, are push-pull type outputs and do not require pull up resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array requires the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an idt70121/125 ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master use the busy signal as a write inhibit signal. thus on the idt70121 ram the busy pin is an output of the part, and the busy pin is an input of the idt70125 as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and figure 3. busy and chip enable routing for both width and depth expansion with 70121 (master) and 70125 (slave) rams. 2654 drw 14 master dual port ram busy r ce master dual port ram busy r ce slave dual port ram busy r ce slave dual port ram busy r ce busy l busy r d e c o d e r busy l busy l busy l busy l , inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave.
15 idt70121/idt70125 high-speed 2k x 9 dual-port static ram with busy & interrupt industrial and commercial te mperature ranges ordering information note : 1. industrial temperature: for other speeds, packages and powers contact your sales office. x power xxx speed x package x process/ temperature range blank i (1) commercial (0c to +70c) industrial (-40c to +85c) j 52-pin plcc (j52-1) 25 35 45 55 l s low power standard power xxxxx device type 70121 70125 18k (2k x 9-bit) master dual-port ram w/ interrupt 18k (2k x 9-bit) slave dual-port ram w/ interrupt idt speed in nanoseconds 2654 drw 15 commercial only commercial & industrial commercial only commercial only , corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-5166 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 01/06/99: initiated datasheet document history converted to new format cosmetic and typographical corrections pages 2 and 3 added additional notes to pin configurations 06/03/99: changed drawing format page 1 corrected dsc number 05/28/04: page 3 changed storage temperature parameter from -55 to +125 to -65 to +150 clarified t a parameter footnote page 4 dc electrical parameters?changed test condition wording from "open" to "disabled" page 9 changed 500mv to 0mv in notes page 2 added date revision for pin configuration page 4, 6, 8, 10 & 12 added industrial temp to column headings for 35ns speed to dc and ac electrical characteristics page 4 removed industrial temp from 25, 45 & 55ns speeds from dc electrical characteristics page 3, 4, 6, 8, 10 & 12 removed industrial temp footnote from all tables page 10 corrected error in ac busy timing tables changing 71v33 to 70121 and changing 71v43 to 70125 page 15 added industrial temp offering to 35ns ordering information page 1 & 15 replaced old tm logo with new tm logo page 6 footnote reference 5 removed from ac electrical characteristics read table page 1 changed wording of footnote 1 from " int is totem-pole output" to " int is non-tr-stated push-pull output" page 5 updated ac test conditions input rise/fall times from 5ns to 3ns

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