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? semiconductor components industries, llc, 2001 july, 2001 rev. 2 1 publication order number: ncn6000/d ncn6000 compact smart card interface ic the ncn6000 is an integrated circuit dedicated to the smart card interface applications. the device handles any type of smart card through a simple and flexible microcontroller interface. on top of that, thanks to the builtin chip select pin, several couplers can be connected in parallel. the device is particularly suited for low cost, low power applications, with high extended battery life coming from extremely low quiescent current. features ? 100% compatible with iso78163 and emv standard ? wide battery supply voltage range: 2.7 vbat 6.0 v ? programmable crd_vcc supply to cope with either 3.0 v or 5.0 v card operation ? builtin dc/dc converter generates the crd_vcc supply with a single external low cost inductor only, providing a high efficiency power conversion ? full control of the power up/down sequence yields high signal integrity on both the card i/o and the signal lines ? programmable card clock generator ? builtin chip select logic allows parallel coupling operation ? esd protection on card pins (8.0 kv, human body model) ? fault monitoring includes vbat low and vcc low, providing logic feedback to external cpu ? card detection programmable to handle positive or negative going input ? builtin programmable crd_clk stop function handles both high or low state typical application ? ecommerce interface ? atm smart card ? pay tv system figure 1. simplified application micro controller ncn6000 smart card interface iso/emv device package shipping ordering information ncn6000dtb tssop20 75 units/rail http://onsemi.com tssop20 dtb suffix case 948e 1 20 marking diagram a = assembly location l = wafer lot y = year w = work week pin connections 1 2 3 4 5 6 7 8 20 19 18 16 15 14 13 (top view ) status a0 a1 pgm pwr_on cs reset i/o v bat l out_ h ground crd_v cc crd_clk l out_ l crd_io ncn 6000 alyw 1 20 9 10 11 12 17 int clock_in pwr_gnd crd_rst crd_det ncn6000dbtr2 tssop20 2500/tape & reel
ncn6000 http://onsemi.com 2 gnd v cc pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 irq xtal mcu gnd l1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 a0 a1 pgm pwr_on status cs reset i/o int clock_in v bat l out_h l out_l pwr_gnd ground crd_v cc crd_io crd_clk crd_rst crd_det 22 m h c3 c1 10 m f 100 nf swa swb c8 c4 clk rst v cc gnd i/o 17 18 8 4 3 2 1 5 7 vpp smartcard j1 iso7816 gnd gnd gnd gnd gnd gnd ncn6000 +5 v 10 m f c2 u1 figure 2. typical application
ncn6000 http://onsemi.com 3 ground 3 9 6 2 1 10 5 8 7 15 20 11 19 18 17 16 12 - + a0 a1 pgm pwr_on status cs reset i/o int clock_in v bat l out_h l out_l pwr_gnd crd_v cc crd_det s r q 50 m s delay card detection decoder 1:16 clock divider 4 card status logic & card pins sequencer dc/dc status fault on/off dc/dc converter 3 v / 5 v a status int clock +v bat power down active pwr_down v bat clk stop enable v cc status int gnd v bat gnd clock clk_stop seq 1 seq 2 seq 3 crd_clk crd_rst clock 13 i/o i/o 14 crd_io reset pwr_on v bat v bat v bat 1 2 3 data data 20 k 20 k 50 k seq 1 seq 2 seq 3 2.0 v gnd gnd 500 k +v bat 50 k gnd 1/1 1/2 1/4 1/8 f out set_v cc data select v bat_ok v cc figure 3. block diagram v cc 50 k 1 2 polarity programmable v bat_ok v bat_ok
ncn6000 http://onsemi.com 4 5 v clock_in 1/1 3 v clock_in 1/1 cs i/o a0 a1 reset pgm status program chip dc/dc overloaded card present no card normal chip operation figure 4. programming and normal operation basic timing dc/dc ok 3 v clock_in 1/2 3 v clock_in 1/4 3 v clock_in 1/8 5 v clock_in 1/2 5 v clock_in 1/4 5 v clock_in 1/8 enable crd_clk stop crd_clklow stop crd_clkhigh reserved crd_det = normally open crd_det = normally close crd_det = normally close crd_det = normally close read status = 1> card present/ = 0> no card read status = 1>dc/dcok/ = 0> dc/dc overloaded read vbat status> low = battery ok read crd_v cc status> low = crd_v cc low voltage 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 status h/l h/l l/h h/l pgm l l l l l l l l l l l l l l l l h h h h reset l l l l l l l l h h h h h h h h z z z z a1 l l l l h h h h l l l l h h h h l l h h a0 l l h h l l h h l l h h l l h h l h l h i/o l h l h l h l h l h l h l h l h z z z z
ncn6000 http://onsemi.com 5 the programming can be achieved with the card powered on or off. the identification of the interrupt is carried out by polling the status pin, the vbat voltage and the dc/dc results being provided on the same pin as depicted by the table in figure 4. during the programming mode, the pgm pin can be released to high since the mode is internally latched by the negative going transition presents on the chip select pin. pgm int crd_det card extracted card identification polling 50 m s interrupt acknowledge 50 m s high low low cs a0 a1 status s1 clear interrupt s2 card present: status = 1 s3 clear interrupt s4 card present: status = 0 figure 5. interrupt servicing and card polling when a card is either inserted or extracted, the crd_det pin signal is debounced internally prior to pull the int pin to low. the builtin logic circuit automatically accommodates positive or negative input signal slope, on both insertion and extraction state, depending upon the polarity defined during the initialization sequence. the default condition is normally open switch, negative going card detection. the external cpu shall acknowledge the request by forcing cs = l which, in turn, releases the int pin to high upon positive going of chip select (table 4). polling the status pin as depicted in t able 3 identifies the active card. if a card is present, the status returns high, otherwise a low is presented pin 5. the 50 m s digital filter is activated during both insertion and extraction of the card. the mpu shall clear the int line when the card has been extracted, making the interrupt function available for other purposes. however, neither the ncn6000 operation nor the smart card i/o line or commands are affected by the state of the int pin. on the other hand, clearing the int and reading the status register can be performed by a single read by the mpu: states s1 and s2 can be combined in a single instruction, the same for s3 and s4.
ncn6000 http://onsemi.com 6 abbreviations lout_h dc/dc external inductor lout_l dc/dc external inductor cout output capacitor vcc card power supply input icc current at crd_vcc pin class a 5.0 v smart card class b 3.0 v smart card cs chip select (from mpu) z high impedance logic state (according to iso7816) crd_vcc interface ic card power supply output crd_clk interface ic card clock output crd_rst interface ic card reset output crd_io interface ic card i/o signal line crd_det interface ic card detection atr answer to reset pgm select programming or normal operation int interrupt (to mpu) tr rise time tf fall time td delay time ts storage time pin functions and description pin name type description 1 a0 input this pin is combined with a1, pgm , reset and i/o to program the chip mode of operation and to read the data provided by status. (figures 4 and 5 and tables 2 and 3) 2 a1 input this pin is combined with a0, pgm , reset and i/o to program the chip mode of operation and to read the data provided by status. (figures 4 and 5 and tables 2 and 3) 3 pgm input this pin is combined with a0, a1, reset and i/o to program the chip mode of operation and to read the data provided by status. (figures 4 and 5 and tables 2 and 3) 4 pwr_on input pull down this pin validates the operation of the internal dc/dc converter: cs = l + pwr_on = negative going: dc/dc is off cs = l + pwr_on = positive going: dc/dc is on note: the pwr_on bit must be combined with a low state cs signal to activate the function. (table 2) 5 status output this pin provides logic state related to the card and ncn6000 status. according to the a0, a1 and pgm logic state, this pin carries either the card present status or the vbat or the dc/dc operation state. when pgm = l, status is not affected, see table 2. 6 cs input pull up this pin provides the ncn6000 chip select function. the pwr_on, reset , i/o, a0, a1 and pgm signals are disabled when cs = h. when pgm = l and cs = l, the device jumps to the programming mode (figure 4 and tables 1, 2 and 3). the chip select pin must be a unique physical address when more than one card are controlled by a single mpu. the data presented by the mpu are latched upon positive going edge of the chip select pin.
ncn6000 http://onsemi.com 7 pin functions and description (continued) pin description type name 7 reset input pull down this pin provides two modes of operation depending upon the logic state of pgm pin 3: pgm = 1 : the signal present at this pin is translated to pin 12 (card reset signal) when cs = l and pwr_on = h. it is latched when cs = h. pgm = 0 : the signal present on this pin is used as a logic input to program the internal functions (figure 5 and tables 2 and 3). 8 i/o input/output pull up this pin is connected to an external microcontroller interface. a bidirectional level translator adapts the serial i/o signal between the smart card and the microcontroller. the level translator is enabled when cs = l. the signal present on this pin is latched when cs = h. this pin is also used in programming mode (tables 1, 2 and 3, figures 4 and 5). 9 int output pull down this pin is activated low when a card has been inserted and detected by the interface or when the ncn6000 reports vbat or crd_vcc status (see table 6). the signal is reset to a logic 1 on the rising edge of either cs or pwr_on. the collector open mode makes possible the wired and/or external logic. when two or more interfaces share the int function with a single microcontroller, the software must poll the status pin to identify the origin of the interrupt (figure 5). 10 clock_in clock input high impedance this pin can be connected to either the microcontroller master clock, or to any clock signal, to drive the external smart cards. the signal is fed to internal clock selector circuit and translated to the crd_clk pin at either the same frequency, or divided by 2 or 4 or 8, depending upon the programming mode (tables 1, 2 and 3). care must be observed, at pcb level, to minimize the pickup noise coming from the clock_in line. it is recommended to put a shield, built with a 10 mil copper track, around this line and terminated to the gnd. 11 crd_det input the signal coming from the external card connector is used to detect the presence of the card. a builtin pull up low current source makes this pin active low or high, assuming one side of the external switch is connected to ground. at vbat start up, the default condition is normally open switch, negative going insertion detection. the normally closed switch, positive going insertion detection, can be defined by programming the ncn6000 accordingly. in this case, the polarity must be set up during the first cycles of the system initialization, otherwise an already inserted card will not be detected by the chip. 12 crd_rst output this pin is connected to the reset pin of the card connector. a level translator adapts the reset signal from the microcontroller to the external card. the output current is internally limited to 15 ma. the crd_rst is validated when pwr_on = h and pgm = h and hard wired to ground when the card is deactivated. 13 crd_clk output this pin is connected to the clk pin of the card connector. the crd_clk signal comes from the clock selector circuit output. combining a0, a1, pgm and i/o, as depicted in table 3 and figure 3, programs the clock selection. this signal can be forced into a standby mode with crd_clk either high or low, depending upon the mode defined by the programming sequence (tables 1, 2 and 3 and figure 4). care must be observed, at pcb level, to minimize the pickup noise coming from the crd_clk line. it is recommended to put a shield, built with a 10mil copper track, around this line and terminated to the gnd. 14 crd_io i/o this pin handles the connection to the serial i/o pin of the card connector. a bidirectional level translator adapts the serial i/o signal between the card and the microcontroller. the crd_io pin current is internally limited to 15 ma. a builtin register holds the previous state presents on the i/o input pin. 15 crd_vcc power this pin provides the power to the external card. it is the logic level a1o for crd_io, crd_rst and crd_clk signals. the energy stored by the dc/dc external inductor lout must be smoothed by a 10 m f capacitor, associated with a 100 nf ceramic in parallel, connected across crd_vcc and gnd. in the event of a crd_vcc u vlow voltage, the ncn6000 detects the situation and feedback the information in the status bit. the device does not take any further action, particularly the dc/dc converter is neither stopped nor reprogrammed by the ncn6000. it is up to the external mpu to handle the situation. however, when the crd_vcc is overloaded, the ncn6000 shut off the dc/dc converter, pulls the int pin low and reports the fault in the status register.
ncn6000 http://onsemi.com 8 pin functions and description (continued) pin description type name 16 ground signal the logic and low level analog signals shall be connected to this ground pin. this pin must be externally connected to the pwr_gnd pin 17. the designer must make sure no high current transients are shared with the low signal currents flowing into this pin. 17 pwr_gnd power this pin is the power ground associated with the builtin dc/dc converter and must be connected to the system ground together with ground pin 11. using good quality ground plane is recommended to avoid spikes on the logic signal lines. 18 lout_l power the high side of the external inductor is connected between this pin and lout_h to provide the dc/dc function. the builtin mos devices provide the switching function together with the crd_vcc voltage rectification. 19 lout_h power the high side of the external inductor is connected between this pin and lout_l to provide the dc/dc function. the current flowing into this inductor is limited by a sense resistor internally connected from vbat/pin 20 and pin 19. typically, lout = 22 h, with esr < 2.0 , for a nominal 55 ma output load. 20 vbat power this pin is connected to the supply voltage and monitored by the ncn6000. the operation is inhibited when vbat is below the minimum 2.70 v value, followed by a pwr_down sequence and a low status state. maximum ratings (note 1) rating symbol value unit battery supply voltage vbat 7.0 v battery supply current (note 2) ibat 300 ma power supply voltage vcc 6.0 v power supply current icc 100 ma digital input pins vin 0.5 v < v in < v bat +0.5 v, but < 7.0 v v digital input pins iin 5.0 ma digital output pins vout 0.5 v < v in < v bat +0.5 v, but < 7.0 v v digital output pins iout 10 ma card interface pins vcard 0.5 v < v card < crd_vcc +0.5 v v card interface pins, except crd_clk icard 15 ma inductor current ilout 300 ma esd capability (note 3) standard pins card interface pins and crd_det vesd 2.0 8.0 kv tssop20 package power dissipation @ tamb = +85 c thermal resistance junction to air (r ja ) p ds r ja 320 125 mw c/w operating ambient temperature range ta 25 to +85 c operating junction temperature range tj 25 to +125 c maximum junction temperature (note 4) tjmax +150 c storage temperature range ts g 65 to +150 c 1. maximum electrical ratings are defined as those values beyond which damage to the device may occur at t a = +25 c. 2. this current represents the maximum peak current the pin can sustain, not the ncn6000 consumption (see ibat op ). 3. human body model, r = 1500 w , c = 100 pf. 4. absolute maximum rating beyond which damage to the device may occur.
ncn6000 http://onsemi.com 9 power supply section (25 c to +85 c ambient temperature, unless otherwise noted.) rating symbol pin min typ max unit power supply vbat 20 2.7 6.0 v standby supply current conditions: pwr_on = l, status = h, clock_in = h, cs = h. all other logic inputs and outputs are open: vbat = 3.0 v vbat = 5.0 v ibat sb 20 3.0 8.0 15 m a dc operating current (figure 19) pwr_on = h, clock_in = 0, cs = h, all crd pins unloaded @ vbat = 6.0 v, crd_vcc = 5.0 v @ vbat = 3.6 v, crd_vcc = 5.0 v ibat op 20 7.0 2.0 5.0 ma vbat undervoltage detection high vbat undervoltage detection low vbat undervoltage detection hysteresis vbat lh vbat ll vbat hy 20 2.1 2.0 100 2.7 2.6 v v mv output card supply voltage @ icc = 55 ma @ 2.70 v vbat 6.0 v crd_vcc = 3.0 v crd_vcc = 5.0 v @ vbat ll < vbat < 2.70 v crd_vcc = 5.0 v vcc v c3h v c5h v c5h 15 2.75 4.75 4.50 3.25 5.25 v output card supply peak current @ vcc = 5.0 v @ crd_vcc = 5.0 v @ crd_vcc = 3.0 v @ vbat = 3.6 v, crd_vcc = 5.0 v, tamb < 65 c iccp 15 55 55 65 ma output current limit time out tdoff 15 4.0 ms output over current limit iccov 15 100 ma output dynamic peak current @ crd_vcc = 3.0 v or 5.0 v, cout = 10 m f ceramic xr7, pulse width 400 ns (notes 5 and 6) iccd 15 100 ma battery startup current @ crd_vcc = 3.0 v, 25 c ta + 85 c @ crd_vcc = 5.0 v, 25 c ta + 85 c icc st 20 140 300 ma output card supply voltage ripple @ lout = 22 m h, cout 1 = 10 m f, cout 2 = 100 nf, vbat = 3.6 v iout = 55 ma crd_vcc = 5.0 v (note 5) crd_vcc = 3.0v vcc rip 15 50 50 mv output card supply turn on time @ lout = 22 m f, cout1 = 10 m f, cout2 = 100 nf, vbat = 2.7 v, crd_vcc = 5.0 v vcc ton 15 2.0 ms output card supply shut off time @ cout1 = 10 m f, ceramic, vbat = 2.7 v, crd_vcc = 5.0 v, vcc off < 0.4 v vcc toff 15 250 m s dc/dc converter operating frequency fsw 18 600 khz power switch drain/source resistor r ons 18 1.9 2.2 w output rectifier on resistor r ond 15 2.8 3.4 w 5. ceramic x7r, smd types capacitors are mandatory to achieve the crd_vcc specifications. when electrolytic capacitor is used, t he external filter must include a 100 nf, max 50 m w esr capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. depending upon the pcb layout, it might be necessary is to use two 6.8 m f/10 v/ceramic/x7r//smd1206 in parallel, yielding an improved crd_vcc ripple over the temperature range. 6. according to iso78163, paragraph 4.3.2.
ncn6000 http://onsemi.com 10 digital parameters section @ 2.70 v vbat 6.0 v, normal operating mode (25 c to +85 c ambient temperature, unless otherwise noted.) note: digital inputs undershoot < 0.30 v to ground, digital inputs overshoot <0.30 v to vbat rating symbol pin min typ max unit input asynchronous clock duty cycle = 50% @ vbat = 3.0v over the temperature range f clkin 10 40 mhz clock rise time clock fall time f tr f tf 10 5.0 5.0 ns i/o data transfer switching time, both directions (i/o and crd_io), @ cout = 30 pf i/o rise time* (note 7) i/o fall time t rio t fio 8, 14 0.8 0.8 m s input/output data transfer time, both directions @ 50% crd_vcc, l to h and h to l t tio 8, 14 150 ns minimum pwr_on low level logic state time to power down the dc/dc converter t won 4 2.0 m s crd_vcc power up/down sequence interval t dseq 0.5 2.0 m s status pull up resistance r sta 5 20 50 80 k w chip select cs pull up resistance r cspu 6 20 50 80 k w interrupt int pull up resistance r intpu 9 20 50 80 k w positive going input high voltage threshold (a0, a1, pgm , pwr_on, cs , reset , crd_det) v ih 1, 2, 3, 4, 6, 7, 11 0.70 * vbat vbat v negative going input high voltage threshold (a0, a1, pgm , pwr_on, cs , reset , crd_det) v il 1, 2, 3, 4, 6, 7, 11 0 0.30 * vbat v output high voltage status, int @ i oh = 10 m a v oh 5, 9 vbat 1.0 v v output high voltage status, int @ i oh = 200 m a v ol 5, 9 0.40 v 7. since a 20 k w pull up resistor is provided by the ncn6000, the external mpu can use an open drain connection. digital parameters section @ 2.70 v vbat 6.0 v, chip programming mode (25 c to +85 c ambient temperature, unless otherwise noted.) rating symbol pin min typ max unit a0, a1, pgm , pwr_on, reset and i/o data set up time t smod 1, 2, 3, 4, 7, 8 2.0 m s a0, a1, pgm , pwr_on, reset and i/o data set up time t hmod 1, 2, 3, 4, 7, 8 2.0 m s chip select cs low state pulse width t wcs 6 2.0 m s
ncn6000 http://onsemi.com 11 smart card section (25 c to +85 c ambient temperature, unless otherwise noted.) rating symbol pin min typ max unit crd_rst @ crd_vcc = +5.0 v output reset v oh @ icrd_rst = 20 m a output reset v ol @ icrd_rst = 200 m a output reset rise time @ cout = 30 pf output reset fall time @ cout = 30 pf crd_rst @ vcc = +3.0 v output reset v oh @ icrd_rst = 20 m a output reset v ol @ icrd_rst = 200 m a output reset rise time @ cout = 30 pf output reset fall time @ cout = 30 pf v oh v ol t r t f v oh v ol t r t f 12 crd_vcc 0.9 0 crd_vcc 0.9 0 crd_vcc 0.4 100 100 crd_vcc 0.4 100 100 v v ns ns v v ns ns crd_clk @ crd_vcc = +3.0 v or +5.0 v crd_vcc = +5.0 v output frequency (see note 8) output duty cycle @ dc fin = 50% 1% output crd_clk rise time @ cout = 30 pf output crd_clk fall time @ cout = 30 pf output v oh @ icrd_clk = 20 m a output v ol @ icrd_clk = 100 m a crd_vcc = +3.0 v output frequency (see note 8) output duty cycle @ dc fin = 50% 1% output crd_clk rise time @ cout = 30 pf output crd_clk fall time @ cout = 30 pf output v oh @ icrd_clk = 20 m a @ cout = 30 pf output v ol @ icrd_clk = 100 m a @ cout = 30 pf f crdclk f crddc t r t f v oh v ol f crdclk f crddc t r t f v oh v ol 13 45 3.15 0 40 1.85 0 5.0 55 18 18 crd_vcc +0.5 5.0 60 18 18 crd_vcc 0.7 mhz % ns ns v v mhz % ns ns v v crd_i/o @ crd_vcc = +5.0 v crd_i/o data transfer frequency crd_i/o rise time @ cout = 30 pf crd_i/o fall time @ cout = 30 pf output v oh @ icrd_i/o = 20 m a output v ol @ icrd_i/o = 500 m a, v il = 0 v crd_i/o @ crd_vcc = +3.0 v crd_i/o data transfer frequency crd_i/o rise time @ cout = 30 pf crd_i/o fall time @ cout = 30 pf output v oh @ icrd_i/o = 20 m a output v ol @ icrd_i/o = 500 m a, v il = 0 v f io t rio t fio v oh v ol f io t rio t fio v oh v ol 14 crd_vcc 0.9 0 crd_vcc 0.9 0 315 315 0.8 0.8 crd_vcc 0.4 0.8 0.8 crd_vcc 0.4 khz m s m s v v khz m s m s v v crd_io pull up resistor @ pwr_on = h r crdpu 14 14 20 26 k w card detection debouncing delay: card insertion card extraction t crdin t crdoff 11 50 50 150 150 m s m s card insertion or extraction positive going input high voltage v ihdet 11 0.70 * vbat vbat v card insertion or extraction negative going input low voltage v ildet 11 0 0.30 * vbat v card detection bias pull up current @ vbat = 5.0 v i det 11 10 m a output peak max current under card static operation mode @ vcc = 3.0 v or vcc = 5.0 v icrd_iorst 12, 14 15 ma output peak max current under card static operation mode @ vcc = 3.0 v or vcc = 5.0 v icrd_clk 13 70 ma 8. the crd_clk clock can operate up to 20 mhz, but the rise and fall time are not guaranteed to be fully within the iso7816 spec ification over the temperature range. typically, tr and tf are 12 ns @ crd_clk = 10 mhz.
ncn6000 http://onsemi.com 12 programming and status functions the ncn6000 features a programming interface and a status interface. figure 4 illustrates the programming mode. table 1. programming and status functions pinout logic pins name crd_vcc prg. 3.0 v/5.0 v clock_in divide ratio crd_det clock stop and start poll card status dc/dc status vbat status crd_vcc status 5 status not affected not affected not affected not affected read read read read 6 cs latch on rising edge latch on rising edge latch on rising edge latch on rising edge 0 0 0 0 3 pgm 0 0 0 0 1 1 1 1 1 a0 0/1 0/1 0/1 0/1 0 1 0 1 2 a1 0/1 0/1 1 0 0 0 1 1 7 reset 0 0 1 1 z z z z 8 i/o (in) 0/1 0/1 0/1 0/1 z z z z the pgm signal, pin 3, controls the mode of operation (chip programming or smart card transaction) and must be set up accordingly prior to pull chip select (pin 6) low. table 2. status pin logic output name cs pgm a1 a0 status logic level none h x x x no chip access none l l x x programming mode, no read available card present l h l l low: no card inserted high: card inserted dc/dc l h l h low: dc/dc over range high: dc/dc operates normally vbat l h h l low: vbat within range high: vbat below minimum range crd_vcc overload l h h h low: crd_vcc voltage below minimum range high: crd_vcc in range
ncn6000 http://onsemi.com 13 card vcc, card clock and card detection polarity programming the crd_vcc and clock_in programming options allows matching the system frequency with the card clock frequency, and to select 3.0 v or 5.0 v crd_vcc supply. the crd_det programming option allows the usage of either normally open or normally close detection switch. table 3 highlights the a0, a1, pgm and i/o logic states for the possible options. the default power up reset condition is state 1: asynchronous clock, ratio 1/1, crd_clk active, crd_det = normally open, crd_vcc = 3.0 v . all states are latched for each output variable in programming mode at the positive going slope of chip select [cs ] signal. it is the system designer's responsibility to set up the options needed to match the chip with the peripherals. in particular, when using normally close switch, the crd_det polarity must be defined during the first cycles of the initialization. table 3. card vcc, card clock and card detection polarity truth table hexa cs pwr_on pgm reset a1 a0 i/o crd_vcc crd_clk crd_det status $00 l l l l l l 3.0 v clock_in 1/1 h (note 13) $01 l l l l l h 3.0 v clock_in 1/2 h (note 13) $02 l l l l h l 3.0 v clock_in 1/4 h (note 13) $03 l l l l h h 3.0 v clock_in 1/8 h (note 13) $04 l l l h l l 5.0 v clock_in 1/1 h (note 13) $05 l l l h l h 5.0 v clock_in 1/2 h (note 13) $06 l l l h h l 5.0 v clock_in 1/4 h (note 13) $07 l l l h h h 5.0 v clock_in 1/8 h (note 13) $08 l l h l l l start h (note 13) $09 l l h l l h stop low h (note 13) $0a l l h l h l stop high h (note 13) $0b l l h l h h reserve h (note 13) $0c l l h h l l normally open (note 12) h (note 13) $0d l l h h l h normally close (note 12) h (note 13) $0e l l h h h l normally close (note 12) h (note 13) $0f l l h h h h normally close note 12) h (note 13) $10 l h z l l z card present $12 l 1 h z l h z dc/dc status $14 l h z h l z vbat $16 l 1 h z h h z crd_vcc 9. the programmed conditions are latched upon the chip select (cs , pin 6) positive going transient. 10. card clock integrity is guaranteed no spikes whatever be the frequency switching. 11. the status register is not affected when the ncn6000 operates in any of the programming functions. 12. the crd_vcc and crd_clk are not affected when the ncn6000 operates outside their respective decoded logic address. 13. the high level on status in registors $00 to $0f, inclusive, having being implemented to reduce current comsumption but have no other meanings. 14. at turn on, the ncn6000 is initialized with crd_vcc = 3.0v, clock_in ratio = 1/1, crd_clk = start, crd_det = normally open.
ncn6000 http://onsemi.com 14 dc/dc converter and card detector status the ncn6000 status can be polled when cs = l. please consult figures 4 and 5 for a description of input and output signals. the status message is described in table 4. note: in order to cope with a start up under low battery condition, the vbat ok message uses a negative logic as depicted here below. table 4. card and dc/dc status output pgm a1 a0 status message high l l low no card high l l high card present high l h low dc/dc converter overloaded high l h high dc/dc converter ok high h l low vbat ok high h l high vbat undervoltage high h h high crd_vcc ok high h h low crd_vcc undervoltage the status pin provides a feedback related to the detection of the card, the state of the dc/dc converter, the vbat undervoltage and crd_vcc undervoltage situations. when pgm = h, the status pin returns a high if a card is detected present, a low being asserted if there is no card inserted. in any case, the external card is not automatically powered up. when the external mpu asserts pwr_on = h, together with cs = l, the crd_vcc supply is provided to the card and the state of the dc/dc converter, the vbat and the crd_vcc can be polled through the status pin. card power supply timing at power up, the crd_vcc power supply rise time depends upon the current capability of the dc/dc converter associated with the external inductor l1 and the reservoir capacitor connected across crd_vcc and ground. on the other hand, at turn off, the crd_vcc fall time depends upon the external reservoir capacitor and the peak current absorbed by the internal cmos transistor built across crd_vcc and ground. these behaviors are depicted in figure 6. since these parameters have finite values, depending upon the external constraints, the designer must take care of these limits if the t on or the t off provided by the data sheets does not meet his requirements. figure 6. card power supply turn on and off timing typical crd_vcc rise time @ cout = 10 f, v = 5.0 v typical crd_vcc fall time @ cout = 10 f, v = 5.0 v
ncn6000 http://onsemi.com 15 basic operating modes flow chart the ncn6000 brings all the functions necessary to handle data communication between a host computer and the smart card. the builtin chip select pin provides a simple way to share the same mpu bus with several card interface. on top of that, the logic control are derived from specific pins, avoiding the risk of mixing up the operation when the interface is controlled by a low end microcontroller. during the transaction operation, the external mpu takes care of whatever is necessary to he data on the single bidirectional i/o line. leaving aside the dcdc control and associated failures, the ncn6000 does not take any further responsibility in the data transaction. when the chip operates in the programming mode, the ncn6000 provide a flexible access to set up the crd_vcc voltage, the crd_clk and the crd_det smart card signals. the external micro controller takes care of the smart card transaction and shall handle the interface accordingly. figure 7. operating modes flow chart reset vbat = ok stand by mode select operating mode programming mode set ncn6000 parameters active mode send atr sequence transaction mode end mode power down sequence idle mode finish pwr_on = h cs = h cs = h pgm = h pgm = l cs = l pgm = h cs = l latch ncn6000 parameters pgm = h cs = h standby mode the standby mode allows the ncn6000 to detect a card insertion, keeping the power consumption at a minimum. the power supply crd_vcc is not applied to the card, until the external controllers set pwr_on = h with cs = l. standby mode logic conditions: card output: cs = h pwr_on = h a0 = z a1 = z pgm = z i/o = z reset = z crd_vcc = 0 v crd_clk = l crd_rst = l crd_io = l when a card is inserted, the internal logic filters the signal present pin 11, then asserts the int pin to low if the pulse applied to crd_det is longer than 150 s. the external mpu shall run whatever is necessary to handle the card. the int is cleared (return to high) when a positive going transition is asserted to either the cs or to the pwr_on signal logically combined with chip select = low.
ncn6000 http://onsemi.com 16 programming mode the programming mode allows the configuration of the card power supply, card clock and card detection input logic polarity. these signals (crd_vcc, crd_clk and crd_det) are described in the pin description paragraph associated with tables 1 and 3 and figures 4 and 8. programming mode logic conditions: card output: cs = l pwr_on = l a0 = h/l a1 = h/l pgm = l i/o = l/h reset = l/h crd_vcc = 0 v crd_clk = l crd_rst = l crd_io = h/l depending upon the previous i/o pin logic state the i/o and reset pins are not connected to the smart card and become logic inputs to control the ncn6000 programming sequence. the programmed values are latched upon transition of cs from low to high, pgm being low during the transition. when a programming mode is validated by a chip select negative going transient, the mode is latched and pgm can be released to high. this latch is automatically reset when cs returns to high. the logic input signals can be set simultaneously, or one bit a time (using either a staa or a bset function), the key point being the minimum delay between the shorter bit and the chip select pulse. the programmed value is latched into the ncn6000 register on the cs positive going edge. programming 2 m s2 m s 1 m s normal mode pgm i/o a0 a1 reset cs figure 8. minimum programming timings active mode in the active mode, the ncn6000 is selected by the external mpu and the status pin can be polled to get the status of either the dc/dc converter or the presence of the card (inserted or not valid). the power is not connected to the card: crd_vcc = 0 v. active mode logic conditions: card output: cs = l pwr_on = l a0 = l a1 = l pgm = h i/o = z reset = z status = l/h is card inserted? crd_vcc = 0 v crd_clk = l crd_rst = l crd_io = h/l depending upon the previous i/o pin logic state the chip select pulse [cs ] will automatically clear the previously asserted int signal upon the positive going transition. if a card is present, the mpu shall activate the dc/dc converter by asserting pwr_on = h. the ncn6000 will automatically run a power up sequence when the crd_vcc reaches the undervoltage level (either v c5h or v c3h , depending upon the crd_vcc voltage supply programmed). the crd_io, crd_rst and crd_clk pins are validated, according to the iso78163 sequence. the interface is now in transaction mode and the system is ready for data exchange through the i/o and reset lines. at any time, the micro controller can change the crd_clk frequency and mode, or the crd_vcc value as determined by the card being in use.
ncn6000 http://onsemi.com 17 transaction mode during the transaction mode, the ncn6000 maintains power supply and clock signal to the card. all the signal levels related with the card are translated as necessary to cope with the mpu and the card. the dc/dc converter status and the vbat state can be monitored on the status by using the a0 and a1 logic inputs as depicted tables 3 and 4. transaction mode logic conditions: card output: cs = l pwr_on = h a0 = h a1 = h pgm = h i/o = data transfer reset = h/l status = l/h dc/dc status: fail/pass? crd_vcc = 3.0 or 5.0 v crd_clk = clock crd_rst = h/l crd_io = data transfer to make sure the data are not polluted by power losses, it is recommended to check the state of crd_vcc before launching a new data transaction. since cs = l, this is achieved by forcing bits a0 and a1 according to table 4, and reading the status pin 5. idle mode the idle mode is used when a card is powered up (crd_vcc = vcc), without communication on going. idle mode logic conditions: card output: cs = l pwr_on = h a0 = h a1 = h pgm = h i/o = z reset = h status = l/h according to the internal register results crd_vcc = 3.0 or 5.0 v crd_clk = clock active or l or h crd_rst = h crd_io = z in addition, the crd_clk signal can be stopped, as depicted in tables 3 and 4, to minimize the current consumption of the external smart card, leaving crd_vcc active. power down operation the power down mode can be initiated by either the external mpu (pulling pwr_on = l) or by one of the internal error condition (crd_vcc overload or vbat low). the communication session is terminated immediately, according to the iso78163 sequence. on the other hand, the mpu can run the standby mode by forced cs = h. when the card is extracted, the interface shall detect the operation and run the power shut off of the card as described by the iso/cei 78163 sequence depicted here after: iso78163 sequence: ? force rst to low ? force clk to low, unless it is already in this state ? force crd_io to low ? shut off the crd_vcc supply since the internal digital filter is activated for any card insertion or extraction, the physical power sequence will be activated 150 s maximum after the card has been extracted. of course, such a delay does not exist when the mpu launch the power down intentionally. the time delay between each negative going signal is 500 ns typical (figure 10).
ncn6000 http://onsemi.com 18 card extraction detected crd_vcc voltage crd_clk crd_rst crd_io digital filter delay (50 m s min) figure 9. typical power down sequence in the ncn6000 interface figure 10. power down sequence details crd_vcc crd_clk crd_rst crd_io
ncn6000 http://onsemi.com 19 card detection the card detector circuit provides a 500 k pull up resistor to bias the crd_det pin, yielding a logic high when the pin is left open (assuming a no switch). the internal logic associated with pin 11 provides an automatic selection of the slope card detection, depending upon the polarity set by the external mpu. at start up, the crd_det is preset to cope with normally open switch. when a normally close switch is used in the card socket, it is mandatory to program the ncn6000 chip during the initialization sequence, otherwise the system will not start if a card was previously inserted. table 3 gives the programming code for such a function. the next lines provide a typical assembler source to handle this crd_det normally close polarity: smart equ $20 ldx #$1000 ldaa #$09 staa smart, x ; ncn6000 physical cs address ; offset ; i/o = h, a0 = a1 = l, reset = h ; set crd_det = normally closed switch the crd_det polarity can be updated at any time, during the program mode sequence (pgm = l), but, generally speaking, is useless since the switch does not change during the usage of the considered module. on the other hand, the card detection switch shall be connected across pin 11 and ground, for any polarity selected. the transition presents pin 11, whatever be the polarity, is filtered out by the internal digital filter circuit, avoiding false interrupt. in addition to the minimum internal 50 s timing, the mpu shall provide an additional delay to cope with the mechanical stabilization of the card interface (typically 3 ms), prior to valid the crd_vcc supply. when a card is inserted, the detector circuit asserts int = low as depicted before. when the ncn6000 detects a card extraction, the power down sequence is activated, regardless of the pwr_on state, and the int pin is asserted low. it is up to the external mpu to clear this interrupt by forcing a chip select pulse as depicted in figure 5. the 75 s delay represent the digital filter builtin the ncn6000 chip being used for the characterization. any pulse shorter than this delay does not generate an interrupt. however, to guarantee an interrupt will be generated, the crd_det signal must be longer than 150 s as defined by the specification. the chip select pulse is generated by the external micro controller, the minimum pulse width being 2 s to make sure the card is detected. the oscillogram, figure 11, depicts the behavior for a normally open switch, the delay existing between the interrupt negative going state and the cs being low comes from the particular software latency existing in this particular mpu. figure 11. card insertion detection and interrupt signals digital filter delay interrupt chip select acknowledge or clear interrupt
ncn6000 http://onsemi.com 20 crd_det input voltage (card extracted) digital filter delay interrupt chip select acknowledge or clear interrupt figure 12. card extraction detection and interrupt signals when the card is extracted, the crd_det signal generates an interrupt, assuming the positive pulse width is longer than the digital filter. the oscillogram, figure 12, depicts the behavior for a normally open switch. note: since the internal pull up resistor is relatively high (500 k w typical), one must use a 10 m w input impedance probe to read this signal. crd_det input voltage (card inserted) interrupt chip select figure 13. interrupt acknowledgement during a card insertion detection sequence the interrupt signal, provided pin 9, is cleared by a positive going chip select signal as depicted by the oscillogram, figure 13. the cs pulse width is irrelevant, as long as it is larger than 2.0 s, to activate a different sequence. leaving the interrupt signal low has no influence on the internal behavior of the ncn6000, but will be automatically cleared when the dc/dc will be activated by the mpu (cs =l, pwr_on = positive high transition)
ncn6000 http://onsemi.com 21 power management the purpose of the power management is to activate the circuit functions needed to run a given mode of operation, yielding a minimum current consumption on the vbat supply. in the standby mode (pwr_on = l), the power management provides energy to the card detection circuit only. all the card interface pins are forced to ground potential. in the event of a power up request coming from the external mpu (pwr_on = h, cs = l), the power manager starts the dc/dc converter. when the crd_vcc voltage reaches the programmed value (3.0 v or 5.0 v), the circuit activates the card signals according to the following sequence: crd_vcc ? crd_io ? crd_clk ? crd_rst the logic level of the data lines are asserted high or low, depending upon the state forced by the external mpu, when the start up sequence is completed. under no situation the ncn6000 shall launch automatically a smart card atr sequence. assuming pwr_on = h, the crd_vcc voltage is maintained whatever be the logic level presents on chip select, pin 6. at the end of the transaction, asserted by the mpu (pwr_on = l, cs = l), or under a card extraction, the iso78163 power down sequence takes place: crd_rst ? crd_clk ? crd_io ? crd_vcc when cs = h, the bidirectional i/o line (pins 8 and 15) is forced into the high impedance mode to avoid signal collision with any data coming from the external mpu. the crd_vcc voltage is controlled by means of cs and pwr_on logic signal as depicted figure 14. the pwr_on logic level define the crd_vcc voltage status, the amplitude being the one pre programmed into the chip. in order to avoid uncontrolled command applied to the smart card, the ncn6000 internal logic circuit, together with the vbat monitoring, clamps the card outputs until the crd_vcc voltage reaches the minimum value. during the crd_vcc slope, all the card outputs are kept low and no spikes can be write to the smart card. the oscillogram on the right hand side is a magnification of the curves given on the opposite side. cs pwr_on crd_vcc crd_vcc rise time crd_vcc no change crd_vcc power down fall time crd_vcc no change 250 m s 2 ms figure 14. card power supply control figure 15. smart card signals sequence at power on crd_vcc crd_clk cp = 15 pf crd_rst crd_io 5.0 v crd_vcc crd_clk crd_rst crd_io 5.0 v cp = 15 pf
ncn6000 http://onsemi.com 22 vbat supply voltage monitoring the builtin comparator, associated with the band gap reference, continuously monitors the +vbat input. during the start up, all the ncn6000 functions are deactivated and no data transfer can take place. when the +vbat voltage rises above 2.35 v (typical), the chip is activated and all the functions becomes available. the typical behavior is provided here after figure 16. at this point, the internal power on reset signal is activated (not accessible externally) and all the logic signals are forced into the states as defined by table 3. if the +vbat voltage drops below 2.25 v (typical) during the operation, the ncn6000 generate a power down sequence and is forced in a no operation mode. the builtin 100 mv (typical) hysteresis avoids unstable operation when the battery voltage slowly varies around the 2.30 v. on the other hand, the micro controller can read the status signal, pin 5, to control the state of the battery prior to launch either a ncn6000 programming or an atr sequence (table 4). 2.80 v figure 16. typical vbat monitoring vbat 2.35 v 2.25 v 3.30 v vbat_ok vbat status note: drawing is not to scale and voltages are typical. see specifications data for details. dc/dc converter operation the builtin dc/dc converter is based on a modified boost structure to cover the full battery and card operating voltage range. the builtin battery voltage monitor provides an automatic system to accommodate the mode of operation whatever be the vbat and crd_vcc voltages. comparator u3/figure 17 tracks the two voltages and set up the operating mode accordingly. u2 + u3 v ref - + mos drive substrat bias u1 pwr_on 3 v/ 5 v overload vcc_ok r1 1r current sense 20 19 18 15 17 v bat v bat l2 22 m h l out_l l out_h + gnd crd_vcc c1 gnd gnd gnd v out _3_5 v ref _3/5 v voltage regulation v bat q3 q1 q2 gnd v bat v bat /v cc comparator nmos gate drive pmos gate drive logic control gnd pwr_gnd gnd figure 17. basic dc/dc structure + r2 r3 r4 active pull down gnd q4
ncn6000 http://onsemi.com 23 when the input voltage vbat is lower than the programmed crd_vcc, the system operates under the boost mode, providing the voltage regulation and current limit to the smart card. in this mode, the external inductor, typically 22 h, stores the energy to drive the +5.0 v card supply from the external low voltage battery. the oscillogram, figure 18, depicts the dc/dc behavior under these two modes of operation. beside the dc/dc converter, nmos q4 provides a low impedance to ground during the power down sequence, yielding the 250 s maximum switch time depicted in the data sheet. figure 18. dc/dc operating modes step down mode crd_vcc 5 v step up mode crd_vcc i l ibat dc operating current @ crd_vcc = 5.0 v 0 1 2 3 4 5 6 7 8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vbat (v) ibat_op (ma) 25 c 85 c power_on figure 19. typical dc operating current 25 c when the input voltage vbat is higher than the programmed crd_vcc, the system operates under a step down mode, yielding the voltage regulation and current limit identical to the boost mode. in this case, the builtin structure turns off q1 and inverts the q2 substrate bias to control the current flowing to the load.these operations are fully automatic and transparent for the end user. the high and low limits of the current flowing into the external inductor l1 are sensed by the operational amplifier u1 associated with the internal shunt r1. since this shunt resistor is located on the hot side of the inductor, the device reads both the charge and discharge of the inductor, providing a clean operation of the converter. in order to optimize the dc/dc power conversion efficiency, it is recommended to use external inductor with r < 2.0 w . the output capacitor c1 stores the energy coming from the converter and smooths the crd_vcc voltage applied to the external card. at this point, care must be observed, beside the micro farad value, to select the right type of capacitor. according to the capacitor's manufacturers, the internal esr can range from a low 10 m w to more than 3.0 w , thus yielding high losses during the dc/dc operation, depending upon the technology used to build the capacitor. the standard electrolytic capacitors have the low cost advantage for a relative high micro farad value, but have poor tolerance, high leakage current and high esr. the tantalum type brings much lower leakage current together with high capacity value per volume, but cost can be an issue and esr is rarely better than 500 m w . the new ceramic type have a very low leakage together with esr in the 50 m w range, but value above 10 f are relatively rare. moreover, depending upon the low cost ceramic material used to build these capacitors, the thermal coefficient can be very bad, as depicted in figure 20. the x7r type is highly recommended to achieve low voltage ripple. figure 20. typical y7r ceramic type value as a function of the temperature. 100% 25 c +25 c +85 c 15%
ncn6000 http://onsemi.com 24 based on the experiments carried out during the ncn6000 characterization, the best comprise, at time of printing this document, is to use two 6.8 f/10 v/ceramic/x7r capacitor in parallel to achieve the crd_vcc filtering. the esr will not extend 50 m w over the temperature range and the combination of standard parts provide an acceptable 20% to +20% tolerance, together with a low cost. obviously, the capacitor must be smd type to achieve the extremely low esr and esl necessary for this application. figure 21 illustrates the crd_vcc ripple observed in the ncn6000 demo board depending upon the type of capacitor used to filter the output voltage. table 5. ceramic/electrolytic capacitors comparison manufacturers type/series format max value tolerance typ. z @ 500 khz murata ceramic/grm225 0805 10 f/6.3 v +80%/20% 30 m vishay tantalum/594c/593c 10 f/16 v 450 m vishay electrolytic/94sv 10 f/10 v 20%/+20% 400 m electrolytic low cost 10 f/10 v 35%/+50% 2.0 top trace = electrolytic or tantalum 10 f bottom trace = x7r 10 f ceramic the high ripple pulse across crd_vcc is the consequence of the large esr of the electrolytic capacitor. figure 21. crd_vcc ripple as a function of the capacitor technology c= 10 f electrolytic or tantalum c= 10 f ceramic notes: rload = 100 w , vbat = 5.0 v, crd_vcc = 5.0 v cout = 10 f/x7r, crd_clk = stop high figure 22. external capacitor current charge and crd_vcc voltage ripple. figure 23. crd_vcc voltage ripple
ncn6000 http://onsemi.com 25 clock divider the main purpose of the builtin clock generator is threefold: 1. adapts the voltage level shifter to cope with the different voltages that might exist between the mpu and the smart card. 2. provides a frequency division to adapt the smart card operating frequency from the external clock source. 3. controls the clock state according to the smart card specification. in addition, the ncn6000 adjusts the signal coming from the microprocessor to get the duty cycle window as defined by the iso78163 specification. the logic input pins a0, a1, pgm , i/o and reset fulfill the programming functions when both pgm and cs are low. the clock input stage (clock_in) can handle a 40 mhz frequency maximum, the divider being capable to provide a 1:8 ratio. of course, the ratio must be defined by the engineer to cope with the smart card considered in a given application and, in any case, the output clock [crd_clk] shall be limited to 20 mhz maximum signal. in order to maximize the clock_in bandwidth, this pin has no schmitt trigger input. the simple associated cmos has a vbat/2 threshold level. in order to minimize the di/dt and dv/dv developed in the crd_clk line, the peak current as been internally limited to 30 ma peak (typical @ crd_vcc = 5.0 v), h ence limited the rise and fall time to 10 ns typical. consequently, the ncn6000 fulfills the iso7816 specification up to 10 mhz maximum, but can be used up to 20 mhz when the final application operates in a limited ambient temperature range. level shifter & control 3 3 clock_in pgm cs reset i/o a0 a1 +3.0 v +5.0 v clock & v cc programming block crd_v cc crd_clk 1 2 1 2 3 3 figure 24. simplified frequency divider and programming functions in order to avoid any duty cycle out of the frequency smart card iso78163 specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio. consequently, the output crd_clk frequency division can be delayed by eight clock_in pulses and the microcontroller software must take this delay into account prior to launch a new data transaction.
ncn6000 http://onsemi.com 26 the example given by the oscillogram here above highlights the delay coming from the internal clock duty cycle resynchronization. in this example, the clock is internally divided by 2 prior to be applied to the crd_clk pin. since the clock signal is asynchronous, it is up to the programmer to make sure the next card transaction is not activated before the crd_clk signal has been updated. generally speaking, such a delay can be derived from the maximum clock frequency provided to the interface, keeping in mind the maximum delay is eight incoming clock pulses. figure 25. clock programming examples the clock can be reprogrammed without halting the rest of the circuit, whatever be the new clock divider ratio. in particular, the crd_vcc can be applied to the card while the clock is reprogrammed.
ncn6000 http://onsemi.com 27 figure 26. command stop clock high the crd_clk signal is halted in the high logic state, following the chip select positive going transition. logic input conditions: pgm = low a0 = low reset = low a1 = low i/o = low cs = low pulsed figure 27. command stop clock low the crd_clk signal is halted in the low logic state, following the chip select positive going transition. logic input conditions: pgm = low a0 = low reset = low a1 = low i/o = high cs = low, pulsed
ncn6000 http://onsemi.com 28 figure 28. command resume clock normal operation the crd_clk signal is resumed in the normal operation, following the chip select positive going transition. the previous halted state is irrelevant and the clock signal is synchronized with the internal clock divider to avoid non crd_clk 50% duty cycle. pgm = low a0 = low reset = high a1 = low i/o = low cs = low, pulsed crd_clk c3 fall 8.255 ns cp = 30 pf crd_clk c3 rise 7.900 ns cp = 30 pf figure 29. card clock rise and fall time since the crd_clk signal can generate very fast transient (i.e. tr = 2.5 ns @ cp = 10 pf), adapting the design to cope with the emv noise specification might be necessary at final check out. using an external rc network is a way to reduce the dv/dt, hence the emi noise. typically, the external series resistor is 10 w , the total capacitance being 30 pf to 50 pf
ncn6000 http://onsemi.com 29 bidirectional level shifter the ncn6000 carries out the voltage difference between the mpu and the smart card i/o signals. when the start sequence is completed, and if no failures have been detected, the device becomes essentially transparent for the data transferred on the i/o line. to fulfill the iso78163 specification, both sides of the i/o line have built in pulsed circuitry to accelerate the signal rise transient. the i/o line is connected on both side of the interface by a nmos switch which provide the level shifter and, thanks to its relative high internal impedance, protects the smart card in the event of data collision. such a situation could occurs if either the mpu of the smart card forces a signal in the opposite logic level direction. when the cs signal goes high, or if the mpu is running any of the programming functions, the built in register holds the previous state presents on the input i/o pin. this mechanism is useful to force the crd_io card pin in either a high or a low predefined logic state. it is the responsibility of the programmer to set up the i/o line according to the system's activity device q4 provides a low impedance to ground when the crd_io line is deactivated. this mechanism avoids noise presence on this line during any of the power operation. when either side of this level shifter is forced to low, the externally connected device will be forward biased by the dc current flowing through the pull up resistors as depicted in figure 30. since these two resistors will carry 350 a max each under the worst case conditions, care must be observed to make sure the external device will be capable to handle this level of current. note: the typical series impedance of the internal mos device (q3, figure 30) is 400 w . the oscillograms figure 31 give the worst case operation when the stray capacitance is 15 pf. q1 q2 q3 gnd v bat i/o 200 ns 20 k 20 k crd_io q4 crd_vcc logic card enable seq 1 figure 30. basic internal i/o level shifter 200 ns figure 31. typical crd_io rise time i/o crd_io crd_vcc = 5.0 v note: the i/o data depends solely upon the smart card atr content, the ncn6000 being not involved in these data. figure 32. typical i/o and rst signals during an atr sequence. crd_vcc i/o card answer request sends on crd_rst line ncn6000 chip select crd_vcc = 3.0 v
ncn6000 http://onsemi.com 30 input schmitt triggers all the logic input pins have builtin schmitt trigger circuits to prevent the ncn6000 against uncontrolled operation. the typical dynamic characteristics of the related pins are depicted in figure 33. the output signal is guaranteed to go high when the input voltage is above 0.70*vbat, and will go low when the input voltage is below 0.30*vbat. the clock_in pin has been design to provide a 40 mhz bandwidth clock receiver input, capable to drive the internal clock divider. this front end circuit yields a constant duty cycle signal, according to the iso specification, to the external smart card, even when the ncn6000 division ratio is 1:1. output v bat on off v bat 0.70 *v bat figure 33. typical schmitt trigger characteristic input 0.30 *v bat interrupt function the ncn6000 flags the external microprocessor by pulling down the int signal provided in pin 9. this signal is activated by one of the here below referenced operations. table 6. interrupt functions pin related clear function status pin 5 card insertion and extraction 11 positive going chip select, or logical combination of chip select low and pwr_on positive going high = card presents low = no card inserted dc/dc converter overloaded 15 positive going chip select, or logical combination of chip select low and pwr_on positive going high = dc/dc operates normally low = output crd_vcc overloaded leaving the int pin low has no influence on the ncn6000 internal behavior. it is up to the engineering to decide when and how the interrupt will be cleared from this pin. as described before, this can be achieved by either providing a chip select positive transient, or by starting the dc/dc converter with the standard command pwr_on = h and cs =l.
ncn6000 http://onsemi.com 31 security features in order to protect both the interface and the external smart card, the ncn6000 provides security features to prevent catastrophic failures as depicted here after. pin current limitation: in the case of a short circuit to ground, the current forced by the device is limited to 15 ma for any pins, except crd_clk pin. no feedback is provided to the external mpu. dc/dc operation: the internal circuit continuously senses the crd_vcc voltage and, in the case of either over or undervoltage situation, update the status register accordingly. this register can be read out by the mpu. battery voltage: both the over and undervoltage are detected by the ncn6000, a power_down sequence and the status register being updated accordingly. the external mpu can read the status pin to take whatever is appropriate to cope with the situation. esd protection the ncn6000 includes silicon devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed across these pins, the builtin structures have been designed to handle either 2.0 kv, when related to the microcontroller side, or 8.0 kv when connected with the external contacts. practically, the crd_rst, crd_clk, crd_io and crd_det pins can sustain 8 kv, the digital pins being capable to sustain 2 kv. the crd_vcc pin has the same 8 kv esd protection, but can source up to 55 ma continuously, the absolute maximum current being 100 ma. to save as much battery current as possible when no card is inserted, one should use a normally open card detection switch connected pin 11. since the internal card detection circuit source 10 a (typical) to bias the switch, using a normally open avoid this direct sink to ground from the battery. parallel operation when two or more ncn6000 operate in parallel on a common digital bus, the chip select pin allows the selection of one chip from the bank of the paralleled devices. of course, the external mpu shall provide one unique cs line for each of the ncn6000 considered interfaces. when a given interface is selected by cs = l, all the logic inputs becomes active, the chip can be programmed or/and the external card can be accessed. when cs = h, all the input logic pins are in the high impedance state, thus leaving the bus available for other purpose. on the other hand, when cs = h, the crd_io and crd_rst hold the previous i/o and reset logic state, the crd_clk being either active or stopped, according to the programmed state forced by the mpu. since there is one single i/o line to communicate with the external microcontroller, one should provide a software routine to save the code when data exchanged are performed between the two cards. generally speaking, the internal microcontroller ram can be used to support such a transaction. the crd_vcc voltage and crd_clk signal of each ncn6000 can be operated simultaneously, these two pins being activated even when the related chip select is high. as depicted figure 14, the dc/dc converter is not deactivated when pwr_on goes to low when cs = high. minimum power consumption to achieve a minimum current consumption, the interface shall be programmed as follow: 1. turn off the dcdc converter : this will disconnect the smart card if still inserted in the socket), reducing the power supply to the minimum needed to control the interface. 2. force the input signals to a logic high to avoid current flowing through the pull up resistors. this applies to the here below table: int pin 9 cs pin 6 status pin 5 i/o pin 8 crd_io pin 14 to save as much battery current as possible when no card is inserted, one should use a normally open card detection switch connected pin 11 to ground. since the internal card detection circuit source is 10 a (typical), using such a no switch saves the direct sink to ground current from the battery to ground. during this mode of operation, the only active sub functions are the card detection and the battery monitoring. the activity resume immediately after either a card insertion, or a cs = low signal applied to pin 6.
ncn6000 http://onsemi.com 32 printed circuit board layout since the ncn6000 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. a typical singlesided pcb layout is provided in figure 34 highlighting the ground technique. the card socket uses a low cost iso only version, all the parts being located on the component side. connector j3 makes reference to the microcontroller used by the final application. of course, the connector is not necessary and standard copper tracks might be used to connect the mpu to the ncn6000 interface chip. 2335 mis (60 mm) 2760 mis (70 mm) u1 ncn6000 smartcard iso contacts mpu v supply +v bat c4 clk rst ground c8 i/o v pp gnd figure 34. typical single sided printed circuit board layout application note a partial schematic diagram of the demo board designed to support the ncn6000 applications is depicted figure 35. this schematic diagram highlights the interface between the micro controller and the smart card, leaving aside the peripherals used to control the mpu. conclusion from a practical stand point, the crd_vcc output capacitor has been split into two 6.8 f/10 v/x7r, one being located as close as possible across pins 13 and 17 of the ncn6000, the second one being located close by the smart card physical connector. on the other hand, cares have been observed to minimize the cross coupling between the clock signals (both input and crd_clk) and the other signals presents on the board. the micro controller holds the software necessary to program the ncn6000, together with the code handling the t0 operation. provisions are made to provide a communication link with an external computer by using the rs232 standard port. thanks to the chip select signal, several ncn6000 can share a common data bus as depicted figure 36. in this example, two interfaces are connected to a single mpu, the cs pins being controlled by two different signals.
ncn6000 http://onsemi.com 33 figure 35. ncn6000 single interface demo board gnd pc0 pc1 pc2 pc3 pc4 pc5 pc7 xirq pc6 l1 22 m h 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 a0 a1 pgm pwr_on status cs reset i/o int clock_in v bat l out_h l out_l pwr_gnd ground crd_v cc crd_io crd_clk crd_rst crd_det c2 smartcard_b j2 iso7816 gnd ncn6000 vcc 10 m f/6.3 v u1 c1 c9 4.7 m f/10 v a0 a1 pgm pwr_on status cs reset i/o clk c8 i/o vpp gnd c4 clk rst vcc swb e pd0/rxd pd1/td pd2 9 10 11 12 13 14 15 16 20 19 5 20 21 22 pa4 pa5 pa6 pa7 xtal 30 29 28 27 in reset gnd c11 2.2 m f 16 v reset sw13 u5 mc34164 c10 4.7 m f/10 v gnd 0.1 m f/25 v swa 8 7 6 5 4 3 2 1 18 17 gnd gnd irq r7 4.7k vcc 16 int pd3 23 pd4 24 pd5 25 tx rx r8 4.7k r10 4.7k vcc vcc vss vrl vrh modb moda c4 0.1 m f/25 v r14 10 r gnd r20 4.7 k r21 4.7 k vcc 51 52 2 4 3 6 stra strb rst 17 1 r9 4.7k vcc r16 220 r vcc gnd r16 220 r gnd 1 3 2 1 2 3 4 5 6 vcc r6 10 m c6 22 pf c7 22 pf y1 8 mhz gnd gnd vcc c2 0.1 m f/25 v gnd 10 m f/6.3 v c1 extal 26 7 8 vdd pa0 pa1 pa2 pa3 34 33 32 31 pe0 pe1 pe2 pe3 43 45 47 49 pe4 pe5 pe6 pe7 44 46 48 50 pb7 pb6 pb5 pb4 35 36 37 38 pb3 pb2 pb1 pb0 39 40 41 42 u1 68hc11e9 sw dip2 1 = mode b 2 = mode a s? r1 10k
ncn6000 http://onsemi.com 34 figure 36. ncn6000 single interface demo board gnd pc0 pc1 pc2 pc3 pc4 pc5 pc7 xirq pc6 l1 22 m h 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 a0 a1 pgm pwr_on status cs reset i/o clock_in v bat l out_h l out_l pwr_gnd ground crd_v cc crd_io crd_clk crd_rst crd_det c2 gnd vcc 10 m f/6.3 v u1 c1 a0 a1 pgm pwr_on status cs reset i/o c8 i/o vpp gnd c4 clk rst vcc swb e pd0/rxd pd1/td pd2 9 10 11 12 13 14 15 16 20 19 5 20 21 22 pa4 pa5 pa6 pa7 xtal 30 29 28 27 in reset gnd c11 2.2 m f 16 v reset sw13 u5 mc34164 gnd 0.1 m f/25 v swa 8 7 6 5 4 3 2 1 18 17 gnd gnd irq r5 4.7k 16 pd3 23 pd4 24 pd5 25 tx rx r6 4.7k r7 4.7k vcc vcc vss vrl vrh modb moda c5 0.1 m f/25 v r8 10 r gnd r9 4.7 k r10 4.7 k vcc 51 52 2 4 3 6 stra strb rst 17 1 r4 4.7k vcc r16 220 r gnd r16 220 r gnd 1 3 2 1 2 3 4 5 6 vcc r6 10 m c6 22 pf c7 22 pf y1 8 mhz gnd gnd vcc c2 0.1 m f/25 v gnd 10 m f/6.3 v c1 extal 26 7 8 vdd pa0 pa1 pa2 pa3 34 33 32 31 pe0 pe1 pe2 pe3 43 45 47 49 pe4 pe5 pe6 pe7 44 46 48 50 pb7 pb6 pb5 pb4 35 36 37 38 pb3 pb2 pb1 pb0 39 40 41 42 u1 68hc11e9 sw dip2 1 = mode b 2 = mode a s1 a0 a1 pgm pwr_on status cs reset i/o int clock_in v bat l out_h l out_l pwr_gnd ground crd_v cc crd_io crd_clk crd_rst crd_det ncn6000 u1 clk vcc int l1 22 m h 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 a0 a1 pgm pwr_on status cs reset i/o int clock_in v bat l out_h l out_l pwr_gnd ground crd_v cc crd_io crd_clk crd_rst crd_det 1 2 3 4 5 6 7 8 9 a0 a1 pgm pwr_on status cs reset i/o int clock_in v bat l out_h l out_l pwr_gnd ground crd_v cc crd_io crd_clk crd_rst crd_det iso7816 smartcard_b j2 r2 10k gnd c8 i/o vpp gnd c4 clk rst vcc swb swa 8 7 6 5 4 3 2 1 18 17 iso7816 smartcard_b j2 u1 ncn6000 gnd c10 4.7 m f/10 v c9 4.7 m f/10 v
ncn6000 http://onsemi.com 35 summary subject page pin functions and description 6 maximum ratings 8 power supply section 9 digital parameters section 10 smart card interface section 11 programming and status functions 12 card vcc, card clock and card detection polarity programming 13 dc/dc converter and card detector status 14 card power supply timings 14 basic operating mode flow chart 15 standby mode 15 programming mode 16 active mode 16 transaction mode 17 idle mode 17 card power down mode 17 card detection 19 power management 21 vbat supply voltage monitoring 22 dc/dc converter operation 22 clock divider 25 bidirectionnal level shifter 29 input schmitt triggers 30 interrupt functions 30 security features 31 esd protection 31 multi card parallel operation 31 minimum power cunsumption 31 printed circuit board layout 32 application note 32 package outline dimensions 36 conclusion 32 figure index fig. # title page 1 simplified application diagram 1 2 typical application diagram 2 3 block diagram 3 4 programming and normal operation basic timing 4 5 interrupt servicing and card polling 5 6 card power supply turn on and off timing 14 7 operating modes flow chart 15 8 minimum programming timings 16 9 typical power down sequence in the ncn6000 interface 18 10 power down sequence details 18 11 card insertion detection and interrupt signals 19 12 card extraction detection and interrupt signals 20 13 interrupt acknowledgement during a card insertion detection sequence. 20 14 card power supply control 21 15 smart card signals sequence at power on 21 16 typical vbat monitoring 22 17 basic dc/dc structure 22 18 dcdc operating modes 23 19 typical dc operating current 23 20 typical y7r ceramic type value as a function of the temperature. 23 21 crd_vcc ripple as a function of the capacitor technology 24 22 external capacitor current charge and crd_vcc voltage ripple 24 23 crd_vcc voltage ripple 24 24 simplified frequency divider and programming functions 25 25 clock programming examples 26 26 command stop clock high 27 27 command stop clock low 27 28 command resume clock normal operation 28 29 card clock rise and fall time 28 30 basic internal i/o level shifter 29 31 typical crd_io rise time 29 32 typical i/o and rst signals during an atr sequence 29 33 typical schmitt trigger characteristic 30 34 typical single sided printed circuit board layout 32 35 ncn6000 single interface demo board 33 36 typical dual interface application 34
ncn6000 http://onsemi.com 36 package dimensions tssop20 dtb suffix case 948e02 issue a dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. 110 11 20 pin 1 ident a b t 0.100 (0.004) c d g h section nn k k1 jj1 n n m f w seating plane v u s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 --- --- s u 0.15 (0.006) t on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its p roducts for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, i ncluding atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor t he rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative a ction employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncn6000/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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