View PI7C7100CNA_5720057.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

09/18/00 rev 1.1 pi7c7100 3-port pci bridge the complete interface solution 2380 bering drive, san jose, california 95131 telephone: 1-877-pericom, (1-877-737-4266) fax: (408) 435-1100, e-mail: nolimits@pericom.com internet: http://www.pericom.com ? 2000 pericom semiconductor corporation pericom semiconductor corporation rev 1.1
ii 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 life support policy pericom semiconductor corporations products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of psc. 1.life support devices or systems are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.pericom semiconduc tor corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to impro ve design or performance and to supply the best possible product. pericom semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a pericom semiconductor product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of peri com semiconductor corporation. all other trademarks are of their respective companies.
iii 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456 7 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 1. introduction/product features ............................................................................................................................... 1 2. pi7c7100 block diagram ............................................................................................................................... ....... 3 3. signal definitions ............................................................................................................................... .................... 4 3.1 signal types ................................................................................................................ ............................................ 4 3.2 signals ..................................................................................................................... ................................................. 4 3.2.1 primary bus interface signals .................................................................................................. ................................ 4 3.2.2 secondary bus interface signals ................................................................................................ ............................. 6 3.2.3 clock signals .................................................................................................................. .......................................... 8 3.2.4 m iscellaneous signals ........................................................................................................... .................................. 8 3.2.5 jtag boundary scan signals ..................................................................................................... ............................. 9 3.2.6 power and ground ............................................................................................................... ..................................... 9 3.3 pi7c7100 pbga pin listing ................................................................................................... .................................. 9 4. pci bus operation ............................................................................................................................... ................. 13 4.1 types of transactions ....................................................................................................... .................................... 13 4.2 single address phase ........................................................................................................ .................................... 14 4.3 device select (devsel#) generation .......................................................................................... .......................... 14 4.4 data phase .................................................................................................................. ........................................... 14 4.5 write transactions .......................................................................................................... ...................................... 14 4.5.1 posted write transactions ...................................................................................................... .............................. 14 4.5.2 memory write and invalidate transactions ....................................................................................... ................... 15 4.5.3 del ayed write transactions ........................................................................................................ .......................... 15 4.5.4 write transaction address boundaries ........................................................................................... ..................... 16 4.5.5 buffering mu ltiple write transactions ...................................................................................................... ............ 16 4.5.6 fast back-to-back write transactions ........................................................................................... ....................... 16 4.6 read transactions ........................................................................................................... ...................................... 17 4.6.1 prefetchable read transactions ................................................................................................. ........................... 17 4.6.2 n on-prefetchable read transactions .............................................................................................. ...................... 17 4.6.3 read pre-fetch address boundaries .............................................................................................. ........................ 17 4.6.4 d elayed read requests ........................................................................................................... .............................. 18 4.6.5 delayed read completion with target ............................................................................................ ...................... 18 4.6.6 delayed read completion on initiator bus ....................................................................................... .................... 18 4.7 configuration transactions .................................................................................................. ................................. 19 4.7.1 type 0 access to pi7c7100 ...................................................................................................... ............................. 19 4.7.2 type 1 to type 0 conversion .................................................................................................... ............................ 20 4.7.3 type 1 to type 1 forwarding .................................................................................................... ............................ 21 4.7.4 special cycles ................................................................................................................. ....................................... 22 4.8 transaction termination ..................................................................................................... ................................... 22 4.8.1 m aster termination initiated by pi7c7100 ........................................................................................ .................... 23 4.8.2 master abort received by pi7c7100 .............................................................................................. ....................... 23 4.8.3 target termination received by pi7c7100 ........................................................................................ .................... 24 4.8.3.1 del ayed write target termination response ......................................................................................... .............. 24 4.8.3.2 posted write target termination response ....................................................................................... .................. 24 4.8.3.3 delayed read target termination response ....................................................................................... ................. 25 4.8.4 target termination initiated by pi7c7100 ....................................................................................... ...................... 26 4.8.4.1 target retry ................................................................................................................... ........................................ 26 4.8.4.2 target disconnect .............................................................................................................. .................................... 27 table of contents
iv 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 4.8.4.3 target abort ................................................................................................................... ....................................... 27 4.9 concurrent mode operation ................................................................................................... ............................... 27 5. address decoding ............................................................................................................................... ................... 28 5.1 address ranges .............................................................................................................. ....................................... 28 5.2 i/o address decoding ........................................................................................................ ................................... 28 5.2.1 i/o base and limit address registers ........................................................................................... ........................ 28 5.2.2 isa mode ........................................................................................................................... .................................... 29 5.3 memory address decoding ..................................................................................................... .............................. 29 5.3.1 mem ory-mapped i/o base and limit address registers ................................................................................ ...... 30 5.3.2 p refetchable memory base and limit address registers ............................................................................ .......... 30 5.4 vga support ................................................................................................................. ......................................... 31 5.4.1 vga mode ....................................................................................................................... ...................................... 31 5.4.2 vga snoop mode ................................................................................................................. ................................. 31 6. transaction ordering ............................................................................................................................... ............ 32 6.1 transactions governed by ordering rules ..................................................................................... ...................... 32 6.2 general ordering guidelines ................................................................................................. ................................. 32 6.3 ordering rules .............................................................................................................. ......................................... 33 6.4 data synchronization ........................................................................................................ ..................................... 34 7. error handling ............................................................................................................................... ....................... 35 7.1 address parity errors ....................................................................................................... ...................................... 35 7.2 data parity errors .......................................................................................................... ......................................... 35 7.2.1 c onfiguration write transactions to configuration space ......................................................................... .......... 35 7.2.2 read transactions .............................................................................................................. ................................... 36 7.2.3 del ayed write transactions ........................................................................................................ .......................... 36 7.2.4 posted write transactions ...................................................................................................... .............................. 38 7.3 data parity error reporting summary ......................................................................................... ........................... 39 7.4 system error (serr#) reporting .............................................................................................. ............................. 45 8. exclusive access ............................................................................................................................... .................... 46 8.1 concurrent locks ............................................................................................................ ....................................... 46 8.2 acquiring exclusive access across pi7c7100 .................................................................................. ..................... 46 8.3 ending exclusive access ..................................................................................................... .................................. 47 9. pci bus arbitration ............................................................................................................................... ............... 48 9.1 primary pci bus arbitration ................................................................................................. .................................. 48 9.2 secondary pci bus arbitration ............................................................................................... .............................. 48 9.2.1 secondary bus arbitration using the internal arbiter ........................................................................... ............... 48 9.2.2 secondary bus arbitration using an external arbiter ............................................................................ ............... 49 9.2.3 bus parking .................................................................................................................... ........................................ 49 10. clocks ............................................................................................................................... ..................................... 50 10.1 prim ary clock inputs ............................................................................................................... ............................... 50 10.2 secondary clock outputs ........................................................................................................ .............................. 50 11. reset ............................................................................................................................... ....................................... 51 11.1 primary interface reset ........................................................................................................ .................................. 51 11.2 secondary interface reset ...................................................................................................... ............................... 51 11.3 chip reset ..................................................................................................................... ......................................... 51 12. supported commands ............................................................................................................................... ............. 52 12.1 primary interface .............................................................................................................. ...................................... 52 12.2 secondary interface ............................................................................................................ ................................... 54 13. configuration registers ............................................................................................................................... ........ 55
v 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456 7 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 13.1 c onfig register 1 ............................................................................................................... ..................................... 55 13.2 c onfig register 2 ............................................................................................................... ..................................... 56 13.2.1 config register 1 or 2:vendor id register (read only, bit 15-0; offset 00h) .................................................... ...... 57 13.2.2 config register 1: device id register (read only, bit 31-16; offset 00h) ....................................................... ........ 57 13.2.3 config register 2: device id register (read only, bit 31-16; offset 00h) ....................................................... ........ 57 13.2.4 config register 1: command register (bit 15-0; offset 04h) ..................................................................... ............. 57 13.2.5 config register 2: command register (bit 15-0; offset 04h) ..................................................................... ............. 58 13.2.6 config register 1 or 2: status register (for primary bus, bit 31-16; offset 04h) ............................................... ...... 59 13.2.7 c onfig register 1 or 2: revision id register (read only, bit 7-0; offset 08h) ................................................... ...... 60 13.2.8 config register 1 or 2: class code register (read only, bit 31-8; offset 08h) .................................................. ...... 60 13.2.9 c onfig register 1 or 2: cache line size register (read/write, bit 7-0; offset 0ch) .............................................. ... 60 13.2.10 config register 1: primary latency timer register (read/write, bit 15-8; offset 0ch) ........................................... .60 13.2.11 config register 2: primary latency timer register (read/write, bit 15-8; offset 0ch) ........................................... .60 13.2.12 config register 1: header type register (read only, bit 23-16; offset 0ch) ..................................................... ..... 60 13.2.13 config register 2: header type register (read only, bit 23-16; offset 0ch) ..................................................... ..... 60 13.2.14 config register 1: primary bus number register (read/write, bit 7-0; offset 18h) ............................................... .. 60 13.2.15 config register 2: primary bus number register (read/write, bit 7-0; offset 18h) ............................................... .. 60 13.2.16 config register 1 or 2: secondary bus number register (read/write, bit 15-8; offset 18h) ................................... 60 13.2.17 config register 1 or 2: subordinate bus number register (read/write, bit 23-16; offset 18h) ............................... 60 13.2.18 config register 1 or 2: secondary latency timer (read/write, bit 31-24; offset 18h) ............................................ 60 13.2.19 config register 1 or 2: i/o base register (read/write, bit 7-0; offset 1ch) .................................................... ........ 60 13.2.20 config register 1 or 2: i/o limit register (read/write, bit 15-8; offset 1ch) .................................................. ......... 60 13.2.21 config register 1 or 2: secondary status register (bit 31-16; offset 1ch) ...................................................... ...... 61 13.2.22 config register 1 or 2: memory base register (read/write, bit 15-0; offset 20h) ................................................ ... 62 13.2.23 config register 1 or 2: memory limit register (read/write, bit 31:16; offset 20h) .............................................. ... 62 13.2.24 config register 1 or 2: prefetchable memory base register (read/write, bit 15-0;offset 24h) ............................... 62 13.2.25 config register 1 or 2: prefetchable memory limit register (read/write, bit 31-16; offset 24h) ............................ 62 13.2.26 config register 1 or 2: i/o base address upper 16 bits register (read/write, bit 15-0; offset 30h) ...................... 62 13.2.27 config register 1 or 2: i/o limit address upper 16 bits register (read/write, bit 31-16; offset 30h) .................... 62 13.2.28 config register 1 or 2: subsystem vendor id (read/write, bit 15-0; offset 34h) ................................................. ... 62 13.2.29 config register 1 or 2: subsystem id (read/write, bit 31-16; offset 34h) ....................................................... ........ 62 13.2.30 config register 1 or 2: interrupt pin register (read only, bit 15-8; offset 3ch) ............................................... ...... 62 13.2.31 config register 1 or 2: bridge control register (bit 31-16; offset 3ch) ........................................................ ......... 63 13.2.32 config register 1 or 2: diagnostic/chip control register (bit 15-0; offset 40h) ................................................ .... 64 13.2.33 config register 1 or 2: arbiter control register (bit 31-16; offset 40h) ....................................................... .......... 64 13.2.34 config register 1: primary prefetchable memory base register (read/write, bit 15-0; offset 44h) ..................... 65 13.2.35 config register 2: primary prefetchable memory base register (read/write, bit 15-0; offset 44h) ..................... 65 13.2.36 config register 1: primary prefetchable memory limit register (read/write, bit 31-16; offset 44h) .................... 65 13.2.37 config register 2: primary prefetchable memory limit register (read/write, bit 31-16; offset 44h) .................... 65 13.2.38 config register 1 or 2: p_serr# event disable register (bit 7-0; offset 64h) ................................................... ... 65 13.2.39 config register 1: secondary clock control register (bit 15-0; offset 68h) ..................................................... ..... 66 13.2.40 config register 2: secondary clock control register (bit 15-0; offset 68h) ..................................................... ..... 66 13.2.41 config register 1 or 2: non-posted memory base register (read/write, bit 15-0; offset 70h) .............................. 67 13.2.42 config register 1 or 2: non-posted memory limit register (read/write, bit 31-16; offset 70h) ............................. 67 13.2.43 config register 1: port option register (bit 15-0; offset 74h) ................................................................. .............. 67 13.2.44 config register 2: port option register (bit 15-0; offset 74h) ................................................................. .............. 68 13.2.45 config register 1 or 2: master timeout counter register (read/write, bit 31-16; offset 74h) ................................ 69 13.2.46 config register 1 or 2: retry counter register (read/write, bit 31-0; offset 78h) .............................................. .... 69 13.2.47 config register 1 or 2: sampling timer register (read/write, bit 31-0; offset 7ch) ............................................. ... 69 13.2.48 config register 1 or 2: successful i/o read count register (read/write, bit 31-0; offset 80h) ............................. 69
vi 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 13.2.49 config register 1 or 2: successful i/o write count register (read/write, bit 31-0; offset 84h) ............................. 69 13.2.50 config register 1 or 2: successful memory read count register (read/write, bit 31-0; offset 88h) ..................... 69 13.2.51 config register 1 or 2: successful memory write count register (read/write, bit 31-0; offset 8ch) .................... 69 13.2.52 config register 1: primary successful i/o read count register (read/write, bit 31-0; offset 90h) ....................... 69 13.2.53 config register 1: primary successful i/o write count register (read/write, bit 31-0; offset 94h) ....................... 69 13.2.54 config register 1: primary successful memory read count register (read/write, bit 31-0; offset 98h) ............... 69 13.2.55 config register 1: primary successful memory write count register (read/write, bit 31-0; offset 9ch) .............. 69 14. bridge behavior ............................................................................................................................... ..................... 70 14.1 bridge actions for various cycle types ......................................................................................... ...................... 70 14.2 transaction ordering ........................................................................................................... .................................. 70 14.3 abnormal term ination (initiated by bridge master) ........................................................................................... .. 71 14.3.1 m aster abort .................................................................................................................... ..................................... 71 14.3.2 parity and error reporting ..................................................................................................... ................................ 71 14.3.3 reporting parity errors ........................................................................................................ ................................... 71 14.3.4 secondary idsel mapping ........................................................................................................ ............................ 71 15. ieee 1149.1 compatible jtag controller ........................................................................................................... 72 15.1 boundary scan architecture ..................................................................................................... ............................ 72 15.1.1 tap pins ....................................................................................................................... ......................................... 72 15.1.2 instruction register ........................................................................................................... .................................... 72 15.2 b oundary scan instruction set ................................................................................................... ........................... 73 15.3 tap test data registers ........................................................................................................ ............................... 74 15.4 bypass register ................................................................................................................ ..................................... 74 15.5 boundary-scan register ......................................................................................................... ................................ 74 15.6 tap controller ..................................................................................................................... .................................. 74 16. electrical and timing specifications .................................................................................................................... 79 16.1 maximum ratings ............................................................................................................................... .................... 79 16.2 3.3v dc specifications ......................................................................................................... .................................. 79 16.3 3.3v ac specifications ......................................................................................................... .................................. 80 16.4 primary and secondary buses at 33 mhz clock timing ............................................................................. ............. 80 16.5 power consumption .............................................................................................................. ................................. 80 17. 256-pin pbga package ........................................................................................................ ................................... 81 17.1 part number ordering information ............................................................................................... ......................... 81
vii 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 123456 7 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 list of figures 1-1. pi7c7100 on the system board ................................................................................................... ................................. 2 1-2. pi7c7100 in redundant applications ............................................................................................. ............................. 2 1-3. pi 7c7100 on network switching hub ................................................................................................ .......................... 2 2-1. pi7c7100 block diagram ............................................................................................................................... ............... 3 9-1. sec ondary arbiter example ......................................................................................................... .............................. 48 15-1. test access port block diagram ................................................................................................. .............................. 72 16-1. pci signal timing measurement conditions ....................................................................................... ..................... 80 17-1. 256-pin pbga package drawing ................................................................................................... ............................. 81 list of tables 4-1. pci transaction ................................................................................................................ ......................................... 13 4-2. write transaction forwarding ................................................................................................... ............................... 14 4-3. write transaction disconnect address boundaries ................................................................................ ................ 16 4-4. read pre-fetch address boundaries .............................................................................................. ........................... 17 4-5. read transaction pre-fetching .................................................................................................. ................................ 18 4-6. device number to idsel s1_ad or s2_ad pin mapping .............................................................................. ......... 21 4-7. del ayed write target termination response ......................................................................................... .................. 24 4-8. responses to posted write target termination ................................................................................... .................... 25 4-9. responses to delayed read target termination ................................................................................... ................... 25 6-1. summ ary of tranaction ordering ..................................................................................................... ......................... 33 7-1. setting the primary interface detected parity error bit ........................................................................ ..................... 39 7-2. setting the secondary interface detected parity error bit ...................................................................... .................. 40 7-3. setting the primary interface data parity detected bit ......................................................................... ..................... 40 7-4. setting the secondary interfacedata parity detected bit ........................................................................ ................. 41 7-5. assertion of p_perr# ........................................................................................................... .................................... 42 7-6. assertion of s_perr# ........................................................................................................... .................................... 43 7-7. assertion of p_serr# for data parity errors .................................................................................... ....................... 44 15-1. tap pins ....................................................................................................................... ............................................. 73 15-2. j tag boundary register order .................................................................................................... ............................ 75
viii 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 09/18/00 rev 1.1 appendix a - timing diagrams 1. configuration read transaction ............................................................................................... .................................. a-3 2. configuration write transaction .............................................................................................. ..................................a-3 3. type 1 to type 0 configuration read transaction (p ? s) ......................................................................................a-3 4. type 1 to type 0 configuration write transaction (p ? s) .....................................................................................a-4 5. upstream type 1 to special cycle transaction (s ? p) ............................................................................................. a-4 6. downstream type 1 to special cycle transaction (p ? s) ........................................................................................ a-5 7. downstream type 1 to type 1 configuration read transaction (p ? s) ..................................................................a-5 8. downstream type 1 to type 1 configuration write transaction (p ? s) .................................................................a-6 9. upstream delayed burst memory read transaction (s ? p) ...................................................................................a-6 10. downstream delayed burst memory read transaction (p ? s) ..............................................................................a-7 11. downstream delayed memory read transaction (p/33mhz ? s/33mhz) ............................................................... a-7 12. downstream delayed memory read transaction (s2/33mhz ? s1/33mhz) ...........................................................a-8 13. downstream delayed memory read transaction (s1/33mhz ? s2/33mhz) ...........................................................a-8 14. upstream delayed memory read transaction (s/33mhz ? p/33mhz) ...................................................................a-9 15. downstream posted memory write transaction (p/33mhz ? s/33mhz) ................................................................ a-9 16. downstream posted memory write transaction (s2/33mhz ? s1/33mhz) ........................................................... a-10 17. downstream posted memory write transaction (s1/33mhz ? s2/33mhz) ........................................................... a-10 18. upstream posted memory write transaction (s/33mhz ? p/33mhz) ................................................................... a-11 19. downstream flow-through posted memory write transaction (p/33mhz ? s/33mhz) ........................................ a-11 20. downstream flow-through posted memory write transaction (s2/33mhz ? s1/33mhz) .................................... a-12 21. downstream flow-through posted memory write transaction (s1/33mhz ? s2/33mhz) .................................... a-12 22. upstream flow-through posted memory write transaction (s/33mhz ? p/33mhz) ............................................ a-13 23. downstream delayed i/o read transaction (p ? s) ............................................................................................... a-13 24. downstream delayed i/o read transaction (s2/33mhz ? s1/33mhz) .................................................................. a-14 25. downstream delayed i/o read transaction (s1/33mhz ? s2/33mhz) .................................................................. a-14 26. downstream delayed i/o read transaction (s/33mhz ? p/33mhz) ...................................................................... a-15 27. downstream delayed i/o write transaction (p ? s) .............................................................................................. a-15 28. downstream delayed i/o write transaction (s2/33mhz ? s1/33mhz) ................................................................. a-16 29. downstream delayed i/o write transaction (s1/33mhz ? s2/33mhz) ................................................................. a-16 30. upstream delayed i/o write transaction (s ? p) ................................................................................................... a-17 appendix b - evaluation board user's manual general information ............................................................................................................ ............................................... b-3 frequently asked questions ..................................................................................................... ....................................... b-5 appendix c - three-port pci bridge evaluation board schematics pci chip ............................................................................................................................... .............................................. c-3 pci edge connector ............................................................................................................. ............................................. c-4 secondary 1 pci bus ............................................................................................................ ............................................. c-5 secondary 2 pci bus ............................................................................................................ ............................................. c-6 top view ............................................................................................................................... ............................................. c-7 appendix d - representatives and distributors
1 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information product features ? 32-bit primary & two secondary ports run up to 33 mhz ? all three ports compliant with the pci local bus specification, revision 2.1 ? compliant with pci-to-pci bridge architecture specification, revision 1.0. - all i/o and memory commands - type 1 to type 0 configuration conversion - type 1 to type 1 configuration forwarding - type 1 configuration-write to special cycle conversion ? concurrent primary to secondary bus operation and independent intra-secondary port channel to reduce traffic on the primary port ? provides internal arbitration for two sets of eight secondary bus masters - programmable 2-level priority arbiter - disable control for use of external arbiter ? supports posted write buffers on all directions ? three 128 byte fifos for delay transactions ? three 128 byte fifos for posted memory transactions ? enhanced address decoding - 32-bit i/o address range - 32-bit memory-mapped i/o address range - vga addressing and vga palette snooping - isa-aware mode for legacy support in the first 64kb of i/o address range ? interrupt handling - pci interrupts are routed through an external interrupt concentrator ? supports system transaction ordering rules ? hot-plug support on secondary buses - 3-state control of output buffers ? ieee 1149.1 jtag interface support ? 3.3v core; 3.3v pci i/o interface with 5v i/o tolerant ? 256-pin plastic bga package product description pi7c7100 is the first triple port pci-to-pci bridge device designed to be fully compliant with the 32-bit, 33 mhz implementation of the pci local bus specification, revision 2.1 . pi7c7100 supports only synchronous bus transactions between devices on the primary 33 mhz bus and the secondary buses operating at 33 mhz. the primary and the secondary buses can also operate in concurrent mode, resulting in added increase in system performance. concurrent bus operation off-loads and isolates unnecessary traffic from the primary bus; thereby enabling a master and a target device on the same secondary pci bus to communicate even while the primary bus is busy. 1. introduction
2 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information figure 1-2. pi7c7100 in redundant application figure 1-1. pi7c7100 on the system board s1 pci bus s2 pci bus pi7c7100 cpu nb slot slot system memory pci device pci device pi7c7100 system primary pci bus pi7c7100 s1 pci bus master controller redundant controller s2 pci bus system primary pci bus s1 s1 s2 s2 figure 1-3. pi7c7100 on network switching hub cpu pci bus 32/33 pi7c7100 pci bus 32/33 core logic l2 cache i/o daughter board to isolate traffic pi7c7100 pi7c7100 fast ethernet internal slot
3 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information configuration register #1 arbiter arbiter secondary interface b secondary interface a secondary pci bus a transaction queue #1 transaction queue #2 transaction queue #3 configuration register #2 primary pci bus secondary pci bus b primary interface 2. pi7c7100 block diagram figure 2-1. pi7c7100 block diagram
4 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information e p y t l a n g i sn o i t p i r c s e d i p) t n a r e l o t v 5 , v 3 . 3 ( t u p n i i c p u i pp u - l l u p k a e w h t i w ) t n a r e l o t v 5 , v 3 . 3 ( t u p n i i c p b p) t n a r e l o t v 5 , v 3 . 3 ( l a n o i t c e r i d i b e t a t s - 3 i c p o p) v 3 . 3 ( t u p t u o i c p s t s p e l c y c e n o r o f e v i t c a n i n e v i r d e b t s u m h c i h w l a n g i s w o l e v i t c a ( l a n o i t c e r i d i b e t a t s - 3 d e n i a t s u s i c p ) e n i l l a n g i s d e r a h s a n o e c n a m r o f r e p h g i h e r u s n e o t d e t a t s - 3 g n i e b e r o f e b s t pt u p t u o e t a t s - 3 i c p d o p d e t a t s - 3 r o ) e t a t s e v i t c a ( w o l s e v i r d r e h t i e h c i h w t u p t u o i c p i ct u p n i s o m c u i cp u - l l u p k a e w h t i w t u p n i s o m c d i cn w o d - l l u p k a e w h t i w t u p n i s o m c o t ct u p t u o e t a t s - 3 s o m c 3. signal definitions 3.1 signal types e m a n# n i pe p y tn o i t p i r c s e d ] 0 : 1 3 [ d a _ p, 8 v , 8 w , 8 y , 7 w , 7 y , 0 1 w , 9 w , 9 y , 8 u , 1 1 u , 1 1 v , 1 1 y , 0 1 v , 6 1 v , 2 1 v , 2 1 w , 2 1 y , 7 1 w , 6 1 y , 6 1 w , 8 1 y , 8 1 w , 8 1 u , 7 1 y , 0 2 u , 9 1 y , 9 1 w , 9 1 u 7 1 r , 7 1 t , 0 2 y , 0 2 v b p . a t a d / s s e r d d a y r a m i r p s i s s e r d d a . s u b a t a d d n a s s e r d d a d e x e l p i t l u m n e h w d i l a v d n a e l b a t s s i a t a d e t i r w . n o i t r e s s a # e m a r f _ p y b d e t a c i d n i s i # y d r t _ p n e h w d i l a v d n a e l b a t s s i a t a d d a e r d n a d e t r e s s a s i # y d r i _ p d n a # y d r i _ p h t o b n e h w s e g d e k c o l c g n i s i r n o d e r r e f s n a r t s i a t a d . d e t r e s s a d i l a v a o t d a _ p s e v i r d 0 0 1 7 c 7 i p , e l d i s u b g n i r u d . d e t r e s s a e r a # y d r t _ p . d e t r e s s a s i # t n g _ p n e h w l e v e l c i g o l ] 0 : 3 [ e b c _ p9 1 v , 6 1 u , 2 1 u , 9 vb p . s e l b a n e e t y b / d n a m m o c y r a m i r p e t y b d n a d l e i f d n a m m o c d e x e l p i t l u m e p y t n o i t c a s n a r t e h t s e v i r d r o t a i t i n i e h t , e s a h p s s e r d d a g n i r u d . d l e i f e l b a n e a t a d g n i r u d s e l b a n e e t y b e h t s e v i r d r o t a i t i n i e h t t a h t r e t f a . s n i p e s e h t n o l e v e l c i g o l d i l a v a o t ] 0 : 3 [ e b c _ p s e v i r d 0 0 1 7 c 7 i p , e l d i s u b g n i r u d . s e s a h p . d e t r e s s a s i # t n g _ p n e h w r a p _ p5 1 ub p . y t i r a p y r a m i r p d n a , ] 0 : 3 [ e b c _ p , ] 0 : 1 3 [ d a _ p s s o r c a n e v e s i y t i r a p d n a d i l a v s i d n a t u p n i n a s i r a p _ p . ) s ' 1 ' f o r e b m u n n e v e n a . e . i ( r a p _ p f o n o i t r e s s a y b d e t a c i d n i ( e s a h p s s e r d d a e h t r e t f a e l c y c e n o e l b a t s t u p n i n a s i r a p _ p , s e s a h p a t a d e t i r w r o f . y t i r a p s s e r d d a r o f ) # e m a r f _ p , e s a h p a t a d d a e r r o f . d e t r e s s a s i # y d r i _ p r e t f a k c o l c e n o d i l a v s i d n a . d e t r e s s a s i # y d r t _ p r e t f a k c o l c e n o d i l a v s i d n a t u p t u o n a s i r a p _ p g n i r u d . d e t a t s - 3 e r a s e n i l d a p e h t r e t f a e l c y c e n o d e t a t s - i r t s i r a p _ p l a n g i s s i # t n g _ p n e h w l e v e l c i g o l d i l a v a o t r a p p s e v i r d 0 0 1 7 c 7 i p , e l d i s u b . d e t r e s s a # e m a r f _ p3 1 ws t s p . ) w o l e v i t c a ( e m a r f y r a m i r p o t n o i t c a s n a r t a f o r o t a i t i n i e h t y b n e v i r d f o n o i t r e s s a - e d e h t . s s e c c a n a f o n o i t a r u d d n a g n i n n i g e b e h t e t a c i d n i e r o f e b . r o t a i t i n i e h t y b d e t s e u q e r e s a h p a t a d l a n i f e h t s e t a c i d n i # e m a r f _ p . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d s i t i , d e t a t s - 3 g n i e b 3.2 signals ( note: signal name that ends with character # is active low.) 3.2.1 primary bus interface signals
5 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information e m a n# n i pe p y tn o i t p i r c s e d # y d r i _ p3 1 vs t s p o t y t i l i b a s t i e t a c i d n i o t n o i t c a s n a r t a f o r o t a i t i n i e h t y b n e v i r d . ) w o l e v i t c a ( y d r i y r a m i r p t o n s i t i , e s a h p a t a d a n i d e t r e s s a e c n o . e d i s y r a m i r p e h t n o e s a h p a t a d t n e r r u c e t e l p m o c d e t r e s s a - e d a o t n e v i r d s i t i , d e t a t s - 3 g n i e b e r o f e b . e s a h p a t a d f o d n e l i t n u d e t r e s s a - e d . e l c y c e n o r o f e t a t s # y d r t _ p3 1 us t s p o t y t i l i b a s t i e t a c i d n i o t n o i t c a s n a r t a f o t e g r a t e h t y b n e v i r d . ) w o l e v i t c a ( y d r t y r a m i r p t o n s i t i , e s a h p a t a d a n i d e t r e s s a e c n o . e d i s y r a m i r p e h t n o e s a h p a t a d t n e r r u c e t e l p m o c d e t r e s s a - e d a o t n e v i r d s i t i , d e t a t s - 3 g n i e b e r o f e b . e s a h p a t a d f o d n e l i t n u d e t r e s s a - e d . e l c y c e n o r o f e t a t s # l e s v e d _ p4 1 ys t s p . ) w o l e v i t c a ( t c e l e s e c i v e d y r a m i r p e c i v e d e h t t a h t g n i t a c i d n i t e g r a t e h t y b d e t r e s s a l a n g i s s i h t f o n o i t r e s s a e h t r o f s t i a w 0 0 1 7 c 7 i p , r e t s a m a s a . n o i t c a s n a r t e h t g n i t p e c c a s i e r o f e b . t r o b a r e t s a m h t i w e t a n i m r e t , e s i w r e h t o ; n o i t r e s s a # e m a r f _ p f o s e l c y c 5 n i h t i w . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d s i t i , d e t a t s - 3 g n i e b # p o t s _ p4 1 ws t s p . ) w o l e v i t c a ( p o t s y r a m i r p s i t e g r a t e h t t a h t g n i t a c i d n i t e g r a t e h t y b d e t r e s s a n e v i r d s i t i , d e t a t s - 3 g n i e b e r o f e b . n o i t c a s n a r t t n e r r u c e h t p o t s o t r o t a i t i n i e h t g n i t s e u q e r . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t # k c o l _ p4 1 vs t s p . ) w o l e v i t c a ( k c o l y r a m i r p . e t e l p m o c o t s n o i t c a s n a r t e l p i t l u m r o f r e t s a m y b d e t r e s s a l e s d i _ p0 1 yi p . t c e l e s d i y r a m i r p 0 0 1 7 c 7 i p o t s s e c c a n o i t a r u g i f n o c 0 e p y t r o f e n i l t c e l e s p i h c s a d e s u . e c a p s n o i t a r u g i f n o c # r r e p _ p5 1 ys t s p r o r r e y t i r a p y r a m i r p. ) w o l e v i t c a ( r o f d e t c e t e d s i r o r r e y t i r a p a t a d a n e h w d e t r e s s a - e d a o t n e v i r d s i t i , d e t a t s - 3 g n i e b e r o f e b . e c a f r e t n i y r a m i r p e h t n o d e v i e c e r a t a d . e l c y c e n o r o f e t a t s d e t r e s s a # r r e s _ p5 1 wd o p . ) w o l e v i t c a ( r o r r e m e t s y s y r a m i r p a e t a c i d n i o t e c i v e d y n a y b w o l n e v i r d e b n a c : n o n i p s i h t s e v i r d 0 0 1 7 c 7 i p , n o i t i d n o c r o r r e m e t s y s r o r r e y t i r a p s s e r d d a ? s u b t e g r a t n o r o r r e y t i r a p a t a d e t i r w d e t s o p ? d e t r e s s a # r r e s _ 2 s r o # r r e s _ 1 s y r a d n o c e s ? n o i t c a s n a r t e t i r w d e t s o p g n i r u d t r o b a r e t s a m ? n o i t c a s n a r t e t i r w d e t s o p g n i r u d t r o b a t e g r a t ? d e d r a c s i d n o i t c a s n a r t e t i r w d e t s o p ? d e d r a c s i d t s e u q e r e t i r w d e y a l e d ? d e d r a c s i d t s e u q e r d a e r d e y a l e d ? t u o e m i t r e t s a m n o i t c a s n a r t d e y a l e d ? . n o i t a r e p o r e p o r p r o f r o t s i s e r p u - l l u p l a n r e t x e n a s e r i u q e r l a n g i s s i h t # q e r _ p6 ws t p . ) w o l e v i t c a ( t s e u q e r y r a m i r p s t n a w t i t a h t e t a c i d n i o t 0 0 1 7 c 7 i p y b d e t r e s s a s i s i h t i c p 2 t s a e l t a r o f n i p s i h t s t r e s s a - e d 0 0 1 7 c 7 i p . s u b y r a m i r p e h t n o n o i t c a s n a r t a t r a t s o t . n i a g a t i g n i t r e s s a e r o f e b s e l c y c k c o l c # t n g _ p7 ui p ) w o l e v i t c a ( t n a r g y r a m i r p . s u b y r a m i r p e h t s s e c c a n a c 0 0 1 7 c 7 i p , d e t r e s s a n e h w . o t r a p _ p d n a e b c _ p , d a _ p e v i r d l l i w 0 0 1 7 c 7 i p , d e t r e s s a # t n g _ p d n a e l d i g n i r u d . s l e v e l c i g o l d i l a v # t e s e r _ p5 yi p . ) w o l e v i t c a ( t e s e r y r a m i r p e b d l u o h s s l a n g i s i c p l l a , e v i t c a s i # t e s e r _ p n e h w . d e t a t s - 3 y l s u o n o r h c n y s a # h s u l f _ p5 wi p . ) w o l e v i t c a ( h s u l f o f i f y r a m i r p ) s ( o f i f y r a m i r p l l a , e v i t c a s i # h s u l f _ p n e h w c i t a t s a o t d e l l u p e b d l u o h s l a n g i s s i h t . ) s n o i t c a s n a r t y r a m i r p l l a e t a d i l a v n i ( d e r a e l c e r a " . h g i h " n e 6 6 m _ p8 1 vC . e s u e r u t u f r o f d e v r e s e r . d n u o r g o t d e i t e b t s u m 3.2.1 primary bus interface signals (continued)
6 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information e m a n# n i pe p y tn o i t p i r c s e d , ] 0 : 1 3 [ d a _ 1 s ] 0 : 1 3 [ d a _ 2 s , 9 1 c , 0 2 c , 9 1 b , 0 2 b , 7 1 d , 9 1 d , 0 2 d , 8 1 c , 0 2 f , 7 1 e , 8 1 e , 9 1 e , 9 1 g , 0 2 g , 7 1 f , 9 1 f , 0 2 m , 8 1 l , 9 1 l , 0 2 l , 9 1 n , 0 2 n , 7 1 m , 9 1 m , 0 2 r , 7 1 p , 7 1 n , 8 1 n 9 1 t , 0 2 t , 8 1 r , 9 1 r , 1 g , 4 h , 3 h , 2 h , 1 h , 4 j , 1 e , 4 f , 3 f , 2 f , 4 g , 3 g , 5 b , 5 c , 1 b , 1 c , 1 d , 4 e , 7 b , 7 c , 6 a , 6 b , 6 c , 6 d , 9 a , 9 b , 9 c , 9 d , 8 c , 8 d 0 1 c , 0 1 d b p . a t a d / s s e r d d a y r a d n o c e s . s u b a t a d d n a s s e r d d a d e x e l p i t l u m . n o i t r e s s a # e m a r f _ 2 s r o # e m a r f _ 1 s y b d e t a c i d n i s i s s e r d d a s i # y d r i _ 2 s r o # y d r i _ 1 s n e h w d i l a v d n a e l b a t s s i a t a d e t i r w r o # y d r t _ 1 s n e h w d i l a v d n a e l b a t s s i a t a d d a e r d n a d e t r e s s a s e g d e k c o l c g n i s i r n o d e r r e f s n a r t s i a t a d . d e t r e s s a s i # y d r t _ 2 s d n a # y d r i _ 2 s r o # y d r t _ 1 s d n a # y d r i _ 1 s h t o b n e h w s e v i r d 0 0 1 7 c 7 i p , e l d i s u b g n i r u d . d e t r e s s a e r a # y d r t _ 2 s r o # t n g _ 1 s e h t n e h w l e v e l c i g o l d i l a v a o t d a _ 2 s r o d a _ 1 s . y l e v i t c e p s e r d e t r e s s a s i # t n g _ 2 s , ] 0 : 3 [ e b c _ 1 s ] 0 : 3 [ e b c _ 2 s 0 2 p , 7 1 k , 8 1 g , 0 2 e 7 a , 4 a , 1 a , 1 f b p . s e l b a n e e t y b / d n a m m o c y r a d n o c e s d n a m m o c d e x e l p i t l u m r o t a i t i n i e h t , e s a h p s s e r d d a e h t g n i r u d . d l e i f e l b a n e e t y b d n a d l e i f r o t a i t i n i e h t t a h t r e t f a . s n i p e s e h t n o e p y t n o i t c a s n a r t e h t s e v i r d , e l d i s u b g n i r u d . s e s a h p a t a d g n i r u d s e l b a n e e t y b e h t s e v i r d c i g o l d i l a v a o t ] 0 : 3 [ e b c _ 2 s r o ] 0 : 3 [ e b c _ 1 s s e v i r d 0 0 1 7 c 7 i p . d e t r e s s a s i t n a r g l a n r e t n i e h t n e h w l e v e l , r a p _ 1 s r a p _ 2 s , 8 1 k 4 b b p . y t i r a p y r a d n o c e s , ] 0 : 1 3 [ d a _ 1 s s s o r c a n e v e s i y t i r a p d n a , ] 0 : 3 [ e b c _ 2 s , ] 0 : 1 3 [ d a _ 2 s r o r a p _ 1 s d n a , ] 0 : 3 [ e b c _ 1 s n a s i r a p _ 2 s r o r a p _ 1 s . ) s ' 1 ' f o r e b m u n n e v e n a . e . i ( r a p _ 2 s e s a h p s s e r d d a e h t r e t f a e l c y c e n o e l b a t s d n a d i l a v s i d n a t u p n i r o f ) # e m a r f _ 2 s r o # e m a r f _ 1 s f o n o i t r e s s a y b d e t a c i d n i ( n a s i r a p _ 2 s r o r a p _ 1 s , s e s a h p a t a d e t i r w r o f . y t i r a p s s e r d d a s i # y d r i _ 2 s r o # y d r i _ 1 s r e t f a k c o l c e n o d i l a v s i d n a t u p n i t u p t u o n a s i r a p _ 2 s r o r a p _ 1 s , e s a h p a t a d d a e r r o f . d e t r e s s a . d e t r e s s a s i # y d r t _ 2 s r o # y d r t _ 1 s r e t f a k c o l c e n o d i l a v s i d n a d a _ 1 s e h t r e t f a e l c y c e n o d e t a t s - 3 s i r a p _ 2 s r o r a p _ 1 s l a n g i s s e v i r d 0 0 1 7 c 7 i p , e l d i s u b g n i r u d . d e t a t s - i r t e r a s e n i l d a _ 2 s r o s i t n a r g l a n r e t n i e h t n e h w l e v e l c i g o l d i l a v a o t r a p _ 2 s r o r a p _ 1 s . d e t r e s s a , # e m a r f _ 1 s # e m a r f _ 2 s , 0 2 h 2 d s t s p . ) w o l e v i t c a ( e m a r f y r a d n o c e s a f o r o t a i t i n i e h t y b n e v i r d . s s e c c a n a f o n o i t a r u d d n a g n i n n i g e b e h t e t a c i d n i o t n o i t c a s n a r t l a n i f e h t s e t a c i d n i # e m a r f _ 2 s r o # e m a r f _ 1 s f o n o i t r e s s a - e d s i t i , d e t a t s - 3 g n i e b e r o f e b . r o t a i t i n i y b d e t s e u q e r e s a h p a t a d . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d , # y d r i _ 1 s # y d r i _ 2 s , 9 1 h 2 b s t s p . ) w o l e v i t c a ( y d r i y r a d n o c e s a f o r o t a i t i n i e h t y b n e v i r d a t a d t n e r r u c e h t e t e l p m o c o t y t i l i b a s t i e t a c i d n i o t n o i t c a s n a r t s i t i , e s a h p a t a d a n i d e t r e s s a e c n o . e d i s y r a m i r p e h t n o e s a h p , d e t a t s - 3 g n i e b e r o f e b . e s a h p a t a d e h t f o d n e l i t n u d e t r e s s a - e d t o n . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d s i t i , # y d r t _ 1 s # y d r t _ 2 s , 8 1 h 2 a s t s p . ) w o l e v i t c a ( y d r t y r a d n o c e s a f o t e g r a t e h t y b n e v i r d a t a d t n e r r u c e h t e t e l p m o c o t y t i l i b a s t i e t a c i d n i o t n o i t c a s n a r t s i t i , e s a h p a t a d a n i d e t r e s s a e c n o . e d i s y r a m i r p e h t n o e s a h p , d e t a t s - 3 g n i e b e r o f e b . e s a h p a t a d e h t f o d n e l i t n u d e t r e s s a - e d t o n . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d s i t i , # l e s v e d _ 1 s # l e s v e d _ 2 s , 0 2 j 3 d s t s p . ) w o l e v i t c a ( t c e l e s e c i v e d y r a d n o c e s t e g r a t e h t y b d e t r e s s a a s a . n o i t c a s n a r t e h t g n i t p e c c a s i e c i v e d e h t t a h t g n i t a c i d n i 5 n i h t i w l a n g i s s i h t f o n o i t r e s s a e h t r o f s t i a w 0 0 1 7 c 7 i p , r e t s a m , e s i w r e h t o ; n o i t r e s s a # e m a r f _ 2 s r o # e m a r f _ 1 s f o s e l c y c a o t n e v i r d s i t i , d e t a t s - 3 g n i e b e r o f e b . t r o b a r e t s a m h t i w e t a n i m r e t . e l c y c e n o r o f e t a t s d e t r e s s a - e d 3.2.2 secondary bus interface signals
7 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information e m a n# n i pe p y tn o i t p i r c s e d , # p o t s _ 1 s # p o t s _ 2 s , 9 1 j 3 c s t s p . ) w o l e v i t c a ( p o t s y r a d n o c e s e h t t a h t g n i t a c i d n i t e g r a t e h t y b d e t r e s s a g n i e b e r o f e b . n o i t c a s n a r t t n e r r u c e h t p o t s o t r o t a i t i n i e h t g n i t s e u q e r s i t e g r a t . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d s i t i , d e t a t s - 3 , # k c o l _ 1 s # k c o l _ 2 s , 8 1 j 3 b s t s p . ) w o l e v i t c a ( k c o l y r a d n o c e s s n o i t c a s n a r t e l p i t l u m r o f r e t s a m y b d e t r e s s a . e t e l p m o c o t , # r r e p _ 1 s # r r e p _ 2 s , 7 1 j 4 d s t s p . ) w o l e v i t c a ( r o r r e y t i r a p y r a d n o c e s s i r o r r e y t i r a p a t a d a n e h w d e t r e s s a t i , d e t a t s - 3 g n i e b e r o f e b . e c a f r e t n i y r a d n o c e s e h t n o d e v i e c e r a t a d r o f d e t c e t e d . e l c y c e n o r o f e t a t s d e t r e s s a - e d a o t n e v i r d s i , # r r e s _ 1 s # r r e s _ 2 s , 0 2 k 4 c i p . ) w o l e v i t c a ( r o r r e m e t s y s y r a d n o c e s o t e c i v e d y n a y b w o l n e v i r d e b n a c . n o i t i d n o c r o r r e m e t s y s a e t a c i d n i , ] 0 : 7 [ # q e r _ 1 s ] 0 : 7 [ # q e r _ 2 s , 2 1 a , 1 1 b , 3 1 c , 3 1 d , 6 1 a , 5 1 c 7 1 b , 7 1 c , 2 p , 3 r , 2 t , 1 m , 2 m , 1 p 3 k , 1 k u i p . ) w o l e v i t c a ( t s e u q e r y r a d n o c e s o t e c i v e d l a n r e t x e n a y b d e t r e s s a s i s i h t s i t u p n i e h t . s u b y r a d n o c e s e h t n o n o i t c a s n a r t a t r a t s o t s t n a w t i t a h t e t a c i d n i . d d v o t r o t s i s e r a h g u o r h t p u d e l l u p y l l a n r e t x e , ] 0 : 7 [ # t n g _ 1 s ] 0 : 7 [ # t n g _ 2 s , 2 1 b , 1 1 c , 4 1 a , 3 1 b , 6 1 b , 4 1 d 8 1 b , 6 1 d , 1 r , 4 p , 1 u , 4 l , 3 m , 4 n 2 k , 1 l o p . ) w o l e v i t c a ( t n a r g y r a d n o c e s e h t s s e c c a o t n i p s i h t s t r e s s a 0 0 1 7 c 7 i p s e l c y c k c o l c i c p 2 t s a e l t a r o f n i p s i h t s t r e s s a - e d 0 0 1 7 c 7 i p . s u b y r a d n o c e s , d e t r e s s a # t n g _ 2 s r o # t n g _ 1 s d n a e l d i g n i r u d . n i a g a t i g n i t r e s s a e r o f e b d n a e b c _ 2 s , d a _ 2 s r o r a p _ 1 s d n a e b c _ 1 s , d a _ 1 s e v i r d l l i w 0 0 1 7 c 7 i p . s l e v e l c i g o l d i l a v o t r a p _ 2 s , # t e s e r _ 1 s # t e s e r _ 2 s , 0 1 b 4 t o p . ) w o l e v i t c a ( t e s e r y r a d n o c e s g n i w o l l o f e h t f o y n a n e h w d e t r e s s a : t e m e r a s n o i t i d n o c . d e t r e s s a s i # t e s e r _ p l a n g i s . 1 n o i t a r u g i f n o c n i r e t s i g e r l o r t n o c e g d i r b n i t i b t e s e r y r a d n o c e s . 2 . t e s s i e c a p s n e v i r d e r a s o r e z d n a d e t a t s - 3 e r a s l a n g i s l o r t n o c l l a , d e t r e s s a n e h w . r a p _ 2 s d n a , e b c _ 2 s , d a _ 2 s r o r a p _ 1 s d n a , e b c _ 1 s , d a _ 1 s n o , n e _ 1 s n e _ 2 s , 3 w 4 w u i p . ) h g i h e v i t c a ( e l b a n e y r a d n o c e s , e v i t c a n i s i n e _ 2 s r o n e _ 1 s n e h w . d e t a t s - 3 y l s u o n o r h c n y s a e b l l i w s u b 2 s r o 1 s i c p y r a d n o c e s n e 6 6 m _ s7 dC . e s u e r u t u f r o f d e v r e s e r . d n u o r g o t d e i t e b t s u m # n f c _ s2 yu i c . n i p l o r t n o c n o i t c n u f l a r t n e c s u b y r a d n o c e s s e l b a n e t i , w o l d e i t n e h w . d e s u e b t s u m r e t i b r a l a n r e t x e n a , h g i h d e i t n e h w . r e t i b r a l a n r e t n i e h t , t u p n i t n a r g s u b y r a d n o c e s e h t e b o t d e r u g i f n o c e r s i # 0 q e r _ 2 s r o # 0 q e r _ 1 s t s e u q e r s u b y r a d n o c e s e h t e b o t d e r u g i f n o c e r s i # 0 t n g _ 2 s r o # 0 t n g _ 1 s d n a . t u p t u o 3.2.2 secondary bus interface signals (continued)
8 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information e m a n# n i pe p y tn o i t p i r c s e d k l c _ p6 vi p t u p n i k c o l c y r a m i r p . e c a f r e t n i y r a m i r p n o n o i t c a s n a r t l l a r o f g n i m i t s e d i v o r p . t u o k l c _ s ] 0 : 5 1 [ , 3 p , 1 t , 3 t , 2 l , 3 l , 4 m , 3 n , 2 1 c , 1 1 a , 1 j , 4 1 b , 3 1 a , 6 1 c , 5 1 b 9 1 a , 8 1 a s t p . t u p t u o k c o l c y r a d n o c e s h t i w s u o n o r h c n y s e s a h p s k c o l c y r a d n o c e s s e d i v o r p . k l c _ p e h t 3.2.3 clock signals e m a n# n i pe p y tn o i t p i r c s e d s s a p y b4 yC . e s u e r u t u f r o f d e v r e s e r . h g i h d e i t e b t s u m m t _ l l p3 yC . e s u e r u t u f r o f d e v r e s e r . w o l d e i t e b t s u m n i k l c _ s5 vi p . t u p n i k c o l c t s e t y r a d n o c e s o s l a t i . e d o m l a m r o n n i w o l o t d e i t e b d l u o h s t i d n a # m t _ n a c s h t o b f i s e s u b y r a d n o c e s e h t r o f t u p n i k c o l c y r a d n o c e s a e b y a m . " 1 " c i g o l o t d e t c e n n o c e r a n e _ n a c s # m t _ n a c s4 vi c . ) w o l e v i t c a ( e l b a n e e d o m t s e t n a c s - l l u f e h t , e v i t c a s i # m t _ n a c s n e h w d n a s t u p n i n a c s e h t . k l c _ p s i k c o l c n a c s e h t . d e l b a n e e b l l i w s n i a h c n a c s e v l e w t : s w o l l o f s a e r a s t u p t u o , ] 2 [ q e r _ 1 s , ] 3 [ q e r _ 1 s , ] 4 [ q e r _ 1 s , ] 5 [ q e r _ 1 s , ] 6 [ q e r _ 1 s , ] 7 [ q e r _ 1 s d n a ] 2 [ q e r _ 2 s , ] 3 [ q e r _ 2 s , ] 4 [ q e r _ 2 s , ] 5 [ q e r _ 2 s , ] 6 [ q e r _ 2 s , ] 7 [ q e r _ 2 s , ] 2 [ t n g _ 1 s , ] 3 [ t n g _ 1 s , ] 4 [ t n g _ 1 s , ] 5 [ t n g _ 1 s , ] 6 [ t n g _ 1 s , ] 7 [ t n g _ 1 s ] 2 [ t n g _ 2 s , ] 3 [ t n g _ 2 s , ] 4 [ t n g _ 2 s , ] 5 [ t n g _ 2 s , ] 6 [ t n g _ 2 s , ] 7 [ t n g _ 2 s y l e v i t c e p s e r n e _ n a c s5 uu i c . l o r t n o c e l b a n e n a c s - l l u f n o i t a r e p o t f i h s n i s i n a c s - l l u f , w o l s i n e _ n a c s n e h w n o i t a r e p o l e l l a r a p n i s i n a c s - l l u f , h g i h s i n e _ n a c s n e h w . e v i t c a s i # m t _ n a c s f i f i . e d o m l a m r o n n i w o l d e i t e b d l u o h s n e _ n a c s . e v i t c a s i # m t _ n a c s f i k c o l c e h t s i n i k l c _ s , " 1 " c i g o l o t d e t c e n n o c e r a n e _ n a c s d n a # m t _ n a c s d n a " 1 " c i g o l o t d e t c e n n o c s i # m t _ n a c s f i . k c o l c y r a d n o c e s l a n r e t n i e h t r o f e c r u o s l a n r e t n i e h t r o f e c r u o s k c o l c e h t s i k l c _ p , " 0 " c i g o l o t d e t c e n n o c s i n e _ n a c s . k c o l c y r a d n o c e s : e t o n . l l p p i h c - n o e h t r o f l a n g i s t e s e r e h t s i n e _ n a c s , p u - r e w o p g n i r u d 1 o p m c6 uC . e s u e r u t u f r o f d e v r e s e r d e v r e s e r4 r d e v r e s e r 3.2.4 miscellaneous signals 3.2.5 jtag boundary scan signals e m a n# n i pe p y tn o i t p i r c s e d k c t2 vu i c . k c o l c t s e t g n i r u d 0 0 1 7 c 7 i p e h t f o t u o d n a o t n i a t a d d n a n o i t a m r o f n i e t a t s k c o l c o t d e s u . n a c s y r a d n u o b s m t1 wu i c t c e l e s e d o m t s e t . r e l l o r t n o c t r o p s s e c c a t s e t e h t f o e t a t s e h t l o r t n o c o t d e s u . o d t3 vo t c . t u p t u o a t a d t s e t a t a d t f i h s o t ) k c t h t i w n o i t c n u j n o c n i ( d e s u s i t i h g i h s i n e n a c s n e h w . m a e r t s t i b l a i r e s a n i ) p a t ( t r o p s s e c c a t s e t e h t f o t u o i d t2 wu i c . t u p n i a t a d t s e t a t a d t f i h s o t ) k c t h t i w n o i t c n u j n o c n i ( d e s u s i t i h g i h s i n e n a c s n e h w . m a e r t s t i b l a i r e s a ) p a t ( t r o p s s e c c a t s e t e h t o t n i s n o i t c u r t s n i d n a # t s r t3 uu i c . t e s e r t s e t n a o t n i r e l l o r t n o c ) p a t ( t r o p s s e c c a t s e t e h t t e s e r o t l a n g i s w o l e v i t c a . e t a t s d e z i l a i t i n i
9 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information e m a n# n i pe p y tn o i t p i r c s e d d d v, 9 1 p , 2 n , 7 1 l , 3 j , 8 1 f , 2 e , 5 1 d , 1 1 d , 5 d , 4 1 c , 8 b 0 2 w , 5 1 v , 7 v , 1 v , 0 1 u r e w o p l a t i g i d v 3 . 3 + s s v, 8 1 d , 2 1 d , 2 c , 0 2 a , 7 1 a , 5 1 a , 0 1 a , 8 a , 5 a , 3 a , 2 r , 8 1 p , 1 n , 8 1 m , 9 1 k , 4 k , 2 j , 7 1 h , 7 1 g , 2 g , 3 e 3 1 y 6 y 1 1 w 7 1 v 7 1 u , 4 1 u , 9 u , 2 u , 8 1 t d n u o r g l a t i g i d c c v a1 y l l p r o f v 3 . 3 g o l a n a d n g a4 u l l p r o f d n u o r g g o l a n a 3.2.6 power and ground 3.3 pi7c7100 pbga pin list . o n n i pe m a ne p y t. o n n i pe m a ne p y t 1 a] 2 [ e b c _ 2 sb p2 a# y d r t _ 2 ss t s p 3 as s vC 4 a] 1 [ e b c _ 2 sb p 5 as s vC 6 a] 0 1 [ d a _ 2 sb p 7 a] 0 [ e b c _ 2 sb p8 as s vC 9 a] 2 [ d a _ 2 sb p0 1 as s vC 1 1 a] 7 [ t u o k l c _ ss t p2 1 a] 6 [ # q e r _ 1 su i p 3 1 a] 5 [ t u o k l c _ ss t p4 1 a] 6 [ # t n g _ 1 so p 5 1 as s vC 6 1 a] 2 [ # q e r _ 1 su i p 7 1 as s vC 8 1 a] 1 [ t u o k l c _ ss t p 9 1 a] 0 [ t u o k l c _ ss t p0 2 as s vC 1 b] 6 1 [ d a _ 2 sb p2 b# y d r i _ 2 ss t s p 3 b# k c o l _ 2 ss t s p4 br a p _ 2 sb p 5 b] 4 1 [ d a _ 2 sb p6 b] 1 1 [ d a _ 2 sb p 7 b] 8 [ d a _ 2 sb p8 bd d vC 9 b] 3 [ d a _ 2 sb p0 1 b# t e s e r _ 1 so p 1 1 b] 7 [ # q e r _ 1 su i p2 1 b] 6 [ # t n g _ 1 so p 3 1 b] 7 [ # t n g _ 1 so p4 1 b] 4 [ t u o k l c _ ss t p 5 1 b] 3 [ t u o k l c _ ss t p6 1 b] 2 [ # t n g _ 1 so p 7 1 b] 0 [ # q e r _ 1 su i p8 1 b] 0 [ # t n g _ 1 so p 9 1 b] 0 3 [ d a _ 1 sb p0 2 b] 1 3 [ d a _ 1 sb p 1 c] 7 1 [ d a _ 2 sb p2 cs s vC 3 c# p o t s _ 2 ss t s p4 c# r e s _ 2 si p 5 c] 5 1 [ d a _ 2 sb p6 c] 2 1 [ d a _ 2 sb p 7 c] 9 [ d a _ 2 sb p8 c] 6 [ d a _ 2 sb p 9 c] 4 [ d a _ 2 sb p0 1 c] 0 [ d a _ 2 sb p 1 1 c] 7 [ # t n g _ 1 so p2 1 c] 6 [ t u o k l c _ ss t p 3 1 c] 4 [ # q e r _ 1 su i p4 1 cd d vC 5 1 c] 3 [ # q e r _ 1 su i p6 1 c] 2 [ t u o k l c _ ss t p
10 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information . o n n i pe m a ne p y t. o n n i pe m a ne p y t 7 1 c] 1 [ # q e r _ 1 su i p8 1 c] 7 2 [ d a _ 1 sb p 9 1 c] 8 2 [ d a _ 1 sb p0 2 c] 9 2 [ d a _ 1 sb p 1 d] 8 1 [ d a _ 2 sb p2 d# e m a r f _ 2 ss t s p 3 d# l e s v e d _ 2 ss t s p4 d# r r e p _ 2 ss t s p 5 dd d vC 6 d] 3 1 [ d a _ 2 sb p 7 dn e 6 6 m _ sC 8 d] 7 [ d a _ 2 sb p 9 d] 5 [ d a _ 2 sb p0 1 d] 1 [ d a _ 2 sb p 1 1 dd d vC 2 1 ds s vC 3 1 d] 5 [ # q e r _ 1 su i p4 1 d] 3 [ # t n g _ 1 so p 5 1 dd d vC 6 1 d] 1 [ # t n g _ 1 so p 7 1 d] 4 2 [ d a _ 1 sb p8 1 ds s vC 9 1 d] 5 2 [ d a _ 1 sb p0 2 d] 6 2 [ d a _ 1 sb p 1 e] 0 2 [ d a _ 2 sb p2 ed d vC 3 es s vC 4 e] 9 1 [ d a _ 2 sb p 7 1 e] 1 2 [ d a _ 1 sb p8 1 e] 2 2 [ d a _ 1 sb p 9 1 e] 3 2 [ d a _ 1 sb p0 2 e] 3 [ e b c _ 1 sb p 1 f] 3 [ e b c _ 2 sb p2 f] 3 2 [ d a _ 2 sb p 3 f] 2 2 [ d a _ 2 sb p4 f] 1 2 [ d a _ 2 sb p 7 1 f] 8 1 [ d a _ 1 sb p8 1 fd d vC 9 1 f] 9 1 [ d a _ 1 sb p0 2 f] 0 2 [ d a _ 1 sb p 1 g] 6 2 [ d a _ 2 sb p2 gs s vC 3 g] 5 2 [ d a _ 2 sb p4 g] 4 2 [ d a _ 2 sb p 7 1 gs s vC 8 1 g] 2 [ e b c _ 1 sb p 9 1 g] 6 1 [ d a _ 1 sb p0 2 g] 7 1 [ d a _ 1 sb p 1 h] 0 3 [ d a _ 2 sb p2 h] 9 2 [ d a _ 2 sb p 3 h] 8 2 [ d a _ 2 sb p4 h] 7 2 [ d a _ 2 sb p 7 1 hs s vC 8 1 h# y d r t _ 1 ss t s p 9 1 h# y d r i _ 1 ss t s p0 2 h# e m a r f _ 1 ss t s p 1 j] 8 [ t u o k l c _ ss t p2 js s vC 3 jd d vC 4 j] 1 3 [ d a _ 2 sb p 7 1 j# r r e p _ 1 ss t s p8 1 j# k c o l _ 1 ss t s p 9 1 j# p o t s _ 1 ss t s p0 2 j# l e s v e d _ 1 ss t s p 3.3 pi7c7100 pbga pin list (continued)
11 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information . o n n i pe m a ne p y t. o n n i pe m a ne p y t 1 k] 1 [ # q e r _ 2 su i p2 k] 0 [ # t n g _ 2 so p 3 k] 0 [ # q e r _ 2 su i p4 ks s vC 7 1 k] 1 [ e b c _ 1 sb p8 1 kr a p _ 1 sb p 9 1 ks s vC 0 2 k# r r e s _ 1 si p 1 l] 1 [ # t n g _ 2 so p2 l] 9 [ t u o k l c _ ss t p 3 l] 0 1 [ t u o k l c _ ss t p4 l] 2 [ # t n g _ 2 so p 7 1 ld d vC 8 1 l] 3 1 [ d a _ 1 sb p 9 1 l] 4 1 [ d a _ 1 sb p0 2 l] 5 1 [ d a _ 1 sb p 1 m] 2 [ # q e r _ 2 su i p2 m] 3 [ # q e r _ 2 su i p 3 m] 3 [ # t n g _ 2 so p4 m] 1 1 [ t u o k l c _ ss t p 7 1 m] 0 1 [ d a _ 1 sb p8 1 ms s vC 9 1 m] 1 1 [ d a _ 1 sb p0 2 m] 2 1 [ d a _ 1 sb p 1 ns s vC 2 nd d vC 3 n] 2 1 [ t u o k l c _ ss t p4 n] 4 [ # t n g _ 2 so p 7 1 n] 6 [ d a _ 1 sb p8 1 n] 7 [ d a _ 1 sb p 9 1 n] 8 [ d a _ 1 sb p0 2 n] 9 [ d a _ 1 sb p 1 p] 4 [ # q e r _ 2 su i p2 p] 5 [ # q e r _ 2 su i p 3 p] 3 1 [ t u o k l c _ ss t p4 p] 6 [ # t n g _ 2 so p 7 1 p] 5 [ d a _ 1 sb p8 1 ps s vC 9 1 pd d vC 0 2 p] 0 [ e b c _ 1 sb p 1 r] 5 [ # t n g _ 2 so p2 rs s vC 3 r] 6 [ # q e r _ 2 su i p4 rd e v r e s e rC 7 1 r] 0 [ d a _ pb p8 1 r] 2 [ d a _ 1 sb p 9 1 r] 3 [ d a _ 1 sb p0 2 r] 4 [ d a _ 1 sb p 1 t] 4 1 [ t u o k l c _ ss t p2 t] 7 [ # q e r _ 2 su i p 3 t] 5 1 [ t u o k l c _ ss t p4 t# t e s e r _ 2 so p 7 1 t] 1 [ d a _ pb p8 1 ts s vC 9 1 t] 0 [ d a _ 1 sb p0 2 t] 1 [ d a _ 1 sb p 1 u] 7 [ # t n g _ 2 so p2 us s vC 3 u# t s r tu i c4 ud n g aC 5 un e _ n a c su i c6 u1 o p m cC 7 u# t n g _ pi p8 u] 6 2 [ d a _ pb p 3.3 pi7c7100 pbga pin list (continued)
12 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information . o n n i pe m a ne p y t. o n n i pe m a ne p y t 9 us s vC 0 1 ud d vC 1 1 u] 9 1 [ d a _ pb p2 1 u] 2 [ e b c _ p 3 1 u# y d r t _ pb p4 1 us s vC 5 1 ur a p _ pb p6 1 u] 1 [ e b c _ pb p 7 1 us s vC 8 1 u] 0 1 [ d a _ pb p 9 1 u] 7 [ d a _ pb p0 2 u] 4 [ d a _ pb p 1 vd d vC 2 vk c tu i c 3 vo d to t c4 v# m t _ n a c si c 5 vn i k l c _ si p6 vk l c _ pi p 7 vd d vC 8 v] 7 2 [ d a _ pb p 9 v] 3 [ e b c _ pb p0 1 v] 2 2 [ d a _ pb p 1 1 v] 0 2 [ d a _ pb p2 1 v] 6 1 [ d a _ pb p 3 1 v# y d r i _ pb p4 1 v# k c o l _ ps t s p 5 1 vd d vC 6 1 v] 5 1 [ d a _ pb p 7 1 vs s vC 8 1 vn e 6 6 m _ pC 9 1 v] 0 [ e b c _ pb p0 2 v] 3 [ d a _ pb p 1 ws m tu i c2 wi d tu i c 3 wn e _ 1 su i p4 wn e _ 2 su i p 5 w# h s u l f _ pi p6 w# q e r _ ps t p 7 w] 0 3 [ d a _ pb p8 w] 8 2 [ d a _ pb p 9 w] 4 2 [ d a _ pb p0 1 w] 3 2 [ d a _ pb p 1 1 ws s vC 2 1 w] 7 1 [ d a _ pb p 3 1 w# e m a r f _ pb p4 1 w# p o t s _ ps t s p 5 1 w# r r e s _ pd o p6 1 w] 4 1 [ d a _ pb p 7 1 w] 2 1 [ d a _ pb p8 1 w] 9 [ d a _ pb p 9 1 w] 6 [ d a _ pb p0 2 wd d vC 1 yc c v aC 2 y# n f c _ su i c 3 ym t _ l l pC 4 ys s a p y bC 5 y# t e s e r _ pi p6 ys s vC 7 y] 1 3 [ d a _ pb p8 y] 9 2 [ d a _ pb p 9 y] 5 2 [ d a _ pb p0 1 yl e s d i _ pi p 1 1 y] 1 2 [ d a _ pb p2 1 y] 8 1 [ d a _ pb p 3 1 ys s vC 4 1 y# l e s v e d _ ps t s p 5 1 y# r r e p _ ps t s p6 1 y] 3 1 [ d a _ pb p 7 1 y] 1 1 [ d a _ pb p8 1 y] 8 [ d a _ pb p 9 1 y] 5 [ d a _ pb p0 2 y] 2 [ d a _ pb p 3.3 pi7c7100 pbga pin list (continued)
13 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 4. pci bus operation this chapter offers information about pci transactions, transaction forwarding across pi7c7100, and transaction termination. the pi7c7100 has three 128-byte buffers for buffering of upstream and downstream transactions. these hold addresses, data, commands, and byte enables and are used for both read and write transactions. 4.1 types of transactions this section provides a summary of pci transactions performed by pi7c7100. table 4C1 lists the command code and name of each pci transaction. the master and target columns indicate support for each transaction when pi7c7100 initiates transactions as a master, on the primary (p) and secondary (s1, s2) buses, and when pi7c7100 responds to transactions as a target, on the primary (p) and secondary (s1, s2) buses. s n o i t c a s n a r t f o e p y tr e t s a m s a s e t a i t i n it e g r a t s a s d n o p s e r y r a m i r py r a d n o c e sy r a m i r py r a d n o c e s 0 0 0 0e g d e l w o n k c a t p u r r e t n innnn 1 0 0 0e l c y c l a i c e p syynn 0 1 0 0d a e r o / iyyyy 1 1 0 0e t i r w o / iyyyy 0 0 1 0d e v r e s e rnnnn 1 0 1 0d e v r e s e rnnnn 0 1 1 0d a e r y r o m e myyyy 1 1 1 0e t i r w y r o m e myyyy 0 0 0 1d e v r e s e rnnnn 1 0 0 1d e v r e s e rnnnn 0 1 0 1d a e r n o i t a r u g i f n o cnyyn 1 1 0 1e t i r w n o i t a r u g i f n o c) y l n o 1 e p y t ( yyy ) y l n o 1 e p y t ( y 0 0 1 1e l p i t l u m d a e r y r o m e myyyy 1 0 1 1e l c y c s s e r d d a l a u dnnnn 0 1 1 1e n i l d a e r y r o m e myyyy 1 1 1 1e t a d i l a v n i d n a e t i r w y r o m e mnnyy table 4-1. pci transactions as indicated in table 4C1, the following pci commands are not supported by pi7c7100: ? pi7c7100 never initiates a pci transaction with a reserved command code and, as a target, pi7c7100 ignores reserved command codes. ? pi7c7100 does not generate interrupt acknowledge transactions. pi7c7100 ignores interrupt acknowledge transactions as a target. ? pi7c7100 does not respond to special cycle transactions. pi7c7100 cannot guarantee delivery of a special cycle transaction to downstream buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. to generate special cycle transactions on other pci buses, either upstream or downstream, type 1 configuration write must be used. ? pi7c7100 neither generates type 0 configuration transactions on the primary pci bus nor responds to type 0 configuration transactions on the secondary pci buses. ? pi7c7100 does not support dac (dual address cycle) transactions.
14 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 4.2 single address phase a 32-bit address uses a single address phase. this address is driven on p_ad[31:0], and the bus command is driven on p_cbe[3:0]. pi7c7100 supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. if either of the lowest two address bits is nonzero, pi7c7100 automatically disconnects the transaction afte r the first data transfer. 4.3 device select (devsel#) generation pi7c7100 always performs positive address decoding (medium decode) when accepting transactions on either the primary or secondary buses. pi7c7100 never does subtractive decode. 4.4 data phase the address phase of a pci transaction is followed by one or more data phases. a data phase is completed when irdy# and either trdy# or stop# are asserted. a transfer of data occurs only when both irdy# and trdy# are asserted during the same pci clock cycle. the last data phase of a transaction is indicated when frame# is de-asserted and both trdy# and irdy# are asserted, or when irdy# and stop# are asserted. see section 4.8 for further discussion of transaction termination. depending on the command type, pi7c7100 can support multiple data phase pci transactions. for a detailed description of how pi7c7100 imposes disconnect boundaries, see section 4.5.4 for write address boundaries and section 4.6.3 read address boundaries. 4.5 write transactions write transactions are treated as either posted write or delayed write transactions. table 4C2 shows the method of forwarding used for each type of write operation. n o i t c a s n a r t f o e p y t g n i d r a w r o f f o e p y t e t i r w y r o m e m ) y r o m e m a g v t p e c x e ( d e t s o p e t a d i l a v n i d n a e t i r w y r o m e md e t s o p e t i r w o / id e y a l e d e t i r w n o i t a r u g i f n o c 1 e p y td e y a l e d table 4-2. write transaction forwarding 4.5.1 posted write transactions posted write forwarding is used for memory write and memory write and invalidate transactions. when pi7c7100 determines that a memory write transaction is to be forwarded across the bridge, pi7c7100 asserts devsel# with medium timing and trdy# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one dword of data. under this condition, pi7c7100 accepts write data without obtaining access to the target bus. the pi7c7100 can accept one dword of write data every pci clock cycle. that is, no target wait state is inserted. the write data is stored in an internal posted write buffers and is subsequently delivered to the target. the pi7c7100 continues to accept write data until one of the following events occurs: ? the initiator terminates the transaction by de-asserting frame# and irdy#. ? an internal write address boundary is reached, such as a cache line boundary or an aligned 4kb boundary, depending on the transaction type. ? the posted write data buffer fills up. for timing diagrams, see figures 15-22 and 27-30 in appendix a
15 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information when one of the last two events occurs, the pi7c7100 returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. once the posted write data moves to the head of the posted data queue, pi7c7100 asserts its request on the target bus. this can occur while pi7c7100 is still receiving data on the initiator bus. when the grant for the target bus is received and the target bus is detected in the idle condition, pi7c7100 asserts frame# and drives the stored write address out on the target bus. on the following cycle, pi7c7100 drives the first dword of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. as long as write data exists in the queue, pi7c7100 can drive one dword of write data each pci clock cycle; that is, no master wait states are inserted. if write data is flowing through pi7c7100 and the initiator stalls, pi7c7100 will signal the last data phase for the current transaction at the target bus if the queue empties. pi7c7100 will restart the follow-on transactions if the queue has new data. pi7c7100 ends the transaction on the target bus when one of the following conditions is met: ? all posted write data has been delivered to the target. ? the target returns a target disconnect or target retry (pi7c7100 starts another transac tion to deliver the rest of write data). ? the target returns a target abort (pi7c7100 discards remaining write data). ? the master latency timer expires, and pi7c7100 no longer has the target bus grant (pi7c7100 starts another transaction to deliver remaining write data). section 4.8.3.2 provides detailed information about how pi7c7100 responds to target termination during posted write transactions. 4.5.2 memory write and invalidate transactions posted write forwarding is used for memory write and invalidate transactions. pi7c7100 always converts memory write and invalidate transactions to memory write transactions. the pi7c7100 disconnects memory write and invalidate commands at aligned cache line boundaries. the cache line size value in the cache line size register gives the number of dword in a cache line. if the value in the cache line size register does meet the memory write and invalidate conditions, the pi7c7100 returns a target disconnect to the initiator either on a cache line boundary or when the posted write buffer fills. when the memory write and invalidate transaction is disconnected before a cache line boundary is reached, typically because the posted write buffer fills, the transaction is converted to memory write transaction. 4.5.3 delayed write transactions delayed write forwarding is used for i/o write transactions and type 1 configuration write transactions. a delayed write transaction guarantees that the actual target response is returned back to the initiator without holding the initiating bus in wait states. a delayed write transaction is limited to a single dword data transfer. when a write transaction is first detected on the initiator bus, and pi7c7100 forwards it as a delayed transaction, pi7c7100 claims the access by asserting devsel# and returns a target retry to the initiator. during the address phase, pi7c7100 samples the bus command, address, and address parity one cycle later. after irdy# is asserted, pi7c7100 also samples the first data dword, byte enable bits, and data parity. this information is placed into the delayed transaction queue. the transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transaction queue is not full. when the delayed write transaction moves to the head of the delayed transaction queue and all ordering constraints with posted data are satisfied. the pi7c7100 initiates the transaction on the target bus. pi7c7100 transfers the write data to the target. if pi7c7100 receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered. if pi7c7100 is unable to deliver write data after 2 24 (default) or 2 32 (maximum) attempts, pi7c7100 will report a system error. pi7c7100 also asserts p_serr# if the primary serr# enable bit is set in the command register. see section 7.4 for information on the assertion of p_serr#. when the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the pi7c7100
16 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information n o i t c a s n a r t f o e p y tn o i t i d n o cy r a d n u o b s s e r d d a d e n g i l a e t i r w d e y a l e dl l a r e f s n a r t a t a d e n o r e t f a s t c e n n o c s i d e t i r w y r o m e m d e t s o p 6 1 , 8 , 4 , 2 , 1 o t l a u q e t o n e z i s e n i l e h c a c y r a d n u o b s s e r d d a d e n g i l a b k 4 e t i r w y r o m e m d e t s o p6 1 , 8 , 4 , 2 , 1 = e z i s e n i l e h c a c y r a d n u o b e n i l e h c a c t a s t c e n n o c s i d e t a d i l a v n i d n a e t i r w y r o m e m d e t s o p 6 1 , 8 , 4 , 2 , 1 o t l a u q e t o n e z i s e n i l e h c a c y r a d n u o b s s e r d d a d e n g i l a b k 4 e t a d i l a v n i d n a e t i r w y r o m e m d e t s o p6 1 , 8 , 4 , 2 , 1 = e z i s e n i l e h c a c, y r a d n u o b e n i l e h c a c table 4-3. write transaction disconnect address boundaries note 1. memory-write-disconnect-control bit is bit 1 of the chip control register at offset 40h in configuration space. 4.5.5 buffering multiple write transactions pi7c7100 continues to accept posted memory write transactions as long as space for at least one dword of data in the posted write data buffer remains. if the posted write data buffer fills before the initiator terminates the write transact ion, pi7c7100 returns a target disconnect to the initiator. delayed write transactions are posted as long as at least one open entry in the delayed transaction queue exists. therefore, several posted and delayed write transactions can exist in data buffers at the same time. see chapter 6 for information about how multiple posted and delayed write transactions are ordered. 4.5.6 fast back-to-back write transactions pi7c7100 can recognize and post fast back-to-back write transactions. when pi7c7100 cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. claims the access by asserting devsel# and returns trdy# to the initiator, to indicate that the write data was transferred. if the initiator requests multiple dword, pi7c7100 also asserts stop# in conjunction with trdy# to signal a target disconnect. note that only those bytes of write data with valid byte enable bits are compared. if any of the byte enable bits are turned off (driven high), the corresponding byte of write data is not compared. if the initiator repeats the write transaction before the data has been transferred to the target, pi7c7100 returns a target retry to the initiator. pi7c7100 continues to return a target retry to the initiator until write data is delivered to the targe t, or until an error condition is encountered. when the write transaction is repeated, pi7c7100 does not make a new entry into the delayed transaction queue. section 4.8.3.1 provides detailed information about how pi7c7100 responds to target termination during delayed write transactions. pi7c7100 implements a discard timer that starts counting when the delayed write completion is at the head of the delayed transaction queue. the initial value of this timer can be set to the retry counter register offset 78h. if the initiator does n ot repeat the delayed write transaction before the discard timer expires, pi7c7100 discards the delayed write completion from the delayed transaction queue. pi7c7100 also conditionally asserts p_serr# (see section 7.4). 4.5.4 write transaction address boundaries pi7c7100 imposes internal address boundaries when accepting write data. the aligned address boundaries are used to prevent pi7c7100 from continuing a transaction over a device address bound ary and to provide an upper limit on maximum latency. pi7c7100 returns a target disconnect to the initiator when it reaches the alig ned address boundaries under conditions shown in table 4C3.
17 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 4.6 read transactions delayed read forwarding is used for all read transactions crossing pi7c7100. delayed read transactions are treated as either prefetchable or non-prefetchable. table 4-4 shows the read beh avior, prefetchable or non-prefetchable, for each type of read operation. for timing diagrams, see figures 11-14 and 23-26 in appendix a 4.6.1 prefetchable read transactions a prefetchable read transaction is a read transaction where pi7c7100 performs speculative dword reads, transferring data from the target before it is requested from the initiator. this behavior allows a prefetchable read transaction to consist of multiple data transfers. however, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non-prefetchable read transaction. for prefetchable read transactions, pi7c7100 forces all byte enable bits to be turned on for all data phases. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. the amount of data that is pre-fetched depends on the type of transaction. the amount of pre-fetching may also be affected by the amount of free buffer space available in pi7c7100, and by any read address boundaries encountered. pre-fetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, fi fos, and so on. the target devices base address register or registers indicate if a memory address region is prefetchable. 4.6.2 non-prefetchable read transactions a non-prefetchable read transaction is a read transaction where pi7c7100 requests one and only one dword from the target and disconnects the initiator after delivery of the first dword of read data. unlike prefetchable read transactions, pi7c7100 forwards the read byte enable information for the data phase. non-prefetchable behavior is used for i/o and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. if extra read transactions could have side effects, for example, when accessing a fifo, use non-prefetchable read transactions to those locations. accordingly, if it is important to retain the value of the byte enable bits during the data ph ase, use non-prefetchable read transactions. if these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped i/o) memory space to use non-prefetching behavior. 4.6.3 read pre-fetch address boundaries pi7c7100 imposes internal read address boundaries on read pre-fetched data. when a read transaction reaches one of these aligned address boundaries, the pi7c7100 stops pre-fetched data, unless the target signals a target disconnect before the read pre-fetched boundary is reached. when pi7c7100 finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. any leftover pre-fetched data is discarded. prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4kb address boundary, or until the initiator de-asserts frame#. section 4.6.6 describes flow-through mode during read operations. table 4-5 shows the read pre-fetch address boundaries for read transactions during non-flow-through mode. table 4-4. read pre-fetch address boundaries n o i t c a s n a r t f o e p y te c a p s s s e r d d a) s l c ( e z i s e n i l e h c a cy r a d n u o b s s e r d d a d e n g i l a h c t e f - e r p d a e r g i f n o c-- ) h c t e f - e r p o n ( d r o w d e n o d a e r o / i-- ) h c t e f - e r p o n ( d r o w d e n o d a e r y r o m e me l b a h c t e f e r p - n o n- ) h c t e f - e r p o n ( d r o w d e n o d a e r y r o m e me l b a h c t e f e r p8 , 4 , 2 , 1 o t l a u q e t o n s l cy r a d n u o b s s e r d d a d e n g i l a d r o w d - 6 1 d a e r y r o m e me l b a h c t e f e r p8 , 4 , 2 , 1 = s l cy r a d n u o b s s e r d d a e n i l e h c a c e n i l d a e r y r o m e m- 8 , 4 , 2 , 1 o t l a u q e t o n s l cy r a d n u o b s s e r d d a d e n g i l a d r o w d - 6 1 e n i l d a e r y r o m e m- 8 , 4 , 2 , 1 = s l cy r a d n u o b e n i l e h c a c e l p i t l u m d a e r y r o m e m- 8 , 4 , 2 , 1 o t l a u q e t o n s l cy r a d n u o b s s e r d d a d e n g i l a d r o w d - 2 3 e l p i t l u m d a e r y r o m e m- 8 , 4 , 2 , 1 = s l cy r a d n u o b e n i l e h c a c f o s e m i t 2
18 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 4.6.4 delayed read requests pi7c7100 treats all read transactions as delayed read transactions, which means that the read request from the initiator is posted into a delayed transaction queue. read data from the target is placed in the read data queue directed toward the initiator bus interface and is transferred to the initiator when the initiator repeats the read transaction. when pi7c7100 accepts a delayed read request, it first samples the read address, read bus command, and address parity. when irdy# is asserted, pi7c7100 then samples the byte enable bits for the first data phase. this information is entered into the delayed transaction queue. pi7c7100 terminates the transaction by signaling a target retry to the initiator. upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one dat a transfer is completed, or until a target response (target abort or master abort) other than a target retry is received. 4.6.5 delayed read completion with target when delayed read request reaches the head of the delayed transaction queue, pi7c7100 arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. pi7c7100 uses the exact read address and read command captured from the initiator during the initial delayed read request to initiate the read transaction. if the read transaction is a non-prefetchable read, pi7c7100 drives the captured byte enable bits during the next cycle. if the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all da ta phases. if pi7c7100 receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered. if the transact ion is terminated via normal master termination or target disconnect after at least one data transfer has been completed, pi7c7100 does not initiate any further attempts to read more data. if pi7c7100 is unable to obtain read data from the target after 2 24 (default) or 2 32 (maximum) attempts, pi7c7100 will report system error. the number of attempts is programmable. pi7c7100 also asserts p_serr# if the primary serr# enable bit is set in the command register. see section 7.4 for information on the assertion of p_serr#. once pi7c7100 receives devsel# and trdy# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite interface, before terminating the transaction. for example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read data queue. the pi7c7100 can accept one dword of read data each pci clock cycle; that is, no master wait states are inserted. the number of dword transferred during a delayed read transaction depends on the conditions given in table 4C5 (assuming no disconnect is received from the target). 4.6.6 delayed read completion on initiator bus when the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the pi7c7100 transfers the data to the initiator when the initiator repeats the transaction. for memory read transactions, pi7c7100 aliases the memory read, memory read line, and memory read multiple bus commands when matching the bus command of the transaction to the bus command in the delayed transaction queue. pi7c7100 returns a target disconnect along with the transfer of the last dword of read data to the initiator. if pi7c7100 initiator terminates the transaction before all read data has been transferred, the remaining read data left in data buffers is discarded. n o i t c a s n a r t f o e p y tr o i v a h e b d a e r d a e r o / ie n o d r e v e n g n i h c t e f - e r p d a e r n o i t a r u g i f n o ce n o d r e v e n g n i h c t e f - e r p d a e r y r o m e m e c a p s e l b a h c t e f e r p n i s s e r d d a f i d e s u g n i h c t e f - e r p : m a e r t s n w o d d e s u g n i h c t e f - e r p : m a e r t s p u e n i l d a e r y r o m e md e s u s y a w l a g n i h c t e f - e r p e l p i t l u m d a e r y r o m e md e s u s y a w l a g n i h c t e f - e r p table 4-5. read transaction pre-fetching see section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
19 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information when the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. in this case, the read transaction is allowed to continue until the initiato r terminates the transaction, or until an aligned 4kb address boundary is reached, or until the buffer fills, whichever comes first. when the buffer empties, pi7c7100 reflects the stalled condition to the initiator by de-asserting trdy# until more read data is available; otherwise, pi7c7100 does not insert any target wait states. when the initiator terminates the transaction, pi7c7100 de-assertion of frame# on the initiator bus is forwarded to the target bus. any remaining read data is discarded. pi7c7100 implements a discard timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. the initial value of this timer is programmable through configuration register. if the initiator does not repeat the read transaction and before the discard timer expires (2 15 default), pi7c7100 discards the read transaction and read data from its queues. pi7c7100 also conditionally asserts p_serr# (see section 7.4). pi7c7100 has the capability to post multiple delayed read requests, up to a maximum of four in each direction. if an initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted as it is already contained in the delayed transaction queue. see section 6 for a discussion of how delayed read transactions are ordered when crossing pi7c7100. 4.7 configuration transactions configuration transactions are used to initialize a pci system. every pci device has a configuration space that is accessed by configuration commands. all registers are accessible in configuration space only. in addition to accepting configuration transactions for initialization of its own configuration space, the pi7c7100 also forwards configuration transactions for device initialization in hierarchical pci systems, as well as for special cycle generation. to support hierarchical pci bus systems, two types of configuration transactions are specified: type 0 and type 1. type 0 configuration transactions are issued when the intended target resides on the same pci bus as the initiator. a type 0 configuration transaction is identified by the configuration command and the lowest two bits of the address set to 00b. type 1 configuration transactions are issued when the intended target resides on another pci bus, or when a special cycle is to be generated on another pci bus. a type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. the register number is found in both type 0 and type 1 formats and gives the dword address of the configuration register to be accessed. the function number is also included in both type 0 and type 1 formats and indicates which function of a multifunction device is to be accessed. for single-function devices, this value is not decoded. the addresses of type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target pci bus that is to be accessed. in addition, the bus number in type 1 transactions specifies the pci bus to which the transaction is targeted. for timing diagrams, see figures 1-8 in appendix a. 4.7.1 type 0 access to pi7c7100 the configuration space is accessed by a type 0 configuration transaction on the primary interface. the configuration space cannot be accessed from the secondary bus. the pi7c7100 responds to a type 0 configuration transaction by asserting p_devsel# when the following conditions are met during the address phase: ? the bus command is a configuration read or configuration write transaction. ? lowest two address bits p_ad[1:0] must be 00b. ? signal p_idsel must be asserted. function code is either 0 for configuration space of s1, or 1 for configuration space of s2 as pi7c7100 is a multi-function device. pi7c7100 limits all configuration access to a single dword data transfer and returns target-disconnect with the first data transfer if additional data phases are requested. because read transactions to configuration space do not have side effects, all bytes in the requested dword are returned, regardless of the value of the byte enable bits.
20 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the state of the data buffers. the pi7c7100 ignores all type 0 transactions initiated on the secondary interface. 4.7.2 type 1 to type 0 conversion type 1 configuration transactions are used specifically for device configuration in a hierarchical pci bus system. a pci- to-pci bridge is the only type of device that should respond to a type 1 configuration command. type 1 configuration commands are used when the configuration access is intended for a pci device that resides on a pci bus other than the one where the type 1 transaction is generated. pi7c7100 performs a type 1 to type 0 translation when the type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. pi7c7100 must convert the configuration command to a type 0 format so that the secondary bus device can respond to it. type 1 to type 0 translations are performed only in the downstream direction; that is, pi7c7100 generates a type 0 transaction only on the secondary bus, and never on the primary bus. pi7c7100 responds to a type 1 configuration transaction and translates it into a type 0 transaction on the secondary bus when the following conditions are met during the address phase: ? the lowest two address bits on p_ad[1:0] are 01b. ? the bus number in address field p_ad[23:16] is equal to the value in the secondary bus number register in configuration space. ? the bus command on p_cbe[3:0] is a configuration read or configuration write transaction. ? when pi7c7100 translates the type 1 transaction to a type 0 transaction on the secondary interface, it performs the following translations to the address: ? sets the lowest two address bits on s1_ad[1:0] or s2_ad[1:0] to 00b. ? decodes the device number and drives the bit pattern specified in table 4C6 on s1_ad[31:16] or s2_ad[31:16] for the purpose of asserting the devices idsel signal. ? sets s1_ad[15:11] or s2_ad[15:11] to 0. ? leaves unchanged the function number and register number fields. pi7c7100 asserts a unique address line based on the device number. these address lines may be used as secondary bus idsel signals. the mapping of the address lines depends on the device number in the type 1 address bits p_ad[15:11]. table 4C6 presents the mapping that pi7c7100 uses
21 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information pi7c7100 can assert up to 16 unique address lines to be used as idsel signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 15. because of electrical loading constraints of the pci bus, more than 16 idsel signals should not be necessary. however, if device numbers greater than 15 are desired, some external method of generating idsel lines must be used, and no upper address bits are then asserted. the configuration transaction is still translated and passed from the primary bus to the secondary bus. if no idsel pin is asserted to a secondary device, the transaction ends in a master abort. pi7c7100 forwards type 1 to type 0 configuration read or write transactions as delayed transactions. type 1 to type 0 configuration read or write transactions are limited to a single 32-bit data transfer. 4.7.3 type 1 to type 1 forwarding type 1 to type 1 transaction forwarding provides a hierarchical configuration mechanism when two or more levels of pci- to-pci bridges are used. when pi7c7100 detects a type 1 configuration transaction intended for a pci bus downstream from the secondary bus, pi7c7100 forwards the transaction unchanged to the secondary bus. ultimately, this transaction is translated to a type 0 configuration command or to a special cycle transaction by a downstream pci-to-pci bridge. downstream type 1 to type 1 forwarding occurs when the following conditions are met during the address phase: ? the lowest two address bits are equal to 01b. ? the bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. ? the bus command is a configuration read or write transaction. r e b m u n e c i v e d> 1 1 : 5 1 < d a _ p] 6 1 : 1 3 [ d a _ 1 s l e s d i y r a d n o c e s ] 6 1 : 1 3 [ d a _ 2 s r o t i b d a _ 2 s r o d a _ 1 s h 00 0 0 0 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 06 1 h 11 0 0 0 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 07 1 h 20 1 0 0 00 0 1 0 0 0 0 0 0 0 0 0 0 0 0 08 1 h 31 1 0 0 00 0 0 1 0 0 0 0 0 0 0 0 0 0 0 09 1 h 40 0 1 0 00 0 0 0 1 0 0 0 0 0 0 0 0 0 0 00 2 h 51 0 1 0 00 0 0 0 0 1 0 0 0 0 0 0 0 0 0 01 2 h 60 1 1 00 0 0 0 0 0 1 0 0 0 0 0 0 0 0 02 2 h 71 1 1 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 0 03 2 h 80 0 0 1 00 0 0 0 0 0 0 0 1 0 0 0 0 0 0 04 2 h 91 0 0 1 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 05 2 h a0 1 0 1 00 0 0 0 0 0 0 0 0 0 1 0 0 0 0 06 2 h b1 1 0 1 00 0 0 0 0 0 0 0 0 0 0 1 0 0 0 07 2 h c0 0 1 1 00 0 0 0 0 0 0 0 0 0 0 0 1 0 0 08 2 h d1 0 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 1 0 09 2 h e0 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00 3 h f1 1 1 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 3 h e 1 - h 0 10 1 1 1 1 - 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0- h f 11 1 1 1 1) h 0 0 = ] 2 : 7 [ d a _ p ( e l c y c l a i c e p s e t a r e n e g ) h 0 0 = ] 2 : 7 [ d a _ p ( 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - table 4C6. device number to idsel s1_ad or s2_ad pin mapping
22 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information pi7c7100 also supports type 1 to type 1 forwarding of configuration write transactions upstream to support upstream special cycle generation. a type 1 configuration command is forwarded upstream when the following conditions are met: ? the lowest two address bits are equal to 01b. ? the bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. ? the device number in address bits ad[15:11] is equal to 11111b. ? the function number in address bits ad[10:8] is equal to 111b. ? the bus command is a configuration write transaction. the pi7c7100 forwards type 1 to type 1 configuration write transactions as delayed transactions. type 1 to type 1 configuration write transactions are limited to a single data transfer. 4.7.4 special cycles the type 1 configuration mechanism is used to generate special cycle transactions in hierarchical pci systems. special cycle transactions are ignored by acting as a target and are not forwarded across the bridge. special cycle transactions can be generated from type 1 configuration write transactions in either the upstream or the downstream direction. pi7c7100 initiates a special cycle on the target bus when a type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: ? the lowest two address bits on ad[1:0] are equal to 01b. ? the device number in address bits ad[15:11] is equal to 11111b. ? the function number in address bits ad[10:8] is equal to 111b. ? the register number in address bits ad[7:2] is equal to 000000b. ? the bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. ? the bus command on cbe# is a configuration write command. when pi7c7100 initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. the address and data are forwarded unchanged. devices that use special cycles ignore the address and decode only the bus command. the data phase contains the special cycle message. the transaction is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). once the transaction is completed on the target bus, through detection of the master abort condition, pi7c7100 responds with trdy# to the next attempt of the configuration transaction from the initiator. if more than one data transfer is requested, pi7c7100 responds with a target disconnect operation during the first data phase. 4.8 transaction termination this section describes how pi7c7100 returns transaction termination conditions back to the initiator. the initiator can terminate transactions with one of the following types of termination: ? normal termination normal termination occurs when the initiator de-asserts frame# at the beginning of the last data phase, and de- asserts irdy# at the end of the last data phase in conjunction with either trdy# or stop# assertion from the target. ? master abort a master abort occurs when no target response is detected. when the initiator does not detect a devsel# from the target within five clock cycles after asserting frame#, the initiator terminates the transaction with a master abort. if frame# is still asserted, the initiator de-asserts frame# on the next cycle, and then de-asserts irdy# on the following cycle. irdy# must be asserted in the same cycle in which frame# de-asserts. if frame# is already de-asserted, irdy# can be de-asserted on the next clock cycle following detection of the master abort condition.
23 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information the target can terminate transactions with one of the following types of termination: ? normal termination trdy# and devsel# asserted in conjunction with frame# de-asserted and irdy# asserted. ? target retry stop# and devsel# asserted with trdy# de-asserted during the first data phase. no data transfers occur during the transaction. this transaction must be repeated. ? target disconnect with data transfer stop#, devsel# and trdy# asserted. it signals that this is the last data transfer of the transaction. ? target disconnect without data transfer stop# and devsel# asserted with trdy# de-asserted after previous data transfers have been made. indicates that no more data transfers will be made during this transaction. ? target abort stop# asserted with devsel# and trdy# de-asserted. indicates that target will never be able to complete this transaction. devsel# must be asserted for at least one cycle during the transaction before the target abort is signaled. 4.8.1 master termination initiated by pi7c7100 pi7c7100, as an initiator, uses normal termination if devsel# is returned by target within five clock cycles of pi7c7100s assertion of frame# on the target bus. as an initiator, pi7c7100 terminates a transaction when the following conditions are met: ? during a delayed write transaction, a single dword is delivered. ? during a non-prefetchable read transaction, a single dword is transferred from the target. ? during a prefetchable read transaction, a pre-fetch boundary is reached. ? for a posted write transaction, all write data for the transaction is transferred from data buffers to the target. ? for burst transfer, with the exception of memory write and invalidate transactions, the master latency timer expires and the pi7c7100s bus grant is de-asserted. ? the target terminates the transaction with a retry, disconnect, or target abort. if pi7c7100 is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another transaction to deliver the remaining write data. the address of the transaction is updated to reflect the address of the current dword to be delivered. if pi7c7100 is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data. 4.8.2 master abort received by pi7c7100 if the initiator initiates a transaction on the target bus and does not detect devsel# returned by the target within five clock cycles of the assertion of frame#, pi7c7100 terminates the transaction with a master abort. this sets the received- master-abort bit in the status register corresponding to the target bus. for delayed read and write transactions, pi7c7100 is able to reflect the master abort condition back to the initiator. when pi7c7100 detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, pi7c7100 does not respond to the transaction with devsel# which induces the master abort condition back to the initiator. the transaction is then removed from the delayed transaction queue. when a master abort is received in response to a posted write transaction, pi7c7100 discards the posted write data and makes no more attempt to deliver the data. pi7c7100 sets the received-master-abort bit in the status register when the master abort is received on the primary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. when master abort is detected in posted write transaction with both master-abort-mode bit (bit 5 of bridge control register) and the serr# enable bit (bit 8 of command register for secondary bus s1 or s2) are set, pi7c7100 asserts p_serr# if the master-abort-on-posted-write is not set. the master-abort-on-posted-write bit is bit 4 of the p_serr# event disable register (offset 64h). note: when pi7c7100 performs a type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. in this case, the master abort received bit is not set, and the type 1 configuration transaction is disconnected after the first data phase.
24 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information table 4-7. delayed write target termination response after the pi7c7100 makes 2 24 (default) attempts of the same delayed write transaction on the target bus, pi7c7100 asserts p_serr# if the serr# enable bit (bit 8 of command register for secondary bus s1 or s2) is set and the delayed-write- non-delivery bit is not set. the delayed-write-non-delivery bit is bit 5 of p_serr# event disable register (offset 64h). pi7c7100 will report system error. see section 7.4 for a description of system error conditions. 4.8.3.2 posted write target termination response when pi7c7100 initiates a posted write transaction, the target termination cannot be passed back to the initiator. table 4C8 shows the response to each type of target termination that occurs during a posted write transaction. n o i t a n i m r e t t e g r a t e s n o p s e r l a m r o n s e s a h p a t a d e l p i t l u m f i y l n o r e f s n a r t a t a d t s r i f h t i w r o t a i t i n i o t t c e n n o c s i d g n i n r u t e r . d e t s e u q e r y r t e r t e g r a t . t e g r a t o t s t p m e t t a e t i r w e u n i t n o c . r o t a i t i n i o t y r t e r t e g r a t g n i n r u t e r t c e n n o c s i d t e g r a t s e s a h p a t a d e l p i t l u m f i y l n o r e f s n a r t a t a d t s r i f h t i w r o t a i t i n i o t t c e n n o c s i d g n i n r u t e r . d e t s e u q e r t r o b a t e g r a t e c a f r e t n i t e g r a t n i t i b t r o b a t e g r a t d e v i e c e r t e s . r o t a i t i n i o t t r o b a t e g r a t g n i n r u t e r . r e t s i g e r s u t a t s e c a f r e t n i r o t a i t i n i n i t i b t r o b a t e g r a t d e l a n g i s t e s . r e t s i g e r s u t a t s 4.8.3 target termination received by pi7c7100 when pi7c7100 initiates a transaction on the target bus and the target responds with devsel#, the target can end the transaction with one of the following types of termination: ? normal termination (upon de-assertion of frame#) ? target retry ? target disconnect ? target abort pi7c7100 handles these terminations in different ways, depending on the type of transaction being performed. 4.8.3.1 delayed write target termination response when pi7c7100 initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator. table 4C7 shows the response to each type of target termination that occurs during a delayed write transaction. pi7c7100 repeats a delayed write transaction until one of the following conditions is met: ? pi7c7100 completes at least one data transfer. ? pi7c7100 receives a master abort. ? pi7c7100 receives a target abort. pi7c7100 makes 2 24 (default) or 2 32 (maximum) write attempts resulting in a response of target retry.
25 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information n o i t a n i m r e t t e g r a t e s n o p s e r l a m r o n. n o i t c a l a n o i t i d d a o n y r t e r t e g r a t . t e g r a t o t n o i t c a s n a r t e t i r w g n i t a e p e r t c e n n o c s i d t e g r a t . a t a d e t i r w d e t s o p g n i n i a m e r g n i r e v i l e d r o f n o i t c a s n a r t e t i r w e t a i t i n i t r o b a t e g r a t t r e s s a . r e t s i g e r s u t a t s e c a f r e t n i t e g r a t e h t n i t i b t r o b a - t e g r a t - d e v i e c e r t e s s u t a t s y r a m i r p n i t i b r o r r e - m e t s y s - d e l a n g i s e h t t e s d n a , d e l b a n e f i # r r e s _ p . r e t s i g e r table 4-8. responses to posted write target termination note that when a target retry or target disconnect is returned and posted write data associated with that transaction remains in the write buffers, pi7c7100 initiates another write transaction to attempt to deliver the rest of the write data. if there is a target retry, the exact same address will be driven as for the initial write transaction attempt. if a target disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect the address of the current dword. if the initial write transaction is memory-write-and-invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, pi7c7100 will use the memory write command to deliver the rest of the write data. it is because an incomplete cache line will be transferred in the subsequent write transaction attempt. after the pi7c7100 makes 2 24 (default) write transaction attempts and fails to deliver all posted write data associated with that transaction, pi7c7100 asserts p_serr# if the primary serr# enable bit is set (bit 8 of command register for secondary bus s1 or s2) and posted-write-non-delivery bit is not set. the posted-write-non-delivery bit is the bit 2 of p_serr# event disable register (offset 64h). pi7c7100 will report system error. see section 7.4 for a discussion of system error conditions. 4.8.3.3 delayed read target termination response when pi7c7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. other target responses depend on how much data the initiator requests. table 4C9 shows the response to each type of target termination that occurs during a delayed read transaction. pi7c7100 repeats a delayed read transaction until one of the following conditions is met: ? pi7c7100 completes at least one data transfer. ? pi7c7100 receives a master abort. ? pi7c7100 receives a target abort. ? pi7c7100 makes 2 24 (default) read attempts resulting in a response of target retry. table 4-9. responses to delayed read target termination n o i t a n i m r e t t e g r a t e s n o p s e r l a m r o n d a e r n a h t a t a d e r o m s t s e u q e r r o t a i t i n i f i y l n o t c e n n o c s i d t e g r a t , e l b a h c t e f e r p f i . e s a h p a t a d t s r i f n o t c e n n o c s i d t e g r a t , e l b a h c t e f e r p - n o n f i . t e g r a t m o r f y r t e r t e g r a t . t e g r a t o t n o i t c a s n a r t d a e r e t a i t i n i e r t c e n n o c s i d t e g r a t o t t c e n n o c s i d t e g r a t n r u t e r , t e g r a t m o r f d a e r n a h t a t a d e r o m s t s e u q e r r o t a i t i n i f i . r o t a i t i n i t r o b a t e g r a t e c a f r e t n i t e g r a t e h t n i t i b t r o b a t e g r a t d e v i e c e r t e s . r o t a i t i n i o t t r o b a t e g r a t n r u t e r s u t a t s e c a f r e t n i r o t a i t i n i e h t n i t i b t r o b a t e g r a t d e l a n g i s t e s . r e t s i g e r s u t a t s . r e t s i g e r
26 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information after pi7c7100 makes 2 24 (default) attempts of the same delayed read transaction on the target bus, pi7c7100 asserts p_serr# if the primary serr# enable bit is set (bit 8 of command register for secondary bus s1 or s2) and the delayed- write-non-delivery bit is not set. the delayed-write-non-delivery bit is bit 5 of p_serr# event disable register (offset 64h). pi7c7100 will report system error. see section 7.4 for a description of system error conditions. 4.8.4 target termination initiated by pi7c7100 pi7c7100 can return a target retry, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 4.8.4.1 target retry pi7c7100 returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. pi7c7100 returns a target retry to an initiator when any of the following conditions is met: for delayed write transactions: ? the transaction is being entered into the delayed transaction queue. ? transaction has already been entered into delayed transaction queue, but target response has not yet been received. ? target response has been received but has not progressed to the head of the return queue. ? the delayed transaction queue is full, and the transaction cannot be queued. ? a transaction with the same address and command has been queued. ? a locked sequence is being propagated across pi7c7100, and the write transaction is not a locked transaction. ? the target bus is locked and the write transaction is a locked transaction. ? use more than 16 clocks to accept this transaction. for delayed read transactions: ? the transaction is being entered into the delayed transaction queue. ? the read request has already been queued, but read data is not yet available. ? data has been read from target, but it is not yet at head of the read data queue, or a posted write transaction precedes it. ? the delayed transaction queue is full, and the transaction cannot be queued. ? a delayed read request with the same address and bus command has already been queued. ? a locked sequence is being propagated across pi7c7100, and the read transaction is not a locked transaction. ? pi7c7100 is currently discarding previously pre-fetched read data. ? the target bus is locked and the write transaction is a locked transaction. ? use more than 16 clocks to accept this transaction. for posted write transactions: ? the posted write data buffer does not have enough space for address and at least one dword of write data. ? a locked sequence is being propagated across pi7c7100, and the write transaction is not a locked transaction. when a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. otherwise, the transaction is discarded from the buffers.
27 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 4.8.4.2 target disconnect pi7c7100 returns a target disconnect to an initiator when one of the following conditions is met: ? pi7c7100 hits an internal address boundary. ? pi7c7100 cannot accept any more write data. ? pi7c7100 has no more read data to deliver. see section 4.5.4 for a description of write address boundaries, and section 4.6.3 for a description of read address boundaries. 4.8.4.3 target abort pi7c7100 returns a target abort to an initiator when one of the following conditions is met: ? pi7c7100 is returning a target abort from the intended target. when pi7c7100 returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. 4.9 concurrent mode operation the bridge can be configured to run in concurrent operation. concurrent operation is defined as cycles going from one device on one secondary bus to another device on the same or other secondary bus. this off-loads traffic from the primary bus, allowing other traffic to run on the primary bus concurrently. the bridge is already configured to handle concurrent operation. however, the devices themselves need to be configured to do so. meaning, device drivers for the specific device used will have to be configured to perform the operation. please contact pericom for more information.
28 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 5. address decoding pi7c7100 uses three address ranges that control i/o and memory transaction forwarding. these address ranges are defined by base and limit address registers in the configuration space. this chapter describes these address ranges, as well as isa- mode and vga-addressing support. 5.1 address ranges pi7c7100 uses the following address ranges that determine which i/o and memory transactions are forwarded from the primary pci bus to the secondary pci bus, and from the secondary bus to the primary bus: ? two 32-bit i/o address ranges ? two 32-bit memory-mapped i/o (non-prefetchable memory) ranges ? two 32-bit prefetchable memory address ranges transactions falling within these ranges are forwarded downstream from the primary pci bus to the two secondary pci buses. transactions falling outside these ranges are forwarded upstream from the two secondary pci buses to the primary pci bus. no address translation is required in pi7c7100. the addresses that are not marked for downstream are always forwarded upstream. however, if an address of a transaction initiated from s1 bus is located in the marked address range for downstream in s2 bus and not in the marked address range for downstream in s1 bus, the transaction will be forwarded to s2 bus instead of primary bus. by the same token, if an address of a transaction initiated from s2 bus is located in the marked address range for downstream in s1 bus and not in the marked address range for downstream in s2 bus, the transaction will be forwarded to s1 bus instead of primary bus. 5.2 i/o address decoding pi7c7100 uses the following mechanisms that are defined in the configuration space to specify the i/o address space for downstream and upstream forwarding: ? i/o base and limit address registers ? the isa enable bit ? the vga mode bit ? the vga snoop bit this section provides information on the i/o address registers and isa mode. section 5.4 provides information on the vga modes. to enable downstream forwarding of i/o transactions, the i/o enable bit must be set in the command register in configuration space. all i/o transactions initiated on the primary bus will be ignored if the i/o enable bit is not set. to enable upstream forwarding of i/o transactions, the master enable bit must be set in the command register. if the master- enable bit is not set, pi7c7100 ignores all i/o and memory transactions initiated on the secondary bus. the master- enable bit also allows upstream forwarding of memory transactions if it is set. caution if any configuration state affecting i/o transaction forwarding is changed by a configuration write operation on the primary bus at the same time that i/o transactions are ongoing on the secondary bus, pi7c7100 response to the secondary bus i/o transactions is not predictable. configure the i/o base and limit address registers, isa enable bit, vga mode bit, and vga snoop bit before setting i/o enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle. 5.2.1 i/o base and limit address registers pi7c7100 implements one set of i/o base and limit address registers in configuration space that define an i/o address range per port downstream forwarding. pi7c7100 supports 32-bit i/o addressing, which allows i/o addresses downstream of pi7c7100 to be mapped anywhere in a 4gb i/o address space.
29 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information i/o transactions with addresses that fall inside the range defined by the i/o base and limit registers are forwarded downstream from the primary pci bus to the secondary pci bus. i/o transactions with addresses that fall outside this range are forwarded upstream from the secondary pci bus to the primary pci bus. the i/o range can be turned off by setting the i/o base address to a value greater than that of the i/o limit address. when the i/o range is turned off, all i/o transactions are forwarded upstream, and no i/o transactions are forwarded downstream. the i/o range has a minimum granularity of 4kb and is aligned on a 4kb boundary. the maximum i/o range is 4gb in size. the i/o base register consists of an 8-bit field at configuration address 1ch, and a 16-bit field at address 30h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o base address. the bottom 4 bits read only as 1h to indicate that pi7c7100 supports 32-bit i/o addressing. bits [11:0] of the base address are assumed to be 0, which naturally aligns the base address to a 4kb boundary. the 16 bits contained in the i/o base upper 16 bits register at configuration offset 30h define ad[31:16] of the i/o base address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o base address is initialized to 0000 0000h. the i/o limit register consists of an 8-bit field at configuration offset 1dh and a 16-bit field at offset 32h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o limit address. the bottom 4 bits read only as 1h to indicate that 32-bit i/o addressing is supported. bits [11:0] of the limit address are assumed to be fffh, which naturally aligns the limit address to the top of a 4kb i/o address block. the 16 bits contained in the i/o limit upper 16 bits register at configuration offset 32h define ad[31:16] of the i/o limit address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o limit address is reset to 0000 0fffh. note: the initial states of the i/o base and i/o limit address registers define an i/o range of 0000 0000h to 0000 0fffh, which is the bottom 4kb of i/o space. write these registers with their appropriate values before setting either the i/o enable bit or the master enable bit in the command register in configuration space. 5.2.2 isa mode pi7c7100 supports isa mode by providing an isa enable bit in the bridge control register in configuration space. isa mode modifies the response of pi7c7100 inside the i/o address range in order to support mapping of i/o space in the presence of an isa bus in the system. this bit only affects the response of pi7c7100 when the transaction falls inside the address range defined by the i/o base and limit address registers, and only when this address also falls inside the first 64kb of i/o space (address bits [31:16] are 0000h). when the isa enable bit is set, pi7c7100 does not forward downstream any i/o transactions addressing the top 768 bytes of each aligned 1kb block. only those transactions addressing the bottom 256 bytes of an aligned 1kb block inside the base and limit i/o address range are forwarded downstream. transactions above the 64kb i/o address boundary are forwarded as defined by the address range defined by the i/o base and limit registers. accordingly, if the isa enable bit is set, pi7c7100 forwards upstream those i/o transactions addressing the top 768 bytes of each aligned 1kb block within the first 64kb of i/o space. the master enable bit in the command configuration register must also be set to enable upstream forwarding. all other i/o transactions initiated on the secondary bus are forwarded upstream only if they fall outside the i/o address range. when the isa enable bit is set, devices downstream of pi7c7100 can have i/o space mapped into the first 256 bytes of each 1kb chunk below the 64kb boundary, or anywhere in i/o space above the 64kb boundary. 5.3 memory address decoding pi7c7100 has three mechanisms for defining memory address ranges for forwarding of memory transactions: ? memory-mapped i/o base and limit address registers ? prefetchable memory base and limit address registers ? vga mode this section describes the first two mechanisms. section 5.4.1 describes vga mode. to enable downstream forwarding of memory transactions, the memory enable bit must be set in the command register in configuration space. to enable upstream forwarding of memory transactions, the master-enable bit must be set in the command register. the master-enable bit also allows upstream forwarding of i/o transactions if it is set.
30 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information caution if any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. configure the memory-mapped i/ o base and limit address registers, prefetchable memory base and limit address registers, and vga mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle. 5.3.1 memory-mapped i/o base and limit address registers memory-mapped i/o is also referred to as non-prefetchable memory. memory addresses that cannot automatically be pre- fetched but that can be conditionally pre-fetched based on command type should be mapped into this space. read transactions to non-prefetchable space may exhibit side effects; this space may have non-memory-like behavior. pi7c7100 pre-fetches in this space only if the memory read line or memory read multiple commands are used; transactions using the memory read command are limited to a single data transfer. the memory-mapped i/o base address and memory-mapped i/o limit address registers define an address range that pi7c7100 uses to determine when to forward memory commands. pi7c7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the memory-mapped i/o address range. pi7c7100 ignores memory transactions initiated on the secondary interface that fall into this address range. any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstream by the vga mechanism). the memory-mapped i/o range supports 32-bit addressing only. the pci-to-pci bridge architecture specification does not provide for 64-bit addressing in the memory-mapped i/o space. the memory-mapped i/o address range has a granularity and alignment of 1mb. the maximum memory-mapped i/o address range is 4gb. the memory-mapped i/o address range is defined by a 16-bit memory-mapped i/o base address register at configuration offset 20h and by a 16-bit memory-mapped i/o limit address register at offset 22h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the low 4 bits are hardwired to 0. the lowest 20 bits of the memory- mapped i/o base address are assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the lowest 20 bits of the memory-mapped i/o limit address are assumed to be f ffffh, which results in an alignment to the top of a 1mb block. note: the initial state of the memory-mapped i/o base address register is 0000 0000h. the initial state of the memory- mapped i/o limit address register is 000f ffffh. note that the initial states of these registers define a memory-mapped i/o range at the bottom 1mb block of memory. write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. to turn off the memory-mapped i/o address range, write the memory-mapped i/o base address register with a value greater than that of the memory-mapped i/o limit address register. 5.3.2 prefetchable memory base and limit address registers locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. this means that extra reads to a prefetchable memory location must have no side effects. pi7c7100 pre-fetches for all types of memory read commands in this address space. the prefetchable memory base address and prefetchable memory limit address registers define an address range that pi7c7100 uses to determine when to forward memory commands. pi7c7100 forwards a memory transaction from the primary to the secondary interface if the transaction address falls within the prefetchable memory address range. pi7c7100 ignores memory transactions initiated on the secondary interface that fall into this address range. pi7c7100 does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped i/o range or are not forwarded by the vga mechanism). the prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. for address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. this upper
31 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 32-bit value of 0 is compared to the prefetchable memory base address upper 32 bits register and the prefetcha ble memory limit address upper 32 bits register. the prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. prefetchable memory address range has a granularity and alignment of 1mb. m aximum memory address range is 4gb when 32-bit addressing is being used. prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit address register at offset 26h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the lowest 4 bits are hardwired to 1h. the lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the low est 20 bits of the prefetchable memory limit address are assumed to be fffffh, which results in an alignment to the top of a 1mb block. note: the initial state of the prefetchable memory base address register is 0000 0000h. the initial state of the prefetchable memory limit address register is 000f ffffh. note that the initial states of these registers define a prefetchable memory range at the bottom 1mb block of memory. write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. to turn off the prefetchable memory address range, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. the entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set greater than the lower limit register. otherwise, the upper 32-bit base must be greater than the upper 32-bit limit. 5.4 vga support pi7c7100 provides two modes for vga support: ? vga mode, supporting vga-compatible addressing ? vga snoop mode, supporting vga palette forwarding 5.4.1 vga mode when a vga-compatible device exists downstream from pi7c7100, set the vga mode bit in the bridge control register in configuration space to enable vga mode. when pi7c7100 is operating in vga mode, it forwards downstream those transactions addressing the vga frame buffer memory and vga i/o registers, regardless of the values of the base and limit address registers. pi7c7100 ignores transactions initiated on the secondary interface addressing these locations. the vga frame buffer consists of the following memory address range: 000a 0000hC000b ffffh read transactions to frame buffer memory are treated as non-prefetchable. pi7c7100 requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. the vga i/o addresses are in the range of 3b0hC3bbh and 3c0hC3dfh i/o. these i/o addresses are aliases every 1kb throughout the first 64kb of i/o space. this means that address bits <15:10> are not decoded and can be any value, while address bits [31:16] must be all 0s. vga bios addresses starting at c0000h are not decoded in vga mode. 5.4.2 vga snoop mode pi7c7100 provides vga snoop mode, allowing for vga palette write transactions to be forwarded downstream. this mode is used when a graphics device downstream from pi7c7100 needs to snoop or respond to vga palette write transactions. to enable the mode, set the vga snoop bit in the command register in configuration space. note that pi7c7100 claims vga palette write transactions by asserting devsel# in vga snoop mode. when vga snoop bit is set, pi7c7100 forwards downstream transactions within the 3c6h, 3c8h and 3c9h i/o addresses space. note that these addresses are also forwarded as part of the vga compatibility mode previously described. again, address bits <15:10> are not decoded, while address bits <31:16> must be equal to 0, which means that these addresses are aliases every 1kb throughout the first 64kb of i/o space. note: if both the vga mode bit and the vga snoop bit are set, pi7c7100 behaves in the same way as if only the vga mode bit were set.
32 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 6. transaction ordering to maintain data coherency and consistency, pi7c7100 complies with the ordering rules set forth in the pci local bus specification, revision 2.1, for transactions crossing the bridge. this chapter describes the ordering rules that control transaction forwarding across pi7c7100. 6.1 transactions governed by ordering rules ordering relationships are established for the following classes of transactions crossing pi7c7100: ? posted write transactions, comprised of memory write and memory write and invalidate transactions. posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. ? delayed write request transactions, comprised of i/o write and configuration write transactions. delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. a delayed write transaction must complete on the target bus before it completes on the initiator bus. ? delayed write completion transactions, comprised of i/o write and configuration write transactions. delayed write completion transactions complete on the target bus, and the target response is queued in the buffers. a delayed write completion transaction proceeds in the direction opposite that of the original delayed write request; that is, a delayed write completion transaction proceeds from the target bus to the initiator bus. ? delayed read request transactions, comprised of all memory read, i/o read, and configuration read transactions. delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. ? delayed read completion transactions, comprised of all memory read, i/o read, & configuration read transactions. delayed read completion transactions complete on the target bus, and the read data is queued in the read data buffers. a delayed read completion transaction proceeds in the direction opposite that of the original delayed read request; that is, a delayed read completion transaction proceeds from the target bus to the initiator bus. pi7c7100 does not combine or merge write transactions: ? pi7c7100 does not combine separate write transactions into a single write transactionthis optimization is best implemented in the originating master. ? pi7c7100 does not merge bytes on separate masked write transactions to the same dword addressthis optimization is also best implemented in the originating master. ? pi7c7100 does not collapse sequential write transactions to the same address into a single write transactionthe pci local bus specification does not permit this combining of transactions. 6.2 general ordering guidelines independent transactions on primary and secondary buses have a relationship only when those transactions cross pi7c7100. the following general ordering guidelines govern transactions crossing pi7c7100: ? the ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. ? requests terminated with target retry can be accepted and completed in any order with respect to other transac- tions that have been terminated with target retry. if the order of completion of delayed requests is important, the initiator should not start a second delayed transaction until the first one has been completed. if more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests, using some fairness algorithm. repeating a delayed trans action cannot be contingent on completion of another delayed transaction. otherwise, a deadlock can occur.
33 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information s s a pe t i r w d e t s o p d a e r d e y a l e d t s e u q e r e t i r w d e y a l e d t s e u q e r d a e r d e y a l e d n o i t e l p m o c e t i r w d e y a l e d n o i t e l p m o c e t i r w d e t s o pn 1 y 5 y 5 y 5 y 5 t s e u q e r d a e r d e y a l e dn 2 nn y y t s e u q e r e t i r w d e y a l e dn 4 nn y y n o i t e l p m o c d a e r d e y a l e dn 3 yy n n n o i t e l p m o c e t i r w d e y a l e dyyynn note: the superscript accompanying some of the table entries refers to any applicable ordering rule listed in this section. many entries are not governed by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. the entries without superscripts reflect the pi7c7100s implementation choices. the following ordering rules describe the transaction relationships. each ordering rule is followed by an explanation, and the ordering rules are referred to by number in table 6C1. these ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing pi7c7100 in the same direction. note that delayed completion transactions cross pi7c7100 in the direction opposite that of the corresponding delayed requests. 1. posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. the subsequent posted write transaction can be setting a flag that covers the data in the first posted write transaction; if the second transaction were to complete before the first transaction, a device checking the flag could subsequently consume stale data. 2. a delayed read request traveling in the same direction as a previously queued posted write transaction must push the posted write data ahead of it. the posted write transaction must complete on the target bus before the delayed read request can be attempted on the target bus. the read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. a delayed read completion must pull ahead of previously queued posted write data traveling in the same direction. in this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of pi7c7100 as the target of the write transaction. the posted write transaction must complete to the target before the read data is returned to the initiator. the read transaction can be a reading to a status register of the initiator of the posted write data and therefore should not complete until the write transaction is complete. 4. delayed write requests cannot pass previously queued posted write data. for posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. if the delayed write request were to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. 6.3 ordering rules table 6C1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. table 6-1. summary of transaction ordering ? write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. pi7c7100 can accept posted write transactions on both interfaces at the same time, as well as initiate posted write transactions on both interfaces at the same time. ? the acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transaction as a master. this is true for pi7c7100 and must also be true for other bus agents. otherwise, a deadlock can occur. ? pi7c7100 accepts posted write transactions, regardless of the state of completion of any delayed transactions being forwarded across pi7c7100.
34 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 5. posted write transactions must be given opportunities to pass delayed read and write requests and completions. otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. a fairness algorithm is used to arbitrate between the posted write queue and the delayed transaction queue. 6.4 data synchronization data synchronization refers to the relationship between interrupt signaling and data delivery. the pci local bus specification, revision 2.1, provides the following alternative methods for synchronizing data and interrupts: ? the device signaling the interrupt performs a read of the data just written (software). ? the device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). ? system hardware guarantees that write buffers are flushed before interrupts are forwarded. pi7c7100 does not have a hardware mechanism to guarantee data synchronization for posted write transactions. therefore, all posted write transactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers.
35 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 7. error handling pi7c7100 checks, forwards, and generates parity on both the primary and secondary interfaces. to maintain transparency, pi7c7100 always tries to forward the existing parity condition on one bus to the other bus, along with address and data. pi7c100 always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. to support error reporting on the pci bus, pi7c7100 implements the following: ? perr# and serr# signals on both the primary and secondary interfaces ? primary status and secondary status registers ? the device-specific p_serr# event disable register this chapter provides detailed information about how pi7c7100 handles errors. it also describes error status reporting and error operation disabling. 7.1 address parity errors pi7c7100 checks address parity for all transactions on both buses, for all address and all bus commands. when pi7c7100 detects an address parity error on the primary interface, the following events occur: ? if the parity error response bit is set in the command register, pi7c7100 does not claim the transaction with p_devsel#; this may allow the transaction to terminate in a master abort. if parity error response bit is not set, pi7c7100 proceeds normally and accepts the transaction if it is directed to or across pi7c7100. ? pi7c7100 sets the detected parity error bit in the status register. ? pi7c7100 a sserts p_serr# and sets signaled system error bit in the status register, if both the following condit ions are met: - the serr# enable bit is set in the command register. - the parity error response bit is set in the command register. when pi7c7100 detects an address parity error on the secondary interface, the following events occur: ? if the parity error response bit is set in the bridge control register, pi7c7100 does not claim the transaction with s1_devsel# or s2_devsel#; this may allow the transaction to terminate in a master abort. if parity error response bit is not set, pi7c7100 proceeds normally and accepts transaction if it is directed to or across pi7c7100. ? pi7c7100 sets the detected parity error bit in the secondary status register. ? pi7c7100 asserts p_serr# and sets signaled system error bit in status register, if both of the following conditions are met: - the serr# enable bit is set in the command register. - the parity error response bit is set in the bridge control register. 7.2 data parity errors when forwarding transactions, pi7c7100 attempts to pass the data parity condition from one interface to the other unchanged, whenever possible, to allow the master and target devices to handle the error condition. the following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across pi7c7100. 7.2.1 configuration write transactions to configuration space when pi7c7100 detects a data parity error during a type 0 configuration write transaction to pi7c7100 configuration space, the following events occur: ? if the parity error response bit is set in the command register, pi7c7100 asserts p_trdy# and writes the data to the configuration register. pi7c7100 also asserts p_perr#. if the parity error response bit is not set, pi7c7100 does not assert p_perr#. ? pi7c7100 sets the detected parity error bit in the status register, regardless of the state of the parity error response bit.
36 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 7.2.2 read transactions when pi7c7100 detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts perr#. for downstream transactions, when pi7c7100 detects a read data parity error on the secondary bus, the following events occur: ? pi7c7100 asserts s_perr# two cycles following the data transfer, if the secondary interface parity error re- sponse bit is set in the bridge control register. ? pi7c7100 sets the detected parity error bit in the secondary status register. ? pi7c7100 sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. ? pi7c7100 forwards the bad parity with the data back to the initiator on the primary bus. if the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator. ? pi7c7100 completes the transaction normally. for upstream transactions, when pi7c7100 detects a read data parity error on the primary bus, the following events occur: ? pi7c7100 asserts p_perr# two cycles following the data transfer, if the primary interface parity error response bit is set in the command register. ? pi7c7100 sets the detected parity error bit in the primary status register. ? pi7c7100 sets the data parity detected bit in the primary status register, if the primary interface parity-error- response bit is set in the command register. ? pi7c7100 forwards the bad parity with the data back to the initiator on the secondary bus. if the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with bad parity is not returned to the initiator. ? pi7c7100 completes the transaction normally. pi7c7100 returns to the initiator the data and parity that was received from the target. when the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts perr# two cycles after the data transfer occurs. it is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when pi7c7100 detects perr# asserted while returning read data to the initiator, pi7c7100 does not take any further action and completes the transaction normally. 7.2.3 delayed write transactions when pi7c7100 detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts perr#. for delayed write transactions, a parity error can occur at the following times: ? during the original delayed write request transaction ? when the initiator repeats the delayed write request transaction ? when pi7c7100 completes the delayed write transaction to the target when a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured and a target retry is returned to the initiator. when pi7c7100 detects a parity error on the write data for the initial delayed write request transaction, the following events occur: ? if the parity-error-response bit corresponding to the initiator bus is set, pi7c7100 asserts trdy# to the initiator and the transaction is not queued. if multiple data phases are requested, stop# is also asserted to cause a target disconnect. two cycles after the data transfer, pi7c7100 also asserts perr#. if the parity-error-response bit is not set, pi7c7100 returns a target retry. it queues the transaction as usual. pi7c7100 does not assert perr#. in this case, the initiator repeats the transaction. ? pi7c7100 sets the detected-parity-error bit in the status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit.
37 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information note: if parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiators re-attempts of the write transaction may not match the original queued delayed write information contained in the delayed transaction queue. in this case, a master timeout condition may occur, possibly resulting in a system error (p_serr# assertion). for downstream transactions, when pi7c7100 is delivering data to the target on the secondary bus and s_perr# is asserted by the target, the following events occur: ? pi7c7100 sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. ? pi7c7100 captures the parity error condition to forward it back to the initiator on the primary bus. similarly, for upstream transactions, when pi7c7100 is delivering data to the target on the primary bus and p_perr# is asserted by the target, the following events occur: ? pi7c7100 sets the primary interface data-parity-detected bit in the status register, if the primary parity-error- response bit is set in the command register. ? pi7c7100 captures the parity error condition to forward it back to the initiator on the secondary bus. a delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, data, and byte enable bits as the delayed write command that is at the head of the posted data queue. note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. two cases must be considered: ? when parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus ? when parity error is forwarded back from the target bus for downstream delayed write transactions, when the parity error is detected on the initiator bus and pi7c7100 has write status to return, the following events occur: ? pi7c7100 first asserts p_trdy# and then asserts p_perr# two cycles later, if the primary interface parity- error-response bit is set in the command register. ? pi7c7100 sets the primary interface parity-error-detected bit in the status register. ? because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and pi7c7100 has write status to return, the following events occur: ? pi7c7100 first asserts s1_trdy# or s2_trdy# and then asserts s_perr# two cycles later, if the secondary interface parity-error-response bit is set in the bridge control register (offset 3ch). ? pi7c7100 sets the secondary interface parity-error-detected bit in the secondary status register. ? because there was not an exact data and parity match, the write status is not returned and the transaction remains in the queue. for downstream transactions, where the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ? pi7c7100 asserts p_perr# two cycles after the data transfer, if the following are both true: - the parity-error-response bit is set in the command register of the primary interface. - the parity-error-response bit is set in the bridge control register of the secondary interface. ? pi7c7100 completes the transaction normally.
38 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information for upstream transactions, when the parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ? pi7c7100 asserts s_perr# two cycles after the data transfer, if the following are both true: - the parity error response bit is set in the command register of the primary interface. - the parity error response bit is set in the bridge control register of the secondary interface. ? pi7c7100 completes the transaction normally. 7.2.4 posted write transactions during downstream posted write transactions, when pi7c7100 responds as a target, it detects a data parity error on the initiator (primary) bus, the following events occur: ? pi7c7100 asserts p_perr# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. ? pi7c7100 sets the parity error detected bit in the status register of the primary interface. ? pi7c7100 captures and forwards the bad parity condition to the secondary bus. ? pi7c7100 completes the transaction normally. similarly, during upstream posted write transactions, when pi7c7100 responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: ? pi7c7100 asserts s_perr# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. ? pi7c7100 sets the parity error detected bit in the status register of the secondary interface. ? pi7c7100 captures and forwards the bad parity condition to the primary bus. ? pi7c7100 completes the transaction normally. during downstream write transactions, when a data parity error is reported on the target (secondary) bus by the targets assertion of s_perr#, the following events occur: ? pi7c7100 sets the data parity detected bit in the status register of secondary interface, if the parity error response bit is set in the bridge control register of the secondary interface. ? pi7c7100 asserts p_serr# and sets the signaled system error bit in the status register, if all the following conditions are met: - the serr# enable bit is set in the command register. - the posted write parity error bit of p_serr# event disable register is not set. - the parity error response bit is set in the bridge control register of the secondary interface. - the parity error response bit is set in the command register of the primary interface. - pi7c7100 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the primary bus to the secondary bus. during upstream write transactions, when a data parity error is reported on the target (primary) bus by the targets assertion of p_perr#, the following events occur: ? pi7c7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the command register of the primary interface. ? pi7c7100 asserts p_serr# and sets the signaled system error bit in the status register, if all the following conditions are met: - the serr# enable bit is set in the command register. - the parity error response bit is set in the bridge control register of the secondary interface. - the parity error response bit is set in the command register of the primary interface. - pi7c7100 has not detected the parity error on the secondary (initiator) bus which the parity error is not forwarded from the secondary bus to the primary bus. assertion of p_serr# is used to signal the parity error condition when the initiator does not know that the error occurred.
39 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information d e t c e t e d y r a m i r p t i b r o r r e y t i r a p n o i t c a s n a r t e p y t n o i t c e r i d r o r r e e r e h w s u b d e t c e t e d s a w y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p 0d a e rm a e r t s n w o dy r a m i r px / x 1 0d a e rm a e r t s n w o dy r a d n o c e sx / x 1d a e rm a e r t s p uy r a m i r px / x 0d a e rm a e r t s p uy r a d n o c e sx / x 1e t i r w d e t s o pm a e r t s n w o dy r a m i r px / x 0e t i r w d e t s o pm a e r t s n w o dy r a d n o c e sx / x 0e t i r w d e t s o pm a e r t s p uy r a m i r px / x 0e t i r w d e t s o pm a e r t s p uy r a d n o c e sx / x 1e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / x 0e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e sx / x 0e t i r w d e y a l e dm a e r t s p uy r a m i r px / x 0e t i r w d e y a l e dm a e r t s p uy r a d n o c e sx / x 1 x =dont care table 7C1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. this bit is set when pi7c7100 detects a parity error on the primary interface. table 7C1 setting the primary interface detected parity error bit 1 x =don t care because the data has already been delivered with no errors, there is no other way to signal this information back to the initiator. if the parity error has forwarded from the initiating bus to the target bus, p_serr# will not be asserted. 7.3 data parity error reporting summary in the previous sections, the responses of pi7c7100 to data parity errors are presented according to the type of transaction in progress. this section organizes the responses of pi7c7100 to data parity errors according to the status bits that pi7c7100 sets and the signals that it asserts.
40 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 1 x =dont care table 7C3 shows setting data parity detected bit in the primary interfaces status register. this bit is set under the followin g conditions: ? pi7c7100 must be a master on the primary bus. ? the parity error response bit in the command register, corresponding to the primary interface, must be set. ? the p_perr# signal is detected asserted or a parity error is detected on the primary bus. a t a d y r a m i r p t i b y t i r a p n o i t c a s n a r t e p y t n o i t c e r i d s a w r o r r e e r e h w s u b d e t c e t e d y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p 0d a e rm a e r t s n w o dy r a m i r px / x 1 0d a e rm a e r t s n w o dy r a d n o c e sx / x 1d a e rm a e r t s p uy r a m i r px / 1 0d a e rm a e r t s p uy r a d n o c e sx / x 0e t i r w d e t s o pm a e r t s n w o dy r a m i r px / x 0e t i r w d e t s o pm a e r t s n w o dy r a d n o c e sx / x 1e t i r w d e t s o pm a e r t s p uy r a m i r px / 1 0e t i r w d e t s o pm a e r t s p uy r a d n o c e sx / x 0e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / x 0e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e sx / x 1e t i r w d e y a l e dm a e r t s p uy r a m i r px / 1 0e t i r w d e y a l e dm a e r t s p uy r a d n o c e sx / x table 7C3. setting primary interface data parity detected bit d e t c e t e d y r a d n o c e s t i b r o r r e y t i r a p n o i t c a s n a r t e p y t n o i t c e r i d r o r r e e r e h w s u b d e t c e t e d s a w y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p 0d a e rm a e r t s n w o dy r a m i r px / x 1 1d a e rm a e r t s n w o dy r a d n o c e sx / x 0d a e rm a e r t s p uy r a m i r px / x 0d a e rm a e r t s p uy r a d n o c e sx / x 0e t i r w d e t s o pm a e r t s n w o dy r a m i r px / x 0e t i r w d e t s o pm a e r t s n w o dy r a d n o c e sx / x 0e t i r w d e t s o pm a e r t s p uy r a m i r px / x 1e t i r w d e t s o pm a e r t s p uy r a d n o c e sx / x 0e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / x 0e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e sx / x 0e t i r w d e y a l e dm a e r t s p uy r a m i r px / x 1e t i r w d e y a l e dm a e r t s p uy r a d n o c e sx / x table 7C2. setting secondary interface detected parity error bit table 7C2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. this bit is set when pi7c7100 detects a parity error on the secondary interface.
41 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information a t a d y r a d n o c e s t i b d e t c e t e d y t i r a p n o i t c a s n a r t e p y t n o i t c e r i d s a w r o r r e e r e h w s u b d e t c e t e d y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p 0d a e rm a e r t s n w o dy r a m i r px / x 1 1d a e rm a e r t s n w o dy r a d n o c e s1 / x 0d a e rm a e r t s p uy r a m i r px / x 0d a e rm a e r t s p uy r a d n o c e sx / x 0e t i r w d e t s o pm a e r t s n w o dy r a m i r px / x 1e t i r w d e t s o pm a e r t s n w o dy r a d n o c e s1 / x 0e t i r w d e t s o pm a e r t s p uy r a m i r px / x 0e t i r w d e t s o pm a e r t s p uy r a d n o c e sx / x 0e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / x 1e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e s1 / x 0e t i r w d e y a l e dm a e r t s p uy r a m i r px / x 0e t i r w d e y a l e dm a e r t s p uy r a d n o c e sx / x 1 x =dont care table 7C4. setting secondary interface data parity detected bit table 7C4 shows setting the data parity detected bit in the status register of secondary interface. this bit is set under the following conditions: ? the pi7c7100 must be a master on the secondary bus. ? the parity error response bit must be set in the bridge control register of secondary interface. ? the s_perr# signal is detected asserted or a parity error is detected on the secondary bus.
42 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information table 7C5. assertion of p_perr# # r r e p _ p n o i t c a s n a r t e p y t n o i t c e r i d s a w r o r r e e r e h w s u b d e t c e t e d y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p ) d e t r e s s a - e d ( 1d a e rm a e r t s n w o dy r a m i r px / x 1 1d a e rm a e r t s n w o dy r a d n o c e sx / x ) d e t r e s s a ( 0d a e rm a e r t s p uy r a m i r px / 1 1d a e rm a e r t s p uy r a d n o c e sx / x 0e t i r w d e t s o pm a e r t s n w o dy r a m i r px / 1 1e t i r w d e t s o pm a e r t s n w o dy r a d n o c e sx / x 1e t i r w d e t s o pm a e r t s p uy r a m i r px / x 1e t i r w d e t s o pm a e r t s p uy r a d n o c e sx / x 0e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / 1 0 2 e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e s1 / 1 1e t i r w d e y a l e dm a e r t s p uy r a m i r px / x 1e t i r w d e y a l e dm a e r t s p uy r a d n o c e sx / x 1 x =dont care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. table 7C5 shows assertion of p_perr#. this signal is set under the following conditions: ? pi7c7100 is either the target of a write transaction or the initiator of a read transaction on the primary bus. ? the parity-error-response bit must be set in the command register of primary interface. ? pi7c7100 detects a data parity error on the primary bus or detects s_perr# asserted during the completion phase of a downstream delayed write transaction on the target (secondary) bus.
43 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information table 7C6. assertion of s_perr# # r r e p _ s n o i t c a s n a r t e p y t n o i t c e r i d r o r r e e r e h w s u b d e t c e t e d s a w y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p ) d e t r e s s a - e d ( 1d a e rm a e r t s n w o dy r a m i r px / x 1 ) d e t r e s s a ( 0d a e rm a e r t s n w o dy r a d n o c e s1 / x 1d a e rm a e r t s p uy r a m i r px / x 1d a e rm a e r t s p uy r a d n o c e sx / x 1e t i r w d e t s o pm a e r t s n w o dy r a m i r px / x 1e t i r w d e t s o pm a e r t s n w o dy r a d n o c e sx / x 1e t i r w d e t s o pm a e r t s p uy r a m i r px / x 0e t i r w d e t s o pm a e r t s p uy r a d n o c e s1 / x 1e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / x 1e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e sx / x 0 2 e t i r w d e y a l e dm a e r t s p uy r a m i r p1 / 1 0e t i r w d e y a l e dm a e r t s p uy r a d n o c e s1 / x 1 x =dont care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. table 7C6 shows assertion of s_perr# that is set under the following conditions: ? pi7c7100 is either the target of a write transaction or the initiator of a read transaction on the secondary bus. ? the parity error response bit must be set in the bridge control register of secondary interface. ? pi7c7100 detects a data parity error on the secondary bus or detects p_perr# asserted during the completion phase of an upstream delayed write transaction on the target (primary) bus.
44 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information table 7C7 shows assertion of p_serr#. this signal is set under the following conditions: ? pi7c7100 has detected p_perr# asserted on an upstream posted write transaction or s_perr# asserted on a downstream posted write transaction. ? pi7c7100 did not detect the parity error as a target of the posted write transaction. ? the parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. ? the serr# enable bit must be set in the command register. table 7C7. assertion of p_serr# for data parity errors # r r e s _ p n o i t c a s n a r t e p y t n o i t c e r i d s a w r o r r e e r e h w s u b d e t c e t e d y r a d n o c e s / y r a m i r p s t i b e s n o p s e r r o r r e y t i r a p ) d e t r e s s a - e d ( 1d a e rm a e r t s n w o dy r a m i r px / x 1 1d a e rm a e r t s n w o dy r a d n o c e sx / x 1d a e rm a e r t s p uy r a m i r px / x 1d a e rm a e r t s p uy r a d n o c e sx / x 1e t i r w d e t s o pm a e r t s n w o dy r a m i r px / x 0 2 ) d e t r e s s a (e t i r w d e t s o pm a e r t s n w o dy r a d n o c e s1 / 1 0 3 e t i r w d e t s o pm a e r t s p uy r a m i r p1 / 1 1e t i r w d e t s o pm a e r t s p uy r a d n o c e sx / x 1e t i r w d e y a l e dm a e r t s n w o dy r a m i r px / x 1e t i r w d e y a l e dm a e r t s n w o dy r a d n o c e sx / x 1e t i r w d e y a l e dm a e r t s p uy r a m i r px / x 1e t i r w d e y a l e dm a e r t s p uy r a d n o c e sx / x 1 x =dont care 2 the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 the parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
45 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 7.4 system error (serr#) reporting pi7c7100 uses the p_serr# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in section 7.2.3. whenever assertion of p_serr# is discussed in this document, it is assumed that the following conditions apply: ? for pi7c7100 to assert p_serr# for any reason, the serr# enable bit must be set in the command register. ? whenever pi7c7100 asserts p_serr#, pi7c7100 must also set the signaled system error bit in the status register. in compliance with the pci-to-pci bridge architecture specification, pi7c7100 asserts p_serr# when it detects the secondary serr# input, s_serr#, asserted and the serr# forward enable bit is set in the bridge control register. in addition, pi7c7100 also sets the received system error bit in the secondary status register. pi7c7100 also conditionally asserts p_serr# for any of the following reasons: ? target abort detected during posted write transaction ? master abort detected during posted write transaction ? posted write data discarded after 2 24 (default) attempts to deliver (2 24 target retries received) ? parity error reported on target bus during posted write transaction (see previous section) ? delayed write data discarded after 2 24 (default) attempts to deliver (2 24 target retries received) ? delayed read data cannot be transferred from target after 2 24 (default) attempts (2 24 target retries received) ? master timeout on delayed transaction the device-specific p_serr# status register reports the reason for the assertion of p_serr#. most of these events have additional device-specific disable bits in the p_serr# event disable register that make it possible to mask out p_serr# assertion for specific events. the master timeout condition has a serr# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit.
46 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 8. exclusive access this chapter describes the use of the lock# signal to implement exclusive access to a target for transactions that cross pi7c7100. 8.1 concurrent locks the primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses pi7c7100. a primary master can lock a primary target without affecting the status of the lock on the secondary bus, and vice versa. this means that a primary master can lock a primary target at the same time that a secondary master locks a secondary target. 8.2 acquiring exclusive access across pi7c7100 for any pci bus, before acquiring access to the lock# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: ? the pci bus must be idle. ? the lock# signal must be de-asserted. the initiator leaves the lock# signal de-asserted during the address phase and asserts lock# one clock cycle later. once a data transfer is completed from the target, the target lock has been achieved. locked transactions can cross pi7c7100 in the downstream and upstream directions, from the primary bus to the secondary bus and vice versa. when the target resides on another pci bus, the master must acquire not only the lock on its own pci bus but also the lock on every bus between its bus and the targets bus. when pi7c7100 detects on the primary bus, an initial locked transaction intended for a target on the secondary bus, pi7c7100 samples the address, transaction type, byte enable bits, and parity, as described in section 4.6.4. it also samples the lock signal. if there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forward. because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is not yet established. the first locked transaction must be a read transaction. subsequent locked transactions can be read or write transactions. posted memory write transactions that are a part of the locked transaction sequence are still posted. memory read transactions that are a part of the locked transaction sequence are not pre-fetched. when the locked delayed read request is queued, pi7c7100 does not queue any more transactions until the locked sequence is finished. pi7c7100 signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of pi7c7100. pi7c7100 allows any transactions queued before the locked transaction to complete before initiating the locked transaction. when the locked delayed read request transaction moves to the head of the delayed transaction queue, pi7c7100 initiates the transaction as a locked read transaction by de-asserting lock# on the target bus during the first address phase, and by asserting lock# one cycle later. if lock# is already asserted (used by another initiator), pi7c7100 waits to request access to the secondary bus until lock# is de-asserted when the target bus is idle. note that the existing lock on the target bus could not have crossed pi7c7100. otherwise, the pending queued locked transaction would not have been queued. when pi7c7100 is able to complete a data transfer with the locked read transaction, the lock is established on the secondary bus. when the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, pi7c7100 transfers the read data back to the initiator, and the lock is then also established on the primary bus. for pi7c7100 to recognize and respond to the initiator, the initiators subsequent attempts of the read transaction must use the locked transaction sequence (de-assert lock# during address phase, and assert lock# one cycle later). if the lock# sequence is not used in subsequent attempts, a master timeout condition may result. when a master timeout condition occurs, serr# is conditionally asserted (see section 7.4), the read data and queued read transaction are discarded, and the lock# signal is de-asserted on the target bus.
47 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by pi7c7100 are driven as locked transactions on the target bus. when pi7c7100 receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the initiator, and no locks are established on either the target or the initiator bus. pi7c7100 resumes forwarding unlocked transactions in both directions. 8.3 ending exclusive access after the lock has been acquired on both initiator and target buses, pi7c7100 must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. the only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. on subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. an established target lock is maintained until the initiator relinquishes the lock. pi7c7100 does not know whether the current transaction is the last one in a sequence of locked transactions until the initiator de-asserts the lock# signal at end of the transaction. when the last locked transaction is a delayed transaction, pi7c7100 has already completed the transaction on the secondary bus. in this example, as soon as pi7c7100 detects that the initiator has relinquished the lock# signal by sampling it in the de-asserted state while frame# is de-asserted, pi7c7100 de-asserts the lock# signal on the target bus as soon as possible. because of this behavior, lock# may not be de-asserted until several cycles after the last locked transaction has been completed on the target bus. as soon as pi7c7100 has de-asserted lock# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. when the last locked transaction is a posted write transaction, pi7c7100 de-asserts lock# on the target bus at the end of the transaction because the lock was relinquished at the end of the write transaction on the initiator bus. when pi7c7100 receives a target abort or a master abort in response to a locked delayed transaction, pi7c7100 returns a target abort or a master abort when the initiator repeats the locked transaction. the initiator must then de-assert lock# at the end of the transaction. pi7c7100 sets the appropriate status bits, flagging the abnormal target termination condition (see section 4.8). normal forwarding of unlocked posted and delayed transactions is resumed. when pi7c7100 receives a target abort or a master abort in response to a locked posted write transaction, pi7c7100 cannot pass back that status to the initiator. pi7c7100 asserts serr# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the serr# enable bit is set in the command register. signal serr# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see section 7.4).
48 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 9. pci bus arbitration pi7c7100 must arbitrate for use of the primary bus when forwarding upstream transactions. also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. the arbiter for the primary bus resides external to pi7c7100, typically on the motherboard. for the secondary pci bus, pi7c7100 implements an internal arbiter. this arbiter can be disabled, and an external arbiter can be used instead. this chapter describes primary and secondary bus arbitration. 9.1 primary pci bus arbitration pi7c7100 implements a request output pin, p_req#, and a grant input pin, p_gnt#, for primary pci bus arbitration. pi7c7100 asserts p_req# when forwarding transactions upstream; that is, it acts as initiator on the primary pci bus. as long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed transaction requests, pi7c7100 keeps p_req# asserted. however, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by pi7c7100 on the primary pci bus, pi7c7100 de-asserts p_req# for two pci clock cycles. for all cycles through the bridge, p_req# is not asserted until the transaction request has been completely queued. when p_gnt# is asserted low by the primary bus arbiter after pi7c7100 has asserted p_req#, pi7c7100 initiates a transaction on the primary bus during the next pci clock cycle. when p_gnt# is asserted to pi7c7100 when p_req# is not asserted, pi7c7100 parks p_ad, p_cbe, and p_par by driving them to valid logic levels. when the primary bus is parked at pi7c7100 and pi7c7100 has a transaction to initiate on the primary bus, pi7c7100 starts the transaction if p_gnt# was asserted during the previous cycle. 9.2 secondary pci bus arbitration pi7c7100 implements an internal secondary pci bus arbiter. this arbiter supports two sets of eight external masters in addition to pi7c7100. the internal arbiter can be disabled, and an external arbiter can be used instead for secondary bus arbitration. 9.2.1 secondary bus arbitration using the internal arbiter to use the internal arbiter, the secondary bus arbiter enable pin, s_cfn#, must be tied low. pi7c7100 has two sets of eight secondary bus request input pins, s1_req#[7:0], s2_req#[7:0], and two sets of eight secondary bus output grant pins, s1_gnt#[7:0], s2_gnt#[7:0], to support external secondary bus masters. the secondary bus request and grant signals are connected internally to the arbiter and are not brought out to external pins when s_cfn# is high. the secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 8 requests/ grants. each set of masters can be assigned to a high priority group and a low priority group. the low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. priority rotates evenly among the low priority group. therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. figure 9C1 shows an example of an internal arbiter where four masters, including pi7c7100, are in the high priority group, and five masters are in the low priority group. using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion b m0 m1 m2 lpg m3 m4 m5 m6 m7 figure 9-1. secondary arbiter example (high priority members are given in italics, low priority members, in boldface type): b, m0, m1 , m2 , m3 , b, m0, m1, m2 , m4 , b, m0, m1, m2 , m5 , b, m0, m1, m2 , m6 , b, m0, m1, m2 , m7 and so on.
49 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information each bus master, including pi7c7100, can be configured to be in either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter-control register. the arbiter-control register is located at offset 40 h. each master has a corresponding bit. if the bit is set to 1, the master is assigned to the high priority group. if the bit is set to 0, the master is assigned to the low priority group. if all the masters are assigned to one group, the algorithm default s to a straight rotating priority among all the masters. after reset, all external masters are assigned to the low priority group , and pi7c7100 is assigned to the high priority group. pi7c7100 receives highest priority on the target bus every other transaction, and priority rotates evenly among the other masters. priorities are re-evaluated every time s1_frame# or s2_frame# is asserted at the start of each new transaction on the secondary pci bus. from this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. if a grant for a particular request is asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next pci clock cycle. when priorities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. the master that initiated the last transaction now has the lowest priority in its group. if pi7c7100 detects that an initiator has failed to assert s1_frame# or s2_frame# after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant. that master does not receive any more grants until it de-asserts its request for at least one pci clock cycle. to prevent bus contention, if the secondary pci bus is idle, the arbiter never asserts one grant signal in the same pci cycle in which it de-asserts another. it de-asserts one grant and asserts the next grant, no earlier than one pci clock cycle later. if the secondary pci bus is busy, that is, either s1_frame# (s2_frame#) or s1_irdy# (s2_irdy#) is asserted, the arbiter can de-assert one grant and assert another grant during the same pci clock cycle. 9.2.2 secondary bus arbitration using an external arbiter the internal arbiter is disabled when the secondary bus central function control pin, s_cfn#, is tied high. an external arbiter must then be used. when s_cfn# is tied high, pi7c7100 reconfigures four pins (two per port) to be external request and grant pins. the s1_gnt#[0] and s2_gnt#[0] pins are reconfigured to be the external request pins because they are output. the s1_req#[0] and s2_req#[0] pins are reconfigured to be the external grant pins because they are input. when an external arbiter is used, pi7c7100 uses the s1_gnt#[0] or s2_gnt#[0] pin to request the secondary bus. when the reconfigured s1_req#[0] or s2_req#[0] pin is asserted low after pi7c7100 has asserted s1_gnt#[0] or s2_gnt#[0]. pi7c7100 initiates a transaction on the secondary bus one cycle later. if grant is asserted and pi7c7100 has not asserted the request, pi7c7100 parks ad, cbe and par pins by driving them to valid logic levels. the unused secondary bus grant outputs, s1_gnt#[7:1] and s2_gnt#[7:1] are driven high. the unused secondary bus request inputs, s1_req#[7:1] and s2_req#[7:1], should be pulled high. 9.2.3 bus parking bus parking refers to driving the ad[31:0], cbe[3:0]#, and par lines to a known value while the bus is idle. in general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. a device parks the bus when the bus is idle, its bus grant is asserted, and the devices request is not asserted. the ad and cbe signals should be driven first, with the par signal driven one cycle later. pi7c7100 parks the primary bus only when p_gnt# is asserted, p_req# is de-asserted, and the primary pci bus is idle. when p_gnt# is de-asserted, pi7c7100 3-states the p_ad, p_cbe, and p_par signals on the next pci clock cycle. if pi7c7100 is parking the primary pci bus and wants to initiate a transaction on that bus, then pi7c7100 can start the transaction on the next pci clock cycle by asserting p_frame# if p_gnt# is still asserted. if the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the pci bus. that is, pi7c7100 keeps the secondary bus grant asserted to a particular master until a new secondary bus request comes along. after reset, pi7c7100 parks the secondary bus at itself until transactions start occurring on the secondary bus. if the internal arbiter is disabled, pi7c7100 parks the secondary bus only when the reconfigured grant signal, s_req#<0>, is asserted and the secondary bus is idle.
50 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 10. clocks this chapter provides information about the clocks. 10.1 primary clock inputs pi7c7100 implements a primary clock input for the pci interface. the primary interface is synchronized to the primary clock input, p_clk, and the secondary interface is synchronized to the secondary clock. the secondary clock is derived internally from the primary clock, p_clk, through an internal pll. pi7c7100 operates at a maximum frequency of 33 mhz. 10.2 secondary clock outputs pi7c7100 has 16 secondary clock outputs, s_clkout[15:0] that can be used as clock inputs for up to sixteen external secondary bus devices. the s_clkout[15:0] outputs are derived from p_clk. the secondary clock edges are delayed from p_clk edges by a minimum of 0ns. this is the rule for using secondary clocks: ? each secondary clock output is limited to no more than one load.
51 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 11. reset this chapter describes the primary interface, secondary interface, and chip reset mechanisms. 11.1 primary interface reset pi7c7100 has a reset input, p_reset#. when p_reset# is asserted, the following events occur: ? pi7c7100 immediately 3-states all primary and secondary pci interface signals. ? pi7c7100 performs a chip reset. ? registers that have default values are reset. p_reset# asserting and de-asserting edges can be asynchronous to p_clk and s_clk. 11.2 secondary interface reset pi7c7100 is responsible for driving the secondary bus reset signals, s1_reset# and s2_reset#. pi7c7100 asserts s1_reset# or s2_reset# when any of the following conditions is met: ? signal p_reset# is asserted. signal s1_reset# or s2_reset# remains asserted as long as p_reset# is asserted and does not de-assert until p_reset# is de-asserted. ? the secondary reset bit in the bridge control register is set. signal s1_reset# or s2_reset# remains asserted until a configuration write operation clears the secondary reset bit. ? s1_reset# or s2_reset# pin is asserted. when s1_reset# or s2_reset# is asserted, the following events occur: pi7c7100 immediately 3-states all the secondary pci interface signals associated with the secondary s1 or s2 port. the s1_reset# or s2_reset# in asserting and de-asserting edges can be asynchronous to p_clk. ? the chip reset bit in the diagnostic control register is set. signal s1_reset# or s2_reset# remains asserted until a configuration write operation clears the secondary reset bit and the secondary clock serial mask has been shifted in. when s1_reset# or s2_reset# is asserted, all secondary pci interface control signals, including the secondary grant outputs, are immediately 3-stated. signals s1_ad, s1_cbe[3:0]#, s1_par (s2_ad, s2_cbe[3:0]#, s2_par) are driven low for the duration of s1_reset# (s2_reset#) assertion. all posted write and delayed transaction data buffers are reset. therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. when s1_reset# or s2_reset# is asserted by means of the secondary reset bit, pi7c7100 remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface. 11.3 chip reset the chip reset bit in the diagnostic control register can be used to reset pi7c7100 and the secondary buses. all registers, and chip state machines are reset and all signals are 3-stated when the chip reset is set. in addition, s1_reset# or s2_reset# is asserted, and the secondary reset bit is automatically set. signal s1_reset# or s2_reset# remains asserted until a configuration write operation clears the secondary reset bit. as soon as chip reset completes, within 20 pci clock cycles after completion of the configuration write operation that sets the chip reset bit, the chip reset bit automatically clears and the chip is ready for configuration. during chip reset, pi7c7100 is inaccessible.
52 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 12. supported commands the pci command set is given below for the primary and secondary interfaces. 12.1 primary interface # ] 0 : 3 [ e b c _ pd n a m m o cn o i t c a 0 0 0 0e g d e l w o n k c a t p u r r e t n i. e r o n g i 1 0 0 0e l c y c l a i c e p s. e r o n g i . m i a l c t o n o d 0 1 0 0d a e r o / i s s a p d n a m i a l c : e g n a r o / i h g u o r h t s s a p n i h t i w s i s s e r d d a f i . 1 . h g u o r h t d n a m i a l c : r e t s i g e r l a n r e t n i e g d i r b d e p p a m o / i o t s t n i o p s s e r d d a f i . 2 . h g u o r h t s s a p t o n o d , r e t s i g e r o t s s e c c a t i m r e p . s s e c c a l a n r e t n i r o f m i a l c t o n o d d n a h g u o r h t s s a p t o n o d , e s i w r e h t o . 3 1 1 0 0e t i r w o / i. d a e r o / i s a e m a s 0 0 1 0d e v r e s e r- - - - - 1 0 1 0d e v r e s e r- - - - - 0 1 1 0d a e r y r o m e m s s a p d n a m i a l c : e g n a r y r o m e m h g u o r h t s s a p n i h t i w s i s s e r d d a f i . 1 . h g u o r h t m i a l c : e g n a r o / i d e p p a m y r o m e m h g u o r h t s s a p n i h t i w s i s s e r d d a f i . 2 . h g u o r h t s s a p d n a m i a l c : r e t s i g e r l a n r e t n i e g d i r b d e p p a m y r o m e m o t s t n i o p s s e r d d a f i . 3 . h g u o r h t s s a p t o n o d , r e t s i g e r o t s s e c c a t i m r e p d n a . s s e c c a l a n r e t n i r o f m i a l c t o n o d d n a h g u o r h t s s a p t o n o d , e s i w r e h t o . 4 1 1 1 0e t i r w y r o m e md a e r y r o m e m s a e m a s 0 0 0 1d e v r e s e r- - - - - 1 0 0 1d e v r e s e r- - - - - 0 1 0 1n o i t a r u g i f n o c d a e r i . : d a e r n o i t a r u g i f n o c 0 e p y t d n a e d o c e d n o i t c n u f m r o f r e p , d e t r e s s a s i e n i l l e s d i s ' e g d i r b e h t f i , d e m i a l c f i . e r o n g i , e s i w r e h t o , d e t n e m e l p m i s i n o i t c n u f t e g r a t f i m i a l c s s a p t o n o d . s r e t s i g e r n o i t a r u g i f n o c s ' n o i t c n u f t e g r a t o t s s e c c a t i m r e p . s e c n a t s m u c r i c y n a r e d n u h g u o r h t : d a e r n o i t a r u g i f n o c 1 e p y t . i i d n a m i a l c : s u b y r a d n o c e s s ' e g d i r b e h t s i s u b t e g r a t e h t f i . 1 . d a e r n o i t a r u g i f n o c 0 e p y t a s a h g u o r h t s s a p e h t d n i h e b s t s i x e t a h t s u b e t a n i d r o b u s a s i s u b t e g r a t e h t f i . 2 d n a m i a l c : ) s u b y r a d n o c e s e h t o t l a u q e t o n t u b ( e g d i r b . d a e r n o i t a r u g i f n o c 1 e p y t a s a h g u o r h t s s a p . e r o n g i , e s i w r e h t o . 3
53 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 12.1 primary interface (continued) # ] 0 : 3 [ e b c _ pd n a m m o cn o i t c a 1 1 0 1n o i t a r u g i f n o c e t i r w . d a e r n o i t a r u g i f n o c s a e m a s : e t i r w n o i t a r u g i f n o c 0 e p y t . i : ) t s e u q e r e l c y c l a i c e p s t o n ( e t i r w n o i t a r u g i f n o c 1 e p y t . i i s s a p d n a m i a l c : s u b y r a d n o c e s s ' e g d i r b e h t s i s u b t e g r a t e h t f i . 1 e t i r w n o i t a r u g i f n o c 0 e p y t a s a h g u o r h t e g d i r b e h t d n i h e b s t s i x e t a h t s u b e t a n i d r o b u s a s i s u b t e g r a t e h t f i . 2 h g u o r h t s s a p d n a m i a l c : ) s u b y r a d n o c e s e h t o t l a u q e t o n t u b ( . e t i r w n o i t a r u g i f n o c 1 e p y t a s a d e g n a h c n u . e r o n g i , e s i w r e h t o . 3 t s e u q e r e l c y c l a i c e p s s a e t i r w n o i t a r u g i f n o c . i i i : ) h 7 = n o i t c n u f , h f 1 = e c i v e d ( s s a p d n a m i a l c : s u b y r a d n o c e s s ' e g d i r b e h t s i s u b t e g r a t e h t f i . 1 e l c y c l a i c e p s a s a h g u o r h t e g d i r b e h t d n i h e b s t s i x e t a h t s u b e t a n i d r o b u s a s i s u b t e g r a t e h t f i . 2 h g u o r h t s s a p d n a m i a l c : ) s u b y r a d n o c e s e h t o t l a u q e t o n t u b ( . e t i r w n o i t a r u g i f n o c 1 e p y t a s a d e g n a h c n u e r o n g i , e s i w r e h t o . 3 0 0 1 1d a e r y r o m e m e l p i t l u m d a e r y r o m e m s a e m a s 1 0 1 1s s e r d d a l a u d e l c y c d e t r o p p u s t o n 0 1 1 1d a e r y r o m e m e n i l d a e r y r o m e m s a e m a s 1 1 1 1e t i r w y r o m e m e t a d i l a v n i & d a e r y r o m e m s a e m a s
54 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information # ] 0 : 3 [ e b c _ 1 s # ] 0 : 3 [ e b c _ 2 s d n a m m o cn o i t c a 0 0 0 0t p u r r e t n i e g d e l w o n k c a . e r o n g i 1 0 0 0e l c y c l a i c e p s. e r o n g i . m i a l c t o n o d 0 1 0 0d a e r o / i. e c a f r e t n i y r a m i r p s a e m a s 1 1 0 0e t i r w o / i. d a e r o / i s a e m a s 0 0 1 0d e v r e s e r- - - - - 1 0 1 0d e v r e s e r- - - - - 0 1 1 0d a e r y r o m e m. e c a f r e t n i y r a m i r p s a e m a s 1 1 1 0e t i r w y r o m e m. d a e r y r o m e m s a e m a s 0 0 0 1d e v r e s e r- - - - - 1 0 0 1d e v r e s e r- - - - - 0 1 0 1n o i t a r u g i f n o c d a e r . e r o n g i 1 1 0 1n o i t a r u g i f n o c e t i r w : e t i r w n o i t a r u g i f n o c 0 e p y t . i . e r o n g i : ) t s e u q e r e l c y c l a i c e p s t o n ( e t i r w n o i t a r u g i f n o c 1 e p y t . i i . e r o n g i t s e u q e r e l c y c l a i c e p s s a e t i r w n o i t a r u g i f n o c . i i i : ) h 7 = n o i t c n u f , h f 1 = e c i v e d ( h g u o r h t s s a p d n a m i a l c : s u b y r a m i r p s ' e g d i r b e h t s i s u b t e g r a t e h t f i . 1 . e l c y c l a i c e p s a s a s e s u b f o e g n a r n i t i s i r o n s u b y r a m i r p e h t r e h t i e n s i s u b t e g r a t e h t f i . 2 m i a l c : s r e t s i g e r s u b e t a n i d r o b u s d n a y r a d n o c e s s ' e g d i r b e h t y b d e n i f e d . e t i r w n o i t a r u g i f n o c 1 e p y t a s a d e g n a h c n u h g u o r h t s s a p d n a s e s u b f o e g n a r n i s i t u b : s u b y r a m i r p s ' e g d i r b e h t t o n s i s u b t e g r a t e h t f i . 3 . e r o n g i : s r e t s i g e r s u b e t a n i d r o b u s d n a y r a d n o c e s s ' e g d i r b e h t y b d e n i f e d 0 0 1 1d a e r y r o m e m e l p i t l u m d a e r y r o m e m s a e m a s 1 0 1 1s s e r d d a l a u d e l c y c d e t r o p p u s t o n 0 1 1 1d a e r y r o m e m e n i l d a e r y r o m e m s a e m a s 1 1 1 1e t i r w y r o m e m e t a d i l a v n i & d a e r y r o m e m s a e m a s 12.2 secondary interface
55 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 13. configuration registers as pi7c7100 supports two secondary interfaces, it has two sets of configuration registers which are almost identical and accessed through different function numbers. the description below is for one set only. pci configuration defines a 64-byte space (configuration header) to define various attributes of the pci-to-pci bridge as shown below. all of the registers in bold type are required by the pci specification and are implemented in this bridge. the others are available for use as control registers for the device. there are two configuration registers: configuration register 1 and configuration register 2 corresponding to secondary bus 1 and secondary bus 2 interfaces respectively. also, the configuration for the primary interface is implemented through the configuration register 1. 4 2 - 1 36 1 - 3 28 - 5 10 - 7s s e r d d a d i e c i v e dd i r o d n e v h 0 0 s u t a t sd n a m m o c h 4 0 e d o c s s a l cd i n o i s i v e r h 8 0 d e v r e s e r e p y t r e d a e hr e m i t y c n e t a l y r a m i r pe z i s e n i l e h c a c h c 0 d e v r e s e rh 4 1 - h 0 1 y c n e t a l y r a d n o c e s r e m i t s u b e t a n i d r o b u s r e b m u n s u b y r a d n o c e s r e b m u n s u b y r a m i r p r e b m u n h 8 1 s u t a t s y r a d n o c e st i m i l o / ie s a b o / i h c 1 t i m i l y r o m e me s a b y r o m e m h 0 2 t i m i l y r o m e m e l b a h c t e f e r p e s a b y r o m e m e l b a h c t e f e r ph 4 2 d e v r e s e rh c 2 - h 8 2 s t i b 6 1 r e p p u t i m i l o / i s t i b 6 1 r e p p u e s a b o / ih 0 3 d i m e t s y s b u sd i r o d n e v m e t s y s b u sh 4 3 d e v r e s e rh 8 3 l o r t n o c e g d i r b n i p t p u r r e t n id e v r e s e r h c 3 l o r t n o c r e t i b r al o r t n o c c i t s o n g a i dl o r t n o c p i h ch 0 4 t i m i l y r o m e m e l b a h c t e f e r p y r a m i r p e s a b y r o m e m e l b a h c t e f e r p y r a m i r ph 4 4 d e v r e s e rh 0 6 - h 8 4 d e v r e s e rt n e v e # r r e s _ p e l b a s i d h 4 6 d e v r e s e rd e v r e s e rl o r t n o c k c o l c y r a d n o c e sh 8 6 d e v r e s e rh c 6 t i m i l y r o m e m d e t s o p - n o n e s a b y r o m e m d e t s o p - n o nh 0 7 r e t n u o c t u o e m i t r e t s a mn o i t p o t r o ph 4 7 r e t n u o c y r t e rh 8 7 r e m i t g n i l p m a sh c 7 t n u o c d a e r o / i l u f s s e c c u s y r a d n o c e s h 0 8 t n u o c e t i r w o / i l u f s s e c c u s y r a d n o c e s h 4 8 t n u o c d a e r y r o m e m l u f s s e c c u s y r a d n o c e s h 8 8 t n u o c e t i r w y r o m e m l u f s s e c c u s y r a d n o c e s h c 8 t n u o c d a e r o / i l u f s s e c c u s y r a m i r p h 0 9 t n u o c e t i r w o / i l u f s s e c c u s y r a m i r p h 4 9 t n u o c d a e r y r o m e m l u f s s e c c u s y r a m i r p h 8 9 t n u o c e t i r w y r o m e m l u f s s e c c u s y r a m i r p h c 9 d e v r e s e rh f f - h 0 a 13.1 configuration register 1
56 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 4 2 - 1 36 1 - 3 28 - 5 10 - 7s s e r d d a d i e c i v e dd i r o d n e v h 0 0 s u t a t sd n a m m o c h 4 0 e d o c s s a l cd i n o i s i v e r h 8 0 d e v r e s e r e p y t r e d a e hr e m i t y c n e t a l y r a m i r pe z i s e n i l e h c a c h c 0 d e v r e s e rh 4 1 - h 0 1 y c n e t a l y r a d n o c e s r e m i t s u b e t a n i d r o b u s r e b m u n s u b y r a d n o c e s r e b m u n s u b y r a m i r p r e b m u n h 8 1 s u t a t s y r a d n o c e st i m i l o / ie s a b o / i h c 1 t i m i l y r o m e me s a b y r o m e m h 0 2 t i m i l y r o m e m e l b a h c t e f e r p e s a b y r o m e m e l b a h c t e f e r ph 4 2 d e v r e s e rh c 2 - h 8 2 s t i b 6 1 r e p p u t i m i l o / is t i b 6 1 r e p p u e s a b o / ih 0 3 d i m e t s y s b u sd i r o d n e v m e t s y s b u sh 4 3 d e v r e s e rh 8 3 l o r t n o c e g d i r b n i p t p u r r e t n id e v r e s e r h c 3 l o r t n o c r e t i b r al o r t n o c c i t s o n g a i dl o r t n o c p i h ch 0 4 t i m i l y r o m e m e l b a h c t e f e r p y r a m i r p e s a b y r o m e m e l b a h c t e f e r p y r a m i r ph 4 4 d e v r e s e rh 0 6 - h 8 4 d e v r e s e rh 4 6 d e v r e s e rd e v r e s e rl o r t n o c k c o l c y r a d n o c e sh 8 6 d e v r e s e rh c 6 t i m i l y r o m e m d e t s o p - n o n e s a b y r o m e m d e t s o p - n o nh 0 7 d e v r e s e rd e v r e s e rh 4 7 d e v r e s e rh 8 7 r e m i t g n i l p m a sh c 7 t n u o c d a e r o / i l u f s s e c c u s y r a d n o c e sh 0 8 t n u o c e t i r w o / i l u f s s e c c u s y r a d n o c e sh 4 8 t n u o c d a e r y r o m e m l u f s s e c c u s y r a d n o c e s h 8 8 t n u o c e t i r w y r o m e m l u f s s e c c u s y r a d n o c e s h c 8 d e v r e s e rh 0 9 d e v r e s e rh 4 9 d e v r e s e rh 8 9 d e v r e s e rh c 9 d e v r e s e rh f f - h 0 a 13.2 configuration register 2
57 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 13.2.1 config register 1 or 2: vendor id register (read only, bit 15-0; offset 00h) pericom id is 12d8h. 13.2.2 config register 1: device id register (read only, bit 31-16; offset 00h) hardwired to 1b59h (s1) 13.2.3 config register 2: device id register (read only, bit 31-16; offset 00h) hardwired to 1b5ah (s2) 13.2.4 configuration register 1: command register (bit 15-0; offset 04h) t i bn o i t c n u fe p y tn o i t p i r c s e d 0 1 - 5 1d e v r e s e ro / r' 0 0 0 0 0 0 ' o t t e s e r 9 o t k c a b t s a f e l b a n e k c a b w / r s n o i t c a s n a r t k c a b - o t - k c a b t s a f e t a r e n e g o t y t i l i b a s ' e g d i r b s l o r t n o c . e c a f r e t n i y r a m i r p e h t n o s e c i v e d t n e r e f f i d o t n o i t c a s n a r t k c a b o t k c a b t s a f o n = 0 n o i t c a s n a r t k c a b o t k c a b t s a f e l b a n e = 1 0 o t t e s e r 8 e l b a n e # r r e sw / r. n i p # r r e s _ p e h t r o f e l b a n e e h t s l o r t n o c r e v i r d # r r e s _ p e h t e l b a s i d = 0 r e v i r d # r r e s _ p e h t e l b a n e = 1 0 o t t e s e r 7 l o r t n o c e l c y c t i a wo / r. d e t r o p p u s g n i p p e t s a t a d o n 0 o t t e s e r 6 e l b a n e r o r r e y t i r a pw / r. s r o r r e y t i r a p o t e s n o p s e r s ' e g d i r b s l o r t n o c s r o r r e y t i r a p y n a e r o n g i = 0 d e m r o f r e p g n i k c e h c y t i r a p l a m r o n = 1 0 o t t e s e r 5 e l b a n e p o o n s e t t e l a p a g vw / r . s e s s e c c a e t t e l a p e l b i t a p m o c a g v o t e s n o p s e r s ' e g d i r b s l o r t n o c e c a f r e t n i y r a m i r p e h t n o s e s s e c c a e t t e l a p a g v e r o n g i = 0 e c a f r e t n i y r a m i r p e h t n o s e t i r w e t t e l a p a g v o t e s n o p s e r e l b a n e = 1 h 8 c 3 , h 6 c 3 = ] 0 : 9 [ d a s s e r d d a o / i () h 9 c 3 d n a 0 o t t e s e r 4 d n a e t i r w y r o m e m e l b a n e e t a d i l a v n i o / rd e t r o p p u s t o n e t a d i l a v n i d n a e t i r w y r o m e m 0 o t t e s e r 3 e l b a n e e l c y c l a i c e p so / rn o i t a t n e m e l p m i e l c y c l a i c e p s o n 0 o t t e s e r 2 e l b a n e r e t s a m s u bw / ry r a m i r p e h t n o r e t s a m a s a e t a r e p o o t y t i l i b a s ' e g d i r b s l o r t n o c . e c a f r e t n i d n a e c a f r e t n i y r a m i r p e h t n o n o i t c a s n a r t e t a i t i n i t o n o d = 0 y r a d n o c e s n o s n o i t c a s n a r t o / i r o y r o m e m o t e s n o p s e r e l b a s i d e c a f r e t n i y r a m i r p e h t n o r e t s a m a s a e t a r e p o o t e g d i r b e h t e l b a n e = 1 e c a f r e t n i 0 o t t e s e r 1 e l b a n e e c a p s y r o m e mw / ry r a m i r p e h t n o s e s s e c c a y r o m e m o t e s n o p s e r s ' e g d i r b s l o r t n o c . e c a f r e t n i n o i t c a s n a r t y r o m e m l l a e r o n g i = 0 n o i t c a s n a r t y r o m e m o t e s n o p s e r e l b a n e = 1 0 o t t e s e r 0 e l b a n e e c a p s o / iw / r . e c a f r e t n i y r a m i r p e h t n o s e s s e c c a o / i o t e s n o p s e r s ' e g d i r b s l o r t n o c n o i t c a s n a r t o / i e r o n g i = 0 n o i t c a s n a r t o / i o t e s n o p s e r e l b a n e = 1 0 o t t e s e r note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear
58 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information t i bn o i t c n u fe p y tn o i t p i r c s e d 0 1 - 5 1 d e v r e s e ro / r ' 0 0 0 0 0 0 ' o t t e s e r 9d e v r e s e rw / r 0 o t t e s e r 8d e v r e s e rw / r 0 o t t e s e r 7 l o r t n o c e l c y c t i a wo / r. d e t r o p p u s g n i p p e t s a t a d o n 0 o t t e s e r 6 d e v r e s e rw / r 0 o t t e s e r 5 e t t e l a p a g v e l b a n e p o o n s w / r. s e s s e c c a e t t e l a p e l b i t a p m o c a g v o t e s n o p s e r s ' e g d i r b s l o r t n o c e c a f r e t n i y r a m i r p e h t n o s e s s e c c a e t t e l a p a g v e r o n g i = 0 e c a f r e t n i y r a m i r p e h t n o s e t i r w e t t e l a p a g v o t e s n o p s e r e l b a n e = 1 ) h 9 c 3 d n a h 8 c 3 , h 6 c 3 = ] 0 : 9 [ d a s s e r d d a o / i ( 0 o t t e s e r 4 d n a e t i r w y r o m e m e l b a n e e t a d i l a v n i o / r. d e t r o p p u s t o n e t a d i l a v n i d n a e t i r w y r o m e m 0 o t t e s e r 3 e l c y c l a i c e p s e l b a n e o / r. n o i t a t n e m e l p m i e l c y c l a i c e p s o n 0 o t t e s e r 2 r e t s a m s u b e l b a n e w / r . e c a f r e t n i y r a m i r p e h t n o r e t s a m a s a e t a r e p o o t y t i l i b a s ' e g d i r b s l o r t n o c e l b a s i d d n a e c a f r e t n i y r a m i r p e h t n o n o i t c a s n a r t e t a i t i n i t o n o d = 0 e c a f r e t n i y r a d n o c e s n o s n o i t c a s n a r t o / i r o y r o m e m o t e s n o p s e r e c a f r e t n i y r a m i r p e h t n o r e t s a m a s a e t a r e p o o t e g d i r b e h t e l b a n e = 1 0 o t t e s e r 1 e l b a n e e c a p s y r o m e mw / ry r a m i r p e h t n o s e s s e c c a y r o m e m o t e s n o p s e r s ' e g d i r b s l o r t n o c . e c a f r e t n i n o i t c a s n a r t y r o m e m l l a e r o n g i = 0 n o i t c a s n a r t y r o m e m o t e s n o p s e r e l b a n e = 1 0 o t t e s e r 0 e l b a n e e c a p s o / iw / r . e c a f r e t n i y r a m i r p e h t n o s e s s e c c a o / i o t e s n o p s e r s ' e g d i r b s l o r t n o c n o i t c a s n a r t o / i e r o n g i = 0 n o i t c a s n a r t o / i o t e s n o p s e r e l b a n e = 1 0 o t t e s e r 13.2.5 configuration register 2: command register (bit 15-0; offset 04h) note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear
59 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 13.2.6 configuration register 1 or 2: status register (for primary bus, bits 31-16; offset 04h) t i bn o i t c n u fe p y tn o i t p i r c s e d 1 3r o r r e y t i r a p d e t c e t e dc w / re h t f o s s e l d r a g e r d e t c e t e d s i r o r r e y t i r a p a r e v e n e h w t e s e b d l u o h s . r e t s i g e r d n a m m o c e h t f o 6 t i b f o e t a t s 0 o t t e s e r 0 3r o r r e m e t s y s d e l a n g i sc w / r. d e t r e s s a s i # r r e s _ p r e v e n e h w t e s e b d l u o h s 0 o t t e s e r 9 2t r o b a r e t s a m d e v i e c e rc w / rd e t a n i m r e t e r a s n o i t c a s n a r t n e h w ) r e t s a m a y b ( ' 1 ' o t t e s . t r o b a r e t s a m h t i w 0 o t t e s e r 8 2t r o b a t e g r a t d e v i e c e rc w / rd e t a n i m r e t e r a s n o i t c a s n a r t n e h w ) e c i v e d r e t s a m a y b ( ' 1 ' o t t e s . t r o b a t e g r a t h t i w 0 o t t e s e r 7 2t r o b a t e g r a t d e l a n g i sc w / rt r o b a t e g r a t a r e v e n e h w ) e c i v e d t e g r a t a y b ( t e s e b d l u o h s . s r u c c o e l c y c 0 o t t e s e r 5 2 - 6 2g n i m i t l e s v e do / r. g n i m i t # l e s v e d m u i d e m ' 1 0 ' o t t e s e r 4 2d e t c e t e d r o r r e y t i r a p a t a dc w / r: t e m e r a s n o i t i d n o c g n i w o l l o f e h t n e h w t e s s i t i d e t r e s s a s i # r r e p _ p . 1 t e s s i r e t s i g e r d n a m m o c f o 6 t i b . 2 0 o t t e s e r 3 2e l b a p a c k c a b o t k c a b t s a fo / r. e d i s y r a m i r p n o e l b a p a c e t i r w k c a b - o t - k c a b t s a f 1 o t t e s e r 2 2d e v r e s e ro / r 0 o t t e s e r 1 2d e v r e s e ro / r 1 o t t e s e r 0 2t s i l s e i t i l i b a p a co / r. d e t r o p p u s t o n s i t s i l s e i t i l i b a p a c 0 o t t e s e r 6 1 - 9 1d e v r e s e ro / r 0 o t t e s e r note: r/w - read/write; r/o - read only; r/wc - read/write1 to clear.
60 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 13.2.7 config register 1 or 2: revision id register (read only, bit 7-0; offset 08h) hardwired to 01h 13.2.8 config register 1 or 2: class code register (read only, bit 31-8; offset 08h) hardwired to 060400h 13.2.9 config register 1 or 2: cache line size register (read/write, bit 7-0; offset 0ch) this register is used when terminating memory write and invalidate transactions and when pre-fetching. only cache line sizes (in units of 4-byte) which are power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, 10h are valid values). reset to 00h 13.2.10 config register 1: primary latency timer register (read/write, bit 15-8; offset 0ch) this register sets the value for master latency timer which starts counting when master asserts frame#. reset to 00h 13.2.11 config register 2: primary latency timer register (read/write, bit 15-8; offset 0ch) this register is implemented but not being used internally. reset to 00h 13.2.12 config register 1: header type register (read only, bit 23-16; offset 0ch) hardwired to 81h for function 0 (multiple function pci-to-pci bridge, for secondary bus s1) 13.2.13 config register 2: header type register (read only, bit 23-16; offset 0ch) hardwired to 01h for function 1 (single function pci-to-pci bridge, for secondary bus s2) 13.2.14 config register 1: primary bus number register (read/write, bit 7-0; offset 18h) programmed with the number of the pci bus to which the primary bridge interface is connected. this value is set by software during configuration. reset to 00h 13.2.15 config register 2: primary bus number register (read/write, bit 7-0; offset 18h) this register is implemented but not being used internally. reset to 00h 13.2.16 config register 1 or 2: secondary bus number register (read/write, bit 15-8; offset 18h) programmed with the number of the pci bridge secondary bus interface. this value is set by software during configu- ration. reset to 00h 13.2.17 config register 1 or 2: subordinate bus number register (read/write, bit 23-16; offset 18h) programmed with the number of the pci bus with the highest number that is subordinate to the bridge. this value is set by software during configuration. reset to 00h 13.2.18 config register 1 or 2: secondary latency timer (read/write, bit 31-24; offset 18h) this register is programmed in units of pci bus clocks.the latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. reset to 00h 13.2.19 config register 1 or 2: i/o base register (read/write, bit 7-0; offset 1ch) this register defines the bottom address of the i/o address range for the bridge. the upper four bits define the bottom address range used by the chip to determine when to forward i/o transactions from one interface to the other. these 4 bits correspond to address bits [15:12] and are write-able. the upper 16 bits corresponding to address bits [31:16] are defined in the i/o base upper 16 bits address register. the address bits [11:0] are assumed to be 000h. the lower four bits (3:0) of this register set to 0001 (read-only) to indicate 32-bit i/o addressing. reset to 00h 13.2.20 config register 1 or 2: i/o limit register (read/write, bit 15-8; offset 1ch) this register defines the top address of the i/o address range for the bridge. the upper four bits define the top address range used by the chip to determine when to forward i/o transactions from one interface to the other. these 4 bits correspond to address bits [15:12] and are write-able. the upper 16 bits corresponding to address bits [31:16] are defined in the i/o limit upper 16 bits address register. the address bits [11:0] are assumed to be fffh. the lower four bits (3:0) of this register set to 0001 (read-only) to indicate 32-bit i/o addressing. reset to 00h.
61 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information t i bn o i t c n u fe p y tn o i t p i r c s e d 1 3r o r r e y t i r a p d e t c e t e dc w / re h t f o s s e l d r a g e r d e t c e t e d s i r o r r e y t i r a p a r e v e n e h w t e s e b d l u o h s . r e t s i g e r d n a m m o c e h t f o 6 t i b f o e t a t s 0 o t t e s e r 0 3r o r r e m e t s y s d e l a n g i sc w / r. d e t c e t e d s i # r r e s _ 2 s r o # r r e s _ 1 s r e v e n e h w t e s e b d l u o h s . t e s e r r e t f a ' 0 ' a e b d l u o h s 0 o t t e s e r 9 2t r o b a r e t s a m d e v i e c e rc w / rh t i w d e t a n i m r e t e r a s n o i t c a s n a r t n e h w ) r e t s a m a y b ( ' 1 ' o t t e s . t r o b a r e t s a m 0 o t t e s e r 8 2t r o b a t e g r a t d e v i e c e rc w / r h t i w d e t a n i m r e t e r a s n o i t c a s n a r t n e h w ) e c i v e d r e t s a m a y b ( ' 1 ' o t t e s . t r o b a t e g r a t 0 o t t e s e r 7 2t r o b a t e g r a t d e l a n g i sc w / r . s r u c c o e l c y c t r o b a t e g r a t a r e v e n e h w ) e c i v e d t e g r a t a y b ( t e s e b d l u o h s . t e s e r r e t f a ' 0 ' e b d l u o h s 0 o t t e s e r 5 2 - 6 2g n i m i t l e s v e do / r. g n i m i t # l e s v e d m u i d e m ' 1 0 ' o t t e s e r 4 2d e t c e t e d r o r r e y t i r a p a t a dc w / r: t e m e r a s n o i t i d n o c g n i w o l l o f e h t n e h w t e s s i t i d e t r e s s a s i # r r e p _ 2 s r o # r r e p _ 1 s . 1 t e s s i r e t s i g e r d n a m m o c f o 6 t i b . 2 0 o t t e s e r 3 2e l b a p a c k c a b - o t - k c a b t s a fo / r. s e s u b y r a d n o c e s n o e l b a p a c e t i r w k c a b - o t - k c a b t s a f 1 o t t e s e r 2 2d e v r e s e ro / r 0 o t t e s e r 1 2d e v r e s e ro / r 0 o t t e s e r 6 1 - 0 2d e v r e s e ro / r ' 0 0 0 0 0 ' o t t e s e r 13.2.21 configuration register 1 or 2: secondary status register (bits 31-16; offset 1ch) note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear
62 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 13.2.22 config register 1 or 2: memory base register (read/write, bit 15-0; offset 20h) this register defines the base address of the memory-mapped address range for forwarding the cycle through the bridge. the upper twelve bits corresponding to address bits [31:20] are read/write. the twelve bits are reset to 000h. the lower 20 address bits (19:0) are assumed to be 00000h. 13.2.23 config register 1 or 2: memory limit register (read/write, bit 31:16; offset 20h) this register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bridge. upper twelve bits corresponding to address bit [31:20] are read/write. upper twelve bits are reset to 0000h. lower 20 address bits (19:0) are assumed to be fffffh. 13.2.24 config register 1 or 2: prefetchable memory base register (read/write, bit 15-0;offset 24h) this register defines the base address of the prefetchable memory-mapped address range for forwarding the cycle through the bridge. the upper twelve bits corresponding to address bits [31:20] are read/write. the upper twelve bits are reset to 000h. the lower four bits are read only and are set to 0. the lower 20 address bits (19:0) are as- sumed to be 00000h. 13.2.25 config register 1 or 2: prefetchable memory limit register (read/write, bit 31-16; offset 24h) this register defines the upper limit address of the memory-mapped address range for forwarding the cycle through the bri dge. the upper twelve bits correspond to address bit [31:20] are read/write. the upper twelve bits are reset to 000h. the lower four bits are read only and are set to 0. the lower 20 address bits (19:0) are assumed to be fffffh. 13.2.26 config register 1 or 2: i/o base address upper 16 bits register (read/write, bit 15-0; offset 30h) this register defines the upper 16 bits of a 32-bit base i/o address range used for forwarding the cycle through the bridge. reset to 0000h. 13.2.27 config register 1 or 2: i/o limit address upper 16 bits register (read/write, bit 31-16; offset 30h) this register defines the upper 16 bits of a 32-bit limit i/o address range used for forwarding the cycle through the bridge. reset to 0000h. 13.2.28 config register 1 or 2: subsystem vendor id (read/write, bit 15-0; offset 34h) a 16-bit register for add-on cards to distinguish from one another. reset to 0000h. 13.2.29 config register 1 or 2: subsystem id (read/write, bit 31-16; offset 34h) a 16-bit register for add-on cards to distinguish from one another. reset to 0000h. 13.2.30 config register 1 or 2: interrupt pin register (read only, bit 15-8; offset 3ch) the register reads as 00h to indicate that pi7c7100 does not use any interrupt pins.
63 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information t i bn o i t c n u fe p y tn o i t p i r c s e d 8 2 - 1 3d e v r e s e ro / r ' 0 0 0 0 ' o t t e s e r 7 2d e v r e s e rw / r 0 o t t e s e r 6 2t u o e m i t r e t s a m s u t a t s c w / r. t u o e m i t r e t s a m y r a d n o c e s r o r e t s a m y r a m i r p r e h t i e n e h w ' 1 ' o t t e s 0 o t t e s e r 5 2d e v r e s e rw / r 0 o t t e s e r 4 2d e v r e s e rw / r 0 o t t e s e r 3 2k c a b - o t - k c a b t s a f e l b a n e w / r o t s n o i t c a s n a r t k c a b - o t - k c a b t s a f e t a r e n e g o t y t i l i b a s ' e g d i r b s l o r t n o c t n e r e f f i d y r a d n o c e s e h t n o s e c i v e d. e c a f r e t n i n o i t c a s n a r t k c a b - o t - k c a b t s a f o n = 0 n o t c a s n a r t k c a b - o t - k c a b t s a f e l b a n e = 1 0 o t t e s e r 2 2e c a f r e t n i y r a d n o c e s t e s e r w / r y r a d n o c e s e h t n o n i p l a n g i s # t e s e r _ 2 s r o # t e s e r _ 1 s f o n o i t r e s s a e h t s e c r o f . e c a f r e t n i n i p # t e s e r _ 2 s r o # t e s e r _ 1 s f o n o i t r e s s a e h t e c r o f t o n o d = 0 n i p # t e s e r _ 2 s r o # t e s e r _ 1 s f o n o i t r e s s a e h t e c r o f = 1 0 o t t e s e r 1 2e d o m t r o b a r e t s a mw / r y r a d n o c e s n o s t r o b a r e t s a m o t g n i d n o p s e r r o i v a h e b s ' e g d i r b s l o r t n o c . e c a f r e t n i d n a d a e r n o h f f f f _ f f f f n r u t e r ( s t r o b a r e t s a m t r o p e r t o n o d = 0 ) e t i r w n o a t a d d r a c s i d f o n o i t r e s s a e h t y b e l b i s s o p f i t r o b a t e g r a t g n i l a n g i s y b s t r o b a r e t s a m t r o p e r = 1 d e l b a n e f i # r r e s _ p 0 o t t e s e r 0 2d e v r e s e ro / r 0 o t t e s e r 9 1e l b a n e a g vw / r. s e s s e r d d a e l b i t a p m o c a g v o t e s n o p s e r s ' e g d i r b e h t s l o r t n o c s e s s e r d d a o / i d n a y r o m e m e l b i t a p m o c a g v d r a w r o f t o n o d = 0 y r a d n o c e s o t y r a m i r p m o r f y r a d n o c e s o t y r a m i r p m o r f s s e r d d a o / i d n a y r o m e m e l b i t a p m o c a g v d r a w r o f = 1 s g n i t t e s r e h t o f o s s e l d r a g e r 0 o t t e s e r 8 1e l b a n e a s iw / r . k 4 6 t s r i f e h t o t d e t i m i l s i h c i h w s s e r d d a o / i a s i o t e s n o p s e r s ' e g d i r b s l o r t n o c b o / i e h t y b d e n i f e d e g n a r e h t n i s e s s e r d d a o / i l l a d r a w r o f = 0 a o / i d n a e s s r e t s i g e r t i m i l , e h t y b d e n i f e d e g n a r e h t n i s e s s e r d d a o / i a s i f o g n i d r a w r o f k c o l b = 1 s s e r d d a t a h t e c a p s o / i f o k 4 6 t s r i f e h t n i e r a t a h t s r e t s i g e r t i m i l o / i d n a e s a b o / i e r a s n o i t c a s n a r t o / i y r a d n o c e s . k c o l b s e t y b k 1 h c a e n i s e t y b 8 6 7 t s a l e h t e h t n i h t i w s l l a f s s e r d d a e h t f i m a e r t s p u d e d r a w r o f k c o l b e t y b k 1 h c a e n i s e t y b 8 6 7 t s a l 0 o t t e s e r 7 1r o # r r e s _ 1 s # r r e s _ 2 s e l b a n e . e c a f r e t n i y r a m i r p e h t o t # r r e s _ 2 s r o # r r e s _ 1 s f o g n i d r a w r o f e h t s l o r t n o c y r a m i r p o t # r r e s _ 2 s r o # r r e s _ 1 s g n i d r a w r o f e h t e l b a s i d = 0 . e c a f r e t n i y r a m i r p o t # r r e s _ 2 s r o # r r e s _ 1 s f o g n i d r a w r o f e h t e l b a n e = 1 0 o t t e s e r 6 1r o r r e y t i r a p e s n o p s e r e l b a n e . e c a f r e t n i y r a d n o c e s e h t n o s r o r r e y t i r a p o t e s n o p s e r s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a d n o c e s e h t n o s r o r r e y t i r a p a t a d d n a s s e r d d a e r o n g i = 0 . e c a f r e t n i y r a d n o c e s e h t n o n o i t c e t e d d n a g n i t r o p e r r o r r e y t i r a p e l b a n e = 1 0 o t t e s e r 13.2.31 configuration register 1 or 2: bridge control register (bits 31-16; offset 3ch) note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear.
64 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information t i bn o i t c n u fe p y tn o i t p i r c s e d 1 1 - 5 1d e v r e s e ro / r ' 0 0 0 0 0 ' o t t e s e r 9 - 0 1e d o m t s e tw / r e r a r e t n u o c f o s t i b l l a , 0 0 n e h w . s r e t n u o c l a n r e t n i s ' p i h c f o y t i l i b a t s e t s l o r t n o c f o 2 e t y b , 0 1 n e h w . d e s i c r e x e s i r e t n u o c f o 1 e t y b , 1 0 n e h w . d e s i c r e x e . d e s i c r e x e s i r e t n u o c f o 3 e t y b , 1 1 n e h w . d e s i c r e x e s i r e t n u o c 0 o t t e s e r 5 - 8d e v r e s e ro / r ' 0 0 0 0 ' o t t e s e r 4d e v r e s e rw / r 0 o t t e s e r 2 - 3d e v r e s e ro / r ' 0 0 ' o t t e s e r 1d e v r e s e rw / r 0 o t t e s e r 0d e v r e s e ro / r 0 o t t e s e r t i bn o i t c n u fe p y tn o i t p i r c s e d 8 2 : 1 3d e v r e s e ro / r ' 0 0 0 0 ' o t t e s e r 7 2d i r b y hw / r. 2 d n a 1 s u b y r a d n o c e s m o r f s r e t s a m r o f n o i t a r t i b r a d e x i m # ] 0 : 7 [ q e r _ 2 s d n a # ] 0 : 7 [ q e r _ 1 s r o f n o i t a r t i b r a e t a r a p e s = 0 . n o i t a r t i b r a r o f # ] 0 : 3 [ q e r _ 2 s h t i w d e x i m e r a # ] 0 : 3 [ q e r _ 1 s = 1 . d e s u s i r e t i b r a e n o y l n o 0 o t t e s e r 6 2d e v r e s e rw / r 0 o t t e s e r 5 2f o y t i r o i r p y r a d n o c e s t r o p w / ry t i r o i r p h g i h n i s i 0 0 1 7 c 7 i p f o t r o p y r a d n o c e s e h t r e h t e h w s e n i f e d . p u o r g y t i r o i r p w o l e h t r o p u o r g p u o r g y t i r o i r p w o l = 0 p u o r g y t i r o i r p h g i h = 1 1 o t t e s e r 4 2d e v r e s e ro / r 0 o t t e s e r 6 1 - 3 2r e t i b r a l o r t n o c w / r y t i r o i r p h g i h e h t o t d e n g i s s a s i r e t s a m s u b - y r a d n o c e s a r e h t e h w s l o r t n o c t i b h c a e s t u p n i t s e u q e r o t d n o p s e r r o c ] 0 : 7 [ t i b . p u o r g y t i r o i r p w o l e h t r o p u o r g . # ] 0 : 7 [ q e r _ 2 s r o # ] 0 : 7 [ q e r _ 1 s ' 0 0 0 0 0 0 0 0 ' o t t e s e r 13.2.32 configuration register 1 or 2: diagnostic/chip control register (bit 15-0, offset 40h) 13.2.33 configuration register 1 or 2: arbiter control register (bit 31-16, offset 40h) note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear.
65 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 13.2.34 config register 1: primary prefetchable memory base register (read/write, bit 15-0; offset 44h) this register is implemented but not being used internally.this register defines the base address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. the upper twelve bits corresponding to address bits [31:20] are read/write. the upper twelve bits are reset to 0000h. the lower four bits are read only and are set to 0h. the lower 20 address bits (19:0) are assumed to be 00000h. 13.2.35 config register 2: primary prefetchable memory base register (read/write, bit 15-0; offset 44h) this register is implemented but not being used internally. the upper twelve bits corresponding to address bits [31:20] are read/write. the upper twelve bits are reset to 0000h. the lower four bits are read only and are set to 0h. 13.2.36 config register 1: primary prefetchable memory limit register (read/write, bit 31-16; offset 44h) this register is implemented but not being used internally.this register defines the upper limit address of the primary prefetchable memory-mapped address range for forwarding the cycle through the bridge. the upper twelve bits corresponding to address bits [31:20] are read/write. the upper twelve bits are reset to 0000h. the lower four bits are read only and are set to 0h. the lower 20 address bits (19:0) are assumed to be fffffh. 13.2.37 config register 2: primary prefetchable memory limit register (read/write, bit 31-16; offset 44h) this register is implemented but not being used internally. the upper twelve bits corresponding to address bits [31:20] are read/write. the upper twelve bits are reset to 0000h. the lower four bits are read only and are set to 0h. t i bn o i t c n u fe p y tn o i t p i r c s e d 7d e v r e s e ro / r 0 o t t e s e r 6- d a e r d e y a l e d m o r f a t a d o n t e g r a t w / r y n a r e f s n a r t o t e l b a n u s i t i n e h w # r r e s _ p t r e s s a o t 0 0 1 7 c 7 i p f o y t i l i b a s l o r t n o c 2 r e t f a t e g r a t e h t m o r f a t a d d a e r 4 2 t n e v e s i h t f i d e t r e s s a s i # r r e s _ p . s t p m e t t a . t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e # r r e s d n a 0 s i t i b s i h t n e h w s r u c c o 0 o t t e s e r 5e t i r w d e y a l e d r e v i l e d n o n w / r r e f s n a r t o t e l b a n u s i t i n e h w # r r e s _ p t r e s s a o t 0 0 1 7 c 7 i p f o y t i l i b a s l o r t n o c 2 r e t f a a t a d e t i r w d e y a l e d 4 2 s r u c c o t n e v e s i h t f i d e t r e s s a s i # r r e s _ p . s t p m e t t a . t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e # r r e s d n a 0 s i t i b s i h t n e h w 0 o t t e s e r 4t r o b a r e t s a m d e t s o p n o e t i r w w / r t r o b a r e t s a m a s e v i e c e r t i n e h w # r r e s _ p t r e s s a o t 0 0 1 7 c 7 i p f o y t i l i b a s l o r t n o c t n e v e s i h t f i d e t r e s s a s i # r r e s _ p . a t a d e t i r w d e t s o p r e v i l e d o t g n i t p m e t t a n e h w . t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e # r r e s d n a 0 s i t i b s i h t n e h w s r u c c o 0 o t t e s e r 3t r o b a t e g r a t d e t s o p g n i r u d e t i r w w / r t r o b a t e g r a t a s e v i e c e r t i n e h w # r r e s _ p t r e s s a o t 0 0 1 7 c 7 i p f o y t i l i b a s l o r t n o c t n e v e s i h t f i d e t r e s s a s i # r r e s _ p . a t a d e t i r w d e t s o p r e v i l e d o t g n i t p m e t t a n e h w . t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e # r r e s d n a 0 s i t i b s i h t n e h w s r u c c o 0 o t t e s e r 2e t i r w d e t s o p y r e v i l e d - n o n w / r d e t s o p r e v i l e d o t e l b a n u s i t i n e h w # r r e s _ p t r e s s a o t 0 0 1 7 c 7 i p f o y t i l i b a s l o r t n o c 2 r e t f a a t a d e t i r w 4 2 t i b s i h t n e h w s r u c c o t n e v e s i h t f i d e t r e s s a s i # r r e s _ p . s t p m e t t a . t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e # r r e s d n a 0 s i 0 o t t e s e r 1e t i r w d e t s o p r o r r e y t i r a p w / r n o d e t c e t e d s i r o r r e y t i r a p a n e h w # r r e s _ p t r e s s a o t 0 0 1 7 c 7 i p f o y t i l i b a s l o r t n o c t n e v e s i h t f i d e t r e s s a s i # r r e s _ p . n o i t c a s n a r t e t i r w d e t s o p a g n i r u d s u b t e g r a t e h t . t e s s i r e t s i g e r d n a m m o c e h t n i t i b e l b a n e # r r e s d n a 0 s i t i b s i h t n e h w s r u c c o 0 o t t e s e r 0d e v r e s e ro / r 0 o t t e s e r 13.2.38 config register 1 or 2: p_serr# event disable register (bit 7-0; offset 64h) note: r/w - read/write, r/o - read only, r/wc - read/ write 1 to clear.
66 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information t i bn o i t c n u fe p y tn o i t p i r c s e d 4 1 - 5 1 e l b a s i d 7 k c o l c w / r d e l b a n e s i ] 7 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 7 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 2 1 - 3 1 e l b a s i d 6 k c o l c d e l b a n e s i ] 6 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 6 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 0 1 - 1 1 e l b a s i d 5 k c o l c d e l b a n e s i ] 5 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 5 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 8 - 9 e l b a s i d 4 k c o l c d e l b a n e s i ] 4 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 4 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 6 - 7 e l b a s i d 3 k c o l c d e l b a n e s i ] 3 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 3 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 4 - 5 e l b a s i d 2 k c o l c d e l b a n e s i ] 2 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 2 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 2 - 3 e l b a s i d 1 k c o l c d e l b a n e s i ] 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 0 - 1 e l b a s i d 0 k c o l c d e l b a n e s i ] 0 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 0 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w t i bn o i t c n u fe p y tn o i t p i r c s e d 4 1 - 5 1 e l b a s i d 7 k c o l c w / r d e l b a n e s i ] 5 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 5 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 2 1 - 3 1 e l b a s i d 6 k c o l c d e l b a n e s i ] 4 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 4 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 0 1 - 1 1 e l b a s i d 5 k c o l c d e l b a n e s i ] 3 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 3 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 8 - 9 e l b a s i d 4 k c o l c d e l b a n e s i ] 2 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 2 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 6 - 7 e l b a s i d 3 k c o l c d e l b a n e s i ] 1 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 1 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 4 - 5 e l b a s i d 2 k c o l c d e l b a n e s i ] 0 1 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 0 1 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 2 - 3 e l b a s i d 1 k c o l c d e l b a n e s i ] 9 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 9 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 0 - 1 e l b a s i d 0 k c o l c d e l b a n e s i ] 8 [ t u o k l c _ s , 0 s i t i b r e h t i e f i d e l b a s i d s i ] 8 [ t u o k l c _ s , 1 e r a s t i b h t o b n e h w 13.2.39 configuration register 1: secondary clock control register (bit 15-0; offset 68h) 13.2.40 configuration register 2: secondary clock control register (bit 15-0; offset 68h) note: r/w - read/write.
67 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 13.2.41 config register 1 or 2: non-posted memory base register (read/write, bit 15-0; offset 70h) this register defines the base address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. upper twelve bits corresponding to address bits [31:20] are read/write. lower 20 bits (19:0) are assumed to be 00000h. 13.2.42 config register 1 or 2: non-posted memory limit register (read/write, bit 31-16; offset 70h) this register defines the upper limit address of the non-posted memory-mapped address range for forwarding the cycle through the bridge. upper twelve bits corresponding to address bits [31:20] are read/write. lower 20 bits (19:0) are assumed to be fffffh. t i bn o i t c n u fe p y tn o i t p i r c s e d 3 1 - 5 1d e v r e s e ro / r ' 0 0 0 ' o t t e s e r 2 1 d a e r e r p y r a m i r p w / r y r a m i r p n o d n a m m o c r m e m r o f d a e r e r o m 1 e l b a n e e l b a n e = 1 e g n a h c o n = 0 0 1 - 1 1d e v r e s e ro / r ' 0 0 ' o t t e s e r 9 t s e u q e r g n o l e l b a n e w / r e l c y c k c o l r o f t s e u q e r g n o l e l b a n e e g n a h c o n = 0 e l b a n e = 1 8 e u e u q t d t e s e r w / r e u e u q n o i t c a s n a r t d e y a l e d y r a d n o c e s t e s e r e g n a h c o n = 0 t e s e r = 1 6 - 7d e v r e s e ro / r' 0 0 ' o t t e s e r 5e l b a n e e t i r w d iw / rd i r o d n e v m e t s y s b u s , d i e c i v e d , d i r o d n e v o t e t i r w w o l l a . e c a p s n o i t a r u g i f n o c e h t n i d i m e t s y s b u s d n a t c e t o r p e t i r w = 0 e l b a n e e t i r w = 1 0 o t t e s e r 4w m e m y r a d n o c e s e l b a n e s a i l a d n a m m o c w / r d e t s o p - n o n g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a d n o c e s n o r o t a i t i n i m o r f e l c y c y r t e r e t i r w y r o m e m t c a x e e b o t s a h d n a m m o c = 0 i w m e m o t t n e l a v i u q e s i w m e m = 1 0 o t t e s e r 3r m e m y r a d n o c e s e l b a n e s a i l a d n a m m o c w / r d a e r y r o m e m g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a d n o c e s n o r o t a i t i n i m o r f e l c y c y r t e r t c a x e e b o t s a h d n a m m o c = 0 m r m e m r o l r m e m o t t n e l a v i u q e s i r m e m = 1 0 o t t e s e r 2w m e m y r a m i r p e l b a n e s a i l a d n a m m o c w / r d e t s o p - n o n g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a m i r p n o r o t a i t i n i m o r f e l c y c y r t e r e t i r w y r o m e m t c a x e e b o t s a h d n a m m o c = 0 i w m e m o t t n e l a v i u q e s i w m e m = 1 0 o t t e s e r 1r m e m y r a m i r p e l b a n e s a i l a d n a m m o c w / r d a e r y r o m e m g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a m i r p n o r o t a i t i n i m o r f e l c y c y r t e r t c a x e e b o t s a h d n a m m o c = 0 m r m e m r o l r m e m o t t n e l a v i u q e s i r m e m = 1 0 o t t e s e r 0y r a d n o c e s d a e r e r p w / r. y r a d n o c e s n o d n a m m o c r m e m r o f d a e r e r o m 1 e l b a n e e l b a s i d = 0 e l b a n e = 1 0 o t t e s e r 13.2.43 configuration register 1: port option register (bit 15-0; offset74h)
68 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 13.2.44 configuration register 2: port option register (bit 15-0; offset74h) t i bn o i t c n u fe p y tn o i t p i r c s e d 3 1 - 5 1d e v r e s e ro / r ' 0 0 0 ' o t t e s e r 2 1d e v r e s e rw / r 0 o t t e s e r 0 1 - 1 1d e v r e s e ro / r ' 0 0 ' o t t e s e r 8 - 9d e v r e s e rw / r ' 0 0 ' o t t e s e r 6 - 7d e v r e s e ro / r ' 0 0 ' o t t e s e r 5e l b a n e e t i r w d iw / r, d i r o d n e v m e t s y s b u s , d i e c i v e d , d i r o d n e v o t e t i r w w o l l a . e c a p s n o i t a r u g i f n o c e h t n i d i m e t s y s b u s d n a t c e t o r p e t i r w = 0 e l b a n e e t i r w = 1 0 o t t e s e r 4w m e m y r a d n o c e s d n a m m o c e l b a n e s a i l a w / rd e t s o p - n o n g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a d n o c e s n o r o t a i t i n i m o r f e l c y c y r t e r e t i r w y r o m e m t c a x e e b o t s a h d n a m m o c = 0 i w m e m o t t n e l a v i u q e s i w m e m = 1 0 o t t e s e r 3r m e m y r a d n o c e s d n a m m o c e l b a n e s a i l a w / ry r o m e m g n i h c t a m r o f m s i n a h c e m n o i t c e t e d s ' e g d i r b e h t s l o r t n o c . e c a f r e t n i y r a d n o c e s n o r o t a i t i n i m o r f e l c y c y r t e r d a e r t c a x e e b o t s a h d n a m m o c = 0 m r m e m r o l r m e m o t t n e l a v i u q e s i r m e m = 1 0 o t t e s e r 2 d e v r e s e rw / r 0 o t t e s e r 1 d e v r e s e rw / r 0 o t t e s e r 0y r a d n o c e s d a e r e r p w / r. y r a d n o c e s n o d n a m m o c r m e m r o f d a e r e r o m 1 e l b a n e e l b a s i d = 0 e l b a n e = 1 0 o t t e s e r
69 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information 13.2.45 config register 1 or 2: master timeout counter register (read/write, bit 31-16; offset 74h) this register holds the maximum number of pci clocks that pi7c7100 will wait for initiator to retry the same cycle before reporting timeout. default is 8000h. 13.2.46 config register 1 or 2: retry counter register (read/write, bit 31-0; offset 78h) this register holds the maximum number of attempts that pi7c7100 will try before reporting retry timeout. default is 0100_0000h. 13.2.47 config register 1 or 2: sampling timer register (read/write, bit 31-0; offset 7ch) this register set the duration (in pci clocks) during which pi7c7100 will record the number of successful transactions for performance evaluation. the recording will start right after this register is programmed and will be cleared after the timer expires. the maximum period is 128 seconds. reset to 0000_0000h. 13.2.48 config register 1 or 2: successful i/o read count register (read/write, bit 31-0; offset 80h) this register stores the successful i/o read count on the secondary interface which will be updated when the sam- pling timer is active. reset to 0000_0000h. 13.2.49 config register 1 or 2: successful i/o write count register (read/write, bit 31-0; offset 84h) this register stores the successful i/o write count on the secondary interface which will be updated when the sam- pling timer is active. reset to 0000_0000h. 1 3.2.50 config register 1 or 2: successful memory read count register (read/write, bit 31-0; offset 88h) this register stores the successful memory read count on the secondary interface which will be updated when the sampling timer is active. reset to 0000_0000h. 13.2.51 config register 1 or 2: successful memory write count register (read/write, bit 31-0; offset 8ch) this register stores the successful memory write count on the secondary interface which will be updated when the sampling timer is active. reset to 0000_0000h. 13.2.52 config register 1: primary successful i/o read count register (read/write, bit 31-0; offset 90h) this register stores the successful i/o read count on the primary interface which will be updated when the sampling timer is active. reset to 0000_0000h. 13.2.53 config register 1: primary successful i/o write count register (read/write, bit 31-0; offset 94h) this register stores the successful i/o write count on the primary interface which will be updated when the sampling timer is active. reset to 0000_0000h. 13.2.54 config register 1: primary successful memory read count register (read/write, bit 31-0; offset 98h) this register stores the successful memory read count on the primary interface which will be updated when the sampling timer is active. reset to 0000_0000h. 13.2.55 config register 1: primary successful memory write count register (read/write, bit 31-0; offset 9ch) this register stores the successful memory write count on the primary interface which will be updated when the sampling timer is active. reset to 0000_0000h.
70 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information a target then has up to three cycles to respond before subtractive decoding is initiated. if the target detects an address hit, it should assert its devsel# signal in the cycle corresponding to the values of bits 9 and 10 in the configuration status register. termination of a pci cycle can occur in a number of ways. normal termination begins by the initiator (master) de-asserting frame# with irdy# being asserted (or remaining asserted) on the same cycle. the cycle completes when trdy# and irdy# are both asserted simultaneously. the target should de-assert trdy# for one cycle following final assertion (sustained 3-state signal). 14.2 transaction ordering to maintain data coherency and consistency, pi7c7100 complies with the ordering rules put forth in the pci local bus specification, rev 2.1. the following table summarizes the ordering relationship of all the transactions through the bridge. pmw - posted write (either memory write or memory write & invalidate) drr - delayed read request (all memory read, i/o read & configuration read) dwr - delayed write request (i/o write & configuration write) drc - delayed read completion (all memory read, i/o read & configuration read) dwc - delayed write completion (i/o write & configuration write ) 14. bridge behavior a pci cycle is initiated by asserting the frame# signal. in a bridge, there are a number of possibilities. those possibilities are summarized in the table below: 14.1 bridge actions for various cycle types r o t a i t i n it e g r a te s n o p s e r y r a m i r p n o r e t s a my r a m i r p n o t e g r a t g n i d o c e d y b n o i t a u t i s s i h t s t c e t e d t i . d n o p s e r t o n s e o d 0 0 1 7 c 7 i p t s a f r e h t o r o f # l e s v e d _ p e h t g n i r o t i n o m s a l l e w s a s s e r d d a e h t . t r o p y r a m i r p e h t n o s e c i v e d m u i d e m d n a y r a m i r p n o r e t s a my r a d n o c e s n o t e g r a t t i f i y l l a m r o n e l c y c e h t s e t a n i m r e t , # l e s v e d _ p s t r e s s a 0 0 1 7 c 7 i p s e s s a p n e h t t i . y r t e r a h t i w s n r u t e r e s i w r e h t o , d e t s o p e b o t e l b a s i e h t n o e t e l p m o c s i e l c y c e h t n e h w . t r o p e t a i r p o r p p a e h t o t e l c y c e h t d n a e l c y c e m a s e h t t a e p e r o t r o t a i t i n i e h t r o f t i a w l l i w t i , t r o p t e g r a t . n o i t a n i m r e t l a m r o n h t i w d n e y r a m i r p n o r e t s a my r a m i r p n o t o n t e g r a t t r o p y r a d n o c e s r o n r e t s a m s a e t a n i m r e t l l i w e l c y c e h t d n a d n o p s e r t o n s e o d 0 0 1 7 c 7 i p . t r o b a y r a d n o c e s n o r e t s a me m a s e h t n o t e g r a t t r o p y r a d n o c e s . d n o p s e r t o n s e o d 0 0 1 7 c 7 i p y r a d n o c e s n o r e t s a mr o y r a m i r p n o t e g r a t t r o p y r a d n o c e s r e h t o e h t e h t s e t a n i m r e t , # l e s v e d _ 2 s r o # l e s v e d _ 1 s s t r e s s a 0 0 1 7 c 7 i p a h t i w s n r u t e r e s i w r e h t o , d e t s o p e b o t e l b a s i t i f i y l l a m r o n e l c y c s i e l c y c n e h w . t r o p e t a i r p o r p p a e h t o t e l c y c e h t s e s s a p n e h t t i . y r t e r e h t t a e p e r o t r o t a i t i n i e h t r o f t i a w l l i w t i , t r o p t e g r a t e h t n o e t e l p m o c . n o i t a n i m r e t l a m r o n h t i w d n e d n a e l c y c e m a s y r a d n o c e s n o r e t s a my r a m i r p n o t o n t e g r a t y r a d n o c e s r e h t o e h t r o n . d n o p s e r t o n s e o d 0 0 1 7 c 7 i p
71 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information cycle type shown on each row is the subsequent cycle after the previous shown on the column. ? n m u l o c s s a p w o r n a c w m p 1 n m u l o c r r d 2 n m u l o c r w d 3 n m u l o c c r d 4 n m u l o c c w d 5 n m u l o c ) 1 w o r ( w m po ns e ys e ys e ys e y ) 2 w o r ( r r do no no ns e ys e y ) 3 w o r ( r w do no no ns e ys e y ) 4 w o r ( c r do ns e ys e yo no n ) 5 w o r ( c w ds e ys e ys e yo no n in row 1 column 1, pmw cannot pass the previous pmw and that means they must complete on the target bus in the order in which they were received in the initiator bus. in row 2 column 1, drr cannot pass the previous pmw and that means the previous pmw heading to the same direction must be completed before the drr can be attempted on the target bus. in row 1 column 2, pmw can pass the previous drr as long as the drr reaches the head of the delayed transaction queue. 14.3 abnormal termination (initiated by bridge master) 14.3.1 master abort master abort indicates that when pi7c7100 acts as a master and receives no response (i.e., no target asserts p_devsel# or s1_devsel# or s2_devsel#) from a target, the bridge de-asserts frame# and then de-asserts irdy#. 14.3.2 parity and error reporting parity must be checked for all addresses and write data. parity is defined on the p_par, s1_par, and s2_par signals. parity should be even (i.e. an even number of 1s) across ad, cbe, and par. parity information on par is valid the cycle after ad and cbe are valid. for reads, even parity must be generated using the initiators cbe signals combined with the read data. again, the par signal corresponds to read data from the previous data phase cycle. 14.3.3 reporting parity errors for all address phases, if a parity error is detected, the error should be reported on the p_serr# signal by asserting p_serr# for one cycle and then 3-stating two cycles after the bad address. p_serr# can only be asserted if bit 6 and 8 in the command register are both set to 1. for write data phases, a parity error should be reported by asserting the p_perr# signal two cycles after the data phase and should remain asserted for one cycle when bit 8 in the command register is set to a 1. the target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. detection of an address parity error will cause the pci-to-pci bridge target to not claim the bus (p_devsel# remains inactive) and the cycle will then terminate with a master abort. when the bridge is acting as master, a data parity error during a read cycle results in the bridge master initiating a master abort. 14.3.4 secondary idsel mapping when pi7c7100 detects a type 1 configuration transaction for a device connected to the secondary, it translates the type 1 transaction to type 0 transaction on the downstream interface. type 1 configuration format uses a 5-bit field at p_ad[15:11] as a device number. this is translated to s1_ad[31:16] or s2_ad[31:16] by pi7c7100.
72 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 15. ieee 1149.1 compatible jtag controller an ieee 1149.1 compatible test access port (tap) controller and associated tap pins are provided to support boundary scan in pi7c7100 for board-level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst#. all digital input, output, input/output pins are tested except tap pins and clock pin. the ieee 1149.1 test logic consists of a tap controller, an instruction register, and a group of test data registers including bypass, device identification and boundary scan registers. the tap controller is a synchronous 16 state machine driven by the test clock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the machine is in test_logic_reset state at power-up. the jtag signal lines are not active when the pci resource is operating pci bus cycles. pi7c7100 implements 3 basic instructions: bypass, sample/preload, extest. 15.1 boundary scan architecture boundary-scan test logic consists of a boundary-scan register and support logic. these are accessed through a test access port (tap). the tap provides a simple serial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. this mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. the following subsections describe the boundary-scan test logic elements: tap pins, instruction register, test data registers and tap controller. figure 15-1 illustrates how these pieces fit together to form the jtag unit. 15.1.1 tap pins the pi7c7100s tap pins form a serial port composed of four input connections (tms, tck, trst# and tdi) and one output connection (tdo). these pins are described in table 15-1. the tap pins provide access to the instruction register and the test data registers. 15.1.2 instruction register the instruction register (ir) holds instruction codes. these codes are shifted in through the test data input (tdi) pin. the instruction codes are used to select the specific test operation to be performed and the test data register to be accessed. the instruction register is a parallel-loadable, master/slave-configured 2-bit wide, serial-shift register with latched outputs . data is shifted into and out of the ir serially through the tdi pin clocked by the rising edge of tck. the shifted-in instructi on becomes active upon latching from the master stage to the slave stage. at that time the ir outputs along with the tap finite state machine outputs are decoded to select and control the test data register selected by that instruction. upon latching, all actions caused by any previous instructions terminate. boundary-scan register control and clock signals ta p controller instruction register bypass register tdo tdi tms tck trst# tap pins pi7c7100 system pins figure 15-1. test access port block diagram
73 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information the instruction determines the test to be performed, the test data register to be accessed, or both. the ir is two bits wide. when the ir is selected, the most significant bit is connected to tdi, and the least significant bit is connected to tdo. the value presented on the tdi pin is shifted into the ir on each rising edge of tck. the tap controller captures fixed parallel data (01 binary ). when a new instruction is shifted in through tdi, the value 01 (binary) is always shifted out throu gh tdo, least significant bit first. this helps identify instructions in a long chain of serial data from several devices. upon activation of the trst# reset pin, the latched instruction asynchronously changes to the idcode instruction. when the tap controller moves into the test state other than by reset activation, the opcode changes as tdi shifts, and becomes active on the falling edge of tck. 15.2 boundary-scan instruction set the pi7c7100 supports three mandatory boundary-scan instructions (bypass, sample/preload and extest). the table shown below lists the pi7c7100s boundary-scan instruction codes. the reserved code should not be used. e d o c n o i t c u r t s n i ) y r a n i b ( e m a n n o i t c u r t s n ie d o c n o i t c u r t s n i ) y r a n i b ( e m a n n o i t c u r t s n i 0 0t s e t x e0 1d e v r e s e r 1 0d a o l e r p / e l p m a s1 1s s a p y b / n o i t c u r t s n i e t i s i u q e r e d o c p o ) y r a n i b (n o i t p i r c s e d t s e t x e 1 . 9 4 1 1 e e e i d e r i u q e r 0 0 f f o d n a s t c e n n o c r e t n i l e v e l - d r a o b y l l a c i p y t , y r t i u c r i c l a n r e t x e f o g n i t s e t s e t a i t i n i t s e t x e . o d t d n a i d t n e e w t e b r e t s i g e r n a c s - y r a d n u o b e h t s t c e n n o c t s e t x e . y r t i u c r i c p i h c o t n i d e t f i h s s e u l a v y b n e v i r d e r a s e u l a v n i p l a n g i s t u p t u o l l a , d e t c e l e s s i t s e t x e n e h w , o s l a . k c t f o e g d e g n i l l a f e h t n o y l n o e g n a h c y a m d n a r e t s i g e r n a c s - y r a d n u o b e h t e h t o t n i d e d a o l e b t s u m s e t a t s n i p t u p n i m e t s y s l l a , d e t c e l e s s i t s e t x e n e h w . k c t f o e g d e - g n i s i r e h t n o r e t s i g e r n a c s - y r a d n u o b / e l p m a s d a o l e r p 1 . 9 4 1 1 e e e i d e r i u q e r 1 0: s n o i t c n u f o w t s m r o f r e p d a o l e r p / e l p m a s t u o h t i w k c t f o e g d e g n i s i r e h t n o d e r u t p a c s i n o i t c u r t s n i e l p m a s e h t f o t o h s p a n s a r e t s i g e r n a c s - y r a d n u o b s e s u a c n o i t c u r t s n i e h t . n o i t a r e p o l a m r o n h t i w g n i r e f r e t n i . n e v i r d g n i e b e u l a v e h t e l p m a s o t s t u p t u o h t i w d e t a i c o s s a s l l e c d e r r e f s n a r t s i s l l e c n a c s - y r a d n u o b e h t n i d l e h a t a d e h t k c t f o e g d e g n i l l a f e h t n o ? m e t s y s e h t o t d e i l p p a s i a t a d d e h c t a l e v a l s e h t y l l a c i p y t . s l l e c r e t s i g e r e v a l s e h t o t . n o i t c u r t s n i t s e t x e e h t a i v s t u p t u o e d o c d i 1 . 9 4 1 1 e e e i l a n o i t p o 0 1d e v r e s e r s s a p y b 1 . 9 4 1 1 e e e i d e r i u q e r 1 1 0 . s n i p o d t d n a i d t n e e w t e b r e t s i g e r s s a p y b t i b - e n o e h t s t c e l e s n o i t c u r t s n i s s a p y b s i h t e l i h w . r e t s i g e r s s a p y b e h t s e s s e c c a t a h t n o i t c u r t s n i y l n o e h t s i ) y r a n i b ( m e t s y s n o t c e f f e o n e v a h s r e t s i g e r a t a d t s e t r e h t o l l a , t c e f f e n i s i n o i t c u r t s n i r i e h t m r o f r e p y t i l a n o i t c n u f m e t s y s d n a t s e t h t o b h t i w s r e t s i g e r a t a d t s e t . n o i t a r e p o . d e t c e l e s s i n o i t c u r t s n i s i h t n e h w s n o i t c n u f m e t s y s table 15-1. tap pins
74 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information 15.3 tap test data registers the pi7c7100 contains two test data registers (bypass and boundary-scan). each test data register selected by the tap controller is connected serially between tdi and tdo. tdi is connected to the test data registers most significant bit. tdo is connected to the least significant bit. data is shifted one bit position within the register towards tdo on each rising edge of tck. while any register is selected, data is transferred from tdi to tdo without inversion. the following sections describe each of the test data registers. 15.4 bypass register the required bypass register, a one-bit shift register, provides the shortest path between tdi and tdo when a bypass instruction is in effect. this allows rapid movement of test data to and from other components on the board. this path can be selected when no test operation is being performed on the pi7c7100. 15.5 boundary-scan register the boundary-scan register contains a cell for each pin as well as control cells for i/o and the high-impedance pin. table 15-2 shows the bit order of the pi7c7100 boundary-scan register. all table cells that contain control select the direction of bidirectional pins or high-impedance output pins. when a 0 is loaded into the control cell, the associated pin(s) are high-impedance or selected as input. the boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the pi7c7100s pins and on-chip system logic. the vdd, gnd, pll, agnd, avdd and jtag pins are not in the boundary-scan chain. the boundary-scan register cells are dedicated logic and do not have any system function. data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample/ preload and extest instructions. parallel loading takes place on the rising edge of tck. data may be scanned into the boundary-scan register serially via the tdi serial input pin, clocked by the rising edge of tck. when the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of tck state. data may also be shifted out of the boundary-scan register by means of the tdo serial output pin at the falling edge of tck. 15.6 tap controller the tap (test access port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. the tap can be controlled via a bus master. the bus master can be either automatic test equipment or a component (i.e., pld) that interfaces to the tap. the tap controller changes state only in response to a rising edge of tck. the value of the test mode state (tms) input signal at a rising edge of tck controls the sequence of state changes. the tap controller is initialized after power-up by applying a low to the trst# pin. in addition, the tap controller can be initialized by applying a high signal level on the tms input for a minimum of five tck periods. for greater detail on the behavior of the tap controller, test logic in each controller state and the state machine and public instructions, refer to the ieee 1149.1 standard test access port and boundary-scan architecture document (available from the ieee).
75 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information r e d r os e m a n n i pe p y t 1] 1 3 - 0 2 [ d a _ 2 se l b a n e l o r t n o c 2] 1 2 [ d a _ 2 st u p t u o 3] 1 2 [ d a _ 2 st u p n i 4# r r e p _ 2 se l b a n e l o r t n o c 5# r r e p _ 2 st u p t u o 6# r r e p _ 2 st u p n i 7] 9 1 - 8 [ d a _ 2 se l b a n e l o r t n o c 8] 6 1 [ d a _ 2 st u p t u o 9] 6 1 [ d a _ 2 st u p n i 0 1# e m a r f _ 2 se l b a n e l o r t n o c 1 1# e m a r f _ 2 st u p t u o 2 1# e m a r f _ 2 st u p n i 3 1# y d r t _ 2 s / # l e s v e d _ 2 se l b a n e l o r t n o c 4 1# l e s v e d _ 2 st u p t u o 5 1# l e s v e d _ 2 st u p n i 6 1] 9 1 [ d a _ 2 st u p t u o 7 1] 9 1 [ d a _ 2 st u p n i 8 1] 7 1 [ d a _ 2 st u p t u o 9 1] 7 1 [ d a _ 2 st u p n i 0 2] 8 1 [ d a _ 2 st u p t u o 1 2] 8 1 [ d a _ 2 st u p n i 2 2] 0 2 [ d a _ 2 st u p t u o 3 2] 0 2 [ d a _ 2 st u p n i 4 2] 2 2 [ d a _ 2 st u p t u o 5 2] 2 2 [ d a _ 2 st u p n i 6 2] 4 2 [ d a _ 2 st u p t u o 7 2] 4 2 [ d a _ 2 st u p n i 8 2] 3 2 [ d a _ 2 st u p t u o 9 2] 3 2 [ d a _ 2 st u p n i 0 3] 3 - 0 [ e b c _ 2 se l b a n e l o r t n o c 1 3] 3 [ e b c _ 2 st u p t u o 2 3] 3 [ e b c _ 2 st u p n i 3 3] 5 2 [ d a _ 2 st u p t u o 4 3] 5 2 [ d a _ 2 st u p n i 5 3] 6 2 [ d a _ 2 st u p t u o r e d r os e m a n n i pe p y t 6 3] 6 2 [ d a _ 2 st u p n i 7 3] 8 2 [ d a _ 2 st u p t u o 8 3] 8 2 [ d a _ 2 st u p n i 9 3] 7 2 [ d a _ 2 st u p t u o 0 4] 7 2 [ d a _ 2 st u p n i 1 4] 9 2 [ d a _ 2 st u p t u o 2 4] 9 2 [ d a _ 2 st u p n i 3 4] 0 3 [ d a _ 2 st u p t u o 4 4] 0 3 [ d a _ 2 st u p n i 5 4] 1 3 [ d a _ 2 st u p t u o 6 4] 1 3 [ d a _ 2 st u p n i 7 4# ] 0 [ t n g _ 2 se l b a n e l o r t n o c 8 4# ] 0 [ t n g _ 2 st u p t u o 9 4# ] 0 [ q e r _ 2 st u p n i 0 5# ] 1 [ q e r _ 2 st u p n i 1 5# ] 1 [ t n g _ 2 st u p t u o 2 5# ] 2 [ t n g _ 2 st u p t u o 3 5# ] 2 [ q e r _ 2 st u p n i 4 5# ] 3 [ q e r _ 2 st u p n i 5 5# ] 3 [ t n g _ 2 st u p t u o 6 5# ] 4 [ t n g _ 2 st u p t u o 7 5# ] 4 [ q e r _ 2 st u p n i 8 5# ] 5 [ q e r _ 2 st u p n i 9 5# ] 5 [ t n g _ 2 st u p t u o 0 6# ] 6 [ t n g _ 2 st u p t u o 1 6# ] 6 [ q e r _ 2 st u p n i 2 6# ] 7 [ q e r _ 2 st u p n i 3 6# ] 7 [ t n g _ 2 st u p t u o 4 6# t e s e r _ 2 st u p t u o 5 6# n f c _ st u p n i 6 6# n e _ 1 st u p n i 7 6# n e _ 2 st u p n i 8 6# m t _ n a c st u p n i 9 6n e _ n a c st u p n i 0 7m t _ l l pt u p n i r e d r os e m a n n i pe p y t 1 7s s a p y bt u p n i 2 7# h s u l ft u p n i 3 7# t e s e r _ pt u p n i 4 7# t n g _ pt u p n i 5 7# q e r _ pe l b a n e l o r t n o c 6 7# q e r _ pt u p t u o 7 7] 1 3 - 0 2 [ d a _ pe l b a n e l o r t n o c 8 7] 0 3 [ d a _ pt u p t u o 9 7] 0 3 [ d a _ pt u p n i 0 8] 1 3 [ d a _ pt u p t u o 1 8] 1 3 [ d a _ pt u p n i 2 8] 7 2 [ d a _ pt u p t u o 3 8] 7 2 [ d a _ pt u p n i 4 8] 6 2 [ d a _ pt u p t u o 5 8] 6 2 [ d a _ pt u p n i 6 8] 8 2 [ d a _ pt u p t u o 7 8] 8 2 [ d a _ pt u p n i 8 8] 9 2 [ d a _ pt u p t u o 9 8] 9 2 [ d a _ pt u p n i 0 9] 3 - 0 [ e b c _ pe l b a n e l o r t n o c 1 9] 3 [ e b c _ pt u p t u o 2 9] 3 [ e b c _ pt u p n i 3 9] 4 2 [ d a _ pt u p t u o 4 9] 4 2 [ d a _ pt u p n i 5 9] 5 2 [ d a _ pt u p t u o 6 9] 5 2 [ d a _ pt u p n i 7 9] 3 2 [ d a _ pt u p t u o 8 9] 3 2 [ d a _ pt u p n i 9 9] 2 2 [ d a _ pt u p t u o 0 0 1] 2 2 [ d a _ pt u p n i 1 0 1l e s d i _ pt u p n i 2 0 1] 1 2 [ d a _ pt u p t u o 3 0 1] 1 2 [ d a _ pt u p n i 4 0 1] 0 2 [ d a _ pt u p t u o 5 0 1] 0 2 [ d a _ pt u p n i table 15-2. jtag boundary register order
76 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information r e d r os e m a n n i pe p y t 6 0 1] 9 1 - 8 [ d a _ pe l b a n e l o r t n o c 7 0 1] 9 1 [ d a _ pt u p t u o 8 0 1] 9 1 [ d a _ pt u p n i 9 0 1] 8 1 [ d a _ pt u p t u o 0 1 1] 8 1 [ d a _ pt u p n i 1 1 1] 7 1 [ d a _ pt u p t u o 2 1 1] 7 1 [ d a _ pt u p n i 3 1 1] 6 1 [ d a _ pt u p t u o 4 1 1] 6 1 [ d a _ pt u p n i 5 1 1] 2 [ e b c _ pt u p t u o 6 1 1] 2 [ e b c _ pt u p n i 7 1 1# e m a r f _ pe l b a n e l o r t n o c 8 1 1# e m a r f _ pt u p t u o 9 1 1# e m a r f _ pt u p n i 0 2 1# y d r i _ pe l b a n e l o r t n o c 1 2 1# y d r i _ pt u p t u o 2 2 1# y d r i _ pt u p n i 3 2 1# y d r t _ p / l e s v e d _ pe l b a n e l o r t n o c 4 2 1# y d r t _ pt u p t u o 5 2 1# y d r t _ pt u p n i 6 2 1# l e s v e d _ pt u p t u o 7 2 1# l e s v e d _ pt u p n i 8 2 1# p o t s _ pe l b a n e l o r t n o c 9 2 1# p o t s _ pt u p t u o 0 3 1# p o t s _ pt u p n i 1 3 1# r r e p _ pe l b a n e l o r t n o c 2 3 1# r r e p _ pt u p t u o 3 3 1# r r e p _ pt u p n i 4 3 1# k c o l _ pe l b a n e l o r t n o c 5 3 1# k c o l _ pt u p t u o 6 3 1# k c o l _ pt u p n i 7 3 1# r r e s _ pe l b a n e l o r t n o c 8 3 1# r r e s _ pt u p t u o 9 3 1] 3 1 [ d a _ pt u p t u o 0 4 1] 3 1 [ d a _ pt u p n i r e d r os e m a n n i pe p y t 1 4 1] 4 1 [ d a _ pt u p t u o 2 4 1] 4 1 [ d a _ pt u p n i 3 4 1] 1 1 [ d a _ pt u p t u o 4 4 1] 1 1 [ d a _ pt u p n i 5 4 1] 5 1 [ d a _ pt u p t u o 6 4 1] 5 1 [ d a _ pt u p n i 7 4 1] 2 1 [ d a _ pt u p t u o 8 4 1] 2 1 [ d a _ pt u p n i 9 4 1] 8 [ d a _ pt u p t u o 0 5 1] 8 [ d a _ pt u p n i 1 5 1] 1 [ e b c _ pt u p t u o 2 5 1] 1 [ e b c _ pt u p n i 3 5 1] 9 [ d a _ pt u p t u o 4 5 1] 9 [ d a _ pt u p n i 5 5 1] 7 - 0 [ d a _ pe l b a n e l o r t n o c 6 5 1] 5 [ d a _ pt u p t u o 7 5 1] 5 [ d a _ pt u p n i 8 5 1n e 6 6 m _ pt u p n i 9 5 1] 6 [ d a _ pt u p t u o 0 6 1] 6 [ d a _ pt u p n i 1 6 1] 2 [ d a _ pt u p t u o 2 6 1] 2 [ d a _ pt u p n i 3 6 1r a p _ pe l b a n e l o r t n o c 4 6 1r a p _ pt u p t u o 5 6 1r a p _ pt u p n i 6 6 1] 0 [ d a _ pt u p t u o 7 6 1] 0 [ d a _ pt u p n i 8 6 1] 0 [ e b c _ pt u p t u o 9 6 1] 0 [ e b c _ pt u p n i 0 7 1] 7 [ d a _ pt u p t u o 1 7 1] 7 [ d a _ pt u p n i 2 7 1] 0 1 [ d a _ pt u p t u o 3 7 1] 0 1 [ d a _ pt u p n i 4 7 1] 1 [ d a _ pt u p t u o 5 7 1] 1 [ d a _ pt u p n i r e d r os e m a n n i pe p y t 6 7 1] 3 [ d a _ pt u p t u o 7 7 1] 3 [ d a _ pt u p n i 8 7 1] 4 [ d a _ pt u p t u o 9 7 1] 4 [ d a _ pt u p n i 0 8 1] 7 - 0 [ d a _ 1 se l b a n e l o r t n o c 1 8 1] 0 [ d a _ 1 st u p t u o 2 8 1] 0 [ d a _ 1 st u p n i 3 8 1] 1 [ d a _ 1 st u p t u o 4 8 1] 1 [ d a _ 1 st u p n i 5 8 1] 2 [ d a _ 1 st u p t u o 6 8 1] 2 [ d a _ 1 st u p n i 7 8 1] 5 [ d a _ 1 st u p t u o 8 8 1] 5 [ d a _ 1 st u p n i 9 8 1] 3 [ d a _ 1 st u p t u o 0 9 1] 3 [ d a _ 1 st u p n i 1 9 1] 4 [ d a _ 1 st u p t u o 2 9 1] 4 [ d a _ 1 st u p n i 3 9 1] 3 - 0 [ e b c _ 1 se l b a n e l o r t n o c 4 9 1] 0 [ e b c _ 1 st u p t u o 5 9 1] 0 [ e b c _ 1 st u p n i 6 9 1] 7 [ d a _ 1 st u p t u o 7 9 1] 7 [ d a _ 1 st u p n i 8 9 1] 6 [ d a _ 1 st u p t u o 9 9 1] 6 [ d a _ 1 st u p n i 0 0 2] 9 1 - 8 [ d a _ 1 se l b a n e l o r t n o c 1 0 2] 8 [ d a _ 1 st u p t u o 2 0 2] 8 [ d a _ 1 st u p n i 3 0 2] 9 [ d a _ 1 st u p t u o 4 0 2] 9 [ d a _ 1 st u p n i 5 0 2] 0 1 [ d a _ 1 st u p t u o 6 0 2] 0 1 [ d a _ 1 st u p n i 7 0 2] 1 1 [ d a _ 1 st u p t u o 8 0 2] 1 1 [ d a _ 1 st u p n i 9 0 2] 2 1 [ d a _ 1 st u p t u o 0 1 2] 2 1 [ d a _ 1 st u p n i table 15-2. jtag boundary register order (continued)
77 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information r e d r os e m a n n i pe p y t 1 1 2] 4 1 [ d a _ 1 st u p t u o 2 1 2] 4 1 [ d a _ 1 st u p n i 3 1 2] 3 1 [ d a _ 1 st u p t u o 4 1 2] 3 1 [ d a _ 1 st u p n i 5 1 2] 5 1 [ d a _ 1 st u p t u o 6 1 2] 5 1 [ d a _ 1 st u p n i 7 1 2# r r e s _ 1 st u p n i 8 1 2r a p _ 1 se l b a n e l o r t n o c 9 1 2r a p _ 1 st u p t u o 0 2 2r a p _ 1 st u p n i 1 2 2] 1 [ e b c _ 1 st u p t u o 2 2 2] 1 [ e b c _ 1 st u p n i 3 2 2# y d r t _ 1 s / # l e s v e d _ 1 se l b a n e l o r t n o c 4 2 2# l e s v e d _ 1 st u p t u o 5 2 2# l e s v e d _ 1 st u p n i 6 2 2# p o t s _ 1 se l b a n e l o r t n o c 7 2 2# p o t s _ 1 st u p t u o 8 2 2# p o t s _ 1 st u p n i 9 2 2# k c o l _ 1 se l b a n e l o r t n o c 0 3 2# k c o l _ 1 st u p t u o 1 3 2# k c o l _ 1 st u p n i 2 3 2# r r e p _ 1 se l b a n e l o r t n o c 3 3 2# r r e p _ 1 st u p t u o 4 3 2# r r e p _ 1 st u p n i 5 3 2# e m a r f _ 1 se l b a n e l o r t n o c 6 3 2# e m a r f _ 1 st u p t u o 7 3 2# e m a r f _ 1 st u p n i 8 3 2# y d r i _ 1 se l b a n e l o r t n o c 9 3 2# y d r i _ 1 st u p t u o 0 4 2# y d r i _ 1 st u p n i 1 4 2# y d r t _ 1 st u p t u o 2 4 2# y d r t _ 1 st u p n i 3 4 2# ] 7 1 [ d a _ 1 st u p t u o 4 4 2# ] 7 1 [ d a _ 1 st u p n i 5 4 2# ] 6 1 [ d a _ 1 st u p t u o r e d r os e m a n n i pe p y t 6 4 2# ] 6 1 [ d a _ 1 st u p n i 7 4 2] 1 3 - 0 2 [ d a _ 1 se l b a n e l o r t n o c 8 4 2] 0 2 [ d a _ 1 st u p t u o 9 4 2] 0 2 [ d a _ 1 st u p n i 0 5 2] 2 [ e b c _ 1 st u p t u o 1 5 2] 2 [ e b c _ 1 st u p n i 2 5 2] 9 1 [ d a _ 1 st u p t u o 3 5 2] 9 1 [ d a _ 1 st u p n i 4 5 2] 3 [ e b c _ 1 st u p t u o 5 5 2] 3 [ e b c _ 1 st u p n i 6 5 2] 3 2 [ d a _ 1 st u p t u o 7 5 2] 3 2 [ d a _ 1 st u p n i 8 5 2] 6 2 [ d a _ 1 st u p t u o 9 5 2] 6 2 [ d a _ 1 st u p n i 0 6 2] 2 2 [ d a _ 1 st u p t u o 1 6 2] 2 2 [ d a _ 1 st u p n i 2 6 2] 5 2 [ d a _ 1 st u p t u o 3 6 2] 5 2 [ d a _ 1 st u p n i 4 6 2] 9 2 [ d a _ 1 st u p t u o 5 6 2] 9 2 [ d a _ 1 st u p n i 6 6 2] 1 2 [ d a _ 1 st u p t u o 7 6 2] 1 2 [ d a _ 1 st u p n i 8 6 2] 8 2 [ d a _ 1 st u p t u o 9 6 2] 8 2 [ d a _ 1 st u p n i 0 7 2] 0 3 [ d a _ 1 st u p t u o 1 7 2] 0 3 [ d a _ 1 st u p n i 2 7 2] 1 3 [ d a _ 1 st u p t u o 3 7 2] 1 3 [ d a _ 1 st u p n i 4 7 2] 7 2 [ d a _ 1 st u p t u o 5 7 2] 7 2 [ d a _ 1 st u p n i 6 7 2] 4 2 [ d a _ 1 st u p t u o 7 7 2] 4 2 [ d a _ 1 st u p n i 8 7 2] 8 1 [ d a _ 1 st u p t u o 9 7 2] 8 1 [ d a _ 1 st u p n i 0 8 2# ] 0 [ t n g _ 1 se l b a n e l o r t n o c r e d r os e m a n n i pe p y t 1 8 2# ] 0 [ t n g _ 1 st u p t u o 2 8 2# ] 0 [ q e r _ 1 st u p n i 3 8 2# ] 1 [ q e r _ 1 st u p n i 4 8 2# ] 1 [ t n g _ 1 st u p t u o 5 8 2# ] 2 [ t n g _ 1 st u p t u o 6 8 2# ] 2 [ q e r _ 1 st u p n i 7 8 2# ] 3 [ q e r _ 1 st u p n i 8 8 2# ] 3 [ t n g _ 1 st u p t u o 9 8 2# ] 4 [ t n g _ 1 st u p t u o 0 9 2# ] 4 [ q e r _ 1 st u p n i 1 9 2# ] 5 [ q e r _ 1 st u p n i 2 9 2# ] 5 [ t n g _ 1 st u p t u o 3 9 2# ] 6 [ t n g _ 1 st u p t u o 4 9 2# ] 6 [ q e r _ 1 st u p n i 5 9 2# ] 7 [ q e r _ 1 st u p n i 6 9 2# ] 7 [ t n g _ 1 st u p t u o 7 9 2# t e s e r _ 1 st u p t u o 8 9 2] 7 - 0 [ d a _ 2 se l b a n e l o r t n o c 9 9 2] 0 [ d a _ 2 st u p t u o 0 0 3] 0 [ d a _ 2 st u p n i 1 0 3] 1 [ d a _ 2 st u p t u o 2 0 3] 1 [ d a _ 2 st u p n i 3 0 3] 2 [ d a _ 2 st u p t u o 4 0 3] 2 [ d a _ 2 st u p n i 5 0 3] 3 [ d a _ 2 st u p t u o 6 0 3] 3 [ d a _ 2 st u p n i 7 0 3] 4 [ d a _ 2 st u p t u o 8 0 3] 4 [ d a _ 2 st u p n i 9 0 3] 5 [ d a _ 2 st u p t u o 0 1 3] 5 [ d a _ 2 st u p n i 1 1 3] 6 [ d a _ 2 st u p t u o 2 1 3] 6 [ d a _ 2 st u p n i 3 1 3] 7 [ d a _ 2 st u p t u o 4 1 3] 7 [ d a _ 2 st u p n i 5 1 3] 0 [ e b c _ 2 st u p t u o table 15-2. jtag boundary register order (continued)
78 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information r e d r os e m a n n i pe p y t 6 1 3] 0 [ e b c _ 2 st u p n i 7 1 3] 8 [ d a _ 2 st u p t u o 8 1 3] 8 [ d a _ 2 st u p n i 9 1 3] 0 1 [ d a _ 2 st u p t u o 0 2 3] 0 1 [ d a _ 2 st u p n i 1 2 3] 9 [ d a _ 2 st u p t u o 2 2 3] 9 [ d a _ 2 st u p n i 3 2 3] 1 1 [ d a _ 2 st u p t u o 4 2 3] 1 1 [ d a _ 2 st u p n i 5 2 3n e 6 6 m _ st u p n i 6 2 3] 2 1 [ d a _ 2 st u p t u o 7 2 3] 2 1 [ d a _ 2 st u p n i 8 2 3] 4 1 [ d a _ 2 st u p t u o 9 2 3] 4 1 [ d a _ 2 st u p n i 0 3 3] 1 [ e b c _ 2 st u p t u o 1 3 3] 1 [ e b c _ 2 st u p n i 2 3 3] 5 1 [ d a _ 2 st u p t u o 3 3 3] 5 1 [ d a _ 2 st u p n i 4 3 3r a p _ 2 se l b a n e l o r t n o c r e d r os e m a n n i pe p y t 5 3 3r a p _ 2 st u p t u o 6 3 3r a p _ 2 st u p n i 7 3 3# r r e s _ 2 st u p n i 8 3 3# k c o l _ 2 se l b a n e l o r t n o c 9 3 3# k c o l _ 2 st u p t u o 0 4 3# k c o l _ 2 st u p n i 1 4 3# y d r t _ 2 st u p t u o 2 4 3# y d r t _ 2 st u p n i 3 4 3# p o t s _ 2 se l b a n e l o r t n o c 4 4 3# p o t s _ 2 st u p t u o 5 4 3# p o t s _ 2 st u p n i 6 4 3# y d r i _ 2 se l b a n e l o r t n o c 7 4 3# y d r i _ 2 st u p t u o 8 4 3# y d r i _ 2 st u p n i 9 4 3] 2 [ e b c _ 2 st u p t u o 0 5 3] 2 [ e b c _ 2 st u p n i 1 5 3] 3 1 [ d a _ 2 st u p t u o 2 5 3] 3 1 [ d a _ 2 st u p n i table 15-2. jtag boundary register order (continued)
79 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 16. electrical and timing specifications 16.1 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested). e r u t a r e p m e t e g a r o t s c 0 5 1 + o t c 5 6 C d e i l p p a r e w o p h t i w e r u t a r e p m e t t n e i b m a c 0 7 + o t c 0 v a & s t u p n i ( s l a i t n e t o p d n u o r g o t e g a t l o v y l p p u s c c v , d d ) y l n ov 6 . 3 + o t v 3 . 0 C e g a t l o v t u p n i c d v 6 . 3 + o t v 5 . 0 C 16.2 3.3v dc specifications l o b m y sr e t e m a r a pn o i t i d n o c. n i m. x a ms t i n us e t o n v , d d v a c c e g a t l o v y l p p u s36 . 3 v v h i e g a t l o v h g i h t u p n iv 5 . 0 d d v d d 5 . 0 + 3 v l i e g a t l o v w o l t u p n i5 . 0 -3 . 0v d d v h i e g a t l o v h g i h t u p n i s o m cv 7 . 0 d d v d d 5 . 0 + 1 v l i e g a t l o v w o l t u p n i s o m c5 . 0 C3 . 0v d d v u p i e g a t l o v p u - l l u p t u p n iv 7 . 0 d d 3 i l i t n e r r u c e g a k a e l t u p n iv < 0 n i v < d d 0 1 a v h o e g a t l o v h g i h t u p t u oi t u o a 0 0 5 C =v 9 . 0 d d v v l o e g a t l o v w o l t u p t u oi t u o a 0 0 5 1 =1 . 0v d d v h o e g a t l o v h g i h t u p t u o s o m ci t u o a 0 0 5 C =v d d 5 . 0 - 2 v l o e g a t l o v w o l t u p t u o s o m ci t u o a 0 0 5 1 =5 . 0 c n i e c n a t i c a p a c n i p t u p n i 0 1 f p 3 c k l c e c n a t i c a p a c n i p k l c52 1 c l e s d i e c n a t i c a p a c n i p l e s d i 8 l n i p e c n a t c u d n i n i p 0 2h n notes: 1. cmos input pins: s_cfn#, tck, tms, tdi, trst#, scan_en, scan_tm# 2. cmos output pin: tdo 3. pci pins: p_ad[31:0], p_cbe[3:0], p_par, p_frame#, p_irdy#, p_trdy#, p_devsel#, p_stop#, p_lock#, pidsel#, p_perr#, p_serr#, p_req#, p_gnt#, p_reset#, s1_ad[31:0], s2_ad[31:0], s1_cbe[3:0], s2_cbe[3:0], s1_par, s2_par, s1_frame#, s2_frame#, s1_irdy#, s2_irdy#, s1_trdy#, s2_trdy#, s1_devsel#, s2_devsel#, s1_stop#, s2_stop#, s1_lock#, s2_lock#, s1_perr#, s2_perr#, s1_serr#, s2_serr#, s1_req[7:0]#, s2_req[7:0]#, s1_gnt[7:0]#, s2_gnt[7:0], s1_reset#, s2_reset#, s1_en, s2_en, p_flush#.
80 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information l o b m y sr e t e m a r a pn o i t i d n o c. n i m. x a ms t i n u t w e k s ] 0 : 5 1 [ t u o k l c _ s g n o m a w e k s00 . 1 s n t y a l e d ] 0 : 5 1 [ t u o k l c _ s d n a k l c p n e e w t e b y a l e dd a o l f p 0 270 1 t e l c y c e m i t e l c y c ] 0 : 5 1 [ t u o k l c _ s , k l c p0 3 t h g i h e m i t h g i h ] 0 : 5 1 [ t u o k l c _ s , k l c p1 1 t w o l e m i t w o l ] 0 : 5 1 [ t u o k l c _ s , k l c p1 1 16.4 primary and secondary buses at 33 mhz clock timing l o b m y sr e t e m a r a p. n i m. x a ms t i n u t u s s l a n g i s d e s u b - k l c o t e m i t p u t e s t u p n i 3 , 2 , 1 7C s n t ) p t p ( u s t n i o p - o t - t n i o p - k l c o t e m i t p u t e s t u p n i 3 , 2 , 1 2 1 , 0 1C t h k l c m o r f e m i t d l o h l a n g i s t u p n i 2 , 1 0C t l a v s l a n g i s d e s u b - y a l e d d i l a v l a n g i s o t k l c 3 , 2 , 1 21 1 t ) p t p ( l a v t n i o p - o t - t n i o p - y a l e d d i l a v l a n g i s o t k l c 3 , 2 , 1 22 1 t n o y a l e d e v i t c a o t t a o l f 2 , 1 2C t f f o y a l e d t a o l f o t e v i t c a 2 , 1 C8 2 v test t val t on t h valid v test C 1.5v for 5v signals: 0.4 v cc for 3.3v signals valid t su input note: output clk t off t inval figure 16-1. pci signal timing measurement conditions 16.5 power consumption r e t e m a r a pl a c i p y ts t i n u n o i t p m u s n o c r e w o p0 0 6w m i , t n e r r u c y l p p u s c c 2 8 1a m 1. see figure 16-1 pci signal timing measurement conditions. 2. all primary interface signals are synchronized to p_clk. all secondary interface signals are synchronized to s_clkout. 3. point-to-point signals are p_req#, s1_req#<7:0>, s2_req#<7:0>, p_gnt#, s1_gnt#<7:0>, and s2_gnt#<7:0>. bused signals are p_ad, p_cbe#, p_par, p_perr#, p_serr#, p_frame#, p_irdy#, p_trdy#, p_lock#, p_devsel#, p_stop#, p_idsel, s1_ad, s1_cbe#, s1_par, s1_perr#, s1_serr#, s1_frame#, s1_irdy#, s1_trdy#, s1_lock#, s1_devsel#, s1_stop#, s2_ad, s2_cbe#, s3_par, s2_perr#, s2_serr#, s2_frame#, s2_irdy#, s2_trdy#, s2_lock#, s2_devsel#, and s2_stop#. 16.3 3.3v ac specifications
81 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information pin #1 corner 20 0.15 19 18 17 16 15 14 13 12 11 10 9 8 7 654 32 1 a b c d e f g h j k l m n p r t u v w y a 8.00 4 x 45 chamfer 2.33 min. / 3.50max. 27.00 0.15 ?1.0 (3x) 0.60 0.1 30 2 seating plane 1.27 1.44 bsc 24.00 0.1 256 x ?0.75 0.15 0.56 0.05 1.17 0.1 0.30 s 0.10 s s s c c b b c c a 27.00 0.15 (4x) 17. 256-pin pbga package top bottom 17.1 part number ordering information t r a pe g a k c a p - n i pe r u t a r e p m e t a n c 0 0 1 7 c 7 i pa g b p - 6 5 2c 0 7 + o t c 0 figure 17-1. 256-pin pbga package
82 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information
pi7c7100 3-port pci bridge appendix a timing diagrams
a-2 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-3 04/18/00 advance information b addr data byte enables 0 12345 6789101112 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l p_idsel 13 14 15 16 17 18 19 20 21 22 figure 2. configuration write transaction a addr data byte enables 0 12345 6789101112 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l p_idsel 13 14 15 16 17 18 19 20 21 22 figure 1. configuration read transaction addr data byte enables a a addr byte enables addr data byte enables a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l p_idsel s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l figure 3. type 1 to type 0 configuration read transaction ( p --> s )
a-4 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr data byte enables b b addr data byte enables addr data byte enables b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l p_idsel s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l figure 4. type 1 to type 0 configuration write transaction ( p --> s ) addr data addr data byte enables byte enables b 1 b addr data byte enables figure 5. upstream type 1 to special cycle transaction ( s --> p ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 23 23
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-5 04/18/00 advance information addr data byte enables b b addr data byte enables addr data byte enables 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l figure 6. downstream type 1 to special cycle transaction ( p --> s ) addr addr bytes enables b b addr addr addr data b b byte enables byte enables byte enables byte enables b addr addr addr data b b b byte enables byte enables byte enables figure 7. downstream type1 to type1 configuration read transaction ( p --> s ) 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l p_idsel s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l
a-6 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr addr b b addr addr addr b b b addr addr addr b b b byte enables data byte enables data byte enables data byte enables data byte enables data byte enables data byte enables data byte enables data figure 8. downstream type1 to type1 configuration write transaction ( p --> s ) 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l p_idsel s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 6 byte enables addr data data data data data data data data addr addr addr 6 6 6 byte enables 6 addr data data data data data data data data figure 9. upstream delayed burst memory read transaction ( s --> p ) 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 46 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 46 byte enables byte enables byte enables
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-7 04/18/00 advance information addr addr addr byte enables byte enables byte enables 6 6 6 byte enables 6 addr data data data data data data data data 6 byte enables addr data data data data data data data data figure 10. downstream delayed burst memory read transaction ( p --> s ) 0 2 4 6 8 1012 141618 2022 2426 283032 34363840424445 1 3 5 7 9 1113151719212325272931333537394143 0 2 4 6 8 1012141618202224 2628303234363840424445 1 3 5 7 9 111315 1719 21 2325 2729 3133353739 4143 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l addr data byte enables 6 6 addr byte enables addr data byte enables 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l figure 11. downstream delayed memory read transaction (p/33mhz-->s/33mhz)
a-8 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr data addr data byte enables byte enables 6 6 6 addr byte enables figure 12. downstream delayed memory read transaction (s2/33mhz-->s1/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s1_ad [31:0] s1_cbe [3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s_clkout[0] s2_ad[31:0] s2_cbe[3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s2_gnt_l s2_req_l s1_gnt_l s1_req_l 23 23 addr data addr data byte enables byte enables 6 6 6 addr byte enables figure 13. downstream delayed memory read transaction (s1/33mhz-->s2/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s2_ad [31:0] s2_cbe [3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s_clkout[0] s1_ad[31:0] s1_cbe[3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s1_gnt_l s1_req_l s2_gnt_l s2_req_l 23 23
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-9 04/18/00 advance information addr data addr data byte enables byte enables 6 6 6 addr byte enables figure 14. upstream delayed memory read transaction (s/33mhz-->p/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 23 data byte enables 7 addr data byte enables 7 addr figure 15. downstream posted memory write transaction (p/33mhz-->s/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l
a-10 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr data data byte enables byte enables 7 7 addr figure 16. downstream posted memory write transaction (s2/33mhz-->s1/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s1_ad [31:0] s1_cbe [3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s_clkout[0] s2_ad[31:0] s2_cbe[3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s2_gnt_l s2_req_l s1_gnt_l s1_req_l addr data data byte enables byte enables 7 7 addr figure 17. downstream posted memory write transaction (s1/33mhz-->s2/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s2_ad [31:0] s2_cbe [3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s_clkout[0] s1_ad[31:0] s1_cbe[3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s1_gnt_l s1_req_l s2_gnt_l s2_req_l
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-11 04/18/00 advance information addr data data byte enables byte enables 7 7 addr figure 18. upstream posted memory write transaction (s/33mhz-->p/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l data data data data data data data data data data byte enables 7 addr data data data data data data data data data data byte enables 7 addr figure 19. downstream flow-through posted memory write transaction (p/33mhz-->s/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l
a-12 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr data data data data data data data data data data data data data data data data data data data data byte enables byte enables 7 7 addr figure 20. downstream flow-through posted memory write transaction (s2/33mhz-->s1/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s1_ad [31:0] s1_cbe [3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s_clkout[0] s2_ad[31:0] s2_cbe[3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s2_gnt_l s2_req_l s1_gnt_l s1_req_l 23 24 25 23 24 25 addr data data data data data data data data data data data data data data data data data data data data byte enables byte enables 7 7 addr figure 21. downstream flow-through posted memory write transaction (s1/33mhz-->s2/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s2_ad [31:0] s2_cbe [3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s_clkout[0] s1_ad[31:0] s1_cbe[3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s1_gnt_l s1_req_l s2_gnt_l s2_req_l 23 24 25 23 24 25
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-13 04/18/00 advance information addr data data data data data data data data data data data data data data data data data data data data byte enables byte enables 7 7 addr figure 22. upstream flow-through posted memory write transaction (s/33mhz-->p/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 23 24 25 26 27 28 23 24 25 26 27 28 addr data byte enables 2 2 addr byte enables addr data byte enables 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 23 24 25 26 figure 23. downstream delayed i/o read transaction ( p --> s )
a-14 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr data addr data byte enables byte enables 2 2 2 addr byte enables figure 24. downstream delayed i/o read transaction (s2/33mhz-->s1/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s1_ad [31:0] s1_cbe [3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s_clkout[0] s2_ad[31:0] s2_cbe[3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s2_gnt_l s2_req_l s1_gnt_l s1_req_l 23 23 addr data addr data byte enables byte enables 2 2 2 addr byte enables figure 25. downstream delayed i/o read transaction (s1/33mhz-->s2/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s2_ad [31:0] s2_cbe [3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s_clkout[0] s1_ad[31:0] s1_cbe[3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s1_gnt_l s1_req_l s2_gnt_l s2_req_l 23 23
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-15 04/18/00 advance information addr data addr data byte enables byte enables 2 2 2 addr byte enables figure 26. upstream delayed i/o read transaction (s/33mhz-->p/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 23 addr data byte enables 3 3 addr data byte enables addr data byte enables 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l figure 27. downstream delayed i/o write transaction ( p --> s )
a-16 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information addr data addr data byte enables byte enables 3 3 3 addr data byte enables figure 28. downstream delayed i/o write transaction (s2/33mhz-->s1/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s1_ad [31:0] s1_cbe [3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s_clkout[0] s2_ad[31:0] s2_cbe[3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s2_gnt_l s2_req_l s1_gnt_l s1_req_l 23 23 addr data addr data byte enables byte enables 3 3 3 addr data byte enables figure 29. downstream delayed i/o write transaction (s1/33mhz-->s2/33mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 s_clkout[0] s2_ad [31:0] s2_cbe [3:0] s2_frame_l s2_irdy_l s2_trdy_l s2_stop_l s2_devsel_l s_clkout[0] s1_ad[31:0] s1_cbe[3:0] s1_frame_l s1_irdy_l s1_trdy_l s1_stop_l s1_devsel_l s1_gnt_l s1_req_l s2_gnt_l s2_req_l 23 23
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123 appendix a pi7c7100 3-port pci bridge a-17 04/18/00 advance information addr data addr data byte enables byte enables 3 3 3 addr data byte enables figure 30. upstream delayed i/o write transaction ( s --> p ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 p_clk p_ad [31:0] p_cbe [3:0] p_frame_l p_irdy_l p_trdy_l p_stop_l p_devsel_l s_clkout[0] s_ad[31:0] s_cbe[3:0] s_frame_l s_irdy_l s_trdy_l s_stop_l s_devsel_l s_gnt_l s_req_l p_gnt_l p_req_l 23 23
a-18 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234 appendix a pi7c7100 3-port pci bridge advance information
pi7c7100 3-port pci bridge appendix b evaluation board users manual
b-2 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix b pi7c7100 3-port pci bridge advance information
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 appendix b pi7c7100 3-port pci bridge b-3 04/18/00 advance information general information 1. please make sure you have included with your pi7c7100 evaluation board, the five-page schematic and the preliminary specification for the pi7c7100. 2. check all jumpers for proper settings: pi7c7100 evaluation board users manual 3. check and make sure there are no shorts between power (3.3v, 5v, 12v, and C12v) and ground. 4. plug evaluation board in any pci slot on your system. make sure your system is powered off before doing so. 5. connect any pci devices on the secondary slots of the evaluation board. be careful that the orientation of the card is correct (see diagram a). e m a n n i pr e p m u jn o i t c n u fn o i t i s o p # n f c _ s4 p je l b a n e r e t i b r a l a n r e t n i) 0 ( 2 - 1 n e _ 1 s5 p je l b a n e s u b 1 s) 1 ( 3 - 2 n e _ 2 s6 p je l b a n e s u b 2 s) 1 ( 3 - 2 n e _ n a c s7 p jl o r t n o c n a c s) 0 ( 2 - 1 n e _ n a c s7 p jt u p n i k c o l c s a n i _ k l c s) 1 ( 3 - 2 m t _ l l p8 p je l b a s i d e d o m t s e t l l p) 0 ( 2 - 1 s s a p y b9 p je l b a s i d l l p) 1 ( 3 - 2 # h s u l f _ p0 1 p je l b a s i d h s u l f o f i f y r a m i r p) 1 ( 3 - 2 pci add-in card pericom semiconductor three-port pci bridge board diagram a
b-4 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix b pi7c7100 3-port pci bridge advance information 6. turn on the power for the system. your os should already have drivers for the pi7c7100 evaluation board. in win9x, plug and play should detect the device as a pci-to-pci bridge. the system may prompt you for the win9x cd for the drivers. the os will detect two pci-to-pci bridges as the pi7c7100 has two secondary pci buses. in win nt, you should not have to install drivers. 7. install drivers for any pci devices you have attached to the evaluation board. 8. if any of the steps are unclear or were unsuccessful, please contact your pericom support person at 408-435-0800. 9. thank you for evaluating pericom semiconductor corporations products. general information (continued)
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 appendix b pi7c7100 3-port pci bridge b-5 04/18/00 advance information frequently asked questions 1. what is the function of scan_en? scan_en is for a full scan test or s_clkin select. during scan mode, scan_en will be driven to logic 0 or logic 1 depending on functionality. during normal mode, if scan_en is connected to logic 0 (jp7 in the 1-2 position), s_clkin will be used for pll test only when pl_tm is active. if scan_en is connected to logic 1 (jp7 in the 2-3 position), s_clkin will be the clock input for the secondary buses. all secondary clock outputs, s_clkout [15:0], are still derived from p_clk with 0-10ns delay. the s_clkout [15:0] should be disabled by programming the bits [15:0] in both configuration registers 1 and 2 at offset 68h. 2. what is the function of scan_tm#? scan_tm# is for full scan test and power on reset for the pll. scan_tm# should be connected to logic 1 or to an rc path (r1 and c13) during normal operation. 3. how do you use the external arbiter? a) disable the on chip arbiter by connecting s_cfn to logic 1 (jp4 in the 2-3 position). b) use s1_req0# as grant and s1_gnt0# as request on the s1 bus. c) use s2_req0# as grant and s2_gnt0# as request on the s2 bus. 4. what is the purpose of having jp1, jp2, and jp3? jp1, jp2, and jp3 are designed for easy access to the primary bus signals. you may connect any of these pins to an oscilloscope or a logic analyzer for observation. no connection is required for normal operation. the following table indicates which bus signals correspond to which pins. 5. what is the purpose for having u17, u19, and u20? u17, u19, and u20 are designed for easy access to the digital ground planes for observation. 6. how is the evaluation board constructed? the evaluation board is a six-layer pcb. the top and bottom layers (1 and 6) are for signals, power, and ground routing. layer 2 and layer 5 are ground planes. layer 3 is a digital 3.3v power plane. layer 4 is a digital 5v power plane with an island of analog 3.3v power. 7. what is the function of s_clkin? the s_clkin pin is a test pin for the on chip pll when pll_tm is set to logic 1. during normal operation, if pll_tm is set to logic 0, scan_tm# is set to logic 1, and scan_en is set to logic 1, then s_clkin will be the clock input for both the secondary buses. however, the s_clkout [15:0] are still derived by program- ming bits [15:0] in both configuration registers 1 and 2 at offset 68h. 8. what clock frequency combinations does the pi7c7100 support? primary bus secondary (1 and 2) buses 33mhz 33mhz 9. how are the jtag signals being connected? the jtag signals consist of trst#, tck, tms, tdi, and tdo. all the mentioned signals have weak internal pull-up connections. therefore, no connection is needed if you want the jtag circuit to be disabled. if you want to activate the jtag circuit, you need to connect all five signals according to the jtag specification (ieee 1149). 1 2 3 456 7 8 9 0 11 12 13 14 15 16 1 2 p jq e r9 2 d a6 2 d a3 e b c1 2 d a8 1 d a2 e b cy d r ik c o lr a p4 1 d a1 1 d a0 e b c6 d a5 d a0 d a 3 p j1 3 d a8 2 d a5 2 d a3 2 d a0 2 d a7 1 d ae m a r fl e s v dr r e p1 e b c3 1 d a0 1 d a8 d a4 d a2 d ad n g 1 p jt n g0 3 d a7 2 d a4 2 d a2 2 d a9 1 d a6 1 d ay d r ip o t sr r e s5 1 d a2 1 d a9 d a7 d a3 d a1 d a
b-6 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix b pi7c7100 3-port pci bridge advance information
pi7c7100 3-port pci bridge appendix c schematics
c-2 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix c pi7c7100 3-port pci bridge advance information
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 c-3 04/18/00 appendix c pi7c7100 3-port pci bridge advance information a a b b c c d d e e 4 4 3 3 2 2 1 1 jp4 jp5 jp6 jp7 jp8 jp9 jp10 jp select name s_cfnn internal arbiter function s1_en s2_en s1_enable s2_enable position 1-2 2-3 2-3 scan_en 1-2 scan disable pll_tm 1-2 pll_tm disable bypass_l pll enable 1-2 p_flush_l p_flush disable 2-3 pi7c7100 1.3 three port pci bridge evaluation board c 15 friday, march 17, 2000 2380 bering dr., san jose, ca pci chip title size document number rev date: sheet of p_ad13 s1_ad2 s1_cbe3 p_ad9 p_ad14 s1_ad20 p_perrn p_ad7 p_ad17 p_ad18 p_ad31 s1_ad3 s1_ad5 s1_ad8 s1_ad13 s1_ad18 s1_ad28 p_ad22 s1_ad24 s1_ad25 p_ad8 s1_ad16 s1_cbe2 p_ad15 p_ad28 p_cbe1 s1_ad9 s1_ad12 s1_ad[31:0] s1_ad0 s1_ad30 p_ad0 p_ad4 p_ad26 s1_ad29 s1_cbe1 p_m66en p_lockn p_ad10 p_ad30 s1_ad11 s1_ad14 s1_ad21 p_ad23 p_ad27 p_cbe0 s1_ad6 s1_ad10 p_ad25 p_cbe3 s1_ad17 p_ad1 p_ad3 p_ad12 s1_ad7 s1_ad15 s1_ad19 s1_cbe0 p_ad19 s1_ad1 s1_ad23 p_ad11 p_ad16 p_ad21 p_ad[31:0] s1_ad4 s1_ad22 p_ad2 p_ad5 p_ad29 s1_ad27 s1_ad[31:0] s1_ad31 s_m66en p_cbe2 p_serrn p_ad6 p_ad20 p_ad24 s1_ad26 bypass s1_framen s1_gntn0 s1_devseln s1_reqn4 s1_gntn2 s1_gntn4 s1_lockn s1_gntn6 s1_reqn3 s1_reqn5 s1_reqn7 s1_gntn1 s1_reqn1 s1_gntn5 s1_gntn3 s1_gntn7 s1_irdyn s1_reqn2 s1_reqn0 s1_par s1_reqn6 s2_ad[31:0] s2_ad13 s2_ad3 s2_ad19 s2_ad22 s2_ad0 s2_ad9 s2_ad10 s2_ad21 s2_ad28 s2_cbe0 s2_ad15 s2_ad27 s2_cbe3 s2_ad25 s2_ad30 s2_ad2 s2_ad11 s2_ad12 s2_ad14 s2_cbe2 s2_ad18 s2_ad20 s2_ad23 s2_ad5 s2_cbe1 s2_ad17 s2_ad29 s2_ad31 s2_ad8 s2_ad4 s2_ad6 s2_ad7 s2_ad16 s2_ad26 s2_ad1 s2_ad24 s2_gntn1 s2_reqn2 s2_gntn7 s2_reqn7 s2_gntn2 s2_gntn4 s2_reqn1 s2_gntn5 s2_reqn3 s2_gntn3 s2_reqn5 s2_reqn4 s2_reqn6 s2_gntn0 s2_gntn6 s2_reqn0 sclkout0 sclkout13 sclkout5 sclkout6 sclkout11 sclkout14 sclkout4 sclkout9 sclkout1 sclkout2 sclkout12 sclkout15 sclkout3 sclkout8 sclkout7 sclkout10 +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v avcc +3.3v +3.3v avcc avcc +3.3v avcc +5v avcc +3.3v +3.3v +3.3v +3.3v r11 5.1k r9 5.1k r1 3.3k r2 5.1k r6 5.1k c13 0.1uf r4 5.1k r8 5.1k jp4 header 3 1 2 3 r3 5.1k r7 5.1k jp5 header 3 1 2 3 jp6 header 3 1 2 3 jp7 header 3 1 2 3 r12 5.1k r10 5.1k jp8 header 3 1 2 3 r13 5.1k r14 5.1k jp9 header 3 1 2 3 c58 0.01uf f3a 1 2 c55 0.001uf c59 0.1uf c19 0.001uf c42 0.001uf c57 0.1uf c41 0.1uf c60 0.001uf c56 0.01uf c40 0.01uf c22 0.01uf c23 0.1uf r15 5.1k jp10 header 3 1 2 3 r16 5.1k c45 0.1uf c44 0.01uf c47 0.1uf c46 0.01uf c48 0.001uf c43 0.001uf f3a 1 2 c50 0.01uf c51 0.1uf c49 0.001uf + c8 10uf + c10 10uf + c9 10uf c12 0.1uf c11 0.01uf c353 0.001uf c371 0.1uf c370 0.01uf c372 0.001uf c373 0.01uf + c374 10uf u0 lt1117 gnd 1 vo 2 vi 3 tab 4 c354 100uf + c7 10uf c16 0.1uf c17 0.1uf r5 121 r17 0 r18 150 r25 226 c24 0.01uf c25 0.01uf c26 0.01uf c27 0.01uf c28 0.01uf c29 0.01uf c21 0.001uf c20 0.001uf c38 0.001uf c39 0.001uf c30 0.001uf c31 0.001uf c36 0.1uf c34 0.1uf c37 0.1uf c33 0.1uf c35 0.1uf c32 0.1uf c360 0.01uf c367 0.001uf c363 0.01uf c365 0.1uf c361 0.001uf c368 0.1uf c366 0.01uf c362 0.1uf c364 0.001uf t1 table1 u1 pi7c7100 p_ad[0] r17 p_ad[1] t17 p_ad[2] y20 p_ad[3] v20 p_ad[4] u20 p_ad[5] y19 p_ad[6] w19 p_ad[7] u19 p_ad[8] y18 p_ad[9] w18 p_ad[10] u18 p_ad[11] y17 p_ad[12] w17 p_ad[13] y16 p_ad[14] w16 p_ad[25] y9 p_ad[16] v12 p_ad[17] w12 p_ad[18] y12 p_ad[19] u11 p_ad[20] v11 p_ad[21] y11 p_ad[22] v10 p_ad[23] w10 p_ad[24] w9 p_ad[15] v16 p_ad[26] u8 p_ad[27] v8 p_ad[28] w8 p_ad[29] y8 p_ad[30] w7 p_ad[31] y7 p_cbe[0] v19 p_cbe[1] u16 p_cbe[2] u12 p_cbe[3] v9 s_cfn_l y2 agnd u4 avcc y1 s1_ad[0] t19 s1_ad[1] t20 s1_ad[2] r18 s1_ad[3] r19 s1_ad[4] r20 s1_ad[5] p17 s1_ad[6] n17 s1_ad[7] n18 s1_ad[8] n19 s1_ad[9] n20 s1_ad[10] m17 s1_ad[11] m19 s1_ad[12] m20 s1_ad[13] l18 s1_ad[14] l19 s1_ad[15] l20 s1_ad[16] g19 s1_ad[17] g20 s1_ad[18] f17 s1_ad[19] f19 s1_ad[20] f20 s1_ad[21] e17 s1_ad[22] e18 s1_ad[23] e19 s1_ad[24] d17 s1_ad[25] d19 s1_ad[26] d20 s1_ad[27] c18 s1_ad[28] c19 s1_ad[29] c20 s1_ad[30] b19 s1_ad[31] b20 s1_cbe[0] p20 s1_cbe[1] k17 s1_cbe[2] g18 s1_cbe[3] e20 dgnd c2 s2_en w4 jtag_tck v2 jtag_tms w1 jtag_td0 v3 jtag_tdi w2 scan_tm_l v4 scan_en_h u5 pll_tm_h y3 cmpo1 u6 reserved r4 bypass y4 p_m66en v18 pll_sclk v5 s_m66en d7 pll_pclk v6 p_flush_l w5 p_reset_l y5 p_gnt u7 p_idsel y10 p_req w6 p_frame_l w13 p_irdy_l v13 p_trdy_l u13 p_devsel_l y14 p_stop_ l w14 p_lock_l v14 p_perr_l y15 p_serr_l w15 p_par u15 trst_l u3 s1_en w3 +d3.3v e2 +d3.3v j3 +d3.3v n2 +d3.3v v1 +d3.3v v7 +d3.3v u10 +d3.3v v15 +d3.3v w20 +d3.3v p19 +d3.3v l17 +d3.3v f18 +d3.3v d15 +d3.3v c14 +d3.3v d11 +d3.3v b8 +d3.3v d5 dgnd e3 dgnd g2 dgnd j2 dgnd k4 dgnd n1 dgnd r2 dgnd u2 dgnd y6 dgnd u9 dgnd w11 dgnd y13 dgnd u14 dgnd v17 dgnd u17 dgnd t18 dgnd p18 dgnd m18 dgnd k19 dgnd h17 dgnd g17 dgnd d18 dgnd a20 dgnd a17 dgnd a15 dgnd d12 dgnd a10 dgnd a8 dgnd a5 dgnd a3 s1_devsel_l j20 s1_frame_l h20 s1_gntn[0] b18 s1_gntn[1] d16 s1_gntn[2] b16 s1_gntn[3] d14 s1_gntn[4] a14 s1_gntn[5] b13 s1_gntn[6] b12 s1_gntn[7] c11 s1_irdy_l h19 s1_lock_l j18 s1_par_l k18 s1_perr_l j17 s1_req[0] b17 s1_req[1] c17 s1_req[2] a16 s1_req[3] c15 s1_req[4] c13 s1_req[5] d13 s1_req[6] a12 s1_req[7] b11 s1_reset_l b10 s1_serr_l k20 s1_stop_l j19 s1_trdy_l h18 s2_ad[0] c10 s2_ad[1] d10 s2_ad[2] a9 s2_ad[3] b9 s2_ad[4] c9 s2_ad[5] d9 s2_ad[6] c8 s2_ad[7] d8 s2_ad[8] b7 s2_ad[9] c7 s2_ad[10] a6 s2_ad[11] b6 s2_ad[12] c6 s2_ad[13] d6 s2_ad[14] b5 s2_ad[15] c5 s2_ad[16] b1 s2_ad[17] c1 s2_ad[18] d1 s2_ad[19] e4 s2_ad[20] e1 s2_ad[21] f4 s2_ad[22] f3 s2_ad[23] f2 s2_ad[24] g4 s2_ad[25] g3 s2_ad[26] g1 s2_ad[27] h4 s2_ad[28] h3 s2_ad[29] h2 s2_ad[30] h1 s2_ad[31] j4 s2_cbe[0] a7 s2_cbe[1] a4 s2_cbe[2] a1 s2_cbe[3] f1 s2_devsel_l d3 s2_frame_l d2 s2_gntn[0] k2 s2_gntn[1] l1 s2_gntn[2] l4 s2_gntn[3] m3 s2_gntn[4] n4 s2_gntn[5] r1 s2_gntn[6] p4 s2_gntn[7] u1 s2_irdy_l b2 s2_lock_l b3 s2_par_l b4 s2_perr_l d4 s2_req[0] k3 s2_req[1] k1 s2_req[2] m1 s2_req[3] m2 s2_req[4] p1 s2_req[5] p2 s2_req[6] r3 s2_req[7] t2 s2_reset_l t4 s2_serr_l c4 s2_stop_l c3 s2_trdy_l a2 sclkout[15] t3 sclkout[14] t1 sclkout[13] p3 sclkout[12] n3 sclkout[11] m4 sclkout[10] l3 sclkout[9] l2 sclkout[8] j1 sclkout[7] a11 sclkout[6] c12 sclkout[5] a13 sclkout[4] b14 sclkout[3] b15 sclkout[2] c16 sclkout[1] a18 sclkout[0] a19 s1_ad[31:0] p_cbe[3:0] p_ad[31:0] s1_cbe[3:0] pll_pclk tdo s_m66en p_devseln p_resetn p_reqn tck p_irdyn p_serrn p_m66en p_framen tms pll_sclk p_idsel tdi pll_cap1 p_trdyn p_stopn trst_l p_gntn p_lockn pll_cap2 p_perrn p_par s1_reqn[7:0] s1_gntn[7:0] s1_stopn s1_framen s1_lockn s1_perrn s1_serrn s1_irdyn s1_resetn s1_par s1_devseln s1_trdyn s2_cbe[3:0] s2_ad[31:0] s2_reqn[7:0] s2_gntn[7:0] s2_irdyn s2_stopn s2_resetn s2_devseln s2_perrn s2_trdyn s2_par s2_lockn s2_serrn s2_framen sclkout[15:0]
c-4 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix c pi7c7100 3-port pci bridge advance information a a b b c c d d e e 4 4 3 3 2 2 1 1 jp1 gnt ad30 ad27 ad24 ad22 ad19 ad16 irdy stop serr ad15 ad12 ad9 ad7 ad3 ad1 jp3 ad31 ad28 ad25 ad23 ad20 ad17 frame dvsel perr cbe1 ad13 ad10 ad8 ad4 ad2 gnd jp2 req ad29 ad26 cbe3 ad21 ad18 cbe2 trdy lock par ad14 ad11 cbe0 ad6 ad5 ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pi7c7100 1.3 three port pci bridge evaluation board c 25 friday, march 17, 2000 2380 bering dr., san jose, ca pci edge connector title size document number rev date: sheet of inta intb p_reset_l ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad23 ad20 ad18 ad17 ad16 c/be2 c/be1 ad0 m66en ad[31:0] c/be[3:0] intc ad24 p_idsel_l ad22 ad15 ad13 ad11 ad9 c/be0 ad6 ad4 ad2 intd p_clk c/be3 ad21 ad19 ad12 ad10 ad8 ad7 ad5 ad3 ad1 p_req_l p_gnt_l p_gnt_l p_req_l ad31 ad30 p_perr_l ad29 ad28 ad27 ad26 ad24 ad25 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 p_frame_l p_frame_l p_irdy_l p_irdy_l p_trdy_l p_trdy_l p_dvsel_l p_dvsel_l p_stop_ l p_stop_ l p_lock_l p_serr_l p_lock_l p_perr_l p_serr_l p_par p_par c/be1 ad15 ad14 ad14 ad13 ad12 ad11 ad10 ad9 c/be0 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 inta intc intb intd +12v -12v +5vio1 +5v +3.3v +3.3v +5v +5vio2 +3.3v c103 0.01uf c104 0.01uf c111 0.1uf c112 0.01uf + c102 10uf + c101 10uf c117 0.01uf r31 5.1k r32 5.1k r27 0 r29 0 r26 0 r28 0 r30 0 c110 0.01uf u38 1header t 1 c113 0.1uf c114 0.1uf c115 0.01uf c116 0.01uf c1 0.1uf c6 0.001uf c14 0.001uf c15 0.001uf c18 0.001uf jp1 header 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp2 header 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 jp3 header 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 u5 pciedge trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5vio1 a10 nc a11 nc a14 rst# a15 +5vio1 a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5vio2 a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 nc b12 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5vio1 b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5vio2 b59 ack64# b60 +5v b61 +5v b62 nc b13 nc a12 nc a13 c121 0.001uf c2 0.01uf c106 0.1uf + c97 10uf c119 0.001uf c108 0.01uf c5 0.1uf c3 0.1uf + c109 10uf u40 1header t 1 u44 1header t 1 u42 1header t 1 u43 1header t 1 u41 1header t 1 u39 1header t 1 u48 1header t 1 u47 1header t 1 u46 1header t 1 u45 1header t 1 c120 0.001uf c105 0.01uf c107 0.01uf c4 0.1uf c118 0.001uf t2 table2 irdy_l lock_l frame_l trdy_l stop_ l par dvsel_l intb_l intd_l reset_l inta_l intc_l clk tck tms trst_l idsel_l serr_l m66en req_l tdi tdo ad[31:0] c/be[3:0] gnt_l perr_l
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 c-5 04/18/00 appendix c pi7c7100 3-port pci bridge advance information a a b b c c d d e e 4 4 3 3 2 2 1 1 pi7c7100 1.3 three port pci bridge evaluation board c 35 friday, march 17, 2000 2380 bering dr., san jose, ca secondary 1 pci bus title size document number rev date: sheet of ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck0 trst0_l tms0 tdi0 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck1 trst1_l tms1 tdi1 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck2 trst2_l tms2 tdi2 sbo2_ l sbo1_ l sbo0_ l sbo0_ l sdone0 sbo1_ l sdone1 sbo2_ l sdone2 sbo3_ l sdone0 sdone2 sdone1 sdone3 m66en ad[31:0] c/be[3:0] req64#2 ack64#2 ack64#0 req64#0 ack64#1 req64#1 ack64#0 ack64#1 req64#0 req64#1 ack64#2 req64#2 req64#3 ack64#3 trdy_l frame_l irdy_l devsel_l perr_l serr_l lock_l stop_ l ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en trst3_l tms3 tdi3 sbo3_ l sdone3 req64#3 ack64#3 tck3 +3.3v +3.3v +12v -12v +3.3v +3.3v +12v -12v +3.3v +12v +3.3v +5v -12v +5v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +5v +3.3v +3.3v +5v +12v +5v +5v -12v c150 0.01uf c149 0.01uf c152 0.01uf r72 5.1k 1 2 r60 5.1k 1 2 r53 5.1k 1 2 r66 5.1k 1 2 r71 5.1k 1 2 r52 5.1k 1 2 r59 5.1k 1 2 r65 5.1k 1 2 c153 0.01uf c154 0.01uf c161 0.01uf c162 0.01uf c163 0.01uf c164 0.01uf c165 0.01uf c166 0.01uf c167 0.01uf c186 0.1uf c189 0.1uf c185 0.01uf c187 0.1uf c184 0.01uf c190 0.1uf c188 0.1uf c211 0.01uf c214 0.01uf c218 0.01uf c210 0.01uf c217 0.01uf c212 0.01uf c209 0.01uf c219 0.01uf + c204 10uf + c206 10uf c220 0.01uf c215 0.01uf c213 0.01uf c131 0.1uf c134 0.1uf c138 0.1uf c132 0.1uf c139 0.1uf c140 0.1uf c135 0.1uf c133 0.1uf r37 5.1k 1 2 r38 5.1k 1 2 r39 5.1k 1 2 r34 5.1k 1 2 r35 5.1k 1 2 r36 5.1k 1 2 r42 5.1k 1 2 r45 5.1k 1 2 r41 5.1k 1 2 r44 5.1k 1 2 r40 5.1k 1 2 r43 5.1k 1 2 r70 5.1k 1 2 r58 5.1k 1 2 r51 5.1k 1 2 r64 5.1k 1 2 r69 5.1k 1 2 r50 5.1k 1 2 r57 5.1k 1 2 r63 5.1k 1 2 r74 5.1k 1 2 r55 5.1k 1 2 r62 5.1k 1 2 r68 5.1k 1 2 r67 5.1k 1 2 r61 5.1k 1 2 r54 5.1k 1 2 r73 5.1k 1 2 u10 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 u9 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 c226 0.01uf c194 0.1uf c195 0.1uf c74 0.1uf c69 0.1uf c70 0.1uf u11 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 c339 0.01uf c340 0.01uf c216 0.01uf r46 5.1k 1 2 r47 5.1k 1 2 r48 5.1k 1 2 u8 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 c148 0.01uf c155 0.01uf c151 0.01uf c147 0.01uf r33 5.1k 1 2 + c156 10uf + c158 10uf c129 0.01uf c191 0.1uf c192 0.1uf c171 0.01uf c72 0.01uf c170 0.01uf c73 0.01uf c172 0.01uf c130 0.01uf irdy_l lock_l perr_l frame_l trdy_l stop_ l par devsel_l irdy_l lock_l perr_l frame_l trdy_l stop_ l devsel_l irdy_l lock_l perr_l frame_l trdy_l stop_l par devsel_l m66en inta_l intc_l intb_l intd_l reset_l clk0 idsel0_l intc_l inta_l intd_l intb_l inta_l intc_l intd_l clk1 clk2 reset_l reset_l idsel1_l idsel2_l par ad[31:0] c/be[3:0] gnt0_l gnt1_l gnt2_l req0_l req1_l req2_l serr_l serr_l serr_l irdy_l lock_l perr_l frame_l trdy_l stop_ l par devsel_l intb_l intc_l intd_l inta_l clk3 reset_l idsel3_l gnt3_l req3_l serr_l intb_l
c-6 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix c pi7c7100 3-port pci bridge advance information a a b b c c d d e e 4 4 3 3 2 2 1 1 pi7c7100 1.3 three port pci bridge evaluation board c 45 friday, march 17, 2000 2380 bering dr., san jose, ca secondary 2 pci bus title size document number rev date: sheet of ad[31:0] c/be[3:0] ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck0 trst0_l tms0 tdi0 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck1 trst1_l tms1 tdi1 ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck2 trst2_l tms2 tdi2 sbo2_ l sbo1_ l sbo0_ l sbo0_ l sdone0 sbo1_ l sdone1 sbo2_ l sdone2 sbo3_ l sdone0 sdone2 sdone1 sdone3 req64#2 ack64#2 ack64#0 req64#0 ack64#1 req64#1 ack64#0 ack64#1 req64#0 req64#1 ack64#2 req64#2 req64#3 ack64#3 trdy_l frame_l irdy_l devsel_l perr_l serr_l lock_l stop_ l ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 c/be3 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 c/be2 serr_l c/be1 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 c/be0 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 m66en tck3 trst3_l tms3 tdi3 sbo3_ l sdone3 req64#3 ack64#3 m66en +3.3v +3.3v +12v -12v +3.3v +5v +5v +3.3v +12v -12v +5v +3.3v +12v -12v +5v +3.3v +12v -12v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +3.3v +5v +5v +5v +3.3v +5v +3.3v c255 0.01uf c253 0.01uf c256 0.01uf c254 0.01uf r114 5.1k 1 2 r113 5.1k 1 2 c259 0.01uf c260 0.01uf c266 0.01uf c267 0.01uf c268 0.01uf c269 0.01uf c270 0.01uf c271 0.01uf c272 0.01uf c275 0.01uf c276 0.01uf c277 0.01uf c291 0.1uf c294 0.1uf c298 0.1uf c290 0.01uf c292 0.1uf c289 0.01uf c299 0.1uf c300 0.1uf c295 0.1uf c293 0.1uf c316 0.01uf c319 0.01uf c323 0.01uf c315 0.01uf c317 0.01uf c314 0.01uf c324 0.01uf + c311 10uf c325 0.01uf c320 0.01uf c318 0.01uf c236 0.1uf c239 0.1uf c243 0.1uf c235 0.01uf c237 0.1uf c234 0.01uf + c232 10uf c244 0.1uf c245 0.1uf c240 0.1uf c238 0.1uf r79 5.1k 1 2 r80 5.1k 1 2 r81 5.1k 1 2 r76 5.1k 1 2 r77 5.1k 1 2 r78 5.1k 1 2 r84 5.1k 1 2 r87 5.1k 1 2 r83 5.1k 1 2 r86 5.1k 1 2 r82 5.1k 1 2 r85 5.1k 1 2 r112 5.1k 1 2 r111 5.1k 1 2 r116 5.1k 1 2 r115 5.1k 1 2 u14 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 u13 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 u15 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 c330 0.01uf c331 0.01uf r75 5.1k 1 2 r89 5.1k 1 2 r90 5.1k 1 2 r88 5.1k 1 2 u12 pcislot trst# a1 +12v a2 tms a3 tdi a4 +5v a5 inta# a6 intc# a7 +5v a8 nc a9 +5v a10 nc a11 gnd a12 gnd a13 nc a14 rst# a15 +5v a16 gnt# a17 gnd a18 nc a19 ad30 a20 +3.3v a21 ad28 a22 ad26 a23 gnd a24 ad24 a25 idsel a26 +3.3v a27 ad22 a28 ad20 a29 gnd a30 ad18 a31 ad16 a32 +3.3v a33 frame# a34 gnd a35 trdy# a36 gnd a37 stop# a38 +3.3v a39 sdone a40 sbo# a41 gnd a42 par a43 ad15 a44 +3.3v a45 ad13 a46 ad11 a47 gnd a48 ad09 a49 nc a50 nc a51 c/be0# a52 +3.3v a53 ad06 a54 ad04 a55 gnd a56 ad02 a57 ad00 a58 +5v a59 req64# a60 +5v a61 +5v a62 -12v b1 tck b2 gnd b3 tdo b4 +5v b5 +5v b6 intb# b7 intd# b8 prsnt1# b9 nc b10 prsnt2# b11 gnd b12 gnd b13 nc b14 gnd b15 clk b16 gnd b17 req# b18 +5v b19 ad31 b20 ad29 b21 gnd b22 ad27 b23 ad25 b24 +3.3v b25 c/be3# b26 ad23 b27 gnd b28 ad21 b29 ad19 b30 +3.3v b31 ad17 b32 c/be2# b33 gnd b34 irdy# b35 +3.3v b36 devsel# b37 gnd b38 lock# b39 perr# b40 +3.3v b41 serr# b42 +3.3v b43 c/be1# b44 ad14 b45 gnd b46 ad12 b47 ad10 b48 m66en b49 nc b50 nc b51 ad08 b52 ad07 b53 +3.3v b54 ad05 b55 ad03 b56 gnd b57 ad01 b58 +5v b59 ack64# b60 +5v b61 +5v b62 c78 0.1uf c79 0.1uf c80 0.01uf c81 0.01uf c321 0.01uf c257 0.01uf c252 0.01uf c258 0.01uf + c229 10uf + c263 10uf + c287 10uf + c284 10uf c82 0.1uf c83 0.1uf c84 0.01uf c85 0.01uf r103 5.1k 1 2 r97 5.1k 1 2 r102 5.1k 1 2 r92 5.1k 1 2 r100 5.1k 1 2 r107 5.1k 1 2 r104 5.1k 1 2 r96 5.1k 1 2 r95 5.1k 1 2 r99 5.1k 1 2 r93 5.1k 1 2 r108 5.1k 1 2 r110 5.1k 1 2 r105 5.1k 1 2 r106 5.1k 1 2 r94 5.1k 1 2 r109 5.1k 1 2 r101 5.1k 1 2 irdy_l lock_l perr_l frame_l trdy_l stop_ l par devsel_l irdy_l lock_l perr_l frame_l trdy_l stop_ l devsel_l irdy_l lock_l perr_l frame_l trdy_l stop_l par devsel_l inta_l intc_l intb_l intd_l reset_l clk0 idsel0_l intc_l inta_l intd_l intb_l inta_l intc_l intb_l intd_l clk1 clk2 reset_l reset_l idsel1_l idsel2_l par ad[31:0] c/be[3:0] gnt0_l gnt1_l gnt2_l req0_l req1_l req2_l serr_l serr_l serr_l irdy_l lock_l perr_l frame_l trdy_l stop_ l par devsel_l intb_l intc_l intd_l inta_l clk3 reset_l idsel3_l gnt3_l req3_l serr_l m66en
1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 c-7 04/18/00 appendix c pi7c7100 3-port pci bridge advance information a a b b c c d d e e 4 4 3 3 2 2 1 1 note: those agnds are only connected to a small gnd plane on the top signal layer pi7c7100 1.3 three port pci bridge evaluation board c 55 friday, march 17, 2000 2380 bering dr., san jose, ca top view title size document number rev date: sheet of edge pciedge irdy_l lock_l perr_l frame_l trdy_l stop_ l par dvsel_l intb_l intd_l reset_l inta_l intc_l clk req_l gnt_l m66en tck tdo tdi tms trst_l idsel_l serr_l ad[31:0] c/be[3:0] s2_interface pcibus2 irdy_l lock_l perr_l frame_l trdy_l stop_ l par devsel_l req0_l gnt0_l serr_l req1_l gnt1_l req2_l gnt2_l req3_l gnt3_l m66en inta_l intc_l intb_l intd_l reset_l clk0 idsel0_l clk1 clk2 clk3 idsel1_l idsel2_l idsel3_l ad[31:0] c/be[3:0] s1_interface pcibus irdy_l lock_l perr_l frame_l trdy_l stop_ l par devsel_l req0_l gnt0_l serr_l req1_l gnt1_l req2_l gnt2_l req3_l gnt3_l m66en inta_l intc_l intb_l intd_l reset_l clk0 idsel0_l clk1 clk2 clk3 idsel1_l idsel2_l idsel3_l ad[31:0] c/be[3:0] chip pcichip s2_par s1_framen s2_irdyn s1_ad[31:0] p_cbe[3:0] s2_lockn s1_irdyn p_ad[31:0] s1_lockn s2_perrn s2_stopn s1_resetn s2_devseln s1_trdyn s1_stopn s2_cbe[3:0] s2_resetn s2_framen s1_devseln s2_ad[31:0] s2_trdyn s1_par s1_perrn s1_cbe[3:0] s2_serrn s2_reqn[7:0] s2_gntn[7:0] s1_reqn[7:0] s1_serrn p_idsel tck tdo tdi tms p_devseln p_framen p_gntn p_irdyn p_lockn p_par p_perrn p_reqn p_resetn p_serrn p_stopn p_trdyn pll_cap2 pll_cap1 pll_sclk p_m66en s_m66en trst_l sclkout[15:0] pll_pclk s1_gntn[7:0] intd_l intc_l intb_l inta_l inta_l intb_l intc_l intd_l intb_l intc_l intd_l inta_l s2_irdy_l p_c/be[3:0] s2_lock_l s2_perr_l s2_frame_l s1_par_l s1_par_l p_devsel_l p_gnt_l p_lock_l p_perr_l s2_stop _l s1_devsel_ l s2_gntn[7:0] p_irdy_l p_perr_l p_reset_l trst_l s2_lock_l s2_c/be[3:0] s1_perr_l tdi p_stop_ l p_trdy_l pll_cap2 s2_devsel_l s2_reset_l s1_c/be[3:0] p_idsel_l s2_irdy_l p_ad[31:0] p_ad[31:0] s2_perr_l s2_stop _l s1_reset_ l s1_stop _l s1_c/be[3:0] s1_gntn[7:0] p_serr_l p_m66en s1_frame_l tms p_par_l s2_c/be[3:0] s2_reset_l s2_ad[31:0] s1_perr_l s2_devsel_ l s1_stop _l tck p_frame_l p_reset_l s_clk s1_serr_l s2_trdy_l s2_serr_l p_devsel_l p_serr_l s1_frame_l p_c/be[3:0] s1_lock_l s2_reqn[7:0] tms p_gnt_l pll_cap1 s2_par_l p_irdy_l p_stop_ l s2_frame_l s1_serr_l p_idsel_l tck tdi s_m66en s2_par_l s2_trdy_l s2_serr_l tdo p_lock_l s1_lock_l tdo p_frame_l p_par_l p_req_l p_trdy_l p_m66en trst_l s1_reset_ l s1_devsel_ l p_req_l p_clk s1_reqn[7:0] s1_trdy_l s1_irdy_l s1_irdy_l s1_trdy_l s1_idsel0_l s1_idsel1_l s1_idsel2_l s1_idsel3_l s2_ad[31:0] s2_idsel0_l s2_ad20 s2_idsel1_l s2_ad21 s2_idsel2_l s2_ad22 s2_idsel3_l s2_ad23 s2_idsel0_l s2_idsel1_l s2_idsel2_l s2_idsel3_l s1_idsel3_l s1_ad23 s1_idsel1_l s1_ad21 s1_idsel0_l s1_ad20 s1_idsel2_l s1_ad22 sclkout0/4 sclkout6 sclkout2/6 sclkout3/7 sclkout1/5 sclkout[15:0] sclkout8/12 sclkout9/13 sclkout11/15 sclkout10/14 sclkout13 sclkout14 s1_gntn[7:0] s1_reqn[7:0] s2_gntn[7:0] s2_reqn[7:0] s1_gntn5 s1_reqn5 s2_gntn5 s2_reqn5 s1_reqn3/7 s1_reqn7 s1_reqn1/5 s1_gntn3/7 s1_gntn7 s1_gntn1/5 s1_gntn2/6 s1_gntn6 s1_reqn2/6 s1_reqn6 s2_reqn1/5 s2_gntn1/5 s2_reqn2/6 s2_reqn6 s2_gntn3/7 s2_gntn7 s2_gntn2/6 s2_gntn6 s2_reqn3/7 s2_reqn7 s1_gntn1/5 s1_gntn2/6 s1_gntn3/7 s1_gntn0/4 s1_reqn0/4 s1_reqn2/6 s1_reqn1/5 s1_reqn3/7 s2_reqn1/5 s2_gntn3/7 s2_gntn2/6 s2_reqn0/4 s2_reqn2/6 s2_reqn3/7 s2_gntn0/4 s2_gntn1/5 sclkout12 sclkout11 sclkout10 sclkout9 sclkout8 sclkout5 sclkout0 s1_gntn4 s1_gntn0/4 s1_gntn3 s1_gntn2 s1_gntn1 s1_gntn0 s1_reqn0 s1_reqn0/4 s1_reqn4 s1_reqn2 s1_reqn1 s1_reqn3 s2_gntn0 s2_gntn0/4 s2_gntn4 s2_gntn2 s2_gntn1 s2_gntn3 s2_reqn0 s2_reqn0/4 s2_reqn4 s2_reqn2 s2_reqn1 s2_reqn3 sclkout7 sclkout15 s1_ad[31:0] s1_ad[31:0] s2_gntn3/7 s2_gntn2/6 s2_gntn0/4 s2_gntn1/5 s2_reqn1/5 s2_reqn0/4 s2_reqn2/6 s2_reqn3/7 s1_reqn0/4 s1_reqn2/6 s1_reqn1/5 s1_reqn3/7 s1_gntn1/5 s1_gntn2/6 s1_gntn3/7 s1_gntn0/4 sclkout4 sclkout2 sclkout1 sclkout3 +5v +3.3v +3.3v c350 100p c351 100p r148 4.7k r150 4.7k u20 test point t u19 test point t u17 test point t c352 47p c349 47p r174 22 1 2 r164 0 1 2 r163 0 1 2 r162 0 1 2 r161 0 1 2 p1 header 6 1 2 3 4 5 6 r199 5.1k 1 2 r173 22 1 2 r152 22 1 2 r151 22 1 2 r149 22 1 2 r147 22 1 2 r170 22 1 2 r143 22 1 2 r165 0 1 2 r177 0 1 2 r178 0 1 2 r179 0 1 2 r180 0 1 2 r184 0 1 2 r166 0 1 2 r182 0 1 2 r183 0 1 2 r181 0 1 2 r188 0 1 2 r167 0 1 2 r186 0 1 2 r187 0 1 2 r185 0 1 2 r192 0 1 2 r168 0 1 2 r190 0 1 2 r191 0 1 2 r189 0 1 2 r171 22 1 2 r172 22 1 2 r175 22 1 2 r176 22 1 2 u22 1header t 1 u23 1header t 1 u24 1header t 1 u25 1header t 1 u26 1header t 1 u27 1header t 1 u28 1header t 1 u29 1header t 1 u30 1header t 1 u31 1header t 1 u32 1header t 1 u33 1header t 1 u34 1header t 1 u35 1header t 1 u36 1header t 1 u37 1header t 1 r49 5.1k 1 2 r169 22 1 2 r145 22 1 2 r144 22 1 2 r146 22 1 2
c-8 04/18/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 appendix c pi7c7100 3-port pci bridge advance information
d1 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information pi7c7100 3-port pci bridge appendix d representatives & distributors
d2 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information corporate headquarters pericom semiconductor corp. 2380 bering drive, san jose, ca 95131-usa 1-800 435-2336 408 435-0800 408 435 1100 fax nolimits@pericom.com northern california, western usa & british columbia pericom semiconductor corp. 2380 bering drive, san jose, ca 95131-usa 1-800 435-2336 408 435-0800 408 435 1100 fax rgorshe@pericom.com southern california-usa pericom semiconductor corp. 3455 lebon street, suite 1536 san diego, ca 92212-usa 858 558-6975 858 558 6685 fax nsoo@pericom.com north central & south central usa pericom semiconductor corp. 5068 west plano parkway, suite 300 plano, tx 75093-usa 972 381-4209 972 381 4208 mmorse@pericom.com mid atlantic and south east usa pericom semiconductor corp 1143-b executive circle cary, nc 27511-usa 919 460-3177 919 460 3179 fax mward@pericom.com north east and mid and eastern canada pericom semiconductor corp radnor station building #2 290 king of prussia road, suite 104 radnor, pa 19087 610.293.7400 610.293.7410 fax gfrancisco@pericom.com europe pericom semiconductor corp. the enterprise center 1-2 davy road gorse lane industrial center clacton on sea, essex, uk co15 4xd 44 1255 479994 44 1255 223676 fax johara@pericom.com china - peoples republic of china pericom technology inc. 481 gui ping road 3f, building 20 shanghai, 200233 86 21 6485 0576 86 21 6485 2181 fax afock@pericom.com hong kong pericom technology inc. 8 wang hoi road, unit 1517 chevalier commercial center kowloon bay, hong kong 852 2243 3660 852 2243 3667 fax qshuai@pti.com.cn taiwan r.o.c. pericom semiconductor corp. 11f, no. 18, alley 1, lane 768, sec 4 pa te road taipei, taiwan - r.o.c. 886 2 2651 5159 886 2 2653 0041 fax mchiang@pericom.com singapore pericom semiconductor corp. 42 mactaggart road #04-01 mactaggart building singapore 368086 65 287 9705 65 287 9706 fax tctee@postone.com japan pericom semiconductor corp. yamamasa daiichi building 5, 2-11-3 kobuchi sagamihara-shi, kanagawa 229-0004-japan 81 427 86 7266 81 427 86 7267 fax ksato@pericom.com pericom corporate offices
d3 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information north america distributors company name street address city s tate zip code country telephone fax number all american ................................... 4950 corporate drive, suite 115d ............................................. huntsville .................. al ............. 35805 ............. usa ....... 800 382-5303 ....... 256-837-7733 future ............................................. 6767 old madison pike, suite 400a ........................................... huntsville .................. al ............. 35806 ............. usa ....... 256-971-2010 ...... 256-922-0004 nu horizons ................................... 4825 university square, suite 8 ................................................ huntsville .................. al ............. 35816 ............. usa ....... 256-722-9330 ...... 256-722-9348 pioneer-standard electronics .......... 4910 university square, suite 7 ................................................ huntsville .................. al ............. 35816 ............. usa ....... 256 837-9300 ....... 256-837-9385 fai ................................................. 11219 financial centre parkway, financial park place, ste 311 .. little rock .................. ar ............ 72211 ............. usa ....... 501-219-1707 ...... 501-219-1747 all american ................................... 4636 east university drive, suite 155 ........................................ phoenix ...................... az ............ 85034 ............. usa ....... 480-966-0006 ...... 480-966-0007 bell microproducts .......................... 4926 east mcdowell road, suite 102 ........................................ phoenix ...................... az ............ 85008 ............. usa ....... 602-267-9551 ...... 602-267-8911 fai ................................................. 4636 east university drive, suite 145 ........................................ phoenix ...................... az ............ 85034 ............. usa ....... 480-731-4661 ...... 480-731-9866 future ............................................. 4636 east university drive, suite 245 ........................................ phoenix ...................... az ............ 85034 ............. usa ....... 602-968-7140 ...... 602-968-0334 nu horizons ................................... 1295 west washington street, suite 212 ................................... tempe ....................... az ............ 85281 ............. usa ....... 602 685-9000 ....... 602-685-9004 pioneer-standard electronics .......... 4908 east mcdowell road, suite 103 ........................................ phoenix ...................... az ............ 85008 ............. usa ....... 602-231-6400 ...... 602-321-8877 aegis electronics group .................. 1015 chestnut avenue, suite g2 ............................................... carlsbad ................... ca ............ 92208 ............. usa ....... 760 729-2026 ....... all american ................................... 10805 holder street, suite 100 .................................................. cypress ..................... ca ............ 90630 ............. usa ....... 714 229-8600 ....... 714-229-8603 all american ................................... 14192 chambers road ............................................................. tustin ........................ ca ............ 92680 ............. usa ....... 714 573-5000 ....... 714-573-5047 all american ................................... 1545 east acequia, suite a ............ ........................................... visalia ....................... ca ............ 93292 ............. usa ....... 209 734-8861 ....... all american ................................... 230 devcon drive ..................................................................... san jose ................... ca ............ 95112 ............. usa ....... 800-222-6001 ...... 408-437-8970 all american ................................... 26010 mureau road, suite 120 ................................................. calabasas ................. ca ............ 91302 ............. usa ....... 818 878-0555 ....... 818-878-0533 all american ................................... 6390 greenwich drive, suite 170 ............................................... san diego ................. ca ............ 92122 ............. usa ....... 800-382-3441 ...... 619-658-0201 bell microproducts .......................... 1921 ringwood avenue ............................................................. san jose ................... ca ............ 95131-1721 .... usa ....... 408 451-9400 ....... 408-467-2734 bell microproducts .......................... 30 f airbanks, suite 114 ............................................................ irvine ......................... ca ............ 92618 ............. usa ....... 949 470-2900 ....... 949-470-2929 bell microproducts .......................... 5090 shoreham place, suite 206 ............................................... san diego ................. ca ............ 92121 ............. usa ....... 858 597-3010 ....... 858-597-3015 bell microproducts .......................... 29800 west agoura road, suite 150 ......................................... agoura hills .............. ca ............ 91301 ............. usa ....... 818 865-0266 ....... 818-865-0215 fai ................................................. 354 bel marin keys blvd., suite d .......................................... ... novato ....................... ca ............ 94949 ............. usa ....... 415 883-9446 ....... 415-883-8336 fai ................................................. 525 south douglas street ......................................................... el segundo ................ ca ............ 90245 ............. usa ....... 310 727-1754 ....... 310-727-1796 fai ................................................. 2220 otoole ave. .................................................................... san jose ................... ca ............ 95131 ............. usa ....... 408 434-0369 ....... 408-433-9599 fai ................................................. 6256 greenwich drive, suite 200 .............................................. san diego ................. ca ............ 92122 ............. usa ....... 858-623-5859 ...... 858-623-5860 fai ................................................. 25b technology drive, suite 200 .............................................. irvine ......................... ca ............ 92618 ............. usa ....... 949-753-4778 ...... 949-753-4778 fai ................................................. 26570 agoura road ................................................................. calabasas ................. ca ............ 91302 ............. usa ....... 818 871-1700 ....... 818-871-1726 fai ................................................. 3009 douglas blvd., suite 215 .................................................. roseville ................... ca ............ 95661 ............. usa ....... 916-782-7882 ...... 916-782-9388 fai ................................................. 1370 valley vista drive, suite 265 ............................................. diamond bar ............. ca ............ 91765 ............. usa ....... 909 612-0667 ....... 909-612-0167 fai ................................................. 2121 41st avenue ..................................................................... capitola ..................... ca ............ 95010 ............. usa ....... 831 465-7373 ....... 831-465-7299 future ............................................. 2220 otoole ave. .................................................................... san jose ................... ca ............ 95131 ............. usa ....... 408 434-1122 ....... 408-433-0822 future ............................................. 26570 agoura road ................................................................. calabasas ................. ca ............ 91302 ............. usa ....... 818 871-1740 ....... 818-871-1764 future ............................................. 25b technology drive, suite 200 .............................................. irvine ......................... ca ............ 92618 ............. usa ....... 949-453-1515 ...... 949-453-1226 future ............................................. 27489 west agoura road, suite 300 ......................................... agoura hills .............. ca ............ 91301 ............. usa ....... 818 865-0040 ....... future ............................................. 3009 douglas blvd., suite 210 .................................................. roseville ................... ca ............ 95661 ............. usa ....... 916 783-7877 ....... 916-783-7988 future ............................................. 5990 stoneridge drive .............................................................. p leasanton ................. ca ............ 94588 ............. usa ....... 925 225-0294 ....... 925 225-9745 future ............................................. 6256 greenwich drive, suite 200 .............................................. san diego ................. ca ............ 92122 ............. usa ....... 858-625-2800 ...... 858-625-2810 nu horizons ................................... 1220 melody lane, suite 110 .................................................... roseville ................... ca ............ 95678 ............. usa ....... 916 783-5500 ....... 916-783-3066 nu horizons ................................... 13900 alton parkway, suite 123 ................................................. irvine ......................... ca ............ 92718 ............. usa ....... 949 470-1011 ....... 949-470-1104 nu horizons ................................... 2070 ringwood avenue ............................................................ san jose ................... ca ............ 95131 ............. usa ....... 408 434-0800 ....... 408-434-0935 nu horizons ................................... 4360 view ridge avenue, suite b ............................................. san diego ................. ca ............ 92123 ............. usa ....... 619 576-0088 ....... 619-576-0990 nu horizons ................................... 850 hampshire road, suite r .................................................. thousand oaks .......... ca ............ 91361 ............. usa ....... 805 370-1515 ....... 805-370-1525 pioneer-standard electronics .......... 217 technology drive, suite 110 ............................................... irvine ......................... ca ............ 92618 ............. usa ....... 949-753-5090 ...... 949-753-5074 pioneer-standard electronics .......... 333 river oaks pkwy. ............................................................... san jose ................... ca ............ 95134 ............. usa ....... 408 954-9100 ....... pioneer-standard electronics .......... 5126 clareton drive, suite 100 ................................................. agoura hills .............. ca ............ 91301 ............. usa ....... 818 865-5800 ....... 818-865-5814 pioneer-standard electronics .......... 9449 balboa ave., suite 114 ...................................................... san diego ................. ca ............ 92123 ............. usa ....... 858-514-7700 ...... 858-514-7799 pioneer-standard electronics .......... 431 dixon landing road .......................................................... milpitas ..................... ca ............ 95035 ............. usa ....... 408 586-5600 ....... 408-586-5785 all american ................................... 7577 west 103rd avenue, suite 204 .......................................... westminster .............. co ............ 80021 ............. usa ....... 303-222-0100 ...... 303-222-0110 all american ................................... 4090 youngfield street ............................................................. w heat ridge ............. co ............ 80033 ............. usa ....... 303 422-1701 ....... bell microproducts .......................... 4600 south ulster street, suite 240 .......................................... denver ....................... co ............ 80237 ............. usa ....... 303-846-3065 ...... 303-846-3064 future ............................................. 1819 denver west drive, bldg. 26, suite 350 ............................ golden ....................... co ............ 80401 ............. usa ....... 303 277-0023 ....... 303-277-0722 pioneer-standard electronics .......... 5600 greenwood plaza blvd. suite 200 ..................................... englewood ................. co ............ 80111 ............. usa ....... 303 773-8090 ....... 303-773-8194 all american ................................... 100 mill plain road, suite 360 .................................................. danbury ..................... ct ............ 06811 ............. usa ....... 203 791-3818 ....... all american ................................... 83 papermill road ............................................................... .... woodbury .................. ct ............ 6798 ............... usa ....... 203-266-0486 ...... same future ............................................. 700 west joh nson avenue, westgate office center .................. cheshire ................... ct ............ 06410 ............. usa ....... 203 250-0083 ....... 203-250-0081 pioneer-standard electronics .......... two trap falls road, suite 100 ............................................... shelton ...................... ct ............ 06484 ............. usa ....... 203-929-5600 ...... 203-929-9791 all american ................................... 600 fairway drive, suite 101 .................................................... deerfield beach ......... fl ............. 33441 ............. usa ....... 954 429-2800 ....... 954-429-0391 all american ................................... 528 south north lake blvd., suite 1040 ..................................... alt amonte springs ..... fl ............. 32701 ............. usa ....... 407 261-1304 ....... 407-261-1330 all american ................................... 14450 46th street north, suite 116 ............................................ clearwater ................. fl ............. 33762 ............. usa ....... 813 532-9800 ....... 813-538-5567 all american ................................... 16115 nw 52nd avenue ............................................................ miami ........................ fl ............. 33014 ............. usa ....... 305 621-8282 ....... 305-620-7831 bell microproducts .......................... 17431 sw 18th street ............................................................... miramar .................... fl ............. 33029 ............. usa ....... 954-450-1850 ...... 954-450-0223 bell microproducts .......................... 1110 douglas avenue, suite 1018 ............................................. alt amonte springs ..... fl ............. 32714 ............. usa ....... 407 682-1199 ....... 407-682-1286 bell microproducts .......................... 1761 west hillsboro blvd., suite 208 ......................................... deerfield beach ......... fl ............. 33442 ............. usa ....... 954 429-1001 ....... edge electronics ............................. 100 second avenue south, suite 200 ......................................... st. petersburg ........... fl ............. 33701 ............. usa ....... 727-894-3343 ...... 727-823-9030 fai ................................................. 525 technology park, suites 125/126 ........................................ lake mary .................. fl ............. 32746 ............. usa ....... 407 333-3177 ....... 407-333-3277 fai ................................................. 348 sw miracle strip pkwy., suite 33 ....................................... . fort walton beach ..... fl ............. 32548 ............. usa ....... 850 301-0766 ....... 850-301-0773 fai ................................................. 2200 tall pines drive, suite 109 ........................................... .... largo ........................ fl ............. 34641 ............. usa ....... 727-530-1665 ...... 727-530-7609 future ............................................. 1400 east newport center drive, suite 200 ............................... deerfield beach ......... fl ............. 33442 ............. usa ....... 954 428-9494 ....... 954-428-9477 future ............................................. 237 south westmonte drive, suite 307 ...................................... altamonte springs ..... fl ............. 32714 ............. usa ....... 407 444-6302 ....... 407-444-6303 future ............................................. 2200 tall pines drive, suite 108 ............................................... lar go ........................ fl ............. 33771 ............. usa ....... 727-530-1222 ...... 727-538-9598 nu horizons ................................... 3421 n.w. 55th street .............................................................. ft. lauderdale ............ fl ............. 33309 ............. usa ....... 954 735-2555 ....... 954-735-2880 nu horizons ................................... 4500 140th avenue north, suites 214/215 .................................. clearwater ................. fl ............. 33762 ............. usa ....... 727-536-5700 ...... 727-536-7799 nu horizons ................................... 600 south north lake blvd., suite 210 ....................................... alt amonte springs ..... fl ............. 32701 ............. usa ....... 407 831-8008 ....... 407-931-8862 pioneer-standard electronics .......... 337 south north lake, suite 1000 .............................................. ala monte springs ...... fl ............. 32701 ............. usa ....... 407 834-9090 ....... 407-834-0865 pioneer-standard electronics .......... 674 south military trail ............................................................ deerfield beech ......... fl ............. 33442 ............. usa ....... 954 428-8877 ....... 954-481-2950
d4 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information company name street address city s tate zip code country telephone fax number all american ................................... 6875 jimmy carter blvd., suite 3100 ............. ............................ norcross ................... ga ............ 30071 ............. usa ....... 770 441-7500 ....... 770-441-3660 bell microproducts .......................... 1950 spectrum circle, suite 400 ............................................... marietta ..................... ga ............ 30067 ............. usa ....... 770-980-4922 ...... 770-857-4399 future ............................................. 44000 river green parkway, suite 220 .... .................................. duluth ....................... ga ............ 30096 ............. usa ....... 770 476-3900 ....... 770-476-8662 future ............................................. 3150 hocomb bridge rd. holcolm place, suite 130 ................. norcross ......... .......... ga ............ 30071 ............. usa ....... 770 441-7676 ....... nu horizons ................................... 100 p innacle way, suite 155 ..................................................... norcross ................... ga ............ 30071 ............. usa ....... 770 416-8666 ....... 770-416-9060 pioneer-standard electronics .......... 4250-c rivergreen pkwy. ......................................................... duluth ....................... ga ............ 30096 ............. usa ....... 770 623-1003 ....... 770-623-0665 fai ................................................. 12438 west bridger street, suite 110 ....................................... boise ......................... id ............. 83713 ............. usa ....... 208 376-8080 ....... 208-376-6186 all american ................................... 1930 north thoreau drive, suite 200 ........................................ schaumburg .............. il .............. 60173 ............. usa ....... 847 303-1995 ....... 847-303-1996 bell microproducts .......................... 953 plum grove road, suite b .................................................. schaumburg .............. il .............. 60173 ............. usa ....... 847 413-8530 ....... 847-413-8541 fai ................................................. 3100 west higgins road, suite 115 ......................................... h offman estates ........ il .............. 60195 ............. usa ....... 847 843-0034 ....... 847-843-1163 future ............................................. 3100 west higgins road, suite 100 ......................................... h offman estates ........ il .............. 60195 ............. usa ....... 847 882-1255 ....... 847-490-9290 nu horizons ................................... basswood office center, 500 east remington road, suite 104 . schaumburg .............. il .............. 60173 ............. usa ....... 847 519-0700 ....... 847-519-7710 pioneer-standard electronics .......... 2171 executive drive suite 200 ................................................. addison ..................... il .............. 60101 ............. usa ....... 630 495-9680 ....... 630-495-9831 future ............................................. 8520 allison pointe blvd., suite 310 .......................................... indi anapolis ............... in ............. 46250 ............. usa ....... 317 913-1355 ....... 317-913-1375 future ............................................. 8425 woodfield crossing, suite 170 ......................................... indiana polis ............... in ............. 46240 ............. usa ....... 317 469-0447 ....... 317-49-0448 pioneer-standard electronics .......... 237 airport n. office park ......................................................... fort wayne ................ in ............. 46285 ............. usa ....... 219 489-0283 ....... pioneer-standard electronics .......... 9350 n. priority way w. drive ................................................... indi anapolis ............... in ............. 46240 ............. usa ....... 317 573-0880 ....... all american ................................... 7201 west 129th street, suite 150 ............................................. overland park ............ ks ............ 66213 ............. usa ....... 913 851 5900 ....... 913-851-5905 fai ................................................. 10977 granada lane, suite 210 ................................................ overland park ............ ks ............ 66211 ............. usa ....... 913 338-4400 ....... 913-338-3412 pioneer-standard electronics .......... 8500 college blvd., suite 128 ................................................... overland .................... ks ............ 66210 ............. usa ....... 913-338-7164 ...... 913-338-7185 all american ................................... 19-a crosby drive ............................................................... .... bedford ...................... ma ............ 01730 ............. usa ....... 781-275-8888 ...... 617-275-1982 bell microproducts .......................... 2a gill street ..................................................................... ...... woburn ...................... ma ............ 1730 ............... usa ....... 781-933-9010 ...... 781-933-8336 future ............................................. 41 main street .................................................................... ..... bolton ........................ ma ............ 01740 ............. usa ....... 978 779-3000 ....... 978-779-3050 interface electronics ........................ 124 grove street, suite 300 ...................................................... fr anklin ..................... ma ............ 2038 ............... usa ....... 508-553-4200 ...... 508-553-9575 interface electronics ........................ 228 south street ....................................................................... ho pkinton .................. ma ............ 1748 ............... usa ....... 508 435-0100 ....... nu horizons ................................... 2 c orporation way, suite 240 .................................................... peabody ..................... ma ............ ,01960 ............ usa ....... 978 532-7666 ....... 978-532-7667 pioneer-standard electronics .......... 299 callardvale street .............................................................. wilmington ................ ma ............ ,01887 ............ usa ....... 978 988-6600 ....... 978-988-6620 all american ................................... 8310 guilford road, suite a ..................................................... columbia ................... md ........... 21046 ............. usa ....... 410 309-6262 ....... 410-309-6272 bell microproducts .......................... 6925 r. oakland mills road ..................................................... columbia ................... md ........... 21045 ............. usa ....... 410 720-5100 ....... 410-381-2172 future ............................................. 857 elkridge landing road, international tower ....................... linthicum ................... md ........... 21090 ............. usa ....... 410 314-1111 ....... 410-314-1110 future ............................................. 6716 alexander bell drive, suite 220 ............. ............................ columbia ................... md ........... 21046 ............. usa ....... 410 290-0600 ....... nu horizons ................................... 8965 guilford road, suite 100 .................................................. columbia ................... md ........... 21046 ............. usa ....... 310-995-6330 ...... 310-995-6332 pioneer-standard electronics .......... 9100 gaither road ................................................................... gaither sburg ............. md ........... 20877 ............. usa ....... 301 921-0660 ....... 301-670-6746 all american ................................... 39201 schoolcraft road, suite b-2 ........................................... livonia ....................... mi ............. 48150 ............. usa ....... 734-464-2202 ...... 734-464-2433 future ............................................. 39340 country club drive, suite 100 ............. ............................ famingron hills ........ mi ............. 48331 ............. usa ....... 248 489-1179 ....... 248-489-1030 future ............................................. 4595 broadmoor se., suite 280 ................................................ g rand rapids ............ mi ............. 49512 ............. usa ....... 616 534-3510 ....... 616-698-6821 pioneer-standard electronics .......... 44190 plymouth oaks blvd. ............ ........................................... ply mouth .................... mi ............. 48170 ............. usa ....... 734-416-2157 ...... 734-416-2415 pioneer-standard electronics .......... 4476 byron center road sw .................................................... g rand rapids ............ mi ............. 49509 ............. usa ....... 616-534-3145 ...... 616-534-3922 all american ................................... 6608 flying cloud drive ......................................................... .. eden prairie .............. mn ........... 55344 ............. usa ....... 612 944-2151 ....... 612-944-9803 bell microproducts .......................... primetech center 1, 6442 city west parkway, suite 200 ............ eden prairie .............. mn ........... 55344 ............. usa ....... 612 943-1122 ....... 612-943-1110 future ............................................. 18882 lake drive east .............................................................. c hanhassen .............. mn ........... 55317 ............. usa ....... 612 934-9100 ....... 612-934-6700 future ............................................. 10025 valley view road, suite 196 ........................................... eden prairie .............. mn ........... 55344 ............. usa ....... 612 944-2200 ....... nu horizons ................................... 10907 valley view road ........................................................... eden prairie .............. mn ........... 55344 ............. usa ....... 612 942-9030 ....... 612-942-9144 pioneer-standard electronics .......... 7625 golden triangle drive, suite g ........................................ eden prairie .............. mn ........... 553 44 ............. usa ....... 612-944-3794 ...... 612-829-2229 fai ................................................. 12125 woodcrest executive drive, suite 208 ............................. st. louis .................... mo ........... 63141 ............. usa ....... 314-542-9922 ...... 314-542-9655 future ............................................. 12125 woodcrest executive drive, suite 206 ............................. st. louis .................... mo ........... 63141 ............. usa ....... 314-469-6805 ...... 314-469-7226 pioneer-standard electronics .......... 4227 earth city expressway ...................................................... earth city .................. mo ........... 63045 ............. usa ....... 314-209-3000 ...... 314-209-3054 all american ................................... 1121 situs court, suite 370 ..................................................... . raleigh ..................... nc ............ 27606 ............. usa ....... 919 851-6566 ....... 919-851-8734 fai ................................................. 5225 capital blvd., 1 north commerce center .......................... raleig h ..................... nc ............ 27616 ............. usa ....... 919 790-7111 ....... 919-790-9022 fai ................................................. 2800 sumner blvd., suite 154 .................................................... raleigh ..................... nc ............ 27616 ............. usa ....... 919 876-0088 ....... 919-876-8597 future ............................................. 8401 university executive parkway, suite 108 ............................ charlotte ................... nc ............ 28262 ............. usa ....... 704-548-9503 ...... 704-548-9469 interface electronics ........................ 4601 six forks road, suite 133 ................................................ raleigh ..................... nc ............ 27609 ............. usa ....... 919-787-8744 ...... 919-787-9192 nu horizons ................................... 2920 highwood boulevard, suite 125 ........................................ raleigh ..................... nc ............ 27604 ............. usa ....... 919 954-0500 ....... 919-954-0545 pioneer-standard electronics .......... 5510 six forks road, suite 310 ................................................ raleigh ..................... nc ............ 27609 ............. usa ....... 919-845-5100 ...... 919-845-5055 all american ................................... 8 east stow road, suite 100 ..................................................... m arlton ...................... nj ............ 8053 ............... usa ....... 609-596-6666 ...... 609-797-1700 bell microproducts .......................... 55 u.s. highway 46 east, suite 403 .......................................... pine brook ................. nj ............ ,07058 ............ usa ....... 973-244-9668 ...... 973-244-9667 bell microproducts .......................... 23 sebago street ..................................................................... clifton ....................... nj ............ 7013 ............... usa ....... 201 777-4100 ....... fai ................................................. 2000 crawford place, suite 900 ................................................ mt. laurel .................. nj ............ ,08054 ............ usa ....... 856 787-1000 ....... 856-787-9626 future ............................................. 12 east stow road, suite 200 ................................................... m arlton ...................... nj ............ 08053 ............. usa ....... 609 596-4080 ....... future ............................................. 1259 route 46 east .................................................................. parsi ppany ................. nj ............ 07054 ............. usa ....... 973 299-0400 ....... 973-299-1377 interface electronics ........................ 20000 horizon way, suite 300 .................................................. mt. laural .................. nj ............ 8054 ............... usa ....... 609-439-0750 ...... 609-439-0519 interface electronics ........................ 1 green tree, suite 201 ........................................................... m arlton ...................... nj ............ 8053 ............... usa ....... 609 988-5448 ....... nu horizons ................................... 18000 horizon way, suite 200 .................................................. mt. laural .................. nj ............ 08054 ............. usa ....... 609 231-0900 ....... 609-231-9510 nu horizons ................................... 39 u.s. route 46 ...................................................................... pine brook ................. nj ............ 07058 ............. usa ....... 973-882-8300 ...... 973-882-8398 pioneer-standard electronics .......... 271 route 46w, suite d206 ...................................................... fairfield ..................... nj ............ ,07004 ............ usa ....... 973 227-7760 ....... 973-227-3305 pioneer-standard electronics .......... 14a madison road ................................................................... fairfield ..................... nj ............ 7004 ............... usa ....... 201 575-3510 ....... fai ................................................. 5250 neil road, suite 106 .................................................. ...... reno ......................... nv ............ 89502 ............. usa ....... 715-826-2500 ...... 715-826-2664 all american ................................... 275b marcus blvd. ................................................................... h auppauge ................ ny ............ 11788 ............. usa ....... 516 434-9000 ....... 516-434-9394 all american ................................... 333 metro park ........................................................................ rochester .................. ny ............ 14623 ............. usa ....... 716 292-6700 ....... 716-292-6755 bell microproducts .......................... 1056 west jericho turnpike ..................................................... smithtown .................. ny ............ 11787 ............. usa ....... 516 543-2000 ....... 516-543-2030 edge electronics ............................. 2271-7 fifth avenue .................................................................. ronkonkoma .............. ny ............ 11779 ............. usa ....... 631-471-3343 ...... 631-471-3405 fai ................................................. 6245 sheridan drive, suite 216 ................................................. williamsville .............. ny ............ 14221 ............. usa ....... 716 633-7188 ....... 716-633-7178 fai ................................................. 251 salina meadows parkway, suite 230 ................................... syr acuse ................... ny ............ 13212 ............. usa ....... 315 451-4405 ....... 315 451-2621 future ............................................. 251 salina meadows parkway, suite 210 ................................... syr acuse ................... ny ............ 13212 ............. usa ....... 315 451-2371 ....... 315 451-7258 future ............................................. 300 linden oaks ....................................................................... rochester .................. ny ............ 14625 ............. usa ....... 716 387-9600 ....... 716-387-9596 future ............................................. 3033 express drive north ......................................................... h auppauge ................ ny ............ 11788 ............. usa ....... 516-234-4000 ...... 516-234-6183 north america distributors (continued)
d5 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information company name street address city s tate zip code country telephone fax number nu horizons ................................... 333 metro park ........................................................................ rochester .................. ny ............ 14623 ............. usa ....... 716 292-0777 ....... 716-292-0750 nu horizons ................................... 70 maxess road ...................................................................... mellville ..................... ny ............ 11747 ............. usa ....... 516 396-5000 ....... 516-396-5050 pioneer-standard electronics .......... 3125 veterans memorial highway, meridian plaza iii ................ ronkonkoma .............. ny ............ 11719 ............. usa ....... 516 738-1700 ....... 516-738-1790 pioneer-standard electronics .......... 1249 upperfront, suite 201 ...................................................... bi nghamton ............... ny ............ 13901 ............. usa ....... 607 722-9300 ....... 607-722-9562 pioneer-standard electronics .......... 1250 pittsford/victor road, bldg. 200 ....................................... pittsford ..................... ny ............ 14534 ............. usa ....... 716 389-8200 ....... 716 389-8240 pioneer-standard electronics .......... 60 crossways park west .......................................................... woodbury .................. ny ............ 11797 ............. usa ....... 516 921-8700 ....... all american ................................... 26650 renaissance parkway .................................................... warrenville heights ... oh ............ 44128 ............. usa ....... 216 514-0625 ....... 216-514-0822 bell microproducts .......................... 13971 placid cove ................................................................... strongsville ............... oh ............ 44136 ............. usa ....... 212 846-9156 ....... 212 846-9599 fai ................................................. 6009-i landerhaven drive ........................................................ mayfield heights ........ oh ............ 44124 ............. usa ....... 440 446-0061 ....... 440-446-0062 future ............................................. 1430 oak court, suite 203 ........................................................ beavercreek ............... oh ............ 45430 ............. usa ....... 937 426-0090 ....... 937-426-8490 future ............................................. 6009-e landerhaven drive ........................................................ mayfield heights ........ oh ............ 44124 ............. usa ....... 440 449-6996 ....... 440-449-8987 future ............................................. 6565 davis industrial parkway, unit aa ..................................... s olon ......................... oh ............ 45430 ............. usa ....... 937 426-0090 ....... 937-426-8490 nu horizons ................................... 2208 enterprise e. parkway ...................................................... tow nsburg ................ oh ............ 44087 ............. usa ....... 330 963-9933 ....... 330 963-9944 pioneer-standard electronics .......... 8741 gander creek drive ......................................................... miamisburg ............... oh ............ 45342 ............. usa ....... 937 428-6900 ....... 937-428-6995 pioneer-standard electronics .......... 6065 parkland boulevard .......................................................... mayfield heights ........ oh ............ 44124 ............. usa ....... 440 720 8500 ....... 440 720 8501 pioneer-standard electronics .......... 6675 parkland blvd. .................................................................. s olon ......................... oh ............ 44139 ............. usa ....... 440 519-6200 ....... 440-519-6250 fai ................................................. 7030 south yale, suite 606 ............ ........................................... t ulsa ......................... ok ............ 74136 ............. usa ....... 918 492-1500 ....... 918-492-4848 pioneer-standard electronics .......... 9717 east 42nd street, suite 105 ............................................... t ulsa ......................... ok ............ 74146 ............. usa ....... 918 665-7840 ....... 918-665-1891 all american ................................... 1815 nw 169th place, suite 1040 ............................................. beaverton .................. or ............ 97006 ............. usa ....... 503 531-3333 ....... 503-531-3695 bell microproducts .......................... 14780 sw osprey drive, suite 240 ........................................... beaverton .................. or ............ 97007 ............. usa ....... 503-524-0787 ...... 503-524-1075 fai ................................................. 7204 sw durham road, suite 900 ............................................ portland ..................... or ............ 97224 ............. usa ....... 503 603-0866 ....... 503-603-0960 future ............................................. 7204 sw durham road, suite 800 ............................................ portland ..................... or ............ 97224 ............. usa ....... 503 603-0956 ....... 503-603-0859 nu horizons ................................... 15455 nw greenbrier parkway, suite 135 ................................. beaverton .................. or ............ 97006 ............. usa ....... 503-439-1200 ...... 503-439-6286 pioneer-standard electronics .......... 5665 sw meadows road, suite 150 .......................................... lake oswego ............. or ............ 97035 ............. usa ....... 503-968-6565 ...... 503-598-2555 future ............................................. 103 bradford road, suite 100, stonewood commons ii .............. w exford ..................... pa ............ 15090 ............. usa ....... 724 935-9600 ....... 724-935-9695 pioneer-standard electronics .......... 500 enterprise road, kuth valley business center ................... hor sham ................... pa ............ 19044 ............. usa ....... 215 674-4000 ....... 215 674-3107 pioneer-standard electronics .......... 259 kappa drive ....................................................................... p ittsburgh .................. pa ............ 15238 ............. usa ....... 412 782-2300 ....... 412-963-8255 all american ................................... 13706 research blvd., suite 103 ............................................... austin ........................ tx ............ 78750 ............. usa ....... 512 335-2280 ....... 512 335-2282 all american ................................... 1771 international parkway, suite 101 ........................................ richardson ................ tx ............ 75081 ............. usa ....... 972 231-5300 ....... 972 437-0353 bell microproducts .......................... 12701 research blvd., suite 360 ............................................... austin ........................ tx ............ 78759 ............. usa ....... 512 258-0725 ....... 512-258-6517 bell microproducts .......................... 833 east araphho road, suite 205 ............................................ richardson ................ tx ............ 75081 ............. usa ....... 972 783-4191 ....... 972-783-4192 bell microproducts .......................... 2900 wilcrest, suite 138 ........................................................... houston ..................... tx ............ 77042 ............. usa ....... 713 917-0663 ....... 713-917-0615 edge electronics ............................. 1411 lemay drive, suite 204 .................................................... carrolton ................... tx ............ 75007 ............. usa ....... 972 323 7977 ....... 972-323-8530 fai ................................................. the courtyard, 7500 viscount, suite c75 .................................. el paso ...................... tx ............ 79925 ............. usa ....... 915 779-7484 ....... future ............................................. 7200 north mopac, suite 310 .................................................... aus tin ........................ tx ............ 78731 ............. usa ....... 512-346-6426 ...... 512-346-6781 future ............................................. 2201 west plano parkway, suite 150 ......................................... p lano ......................... tx ............ 75075 ............. usa ....... 469 467-0070 ....... 469-467-0071 future ............................................. 10737 gateway west, suite 330 ................................................ el paso ...................... tx ............ 79955 ............. usa ....... 915-592-3563 ...... 915-592-3818 future ............................................. 10333 richmond avenue, suite 970 .......................................... houston ..................... tx ............ 77042 ............. usa ....... 713-952-7088 ...... 713-952-7098 future ............................................. 7500 viscount, suite c75 ......................................................... el paso ...................... tx ............ 79925 ............. usa ....... 915 595-1000 ....... future ............................................. 800 east campbell road, suite 130 .......................................... richardson ................ tx ............ 75081 ............. usa ....... 972 437-2437 ....... nu horizons ................................... 1313 valwood parkway, suite 200 .............................................. carrollton .................. tx ............ 75006 ............. usa ....... 972 488-2255 ....... 972-488-2265 nu horizons ................................... 2404 rutland drive, suite 100 ................................................... austin ........................ tx ............ 78758 ............. usa ....... 512 873-9300 ....... 512-873-9800 pioneer-standard electronics .......... 10707 corporate drive, suite 106 ............................................. stafford ...................... tx ............ 77477 ............. usa ....... 281-240-4882 ...... 281-240-7897 pioneer-standard electronics .......... 13765 beta road ...................................................................... dallas ....................... tx ............ 75244 ............. usa ....... 972-419-5500 ...... 972-490-6419 pioneer-standard electronics .......... 4030 west breaker lane, suite 175 ........................................... austin ........................ tx ............ 78759 ............. usa ....... 512 340-9500 ....... 512-340-9552 pioneer-standard electronics .......... 959 east collins blvd., suite 102 ............................................... richardson ................ tx ............ 75081 ............. usa ....... 972-808-1900 ...... 972-808-1940 all american ................................... 6955 south union park center, suite 110 .................................. midvale ...................... ut ............ 84047 ............. usa ....... 801-565-8300 ...... 801-565-9983 bell microproducts .......................... 384 north main street .............................................................. centerville ................. ut ............ 84014 ............. usa ....... 801-295-3900 ...... 801-295-3377 future ............................................. 3450 south highland drive, suite 303 ....................................... salt lake city ............. ut ............ 84106 ............. usa ....... 801 467-9696 ....... 801-467-9755 pioneer-standard electronics .......... 6925 union park center, suite 600-24 ...................................... midvale ...................... ut ............ 84047 ............. usa ....... 801-566-8692 ...... 801-566-8719 bell microproducts .......................... 1039 sterling road, suite 204 .................................................. hern don .................... va ............ 20170 ............. usa ....... 703 834-3696 ....... 703-834-3698 fai ................................................. 660 hunters place, suite 202 ............................................... ..... charlottesville ............ va ............ 22911 ............. usa ....... 804 984-5022 ....... all american ................................... 11807 north creek pkwy south, suite 112 ................................. bothell ....................... wa ............ 98011 ............. usa ....... 425-806-4800 ...... 425-806-9900 fai ................................................. 12100 ne 195th street, suite 150 .............................................. bothell ....................... wa ............ 98011 ............. usa ....... 425-485-6616 ...... 425-483-6109 future ............................................. 19102 north creek parkway, suite 118 ...................................... bothell ....................... wa ............ 98011 ............. usa ....... 425 489-3400 ....... 425-489-3411 nu horizons ................................... 8417 154th avenue ne .............................................................. redmond ................... wa ............ 98052 ............. usa ....... 425-861-9200 ...... 425-861-9800 pioneer-standard electronics .......... 2800 156th avenue se, suite 205 .............................................. b ellevue ..................... wa ............ 98007 ............. usa ....... 425-644-7500 ...... 425-644-7300 all american ................................... 18000 sarah lane, suite 145 .................................................... brookfield .................. wi ............. 53045 ............. usa ....... 414 792-0438 ....... 414-792-9733 fai ................................................. 175 north corporate drive, suite 150 ....................................... brookfield .................. wi ............. 53045 ............. usa ....... 414-792-9778 ...... 414-792-9779 future ............................................. 250 n. patrick blvd., suite 170 .................................................. b rookfield .................. wi ............. 53045 ............. usa ....... 414 879-0244 ....... pioneer-standard electronics .......... 120 bishops way, suite 163 ...................................................... brookfield .................. wi ............. 53005 ............. usa ....... 414-780-3600 ...... 414-780-3613 north america distributors (continued)
d6 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information north america representatives company name street address city s tate zip code country telephone fax number bits, inc. ..................................... 2705 artie st., suite 29 .................................... huntsville ................. al ....................... 35805 ....................... usa ......................... 256 534-4020 ........ 256 534-0410 neutronics components ltd. ......... 206 2723-37th avenue ne ................................ calgary .................... alberta ................ t1y 5r8 .................. canada ................. 403 291 4994 ........ 403 291-4717 schefler-kahn company, inc. ........ 21639 north 12th aveune, suite 105 ................. phoenix .................... az ...................... 85027 ....................... usa ......................... 623 581-0884 ........ 623 581-3522 dynarep .. .................................... 2985 e. hillcrest drive, suite 201 .................... thousand oaks ........ ca ...................... 91362 ....................... usa ......................... 805 777 1185 ........ 805 777-9266 dynarep ...................................... 3002 dow avenue, suite 226 ............................ tustin ....................... ca ...................... 92780 ....................... usa ......................... 714 573 1223 ........ 714 573-0778 innovation sales ........................... 6440 lusk blvd., suite d200 ............................. san diego ................ ca ...................... 92121 ....................... usa ......................... 858-535-9300 ...... 858-550-3707 nctr ...... ................................... 46750 fremont blvd., suite 110 ........................ fremont ................... ca ...................... 94538 ....................... usa ......................... 510 624-8900 ........ 510 624-8905 electrodyne .................................. 2620 south park road, suite 395 ..................... aurora ...................... co ...................... 80014 ....................... usa ......................... 303-695-8903 ....... 303 745-8924 component design marketing ...... 1803 park center drive, suite 200 ................... orlando .................... fl ....................... 32835 ....................... usa ......................... 407-522-5808 ....... 407 522-0774 component design marketing ...... 2240 woolbright road, suite 317 .................... boyton beach ............ fl ....................... 33426 ....................... usa ......................... 561 740-3335 ........ 561 740-3635 bits, inc. ..................................... 5425 sugarloaf pkwy., suite 2201 .................... lawrenceville ............ ga ...................... 30043 ....................... usa ......................... 770-513-8610 ...... 770-513-8680 luscombe sales ........................... 6901 emerald, suite 206 .................................. b oise ....................... id ....................... 83704 ....................... usa ......................... 208-377-1444 ....... 208 377-0282 martan, inc. .................................. 1100 woodfield road ...................................... schaumburg ............. il ........................ 60173 ....................... usa ......................... 847 330 3200 ............................ oasis sales corporation .............. 1101 tonne road ............................................ elk grove village ...... il ........................ 60007 ....................... usa ......................... 847 640 1850 ....... 847-640-9432 martan, inc. .................................. 10820 horton .................................................. overland park ........... ks ...................... 66211 ....................... usa ......................... 913 381 3652 ........ 913 381-3653 universal technology ................... 22 a street ...................................................... b urlington ................ ma ...................... 3803 ........................ usa ......................... 781-890-8523 ....... 781 890-8589 avtek associates .......................... 10632 little patuxent parkway, suite 435 .......... c olumbia .................. md ..................... 21044 ....................... usa ......................... 410 740-5100 ....... 410-740-5103 jay marketing assoc. inc. ............. 44752 helm street .......................................... pl ymouth .................. mi ....................... 48170 ....................... usa ......................... 734-459-1200 ...... 734-459-1697 cahill, schmitz & cahill, inc. ........ 897 st. paul avenue ........................................ st. paul .................... mn ..................... 55116 ....................... usa ......................... 651 699 0200 ....... 651-699-0800 martan, inc. .................................. 257 old stone court ....................................... ofallon ................... mo ..................... 63366 ....................... usa ......................... 314 939 3300 ....... 314-447-1371 bits, inc. ..................................... 940 main campus drive, suite 120 .................. raleigh .................... nc ........... ........... 27606 ....................... usa ......................... 919 807 1000 ....... 919-807-1001 bits, inc. ..................................... 3320 silver pond court ................................... charlotte .................. nc ...................... 28810 ....................... usa ......................... 704-540-8185 ...... 704-540-8183 matrix sales ................................. 30 washington avenue suite b-2 ..................... haddonfield .............. nj ...................... 8033 ........................ usa ......................... 856 795 8833 ........ 856 795 0038 neptune electronics/necco ....... 11 oval drive, suite 169 .................................. islandia .................... ny ...................... 11722 ....................... usa ......................... 631-234-2525 ...... 631-234-2707 nycom, inc. ............................... 10 adler drive ................................................. east syracuse .......... ny ...................... 13057 ....................... usa ......................... 315 437-8343 ....... 315-437-1208 electronic device sales ................ 8000 green ridge court ................................. mentor ..................... oh ...................... 44060 ....................... usa ......................... 440 255-7040 ....... 440-255-7093 electronic device sales ................ 6917 rob vern drive ....................................... cincinnati ................. oh ...................... 45239 ....................... usa ......................... 513 729-8440 ....... 513-729-8448 nova marketing ltd. ..................... 3544 adams road ........................................... mounds .................... ok ...................... 74074 ....................... usa ......................... 918-827-5560 ....... 918 827-5561 neutronics components ltd. ......... 232 herzberg road, suite 201 ........................ kanata ...................... ontario ................ k2k 2a1 .................. canada ................. 613-599-1263 ...... 613-599-4750 neutronics components ltd. ......... 240 terence mathews crescent, suite 105 ...... kanata ...................... ontario ................ k2m 2c4 ................. canada ................. 613 599 1263 ............................ neutronics components ltd. ......... 6271 dorman road, suite 18 ........................... mississauga ............ ontario ................ l4v 1h1 .................. canada ................. 905 671 4001 ........ 905 671-4062 electra ...... ................................... 6700 sw 105th avenue, suite 210 .................... bea verton ................. or ...................... 97008 ....................... usa ......................... 503 643 5074 ........ 503 526-2055 astrorep mid atlantic inc. ............. 65 west street road, suite b-203 ................... w arminster .............. pa ...................... 18974 ....................... usa ......................... 215 957 9580 ............................ neutronics components ltd. ......... 189 hymus blvd., suite 604 ............................. pointe claire ............ quebec ............... h9r 1e9 .................. canada ................. 514 428 5838 ....... 514-428-5837 nova marketing ltd. ..................... 10701 corporate drive, suite 370 .................... stafford .................... tx ...................... 77477 ....................... usa ......................... 214-265-4600 ...... 214-265-4668 nova marketing ltd. ..................... 127 pioneer plaza at 127 san francisco ......... el paso .................... tx ...................... 79901 ....................... usa ......................... 915 543-3212 ....... 915-543-3213 nova marketing ltd. ..................... 3520 executive center drive, suite 159 ............ austin ....................... tx ...................... 78731 ....................... usa ......................... 512 343-2321 ....... 512-343-2487 nova marketing ltd. ..................... 508 twilight trail, suite 203 ............................ richardson .............. tx ...................... 75080 ....................... usa ......................... 214-570-3430 ...... 214-570-3435 luscombe sales ........................... 670 east 3900 south, suite 103 ........................ salt lake city ............ ut ...................... 84107 ....................... usa ......................... 801 268-3434 ........ 801 266-9021 electra ...... ................................... 11411 ne 124th sreet, suite 285 ..................... kirkland .................... wa ...................... 98034 ....................... usa ......................... 425 821 7442 ........ 425 821-7289 oasis sales corporation .............. 1305 n. barker road ....................................... brookfield ................. wi ....................... 53045 ....................... usa ......................... 262 782 6660 ........ 262 782-7921
d7 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information international distributors company name ........................................... address ............................................................................................................................... ............................... country ......................... tel ephone all american ................................................. ave. mariano otero, #3431 ber pisco, col. verde valle, guadalajara, jalisco, 44550 .............................................. mexico ................. 011 523 818 4302, all american ................................................. 6375 dixie road, units 4,5,6, mississuaga, on, l5t 2e7 ............ .......................................................................... canada ...................... 905 670-5946 fai ............................................................... 3689 east 1st ave., suite 200, vancouver, br. colum., v5m 1c2 ............................................................................. canada ...................... 604 654-1050 fai ............................................................... 1780 wellington avenue, suite 504, winnipeg, manitoba, r3h 1b2 ........................................................................ canada ..................... 204-786-3075 fai ............................................................... 1000 st. charles blvd., 10th floor, vaudreuil, quebec, j7v 8p5 ............................................................................. canada ...................... 514 457-1487 fai ............................................................... 1000 st. charles blvd., 1st floor, vaudreuil, quebec, j7v 8p5 ............................................................................... canada ...................... 514 457 3004 fai ............................................................... 1101 prince of wales, suite 210, ottawa, ontario, k2c 3w7 ................................................................................... canada ...................... 613 727 8622 fai ............................................................... 1144 29th avenue ne, suite 200, calgary, alberta, t2e 7p1 ................................................................................... canada ...................... 403 291 5333 fai ............................................................... 5935 airport road, suite 205/210, mississauga, ontario, l4v 1w5 ........................................................................ canada ...................... 905 612 9888 fai ............................................................... 237 hymus blvd., point claire, quebec, h9r 5c7 .................................................................................................. canada ...................... 5 14 694-7710 fai ............................................................... 6029 103rd street, edmonton, alberta, t6h 2h3 .................................................................................................... canada ..................... . 708 438 5888 future ........................................................... 1000 st. jean baptiste, suite 201, quebec, quebec, g2e 5g5 ................................................................................ canada ...................... 418 877-1414 future ........................................................... 1101 prince of wales, suite 210, ottawa, ontario, k2c 3w7 ................................................................................... canada ...................... 613 727 1800 future ........................................................... 1144 29th avenue ne, suite 200, calgary, alberta, t2e 7p1 ................................................................................... canada ..................... 403-219-3443 future ........................................................... 26 mer chants square, ennis, country clare .......................................................................................................... ireland ....................... 353 6541330 future ........................................................... 3689 east 1st avenue, suite 200, vancouver, br. colum., v5m 1c2 ........................................................................ canada ...................... 604 294 1166 future ........................................................... 5, avenue albert durand, aeropole 3, 31700 blagnac, toulouse ............................................................................. france .................. 33 5 62 74 72 40 future ........................................................... black and decker str. 17b, idstein, 65510 ............................................................................................................... germany ......... .......... 06126 9321 0 future ........................................................... buschkamp 84, langenhagen, 30853 ..................................................................................................................... germany ... ................ 0511 72562 0 future ........................................................... eur oparc du chene/ 4 rue edison, 69674 bron cedex, lyon .................................................................................... france .................. 44 3 72 15 86 00 future ........................................................... hauert 8, dortmund, 44227 ............................................................................................................................... ..... germany .................. 0231 975048 0 future ........................................................... johannes-daur str. 1, korntal-munchigen, 70825 .................................................................................................. germany .................... 07 11 830830 future ........................................................... kanalvagen 10c, 184 61 upplands vasby .............................................................................................................. sweden ................ 0046 5 590 041 83 future ........................................................... luxemburger str. 35, berlin, 13353 ........................................................................................................................ germany ................... 030 469089 0 future ........................................................... max-weber-strabe 3, quickborn, 25451 ................................................................................................................ germany ........ ........... 04106 7748 0 future ........................................................... munchner strabe 18, unterforhring, 85774 ............................................................................................................ germany ............ ......... 089 95727 0 future ........................................................... parc technolopolis/l.p. 854 les ulis, 3, ave. du canada/ bat theta 2, courtabeuf, cedex, paris, 91974 ................... france ................... 33 1 69 82 1111 future ........................................................... unit 4 blair court, clydebank bus. park, clydebank, glasgow, g811 2rx ............................................................... uk ................................. 041 9511199 future ........................................................... urb. belmonte galicia #45, mayaguez, 00680 ........................................................................................................ puerto rico ............ ....... 787 289-7801 future ........................................................... via fosse ardeatine 4, 20092 cinisello balsamo, milan ............... .......................................................................... italy .............................. 39 2 660941 future ........................................................... wil helm-wolff str. 6, erfurt, 99099 ......................................................................................................................... german y ................... 0361 42087 0 future electronics oy ................................... olarinluoma 7, fon-02200, espoo, helsinki ............................................................................................................ finland ............ .. 011 358 9 525 9950 future electronics ...... ................................... distribution (spain), s.l., avenida d=dek, oarebib 8-10, madrid ............................................................................ spain .......................... 34 1 72 10 762 future electronics ...... ................................... faerch-huset, l1/ ostergade 5.4, dk-7500 holstebro ......................................... ................................................. denmark ................... 45 961 00961 future electronics as .................................... gpi building, karihaugveien 89, 1086 oslo ............................................................................................................ norway ................ 011 47 22 90 5800 future electronics b.v. .................................. tinstaat 3, 4823aa breda ............................................................................................................................... ....... netherlands ........... 011 31 64 571 2497 future electronics inc. ................................... 103 medinat hayeudim street, p.o. box 2219, herzliya, 46120 ................................................................................ israel ...................... 972 999 586555 future electronics kft- hungary .................. burok utca 34, j-1124, budapest ............................................................................................................................ hun gary ............. 011 36 1 458 5690 future electronics polska .............................. spolka z.o.o u1 panienska 9, 03-704 warsaw ........................................................................................................ poland ............... 011 48 22 618 9202 future electronics srl ................................. galleria camillo ronzani 3/9, casalecchio di reno, bologna, 40033 ...... .............................................................. italy ............................. 051 6136700 future electronics srl ................................. via domenico turazza, 30, 31528 padova ............................................................................................................. italy ............. .............. 049 899 20111 future electronics de mexico ........................ calle paplot #92 bis, col. san martin, xochinahuac, mexico, d. f., 2210 .... ............................................................ mexico .......................... 5-382-4106 future electronics de mexico ........................ chimalhuacan #3569, 4 piso, suite 6 ciudad del sol, zapopan, jalisco, 45050 .................................................... ... mexico .................. 011523 122-0043 future electronics de mexico ........................ col. bosques del alba, cuautitlan, ixcalli, estado de mexico, 54769 ....................................................................... mexico ........................... 5 893 5764 future electronics de mexico ........................ futbol #173-11, col. country club, mexico, d.f., ,04220 ........................................................................................ mexico ........................... 5 689 3340 future electronics de mexico ........................ torre gia piso 8, av. morones prieto , #2805 pte., col. loma larga, monterr ey, n.l., 64710 ................................... mexico .......................... 8-399-0027 future-birminham .......................................... 1st floor 3 hagley court north, waterfront east, brierley hill, w. midlands, dy5 1xf . ........................................... uk ............................... 01384 482 555 future-brazil ................................................ rua luzitana, 740 10 andar, conj 103/104, 13014-121, compinas, sp .................................................................... brazil ................. 011 55 19 232 1511 future-manchester ........................................ adamson house, throstle nest lane, pomona strand, manchester, m16 0tt ......................................................... uk ................................ 44 61 876000 pioneer-standard canada .............................. 10711 cambie road, suite 170, richmond, bc, v6x 3g5 ....................................................................................... canada ...................... 604 273-5575 pioneer-standard canada .............................. 223 colonnade road, unit 100, nepean, on, k2e 7k3 ........................................................................................... canada ...................... 613 226-8840 pioneer-standard canada .............................. 148 york street, suite 209, london, on, n6a 1a9 .................................................................................................. canada ..................... 90 5-405-8300 pioneer-standard canada .............................. 240 graham avenue, suite 808, winnipeg, manitoba, r3c 0j7 ............................................................................... canada ...................... 204 989-1957 pioneer-standard canada .............................. 3415 american drive, mississauga, on, l4v 1t6 .................................................... ............................................. canada ...................... 905 405-8300 pioneer-standard canada .............................. 520 mccaffrey street, ville st. laurent, qc, h4t 1n1 ............................................. ............................................... canada ...................... 514 737-9700 pioneer-standard canada .............................. place iberville iv, 2954 blvd. laurier, suite 100, ste. foy, qc, g1v 4t2 .................................................................. canada ...................... 418 654-1078 pioneer-standard electronics ........................ kuth valley bus. ctr, 500 enterprise road, horsham, pa, 19044 ............................................................................ canada ...................... 215 674-4000
d8 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information international representatives company name address country telephone acetronix ....................................................... 1st floor ashiville palace 31-13 hap-dong, sudaimoon-ku, seoul, 120-030 ................................................ korea ................................ 82-2-796-4561 alcom electronics .......................................... single 3, 2550 kontich belgium ....................................................... .............................................................. belgium .......................... 011 323 458 3033 alcom electronics bv .................................... rivian le straat 52, 2909 le, capelle aan den yssel ........................................ ................................................ netherlands .......................... 31 10 28 82 500 ambar cascom, ltd. ... ................................... the gatehouse, alton house business park, gatehouse way, aylesbury bucks, hp19 3dl ............................. uk ......................................... 01296-434141 boran technologies ltd. ................................ dynacom division, p.o. box 2627, petach tikva, 49125 ................................................................................... israel ................................ 972-3927-4747 braemac pty. ltd. ........................................... unit 1, 59-61 b urrows road, alexandria nsw, 2015 ....................................................................................... australia .......................... 612 9550 6600 chin shang electronics corp. ....................... 4f, no. 18, alley 1, lane 768, sec 4, pa te road, taipei .................... ............................................................ taiwan ............................ 886-2-2-7885470 communica (pty) ltd. .................................. sunnyside 0132 pretoria 0002 ....................................................................................................................... south africa ..................... 011 27 12 33 27613 component design marketing ....................... calle huca #38 bajos bo sabanetas mercedita dr. 00715 ................................................... .......................... puerto rico ............................ 787 844-3840 deltek ........................................................... block 1 unit a3, templeton bus. centre, templeton st., glasgow, g40 1da ................................................... scotland ......................... 0141-556-7233 desner electronics co. ltd. ........................... 4th floor, na-nakorn building, 99/ 349 changwattana rd. 10210 bangkok, laksi, bangkok, 10210 .................... thailand ........................... 662 -576 1500-1 desner electronics, far east pte, ltd. .......... 42 mactaggart road, #04-01, mactaggart building, singapore, 368086 ............. ............................................ singapore ............................. 65-2851566 desner sdn bhd ......................................... no 9, jalan pjs 8/9, bandar sunway, 46150 selangor, kuala lumpur, 46150 ................................................... malaysia ........................... 603-7877 6211 desner sdnbhd ......................................... no.36b jalan tun dr. awang 11900 pulau pinang, pulau pinang, 11900 ........................................................ malaysia ............................. 604-641-1288 eec international (hk) ltd. ............................ room 805 8/f hunghom comm. ctr., tower b, 37-39 ma tau wai road, hunghom, kowloon .......................... hong kong ...................... 011 852 2365 7775 eec technology (s) pte. ltd. ........................ 10 upper aljunied link , #04-01, york intl industrial bldg., singapore, 367904 ................................................. singapore ............................. 65 283 0822 elitetron electronic co. ltd ............................ 4f, 70 cheng kung road, sec. 1 , nankang, taipei ....................... ................................................................ tai wan, r.o.c. .............. 011 886 2 27893300 elitetron electronic co. ltd. ............................ 4f, 70 cheng kung road, section 1, nankang, taipei .................... ............................................................... tai wan, r.o.c. .............. 011 886 2 27893300 epco technology co., ltd. ........................... 10 f, 268, sec. 2, fu-hsing s. rd., taipei .......................................................... ........................................... taiwan .............................. 886 2 2737 3507 fmg electronics ltd. ..................................... garden row, william street, kilkenny ............................................................................................................ ireland ............................... 353-56-64002 gd technik ................................................... tudor house, 24 high street, twyford berks, rg10 9ag ........................ ....................................................... uk ................................... 011441189 342277 gd technik ................................................... u nit 20, blackburn technology mgmt. cntre, challenge way, blackburn, bb1 5qb ........................... .............. uk .......................................... 01254 679831 golden rich technologies ............................ unit 1006, 10/f tower ii, enterprise square, 9 sheung yuet road, kowloon bay ............................................. hong kong ...................... 852 2751-8840 heko electronikk & data a/s ............................ l-rdagsrudeveien 24, fjellhamar, 1472 .......................................................................................................... norway ............................. 47-67-90-52-44 hy-line computer components ...................... inselkammerstrasse 10, unterhaching, 82008 ................................................................................................ germany ................ 011-49-89-614503-40 i&c microsystems,co.ltd .............................. 8th floor, bethel bldg., 324-1, yangjae-dong, seocho-ku , seoul .................................. ............................. korea ................................ 82-2-577-9131 internix inc. (hachioji branch) ........................ 59-10 takakura-cho, hachioji-shi, tokyo, 192-0033 ........................................................................................ japan ................................. 81-426-448786 internix inc. (head office) .............................. shinjuku hamada bldg., 3f 7-4-7, nishishinjuku, shinjuku-ku, tokyo, 160-8388 ............................................... japan ............................... 81-3-3369-1105 leading technologies ................................... 99 route de versailles, champlan, 91160 ...................................................................................................... france ................... ......... 33 01 69 79 9350 leading technologies italia srl ................... via flume 13, 1-20059 vimercate (mi) ......................................... ................................................................. italy ................................... 39 39 66 13 108 mcm japan ltd. ............................................ 2-11-2 sun tower center bldg., sangenjaya, setagaya-ku, tokyo, 154-8539 .................................................. japan ................................ 81-3-3487-8477 micro summit k.k. ...... ................................... premier ki building, 1 kanda, mikura-cho, chiyoda-ku, tokyo, 101-0038 ......................................................... japan ................................... 03-3258-5531 micro summit singapore pte. ltd ................... blk 13 braddell tech, #03-02 , toa payoh lorong 8, singapore, 319261 .......................................................... singapore ............................. 65-2522677 microelectronic visions inc. ........................... 2812 garden creek circle, pleasanton, ca, 94588 ......................................................................................... uk .................................... ...... 510 485-0710 milgray distribution gmbh ........................... allmendstrasse 28, po box 68, 2562 port switzerland .................................................................................... switzerland .............. 011 41 3233 12064 neutronics components ltd. .......................... 189 hymus components, suite 604, pointe claire, quebec, h9r 1er ............................................................ canada ................................. 514 428 5838 neutronics components ltd. .......................... 206 2723-37th avenue ne, calgary, alberta, t1y 5r8 .................................................................................... canada ................................. 403 291 4994 neutronics components ltd. .......................... 240 terence matthews crescent, suite 105, kanata, ontario, k2m 2c4 ......................................................... canada ................................. 613 599 1263 neutronics components ltd. .......................... 6271 dorman road, unit # 18, mississauga, ontario, l4v 1h1 ........................................... ........................... canada ................................. 905 671 4001 newtek .......................................................... 8 rue de lesterel, silic 583, rungis cedex, 94663 ................... ................................................................... france .................................. 1-468-72200 newtek italia spa ........................................... via cassiodoro 16, milano, 20145 ................................................................................................................. italy ........................................ 02-4692156 pan american technical sales ....................... av. avila camacho no. 2275-1, col. country club, c.p. 44610 , zapopan, jalisco ........................................... mexico ... ........................... 011 52 3 824 9999 pan american technical sales ....................... 6624 cresta bonita, el paso, tx, 79912 ........................................................................................................ usa .................... .................... 915 532 1900 pan american technical sales ....................... av. morones prieto #2805 pte. col. loma largo, c.p. 64710, monterrey, nuevo leon ...................................... mexico ... ........................... 011 52 8 399 0024 pan american technical sales ....................... 8100 shoal creek blvd., suite 250, austin, tx, 78757 ..................................................................................... usa ....................................... . 512 371 7272 pangaea international trading corp. ............. unit 703, alabang business center, madrigal business park, ayala alabang, muntinlupa city, 1780 ............... philippines .......................... 632 807 8429 rti industries co., ltd. .................................. room 402, nan fung commercial centre, no 19. lam lok street, kowloon bay .............................................. hong kong ...................... 852-279-57421 silicon concepts ........................................... pbc lynchborough road, passfield, liphook, hampshire, hampshire ..................... ............. uk .......................................... 01428 751617 silicon highway ............................................. 4b saturn house, calieva park, aldermaston,, berkshire, rg7 8ha ............................................................... uk ........................................... 01189816888 spectra innovations inc. ................................. 780 mo ntague expressway, suite 208, san jose, ca, 95131-1316 .................................................................. usa ..................................... (408) 954-8474 spectra innovations inc. ................................. s-822, manipal centre, 47, dickenson road, bangalore, 560 042 ................................................................... india .................................. 91-80-558-8323 sunrise corporation ... ................................... unit 802, daesung bldg. 775-3 daerim-3dong, youngdeungpo-ku, seoul ................................................... korea ................................... 822 844 2328 techmosa international inc. ............................ 4f, no. 18, alley 1, lane 768, sec 4, pa te road, taipei ........................................... ..................................... taiwan ............................ 886-2-2-7822288
d9 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 21234567 pi7c7100 3-port pci bridge advance information notes
d10 09/18/00 rev 1.1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456 pi7c7100 3-port pci bridge advance information notes

▲Up To Search▲

Price & Availability of PI7C7100CNA

	To Download PI7C7100CNA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .