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ds04-13213-1e fujitsu semiconductor data sheet linear ic converter cmos d/a converter for digital tuning (compatible with i 2 c bus) MB88141A n n n n description the fujitsu MB88141A is an 8-bit d/a converter with 12 built - in channels. the 12 analog output channels have built-in op amps, providing large current drive capability. data input is compatible with i 2 c specifications, and is controlled by two control lines. the built-in i/o expander function allows the MB88141A to be controlled by devices incompatible with i 2 c bus specifications (provides conversion between i 2 c serial and 8- or 4-bit parallel i/o). the MB88141A is ideal for replacing electronic knob or pre-set variable resistance tuning devices. n n n n features ? ultra-low power consumption (0.9 mw/channel typ.) ? ultra-compact package ? built-in 12-channel r-2r type 8-bit d/a converter ? built-in analog output amplifier (maximum sink current 1.0 ma, maximum source current 1.0 ma) ? analog output range 0 v to v cc (continued) n n n n packages 24-pin plastic dip 24-pin plastic sop 24-pin plastic ssop (dip-24p-m02) (fpt-24p-m01) (fpt-24p-m03) purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
MB88141A 2 (continued) ? 5 v single power supply ? power supply/gnd for mcu interface and op amp is separate from power supply/gnd for d/a converter ? power supply for d/a converter is divided into two systems for v ddi /v ssi (ao1 to ao4) and v dd2 /v ss2 (ao5 to ao12) , allowing separate level settings for each system ? compatible with serial data input, i 2 c specifications ? built-in i/o expander function (converts between i 2 c serial and 8-or 4-bit parallel) ? cmos process ? packages : dip 24-pin, sop 24-pin, ssop 24-pin
MB88141A 3 n n n n pin assignment (top view) (dip-24p-m02) (fpt-24p-m01) (fpt-24p-m03) 1 2 3 4 5 6 7 8 9 10 11 12 gnd vss1 vdd1 sda scl mod cs2 cs1 cs0 vdd2 vss2 vcc 24 23 22 21 20 19 18 17 16 15 14 13 ao1 ao2 ao3 ao4 ao5/d7 ao6/d6 ao7/d5 ao8/d4 ao9/d3 ao10/d2 ao11/d1 ao12/d0
MB88141A 4 n n n n pin description *1: the mod and cs0-cs2 pins should be used with fixed level input. *2: when using the i/o expander function together with the d/a converter function, take care that d/a converter output precision is within a range that will not affect overall system operation. pin no. symbol circuit type i/o description 21 sda c i/o i 2 c bus data input/output pin (hysteresis input). outputs the acknowledge signal. 20 scl b i i 2 c bus shift clock input pin (hysteresis input) . 19 mod a i d/a converter and i/o expander mode switching pin. * 1, * 2 input l to operate as a d/a converter, h to operate as i/o expander and d/a converter. 16 17 18 cs0 cs1 cs2 ai these pins set the lower 3 bits of the slave address. * 1 this allows up to eight MB88141A chips to be used on the same bus line. 1 2 3 4 ao1 ao2 ao3 ao4 d o 8-bit d/a outputs with op amp. * 2 5 6 7 8 9 10 11 12 ao5/d7 ao6/d6 ao7/d5 ao8/d4 ao9/d3 ao10/d2 ao11/d1 ao12/d0 ei/o 8-bit d/a outputs with op amp. * 2 in i/o expander operation, these pins function as parallel data in- put/output pins. 13 vcc power supply ? power supply pin for digital circuits and op amp. 24 gnd gnd ? gnd pin for digital circuits and op amp. 22 vdd1 power supply ? reference power supply pin for d/a converter (h) . ao1 to ao4. 23 vss1 power supply ? reference power supply pin for d/a converter (l) . ao1 to ao4. 15 vdd2 power supply ? reference power supply pin for d/a converter (h) . ao5 to ao12. 14 vss2 power supply ? reference power supply pin for d/a converter (l) . ao5 to ao12.
MB88141A 5 n n n n block diagram -+ -+ -+ -+ 8 d7/ao5 ao1 ao4 d0/ao12 vcc gnd vdd1 vss1 sda scl cs2 cs1 cs0 mod vdd2 vss2 1 ch 4 ch 5 ch 12 ch d0 d7 d0 d7 d0 d7 d0 d7 i 2 c bus interface d/a & i/o control logic 8-bit latch r-2r ladder circuit 8-bit latch r-2r ladder circuit 8-bit latch r-2r ladder circuit 8-bit latch r-2r ladder circuit
MB88141A 6 n n n n i/o circuit type (continued) type circuit remarks a input dedicated pin b input dedicated pin ?i 2 c bus pin ? hysteresis input c input/output pin ?i 2 c bus pin ? hysteresis input ? n-ch open drain output d analog output pin pch tr nch tr digital input pch tr nch tr digital input pch tr nch tr digital output digital input pch tr nch tr analog output analog output analog feedback
MB88141A 7 (continued) note : circuit types b and c are i 2 c bus pins. caution should be taken in using these pins because when the vcc power is off current from the i 2 c bus line power supply vccs can enter the vcc side of the device power supply. type circuit remarks e analog/digital input/output pin pch tr nch tr analog/digital output analog/digital output analog feedback digital input mode control vccs vccs vcc vcc vcc MB88141A sda (i 2 c bus line) scl (i 2 c bus line)
MB88141A 8 n n n n data configuration the MB88141A has the following data configuration the two operating modes (d/a converter (12-channel) and i/o expander plus d/a converter), selected by the mod pin. 1. for d/a converter (12-channel) operation (mod = = = = l) (1) i 2 c bus format (2) slave address comparison (7 bits) address comparison: operates only for devices whose own slave address (internally fixed cs6 to cs3 and externally set cs2 to cs0) matches the slave address input value. (3) r/w selection (1 bit) fixed at 0 (the d/a converter performs write operations only) . first s6 s0 r/w c7 c0 d7 d0 last s slave address (7 bits) 0a channel selection (8 bits) a d/a data (8 bits) a p : sent from master device : sent from MB88141A (slave device) s : start condition p : stop condition a : acknowledge output slave address input (7 bits) internally fixed externally set s6 s5 s4 s3 s2 s1 s0 cs6 cs5 cs4 cs3 cs2 cs1 cs0 1001000 = 1001000 1001001 = 1001001 1001010 = 1001010 1001011 = 1001011 1001100 = 1001100 1001101 = 1001101 1001110 = 1001110 1001111 = 1001111
MB88141A 9 (4) channel selection (8 bits) : dont care *1: the 1 byte of data following the channel selection is set on all channels (all channels set to same data value) . *2: the 12 bytes of data following the channel selection are set on all channels (all channels set to separate data values) . note: setting will repeat, continuing in order from ch1, until the start and stop conditions are acknowledged. (5) d/a data (8 bits) note: v ref = v dd - v ss c7 c6 c5 c4 c3 c2 c1 c0 channel select 0 0 0 0 all channels selected * 1 0 0 0 1 ao1 selected 1 1 0 0 ao12 selected 1101 dont care 1110 dont care 1 1 1 1 all channels selected * 2 s slave address (7 bits) 0a x x x x 0 0 0 0 a d/a data (8 bits) a p : sent from master device : sent from MB88141A (slave device) s : start condition p : stop condition a : acknowledge output d7 d6 d5 d4 d3 d2 d1 d0 d/a output 00000000 @ v ss 00000001 @ (v ref / 256) 1 + v ss 00000010 @ (v ref / 256) 2 + v ss 11111110 @ (v ref / 256) 254 + v ss 11111111 @ (v ref / 256) 255 + v ss ~ ~ ~ ~ ~ ~ ~ ~ ~ s slave address 0a x x x x1 1 1 1 a ao1 data a ao12 data a p ~ ~ ~ ~ ~ ~ ~ ~ ~
MB88141A 10 2. for d/a converter + i/o expander operation (mod = = = = h) (1) i 2 c bus format (2) slave address comparison (7 bits) slave address comparison is the same as for d/a converter (12-channel) operation (see 1. (2) slave address comparison), with the exception that the cs2 setting determines the number of d/a converter channels and the number of i/o expander bits. when cs2 = 1 is selected, the upper 4 bits (d7 to d4) of write operations (i 2 c bus to parallel interface) are ignored, and the upper 4 bits of read operations (parallel interface to i 2 c bus) are output at 0 (low) . (3) r/w selection (1 bit) first s6 s0 r/w d7 d0 last s slave address (7 bits) 1 a digital data (8 bits) a p first s6 s0 r/w c7 c0 d7 d0 last s slave address (7 bits) 0a channel selection (8 bits) a digital data (8 bits) a p : sent from master device : sent from MB88141A (slave device) s : start condition p : stop condition a : acknowledge output cs2 d/a converter i/o expander 0 4 channels (ao1 to ao4) 8 bits (d7 to d0) 1 8 channels (ao1 to ao8) 4 bits (d3 to d0) r/w i/o expander operation d/a converter operation 0i 2 c bus input ? parallel data output i 2 c bus input ? analog output 1 parallel data input ? i 2 c bus output ?
MB88141A 11 (4) channel selection (8 bits) ( ): when using d/a converter 8 channel, i/o expander 4 bit operation. : dont care (5) d/a data (8 bits) same as 1 (5) d/a data (8 bits). (6) i/o expander continuous operation i 2 c bus input ? parallel data output c7 c6 c5 c4 c3 c2 c1 c0 channel select 0 0 0 0 i/o expander operation 0 0 0 1 ao1 selected 0 1 0 0 ao4 selected 0 1 0 1 dont care (ao5 selected) 1 0 0 0 dont care (ao8 selected) 1001 dont care 1110 dont care 1 1 1 1 i/o expander continuous operation ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ note: in continuous operation, operation continues until start and stop conditions are acknowledged. parallel data input ? i 2 c bus output s slave address 0a x x x x1 1 1 1 a digital data a digital data a p s slave address 1 a digital data a digital data a digital data a p : sent from master device : sent from MB88141A (slave device) s : start condition p : stop condition a : acknowledge output
MB88141A 12 n n n n timing diagram (i 2 c bus specifications) n n n n analog output voltage range note: ? the sda input acknowledge response (ack) is an output signal from the MB88141A. ? the d0-d7 input and output timing represent the timing of switching to write and read operations respectively. also, d0-d7 input remains in hiz state between the end of a read operation and the acknowledgment of the next i/o write signal. s6 12345 6789 10 11 12 17 18 19 20 26 27 s5 s4 s3 s2 s1 s0 r/w ack c7 c6 c5 c0 ack ack d7 d6 d0 dx ack d7 d6 d5 d0 d0 d7 d7 d6 "start" condition data change "acknowledge" response "acknowledge" response "acknowledge" response "stop" condition sda input scl input ao1 to ao12 d0 to d7 output d0 to d7 input sda output hiz state hiz state analog output hiz input load data load data "acknowledge" response digital output delay delay vdd1&vdd2 vss1&vss2 vcc ( = vdd1 , vdd2) gnd ( = vss1 , vss2) r-2r ladder circuit operating amp circuit analog output range
MB88141A 13 n n n n absolute maximum ratings *: v cc 3 v dd1 3 v ss1 , v cc 3 v dd2 3 v ss2 warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol conditions rating unit min. max. supply voltage v cc with reference to gnd, at ta = + 25 c - 0.3 + 7.0 * v v dd - 0.3 + 7.0 * v v ss - 0.3 + 7.0 * v input voltage v in - 0.3 v cc + 0.3 v output voltage v out - 0.3 v cc + 0.3 v power consumption p d ?? 250 mw operating temperature ta ?- 20 + 85 c storage temperature tstg ?- 55 + 120 c parameter symbol conditions value unit min. typ. max. supply voltage 1 v cc ? 4.50 5.00 5.50 v gnd ?? 0 ? v supply voltage 2 v dd1 v cc 3 v dd1 > v ss1 v dd1 - v ss1 3 2.0 v 2.00 ? v cc v v ss1 0.00 ? 3.50 v supply voltage 3 v dd2 v cc 3 v dd2 > v ss2 v dd2 - v ss2 3 2.0 v 2.00 ? v cc v v ss2 0.00 ? 3.50 v analog output current i al source current 0 ? 1.00 ma i ah sink current 0 ? 1.00 ma oscillator limit output capacitance c ol ??? 1.00 m f digital data setting range ?? #00 ? #ff ? operating temperature ta ?- 20 ?+ 85 c
MB88141A 14 n n n n electrical characteristics 1. dc characteristics (1) digital circuits (vcc = + 5 v 10 % , gnd = 0 v, ta = - 20 c to + 85 c) (2) analog circuits 1 (vcc = + 5 v 10 % , gnd = 0 v, ta = - 20 c to + 85 c) parameter symbol pin name conditions value unit min. typ. max. supply voltage v cc vcc ? 4.50 5.00 5.50 v supply current i cc scl = 400 khz, no load ? 1.00 3.70 ma input leak current i ilk sda, scl cs0, cs1 cs2, mod d0 to d7 v in = 0 to v cc - 10 ?+ 10 m a l level input voltage v il ? 0 ? 0.30 v cc v h level input voltage v ih ? 0.70 v cc ? v cc v input hysteresis width v hys sda, scl ? 0.05 v cc ?? v h level output voltage v oh d0 to d7 i oh = - 400 m av cc - 0.4 ?? v l level output voltage v ol1 i ol = 2.5 ma ?? 0.40 v ol2 sda i ol = 3.0 ma ?? 0.40 v v ol3 i ol = 6.0 ma ?? 0.60 parameter symbol pin name conditions value unit min. typ. max. current consumption i dd vdd1, vdd2 no load i dd = i dd1 + i dd2 ? 1.20 2.50 ma analog voltage v dd v dd1 - v ss1 3 2.0 v v dd2 - v ss2 3 2.0 v 2.0 ? v cc v v ss vss1, vss2 gnd ? 3.5 resolution res ao1 to ao12 no load v dd1 ,v dd2 v cc - 0.1 v v ss1 ,v ss2 3 0.1 v ? 8 ? bit monotonic increase rem ? 8 ? bit non-linearity error le - 1.5 ?+ 1.5 lsb differential linearity error d le - 1.0 ?+ 1.0 lsb
MB88141A 15 non-linearity error : error in the input/output curve with respect to a straight line connecting output voltage at 00 and output voltage at ff levels. differential linearity error : deviation from ideal voltage with respect to a 1-bit increase in digital value. (3) analog circuits 2 (vcc = vdd1 = vdd2 = + 5 v, gnd = vss1 = vss2 = 0 v, ta = - 20 c to + 85 c) parameter symbol pin name conditions value unit min. typ. max. output minimum voltage 1 v aol1 ao1 to ao12 i al = 0 m a digital data 00 v ss ? v ss + 0.1 v output minimum voltage 2 v aol2 i al = 500 m av ss - 0.2 v ss v ss + 0.2 v output minimum voltage 3 v aol3 i ah = 500 m av ss ? v ss + 0.2 v output minimum voltage 4 v aol4 i al = 1.0 ma v ss - 0.3 v ss v ss + 0.3 v output minimum voltage 5 v aol5 i ah = 1.0 ma v ss ? v ss + 0.3 v output maximum voltage1 v aoh1 i al = 0 m a digital data ff v dd - 0.1 ? v dd v output maximum voltage2 v aoh2 i al = 500 m av dd - 0.2 ? v dd v output maximum voltage3 v aoh3 i ah = 500 m av dd - 0.2 v dd v dd + 0.2 v output maximum voltage4 v aoh4 i al = 1.0 ma v dd - 0.3 ? v dd v output maximum voltage5 v aoh5 i ah = 1.0 ma v dd - 0.3 v dd v dd + 0.3 v v aoh v aol # 00 # ff ideal linearity non-linearity error digital setting analog output note: v aoh and v dd , as well as v aol and vss are not necessarily the same values.
MB88141A 16 2. ac characteristics *3 : the i/o expander input open time value applies to a read operation following an i/o write operation, or to an i/o write operation following a read operation. parameter symbol con- dition value unit standard mode high-speed mode min. max. min. max. scl clock frequency f scl ? 0 100 0 400 khz bus free time between stop condition and start condition t buf ? 4.7 ? 1.3 ? m s hold time (resend) start condition. the first clock pulse is generated after this interval. t hd ; sta ? 4.0 ? 0.6 ? scl clock low hold time t low ? 4.7 ? 1.3 ? scl clock high hold time t high ? 4.0 ? 0.6 ? resend start condition setup time t su ; sta ? 4.7 ? 0.6 ? data hold time t hd ; dat ? 0 ? 00.9 data setup time t su ; dat ? 250 ? 100 ? ns sda and scl signal fall time t r ?? 1000 20 + 0.1 cb 300 sda and scl signal rise time t f ?? 300 20 + 0.1 cb 300 stop condition setup time t su ; sto ? 4.0 ? 0.6 ?m s pulse width of spike suppressed by input filter t sp ?? ? 050 ns output fall time when bus capacitance is between 10 pf and 400 pf sink current 3ma t of ?? 250 20 + 0.1 cb 250 sink current 6ma ?? ? 20 + 0.1 cb 250 i 2 c bus line capacitance load cb ?? 400 ? 400 pf d/a analog output settling time t dl ; ao *1 ? 100 ? 100 m s i/o expander digital output delay time t dl ; do *2 ? 300 ? 300 ns input open time t dz ; di *3 200 ? 200 ? digital input setup time t su ; di ? 250 ? 100 ? digital input hold time t hd ; di ? 0.9 ? 0.9 ?m s *1: load condition 1 *2: load condition 2 c al = 50 pf r al = 10 k w dut measurement point c al = 50 pf dut measurement point
MB88141A 17 ? input / output timing t buf t dz ; di t dz ; di t dl ; do t dl ; ao t su ; di t hd ; di t high t low t r t f t su ; sto t hd ; sta t su ; dat t hd ; dat t su ; sta t hd ; sta t sp p p s 9 18 sr 90% 10% sda scl d0 to d7 d0 to d7 ao1 to ao12 acknowl- edge acknowl- edge digital input digital output digital input analog output note: the discrimination levels are 70 % and 30 % of v cc .
MB88141A 18 n n n n ordering information part number package remarks MB88141Ap 24-pin plastic dip (dip-24p-m02) MB88141Apf 24-pin plastic sop (fpt-24p-m01) MB88141Apfv 24-pin plastic ssop (fpt-24p-m03)
MB88141A 19 n n n n package dimensions (continued) 24-pin plastic dip (dip-24p-m02) dimensions in mm (inches) c 1994 fujitsu limited d24015s-2c-3 0.45?.08 (.018?003) index-2 2.54(.100) typ ?.30 +0.20 30.20 15?ax 0.51(.020)min (.010?002) 0.25?.05 1.50 +0.50 ? 1.27(.050) max index-1 ? +0.50 0.98 +.020 ? .039 1.189 ?012 +.008 13.55?.25 (.533?010) 4.96(.195) 3.00(.118) .059 ? +.020 15.24(.600) typ max min
MB88141A 20 (continued) (continued) 24-pin plastic sop (fpt-24p-m01) dimensions in mm (inches) c 2000 fujitsu limited f24007s-3c-5 0.13(.005) m "a" 0.68(.027)max 0.18(.007)max 0.20(.008) 0.50(.020) details of "a" part 0.45?.10 0.05(.002)min 7.80?.40 5.30?.30 0.50?.20 (.020?008) (stand off) (.018?004) (.209?012) (.307?016) .600 ?008 +.010 ?.20 +0.25 15.24 .006 ?001 +.002 ?.02 +0.05 0.15 .268 ?008 +.016 ?.20 +0.40 6.80 index typ 1.27(.050) 13.97(.550)ref 2.25(.089)max (mounting height) 0.10(.004)
MB88141A 21 (continued) 24-pin plastic ssop (fpt-24p-m03) note) * marked dimensions do not include resin residues. dimensions in mm (inches) c 2000 fujitsu limited f24018s-2c-3 0.50?.20 (.020?008) 0.10?.10(.004?004) (stand off) 0 10 details of "a" part 7.75?.10(.305?004) 0.65?.12(.0256?0047) 7.15(.281)ref 6.60(.260) 5.60?.10 nom 7.60?.20 (.220?004) (.299?008) "a" .006 ?001 +.002 ?.02 +0.05 0.15 .049 ?004 +.008 ?.10 +0.20 1.25 .009 ?002 +.004 ?.05 +0.10 0.22 index * * (mounting height) 0.10(.004)
MB88141A fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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