document number: 94542 for technical ques tions within your region, please cont act one of the following: www.vishay.com revision: 12-may-10 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com 1 power mosfet, 40 a FC40SA50FKP vishay semiconductors features ? low gate charge q g results in simple drive requirement ? improved gate, avalanche and dynamic dv/dt ruggedness ? fully characterized capacitance and avalanche voltage and current ?low r ds(on) ? fully insulated package ? ul pending ? compliant to rohs directive 2002/95/ec ? designed and qualified for industrial level applications ? switch mode power supply (smps) ? uninterruptible power supply ? high speed power switching ? hard switched and high frequency circuits notes (1) repetitive rating ; pulse width limited by maximum junction temperature (see fig. 11) (2) i sd 40 a, di/dt 150 a/s, v dd v (br)dss , t j 150 c notes (1) starting t j = 25 c, l = 1.55 mh, r g = 25 , i as = 40 a, dv/dt = 5.5 v/ns (see fig. 12a) (2) repetitive rating ; pulse width limited by maximum junction temperature (see fig. 11) product summary v dss 500 v r ds(on) (typical) 0.084 i d 40 a type modules - mosfet package sot-227 sot-227 absolute maximum ratings parameter symbol test conditions max. units continuous drain current, v gs at 10 v i d t c = 25 c 40 a t c = 100 c 26 pulsed drain current i dm (1) 160 power dissi pation p d t c = 25 c 430 w linear derating factor 3.45 w/c gate to source voltage v gs 30 v peak diode recovery dv/dt dv/dt (2) 9.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c avalanche characteristics parameter symbol typ. max. units single pulse avalanche energy e as (1) - 1240 mj avalanche current i ar (2) -40a repetitive avalanche energy e ar (2) -43mj
www.vishay.com for technical qu estions within your region, please contact one of the fo llowing: document number: 94542 2 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com revision: 12-may-10 FC40SA50FKP vishay semiconductors power mosfet, 40 a note (1) pulse width 300 s; duty cycle 2 % notes (1) pulse width 300 s; duty cycle 2 % (2) c oss eff. is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80 % v dss thermal resistance parameter symbol typ. max. units junction to case r thjc -0.29 c/w case to sink, flat , greased surface r thcs 0.05 - static characteristics (t j = 25 c unless otherwise noted) parameter symbol test conditi ons min. typ. max. units drain to source breakdown voltage v( br)dss v gs = 0 v, i d = 250 a 500 - - v breakdown voltage temperature coefficient v (br)dss / t j reference to 25 c, i d = 1 ma - 0.60 - v/c static drain to so urce on-resistance r ds(on) (1) v gs = 10 v, i d = 24 a - 0.084 0.10 gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 3.0 - 5.0 v drain to source leakage current i dss v ds = 500 v, v gs = 0 v v ds = 400 v, v gs = 0 v, t j = 125 c --50 a - - 250 gate to source forward leakage i gss v gs = 30 v - - 250 na gate to source reverse leakage v gs = - 30 v - - - 250 dynamic characteristics (t j = 25 c unless otherwise noted) parameter symbol test conditio ns min. typ. max. units forward transconductance g fs v ds = 50 v, i d = 28 a 23 - - s total gate charge q g (1) i d = 40 a v ds = 400 v v gs = 10 v; see fig. 6 and 13 - - 270 nc gate to source charge q gs (1) --84 gate to drain (" miller") charge q gd (1) - - 130 turn-on delay time t d(on) (1) v dd = 250 v i d = 40 a r g = 1.0 v gs = 10 v, see fig. 10 -25- ns rise time t r (1) -140- turn-off delay time t d(off) (1) -55- fall time t f (1) -74- input capacitance c iss v gs = 0 v v ds = 25 v f = 1.0 mhz, see fig. 5 - 8310 - pf output capacitance c oss -960- reverse transfer capacitance c rss -120- output capacitance c oss v gs = 0 v, v ds = 1.0 v, f = 1.0 mhz - 10 170 - v gs = 0 v, v ds = 480 v, f = 1.0 mhz - 240 - effective output capacitance c oss eff. (2) v gs = 0 v, v ds = 0 v to 480 v - 440 -
document number: 94542 for technical ques tions within your region, please cont act one of the following: www.vishay.com revision: 12-may-10 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com 3 FC40SA50FKP power mosfet, 40 a vishay semiconductors notes (1) repetitive rating ; pulse width limited by maximum junction temperature (see fig. 11) (2) pulse width 300 s; duty cycle 2 % fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature diode characteristics parameter symbol test conditions min. typ. max. units continuous source current (body diode) i s mosfet symbol showing the in tegral reverse p-n junction diode --40 a pulsed source current (body diode) i sm (1) - - 160 diode forward voltage v sd (2) t j = 25 c, i s = 40 a, v gs = 0 v - - 1 v reverse recovery time t rr (2) t j = 25 c, i f = 47 a; di/dt = 100 a/s - 620 940 ns reverse recovery charge q rr -1421c reverse recovery current i rrm t j = 25 c - 38 - a forward turn-on time t on intrinsic turn-on time is negligible (turn-on is dominated by l s + l d ) s d g 0.01 0.1 1 10 100 1000 0.1 1 10 100 v gs to p 15 10 8.0 7.0 6.0 5.5 bottom 5.0 5 v 20 s pulse width tj=25c i d , drain-to-source current (a ) v ds , drain-to-source voltage (v ) 0.1 1 10 100 1000 0.1 1 10 100 v gs to p 15 10 8.0 7.0 6.0 5.5 5.0 bottom 4.5 4.5 v 2 0 s puls e width t150c i d , drain-to-source current (a) v ds , drain-to-source voltage (v ) 0.1 1 10 100 1000 4 5 6 7 8 9 10 11 12 v gs , gate-to-source voltage (v) i d , drain-to-source current (a) t j =150c t j =25c v ds =20v 20 s pul se width 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 t j , junction temperature (c) r ds(on) , drain-to-source on resistance (normalized) v gs =10v i d =24a
www.vishay.com for technical qu estions within your region, please contact one of the fo llowing: document number: 94542 4 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com revision: 12-may-10 FC40SA50FKP vishay semiconductors power mosfet, 40 a fig. 5 - typical capacitance vs. drain to source voltage fig. 6 - typical gate charge vs. gate to source voltage fig. 7 - typical source drain diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit 1 10 100 1000 v ds , drain-to-source voltage (v) 10 100 1000 10000 100000 ) f p ( e c n a t i c a p a c , c coss crss ciss v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 5 10 15 20 0100200300 q g , total gate charge (nc) v gs , gate-to-source voltage (v) i d =40a 0.1 1 10 100 1000 0.20.71.21.7 v sd , source-to-drain voltage (v) i sd , reverse drain current (a ) v gs =0 t j =150c t j =25c 1 10 100 1000 10 100 1000 v ds , drain-to-source voltage (v) i d , drain current (a) 100us 10ms 1ms opera tion in this area limited by rds(on) t c = 25c t j = 150c single pulse 0 10 20 30 40 25 50 75 100 125 150 tc, case temperature (c) id, drain current (a) pulse width 1 s duty factor 0.1 % d.u.t. 10 v + - v ds r d v dd r g v gs
document number: 94542 for technical ques tions within your region, please cont act one of the following: www.vishay.com revision: 12-may-10 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com 5 FC40SA50FKP power mosfet, 40 a vishay semiconductors fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction to case fig. 12a - maximum avalanche energy vs. drain current fig. 12b - unclamped inductive test circuit 10 % v gs t d(on) t r t d(off) t f v ds 90 % 0.001 0.010 0.100 1.000 0.00001 0.0001 0.001 0.01 0.1 1 t1, rectangular pulse duration (s) thermal response ( zthjc single pulse ( therma l response) 0.01 0.02 0.05 0.10 0.30 d = 0.50 notes : 1. duty f actor d = t1/t2 2. peak tj=pdm x zthjc + tc ri (c/w) i (sec) 0.161 0.000759 0.210 0.017991 0.147 0.06094 ? j ? j ? 1 ? 1 ? 2 ? 2 ? 3 ? 3 r 1 r 1 r 2 r 2 r 3 r 3 ? ? c ci i ri ci= ? i ? ri 0 500 1000 1500 2000 2500 3000 25 50 75 100 125 150 starting tj, junction temperature (c) eas, single pulse avalanche energy (mj) i d ... top 18a 26a bottom 40a 0.01 d.u.t l + - driver a 15 v 20 v r g v ds i as t p v dd
www.vishay.com for technical qu estions within your region, please contact one of the fo llowing: document number: 94542 6 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com revision: 12-may-10 FC40SA50FKP vishay semiconductors power mosfet, 40 a fig. 12c - unclamped indu ctive waveforms fig. 13a - gate charge test circuit fig. 13b - basic gate charge waveform fig. 13c - peak diode recovery dv/dt test circuit v (br)dss i as t p - + d.u.t. v gs 1 ma i d r l v ds v g charge v gs v q g q gd q gs + - + + + - - - ? dv/dt controlled by r g ? driver same type as d.u.t. ? i sd controlled by duty factor "d" ? d.u.t. - device under test d.u.t. circuit layout considerations ? low stray inductance ? ground plane ? low leakage inductance current transformer 1 2 4 3 r g v dd
document number: 94542 for technical ques tions within your region, please cont act one of the following: www.vishay.com revision: 12-may-10 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com 7 FC40SA50FKP power mosfet, 40 a vishay semiconductors fig. 14 - for n-channel power mosfets ordering information table p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-applied voltage reverse recovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period * v gs = 5v for logic level devices * 1 - power mosfet 2 - generation 6.2/6.3 mosfet silicon dbc construction 3 - current rating (40 = 40 a) 4 - single switch (see circuit configuration table) 5 - sot-227 6 - voltage rating (50 = 500 v) 7 - mosfet k speed 8 - none = standard production p = lead (pb)-free device code 5 13 24 678 f c 40 s a 50 fk p
www.vishay.com for technical qu estions within your region, please contact one of the fo llowing: document number: 94542 8 diodesamericas@vishay.com , diodesasia@vishay.com , diodeseurope@vishay.com revision: 12-may-10 FC40SA50FKP vishay semiconductors power mosfet, 40 a circuit configuration circuit circuit configuration code circuit drawing single switch no diode s links to related documents dimensions www.vishay.com/doc?95036 packaging information www.vishay.com/doc?95037 s (1-4) d (3) g (2) lead assignment s d g s 3 2 4 1
document number: 95036 for tec hnical questions, contact: indmodules@vishay.com www.vishay.com revision: 28-aug-07 1 sot-227 outline dimensions vishay semiconductors dimensions in millimeters (inches) notes ? dimensioning and toleranc ing per ansi y14.5m-1982 ? controlling dime nsion: millimeter 38.30 (1.508) 37.80 (1.488) -a- 4 12 3 12.50 (0.492) 7.50 (0.295) ? 4.40 (0.173) ? 4.20 (0.165) 30.20 (1.189) 29.80 (1.173) 15.00 (0.590) 6.25 (0.246) 25.70 (1.012) 25.20 (0.992) -b- r full chamfer 2.00 (0.079) x 45 2.10 (0.082) 1.90 (0.075) 8.10 (0.319) 7.70 (0.303) 4 x 2.10 (0.082) 1.90 (0.075) -c- 0.12 (0.005) 12.30 (0.484) 11.80 (0.464) mmm 0.25 (0.010) ca b 4 x m4 nuts
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