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freescale semiconductor document number: FXOS8700CQ data sheet: advance information rev. 1, 06/2012 ? 2012 freescale semiconductor, inc. all righ ts reserved. this document contains information on a new product. specifications and information herein are subject to c hange without notice. 6-axis xtrinsic sensor with integrated linear accelerometer and magnetometer FXOS8700CQ is a small, low-power 6-axis linear accelerometer and magnetometer combined into a single package. the device features a selectable digital i 2 c or spi serial interface with 14 -bit accelerometer and 16-bit magnetometer resolution along with sm art-embedded functions. FXOS8700CQ has dynamically selectable acceleration full scales of 2g/4g/8g and a fixed magnetic measurement range of 1200 t. output data rates (odr) from 1.563 hz to 800 hz are selectable by the user for each sensor. interleaved magnetic and acceleration data is available at odr rates of up to 400 hz. FXOS8700CQ is available in a plastic qf n package and it is guaranteed to operate over the extended temperature range of -40c to +85c. features ? 1.95v to 3.6v vdd supply volt age, 1.62v to 3.6 vddio voltage ? 2g/4g/8g dynamically selectable acceleration full-scale range ? 1200 t magnetic sensor full-scale range ? output data rates (odr) from 1.563 hz to 800 hz for each sensor, and up to 400 hz when operated in hybrid mode with both sensors active ? low noise: < 150 g/ hz acceleration, < 1 t rms magnetic ? 14-bit resolution for acceleration measurements ? 16-bit resolution for magnetic measurements ? footprint compatible with xtrinsic mma8451, 2, 3 ? embedded programmable acceleration event functions: ? freefall and motion detection ? transient detection ? vector-magnitude change detection ? pulse and tap detection (single and double) ? orientation detection (portrait/landscape) ? embedded programmable magnetic event functions: ? threshold detection ? vector-magnitude change detection ? autonomous magnetic min/max detection ? autonomous hard -iron calibration ? programmable automatic odr change using auto-wake and return to sleep functions to save power. this function works with both magnetic and acceleration event interrupt sources. ? 32-sample fifo for acceleration data only ? integrated accelerometer and magnetometer self-test functions target markets ? smart phones, tablets, personal navigation devices, roboti cs, uavs, and wrist watches with embedded electronic compass (ecompass) function. ? medical applications: patient monitoring, fall detection, and rehabilitation 1 vddio 6 2 3 4 5 13 12 11 10 9 78 16 15 14 byp reserved scl/sclk gnd reserved gnd int1 sa1/cs_b int2 sda/mosi sa0/miso crst rst n/c vdd 16 lead qfn 3 mm by 3 mm by 1.2 mm FXOS8700CQ top view pin connections FXOS8700CQ
sensors 2 freescale semiconductor, inc. applications ? ecompass in mo bile devices ? user interface (menu scrolling by orientation change, tap detection for button replacement) ? orientation detection (portrait/landscape: up/down, left/right, back/fron t position identification) ? augmented reality (ar), gaming, and real-tim e activity analysis (pedometry, freefall and drop detection for hard disk drives and other devices) ? power management for mobile devices us ing inertial and magnetic event detection ? shock and vibration monitoring (mechatronic compensation, shipping and warranty usage logging) related documentation the FXOS8700CQdevice features and operations are described in a variety of reference manuals, user guides, and application notes. to find the most-current versions of these documents: 1. go to the freescale homepage at: http://www.freescale.com/ 2. in the keyword search box at the top of the page, enter the device number FXOS8700CQ. in the refine your result pane on the left, click on the documentation link. ordering information part number temperature range package description shipping FXOS8700CQr1 -40c to +85c qfn tape and reel
sensors freescale semiconductor, inc. 3 contents 1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 zero-g and zero-flux offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 device characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 mechanical characteristics (accelerometer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 magnetic characteristics (magnetometer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 hybrid characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 spi interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 embedded functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 factory calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 8-bit or 14-bit accelerometer data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 accelerometer low-power modes versus high-resolution modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 auto-wake/sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5 hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 accelerometer freefall and motion event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 transient detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.8 pulse detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 orientation detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.10 acceleration vector magnitude detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.11 magnetic vector magnitude detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.12 magnetic threshold detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13 magnetic min/max detection (autonomous calibration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 registers by functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 auto-sleep trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4 accelerometer output data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.5 accelerometer fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6 accelerometer sensor data configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.7 accelerometer high-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.8 portrait/landscape detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.9 freefall and motion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.10 accelerometer vector magnitude function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.11 transient (ac) acceleration detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.12 pulse detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.13 accelerometer offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.14 magnetometer data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.15 magnetometer offset correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.16 magnetometer threshold function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.17 magnetometer control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10 mounting guidelines for the quad flat no lead (qfn) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.1 overview of soldering considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.2 halogen content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.3 pcb mounting recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 11 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
sensors 4 freescale semiconductor, inc. 1 block diagram figure 1. block diagram
sensors freescale semiconductor, inc. 5 2 pin description figure 2. pinout diagram device power is supplied through the vdd pin. power supply decoupling capacitors (100 nf ceramic plus 4.7 f bulk) should be placed as close as possible to pin 14 of the device. the digital interface supply voltage (vddio) should be decoupled with a 100 nf ceramic capacitor placed as close as possible to pin 1 of the device. the digital control signals scl, sda, sa0, sa1, and rst are not tolerant of voltages more th an vddio + 0.3v. if vddio is removed, these pins will clamp any logic signals through their internal esd protection diodes. table 1. pin description pin name function 1 vddio interface power supply 2 byp internal regulator output bypass capacitor connection 3 reserved test reserved, connect to gnd 4scl/sclki 2 c serial clock/spi clock 5 gnd ground 6sda/mosii 2 c serial data/spi master out, slave in 7 sa0/miso i 2 c address selection bit 0 (1) /spi master in, slave out 1. see table 9 for i 2 c address options selectable using the sa0 and sa1 pins. 8 crst magnetic reset cap 9 int2 interrupt 2 10 sa1/cs_b i 2 c address selection bit 1 ( 1 ) /spi chip select (active low) 11 int1 interrupt 1 12 gnd ground 13 reserved test reserved, connect to gnd 14 vdd power supply 15 n/c internally not connected 16 rst reset input, active high. connect to gnd if unused 1 vddio 6 2 3 4 5 13 12 11 10 9 78 16 15 14 byp reserved scl/sclk gnd reserved gnd int1 sa1/cs_b int2 sda/mosi sa0/miso crst rst n/c vdd top view 16 lead qfn-col 3 mm by 3 mm by 1.2 mm FXOS8700CQ
sensors 6 freescale semiconductor, inc. the function and timing of the two interrupt pins (int1 and int2) are user programmable through the i 2 c/spi interface. the sda and scl i 2 c connections are open drain and therefore require a pullup resistor as shown in the application diagram in figure 3 . the int1 and int2 pins may also be configured for open-drain oper ation. if they are configured fo r open drain, external pullup resistors are required. figure 3. electr ical connection 2.1 soldering information the qfn package is compliant with the rohs standards. pleas e refer to freescale application note an4077 for more information. vddio int1 int2 sda/mosi sa0/miso rst vdd 0.1 f 0.1 f 0.1 f 4.7 f scl/sclk sa1/cs_b vddio vddio vddio vddio (connect to gnd if unused) note: pullup resistors on int1 and int2 are not required if these pins are configured for push/pull (default) operation. 0.1 f note: pullup resistors on scl/sclk and sda/mosi are not required if the device is operated in spi interface mode. 1 6 2 3 4 5 13 12 11 10 9 78 16 15 14 byp scl/sclk gnd reserved gnd sda/mosi sa0/miso crst rst n/c vdd reserved vddio int1 int2 FXOS8700CQ
sensors freescale semiconductor, inc. 7 2.2 orientation figure 4. product orientation and axis orientation top view pin 1 side view top bottom +ax, +mx +ay, +my +az, +mz 1 top view xout @ 0g magnetic field earth gravity maximum my minimum mx maximum mx minimum my maximum mz minimum mz yout @ -1g zout @ 0g xout @ 1g yout @ 0g zout @ 0g xout @ -1g yout @ 0g zout @ 0g xout @ 0g yout @ 1g zout @ 0g xout @ 0g yout @ 0g zout @ 1g xout @ 0g yout @ 0g zout @ -1g
sensors 8 freescale semiconductor, inc. 3terminology 3.1 sensitivity sensitivity is represented in mg/lsb for the accelerometer and t/lsb for the magnetometer. the magnetometer sensitivity is fixed at 0.1 t/lsb. the accelerometer sensitivity changes with the full-scale range selected by the user. accelerometer sensitivity is 0.244 mg/lsb in 2g mode, 0.488 mg/lsb in 4g mode, and 0.976 mg/lsb in 8g mode. 3.2 zero-g and zero-flux offset for the accelerometer, zero-g offset (tyoff) describes the deviat ion of the output values from the ideal values when the sensor is stationary. w ith an accelerometer stationary on a level horizontal surf ace, the ideal output is 0g for the x and y axes, and 1g for the z-axis. the deviation of each axes output from the ideal value is called zero-g offset. offset is to some extent a resu lt of stress on the mems sensor and therefore th e offset can slightly change after mounti ng the sensor onto a printed circuit board o r exposing it to extensive mechanical stress. for the magnetometer, zero-flux offset de scribes the deviation of the output signa l from zero when the device is shielded from external magnetic field sources (i.e. inside a zero-gauss chamber). 3.3 self-test self-test can be used to verify the accelerometer and magnetome ter transducer functionality without the need for an external acceleration or magnetic field stimulus. when the accelerometer se lf-test is activated, an elec trostatic actuation force is app lied to the sensor, simulating a small acceleration. in this case t he sensor x, y, z outputs will exhibit a change in dc levels rela ted to the selected full- scale range (sensitivity). w hen self-test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by th e electrostatic self-test force. when self-test is activated for the magnetometer, an internal magnetic field is generated along the x, y and z axes . the sensor response will be the sum of the ambient magnetic field and the self-test induced field.
sensors freescale semiconductor, inc. 9 4 device characteristics 4.1 mechanical characteri stics (accelerometer) table 2. mechanical characteristics @ vdd = 2.5v , vddio = 1.8v t = 25c unless otherwise noted . symbol parameter test conditions min typ max unit fs measurement range (1) 1. dynamic range is limited to 4g when in the low-noise mode. 2g mode 2 g 4g mode 4 8g mode 8 so sensitivity 2g mode 4096 lsb/g 0.244 mg/lsb 4g mode 2048 lsb/g 0.488 mg/lsb 8g mode 1024 lsb/g 0.976 mg/lsb tcso (1) sensitivity change with temperature 2g, 4g, 8g modes 0.008 %/c soa sensitivity accuracy (2) 2. sensitivity remains in spec as stated, but changing the oversamp ling mode to low power causes a 3% sensitivity shift. this be havior is also seen when changing from 800 hz odr to any other odr in the normal, low-noise + low-power, or high-resolution modes. 1 % tyoff zero-g level offset accuracy (3) 3. before board mount. 2g, 4g, 8g modes 20 mg tyoffpbm zero-g level offset accuracy post-board mount (4) 4. post-board mount offset specifications are based on an 8-layer pcb. 2g, 4g, 8g modes 30 mg tcoff zero-g level change versus temperature -40c to 85c (1) 0.15 mg/c nl nonlinearity best-fit straight line over 2g range normal mode over 1g range low-noise mode tbd %fs vst self-test output change (5) x y z 5. self-test is only exer cised along one direction for each sensitive axis. set to 4g mode +181 +255 +1680 lsb odr accuracy, 2 mhz clock 2 % bw output-data bandwidth odr/3 odr/2 hz noise output-noise density odr = 400 hz, normal mode 126 g/ hz noise output-noise density low-noise mode (1) odr = 400 hz, normal mode 99 g/ hz top operating temperature range -40 +85 c
sensors 10 freescale semiconductor, inc. 4.2 magnetic character istics (magnetometer) table 3. magnetic characteristics @ vdd = 2.5v, vddio = 1.8v t = 25c unless otherwise noted. symbol parameter test conditions min typ max unit fs measurement range 1200 t so sensitivity 0.1 t/lsb tc sensitivity change versus temperature 0.1 %/c zero-flux offset accuracy (1) 1. after m-cell has been trimmed . 1 t tco zero-flux offset change with temperature 0.8 (xy) 2.4 (z) t/c hysteresis (2) 2. hysteresis is measured by sweepi ng the applied magnetic field from -1500 t to 1500 t and then back to -1500 t. the difference in the two readings at -1500 t divided by the swept field range is the hysteresis figure, expressed in % of the full-scale range (fs). 1 %fs nl nonlinearity (3) best-fit straight line 3. over a 300 t sliding window within the full-scale range. tbd %fs temperature sensor repeatability (4) 4. verified by characterization. 1c temperature sensor sensitivity 0.96 c/lsb noise magnetometer output noise odr = 800 hz, os = 2 1.7 (xy) 2.5 (z) t/rms odr = 400 hz, os = 4 1.2 (xy) 1.8 (z) odr = 200 hz, os = 8 0.85 (xy) 1.3 (z) odr = 100 hz, os = 16 0.6 (xy) 0.9 (z) odr = 50 hz, os = 32 0.42 (xy) 0.6 (z) odr = 12.5 hz, os = 128 0.3 (xy) 0.44 (z) odr = 6.25 hz, os = 256 0.23 (xy) 0.33 (z) odr = 1.56 hz, os = 1024 0.21 (xy) 0.3 (z) vst self-test output change (1) x-axis 20 -1320 tbd lsb y-axis 20 +1300 tbd lsb z-axis 20 100 tbd lsb bw output data bandwidth odr/3 odr/2 hz top operating temperature range -40 +85 c
sensors freescale semiconductor, inc. 11 4.3 hybrid characteristics 4.4 electrical characteristics table 4. hybrid characteristics @ vdd = 2.5v, vddio = 1.8v t = 25c unless otherwise noted. symbol parameter test conditions min typ max unit maximum output data rate in hybrid mode 400 hz top operating temperature range -40 +85 c table 5. electrical characteristi cs @ vdd = 2.5v, vddio = 1.8v t = 25c unless otherwise noted . symbol parameter test conditions min typ max unit vdd supply voltage 1.95 2.5 3.6 v vddio interface supply voltage 1.62 1.8 3.6 v i dd lp low-power acceleration mode odr = 12.5 hz 8 a odr = 100 hz 35 odr = 400 hz 130 i dd normal acceleration mode odr = 50 hz 35 a odr = 200 hz 130 odr = 800 hz 240 i dd hybrid mode odr = 200 hz g-cell os = 4 m-cell os = 2 440 a odr = 100 hz g-cell os = 4 m-cell os = 2 240 odr = 25 hz g-cell os = 4 m-cell os = 2 80 i dd magnetic mode odr = 400 hz, os = 2 575 a odr = 12.5 hz, os = 2 40 idd boot current during boot sequence, 0.9 ms max duration using recommended regulator bypass capacitor vdd = 2.5v 3 ma cap, cres value of capacitors on byp pin and magnetic reset pins -40c to 85c 75 100 470 nf iddstby standby mode current @ 25c standby mode 2 a iddstby standby mode current over-temperature range standby mode 16 a vih digital high-level input voltage rst pin 1.04 v vil digital low-level input voltage rst pin 0.68 v vih digital high-level input voltage scl, sda, sa0, sa1 0.75*vddio v vil digital low-level input voltage scl, sda, sa0, sa1 0.3*vddio v voh high-level output voltage int1, int2 i o = 500 a 0.9*vddio v vol low-level output voltage int1, int2 i o = 500 a 0.1*vddio v vols low-level output voltage sda i o = 500 a 0.1*vddio v
sensors 12 freescale semiconductor, inc. 4.5 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. scl, sda pin leakage 25c 1.0 na -40c to 85c 4.0 scl, sda pin capacitance 3p f bw 3 db signal bandwidth magnetic or acceleration mode odr/3 hz bw signal bandwidth hybrid mode odr/6 hz power-on ramp time 0.001 1000 msec bt boot time (1) 900 1000 s turn-on time (2) 2/odr + 1 ms turn-on time (3) 2/odr + 2 ms top operating temperature range -40 +85 c 1. time from vddio on and vdd > vdd min until i 2 c ready for operation. 2. time to obtain valid data from standby mode to active mode. 3. time to obtain valid data from power-down condition. table 6. maximum ratings rating symbol value unit maximum acceleration (all axes, 100 s) g max 5,000 g supply voltage, io voltage vdd -0.3 to +3.6 v input voltage on any control pin (sa0/miso, sa1/cs_b, scl/sclk, sda/mosi, rst) vin -0.3 to vddio + 0.3 v drop-test height d drop 1.8 m maximum exposed magnetic field without perming (sensor characteristics may be restored us ing the magnetic reset de-gauss function) 10,000 t maximum exposed field without permanent damage 0.1 t storage temperature range t stg -40 to +125 c table 7. esd and latchup protection characteristics rating symbol value unit human body model hbm 2000 v machine model mm 200 v charge device model cdm 500 v latchup current at t = 85c 100 ma table 5. electrical characteristi cs @ vdd = 2.5v, vddio = 1.8v t = 25c unless otherwise noted . this device is sensitive to esd, improper handling can cause permanent damage to the part.
sensors freescale semiconductor, inc. 13 5 digital interfaces 5.1 i 2 c interface characteristics figure 5. i 2 c slave timing diagram table 8. i 2 c slave timing values (1) 1. all values referred to vih (min) and vil (max) levels. parameter symbol i 2 c fast mode unit min max scl clock frequency f scl 0 400 khz bus free time between stop and start condition t buf 1.3 s (repeated) start hold time t hd;sta 0.6 s (repeated) start setup time t su;sta 0.6 s stop condition setup time t su;sto 0.6 s sda data hold time t hd;dat 0.05 0.9 (2) 2. this device does not stretch the low period (t low ) of the scl signal. s sda valid time (3) 3. t vd;dat = time for data signal from scl low to sda output. t vd;dat 0.9 (2) s sda valid acknowledge time (4) 4. t vd;ack = time for acknowledgement signal from scl low to sd a output (high or low, depending on which one is worse). t vd;ack 0.9 (2) s sda setup time t su;dat 100 ns scl clock low time t low 1.3 s scl clock high time t high 0.6 s sda and scl rise time t r 20 + 0.1 c b (5) 5. c b = total capacitance of one bus line in pf. 300 ns sda and scl fall time t f 20 + 0.1 c b (5) 300 ns pulse width of spikes on sda and scl that must be suppressed by internal input filter t sp 05 0n s handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta
sensors 14 freescale semiconductor, inc. 5.1.1 general i 2 c operation there are two signals associated with the i 2 c bus: the serial clock line (scl) and the seri al data line (sda). the latter is a bidirectional line used for sending and receiving the data to/from the interface. external pullup resistors connected to vddio are required for sda and scl. when the bus is free both the lines are high. the i 2 c interface is compliant with fast mode (400 khz), and normal mode (100 khz) i 2 c standards. operation at frequencies higher th an 400 khz is possible, but depends on several factors including the pullup resistor values, and total bus capacitance (trace + device capacitance). see ta b l e 8 for more information. a transaction on the bus is started through a start condition (s t) signal, which is defined as a high-to-low transition on the data line while the scl line is held high. after the st signal ha s been transmitted by the master, the bus is considered busy. the next byte of data transmitted contains the slave address in the first seven bits, and the eighth bit, the read/write bit, i ndicates whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after the st conditi on with its own address. if they ma tch, the device considers itsel f addressed by the master. the 9th clock puls e, following the slave address byte (and ea ch subsequent byte) is the acknowledge (ack). the transmitter must release the sda line during the ack pe riod. the receiver must then pull the data line low so that i t remains stable low during the high period of the acknowledge clock period. the number of bytes per transfer is unlimited. if a receiver can't receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues wh en the receiver is ready for another byte and releases the data line. this delay action is called clock stretching. not all receiver d evices support clock stretching. not all master devices recognize cl ock stretching. this part does not use clock stretching. a low to high transition on the sda line while the scl line is hi gh is defined as a stop conditi on (sp) signal. a write or burs t write is always terminated by the master issuing the sp signal. a mast er should properly terminate a read by not acknowledging a byte at the appropriate time in the protocol. a master may also issue a repeated start signal (sr) during a transfer the slave addresses that may be assigned to the FXOS8700CQ part are 0x1c, 0x1d, 0x1e, or 0x1f. the selection is made by the logic level of the sa1 and sa0 inputs. consult the factory for alternate address programming options. 5.1.2 i 2 c read/write operations single byte read the master (or mcu) transmits a start condition (st) to the FXOS8700CQ, followed by the slave address, with the r/w bit set to ?0? for a write, and the FXOS8700CQ sends an acknowledgement. then the master (or mcu) transmits the address of the register to read and the FXOS8700CQ sends an acknowledgement. the master (or mcu) transmits a repeated start condition (sr), followed by the slave address with the r/w bit set to ?1? for a read from the previously selected register. the fxos8700c q then acknowledges and transmits the data from the requested re gister. the master does not acknowledge (nak) the transmitted data, but transmits a stop condition to end the data transfer. multiple byte read when performing a multi-byte or ?burst? read, the FXOS8700CQ automatically increments the register address read pointer after a read command is received. therefore, after following the steps of a single byte read, multiple bytes of data can be read from sequential registers after each FXOS8700CQ acknowledgment (ak) is received until a no acknowledge (nak) occurs from the master followed by a stop condition (sp) signaling an end of transmission. single byte write to start a write command, the master transmits a start condition (st) to the FXOS8700CQ, followed by the slave address with the r/w bit set to ?0? for a write, and the FXOS8700CQ sends an acknowledgement. then the master (or mcu) transmits the address of the register to write to, a nd the FXOS8700CQ sends an acknowledgement. th en the master (or mcu) transmits the 8-bit data to write to the designated register and the FXOS8700CQ sends an acknowledgement that it has received the data. since this transmission is complete, the mast er transmits a stop condition (sp) to end the da ta transfer. the data sent to the FXOS8700CQ is now stored in the appropriate register. table 9. i 2 c slave address sa1 sa0 slave address* 0 0 0x1e 010 x 1 d 100 x 1 c 1 1 0x1f * preproduction parts have the i 2 c address of 0x1c, 0x1d, 0x1e and 0x1f respectively.
sensors freescale semiconductor, inc. 15 multiple byte write the FXOS8700CQ automatically in crements the register address write pointer af ter a write command is received. therefore, after following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each FXOS8700CQ acknowledgment (ack) is received. figure 6. i 2 c timing diagram < single byte read > master st device address[6:0] w register address[7:0] sr device address[6:0] r nak sp slave ak ak ak data[7:0] < multiple byte read > master st device address[6:0] w register address[7:0] sr device address[6:0] r ak slave ak ak ak data[7:0] master ak ak nak sp slave data[7:0] data[7:0] data[7:0] < multiple byte write > master st device address[6:0] w register address[7:0] data[7:0] data[7:0] sp slave ak ak ak ak < single byte write > master st device address[6:0] w register address[7:0] data[7:0] sp slave ak ak ak legend st: start condition sp: stop condition nak: no acknowledge w: write = 0 sr: repeated start condition ak: acknowledge r: read = 1
sensors 16 freescale semiconductor, inc. 5.2 spi interface characteristics spi interface is a classical master/slave serial port. the FXOS8700CQ is always considered as the slave and thus is never initiating the communication. table 10 and figure 7 describe the timing requir ements for the spi system. figure 7. spi timing diagram 5.2.1 general spi operation the cs_b pin is driven low at the start of a spi transaction, held low for the durati on of the transaction, and driven high aft er the transaction is complete. during a transaction the master togg les the spi clock (sclk) and transmits data on the mosi pin. a write operation is initiated by transmitting a 1 for the r/w bi t. then the 8-bit register addre ss, addr[7:0] is encoded in th e first and second serialized bytes. data to be written starts in the third serialized byte. the order of the bits is as follows: r/w,addr[6],addr[5],addr[4],a ddr[3],addr[2],addr[1],addr[0], addr[7],x,x,x,x,x,x,x, data[7],data[6],data[5],data[4],data[3],data[2],data[1],data[0]. multiple bytes of data may be transmitted. the x indicates a bit that is ignored by the part. the register address is auto- incremented so that the next clock edges will latch the data for the next register. when desired, the rising edge on cs_b stops the spi communication. the FXOS8700CQ spi configuration is as follows: ? polarity: rising/falling ? phase: sample/setup ? order: msb first table 10. spi timing function symbol min max unit operating frequency o f ? 1 mhz sclk period tsclk 1000 ? ns sclk high time tclkh 500 ? ns sclk low time tclkl 500 ? ns cs_b lead time tscs 65 ? ns cs_b lag time thcs 65 ? ns mosi data setup time tset 25 ? ns mosi data hold time thold 75 ? ns miso data valid (after sclk low edge) tddly ? 500 ns width cs high twcs tbd ? ns cs_b sclk mosi miso
sensors freescale semiconductor, inc. 17 5.2.2 spi read/write operations a read operation is initiated by transmitti ng a 0 for the r/w bit. then the 8-bit regist er address, addr[7:0] is encoded in the first and second serialized bytes. subsequent bits are ignored by the part. the read data is deserialized from the miso pin. similarly a write operation is initiated by transmitting a 1 fo r the r/w bit. after the first and second serialized bytes multi ple data bytes can be transmitted into consecutive registers, star ting from the indicated regi ster address in addr[7:0]. an spi transaction is started by asserting the cs_b pin (high- to-low transition), and ended by deasserting the cs_b pin (low-to - high transition). * data bytes must be transmitted to the slav e (FXOS8700CQ) via mosi pin by the master when r/w = 1. data bytes will be transmit ted by the slave (FXOS8700CQ) to the master via miso pin when r/w = 0. the first 2 bytes are always transmitt ed by the master via mosi pin . i.e. a transaction is always initiated by master. figure 8. spi single-burst read/write transaction diagram the registers embedded inside the FXOS8700CQ are accessed through either an i 2 c, or a spi serial interface. to enable either interface the vddio line must be connect ed to the interface supply voltage. if vdd is not present and vddio is present FXOS8700CQ is in shutdown mode and communications on the in terface are ignored. if vddio is held high, vdd can be powered off and the communications pins will be in a high impedance state. this will allow communications to continue on the bus with other devices. 5.2.3 i 2 c/spi auto detection it is possible to factory-trim parts su ch that the part always uses either i 2 c or spi communication protocol. when this trim is not in place the device will operate in either i 2 c or spi interface mode based on the state of the sa0 pin during power up or when exiting reset. once set for i 2 c or spi operation the device will remain in i 2 c or spi mode until the device is reset. 5.2.4 power supply sequencing and i 2 c/spi mode auto detection this component does not have any specific power supply s equencing requirements between vdd and vddio voltage supplies to ensure normal operation. to ensure correct operation of the i 2 c/spi auto-detection function, v ddio should be applied before or at the same time as vdd. if this or der cannot be maintained, the user should either toggle the rst line or power cycle the vdd rail in order to force the auto-detect function to restart and correctly identify the desired interface. please consult the factory for further options if necessary. r/w bit followed by addr [6:0] addr[7] followed by 7 ?don?t care? bits data0* data1 ? datan table 11. serial interface pin descriptions pin name pin description vddio digital interface power sa1/cs_b i 2 c second least significant bit of device address/spi chip select scl/sclk i 2 c/spi serial clock sda/mosi i 2 c serial data/spi master serial data out slave serial data in sa0/miso i 2 c least significant bit of the device addre ss/spi master serial data in slave out table 12. i 2 c/spi auto detection sa0 slave address gnd i 2 c vddio i 2 c floating spi
sensors 18 freescale semiconductor, inc. 6 modes of operation figure 9. FXOS8700CQ power mode transition diagram all register contents are preserved when transitioning from acti ve to standby mode. some registers are reset when transitioning from standby to active. these are all noted in the device memo ry map register table. the sleep and wake modes are active modes. for more information on how to use the sleep and wake modes and configuring the device to transition between them, please refer to section 7, ?embedded functionality? or freescale application note an4074. table 13. mode of operation description mode i 2 c/spi bus state vdd vddio function description off powered down <1.8 v vddio can be > vdd the device is powered off. all analog and digital blocks are shutdown. i 2 c bus inhibited. standby i 2 c/spi communication with FXOS8700CQ is possible on vddio = high vdd = high active bit is cleared only digital blocks are enabled. analog subsystem is disabled. internal clocks disabled. active (wake/sleep) i 2 c/spi communication with FXOS8700CQ is possible on vddio = high vdd = high active bit is set all blocks are enabled (digital and analog). sleep wake standby off active
sensors freescale semiconductor, inc. 19 7 embedded functionality FXOS8700CQ is a low-power, digital output 6-axis sensor with both i 2 c and spi interfaces. extensive embedded functionality is provided to detect inertial and magnetic events at low-power, wit h the ability to notify the host processor of an event via eit her of the two programmable interrupt pins. the embedded functionality includes: ? 8-bit or 14-bit accelerometer data which includes high-pa ss filtered data, and 8 or 16-bit magnetometer data ? four different oversampling options for the accelerometer ou tput data, and eight for the magnetometer. the oversampling settings allow the end user to optimize the resolution versus power trade-off in a given application. ? a low-noise accelerometer mode that functions independent ly of the oversampling modes for even higher resolution ? low-power auto-wake/sleep function for conser ving power in portable battery powered applications ? accelerometer pulse detection circuit which can be used to detect directional single and double taps ? accelerometer directional motion and freefall event detection with programmable threshold and debounce time ? acceleration transient detection with programmable threshold and debounce time. transient detection can employ either a high-pass filter or use the difference between reference and current sample values. ? orientation detection with programmable hysteresis for smooth transitions between portrait/landscape orientations ? accelerometer vector magnitude change event detection with programmable refe rence, threshold, and debounce time values ? magnetic threshold event detection with progra mmable reference, threshold, and debounce time ? magnetometer vector magnitude change ev ent detection with programmable refe rence, threshold and debounce time values ? magnetic min/max detection circuit which can also be used for autonomous calibration of magnetic hard-iron offset many different configurations of the above functions are possible to suit the needs of the end application. separate applicatio n notes are available to further ex plain the different configuratio n settings and potential use cases. 7.1 factory calibration FXOS8700CQ's integrated accelerometer and magnetometer sensor s are factory calibrated for s ensitivity and offset on each axis. the trim values are stored in non-volatile memory (nvm ). on power-up, the trim parameters are read from nvm and applied to the internal compensation circuitry. after mountin g the device to the pcb, the user may further adjust the accelerometer and magnetometer offsets through the off_x/ y/z and m_off_x/y/z registers, respectively. for more information on device calibration, refer to freescale application note, an4069. 7.2 8-bit or 14-bit accelerometer data the measured acceleration data is stored in the out_x_ msb, out_x_lsb, out_y_msb, out_y_lsb, out_z_msb, and out_z_lsb registers as 2?s complement 14-bit numbers. the most significant 8-bits of each axis are stored in the out_x, y , z_msb registers, so applications needing only 8-bit resu lts simply read these three registers and ignore the out_x,y , z_lsb registers. to do this, the f_read mode bit in ctrl_reg1 must be set. when the full-scale range is set to 2g, the measurement range is -2g to +1.999g, and each count corresponds to 0.244 mg at 14-bits resolution. when the full-scale is set to 8g, the meas urement range is -8g to +7.996g, and each count corresponds to 0.976 mg. the resolution is reduced by a factor of 64 if only the 8-bit results are used ([ f_read ] = 1). for further information on the different data formats and modes, please refer to freescale ap plication note an4076. 7.3 accelerometer low-power mod es versus high-resolution modes FXOS8700CQ can be optimized for lower power or for higher reso lution of the accelerometer output data. high resolution is achieved by setting the lnoise bit in register 0x2a. this impr oves the resolution (by lowering the noise), but be aware that th e dynamic range becomes limited to 4g when this bit is set. th is will affect all internal embedded functions (scaling of thresho lds, etc.) and reduce noise. another method for improving the resoluti on of the data is through oversampling. one of the oversamplin g schemes of the output data c an activated when ctrl_reg2[ mods ] = 0b10 which will improve the resolution of the output data without affecting other internal embedded functions or limiting the dynamic range. there is a trade-off between low power and high resolution. low power can be achieved when the ov ersampling rate is reduced. when ctrl_reg2[ mods ] = 0b10, the lowest power is achieved, at the ex pense of higher noise. in general, the lower the selected odr and osr, the lower the power consumption. for more information on how to configure the device in low-power or high-resolution modes and understand the benefits and trade-offs , please refer to freescale application note an4075.
sensors 20 freescale semiconductor, inc. 7.4 auto-wake/sleep mode FXOS8700CQ can be configured to transition between sample rate s (with their respective curren t consumptions) based on the status of the embedded interrupt event generators in the device. the advantage of using the auto-w ake/sleep is t hat the system can automatically transition to a higher sample rate (higher cu rrent consumption) when needed but spends the majority of the time in the sleep mode (lower current) when the device does not require higher sampling rates. auto-wake refers to the device being triggered by one of the interrupt event functions to transition to a higher sample rate. this may also interrupt the proc essor to transition from a sleep mode to a higher power mode. sleep mode occurs when none of the enabled interrupt event functions has detected an interrupt within the user defined time- out period. the device will then transition to the specified lower sample rate. it may also alert the processor to go into a lo wer power mode to save power during this period of inactivity. please refer to an4074 for more detailed info rmation on configuring the au to- wake/sleep function. 7.5 hybrid mode FXOS8700CQ uses a single common analog-to-digital converte r (adc) for both the accelerometer and magnetometer. when operating in hybrid mode (m_ctrl_reg1[m_hm s] = 2?b11), both the accelerometer and magnetometer sensors are actively measured by the adc at an odr equal to o ne half of the setting made in ctrl_reg1[ dr] when operating in accelerometer-only mode (m_ctrl_reg1[m_hms] = 2? b00 (default)) or magnetometer-only mode (m_ctrl_reg1[m_hms] = 2?b01). while the odr is common to both sensors when operating in hybrid mode, the osr settings for each sensor are independent and may be set via ctrl_reg2[mods] for the acce lerometer and m_ctrl_reg1[m_os] for the magnetometer, respectively. 7.6 accelerometer freefall a nd motion event detection FXOS8700CQ integrates a programmable threshold based accelera tion detection function capable of detecting either motion or freefall events depending upon the configuration. for further de tails and examples on using the embedded freefall and motion detection functions, please refer to freescale application note an4070. 7.6.1 freefall detection the detection of ?freefall? invo lves the monitoring of the x, y , and z axes for the condition where the acceleration magnitude is below a user specified threshold for a user definable amount of time. typically, the usable threshold ranges are between 100 mg and 500 mg. 7.6.2 motion detection motion detection is often used to alert the main processor that the device is currently in use. when the acceleration exceeds a set threshold for a set amount of time, the motion interrupt is asserted. a motion can be a fast moving shake or a slow moving tilt. this will depend on the threshold and timing values configured for the event. the motion detection function can analyze s tatic acceleration changes or faster jolts. the timing value is set by a configurable debounce counter. the debounce counter acts lik e a filter to indicate whether the condition exists for longer than a set amount of time (i.e., 100 ms or longer). there is also directional data available in the source register to de tect the direction of the motion that gener ated the interrupt. this is useful for ap plications such as directional shake or flick detection, and can also a ssist gesture detection algorithms by indicating that a motion gest ure has started. 7.7 transient detection FXOS8700CQ integrates an acceleration transient detection functi on that incorporates a high-pass filter. acceleration data goes through the high-pass filter, eliminating the dc tilt offset and low frequency acceleration changes. the high-pass filter cutof f can be set by the user to four different frequencies which are de pendent on the selected output da ta rate (odr). a higher cutoff frequency ensures that dc and slowly changing acceleration data will be filtered out, allowing only the higher frequencies to p ass. the transient detection feature can be used in the same manner as the motion detection by bypassing the high-pass filter. there is an option in the configuration register to do this. this adds more flexibility to cover the various customer use cases. many applications use the accelerometer?s static acceleration readings (i.e., tilt) which measure the change in acceleration du e to gravity only. these function s benefit from acceleration data being filtered with a low-pass filter where high-frequency data is considered noise. however, there are many functions where t he accelerometer must analyze dynamic acceleration. functions such as tap, flick, shake and step counting are based on the anal ysis of the change in the dyna mic acceleration. the transient detection function can be routed to either interrupt pin through bi t 5 in ctrl_reg5 register (0x2e). registers 0x1d ? 0x20 and 0x79 ? 0x7c are the dedicated transient det ection configuration registers. the source register contains directional data to determine the direction of the transient acceleration, either positive or negative. for further information of the embedded tra nsient detection function along with spec ific application examples and recommended conf iguration settings, please refer to freescale application note an4071.
sensors freescale semiconductor, inc. 21 7.8 pulse detection FXOS8700CQ has embedded single/double and directional pulse detection. this function employs several timers for programming the pulse width time and the latency between puls es. the detection thresholds are independently programmable for each axis. the acceleration data input to the pulse detection circuit can be put through both high and low-pass filters, al lowing for greater flexibility in discriminating between pulse and tap events. the pulse_src register provides information on the axis , direction (polarity), and single/double even t status for the detected pulse or tap. fo r more information on how to configure th e device for pulse detection, please refer to freescale application note an4072. 7.9 orientation detection FXOS8700CQ has an embedded orientation detection algorithm with t he ability to detect all six orientations. the transition angl es and hysteresis are programmable, allowing for a smooth transition between portrait and landscape orientations. the angle at which the device no longer detects the orientation change is referred to as the ?z-lockout angle?. the device oper ates down to 29 from the flat position. all angles are accurate to 2. for further information on the orientation detection f unction refer to freescale application note, an4068. 7.10 acceleration vector magnitude detection FXOS8700CQ incorporates an acceleration vector magnitude c hange detection block that can be configured to generate an interrupt when the acceleration magnitude exceeds a pre-set threshold for a programmed debounce time. the function can be configured to operate in absolute or relative modes, and can also act as a wake to sleep/sleep to wake source. this function is useful for detecting acceleration transients when operated in abs olute mode, or for detecting changes in orientation when operated in relative mode. 7.11 magnetic vector magnitude detection FXOS8700CQ incorporates a magnetic vector magnitude change det ection block that can be configured to generate an interrupt when the magnetic field magnitude exceeds a pre-set thre shold for a programmed debounce time. the function can be configured to operate in absolute or relative modes, and can also act as a wake to sleep/sleep to wake source. 7.12 magnetic threshold detection FXOS8700CQ incorporates a magnetic threshold event detection bl ock that can be configured to g enerate an interrupt when the magnetic field on the enabled axes is above or below a programmed threshold. two logic combinations are possible for the detection: all of th e enabled axes below their respective thresholds (and condition ), or any of the enabled axes above their respective thresholds (or condition). even detection may be filtered using a dedicated debounce counter to avoid spurious event detection. the threshol ds for each axis are individually programmable and the function can also act as a wake to sleep/sleep to wake source. 7.13 magnetic min/max detection (autonomous calibration) FXOS8700CQ incorporates a magnetic min/max detection circui t that can be used to automatically track the minimum and maximum field values measured on each of the x, y, and z axes. the stored minimum and maximum values may optionally be used to determine the magnetic hard-iron compensation and load the offset registers with the appropriate correction values.
sensors 22 freescale semiconductor, inc. 8 register map table 14. register address map name type register address auto-increment address default hex value comment status[ f_mode ] = 00, ctrl_reg1[ f_read ] = 0 status[ f_mode ] > 00, ctrl_reg1[ f_read ] = 0 status[ f_mode ] = 00, ctrl_reg1[ f_read ] = 1 status[ f_mode ] > 00, ctrl_reg1[ f_read ] = 1 status (1)(2) r 0x00 0x01 0x00 real-time data-ready status or fifo status (dr_status or f_status) out_x_msb (1)(2) r 0x01 0x02 0x01 0x03 0x01 data [7:0] are 8 msbs of 14-bit sample. root pointer to xyz fifo data. out_x_lsb (1)(2) r 0x02 0x03 0x00 data [7:2] are 6 lsbs of 14-bit real-time sample out_y_msb (1)(2) r 0x03 0x04 0x05 0x00 data [7:0] are 8 msbs of 14-bit real-time sample out_y_lsb (1)(2) r 0x04 0x05 0x00 data [7:2] are 6 lsbs of 14-bit real-time sample out_z_msb (1)(2) r 0x05 0x06 m_ctrl_reg2[ hyb_autoinc_mode ] = 0 0x00, m_ctrl_reg2[ hyb_autoinc_mode ] = 1 0x33 data [7:0] are 8 msbs of 14-bit real-time sample out_z_lsb (1)(2) r 0x06 m_ctrl_reg2[ hyb_autoinc_mode ] = 0 0x00, m_ctrl_reg2[ hyb_autoinc_mode ] = 1 0x33 data [7:2] are 6 lsbs of 14-bit real-time sample reserved r 0x07 - 0x08 0x00 0x00 reserved, reads return 0x00 f_setup (1)(3) r/w 0x09 0x0a 0x00 fifo setup trig_cfg r/w 0x0a 0x0b 0x00 fifo event trigger configuration register sysmod (1)(2) r 0x0b 0x0c output current system mode int_source (1)(2) r 0x0c 0x0d output interrupt status who_am_i (1) r 0x0d 0x0e 0xc7 device id xyz_data_cfg (1)(4) r/w 0x0e 0x0f 0x00 acceleration dynamic range and filter enable settings hp_filter_cutoff (1)(4) r/w 0x0f 0x10 0x00 pulse detection high- pass and low-pass filter enable bits. high-pass filter cutoff frequency selection pl_status (1)(2) r 0x10 0x11 0x00 landscape/portrait orientation status pl_cfg (1)(4) r/w 0x11 0x12 0x83 landscape/portrait configuration pl_count (1)(3) r/w 0x12 0x13 0x00 landscape/portrait debounce counter pl_bf_zcomp (1)(4) r/w 0x13 0x14 0x00 back/front trip angle threshold pl_ths_reg (1)(4) r/w 0x14 0x15 0x1a portrait to landscape trip threshold angle and hysteresis settings a_ffmt_cfg (1)(4) r/w 0x15 0x16 0x00 freefall/motion function configuration a_ffmt_src (1)(2) r 0x16 0x17 0x00 freefall/motion event source register a_ffmt_ths (1)(3) r/w 0x17 0x18 0x00 freefall/motion threshold register a_ffmt_count (1)(3) r/w 0x18 0x19 0x00 freefall/motion debounce counter
sensors freescale semiconductor, inc. 23 reserved r/w 0x19- 0x1c ? reserved, reads return 0x00 transient_cfg (1)(4) r/w 0x1d 0x1a 0x00 transient function configuration transient_src (1)(2) r 0x1e 0x1b 0x00 transient event status register transient_ths (1)(3) r/w 0x1f 0x1c 0x00 transient event threshold transient_count (1)(3) r/w 0x20 0x1d 0x00 transient debounce counter pulse_cfg (1)(4) r/w 0x21 0x22 0x00 pulse function configuration pulse_src (1)(2) r 0x22 0x23 0x00 pulse function source register pulse_thsx (1)(3) r/w 0x23 0x24 0x00 x-axis pulse threshold pulse_thsy (1)(3) r/w 0x24 0x25 0x00 y-axis pulse threshold pulse_thsz (1)(3) r/w 0x25 0x26 0x00 z-axis pulse threshold pulse_tmlt (1)(4) r/w 0x26 0x27 0x00 time limit for pulse detection pulse_ltcy (1)(4) r/w 0x27 0x28 0x00 latency time for second pulse detection pulse_wind (1)(4) r/w 0x28 0x29 0x00 window time for second pulse detection aslp_count (1)(4) r/w 0x29 0x2a 0x00 in activity counter setting for auto-sleep ctrl_reg1 (1)(4) r/w 0x2a 0x2b 0x00 system odr, accelerometer osr, operating mode ctrl_reg2 (1)(4) r/w 0x2b 0x2c 0x00 self-test, reset, accelerometer osr and sleep mode settings ctrl_reg3 (1)(4) r/w 0x2c 0x2d 0x00 sleep mode interrupt wake enable, interrupt polarity, push-pull/open- drain configuration ctrl_reg4 (1)(4) r/w 0x2d 0x2e 0x00 interrupt enable register ctrl_reg5 (1)(4) r/w 0x2e 0x2f 0x00 interrupt pin (int1/int2) map off_x (1)(4) r/w 0x2f 0x30 0x00 x-axis accelerometer offset adjust off_y (1)(4) r/w 0x30 0x31 0x00 y-axis accelerometer offset adjust off_z (1)(4) r/w 0x31 0x0d 0x00 z-axis accelerometer offset adjust m_dr_status r 0x32 0x00 magnetic data ready m_out_x_msb (1)(5) r 0x33 data msb of 16-bit magnetic data for x-axis m_out_x_lsb (1)(5) r 0x34 data lsb of 16-bit magnetic data for x-axis m_out_y_msb (1)(5) r 0x35 data msb of 16-bit magnetic data for y-axis m_out_y_lsb (1)(5) r 0x36 data lsb of 16-bit magnetic data for y-axis m_out_z_msb (1)(5) r 0x37 data msb of 16-bit magnetic data for z-axis m_out_z_lsb (1)(5) r 0x38 data lsb of 16-bit magnetic data for z-axis table 14. register address map
sensors 24 freescale semiconductor, inc. cmp_x_msb (1)(5) r 0x39 data bits [13:8] of integrated x-axis accerleration data cmp_x_lsb (1)(5) r 0x3a data bits [7:0] of integrated x- axis accerleration data cmp_y_msb (1)(5) r 0x3b data bits [13:8] of integrated y-axis accerleration data cmp_y_lsb (1)(5) r 0x3c data bits [7:0] of integrated y- axis accerleration data cmp_z_msb (1)(5) r 0x3d data bits [13:8] of integrated z-axis accerleration data cmp_z_lsb (1)(5) r 0x3e data bits [7:0] of integrated z- axis accerleration data m_off_x_msb (6) r/w 0x3f 0x00 msb of magnetometer of x-axis offset m_off_x_lsb (6) r/w 0x40 0x00 lsb of magnetometer of x-axis offset m_off_y_msb (6) r/w 0x41 0x00 msb of magnetometer of y-axis offset m_off_y_lsb (6) r/w 0x42 0x00 lsb of magnetometer of y-axis offset m_off_z_msb (6) r/w 0x43 0x00 msb of magnetometer of z-axis offset m_off_z_lsb (6) r/w 0x44 0x00 lsb of magnetometer of z-axis offset max_x_msb (1)(6) r 0x45 data magnetometer x-axis maximum value msb max_x_lsb (1)(6) r 0x46 data magnetometer x-axis maximum value lsb max_y_msb (1)(6) r 0x47 data magnetometer y-axis maximum value msb max_y_lsb (1)(6) r 0x48 data magnetometer y-axis maximum value lsb max_z_msb (1)(6) r 0x49 data magnetometer z-axis maximum value msb max_z_lsb (1)(6) r 0x4a data magnetometer z-axis maximum value lsb min_x_msb (1)(6) r 0x4b data magnetometer x-axis minimum value msb min_x_lsb (1)(6) r 0x4c data magnetometer x-axis minimum value lsb min_y_msb (1)(6) r 0x4d data magnetometer y-axis minimum value msb min_y_lsb (1)(6) r 0x4e data magnetometer y-axis minimum value lsb min_z_msb (1)(6) r 0x4f data magnetometer z-axis minimum value msb min_z_lsb (1)(6) r 0x50 data magnetometer z-axis minimum value lsb temp (1) r 0x51 data device temperature, valid range of -128 to 127 c m_ths_cfg (1)(4) r/w 0x52 0x00 magnetic threshold detection function configuration m_ths_src (1)(2) r 0x53 data magnetic threshold event source register table 14. register address map
sensors freescale semiconductor, inc. 25 m_ths_x_msb (1) r/w 0x54 0x00 x-axis magnetic threshold msb m_ths_x_lsb (1) r/w 0x55 0x00 x-axis magnetic threshold lsb m_ths_y_msb (1) r/w 0x56 0x00 y-axis magnetic threshold msb m_ths_y_lsb (1) r/w 0x57 0x00 y-axis magnetic threshold lsb m_ths_z_msb (1) r/w 0x58 0x00 z-axis magnetic threshold msb m_ths_z_lsb (1) r/w 0x59 0x00 z-axis magnetic threshold lsb m_ths_count (1)(3) r/w 0x5a 0x00 magnetic threshold debounce counter m_ctrl_reg1 r/w 0x5b 0x00 control for magnetic sensor functions m_ctrl_reg2 r/w 0x5c 0x00 control for magnetic sensor functions m_ctrl_reg3 r/w 0x5d 0x00 control for magnetic sensor functions m_int_src r 0x5e 0x00 magnetic interrupt source a_vecm_cfg r/w 0x5f 0x00 acceleration vector magnitude configuration register a_vecm_ths_msb r/w 0x60 0x00 acceleration vector magnitude threshold msb a_vecm_ths_lsb r/w 0x61 0x00 acceleration vector magnitude threshold lsb a_vecm_cnt r/w 0x62 0x00 acceleration vector magnitude debounce count a_vecm_initx_msb r/w 0x63 0x00 acceleration vector magnitude x-axis reference value msb a_vecm_initx_lsb r/w 0x64 0x00 acceleration vector magnitude x-axis reference value lsb a_vecm_inity_msb r/w 0x65 0x00 acceleration vector magnitude y-axis reference value msb a_vecm_inity_lsb r/w 0x66 0x00 acceleration vector magnitude y-axis reference value lsb a_vecm_initz_msb r/w 0x67 0x00 acceleration vector magnitude z-axis reference value msb a_vecm_initz_lsb r/w 0x68 0x00 acceleration vector magnitude z-axis reference value lsb m_vecm_cfg r/w 0x69 0x00 magnetic vector magnitude configuration register m_vecm_ths_msb r/w 0x6a 0x00 magnetic vector magnitude threshold msb m_vecm_ths_lsb r/w 0x6b 0x00 magnetic vector magnitude threshold lsb table 14. register address map
sensors 26 freescale semiconductor, inc. note auto-increment addresses which are not a simple increment ar e highlighted in bold. the auto-i ncrement addressing is only enable d when registers are read using burst read mode when configured for i 2 c or spi. the auto-increment address is cleared in i 2 c mode when a stop condition is detected. in spi mode there is no stop condition and the address is not cleared. m_vecm_cnt r/w 0x6c 0x00 magnetic vector magnitude debounce count m_vecm_initx_msb r/w 0x6d 0x00 magnetic vector magnitude reference value x-axis msb m_vecm_initx_lsb r/w 0x6e 0x00 magnetic vector magnitude reference value x-axis lsb m_vecm_inity_msb r/w 0x6f 0x00 magnetic vector magnitude reference value y-axis msb m_vecm_inity_lsb r/w 0x70 0x00 magnetic vector magnitude reference value y-axis lsb m_vecm_initz_msb r/w 0x71 0x00 magnetic vector magnitude reference value z-axis msb m_vecm_initz_lsb r/w 0x72 0x00 magnetic vector magnitude reference value z-axis lsb a_ffmt_ths_x_msb r/w 0x73 0x00 x-axis fmt threshold msb a_ffmt_ths_x_lsb r/w 0x74 0x00 x-axis ffmt threshold lsb a_ffmt_ths_y_msb r/w 0x75 0x00 y-axis ffmt threshold msb a_ffmt_ths_y_lsb r/w 0x76 0x00 y-axis ffmt threshold lsb a_ffmt_ths_z_msb r/w 0x77 0x00 z-axis ffmt threshold msb a_ffmt_ths_z_lsb r/w 0x78 0x00 z-axis ffmt threshold lsb reserved (do not modify) 0x7d ? reserved. reads return 0x00. 1. register contents are preserved when transitioning from active to standby mode. 2. register contents are reset when trans itioning from standby to active mode. 3. register contents can be modified anytime in standby or active mode. a write to this register will cause a reset of the corre sponding internal system debounce counter. 4. modification of this register?s contents can only occur when device is in standby m ode, except the fs[1:0] bit fields in ctrl _reg1 register . hybrid auto-increment mode may be used to read out acceleration and magnetic data from registers x1-x6 using a burst read transaction. when m_ctrl_reg2[ hyb_autoinc_mode ] = 1, the user may do a burst read of 12 bytes starting from out_x_msb (address 0x1) to read out both the current accelerometer and magnetometer data in one contiguous operation. 5. to ensure that valid data is read from these registers, the us er must first read the m_out_x_msb register in either burst or single-read mode. reading of the m_out_x_msb register triggers the update of the m_ out_x/y/z registers with the current time-aligned output data. 6. to ensure that valid data is read from these registers, the us er must first read the msb regist er of each register pair in ei ther burst or single-read mode. reading of the lsb register without first r eading the msb register will result in invalid data. table 14. register address map
sensors freescale semiconductor, inc. 27 9 registers by functional blocks 9.1 device configuration 9.1.1 status (0x00) register the status register aliases allow for the contiguous burst read of both status and current acceleration sample/fifo data using the auto incrementing mechanism in both 8 and 14-bit modes. 9.1.2 dr_status (0x00) register data-ready status when status = 0x00 this status register provides the acquisition status information on a per-sample basis, and reflects real-time updates to the outx, outy, and outz registers. when the fifo subsystem da ta output register driver is disabled (f_setup[ f_mode ] = 0b00), this register indicates the real- time status information of the x, y, and z sample data. dr_status or f_status 00000000 figure 10. status register table 15. status description field description f_setup[ f_mode ] = 0b00 register 0x00 dr_status f_setup[ f_mode ] > 0b00 register 0x00 f_status zyxow zow yor xor zyxdr zdr ydr xdr 00000000 figure 11. dr_status register table 16. dr_status description field description zyxow zyxow is set to 1 whenever new data is acquired before completing the retrieval of the previous set. this event occurs when the content of at least one acceleration data register (i.e. outx, outy, and outz) has been overwritten. zyxow is cleared when the high-bytes of the acceleration data (outx_msb, outy_msb, and outz_msb) are read. x, y, z-axis data overwrite. 0: no data overwrite has occurred 1: previous x, y, z data was overwritten by new x, y, z data before it was completely read zow zow is set to 1 whenever a new z-axis acquis ition is completed before the retrieval of the previous data. when this occurs the previous data is overwritten. zow is cleared anytime outz_msb register is read. z-axis data overwrite. 0: no data overwrite has occurred 1: previous z-axis data was overwritten by new z-axis data before it was read yow yow is set to 1 whenever a new y-axis acquisition is completed be fore the retrieval of the previous data. when this occurs the previous data is overwritten. yow is cleared anytime outy_msb register is read. y-axis data overwrite. 0: no data overwrite has occurred 1: previous y-axis data was overwritte n by new y-axis data before it was read
sensors 28 freescale semiconductor, inc. 9.1.3 f_status (0x00) register fifo status when status > 0x00. if the fifo subsystem data output register driver is enabled, the status register indicates the current st atus information of t he fifo subsystem. the f_ovf and f_wmrk_flag flags remain asserted while the event source is still active, but the user can clear the fifo interrupt bit flag in the interrupt source register (int_source) by reading the f_status register. in this case, the int_source[ src_fifo ] bit will be set again when the next data sample enters the fifo. therefore the f_ovf bit flag will remain asserted while the fifo has overflowed and the f_wmrk_flag bit flag will remain asserted while the f_cnt value is equal to or greater than then f_wmrk value. xow xow is set to 1 whenever a new x-axis acquisi tion is completed before the retrieval of the previous data. when this occurs the previous data is overwritten. xow is cleared anytime outx_msb register is read. x-axis data overwrite. 0: no data overwrite has occurred 1: previous x-axis data was overwritten by new x-axis data before it was read zyxdr zyxdr signals that a new acquisition for any of the enabled chan nels is available. zyxdr is cleared when the high-bytes of the acceleration data (outx_msb, outy_msb, outz_msb) are read. x, y, z-axis new data ready. 0: no new set of data ready 1: new set of data is ready zdr zdr is set to 1 whenever a new z-axis data acquisition is completed. zdr is cleared anytime the outz_msb register is read. z-axis new data available. 0: no new z-axis data is ready 1: new z-axis data is ready ydr ydr is set to 1 whenever a new y-ax is data acquisition is completed. ydr is cleared anytime the outy_msb register is read. y-axis new data available. default value: 0 0: no new y-axis data ready 1: new y-axis data is ready xdr xdr is set to 1 whenever a new x-ax is data acquisition is completed. xdr is cleared anytime the outx_msb register is read. x-axis new data available. default value: 0 0: no new x-axis data ready 1: new x-axis data is ready f_ovf f_wmrk_flag f_cnt[5:0] 00 0 figure 12. f_status register table 17. fifo flag event descriptions f_ovf f_wmrk_flag event description 0 x no fifo overflow events detected. 1 x fifo overflow event detected. x 0 no fifo watermark event detected. x1 a fifo watermark event was detected indicating that a fifo sample count greater than watermark value has been reached. if f_setup[ f_mode ] = 0b11, a fifo trigger event was detected table 16. dr_status description
sensors freescale semiconductor, inc. 29 9.1.4 trig_cfg (0x0a) register fifo trigger configuration register. afte r the interrupt flag of the enabled event in trig_cfg is set, the fifo (when configur ed in trigger mode) is gated at the time of the interrupt event preventing the further collection of data samples. this allows the host processor to analyze the data leading up to the event detection (up to 32 samples). for detailed information on how to utilize the fifo and the various trigger events, please se e an4073 available on the freescale website. 9.1.5 sysmod (0x0b) register the system mode register indicates the current device ope rating mode. applications using the auto-sleep/auto-wake mechanism should use this regi ster to synchronize their app lication with the device operating mode. the system mode register also indicates the status of the fifo gate error flag and the time elapsed since the fifo gate error flag was asserted. table 18. fifo sample count bit description field description f_cnt[5:0] these bits indicate the number of acceleration samples currently stored in the fifo buffer. count 0b000000 indicates that the fifo is empty. fifo sample counter. default value 0b000000. (0b000001 to 0b100000 indicates 1 to 32 samples stored in fifo ? ? trig_trans trig_lndprt trig_pulse tria_ffmt trig_a_vecm ? 00000000 figure 13. trig_cfg register table 19. trig_cfg bit descriptions field description trig_trans transient interrupt fifo trigger enable. trig_lndprt landscape/portrait orientation interrupt fifo trigger enable. trig_pulse pulse interrupt fifo trigger enable tria_ffmt freefall/motion interrupt fifo trigger enable trig_a_vecm acceleration vector magnitude fifo trigger enable. fgerr fgt[4:0] sysmod[1:0] figure 14. sysmod register table 20. sysmod bit description field description fgerr fifo gate error. default value: 0. 0: no fifo gate error detected. 1: fifo gate error was detected. emptying the fifo buffer clears the fgerr bit in the sysmod register. see ctrl_reg3 [interrupt ctrl register] (0x2c) for mo re information on configuri ng the fifo gate function. fgt[4:0] number of odr time units since fgerr was asserted. reset when fgerr is cleared sysmod[1:0] system mode. default value: 0. 00: standby mode 01: wake mode 10: sleep mode
sensors 30 freescale semiconductor, inc. 9.1.6 int_source (0x0c) register interrupt source register. the bits that are set (logic ?1?) i ndicate which function has asserted its interrupt and conversely bits that are cleared (logic ?0?) indicate which function has not assert ed its interrupt. additional interrupt flags for magnetic interru pt events are located in the m_int_src register (0x5e). reading the int_source register does not clear any interrupt status bits (except src_a_vecm, see below); the respective interrupt flag bits are reset by reading the appropriate interrupt source register for the functi on that generated the interrup t. src_aslp src_fifo src_trans src_lndprt src_pulse src_ffmt src_a_vecm src_drdy figure 15. int_source register table 21. int_source bit descriptions field description src_aslp auto-sleep/wake interrupt status bit: logic ?1? indicates that an interrupt event that can cause a wake to sleep or sleep to wake system mode transition has occurred and logic ?0? indicates that no wake to sleep or sleep to wake system mode transition interrupt event has occurred. the ?wake-to-sleep? transition occurs when a period of i nactivity that exceeds the user specified time limit (aslp_count) has been detected, thus causing the system to transition to a user specified low odr setting. a ?sleep-to-wake? transition occurs when the user specified interrupt event has awakened the system, thus causing the system to transition to the us er specified higher odr setting. reading the sysmod register will clear the src_aslp bit. src_fifo fifo interrupt status bit: logic ?1? indicates that a fifo interrupt event such as an overflow or watermark (f_status[ f_cnt ] = f_status[ f_wmrk ]) event has occurred and logic ?0? indicate s that no fifo interrupt event has occurred. this bit is cleared by reading the f_status register. src_trans transient interrupt status bit: logic ?1? indicates that an ac celeration transient value greater than user specified threshold has occurred. and logic ?0? indicates that no transient event has occurred. this bit is asserted whenever transient_src[ ea ] is asserted and the functional block interrupt has been enabled. this bit is cleared by readi ng the transient_src register. src_lndprt landscape/portrait orientation interrupt status bit: logic ?1? indicates that an interrupt was generated due to a change in the device orientation status and logic ?0? indicates t hat no change in orientation status was detected. this bit is asserted whenever pl_status[ newlp ] is asserted and the functional block interrupt has been enabled. this bit is cleared by r eading the pl_status register. src_pulse pulse interrupt status bit: logic ?1? indicates that an in terrupt was generated due to single and/or double pulse event and logic ?0? indicates that no pulse event was detected. this bit is asserted whenever pulse_src[ ea ] is asserted and the functional block interrupt has been enabled. this bit is cleared by r eading the pulse_src register. src_ffmt freefall/motion interrupt status bit: logic ?1? indicates that the freefall/motion function interrupt is active and logic ?0? indicates that no freefall or motion event was detected. this bit is asserted whenever pulse_src[ ea ] is asserted and the functional block interrupt has been enabled. this bit is cleared by readi ng the a_ffmt_src register. src_a_vecm accelerometer vector magnitude interrupt st atus bit: logic ?1? indicates that an interrupt was generated due to acceleration vector magnitude function and logic ?0? indicates that no interrupt has been generated. this bi t is cleared by reading this register (int_source). src_drdy data-ready interrupt status bit. in acceleration only mode this bi t indicates that new accelerome ter data is available to read. in magnetometer only mode, src_drdy indicates that new magnetic data is avail able to be read. in hybrid mode, this bit signals that new acceleration and/or magnetic data is available. the src_drdy interrupt is cleared by reading out the acceleration data in accelerometer only mode and by reading out the magnetic data in magnetometer only or hybrid modes. in hybrid mode and with m_ctrl_reg2[ hyb_autoinc_mode ] = 1, all of the sensor data can be read out in a 12 byte burst read starting at register 0x01 (out_x_msb).
sensors freescale semiconductor, inc. 31 9.1.7 who_am_i (0x0d) register device identification register. this register contains the device identifier which is set to 0xc4 for preproduction devices and 0xc7 for production devices. 9.1.8 ctrl_reg1 (0x2a) register note: except for standby mode selection, the device must be in standby mode to change any of the fields within ctrl_reg1 (0x2a). it is important to note that when the device is in auto-sl eep mode, the system odr and data rate for all the system functional blocks is overridden by the sleep data rate set by the aslp_rate field. when hybrid m ode is enabled, the frequency is one-half of what is shown in ta b l e 2 2 . for example, with aslp_rate = 0b00 the frequency is 25 hz. table 24 shows the various system outp ut data rates (odr) that may be selected us ing the dr[2 :0] bits. the se lected odr is reduced by a factor of two when th e device is operated in hybrid mode. who_am_i[7:0] 0xc7 figure 16. who_am_i register aslp_rate[1:0] dr[2:0] lnoise f_read active 0 0b001 0 0 0 figure 17. ctrl_reg1 register table 22. ctrl_reg1 bit descriptions field description aslp_rate[1:0] configures the auto-wake sample frequency when the device is in sleep mode. see table 22 for more information. dr[2:0] output data rate (odr) selection. see table 23 for more information. lnoise reduced noise and full-scale range mode (analog gain times 2). 0: normal mode 1: reduced noise mode; note that the fsr setting is restricted to a 4g in this mode (lnoise = 1). f_read fast-read mode: data format is limited to the 8-bit msb for both magnetometer and accelerometer output data. the address pointer will skip over the lsb addresses for each ax es sample data when performing a burst read operation. 0: normal mode 1: fast-read mode active standby/active. 0: standby mode 1: active mode table 23. sleep mode poll rate description aslp_rate1 aslp_rate0 frequency (hz) 0 05 0 0 1 12.5 1 06 . 2 5 1 1 1.56
sensors 32 freescale semiconductor, inc. the active bit selects between standby mode and active mode. the default value is 0 (standby mode) on reset. the lnoise bit selects between normal full dynamic range mode and a high sensitivity, low-noise mode. in low-noise mode the maximum signal that can be measured is 4g. note: any thresholds set above 4g will not be reached. the f_read bit selects between normal and fast-read modes where the auto-increment counter will also skip over the lsb data bytes when f_read = 1. data read from the fifo will also skip over th e lsb data, reducing the data acquisition time. in hybrid mode and with m_ctrl_reg2[ hyb_autoinc_mode ] = 1, all of the sensor data msb's can be read out with a single 6-byte burst read starting at the out_x_msb register. note: the f_read bit can only be changed while f_setup[ f_mode ] = 0 9.1.9 ctrl_reg2 (0x2b) register table 24. system output data rate selection dr2 dr1 dr0 odr accelerometer or magnetometer only modes (hz) period accelerometer or magnetometer only modes (ms) odr hybrid mode (hz) period hybrid mode (ms) 0 0 0 800.0 1.25 400 2.5 0 0 1 400.0 2.5 200 5 0 1 0 200.0 5 100 10 0 1 1 100.0 10 50 20 1 0 0 5 0 . 02 02 58 0 1 0 1 12.5 80 6.25 160 1 1 0 6.3 160 3.15 320 1 1 1 1.6 640 0.8 1280 st rst ? smods[1:0] slpe mods[1:0] 000000 figure 18. ctrl_reg2 register table 25. ctrl_reg2 bit descriptions field description st the st bit activates the accelerometer self-test function. when st is set to 1, an output change will occur to the device outputs thus allowing the host applicati on to check the functionality of t he entire measurement signal chain. self-test enable: 0: self-test disabled 1: self-test enabled. rst the rst bit is used to initiate a software reset. the reset me chanism can be enabled in both standby and active modes. when the rst bit is set, the boot mechanism resets al l functional block registers and loads the re spective internal registers with their default values. after setting the rst bit, the system will automatical ly transition to standby mode. therefore, if the system was already in standby mode, the reboot process will immediately begin; else if the system was in active mode the boot mechanism will automatically transition the system from active mode to standby mode, only then can the reboot process begin. a system reset can also be initiated by pulsing the external rst pin high . the i 2 c and spi communication systems are also reset to avoid corrupted data transactions. the host application should allow 1 ms between issuing a software (setting rst bit) or hardware (pulsing rst pin) re set and attempting communications with the device over the i 2 c or spi interfaces. at the end of the boot process the rst bit is deasserted to 0. reading this bit will always return a value of 0. 0: device reset disabled 1: device reset enabled. smods[1:0] sleep mode power scheme selection. see table 25 for more information. slpe (1) 1. when slpe = 1, a transition between sleep mode and wake mode result s in a fifo flush and a reset of internal functional block counters. all functional block status information is preserved except where otherwise stated. for further information, refer to the crtl_ reg3 register description (fifo_gate bit). auto-sleep mode enable: 0: auto-sleep is not enabled 1: auto-sleep is enabled. mods[1:0] accelerometer osr selection. this setting, along with the o dr selection determines the active mode power and rms noise for acceleration measurements. see table 25 for more information.
sensors freescale semiconductor, inc. 33 9.1.10 ctrl_reg3 [interrupt control register] (0x2c) register table 26. ctrl_reg2[mods] oversampling modes (s)mods1 (s)mods0 power mode 00n o r m a l 0 1 low noise, low power 1 0 high resolution 1 1 low power table 27. current consumption versus oversampling mode normal low noise, low power high resolution low power odr current a os ratio current a os ratio current a os ratio current a os ratio 1.5625 37 128 8 32 245 1024 7 16 6.25 37 32 11 8 245 256 9 4 12.5 37 16 14 4 245 128 11 2 50 37 4 37 4 245 32 22 2 100 67 4 67 4 245 16 37 2 200 126 4 126 4 245 8 67 2 400 245 4 245 4 245 4 126 2 800 245 2 245 2 245 2 245 2 fifo_gate wake_trans wake_lndprt wake_pulse wake_ffmt wake_en_a_vecm ipol pp_od 000 0 0 0 0 0 figure 19. ctrl_reg3 register table 28. ctrl_reg3 bit descriptions field description fifo_gate 0: fifo gate is bypassed. fifo is flushed upon the system mode transitioni ng from wake-to-sleep mode or from sleep- to-wake mode. 1: the fifo input buffer is blocked when transitioning from ?wake-to-sleep? mode or from ?sleep-to-wake? mode until the fifo is flushed. (1) although the system transitions from ?wake-to-sleep ? or from ?sleep-to-wake? the contents of the fifo buffer are preserved, new data samples are ignored until the fifo is emptied by the host application. if the fifo_gate bit is set to logic ?1? and the fifo buffer is not emptied before the arrival of the next sample, then the sysmod[ fgerr ] will be asserted. the sysmod[ fgerr ] bit remains asserted as long as the fifo buffer remains un- emptied. emptying the fifo buffer clears the sys_mod[ fgerr ] register. wake_tran 0: transient function is disabled in sleep mode 1: transient function is enabled in sleep mode and can generate an interrupt to wake the system wake_lndprt 0: orientation function is disabled sleep mode. 1: orientation function is enabled in sleep mode and can generate an interrupt to wake the system wake_pulse 0: pulse function is disabled in sleep mode 1: pulse function is enabled in sleep mode and can generate an interrupt to wake the system wake_ffmt 0: freefall/motion function is disabled in sleep mode 1: freefall/motion function is enabled in sleep mo de and can generate an interrupt to wake the system wake_en_a_vecm 0: acceleration vector magnitude f unction is disabled in sleep mode 1: acceleration vector magnitude function is enabled in sleep mode and can generate an interrupt to wake the system
sensors 34 freescale semiconductor, inc. 9.1.11 ctrl_reg4 [interrupt enable register] (0x2d) register the corresponding functional block interrupt enable bit allows the functional block to route its event detection flag to the sy stem?s interrupt controller. the interrupt controller routes the enabled in terrupt signals to either the int1 or int2 pins depending o n the settings made in ctrl_reg5. please note that the interrupt enable bits for the magnetic threshold and vector magnitude interrupts are located in registers 0x52 (mag_th s_cfg), and 0x69 (m_vecm_cfg), respectively. ipol the ipol the bit selects the logic polarity of the interrupt signals output on the int1 and int2 pins. int1/int2 interrupt logic polarity: 0: active low (default) 1: active high pp_od int1/int2 push-pull or open-drain output mode selection. the open-drain configuration can be used for connecting multiple interrupt signals on the same interrupt line but wi ll require an external pullup re sistor to function correctly. 0: push-pull (default) 1: open-drain 1. the fifo contents are flushed whenever the system odr changes in order to prevent the mixing of fifo data from different time domains. the wake enable bits for the magnetic threshold and magnetic vector magnitude functions are located in registers 0x52 (mag_ths_cfg) and 0x69 (m_vecm_cfg), respectively. int_en_aslp int_en_fifo int_en_trans int_en_lndprt int_en_pulse int_en_ffmt int_en_a_vecm int_en_drdy 00000000 figure 20. ctrl_reg4 register table 29. interrupt enable register bit descriptions field description int_en_aslp sleep interrupt enable 0: auto-sleep/wake interrupt disabled 1: auto-sleep/wake interrupt enabled int_en_fifo fifo interrupt enable 0: fifo interrupt disabled 1: fifo interrupt enabled int_en_trans transient interrupt enable 0: transient interrupt disabled 1: transient interrupt enabled int_en_lndprt orientation interrupt enable 0: orientation (landscape/portrait) interrupt disabled 1: orientation (landscape/portrait) interrupt enabled int_en_pulse pulse interrupt enable 0: pulse detection interrupt disabled 1: pulse detection interrupt enabled int_en_ffmt freefall/motion interrupt enable 0: freefall/motion interrupt disabled 1: freefall/motion interrupt enabled int_en_a_vecm acceleration vector magnitude interrupt enable 0: acceleration vector magnitude interrupt disabled 1: acceleration vector magnitude interrupt enabled int_en_drdy data-ready interrupt enable 0: data-ready interrupt disabled 1: data-ready interrupt enabled table 28. ctrl_reg3 bit descriptions
sensors freescale semiconductor, inc. 35 9.1.12 ctrl_reg5 [interrupt routing configuration register] (0x2e) register please note that the routing configuration for th e magnetic threshold interrupt is controlled by m_ths_int_cfg bit located in register 0x52 (mag_ths_cfg), and the magnetic vector magnitude function routing is controlled by m_vecm_int_cfg bit in register 0x69 (m_vecm_cfg). int_cfg_aslp int_cfg_fifo int_cfg_trans int_cfg_lndprt int_cfg_pulse int_cfg_ffmt int_cfg_a_vecm int_cfg_drdy 00000000 figure 21. ctrl_reg5 register table 30. interrupt routing configuration bit descriptions field description int_cfg_aslp sleep interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin int_cfg_fifo fifo interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin int_cfg_trans transient detection interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin int_cfg_lndprt orientation detection interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin int_cfg_pulse pulse detection interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin int_cfg_ffmt freefall/motion detection interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin int_cfg_a_vecm acceleration vector magnitude interrupt routing 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin. int_cfg_drdy int1/int2 configuration. 0: interrupt is routed to int2 pin 1: interrupt is routed to int1 pin.
sensors 36 freescale semiconductor, inc. figure 22. interrupt controller block diagram the system?s interrupt controller uses the corresponding bit field in the ctrl_reg5 register to determine the routing for the i nt1 and int2 interrupt pins. for example, if the int_cfg_drdy bit value is logic ?0? the functional block?s interrupt is routed to int2, and if the bit value is logic ?1? then the interr upt is routed to int1. all interrupt signals routed to either int1 or int2 are log ically ored together as illustrated in figure 23 , thus one or more functional blocks can assert an interrupt pin simultaneously; therefore a host application responding to an interrupt should read the int_source register to determine th e appropriate sources of the interrupt(s). figure 23. int1/int2 pin control logic 9.2 auto-sleep trigger 9.2.1 aslp_count (0x29) register the aslp_count register sets the minimum time period of event flag inactivity required to init iate a change from the current active mode odr value specified in ctrl_reg1[ dr ] to the sleep mode odr value specified in ctrl_reg1[ aslp_rate ], provided that ctrl_reg2[ slpe] = 1. see table 32 for functional blocks that may be monitored for inactivity in order to trigger the return-to-sleep event. interrupt controller data ready freefall/motion detection pulse detection orientation detection transient acceleration detection auto-sleep int enable int cfg int1 int2 99 acceleration vector magnitude magnetic vector magnitude magnetic threshold detection fifo interrupt int1 int2 src_rts src_fifo src_pulse src_ff_mt or or src_drdy
sensors freescale semiconductor, inc. 37 please note that when the device is operated in hybrid mode, the effective odr is half of wh at is selected in ctrl_reg1[ dr ]. for example, with odr = 800 hz and the device set to hy brid mode, the aslp_count time step becomes 640 ms. * if the fifo_gate bit is set to logic ?1?, the assertion of t he src_aslp interrupt does not prevent the system from transition ing to sleep or from wake mode; instead it prevents the fifo buffer from accepting new samp le data until the host application flushes the fifo buffer. the interrupt sources listed in table 33 affect the auto-sleep, return to sleep and wa ke from sleep mechanism only if they have been previously enabled. the functional block event flags that are bypassed while the system is in auto-sleep mode are temporary disabled (see ctrl_reg3 register for more information) and are automatically re-enabled when the device returns from auto-sleep mode (i.e. wakes up), except for the data ready function. if any of the interrupt sources listed under the return-to-sleep column is asserted before the sleep counter reaches the value specified in aslp_count, then all sleep mode transitions are termi nated and the internal sleep counter is reset. if none of the interrupts listed under the return-to-sleep column are asserted within the time limit specified by the aslp_count register, the system will transition to the sleep mode and use the odr value specified in ctrl_reg1[ aslp_rate ]. aslp_cnt[7:0] 0b00000000 figure 24. aslp_count register table 31. aslp_count bit description field description aslp_cnt[7:0] see table 31 for details table 32. aslp_count relationship with odr output data rate (odr) duration (s) odr time step (ms) aslp_count step (ms) 800 0 to 81 1.25 320 400 0 to 81 2.5 320 200 0 to 81 5 320 100 0 to 81 10 320 50 0 to 81 20 320 12.5 0 to 81 80 320 6.25 0 to 81 160 320 1.56 0 to 163 640 640 table 33. sleep/wake mo de gates and triggers interrupt source event restarts time and delays return-to-sleep event will wake-from-sleep src_fifo yes no src_trans yes yes src_lndprt yes yes src_pulse yes yes src_ffmt yes yes src_aslp no* no* src_mag yes yes src_drdy no no src_avecm yes yes src_mvecm yes yes src_mths yes yes
sensors 38 freescale semiconductor, inc. if any of the interrupt sources listed und er the ?wake-from-sleep? column is assert ed, then the system will transition out of t he low sample rate auto-sleep mode to the user specified fast sa mple rate provided the user s pecified wake event function is enabled in register ctrl_reg3. if the auto-sleep interrupt is enabled, a transition from active mode to sleep m ode and vice-versa will generate an interrupt. if ctrl_reg3[ fifo_gate ] = 1, transitioning to auto -sleep mode will preserve th e fifo contents, set sysmod[ fgerr ] (fifo gate error), and stop new acquisitions. the syst em will wait for the fifo buffer to be emptied by the host application before new samples can be acquired. figure 25. auto-sleep state transition diagram 9.3 temperature 9.3.1 temp (0x51) register 8-bit 2?s compliment sensor temperatur e value with 0.96c/lsb resolution. temper ature data is only valid between -40c and 125c. 9.4 accelerometer output data registers 9.4.1 out_x_msb (0x01), out_x_lsb (0x02), out_y_msb (0x03), out_y_lsb (0x04), out_z_msb (0x05), out_z_lsb (0x06) registers these registers contain the x-axis , y-axis, and z-axis 14-bit left-justified sa mple data expressed as 2's complement numbers. the sample data output registers store the current sample data if the fifo buffer func tion is disabled, but if the fifo buffer function is enabled the sample data output r egisters then point to the he ad of the fifo buffer which co ntains up to the previou s 32 x, y, and z data samples. the data is read out in the following order: xmsb, xlsb, ymsb, ylsb, zmsb, zlsb for ctrl_reg1[ f_read ] = 0, and xmsb, ymsb, zmsb for ctrl_reg1[ f_read ] = 1. if the device is operating in hybrid mode and m_ctrl_reg2[ hyb_autoinc_mode ] = 1, the data read out order is acceleration xmsb, xlsb, ymsb, ylsb, zmsb, and zlsb followed by magnetic data xmsb, xlsb, ymsb, ylsb, zmsb, zlsb. similarly, for ctrl_reg1[ f_read ] = 1, only the msb's of the acceleration and magnetic data are read out in the same axis order. if the ctrl_reg1[ f_read ] bit is set, auto increment will skip over the lsb r egisters. this will short en the data acquisition from 7 bytes to 4 bytes, if the lsb registers are directly addre ssed, the lsb information can still be read regardless of the ctrl_reg1[ f_read ] register setting. die_temperature[7:0] figure 26. temp register acquire standby no sleep standby sleep active mode auto-sleep mode slp_counter < slp_counter > aslp count aslp count
sensors freescale semiconductor, inc. 39 if the fifo data output regist er driver is enabled (f_setup[ f_mode ] > 00), register 0x01 points to the head of the fifo buffer, while registers 0x02, 0x03, 0x04, 0x05, 0x06 return a value of zero when read directly. the dr_status registers, out_x_msb, out_x_lsb, out_y_msb, out_y_l sb, out_z_msb, and out_z_lsb are stored in the auto-incrementing address range of 0x00 to 0x06, allowing all of the acceleration data to be read in a single bur st read of 6 bytes starting at the out_x_msb register . if the device is operating in hybrid mode and m_ctrl_reg2[ hyb_autoinc_mode ] = 1, the magnetometer data can also be re ad out in the same axis and endian order by executing a burst read of 12 bytes starting at register out_x_msb. 9.5 accelerometer fifo 9.5.1 f_setup (0x09) register xd[13:6] figure 27. out_x_msb register xd[5:0] ? ? figure 28. out_x_lsb register yd[13:6] figure 29. out_y_msb register yd[5:0] ? ? figure 30. out_y_lsb register zd[13:6] figure 31. out_z_msb register zd[5:0] ? ? figure 32. out_z_lsb register f_mode[1:0] f_wmrk[5:0] 00 figure 33. f_setup register
sensors 40 freescale semiconductor, inc. a fifo sample count exceeding the watermark event does not stop the fifo from accepting new data. the fifo upda te rate is dictated by the sele cted system odr. in active mode the odr is set by ctrl_reg1[ dr ] and when auto-sleep is active, the odr is set by ctrl_reg1[ aslp_rate ] bit fields. when data is read from the fifo buffer, the oldest sample data in the buffer is returned and also deleted from the front of the fifo, while the fifo sample count is decremented by one. it is assumed t hat the host application will use the i 2 c or spi burst read transactions to dump the fifo contents. if the fifo x, y, and z data is not completely read in one burst read transaction, the next read will start at the next fifo location x-axis data. if the y or z data is not read out in the same burst transactio n as the x-axis data, it will be lost. in trigger mode, the fifo is o perated as a circular buffer and will contain up to the 32 most recent acceleration data samples. the oldest sample is discarded and replaced by the current sa mple, until a fifo trigger event occurs. after a trigger event occ urs, the fifo will continue to accept samples only until overflowed, after which point the newest sample data is discarded. for more information on using the fifo buffer and the various fifo ope rating modes, please refer to freescale application note an4073. 9.6 accelerometer sensor data configuration 9.6.1 xyz_data_cfg (0x0e) register the xyz_data_cfg register is used to configure the desired accele ration full-scale range, and also to select whether the output data is passed through the high-pass filter. table 34. f_setup bit descriptions field description f_mode[1:0] (1)(2)(3) 1. this bit field can be written in active mode. 2. this bit field can be written in standby mode. 3. the fifo mode ( f_mode ) cannot be switched between operational modes (01, 10 and 11). fifo buffer operating mode. 00: fifo is disabled. 01: fifo contains the most recent samples when overflowed (c ircular buffer). oldest sample is discarded to be replaced by new sample. 10: fifo stops accepting new samples when overflowed. 11: fifo trigger mode. the fifo is flushed whenever the fifo is disabled, dur ing an automatic odr change (auto-wake/sleep), or on a transition from standby mode to active mode. disabling the fifo ( f_mode = 0b00) resets the f_status[ f_ovf ], f_status[ f_wmrk_flag ], f_status[ f_cnt ] status flags to zero. a fifo overflow event (i.e. f_status[ f_cnt] = 32) will assert the f_status[ f_ovf ] flag. f_wmrk[5:0] (2) fifo sample count watermark. these bits set the number of fifo samples required to tr igger a watermark interrupt. a fifo watermark event flag f_status[ f_wmk_flag ] is raised when fifo sample count f_status[ f_cnt] value is equal to or greater than the f_ wmrk watermark. setting the f_wmrk to 0b000000 will disable the fifo watermark event flag generation. this field is also used to set the number of pre-trigger samples in trigger mode ( f_mode = 0b11). ? ? ? hpf_out ? ? fs[1:0] 000000 0 figure 34. xyz_dat a_cfg register table 35. xyz_data_cfg bit descriptions field description hpf_out enable high-pass filter on acceleration output data 1: output data is high-pass filtered 0: high-pass filter is disabled. fs[1:0] accelerometer full-scale range selection. see table 35
sensors freescale semiconductor, inc. 41 9.7 accelerometer high-pass filter 9.7.1 hp_filter_cutoff (0x0f) register high-pass filter cutoff frequency setting register. table 36. fs[1] fs[0] full-scale range 0 0 0.244 mg/lsb 0 1 0.488 mg/lsb 1 0 0.976 mg/lsb 11 r e s e r v e d ? ? pulse_hpf_byp pulse_lpf_en ? ? sel[1:0] 000000 0 figure 35. hp_filte r_cutoff register table 37. hp_filter_cutoff bit descriptions field description pulse_hpf_byp bypass high-pass filter fo r pulse processing function 0: hpf enabled for pulse processing 1: hpf bypassed for pulse processing pulse_lpf_en enable low-pass filter fo r pulse processing function 0: lpf disabled for pulse processing 1: lpf enabled for pulse processing sel[1:0] hpf cutoff frequency selection see table 37 . table 38. hp_filter_cutoff high-pass cutoff frequency (hz) odr (hz) sel = 0b00 sel = 0b01 normal lpln high resolution low power normal lpln high resolution low power 8 0 01 61 61 61 68888 4 0 01 61 61 688884 2 0 0881 644482 1 0 0441 622281 5 0221 611180 . 5 12.5 2 0.5 16 0.25 1 0.25 8 0.125 6.25 2 0.25 16 0.125 1 0.125 8 0.063 1.56 2 0.063 16 0.031 1 0.031 8 0.016 odr (hz) sel = 0b10 sel = 0b11 normal lpln high resolution low power normal lpln high resolution low power 8 0 044442222 4 0 044422221 2 0 022411120 . 5 100 1 1 4 0.5 0.5 0.5 2 0.25 50 0.5 0.5 4 0.25 0.25 0.25 2 0.125
sensors 42 freescale semiconductor, inc. please note that when the part is operated in hybrid mode, the odr is reduced by a factor of tw o, which also affects the filter cutoff frequency. for example, an odr setting of 400 hz in accelerometer only mode with hp_filter_cutoff[ sel ] = 0b10 sets the cutoff frequency at 4 hz. if the part is operated in hybrid mode, the effective odr becomes 200 hz and the cutoff frequency is now 2 hz for the same odr and hp_filter_cutoff[ sel ] settings. 9.8 portrait/landscape detection the FXOS8700CQ is capable of detecting six orientations: landsca pe left, landscape right, portrait up, and portrait down with z-lockout feature as well as face up and face down orientation as shown in figures 36 , 37 and 38 . for more details on the meaning of the different user configurable settings and for ex ample code, please refer to freescale application note an4068. figure 36. illustration of z-tilt angle lockout transition . figure 37. illustration of landscape to portrait transition 12.5 0.5 0.125 4 0.063 0.25 0.063 2 0.031 6.25 0.5 0.063 4 0.031 0.25 0.031 2 0.016 1.56 0.5 0.016 4 0.008 0.25 0.008 2 0.004 table 38. hp_filter_cutoff normal 90 z-lock = 32.142 0 detection lockout region portrait landscape to portrait 90 trip angle = 60 0 landscape
sensors freescale semiconductor, inc. 43 . figure 38. illustration of portrait to landscape transition 9.8.1 pl_status (0x10) register this status register can be read to get updated information on an y change in orientation by reading bit 7, or the specifics of the orientation by reading the other bits. for further understandin g of portrait up, portrait do wn, landscape left, landscape right , back and front orientations please refer to figure 38 . the interrupt is cleared when reading the pl_status register. the newlp bit is set to 1 after the first orientation detection af ter a standby to active transition, and whenever a change in lo, bafro , or lapo occurs. the newlp bit is cleared anytime the pl_status register is read. lapo, bafro and lo continue to change when newlp is set. the current orientation is locke d if the absolute value of the acceleration experienced on any of the three axes is greater than 1.25g. newlp lo ? ? ? lapo[1:0] bafro 0 000000 figure 39. pl_status register table 39. pl_status bit descriptions field description newlp landscape/portrait status change flag. 0: no change 1: bafro and/or lapo and/or z-tilt lockout value has changed lo z-tilt angle lockout. 0: lockout condition has not been detected. 1: z-tilt lockout trip angle has been exceeded. lockout condition has been detected. bafro back or front orientation. 0: front: equipment is in the front facing orientation. 1: back: equipment is in the back facing orientation. lapo[1:0] (1) 1. the default power up state is bafro(undefined), lapo( undefined), and no lockout for orientation function. landscape/portrait orientation. 00: portrait up: equipment standing vertically in the normal orientation 01: portrait down: equipment standing vertically in the inverted orientation 10: landscape right: equipment is in landscape mode to the right 11: landscape left: equipment is in landscape mode to the left. portrait portrait to landscape 90 trip angle = 30 0 landscape
sensors 44 freescale semiconductor, inc. 9.8.2 pl_cfg (0x11) register this register enables the portrait/landscape function and sets the behavior of the debounce counter. 9.8.3 pl_count (0x12) register this register sets the debounce count for the orientation stat e transition. the minimum debounce latency is determined by the system odr value and the value of the pl_count register. any change to the system odr or a transition from active to standby (or vice-versa) resets the internal landscape/portrait internal debounce counters. when the device is operated in hybri d mode, the effective odr will be half of what is selected by the user, which will also affect the debounce time. for example, if an odr of 400 hz is selected and the part is also in hybrid mode, the effective odr is 200 hz, and the effective debounce time step is 5 ms instead of 2.5 ms 9.8.4 pl_bf_zcomp (0x13) register back/front and z-tilt angle compensation register d b c n t mp l _ e n?????? 10000011 figure 40. pl_cfg register table 40. pl_cfg bit descriptions field description dbcntm debounce counter mode selection. 0: decrements debounce whenever condition of interest is no longer valid. 1: clears counter whenever condition of interest is no longer valid. pl_en portrait/landscape detection enable. 0: portrait/landscape detection is disabled. 1: portrait/landscape detection is enabled. dbnce[7:0] 0 figure 41. pl_count register table 41. pl_count relationship with the odr odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 40.8 0.638 40.8 20 160 2.5 160 1.56 5.1 163 0.638 163 20 640 2.5 640 bkfr[1:0] ? ? ? zlock[2:0] 0000 0b010 figure 42. pl_bf_zcomp register
sensors freescale semiconductor, inc. 45 9.8.5 pl_ths_reg (0x14) register portrait to landscape trip threshold registers. table 42. pl_bf_zcomp bit descriptions field description zlock[2:0] z-lock angle threshold. range is from 13 to 44. step size is approximately 4. see table 42 for more information. default value: 00 13 . maximum value: 07 44 . bkfr[1:0] back/front trip angle threshold. see table 43 for more information. default: 10 75. step size is 5. range: (65 to 80). table 43. z-lockout angle definitions zlock resultant angle (min) for positions between landscape and portrait resultant angle (max) for ideal landscape or portrait 0x00 13.6 14.5 0x01 17.1 18.2 0x02 20.7 22.0 0x03 24.4 25.9 0x04 28.1 30.0 0x05 32.0 34.2 0x06 36.1 38.7 0x07 40.4 43.4 table 44. back/front orientation definitions bkfr back front transition front back transition 00 z < 80 or z > 280 z > 100 and z < 260 01 z < 75 or z > 285 z > 105 and z < 255 10 z < 70 or z > 290 z > 110 and z < 250 11 z < 65 or z > 295 z > 115 and z < 245 pl_ths[4:0] hys[2:0] 0b00011 0b010 figure 43. pl_ths_reg register table 45. threshold angle lookup table threshold angle (approx.) 5-bit register value 15 0x07 20 0x09 30 0x0c 35 0x0d 40 0x0f 45 0x10 55 0x13 60 0x14 70 0x17 75 0x19
sensors 46 freescale semiconductor, inc. 9.9 freefall and motion detection the freefall/motion detection block can be configured to detect low-g (freefall) or high-g (motion) events utilizing the a_ffmt_cfg[ a_ffmt_oae ] bit. in low-g detect mode (a_ffmt_cfg[ a_ffmt_oae ] = 0) a low-g condition will need to occur on all enabled axes (ex. x, y and z) for the a_ffmt_src[ a_ffmt_ea ] bit to be affected. and, in high-g detect mode (a_ffmt_cfg[ a_ffmt_oae ] = 1) a high-g condition occurring in any of the enabled axes (ex. x, y or z) will suffice to affect the a_ffmt_src [ a_ffmt_ea ] bit. the detection threshold(s) are programed in register 0x17 (a_ffmt_ths) for comm on threshold operation, and 0x73-0x78 (a_ffmt_ths_x/y/z) for individual axis threshold operation. a_ffmt_cfg[ a_ffmt_ele ] bit determines the behavior of a_ffmt_src[ a_ffmt_ea ] bit in response to t he desired acceleration event (low-g/high-g). when a_ffmt_cfg[ a_ffmt_ele ] = 1, the freefall or moti on event is latched and the a_ffmt_src[a_ffmt_ea] flag can only be cleared by reading the a_ffmt_src register. when a_ffmt_cfg[ a_ffmt_ele ] = 0, freefall or motion events are not latched , and the a_ffmt_src[ a_ffmt_ea ] bit reflects the real-time status of the event detection. a_ffmt_ths[ a_ffmt_dbcntm ] bit determines the debounce filtering behavior of the logic which sets the a_ffmt_src[ a_ffmt_ea ] bit. see figure 55 for details. it is possible to enable/disable each axis used in the freefall/motion detection func tion by configuring bits a_ffmt_cfg[ a_ffmt_xefe ], a_ffmt_cfg[ a_ffmt_yefe ], and a_ffmt_cfg[ a_ffmt_zefe ]. the freefall/motion detection function has the option to use a common 7-bit unsigned th reshold for each of the x, y, z axes, or individual unsigned 13-bit thresholds for each axis. when a_ffmt_ths_x_msb[ a_ffmt_ths_xyz_en ] = 0, the 7-bit threshold value stored in register 0x17 is used as a co mmon 7-bit threshold for the x, y, and z axes. when a_ffmt_ths_xyz_en = 1, each axis may be programmed with an individual 13-bit thres hold (stored in the a_ffmt_x/y/z msb and lsb registers). 9.9.1 a_ffmt_cfg (0x15) register freefall/motion configuration register. table 46. trip angles versus hysteresis settings hysteresis register value landscape to portrait trip angle portrait to landscape trip angle 04 54 5 14 94 1 25 23 8 35 63 4 45 93 1 56 22 8 66 62 4 76 92 1 table 47. portrait/landscape orientation definitions position description pu y ~ -1g, x ~ 0 pd y ~ +1g, x ~ 0 lr y ~ 0, x ~ +1g ll y ~ 0, x ~ -1g a_ffmt_ele a_ffmt_oae a_ffmt_zefe a_ffmt_yefe a_ffmt_xefe ? ? ? 000000 00 figure 44. a_ffmt_cfg register
sensors freescale semiconductor, inc. 47 9.9.2 a_ffmt_src (0x16) register freefall/motion source register. read-only register. this register keeps track of the acceleration event whic h is triggering (or has triggered, in case of a_ffmt_cfg[ a_ffmt_ele ] = 1) the event flag. in particular a_ffmt_src[ a_ffmt_ea ] is set to a logic ?1? when the logical combination of acceleration event flags specified in a_ffmt_cfg register is true. this bit is used in combination with the values in ctrl_reg4[ int_en_ffmt ] and ctrl_reg5[ int_cfg_ffmt ] register bits to generate the freefall/motion interrupts. table 48. a_ffmt_cfg bit descriptions field description a_ffmt_ele a_ffmt_ele denotes whether the enabled event flag will be latched in the a_ffmt_src register or the event flag status in the a_ffmt_src will indicate the real-time status of the event. if a_ffmt_ele bit is set to a logic ?1?, then the event flags are frozen when the a_ffmt_ea bit gets set, and are cleared by reading the a_ffmt_src source register. default value: 0 0: event flag latch disabled 1: event flag latch enabled a_ffmt_oae a_ffmt_oae bit allows the selection between motion (logical or comb ination of high-g x, y, z-axis event flags) and freefall (logical and combination of low-g x, y, z-axis event flags) detection. motion detect/freefall detect logic selection. default value: 0 (freefall flag) 0: freefall flag(logical and combination of low-g x, y, z-axis event flags) 1: motion flag (logical or combinat ion of high-g x, y, z event flags) a_ffmt_zefe a_ffmt_zefe enables the detection of a high or low-g event when the measured acceleration dat a on z-axis is above/below the threshold set in the a_ffmt_ths register. if the a_ffmt_ele bit is set to logic ?1? in the a_ffmt_cfg register, new event flags are blocked from updating the a_ffmt_src register. default value: 0 0: event detection disabled 1: raise event flag on measured z-ax is acceleration above/below threshold. a_ffmt_yefe a_ffmt_yefe enables the detection of a high or low-g event when the measured acceleration data on y-axis is above/below the threshold set in the a_ffmt_ths register. if the a_ffmt_ele bit is set to logic ?1? in the a_ffmt_cfg register, new event flags are blocked from updating the a_ffmt_src register. default value: 0 0: event detection disabled 1: raise event flag on measured y-axis acceleration above/below threshold. a_ffmt_xefe a_ffmt_xefe enables the detection of a high or low-g event when the measured acceleration dat a on x-axis is above/below the threshold set in the a_ffmt_ths register. if the a_ffmt_ele bit is set to logic ?1? in the a_ffmt_cfg register, new event flags are blocked from updating the a_ffmt_src register. default value: 0 0: event detection disabled 1: raise event flag on measured x-ax is acceleration above/below threshold. a_ffmt_ea ? a_ffmt_zhe a_ffmt_zhp a_ffmt_yhe a_ffmt_yhp a_ffmt_xhe a_ffmt_xhp 00000000 figure 45. a_ffmt_src register table 49. a_ffmt_src bit descriptions field description a_ffmt_ea event active flag. default value: 0 0: no event flag has been asserted 1: one or more event flag has been assert ed. see the description of the a_ffmt_cfg[ a_ffmt_oae ] bit to determine the effect of the 3-axis event flags on the a_ffmt_ea bit. a_ffmt_zhe z-high event flag. default value: 0 0: event detected 1: z-high event has been detected this bit always reads zero if the a_ffmt_zefe control bit is set to zero
sensors 48 freescale semiconductor, inc. 9.9.3 a_ffmt_ths (0x17), a_ffmt_ ths_x_msb (0x73), a_ffmt_ths_x_lsb (0x74), a_ffmt_ths_y_msb (0x75), a_ffmt_ths _y_lsb (0x76), a_ffmt_ths_z_msb (0x77), a_ffmt_ths_z_lsb (0x78) registers freefall/motion detection threshold registers. a_ffmt_zhp z-high event polarity flag. default value: 0 0: z event was positive g 1: z event was negative g this bit read always zero if the a_ffmt_zefe control bit is set to zero a_ffmt_yhe y-high event flag. default value: 0 0: no event detected 1: y-high event has been detected this bit read always zero if the a_ffmt_yefe control bit is set to zero a_ffmt_yhp y-high event polarity flag. default value: 0 0: y event detected was positive g 1: y event was negative g this bit always reads zero if the a_ffmt_yefe control bit is set to zero a_ffmt_xhe x-high event flag. default value: 0 0: no event detected 1: x-high event has been detected this bit always reads zero if the a_ffmt_xefe control bit is set to zero a_ffmt_xhp x-high event polarity flag. default value: 0 0: x event was positive g 1: x event was negative g this bit always reads zero if the a_ffmt_xefe control bit is set to zero a_ffmt_dbcntm ths[6:0] 0 0b0000000 figure 46. a_ffmt_ths (0x17) register table 50. a_ffmt_ths (0x17) bit descriptions field description a_ffmt_dbcntm the asic uses a_ffmt_dbcntm to set the acceleration ffmt debounce counter clear mode independent of the value of the a_ffmt_ths_xyz_en . a_ffmt_dbcntm bit configures the way in which the debounce counter is reset when the inertial event of interest is momentarily not true. when a_ffmt_dbcntm bit is a logic ?1?, the debounce counter is cleared to 0 whenever the inertial event of interest is no longer true (part b, figure 55 ) while if the a_ffmt_dbcntm bit is set to logic ?0? the debounce counter is decremented by 1 whenever the inertial event of interest in longer true (part c, figure 55 ) until the debounce counter reaches 0 or the inertial event of interest become active. the decrementing of the debounce counter acts to filter out irregular spurious events which might impede the correct detection of inertial events. ths[6:0] freefall/motion detection threshold: default value: 0b0000000. resolution is fixed at 63 mg/lsb. a_ffmt_ths_xyz_en a_ffmt_ths_x[12:6] 0 0b0000000 figure 47. a_ffmt_ths_x_msb (0x73) register table 49. a_ffmt_src bit descriptions
sensors freescale semiconductor, inc. 49 table 51. a_ffmt_ths_x_msb (0x73) bit descriptions field description a_ffmt_ths_xyz_en for a_ffmt_ths_xyz_en = 0 the asic uses the ffmt_ths [6:0] value located in register x17[6:0] as a common threshold for the x, y, and z-axis acceleration detection. the common unsigned 7-bit acceleration threshold has a fixed resolution of 63 mg/lsb, with a range of 0-127 counts. for a_ffmt_ths_xyz_en = 1 the asic ignores the common 7-bit g_ffmt_ths value located in register x17 when executing the ffmt function, and the following independent threshold values are used for each axis: a_ffmt_ths_x_msb and a_ffmt_ths_x_lsb are us ed for the x-axis acceleration threshold, a_ffmt_ths_y_msb and a_ffmt_ths_y_lsb for the y-axis acceleration threshold, a_ffmt_ths_z_msb and a_ffmt_ths_z_lsb for the z-axis acceleration threshold. the a_ffmt_ths_x/y/z thresholds are 13-bit unsigned values that have the same resolution as the accelerometer output data determined by xyz_data_cfg fs [1:0]. the a_ffmt_ths_xyz_en and a_ffmt_trans_ths_en bits must not be enabled simultaneously. a_ffmt_ths_x[12:6] 7-bit msb of x-axis acceleration threshold a_ffmt_ths_x[5:0] ? ? 0b000000 0 0 figure 48. a_ffmt_ths_x_lsb (0x74) register a_ffmt_trans_ths_en a_ffmt_ths_y[12:6] 0 0b0000000 figure 49. a_ffmt_ths_y_msb (0x75) register table 52. a_ffmt_ths_x_msb (0x73) bit descriptions field description a_ffmt_trans_ths_en for a_ffmt_trans_ths_en =0 the asic uses the tr_ths[6:0] value located in transient_ths (0x1f) register as a common threshold for the x, y, and z-axis transient ac celeration detection. the common unsigned 7-bit transient acceleration threshold has a fixed resoluti on of 63 mg/lsb with a range of 0-127 counts. for a_ffmt_trans_ths_en = 1 the asic ignores the common 7-bit tr_ths[6:0] value located in register x1f when executing the transient acceleration function, and the fo llowing independent threshold valu es are used for each axis: a_ffmt_ths_x_msb and a_ffmt_ths_x_lsb are used fo r the x-axis transient acceleration threshold, a_ffmt_ths_y_msb and a_ffmt_ths_y_lsb for the y-axis transient acceleration threshold, a_ffmt_ths_z_msb and a_ffmt_ths_z_lsb for t he z-axis transient ac celeration threshold. the a_ffmt_ths_x/y/z thresholds are 13-bit unsigned values that have the same resolution as the accelerometer output data determined by xyz_data_cfg fs [1:0]. the a_ffmt_ths_xyz_en and a_ffmt_trans_ths_en bits must not be enabled simultaneously a_ffmt_ths_y[12:6] 7-bit msb of y-axis acceleration threshold a_ffmt_ths_y[5:0] ? ? 0b000000 0 0 figure 50. a_ffmt_ths_y_lsb (0x76) register ? a_ffmt_ths_z[12:6] 0 0b0000000 figure 51. a_ffmt_ths_z_msb (0x77) register
sensors 50 freescale semiconductor, inc. figure 53. a_ffmt_ths high and low-g level a_ffmt_ths contains the unsigned 7-bit threshold value used by the freefall/motion detection f unctional block and is used to detect either low-g (freefall) or high-g (motio n) events depending on the setting of g_ffmt_cfg[ f_ffmt_oae ]. if g_ffmt_oae = 0, the event is detected when the absolute value of all the enabled axes are below the threshold value. when g_ffmt_oae = 1, the event is detected when the absolute value of any of the enabled axes is above the threshold value (see figure 53 for an illustration of the freefall/motion event detection thresholds). if a_ffmt_ths_x_msb[ a_ffmt_ths_xyz_en ] = 1, the behavior is identical, except that each axis may be programmed with an individual 13-bit thres hold (stored in the a_ffmt_x/y/z msb and lsb registers). 9.9.4 a_ffmt_count (0x18) register debounce count register for freefall/motion detection events this register sets the number of debounce counts for accelerati on sample data matching the user programmed conditions for either a freefall or motion detection event required before the interrupt is triggered. when the internal debounce counter reaches the a_ffmt_count value a freefall/motion event flag is set. the debounce counter will never increase beyond the a_ffmt_count value. th e time step used for the debounce sample count depends on the odr chosen (see table 53 ). when the device is operated in hybrid mode, the effective odr is half of what is selected in ctrl_reg1. this has the effect of dou bling the time-step values shown in ta b l e 5 3 . a_ffmt_ths_z[5:0] ? ? 0b000000 0 0 figure 52. a_ffmt_ths_z_lsb (0x78) register a_ffmt_count[7:0] 0b00000000 figure 54. a_ffmt_count register table 53. a_ffmt_count bit description field description a_ffmt_count[7:0] a_ffmt_count defines the minimum number of debounce sample count s required for the detection of a freefall or motion event. a_ffmt_ths[ ffmt_dbcntm ] determines the behavior of the counter when the condition of interest is momentarily not true. +full scale high-g positive threshold low-g threshold high-g negative threshold -full scale x, y, z high-g region x, y, z high-g region x, y, z low-g region negative positive acceleration acceleration (motion or of enabled axes) (freefall - and of enabled axes) (motion - or of enabled axes)
sensors freescale semiconductor, inc. 51 for example, an odr of 100 hz and a a_ ffmt_count value of 15 would result in minimum debounce response time of 150 ms. if the device is operated in hybr id mode, the effective debounce response time will be 300 ms for the same settings. figure 55. behavior of the a_ffmt debounce co unter in relation to the a_ffmt_dbcntm setting table 54. a_ffmt_count re lationship with the odr high-pass cutoff frequency (hz) odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution lp 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 40.8 0.638 40.8 20 160 2.5 160 1.56 5.1 163 0.638 163 20 640 2.5 640 low-g event on count threshold ea all 3-axis ff counter low-g event on count threshold (a) all 3-axis debounce counter low-g event on count threshold ea all 3-axis a_ffmt_dbcntm = 1 (b) ea a_ffmt_dbcntm = 1 (c) debounce counter
sensors 52 freescale semiconductor, inc. 9.10 accelerometer vector magnitude function the accelerometer vector magnitude function is an inertial event det ection function available to assist host software algorithm s in detecting motion events. if > a_vecm_ths for a time period greater than the value stored in a_vecm_cnt, the vector magnitude change event flag is triggered. a_x_out, a_y_out, and a_z_out are the current accelerometer output values, and a_x_ref, a_y_ref, and a_z_ref are the reference values stored internally in the asic for each axis or in a_vecm_init_x/y/ z registers if a_vecm_cfg[ a_vecm_initm ] is set. please note that the x_ref, y_ref, and z_ref values are not dire ctly visible to the host application through the register inter face. please refer to freescale application note 4458. 9.10.1 a_vecm_cfg (0x5f) register 9.10.2 a_vecm_ths_msb (0x60) register ? a_vecm_ele a_vecm_initm a_vecm_updm a_vecm_en ? ? ? 000 0 0000 figure 56. a_vecm_cfg register table 55. a_vecm_cfg bit descriptions field description a_vecm_ele control bit a_vecm_ele defines the event latch enable mode. event latching is disabled for a_vecm_ele = 0. in this case, the vector magnitude interrupt flag is in updated r eal-time and is cleared when t he condition for triggering the interrupt is no longer true. the setting and clearing of the event flag is controlled by the a_vecm_cnt register?s programmed debounce time. for a_vecm_ele = 1, the interrupt flag is latched in and held unti l the host application reads the int_source register (0x0c). a_vecm_initm control bit a_vecm_initm defines how the initial reference values (x_ref, y_ref, and z_ref) are chosen. for a_vecm_initm = 0 the function uses the current x/y/z accelerometer output data at the time when the vector magnitude function is enabled. for a_vecm_initm = 1 the function uses the data from a_vecm_init_x /y/z registers as the initial reference values. a_vecm_updm control bit a_vecm_updm defines how the reference values are updated once the vector magnitude function has been triggered. for a_vecm_updm = 0, the function updates the reference value with the current x, y, and z accelerometer output data values. for a_vecm_updm = 1, the function does not update the reference values when the interrupt is triggered. instead the function continues to use the reference values that were loaded when the function was enabled. if both a_vecm_initm and a_vecm_updm are set to logic ?1?, the host software can manual ly update the reference values in real time by writing to the a_vecm_initx,y,z registers. a_vecm_en the accelerometer vector magnitude function is enabled by setting a_vecm_en = 1, and disabled by clearing this bit (default). the reference values are loaded with either the curr ent x/y/z acceleration values or the values stored in the a_vecm_init_x/y/z registers, depending on the state of the a_vecm_initm bit. note: the vector magnitude function will only perform correctly up to a maximum odr of 400 hz. a_vecm_dbcntm ? ? a_vecm_ths[12:8] 0 0 0 0b00000 figure 57. a_vecm_ths_msb register a_x_out a_x_ref ? () 2 a_y_out a_y_ref ? () 2 a_z_out a_z_ref ? () 2 ++
sensors freescale semiconductor, inc. 53 9.10.3 a_vecm_ths_lsb (0x61) register 9.10.4 a_vecm_cnt (0x62) register the debounce timer period is determined by the odr selected in ctrl_reg1. for example, in accelerometer only mode with an odr of 100 hz and a_vecm_cnt = 15, the debounce time is set at 150 ms. wh en operating in hybrid mode, the effective odr is reduced by a factor of two, making the debounce time 300 ms for this example. table 56. a_vecm_ths_msb bit descriptions field description a_vecm_dbcntm control bit a_vecm_dbcntm defines how the debounce timer is reset when the condition for triggering the interrupt is no longer true. when a_vecm_dbcntm = 0 the debounce counter is decremented by 1 when the vector magnitude result is below the programmed threshold value. when a_vecm_dbcntm = 1 the debounce counter is cleared when the vector magnitude result is below the programmed threshold value. a_vecm_ths[12:8] five msbs of the 13-bit unsigned a_vecm_ths value. the resolution is equal to the selected accelerometer resolution set in xyz_data_cfg[ fs ] a_vecm_ths[7:0] 0b00000000 figure 58. a_vecm_ths_lsb register a_vecm_cnt[7:0] 0b00000000 figure 59. a_vecm_cnt register table 57. a_vecm_cnt bit description field description a_vecm_cnt[7:0] vector magnitude function debounce count value. table 58. a_vecm_cnt relationship with selected odr and power mode odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.25 2.56 20.4 0.318 40.8 10 80 1.25 160 1.56 2.56 81.6 0.318 163.2 10 320 1.25 640
sensors 54 freescale semiconductor, inc. 9.10.5 a_vecm_initx_msb (0x63) register 9.10.6 a_vecm_initx_lsb (0x64) register 9.10.7 a_vecm_inity_msb (0x65) register 9.10.8 a_vecm_inity_lsb (0x66) register ? ? a_vecm_initx[13:8] 0 0 0b000000 figure 60. a_vecm_initx_msb register table 59. a_vecm_initx_msb bit description field description a_vecm_initx[13:8] most significant 6 bits of the signed 14-bit initia l x-axis value to be used as ref_x when a_vecm_cfg[ a_vecm_initm ] = 1. the resolution is determined by the settings made in xyz_data_cfg[ fs ], and is equal to the accelerometer resolution. a_vecm_initx[7:0] 0b00000000 figure 61. a_vecm_initx_lsb register table 60. a_vecm_initx_lsb bit description field description a_vecm_initx[7:0] lsb of the signed 14-bit initial x-axis value to be used as ref_x when a_vecm_cfg[ a_vecm_initm ] = 1. the resolution is determined by the settings made in xyz_data_cfg[ fs ], and is equal to the accelerometer resolution. ? ? a_vecm_inity[13:8] 0 0 0b000000 figure 62. a_vecm_inity_msb register table 61. a_vecm_inity_msb bit description field description a_vecm_inity[13:8] most significant 6 bits of the signed 14-bit initia l y-axis value to be used as ref_y when a_vecm_cfg[ a_vecm_initm ] = 1. the resolution is determined by the settings made in xyz_data_cfg[ fs ], and is equal to the accelerometer resolution. a_vecm_inity[7:0] figure 63. a_vecm_inity_lsb register table 62. a_vecm_inity_lsb bit description field description a_vecm_inity[7:0] lsb of the signed 14-bit initial y-axis value to be used as ref_y when a_vecm_cfg[ a_vecm_initm ] = 1. the resolution is determined by the settings made in xyz_data_cfg[ fs ], and is equal to the accelerometer resolution.
sensors freescale semiconductor, inc. 55 9.10.9 a_vecm_initz_msb (0x67) register 9.10.10 a_vecm_initz_lsb (0x68) register 9.11 transient (ac) a cceleration detection the transient detection function is similar to the freefall/moti on detection function with the e xception that a high-pass filter can be used to eliminate the dc offset from the acceleration data. th ere is an option to disable the high pass filter, which causes th e transient detection function to work in a similar manner to the motion detection function. the transient detection function can be configured to signal an interrupt when the high-pass filtered acceleration delta values for any of the enabled axes exceeds the threshold programmed in transient_ths for the debounce time programmed in transient_count. for more information on how to use and configure the transient detection function please refer to freescale application note an4461. 9.11.1 transient_cfg (0x1d) register ? ? a_vecm_initz[13:8] 0 0 0b000000 figure 64. a_vecm_initz_msb register table 63. a_vecm_initz_msb bit description field description a_vecm_initz[13:8] most significant 6 bits of the signed 14-bit initial z-axis value to be used as ref_z when a_vecm_cfg[ a_vecm_initm ] = 1. the resolution is determined by the settings made in xyz_data_cfg[ fs ], and is equal to the accelerometer resolution. a_vecm_initz[7:0] 0b00000000 figure 65. a_vecm_initz_lsb register table 64. a_vecm_initz_lsb bit description field description a_vecm_initz[7:0] lsb of the signed 14-bit initial z-axis val ue to be used as ref_z when a_vecm_cfg[ a_vecm_initm ] = 1. the resolution is determined by the settings made in xyz_data_cfg[ fs ], and is equal to the accelerometer resolution. ? ? ? tran_ele tran_zefe tran_yefe tran_xefe tran_hpf_byp 0000000 0 figure 66. transie nt_ cfg register
sensors 56 freescale semiconductor, inc. 9.11.2 transient_src (0x1e) register transient event flag source register. this register provides the event status of the enabled axes and polarity (directional) information. table 65. transient_ cfg bit descriptions field description tran_ele transient event flag latch enable. default value: 0 0: event flag latch disabled: the transient interrupt flag reflects the real-time status of the function. 1: event flag latch enabled: the transient interrupt event flag is latched an d a read of the transient_src register is required to clear the event flag. tran_zefe z-axis transient event flag enable. default value: 0 0: z-axis event detection disabled 1: z-axis event detection enabled. raise event flag on z-axis acceleration value greater than threshold. tran_yefe y-axis transient event fl ag enable. default value: 0 0: y-axis event detection disabled 1: y-axis event detection enabled. raise event flag on y-axis acceleration value greater than threshold. tran_xefe x-axis transient event fl ag enable. default value: 0 0: x-axis event detection disabled 1: x-axis event detection enabled. ra ise event flag on x-axis accelera tion value greater than threshold. tran_hpf_byp transient function high-pass filter bypass. default value: 0 0: high-pass filter is applied to accelerometer data input to the transient function. 1: high-pass filter is not applied to accelerometer data input to the transient function. ? tran_ea tran_zef tran_zpol tran_yef tran_ypol tran_xef trans_xpol 00000000 figure 67. transient_ cfg register table 66. transient_src bit descriptions field description tran_ea transient event active flag. default value: 0 0: no transient event active flag has been asserted. 1: one or more transient event active flags has been asserted. tran_zef z-axis transient event acti ve flag. default value: 0 0: z-axis event flag is not active. 1: z-axis event flag is active; z-axis acceleration has exceeded the programmed threshol d for the debounce time specified in trans_count. tran_zpol z-axis event flag polarity. 0: z-axis event was above positive threshold value. 1: z-axis event was below negative threshold value. tran_yef y-axis transient event acti ve flag. default value: 0 0: y-axis event flag is not active. 1: y-axis event flag is active; y-axis acceleration has exceeded the programmed th reshold for the debounce time specified in trans_count. tran_ypol y-axis event flag polarity. 0: y-axis event was above positive threshold value. 1: y-axis event was below negative threshold value. tran_xef x-axis transient event acti ve flag. default value: 0 0: x-axis event flag is not active. 1: x-axis event flag is acti ve; x-axis acceleration has exceeded the programmed threshold for the debounce time specified in trans_count. tran_xpol x-axis event flag polarity. 0: x-axis event was above positive threshold value. 1: x-axis event was below negative threshold value.
sensors freescale semiconductor, inc. 57 when transient_cfg[ tran_ele ] = 1, the transient_src event flag(s) and polarity bits are latched when the interrupt event is triggered, allowing the host application to determine whic h event flag(s) originally triggered the interrupt. when transient_cfg[ tran_ele ] = 0, events which occur after the event that originally triggered the interr upt will update the flag and polarity bits, but once set, the flags can only be cleared by reading the transient_src register. 9.11.3 transient_ths (0x1f) register the transient_ths register determines the debounce counte r behavior and also sets the transient event detection threshold.it is possible to use a_ffmt_ths_x/y/z msb and lsb re gisters to set transient acceleration thresholds for individual axes via a_ffmt_trans_ths_en bit in a_ffmt_ths_y_msb register. please see section 9.9.3 for more details. the tr_ths[6:0] value is a 7-bit unsigned number, with a fix ed resolution of 63 mg/lsb corresponding to a 8g measurement range. the resolution does not change with the full-scale range setting made in xyz_data_cfg[fs]. if ctrl_reg1[ lnoise ] = 1, the measurement range is fixed at 4g, regard less of the settings made in xyz_data_cfg. 9.11.4 transient_count (0x20) register the transient_count register sets the mi nimum number of debounce counts needed to trigger the transient event interrupt flag when the measured acceleration value exceeds the threshold set in transient_ths for any of the enabled axes. the time step for the transient detection debounce counter is set by the value of the system odr and power mode as shown in table 68 . when the device is operated in hybrid m ode, the effective odr is hal f of what is selected in ctrl_reg1, which also doubles the time-step values shown in table 68 . tr_dbcntm tr_ths[6:0] 0 0b0000000 figure 68. transient_ths register table 67. transient_t hs bit descriptions field description tr_dbcntm debounce counter mode selection. 0: decrements debounce counter when the transient event condition is not true during the current odr period. 1: clears debounce counter when the transient event c ondition is not true during the current odr period. tr_ths[6:0] transient event threshold. this register has a resolution of 63mg/lsb regardless of the full-scale range setting made in xyz_data_cfg[ fs ]. if ctrl_reg1[ lnoise ] = 1, the maximum acceleration measurement range is 4g. tr_count[7:0] 0b00000000 figure 69. transient_count register table 68. transient_count bit description field description tr_count[7:0) transient function debounce count value.
sensors 58 freescale semiconductor, inc. an odr of 100 hz and a transient_count value of 15 woul d result in minimum debounce response time of 150 ms. when the device is operated in hybrid mode, these settings would result in an effective debounce time of 300 ms. 9.12 pulse detection 9.12.1 pulse_cfg (0x21) register this register configures the pulse event detection function. table 69. transient_count re lationship wi th the odr odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 40.8 0.638 40.8 20 160 2.5 160 1.56 5.1 163 0.638 163 20 640 2.5 640 pls_dpa pls_ele pls_zdpefe p ls_zspefe pls_ydpef e pls_yspefe pls_xdpefe pls_xspefe 00000000 figure 70. pulse_cfg register table 70. pulse_cfg bit descriptions field description pls_dpa double pulse abort. 0: double pulse detection is not aborted if the start of a pulse is detected during the time period specified by the pulse_ltcy register. 1: setting the pls_dpa bit momentarily suspends the double tap detection if the start of a pulse is detected during the time period specified by the pulse_ltcy register and the pulse ends before the end of the time period specified by the pulse_ltcy register. pls_ele pulse event flag latch enable. when enabled, a read of the pulse_src register is needed to clear the event flag. 0: event flag latch disabled 1: event flag latch enabled pls_zdpefe event flag enable on double pulse event on z-axis. 0: event detection disabled 1: raise event flag on detection of double pulse event on z-axis pls_zspefe event flag enable on single pulse event on z-axis. 0: event detection disabled 1: raise event flag on detection of single pulse event on z-axis pls_ydpefe event flag enable on double pulse event on y-axis. 0: event detection disabled 1: raise event flag on detection of double pulse event on y-axis pls_yspefe event flag enable on single pulse event on y-axis. 0: event detection disabled 1: raise event flag on detection of single pulse event on z-axis. pls_xdpefe event flag enable on double pulse event on x-axis. 0: event detection disabled 1: raise event flag on detection of double pulse event on x-axis.
sensors freescale semiconductor, inc. 59 9.12.2 pulse_src (0x22) register this register indicates the status bit for the pulse detection function. 9.12.3 pulse_thsx (0x23) register the pulse_thsx, pulse_thsy and pulse_thsz registers define the thresholds us ed by the system to start the pulse event detection procedure. threshold values for each axis are un signed 7-bit numbers with a fixed resolution of 0.063g/lsb, pls_xspefe event flag enable on single pulse event on x-axis. 0: event detection disabled 1: raise event flag on detection of single pulse event on x-axis. pls_src_ea pls_src_axz pls_src_axy pls_src_axx p ls_src_dpe pls_src_polz p ls_src_poly pls_src_polx figure 71. pulse_src register table 71. pulse_src bit descriptions field description pls_src_ea event active flag. 0: no interrupt has been generated 1: one or more interrupt events have been generated pls_src_axz z-axis event flag. 0: no interrupt. 1: z-axis event has occurred pls_src_axy y-axis event flag. 0: no interrupt. 1: y-axis event has occurred pls_src_axx x-axis event flag. 0: no interrupt. 1: x-axis event has occurred. pls_src_dpe double pulse on first event. 0: single pulse event triggered interrupt. 1: double pulse event triggered interrupt. pls_src_polz pulse polarity of z-axis event. 0: pulse event that triggered interrupt was positive. 1: pulse event that triggered interrupt was negative. pls_src_poly pulse polarity of y-axis event. 0: pulse event that triggered interrupt was positive. 1: pulse event that triggered interrupt was negative. pls_src_polx pulse polarity of x-axis event. 0: pulse event that triggered interrupt was positive. 1: pulse event that triggered interrupt was negative. ? pls_thsx[6:0] 0 0b0000000 figure 72. puls e_thsx register table 72. pulse_thsx bit description field description pls_thsx[6:0] pulse threshold for x-axis. table 70. pulse_cfg bit descriptions
sensors 60 freescale semiconductor, inc. corresponding to an 8g acceleration full-scale range. the full-sca le range is fixed at 8g for the pulse detection function, reg ardless of the settings made in xyz_data_cfg[ fs ]. 9.12.4 pulse_thsy (0x24) register 9.12.5 pulse_thsz (0x25) register 9.12.6 pulse_tmlt (0x26) register minimum time step for the pulse time limit is defined in tables 75 and 76 . maximum time for a given odr is ?minimum time step x 255?. ? pls_thsy[6:0] 0 0b0000000 figure 73. pulse_thsy register table 73. pulse_thsy bit description field description pls_thsy[6:0] pulse threshold for y-axis. ? pls_thsz[6:0] 0 0b0000000 figure 74. pulse_thsz register table 74. pulse_thsz bit description field description pls_thsz[6:0] pulse threshold for z-axis. pls_tmlt[7:0] 0b00000000 figure 75. pulse_tmlt register table 75. pulse_tmlt bit description field description pls_tmlt[7:0] pls_tmlt[7:0] defines the maximum time interval that can elapse between the start of the acceleration on the selected channel exceeding the specified thre shold and the end when the channel accele ration goes back below the specified threshold. table 76. time step for pulse time limit lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.319 0.319 0.319 0.319 1.25 1.25 1.25 1.25 400 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 200 1.28 1.28 0.638 1.28 5 5 2.5 5 100 2.55 2.55 0.638 2.55 10 10 2.5 10 50 5.1 5.1 0.638 5.1 20 20 2.5 20
sensors freescale semiconductor, inc. 61 therefore an odr setting of 400 hz with normal power mode would result in a maximum pulse time limit of (0.625 ms * 255) 159 ms. 9.12.7 pulse_ltcy (0x27) register minimum time step for the pulse latency is defined in tables 78 and 79. maximum time is ?(time st ep @ odr and power mode) x 255?. 12.5 5.1 20.4 0.638 20.4 20 80 2.5 80 6.25 5.1 40.8 0.638 40.8 20 160 2.5 160 1.56 5.1 163 0.638 163 20 640 2.5 640 table 77. time step for pulse time limit lpf_en = 0 odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.159 0.159 0.159 0.159 0.625 0.625 0.625 0.625 400 0.159 0.159 0.159 0.319 0.625 0.625 0.625 1.25 200 0.319 0.319 0.159 0.638 1.25 1.25 0.625 2.5 100 0.638 0.638 0.159 1.28 2.5 2.5 0.625 5 50 1.28 1.28 0.159 2.55 5 5 0.625 10 12.5 1.28 5.1 0.159 10.2 5 20 0.625 40 6.25 1.28 10.2 0.159 20.4 5 40 0.625 80 1.56 1.28 40.8 0.159 81.6 5 160 0.625 320 pls_ltcy[7:0] 0b00000000 figure 76. pulse_ltcy register table 78. pulse_ltcy bit description field description pls_ltcy[7:0] pls_ltcy [7:0] defines the time interval that starts after the fi rst pulse detection where the pulse detection function ignores the start of a new pulse. table 79. time step for pulse latency @ odr and power mode lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 400 1.276 1.276 1.276 1.276 5 5 5 5 200 2.56 2.56 1.276 2.56 10 10 5 10 100 5.1 5.1 1.276 5.1 20 20 5 20 50 10.2 10.2 1.276 10.2 40 40 5 40 12.5 10.2 40.8 1.276 40.8 40 160 5 160 6.25 10.2 81.6 1.276 81.6 40 320 5 320 1.56 10.2 326 1.276 326 40 1280 5 1280 table 76. time step for pulse time limit lpf_en = 1
sensors 62 freescale semiconductor, inc. 9.12.8 pulse_wind (0x28) register the time step for the pulse window counter varies with the selected odr and power modes as defined in tables 81 and 82 . the maximum time value is equal to (time step @ odr and power mode) x 255. please note that when the device is operated in hybrid mode, the effective odr is half of what is selected in ctrl_reg1, which will double the time step value from what is shown in table 81 and table 82 . table 80. time step for pulse latency @ odr and power mode lpe_en = 0 odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.25 2.56 20.4 0.318 40.8 10 80 1.25 160 1.56 2.56 81.6 0.318 163.2 10 320 1.25 640 pls_wind[7:0] 0b00000000 figure 77. pulse_wind register table 81. pulse_wind bit description field description pls_wind[7:0] pls_wind [7:0] defines the maximum interval of time that can elapse after the end of the latency interval in which the start of the second pulse event must be detected provided the device has been configured for double pulse detection. the detected second pulse width must be shorter than the time limit constraint specified by the pulse_tmlt register, but the end of the double pulse need not finish within the time specified by the pulse_wind register. table 82. time step for pulse detection window @ odr and power mode lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.638 0.638 0.638 0.638 2.5 2.5 2.5 2.5 400 1.276 1.276 1.276 1.276 5 5 5 5 200 2.56 2.56 1.276 2.56 10 10 5 10 100 5.1 5.1 1.276 5.1 20 20 5 20 50 10.2 10.2 1.276 10.2 40 40 5 40 12.5 10.2 40.8 1.276 40.8 40 160 5 160 6.25 10.2 81.6 1.276 81.6 40 320 5 320 1.56 10.2 326 1.276 326 40 1280 5 1280
sensors freescale semiconductor, inc. 63 9.13 accelerometer offset correction the 8-bit 2?s complement offset correction registers are used to realign the zero-g position of the x, y, and z axes after devi ce board mount. the resolution of the offset registers is 2 mg per l sb, with an effective offset adju stment range of -256 mg to +2 54 mg for each axis. for more information on how to calibrate the 0g offset, please refer to freescale application note an4069. 9.13.1 off_x (0x2f) register 9.13.2 off_y (0x30) register 9.13.3 off_z (0x31) register table 83. time step for pulse detection window @ odr and power mode lpf_en = 1 odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 0.318 0.318 0.318 0.318 1.25 1.25 1.25 1.25 400 0.318 0.318 0.318 0.638 1.25 1.25 1.25 2.5 200 0.638 0.638 0.318 1.276 2.5 2.5 1.25 5 100 1.276 1.276 0.318 2.56 5 5 1.25 10 50 2.56 2.56 0.318 5.1 10 10 1.25 20 12.5 2.56 10.2 0.318 20.4 10 40 1.25 80 6.25 2.56 20.4 0.318 40.8 10 80 1.25 160 1.56 2.56 81.6 0.318 163.2 10 320 1.25 640 figure 78. off_x register off_x[7:0] 0b00000000 table 84. off_x bit description field description off_x[7:0] x-axis offset correction value ex pressed as an 8-bit 2's complement number. off_y[7:0] 0b00000000 figure 79. off_y register table 85. off_y bit description field description off_y[7:0] y-axis offset correction value expressed as an 8-bit 2's complement number. off_z[7:0] 0b00000000 figure 80. off_z register
sensors 64 freescale semiconductor, inc. 9.14 magnetometer data registers 9.14.1 m_dr_status (0x32) register magnetic data ready status register. this register indicates the real-time status info rmation of the x, y, and z magnetic sample data. table 86. off_z bit description field description off_z[7:0] z-axis offset correction value ex pressed as an 8-bit 2's complement number. xyzow zow yow xow xyzdr zdr ydr xdr 00000000 figure 81. m_dr_status register table 87. m_dr_status bit descriptions field description zyxow zyxow is set to one whenever new magnetic data is acquired befor e completing the retrieval of the previous data set. this event occurs when the content of at least one magnetometer output data register (i.e. m_out_x/y/z) has been overwritten. zyxow is cleared when the most significant bytes of the magnetometer data (m_out_x_msb, m_out_y_msb, and m_out_z_msb) are read. x, y, z-axis data overwrite: 0: no data overwrite has occurred 1: previous x, y, z magnetic data was overwritten by new x, y, z data before it was completely read zow zow is set to 1 whenever a new z-axis acquisition is completed before the retrieval of the previous data. when this occurs the previous data is overwritten. zow is cleared anytime the m_ou t_z_msb register is read. z-axis data overwrite: 0: no data overwrite has occurred 1: previous z-axis magnetic data was overwr itten by new z-axis data before it was read yow yow is set to 1 whenever a new y-axis acqui sition is completed before the retrieval of the previous data. when this occurs the previous data is overwritten. yow is cleared anytime m_out_y_msb register is read. y-axis data overwrite: 0: no data overwrite has occurred 1: previous y-axis magnetic data was overwrit ten by new y-axis data before it was read xow xow is set to 1 whenever a new x-axis acqui sition is completed before the retrieval of the previous data. when this occurs the previous data is overwritten. xow is cleared anytime the m_ou t_x_msb register is read. x-axis data overwrite: 0: no data overwrite has occurred 1: previous x-axis magnetic data was overwritten by new x-axis data before it was read zyxdr zyxdr signals that a new acquisition for the x, y, and z axes magnetic data is available. zyxdr is cleared when the most significant bytes of the magnetometer data (m_out _x_msb, m_out_y_msb, and m_out_z_msb) are read. x, y, z new data available: 0: no new set of x, y, z magnetic data is available 1: a new set of x, y, z magnetic data is available zdr zdr is set to 1 whenever a new z-axis data acquisition is completed. zdr is cleared anytime the m_out_z_msb register is read. z-axis new data available: 0: no new z-axis magnetic data is available 1: new z-axis magnetic data is available ydr ydr is set to 1 whenever a new y-axis data acquisition is completed. ydr is cleared anytime the m_out_y_msb register is read. y-axis new data available: 0: no new y-axis magnetic data is available 1: new y-axis magnetic data is available
sensors freescale semiconductor, inc. 65 9.14.2 m_out_x_msb (0x33), m_out_x_lsb (0x34), m_out_y_msb (0x35), m_out_y_lsb (0x36), m_out_z_msb (0x37), m_out_z_lsb (0x38) registers x-axis, y-axis, and z-axis 16-bit magnet ic output data expressed as 2's comp lement numbers, with a resolution of 0.1 t/lsb. 9.14.3 cmp_x_msb (0x39), cmp_x_lsb (0x3a), cmp_y_msb (0x3b), cmp_y_lsb (0x3c), cmp_z_msb (0x3d), cmp_z_lsb (0x3e) registers these registers contain the 2?s complement 14-bit decimated a cceleration values, and are time aligned with the magnetometer sample data. the decimation is contro lled by the odr (ctrl_reg1 dr[2:0]) and the magnetometer osr (m_ctrl_reg1 m_os[2:0]) settings.these registers allow the host applicati on to acquire a complete set of time-aligned magnetic and acceleration data with the same oversampling ratio applied to each axis. note that unlike the acceleration data available in th e out_x/y/z registers located at addre sses x1-x6, the data in the cmp_x/ y/z registers is right justified. xdr xdr is set to 1 whenever a new x-axis data acquisition is completed. xdr is cleared anytime the m_out_x_msb register is read. x-axis new data available: 0: no new x-axis magnetic data is available. 1: new x-axis magnetic data is available m_out_x[15:8] figure 82. m_out_x_msb (0x33) register m_out_x[7:0] figure 83. m_out_x_lsb (0x34) register m_out_y[15:8] figure 84. m_out_y_msb (0x35) register m_out_y[7:0] figure 85. m_out_y_lsb (0x36) register m_out_z[15:8] figure 86. m_out_z_msb (0x37) register m_out_z[7:0] figure 87. m_out_z_lsb (0x38) register ? ? cmp_x[13:8] figure 88. cmp_x_msb (0x39) register cmp_x[7:0] figure 89. cmp_x_lsb (0x3a) register table 87. m_dr_status bit descriptions
sensors 66 freescale semiconductor, inc. 9.14.4 max_x_msb (0x45), max_x_lsb (0x46), max_y_msb (0x47), max_y_lsb (0x48), max_z_msb (0x49), max_z_lsb (0x4a) registers the magnetometer max_x/y/z register s are 16-bit 2's complement format with a resolution of 0.1 t/lsb. the registers are read/write and along with the min_x/y/z regi sters are used to calculate the magnetic offset for each axis using the equation (max_x/y/z + min_x/y/z) /2 when m_ctrl_reg2[ maxmin_dis ] = 0 (default). when m_ctrl_reg1[ m_acal ] = 1 (default 0), the mag_off_x/y/z register s are automatically updated with the calculated offset values at the end of every measur ement cycle (odr period). on a por, or after setting m_ctrl_reg2[ maxmin_rst ] = 1, the max_x/y/z registers are loaded with the hex value 0x8000 (negative full scale). the host application may write to the max_x/y/z registers to change the currently used maximum values for each axis, however, when m_ctrl_reg1[ maxmin_dis ] = 0 (default), the system will overwrite thes e values when it updates the max_x/y/z registers at the end of the ne xt measurement cycle (odr period). ? ? cmp_y[13:8] figure 90. cmp_y_msb (0x3b) register cmp_y[7:0] figure 91. cmp_y_lsb (0x3c) register ? ? cmp_z[13:8] figure 92. cmp_z_msb (0x3d) register cmp_z[7:0] figure 93. cmp_z_lsb (0x3e) register max_x[15:8] 0b00000000 figure 94. max_x_msb register max_x[7:0] 0b00000000 figure 95. max_x_lsb register max_y[15:8] 0b00000000 figure 96. max_y_msb register max_y[7:0] 0b00000000 figure 97. max_y_lsb register
sensors freescale semiconductor, inc. 67 9.14.5 min_x_msb (0x4b), min_x_lsb (0x4c), min_y_msb (0x4d), min_y_lsb (0x4e), min_z_msb (0x4f), min_z_lsb (0x50) registers the magnetometer min_x/y/ z registers are 16-bit 2's compleme nt format with a resolution of 0.1 t/lsb. the registers are read/ write and along with the max_x/y/z register s are used to calculate the magnetic offset for each axis using the equation (max_x/ y/z + min_x/y/z) /2 when m_ctrl_reg2[ maxmin_dis ] = 0 (default). when m_ctrl_reg1[ m_acal ] = 1 (default 0), the mag_off_x/y/z register s are automatically updated with the calculated offset values at the end of every measur ement cycle (odr period). on a por, or after setting m_ctrl_reg2[ maxmin_rst ] = 1, the min_x/y/z registers are loaded with the hex value 0x7fff (positive full scale). the host application may write to the mi n_x/y/z registers to change the currently used minimum values fo r each axis, however, when m_ctrl_reg1[ maxmin_dis ] = 0 (default), the system will overwrit e these values when it updates the min_x/y/z registers at th e end of the next measurement cycle (odr period). max_z[15:8] 0b00000000 figure 98. max_z_msb register max_z[7:0] 0b00000000 figure 99. max_z_lsb register min_x[15:8] 0b00000000 figure 100. min_x_msb register min_x[7:0] 0b00000000 figure 101. min_x_lsb register min_y[15:8] 0b00000000 figure 102. min_y_msb register min_y[7:0] 0b00000000 figure 103. min_y_lsb register min_z[15:8] 0b00000000 figure 104. min_z_msb register
sensors 68 freescale semiconductor, inc. 9.15 magnetometer offset correction 9.15.1 m_off_x_msb (0x3f), m_off_x_ls b (0x40),m_off_y_msb (0x41),m_off_y_lsb (0x42), m_off_z_msb (0x43), m_off_z_lsb (0x44) registers the zero-field output for each axis can be adjusted by writing to these registers. the user must set m_ctrl_reg3[ m_raw ] = 0 (default) for the values in these registers to have any effect on the magnetic output data. each offset register is 16-bit, 2's co mplement format with a resolution of 0.1 t/lsb. min_z[7:0] 0b00000000 figure 105. min_z_lsb register m_off_x[15:8] 0b00000000 figure 106. m_off_x_msb register m_off_x[7:0] 0b00000000 figure 107. m_off_x_lsb register m_off_y[15:8] 0b00000000 figure 108. m_off_y_msb register m_off_y[7:0] 0b00000000 figure 109. m_off_y_lsb register m_off_z[15:8] 0b00000000 figure 110. m_off_z_msb register m_off_z[7:0] 0b00000000 figure 111. m_off_z_lsb register
sensors freescale semiconductor, inc. 69 9.16 magnetometer threshold function the magnetometer threshold function works in a similar manner to the freefall/motion detection m odule but uses magnetic data for the event detection instead of acceleration data. the m_ths_oae bit setting determines the logic used to evaluate the threshold detection function for the enabled axes. with m_ths_oae = 0, the magnetic sample data for each enabled axis must be below the threshold values specified in the mag_th s_x/y/z registers for the time period spec ified in mag_ths_count before the event flag is triggered. for m_ths_oae = 1, any of the enabled axes must be above t he threshold values specified in the mag_ths_x/ y/z registers for the time period specified in mag_ths_count before the event flag is triggered. 9.16.1 m_ths_cfg (0x52) register magnetic field threshold detection configuration register. the unsigned 15-bit m_ths_x/y/z registers hold the threshol d used for magnetic event detection. with m_ths_cfg [m_ths_oae] = 0, the ev ent is detected when all of the enabled axes are below or equal to their respective threshold values (an d condition). with m_ths_cfg [m_ths_oae] = 1, the event is detec ted when any of the enabled axes is above or equal to their respective threshold value (or condition). the thresholds for each axis are applied after the magnetic data has been adjusted by the offset values stored in the m_off_x/y/z registers when m_ctrl_reg3[ m_raw ] = 0. m_ths_ele m_ths_oae m_ths_zefe m_ths_yefe m_ths_xefe m_ths_wake_en m_ths_int_en m_ths_int_cfg 00000 0 0 0 figure 112. m_ths_cfg register table 88. m_ths_cfg bit descriptions field description m_ths_ele magnetic threshold event latch enable. 0: event flag latch disabled. magnetic threshold events are not latched, and the event flag will change state with the real- time status of the event detection logic. 1: event flag latch enabled. magnetic threshold events are la tched and the event flag can only be cleared by reading the m_ths_src register. m_ths_oae magnetic threshold event logic selection. 0: logical ?and? of enabled axes x, y, and z below threshold flags is used to detect the event. 1: logical ?or? of enabled axes x, y, and z above threshold flags is used to detect the event. m_ths_zefe event flag enable on z-axis. default value: 0 0: z-axis event detection disabled 1: raise event flag on measured magnetic field value above/below preset threshold for z-axis m_ths_yefe event flag enable on y-axis. default value: 0 0: y-axis event detection disabled 1: raise event flag on measured magnetic field value above/below preset threshold for y-axis m_ths_xefe event flag enable on x-axis. default value: 0 0: x-axis event detection disabled 1: raise event flag on measured magnetic field value above/below preset threshold for x-axis m_ths_wake_en 0: the system excludes the magnetic threshold event flag when evaluati ng the auto-sleep/wake function. 1: the system includes the magnetic threshold event flag when evaluati ng the auto-sleep/wake function. m_ths_int_en 0: magnetic threshold interrupt is disabled. 1: magnetic threshold interrupt is enabled. m_ths_int_cfg 0: magnetic threshold event flag is output on int2 pi n (logically or'd with other int2 interrupt events) 1: magnetic threshold event flag is output on int1 pi n (logically or'd with other int1 interrupt events)
sensors 70 freescale semiconductor, inc. figure 113. illustration of magnetic threshold detection 9.16.2 m_ths_src (0x53) register magnetic threshold interrupt source register. this register keeps track of the magnetic threshold ev ent which is triggering (or has triggered, when m_ths_cfg[ m_ths_ele ] = 1) the event flag. in particular, if m_ths_src[ m_ths_ea ] is set to a logic ?1? then the lo gical combination of magnetic event flags specified in m_ths_cfg is true. m_ths_ea ? m_ths_zhe m_ths_zhp m_ths_yhe m_ths_yhp m_ths_xhe m_ths_xhp 00000000 figure 114. m_ths_src register table 89. m_ths_src bit descriptions field description m_ths_ea event active flag. 0: no event flag has been asserted 1: one or more event flag(s) has been asserted. m_ths_zhe z-high event flag. 0: no event detected 1: z-high event has been detected this bit always reads zero if the m_ths_zefe control bit is set to zero m_ths_zhp z-high event polarity flag. 0: z event detected was positive polarity 1: z event detected was negative polarity this bit always reads zero if the m_ths_zefe control bit is set to zero m_ths_yhe y-high event flag. 0: no event detected 1: y-high event has been detected this bit always reads zero if the m_ths_yefe control bit is set to zero m_ths_yhp y-high event polarity flag. 0: y event detected was positive polarity 1: y event detected was negative polarity this bit always reads zero if the m_ths _yefe control bit is set to zero m_ths_xhe x-high event flag. 0: no event detected 1: x-high event has been detected this bit always reads zero if the m_ths _xefe control bit is set to zero 0 field - full scale + full scale threshold + threshold - x (y , z) high x (y, z) high lar ger field sm aller field x, y, z above threshold (positive) x, y, z below threshold (negative)
sensors freescale semiconductor, inc. 71 9.16.3 m_ths_x_msb (0x54), m_ths_x_lsb (0x55), m_ths_y_msb (0x56), m_ths_y_lsb (0x57), m_ths_z_msb (0x58), m_ths_z_lsb (0x59) registers t he m_ths_x/y/z registers contain the unsi gned 15-bit magnetic thresholds used by the magnetic threshold function. each register has a resolution of 0.1 t/lsb. the thresholds are evaluated after the magnetic data has been adjusted by the offset value stored in the m_off_x/y/z registers when m_ctrl_reg3[ m_raw ] = 0. m_ths_xhp x-high event polarity flag. 0: x event detected was positive polarity 1: x event detected was negative polarity. this bit always reads zero if the m_ths_xefe control bit is set to zero m_ths_dbcntm m_ths_x[14:8] 0 0b0000000 figure 115. m_ths_x_msb register table 90. m_ths_x_msb bit descriptions field description m_ths_dbcntm the m_ths_dbcntm bit configures the way in which the debounce counter is reset when the magnetic event of interest is momentarily not true. when m_ths_dbcntm = 1, the debounce counter is cleared to 0 whenever t he magnetic event of interest is no longer true. when m_ths_dbcntm = 0, the debounce counter is decremented by 1 w henever the magnetic event of interest is no longer true. m_ths_x[14:8] upper 7 bits of the 15-b it unsigned x-axis magnetic threshold. m_ths_x[7:0] 0b00000000 figure 116. m_ths_x_lsb register ? m_ths_y[14:8] 0 0b0000000 figure 117. m_ths_y_msb register m_ths_y[7:0] 0b00000000 figure 118. m_ths_y_lsb register n/a m_ths_z[14:8] 0 0b0000000 figure 119. m_ths_z_msb register table 89. m_ths_src bit descriptions
sensors 72 freescale semiconductor, inc. 9.16.4 m_ths_count (0x5a) register this register sets the number of debounce sample counts required before a magn etic threshold event is triggered.the behavior of the debounce counter is controlled by m_ths_x_msb [ m_ths_dbcntm ]. when the internal debounce counter reaches the m_ths_count va lue a magnetic event flag is set. the debounce counter will never increase beyond the m_ths_count value. the time st ep used for the debounce sample count depends on the chosen odr. when hybrid mode is enabled, the effective odr is reduced by a factor of two, which incr eases the debounce counter time step by a factor of two from what is shown in table 91 . for example, an odr of 100 hz and a m_ths_count value of 15 would result in a debounce response time of 150 ms. in hybrid mode, the same settings would resu lt in a debounce response time of 300 ms. m_ths_z[7:0] 0b00000000 figure 120. m_ths_z_lsb register m_ths_cnt[7:0] 0b00000000 figure 121. m_ths_count register table 91. m_ths_count bit description field description m_ths_cnt[7:0] magnetic threshold debounce count value. table 92. m_ths_count relationship with the odr this table needs to be re-done for this function. ask design during review odr (hz) max time range (s) time step (ms) normal lpln high resolution low power normal lpln high resolution low power 800 n/a n/a n/a n/a n/a n/a n/a n/a 400 n/a n/a n/a 0.638 n/a n/a n/a 2.5 200 1.28 1.28 n/a 1.28 5 5 n/a 5 100 2.55 2.55 n/a 2.55 10 10 n/a 10 50 5.1 5.1 n/a 5.1 20 20 n/a 20 12.5 5.1 20.4 n/a 20.4 20 80 n/a 80 6.25 5.1 40.8 n/a 40.8 20 160 n/a 160 1.56 5.1 163 n/a 163 20 640 n/a 640
sensors freescale semiconductor, inc. 73 figure 122. dbcntm bit function 9.17 magnetometer control registers 9.17.1 m_ctrl_reg1 (0x5b) register m_acal m_rst m_ost m_os[2:0] m_hms[1:0] 0 0 0 0b000 0b00 figure 123. m_ctrl_reg1 register table 93. m_ctrl_reg1 bit descriptions field description m_acal magnetic hard-iron offset auto-calibration enable: 0: auto-calibration feature disabled 1: auto-calibration feature is enabled; the asic uses the maximum and minimum magnetic data to determine the hard iron offset value. the m_off_x/y/z registers are automatically loaded with (max_x/y/z + min_x/y/z)/2 for each axis at the end of every odr cycle. m_rst one-shot magnetic reset de-gauss control bit: 0: no magnetic sensor reset is active 1: one-shot magnetic reset is enabled, hardware cleared when complete. magnetic event count threshold ea ff counter magnetic event count threshold (a) debounce counter magnetic event count threshold ea mag_ths_x_msb[ m_ths_dbcntm ] = 1 (b) ea mag_ths_x_msb[ m_ths_dbcntm ] = 0 (c) debounce counter
sensors 74 freescale semiconductor, inc. the m_os [2:0] osr setting along with the system odr value set in ctrl_reg1 sets the magnetic output data update rate. w hen m_hms [1:0] = 2'b11, magnetic output data is available in registers m_out_x_msb (0x33), m_out_x_lsb (0x34), m_out_y_msb (0x35), m_out_y_lsb (0x36), m_out_z_msb (0x37), and m_out_z_lsb (0x38) along with the time synchronized accelerome ter data in cmp_x_msb (0x39), cmp_x_lsb (0 x3a), cmp_y_msb (0x3b), cmp_y_lsb (0x3c), cmp_z_msb (0x3d), and cmp_z_lsb (0x3e). 9.17.2 m_ctrl_reg2 (0x5c) register m_ost one-shot magnetic measurement mode: 0: no action taken, or one-shot measurement complete. 1: if device is in active mode no action is taken. if device is in standby mode, take one set of magnetic measurements, clear this bit, and return to standby mode. m_os[2:0] oversample ratio (osr ) for magnetometer data (see table 95 ). m_hms[1:0] 00 = only accelerometer sensor is active 01 = only magnetometer sensor is active 11 = hybrid mode, both acceleromete r and magnetometer sensors are active (1) 1. when operating in hybrid mode, the effective odr for eac h sensor is half of the frequency selected in the ctrl_reg1[ dr ] and ctrl_reg1[ aslp_rate ] bit fields. ? ? hyb_autoinc_mode m_maxmin_dis m_maxmi n_dis_ths m_maxmin_rst m_rst_cnt[1:0] 0 0 0 0 0 0 0b00 figure 124. m_ctrl_reg2 register table 94. m_ctrl_reg2 bit descriptions field description hyb_autoinc_mode with hyb_autoinc_mode = 1 and fast-read mode is disabled (ctrl_reg1 [ f_read ] = 0), the register address will automatically advance to register x 33 (m_out_x_msb) after reading register x06 (out_z_lsb) in burst-read mode. for hyb_autoinc_mode = 1 and fast read mode enabled (ctrl_reg1[ f_read = 1) the register address will automatically advance to register x33 (m_out_x_msb) after reading register x05 (out_z_msb) during a burst- read mode. please refer to the register map auto-increment address column for further information. m_maxmin_dis magnetic measurement max/min detection function disable: 0: magnetic min/max detection function is enabled (default). 1: magnetic min/max detec tion function is disabled. when enabled, the magnetic min/max detection fu nction will update the max_x/y/z and min_x/y/z registers at the end of each odr cycle with the maxi mum and minimum magnetic measurements from each axis. this is used along with the auto-cal feature (m_ctrl_reg1[ m_acal ] = 1) as a hardware based hard-iron offset compensation function. m_maxmin_dis_ths magnetic measurement min/max detection function disable via magnetic th reshold event trigger: 0: no impact to magnetic min/max detec tion function on a magnetic threshold event 1: magnetic min/max detection function is disabl ed when magnetic threshold event is triggered m_maxmin_rst magnetic measurement min/max detection function reset: 0: no reset sequence is active 1: setting this bit resets the min_x/y/z and max_x/y/z registers to 0x7fff and 0x8000, respectively (positive and negative full-scale values).this bit is automatically cleared after the reset is completed. m_rst_cnt[1:0] magnetic auto-reset de-gauss frequency: 00: automatic magnetic reset at the beginning of each odr cycle (default). 01: automatic magnetic reset every 16 odr cycles. 10: automatic magnetic reset every 512 odr cycles. 11: automatic magnetic reset is disabled. magnetic reset only occurs automatically on a transition from standby to active mode, or can be triggered manually by setting m_ctrl_reg1 [ m_rst ] = 1 table 93. m_ctrl_reg1 bit descriptions
sensors freescale semiconductor, inc. 75 9.17.3 m_ctrl_reg3 (0x5d) register 9.17.4 m_int_src (0x5e) register m_raw m_aslp_os[2:0] m_ths_xyz_update m_st_z m_st_xy[1:0] 0 0b000 0 0 0b00 figure 125. m_ctrl_reg3 register table 95. m_ctrl_reg3 bit descriptions field description m_raw magnetic measurement raw mode enable: 0: values stored in the m_off_x/y/z registers are applied to the magnetic sample data. this bit must be cleared in order for the automatic hard-iron com pensation function to have any effect. 1: values stored in m_off_x/y/z are not applied to the magnetic sample data; automatic hard-iron compensation function does not have any effect on the output data. m_aslp_os[2:0] defines magnetometer osr in auto-sleep mode. see table 95 . m_ths_xyz_update this control bit defines which refe rence values are updated when the magnet ic threshold event detection function triggers. 0: x, y and z reference values are all updated when the function triggers on any of the x, y, or z axes. 1 : only the reference value for the axis th at triggered the detection event is updated. m_st_z enables z-axis magnetic se lf-test function when set to 1. m_st_xy[1:0] enables both x and y axes magnetic se lf-test function simultaneously when set to a value greater than 2?b00. x and y magnetic self-test is disabl ed when this field is set to 2'b00 . table 96. m-cell osr versus odr odr (hz) osr = 0 osr = 1 osr = 2 osr = 3 osr = 4 osr = 5 osr = 6 osr = 7 1.56 16 16 32 64 128 256 512 1024 6.25 4 4 8 16 32 64 128 256 12.5 2 2 4 8 16 32 64 128 5 02222481 63 2 1 0 022222481 6 2 0 022222248 4 0 022222224 8 0 022222222 ?????s r c _ m _ t h ss r c _ m _ v e c ms r c _ m _ d r d y 00000000 figure 126. m_int_src register table 97. m_int_src bit description field description src_m_ths magnetic threshold interrupt flag: 0: magnetic threshold event has not been detected. 1: magnetic threshold event has been detected. src_m_vecm magnetic vector magnitude interrupt flag: 0: magnetic vector magnitude change event has not been detected. 1: magnetic vector magnitude change event has been detected.
sensors 76 freescale semiconductor, inc. 9.17.5 magnetometer vector magnitude function the magnetometer vector magnitude fu nction will generate an interrupt when > m_vecm_ths value and t > m_vecm_cnt value. where m_x_out, m_y_out, and m_z_out are the current decimated magnetometer output values, and m_x_ref, m_y_ref, and m_z_ref are the internally latched reference values. t he user may program the m_vecm_ths and m_vecm_cnt registers to establish the conditions needed to dete ct a magnetic vector magnitu de change event. depending on the values chosen for the reference values, this function may be configured to detect a ma gnetic field magnitude that is above a preset threshold (with reference values = 0), or a change in magnitude between two magnet ic vectors greater than the pr eset threshold (with reference values non-zero). please note x_ref, y_ref, z_ref are stored internally and are not observable by the user through the register interface. please refer to freescale application note an4458. 9.17.6 m_vecm_cfg (0x69) register src_m_drdy magnetic data-ready interrupt flag: 0: no new magnetic data is available. 1: new magnetic data is available. ? m_vecm_ele m_vecm_initm m_vecm_updm m_vecm_en m_vecm_wake_en m_vecm_init_en m_vecm_init_cfg 00 0 0 0 0 0 0 figure 127. m_vecm_cfg register table 98. m_vecm_cfg bit descriptions field description m_vecm_ele magnetic vector magnitude event latch enable: 0: event latch disabled 1: event latch enabled with event latching enabled, the src_m_vecm interrupt flag may only be cleared by reading the m_int_src register. with event latching disabled, the src_m_vecm interrupt flag is updated in real time and may be cleared by the asic prior to the user reading the flag. m_vecm_initm magnetic vector magnitude initialization mode: 0: the asic uses the current magnetic output data as the initial reference values at the time the m_vecm_en bit is set. 1: the asic uses the data stored in the m_vecm_x/y/z_init registers as the initial reference values at the time the m_vecm_en bit is set. m_vecm_updm magnetic vector magnitude reference value update mode: 0: the function updates the reference values with the current x/y/z magnetic data when the event is triggered. 1: the function does not update the refer ence values when the event is triggered. setting m_vecm_initm = 1 and m_vecm_updm = 1 allows the user to manually update the reference values using the m_vecm_init_x/y/z registers in real time when the function is enabled. m_vecm_en magnetic vector magnitude function enable: 0: function is disabled. 1: function is enabled, the asic will update the internal m_x/y/z_ref registers with either the current magnetic output data or the values stored in the m_vecm_init_x/y/z registers depending on the state of m_vecm_initm . note: the magnetic vector magnitude function will only function correctly up to a maximum odr of 400 hz. m_vecm_wake_en magnetic vector magnitude wake enable: 0: the system excludes the src_m_vecm event flag when evaluating the auto-sleep function. 1: the system includes the src_m_vecm event flag when evaluating the auto-sleep function. m_vecm_int_en magnetic vector magnitude interrupt enable: 0: magnetic vector magnitude interrupt is disabled. 1: magnetic vector magnitude interrupt is enabled. m_vecm_init_cfg magnetic vector magnitude interrupt configuration: 0: magnetic vector magnitude interrupt is output on int2 pin. 1: magnetic vector magnitude interrupt is output on int1 pin. table 97. m_int_src bit description m_x_out m_x_ref ? () 2 m_y_out m_y_ref ? () 2 m_z_out m_z_ref ? () 2 ++
sensors freescale semiconductor, inc. 77 9.17.7 m_vecm_ths_msb (0x6a) register 9.17.8 m_vecm_ths_lsb (0x6b) register 9.17.9 m_vecm_cnt (0x6c) register 9.17.10 m_vecm_initx_msb (0x6d) register m_vecm_dbcntm m_vecm_ths[14:8] 0 0b0000000 figure 128. m_vecm_ths_msb register table 99. m_vecm_ths_msb bit descriptions field description m_vecm_dbcntm magnetic vector magnitude debounce counter mode selection: 0: the debounce counter is decremented by 1 whenever the current vector magnitude result is below the threshold set in m_vecm_ths. 1: the debounce counter is cleared whenever the current vector magnitude result is below the threshold set in m_vecm_ths. m_vecm_ths[14:8] seven most significant bits of 15-bit unsi gned magnetic vector magnitude threshold. resolution is 0.1 t/lsb. m_vecm_ths[7:0] 0b00000000 figure 129. m_vecm_ths_lsb register m_vecm_cnt[7:0] 0b00000000 figure 130. m_vecm_cnt register table 100. m_vecm_cnt bit description field description m_vecm_cnt[7:0] magnetic vector magnitude debounce count value. the debounce timer count period is set by the current odr. for example, with m_vecm_cnt = 15 and an odr of 100 hz selected, the debounce is set to 150 ms. when operating in hybrid mode, the effective odr is reduced by a factor of two, making the debounce time for this example 300 ms. m_vecm_initx[15:8] 0b00000000 figure 131. m_vecm_initx_msb register table 101. m_vecm_initx_msb bit description field description m_vecm_initx[15:8] msb of signed 16-bit initial x-axis value used by the magnetic vector magnitude function when m_vecm_cfg[ m_vecm_initm ] = 1.
sensors 78 freescale semiconductor, inc. 9.17.11 m_vecm_initx_lsb (0x6e) register 9.17.12 m_vecm_inity_msb (0x6f) register 9.17.13 m_vecm_inity_lsb (0x70) register 9.17.14 m_vecm_initz_msb (0x71) register m_vecm_initx[7:0] 0b00000000 figure 132. m_vecm_initx_lsb register table 102. m_vecm_initx_lsb bit description field description m_vecm_initx[7:0] lsb of signed 16-bit initial x-axis value used by the magnetic vector magnitude function when m_vecm_cfg[ m_vecm_initm ] = 1. m_vecm_inity[15:8] 0b00000000 figure 133. m_vecm_inity_msb register table 103. m_vecm_inity_msb bit description field description m_vecm_inity[15:8] msb of signed 16-bit initial y-axis value used by the magnetic vector magnitude function when m_vecm_cfg[ m_vecm_initm ] = 1. m_vecm_inity[7:0] 0b00000000 figure 134. m_vecm_inity_lsb register table 104. m_vecm_inity_lsb bit description field description m_vecm_inity[7:0] lsb of signed 16-bit initial y-axis value used by the magnetic vector magnitude function when m_vecm_cfg[ m_vecm_initm ] = 1. m_vecm_initz[15:8] 0b00000000 figure 135. m_vecm_initz_msb register table 105. m_vecm_initz_msb bit description field description m_vecm_initz[15:8] msb of signed 16-bit initial z-axis value used by the magnetic vector magnitude function when m_vecm_cfg[ m_vecm_initm ] = 1.
sensors freescale semiconductor, inc. 79 9.17.15 m_vecm_initz_lsb (0x72) register m_vecm_initz[7:0] 0b00000000 figure 136. m_vecm_initz_lsb register table 106. m_vecm_initz_lsb bit description field description m_vecm_initz[7:0] lsb of signed 16-bit initial z-axis value used by the magnetic vector magnitude function when m_vecm_cfg[ m_vecm_initm ] = 1.
sensors 80 freescale semiconductor, inc. 10 mounting guidelines for the qu ad flat no lead (qfn) package printed circuit board (pcb) layout is a cr itical portion of the total design. the footprint for the surface mount packages must be the correct size to ensure proper solder connection interface be tween the pcb and the package. with the correct footprint, the packages will self-align when subjected to a solder reflow process. these guidelines are for soldering and mount ing the quad flat no-lead (qfn) package inertial sensors to pcbs. the purpose is to minimize the stress on the package after board mounting. the FXOS8700CQ uses the qfn package platform. this section describes suggested methods of soldering these devices to the pcb for consumer applications. 10.1 overview of sold ering considerations information provided here is based on experiments executed on qfn devices. they do not repres ent exact conditions present at a customer site. hence, information herein should be used for guidance only and process and design optimizations are recommended to develop an application specific solution. it shoul d be noted that with the proper pcb footprint and solder stenc il designs, the package will self-align during the solder reflow process. 10.2 halogen content this package is designed to be halogen free, exceeding most industry and customer standar ds. halogen free means that no homogeneous material within the assembly package shall contain ch lorine (cl) in excess of 700 ppm or 0.07% weight/weight or bromine (br) in excess of 900 ppm or 0.09% weight/weight. 10.3 pcb mounting recommendations 1. the pcb land should be designed with non-solder mask defined (nsmd) as shown in figure 138 and figure 139 2. no additional via pattern underneath package. 3. pcb land pad is 0.8 mm by 0.3 mm as shown in figure 138 and figure 139 . 4. solder mask opening = pcb land pad edge + 0.113 mm larger all around. 5. stencil opening = pcb land pad -0.015 mm smaller all around = 0.77 mm by 0.27 mm. 6. stencil thickness is 100 or 125 m. 7. do not place any components or vias at a distance le ss than 2 mm from the package land area. this may cause additional package stress if it is too close to the package land area. 8. signal traces connected to pads are as symmetric as possi ble. put dummy traces on nc pads in order to have same length of exposed trace for all pads. 9. use a standard pick and place process and equipment. do not use a hand soldering process. 10. do not use a screw down or stacking to fix the pcb into an enclosure because this could bend the pcb, putting stress on the package. 11. the pcb should be rated for the multiple lead- free reflow condition with max 260c temperature. 12. no copper traces on top layer of pcb under the package. this will cause planarity issues with board mount. freescale qfn sensors are compliant with restrictions on haza rdous substances (rohs), having halide-free molding compound (green) and lead-free terminations. these terminations are compatible with tin-lead (sn-pb) as well as tin- silver-copper (sn-ag-cu) solder paste so ldering processes. reflow profiles applic able to those processes can be used successfully for soldering the devices.
sensors freescale semiconductor, inc. 81 figure 137. recommended pcb land pattern, solder mask, and stencil opening near package footprint figure 138. detailed dimensions package footprint 0.467mm x 0.25mm package footprint pcblandpattern&stencil stencil opening = pcb land pad -0.015mm smaller all around = 0.77mm x 0.27mm solder mask opening = pcb land pad edge + 0.113mm larger all around pcb land pad = 0.8mm x 0.3mm 0.567 mm x 0.25 mm no copper in this area
sensors 82 freescale semiconductor, inc. 11 package case 2188-01 issue o 16 lead qfn
sensors freescale semiconductor, inc. 83 case 2188-01 issue o 16 lead qfn
sensors 84 freescale semiconductor, inc. case 2188-01 issue o 16 lead qfn
sensors freescale semiconductor, inc. 85 table 107. revision history revision number revision date description of changes 0.1 05/2012 ? corrected figure 1 and updated figure 4 to include acceleration values. 0.2 05/2012 ? added autonomous sub-bullets to first page. ? table 2: changed cross-axis max value to 0.5 and die-to-package alignment error max value to 2. ? table 13: who_am_i register, default hex value numbers changed from 0xc4/0xc7 to 0xc7 removed note 4 and 5. ? section 9.1.7, who_am_i register changed register numbers in figure 16 from 0xc4/0xc7 to 0xc7 0.3 05/2012 ? table 2: changed nonlinearity values to tb d. added test conditions for noise rows. ? table 3: added min values for self-test output change for x-axis and y-axis rows. ? table 5: updated odr values for low-power accelerati on mode, normal-acceleration mode, hybrid mode and magnetic mode. added max value for iddstby, standby m ode; added typ values for vih and vil, all previously tbd. added typ value for 25 scl, sda pin leakage. ? added section 7.5, hybrid mode. ? table 13:. deleted registers 0x79, 0x7a, 0x7b and 0x7c, ? table 50: updated a_ffmt_ths_xyz_en description. ? table 51: updated a_ffmt_trans_ths_en description. ? updated descriptive paragraph for section 9.11.3. ? updated descriptive paragraph for section 9.11.4. 1 06/2012 ? changed title of document. ? table 3: updated note 2. tco spec updated, hyster esis value updated, updated noise values for odr = 6.25 hz, os = 256 and odr = 1.56 hz, os = 1024. updat ed vst x-axis typ value from -1500 to -1320 and z- axis from tbd to 100. ? table 4: removed first 2 rows, x, y, z i nertial alignment parameters and typ values. ? table 8: added scl, sda pin leakage typ val ue 4 na, added scl, sda pin capacitance 3 pf. ? replace table 8 with updated parameters. ? updated section 5.2 spi interface characteristics. ? table 94: updated m_st_xy[1:0] bit description.
FXOS8700CQ rev. 1 06/2012 information in this document is provided solely to enable system and software implementers to use freescale products. th ere are no express or implied copyright licenses granted hereunder to design or fabr icate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the applic ation or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals,? must be validated for each customer application by customer?s technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.reg.net/ v2/webservices/freescale/docs/termsandconditions.htm . freescale and the freescale logo are tradem arks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. xtrinsic is a trademark of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? 2012 freescale semiconductor, inc. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support rohs-compliant and/or pb-free versions of freescale products have the functi onality and electrical characteristics of their non-rohs-compliant and/or non-pb-free counterparts. for further information, see http:/www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp .

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