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? 1997 data sheet mos integr a ted circuit m pd42s65165, 4265165 description the m pd42s65165, 4265165 are 4,194,304 words by 16 bits cmos dynamic rams with optional edo. edo is a kind of the page mode and is useful for the read operation. besides, the m pd42s65165 can execute cas before ras self refresh. these are packaged in 50-pin plastic tsop (ii). features ? edo (hyper page mode) ? 4,194,304 words by 16 bits organization ? single +3.3 v 0.3 v power supply ? fast access and cycle time part number power consumption access time r/w cycle time edo (hyper page mode) active (max.) (max.) (min.) cycle time (min.) m pd42s65165-a50, 4265165-a50 540 mw 50 ns 84 ns 20 ns m pd42s65165-a60, 4265165-a60 468 mw 60 ns 104 ns 25 ns ? the m pd42s65165 can execute cas before ras self refresh. part number refresh cycle refresh power consumption at standby (max.) m pd42s65165 4,096 cycles/128 ms ras only refresh, normal read/write, 0.72 mw cas before ras self refresh, (cmos level input) cas before ras refresh, hidden refresh m PD4265165 4,096 cycles/64 ms ras only refresh, normal read/write, 1.8 mw cas before ras refresh, hidden refresh (cmos level input) the information in this document is subject to change without notice. 64 m-bi t dynami c ram 4 m- w or d b y 16-bi t , ed o , byte read/write mode document no. m12282ej1v 1 ds00 (1st edition) date published february 1997 n printed in japan
m pd42s65165, 4265165 2 ordering information part number access time package refresh (max.) m pd42s65165g5-a50-7j f 50 ns 50-pin plastic tsop ( i i) cas before ras self refresh (400 mil) cas before ras refresh m pd42s65165g5-a60-7j f 60 ns ras only refresh hidden refresh m PD4265165g5-a50-7j f 50 ns 50-pin plastic tsop ( i i) cas before ras refresh (400 mil) ras only refresh m PD4265165g5-a60-7j f 60 ns hidden refresh
m pd42s65165, 4265165 3 pin configuration (marking side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 gnd i/o16 i/o15 i/o14 i/o13 gnd i/o12 i/o11 i/o10 i/o9 nc gnd lcas ucas oe nc nc nc a11 a10 a9 a8 a7 a6 gnd v cc i/o1 i/o2 i/o3 i/o4 v cc i/o5 i/o6 i/o7 i/o8 nc v cc we ras nc nc nc nc a0 a1 a2 a3 a4 a5 v cc 50-pin plastic tsop (ii) (400 mil) m m pd42s65165g5-7jf PD4265165g5-7jf a0 to a11 : address inputs i/o1 to i/o16 : data inputs/outputs ras : row address strobe ucas : upper byte column address strobe lcas : lower byte column address strobe we : write enable oe : output enable v cc : power supply gnd : ground nc : no connection
m pd42s65165, 4265165 4 block diagram notes 1. part number row address column address m pd42s65165, 4265165 a0 - a11 a0 - a9 2. 4,096 1,024 16 clock generator ras lcas ucas we v cc gnd cas before ras counter row address buffer column address buffer address row decoder memory cell array sense amplifier column decoder lower byte control upper byte control data output buffer data input buffer data output buffer data input buffer 16 oe i/o1 to i/o8 (lower byte) i/o9 to i/o16 (upper byte) bit organization note 2 note 1
m pd42s65165, 4265165 5 input/output pin functions the m pd42s65165, 4265165 have input pins ras, ucas, lcas, we, oe, a0 to a11 and input/output pins i/o1 to i/o16. pin name ras (row address strobe) ucas, lcas (upper, lower column address strobe) a0 to a11 (address inputs) we (write enable) oe (output enable) i/o1 to i/o16 (data inputs/outputs) input/output function input ras activates the sense amplifier by latching a row address and selecting a corresponding word line. it refreshes memory cell array of one line selected by the row address. it also selects the following function. ? cas before ras self refresh, cas before ras refresh input ucas, lcas activates data input/output circuit by latching column address and selecting a digit line connected with the sense amplifier. input address bus. input total 22-bit of address signal, upper 12-bit and lower 10-bit in sequence (address multiplex method). therefore, one word is selected from 4,194,304-word by 16-bit memory cell array. in actual operation, latch row address by specifying row address and activating ras. then, switch the address bus to column address and activate cas. each address is taken into the device when ras and cas are activated. therefore, the address input setup time (t asr , t asc ) and hold time (t rah , t cah ) are specified for the activation of ras and cas. input write control signal. write operation is executed by activating ras, cas and we. input read control signal. read operation can be executed by activating ras, cas and oe. if we is activated during read operation, oe is to be ineffective in the device. therefore, read operation cannot be executed. input/output 16-bit data bus. i/o1 to i/o16 are used to input/output data.
m pd42s65165, 4265165 6 hyper page mode (edo) the hyper page mode (edo) is a kind of page mode with enhanced features. the two major features of the hyper page mode (edo) are as follows. 1. data output time is extended. in the hyper page mode (edo), the output data is held to the next cas cycles falling edge, instead of the rising edge. for this reason, valid data output time in the hyper page mode (edo) is extended compared with the fast page mode (= data extend function). in the fast page mode, the data output time becomes shorter as the cas cycle time becomes shorter. therefore, in the hyper page mode (edo), the timing margin in read cycle is larger than that of the fast page mode even if the cas cycle time becomes shorter. 2. the cas cycle time in the hyper page mode (edo) is shorter than that in the fast page mode. in the hyper page mode (edo), due to the data extend function, the cas cycle time can be shorter than in the fast page mode if the timing margin is the same. taking a device whose t rac is 60 ns as an example, the cas cycle time in the fast page mode is 25 ns while that in the fast page mode is 40 ns. in the hyper page mode (edo), read (data out) and write (data in) cycles can be executed repeatedly during one ras cycle. the hyper page mode (edo) allows both read and write operations during one cycle. the following shows a part of the hyper page mode (edo) read cycle. specifications to be observed are described in the next page. hyper page mode (edo) read cycle t hpc t oea t oez t aa hi - z hi - z row col.a col.b col.c t oea t olz ras v ih ? v il ? cas v ih ? v il ? address v ih ? v il ? v ih ? v il ? oe v ih ? v il ? i/o v oh ? v ol ? data out a data out b data out c data out c t oez t aa t cac t oez t oep t oep t och t cho t cho we t rac t aa t cac t clz t cac t clz t wpz t dhc t ofc t ofr t wez t och t rrh t rch
m pd42s65165, 4265165 7 cautions when using the hyper page mode (edo) 1. cas access should be used to operate t hpc at the min. value. 2. to make i/os to hi-z in read cycle, it is necessary to control ras, cas, we, oe as follows. the effective specification depends on the state of each signal. (1) both ras and cas are inactive (at the end of read cycle) we: inactive, oe: active t ofc is effective when ras is inactivated before cas is inactivated. t ofr is effective when cas is inactivated before ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both ras and cas are active or either ras or cas is active (in read cycle) we, oe: inactive t oez is effective. both ras and cas are inactive or ras is active and cas is inactive (at the end of read cycle) we, oe: active and either t rrh or t rch must be met t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective. 3. in read cycle, the effective specification depends on the state of cas signal when controlling data output with the oe signal. (1) cas: inactive, oe: active t cho is effective. (2) cas, oe: active t och is effective.
m pd42s65165, 4265165 8 electrical specifications ? cas means ucas and lcas. ? all voltages are referenced to gnd. ? after power up (v cc 3 v cc(min.) ), wait more than 100 m s (ras, cas inactive) and then, execute eight cas before ras or ras only refresh cycles as dummy cycles to initialize internal circuit. absolute maximum ratings parameter symbol condition rating unit voltage on any pin relative to gnd v t C0.5 to +4.6 v supply voltage v cc C0.5 to +4.6 v output current i o 50 ma power dissipation p d 1w operating ambient temperature t a 0 to +70 ?c storage temperature t stg C55 to +125 ?c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 +0.8 v operating ambient temperature t a 070?c capacitance (t a = 25 ?c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 address 5 pf c i2 ras, cas, we, oe 7 data input/output capacitance c i/o i/o 7 pf
m pd42s65165, 4265165 9 dc characteristics (recommended operating conditions unless otherwise noted) [ m pd42s65165, 4265165] parameter symbol test condition min. max. unit notes operating current i cc1 ras, cas cycling t rac = 50 ns 150 ma 1, 2, 3 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 130 standby m pd42s65165 i cc2 ras, cas 3 v ih (min.) , i o = 0 ma 1.0 ma current ras, cas 3 v cc C 0.2 v, i o = 0 ma 0.2 m PD4265165 ras, cas 3 v ih (min.) , i o = 0 ma 1.0 ras, cas 3 v cc C 0.2 v, i o = 0 ma 0.5 ras only refresh current i cc3 ras cycling, cas 3 v ih (min.) t rac = 50 ns 150 ma 1, 2, 3 ,4 t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 130 operating current i cc4 ras v il (max.) , cas cycling t rac = 50 ns 120 ma 1, 2, 5 (hyper page mode (edo)) t hpc = t hpc (min.) , i o = 0 ma t rac = 60 ns 100 cas before ras i cc5 ras cycling t rac = 50 ns 150 ma 1, 2 refresh current t rc = t rc (min.) , i o = 0 ma t rac = 60 ns 130 cas before ras i cc6 cas before ras refresh: t ras 300 ns 500 m a 1, 2 long refresh current t rc = 31.3 m s (4,096 cycles/128 ms, ras, cas: only for the m pd42s65165) v cc C 0.2 v v ih v ih (max.) 0 v v il 0.2 v standby: t ras 1 m s 600 m a 1, 2 ras, cas 3 v cc C 0.2 v address: v ih or v il we, oe: v ih i o = 0 ma cas before ras i cc7 ras, cas: 400 m a2 self refresh current t rass = 5 ms (only for the m pd42s65165) v cc C 0.2 v v ih v ih (max.) 0 v v il 0.2 v i o = 0 ma input leakage current i i (l) v i = 0 to 3.6 v C5 +5 m a all other pins not under test = 0 v output leakage current i o (l) v o = 0 to 3.6 v C5 +5 m a output is disabled (hi-z) high level output voltage v oh i o = C2.0 ma 2.4 v low level output voltage v ol i o = +2.0 ma 0.4 v notes 1. i cc1 , i cc3 , i cc4 , i cc5 and i cc6 depend on cycle rates (t rc and t hpc ). 2. specified values are obtained with outputs unloaded. 3. i cc1 and i cc3 are measured assuming that address can be changed once or less during ras v il (max.) and cas 3 v ih (min.) . 4. i cc3 is measured assuming that all column address inputs are held at either high or low. 5. i cc4 is measured assuming that all column address inputs are switched only once during each hyper page (edo) cycle.
m pd42s65165, 4265165 10 ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions (1) input timing specification (2) output timing specification v ih (min.) = 2.0 v v il (max.) = 0.8 v v oh (min.) = 2.0 v v ol (max.) = 0.8 v t t = 2 ns t t = 2 ns (3) output load condition 100 pf c l i/o 1,180 w 870 w v cc common to read, write, read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t rc 84 C 104 C ns ras precharge time t rp 30 C 40 C ns cas precharge time t cpn 7C10Cns ras pulse width t ras 50 10,000 60 10,000 ns 1 cas pulse width t cas 8 10,000 10 10,000 ns ras hold time t rsh 13 C 15 C ns cas hold time t csh 38 C 40 C ns ras to cas delay time t rcd 11 37 14 45 ns 2 ras to column address delay time t rad 9 251230ns2 cas to ras precharge time t crp 5C5Cns3 row address setup time t asr 0C0Cns row address hold time t rah 7C10Cns column address setup time t asc 0C0Cns column address hold time t cah 7C10Cns oe lead time referenced to ras t oes 0C0Cns cas to data setup time t clz 0C0Cns oe to data setup time t olz 0C0Cns oe to data delay time t oed 10 C 13 C ns masked byte write hold time referenced to ras t mrh 0C0Cns transition time (rise and fall) t t 1 50 1 50 ns refresh time m pd42s65165 t ref C 128 C 128 ms 4 m PD4265165 C 64 C 64 ms
m pd42s65165, 4265165 11 notes 1. in cas before ras refresh cycles, t ras (max.) is 100 m s. if 10 m s < t ras < 100 m s, ras precharge time for cas before ras self refresh (t rps ) is applied. 2. for read cycles, access time is defined as follows: input conditions access time access time from ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 3. t crp (min.) requirement is applied to ras, cas cycles. 4. this specification is applied only to the m pd42s65165. read cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. access time from ras t rac C 50 C 60 ns 1 access time from cas t cac C 15 C 15 ns 1 access time from column address t aa C 25 C 30 ns 1 access time from oe t oea C 13 C 15 ns column address lead time referenced to ras t ral 25 C 30 C ns read command setup time t rcs 0C0Cns read command hold time referenced to ras t rrh 0C0Cns2 read command hold time referenced to cas t rch 0C0Cns2 output buffer turn-off delay time from oe t oez 0 10 0 13 ns 3 cas hold time to oe t cho 5C5Cns4 notes 1. for read cycles, access time is defined as follows: input conditions access time access time from ras t rad t rad (max.) and t rcd t rcd (max.) t rac (max.) t rac (max.) t rad > t rad (max.) and t rcd t rcd (max.) t aa (max.) t rad + t aa (max.) t rcd > t rcd (max.) t cac (max.) t rcd + t cac (max.) t rad (max.) and t rcd (max.) are specified as reference points only; they are not restrictive operating parameters. they are used to determine which access time (t rac , t aa or t cac ) is to be used for finding out when output data will be available. therefore, the input conditions t rad 3 t rad (max.) and t rcd 3 t rcd (max.) will not cause any operation problems. 2. either t rch (min.) or t rrh (min.) should be met in read cycles. 3. t oez(max.) defines the time when the output achieves the condition of hi-z and is not referenced to v oh or v ol . 4. we: inactive (in read cycle) cas: inactive, oe: activet cho is effective. cas, oe: activet och is effective.
m pd42s65165, 4265165 12 write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. we hold time referenced to cas t wch 7C10Cns1 we pulse width t wp 7C10Cns1 we lead time referenced to ras t rwl 13 C 15 C ns we lead time referenced to cas t cwl 7C10Cns we setup time t wcs 0C0Cns2 oe hold time t oeh 0C0Cns data-in setup time t ds 0C0Cns3 data-in hold time t dh 7C10Cns3 notes 1. t wp (min.) is applied to late write cycles or read modify write cycles. in early write cycles, t wch (min.) should be met. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. 3. t ds (min.) and t dh (min.) are referenced to the cas falling edge in early write cycles. in late write cycles and read modify write cycles, they are referenced to the we falling edge. read modify write cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. read modify write cycle time t rwc 107 C 133 C ns ras to we delay time t rwd 64 C 77 C ns 1 cas to we delay time t cwd 27 C 32 C ns 1 column address to we delay time t awd 39 C 47 C ns 1 note 1. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate.
m pd42s65165, 4265165 13 hyper page mode (edo) parameter symbol t rac = 50 ns t rac = 60 ns unit notes min. max. min. max. read / write cycle time t hpc 20 C 25 C ns 1 ras pulse width t rasp 50 125,000 60 125,000 ns cas pulse width t hcas 8 10,000 10 10,000 ns cas precharge time t cp 7C10Cns access time from cas precharge t acp C 30 C 35 ns cas precharge to we delay time t cpwd 41 C 52 C ns 2 ras hold time from cas precharge t rhcp 30 C 35 C ns read modify write cycle time t hprwc 52 C 66 C ns data output hold time t dhc 5C5Cns oe to cas hold time t och 5C5Cns3 oe precharge time t oep 5C5Cns output buffer turn-off delay from we t wez 0 10 0 13 ns 4, 5 we pulse width t wpz 7C10Cns5 output buffer turn-off delay from ras t ofr 0 10 0 13 ns 4, 5 output buffer turn-off delay from cas t ofc 0 10 0 13 ns 4, 5 notes 1. t hpc (min.) is applied to cas access. 2. if t wcs 3 t wcs (min.) , the cycle is an early write cycle and the data out will remain hi-z through the entire cycle. if t rwd 3 t rwd (min.) , t cwd 3 t cwd (min.) , t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.) , the cycle is a read modify write cycle and the data out will contain data read from the selected cell. if neither of the above conditions is met, the state of the data out is indeterminate. 3. we: inactive (in read cycle) cas: inactive, oe: active t cho is effective. cas, oe: active t och is effective. 4. t ofc (max.) , t ofr (max.) and t wez (max.) define the time when the output achieves the conditions of hi-z and is not referenced to v oh or v ol . 5. to make i/os to hi-z in read cycle, it is necessary to control ras, cas, we, oe as follows. the effective specification depends on state of each signal. (1) both ras and cas are inactive (at the end of the read cycle) we: inactive, oe: active t ofc is effective when ras is inactivated before cas is inactivated. t ofr is effective when cas is inactivated before ras is inactivated. the slower of t ofc and t ofr becomes effective. (2) both ras and cas are active or either ras or cas is active (in read cycle) we, oe: inactive t oez is effective. both ras and cas are inactive or ras is active and cas is inactive (at the end of read cycle) we, oe: active and either t rrh or t rch must be met t wez and t wpz are effective. the faster of t oez and t wez becomes effective. the faster of (1) and (2) becomes effective.
m pd42s65165, 4265165 14 refresh cycle parameter symbol t rac = 50 ns t rac = 60 ns unit note min. max. min. max. cas setup time t csr 5C5Cns cas hold time (cas before ras refresh) t chr 10 C 10 C ns ras precharge cas hold time t rpc 5C5Cns ras pulse width (cas before ras self refresh) t rass 100 C 100 C m s1 ras precharge time (cas before ras self refresh) t rps 90 C 110 C ns 1 cas hold time (cas before ras self refresh) t chs C50 C C50 C ns 1 we setup time t wsr 10 C 10 C ns we hold time t whr 15 C 15 C ns note 1. this specification is applied only to the m pd42s65165.
m pd42s65165, 4265165 15 read cycle t rc t ras t rp v ih v il ? ras t ofr hi - z t csh data out v ih v il ? ucas v ih v il ? address v ih v il ? we v ih v il ? u i/o v oh v ol ? hi - z t ofc t oez t clz t olz t cac t aa t rac t oea t wez t wpz t rrh t rcs row col. t cah t asc t rah t asr t rad t crp t rcd t rsh t cas t cpn t ral t rch t cho t oes t och lcas l i/o oe
m pd42s65165, 4265165 16 upper byte read cycle v ih v il ? ras v ih v il ? ucas v ih v il ? address v ih v il ? we v ih v il ? oe v oh v ol ? u i/o t rc t ras t rp hi - z t csh data out hi - z t ofc t oez t clz t olz t cac t aa t rac t oes t oea t rch t rcs row col. t cah t asc t rah t asr t rad t crp t rcd t rsh t cas t cpn t crp t mrh t ral v ih v il ? lcas t rrh t ofr t cho t wez t wpz t och remark l i/o: hi-z
m pd42s65165, 4265165 17 lower byte read cycle v ih v il ? ras v ih v il ? ucas v ih v il ? address v ih v il ? we v ih v il ? oe v oh v ol ? l i/o t crp t mrh t rc t ras t rp hi - z t csh data out hi - z t ofc t oez t clz t olz t cac t aa t rac t oes t oea t rch t rcs row col. t cah t asc t rah t asr t rad t crp t rcd t rsh t cas t cpn t ral v ih v il ? lcas t rrh t ofr t cho t wez t wpz t och remark u i/o: hi-z
m pd42s65165, 4265165 18 early write cycle ras t ras t rc t rp t csh t rsh t rcd t cas t cpn t crp t rad t asr t rah t asc t cah row col. t wcs v ih? v il? ucas v ih? v il? address v ih? v il? we v ih? v il? data in l i/o v ih? v il? t ds t wch t dh u i/o lcas remark oe: dont care
m pd42s65165, 4265165 19 upper byte early write cycle v ih v il ? ras v ih v il ? ucas lcas v ih v il ? address v ih v il ? we v ih v il ? u i/o t rc t ras t rp t asr t crp t cah t asc t rah t rad t csh t rcd t rsh t cas row col. t mrh data in t wcs t ds t wch t dh v ih v il ? t crp t cpn remark oe, l i/o: dont care
m pd42s65165, 4265165 20 lower byte early write cycle v ih v il ? ras t rc t ras t rp t crp t mrh t cpn t rsh t crp t rcd t cas t csh t asr t rah row col. t asc t cah t rad data in t wcs t wch t ds t dh v ih v il ? ucas v ih v il ? lcas v ih v il ? address v ih v il ? we v ih v il ? l i/o remark oe, u i/o: dont care
m pd42s65165, 4265165 21 late write cycle u i/o l i/o ras v ih? v il? we v ih? v il? t ras t rp t rc ucas v ih? v il? t csh t rcd t crp t rsh t cas t cpn address v ih? v il? t asr t rah t asc t cah t rad row col. t rcs oe v ih? v il? v ih? v il? t cwl t oed data in hi-z t rwl t wp t oeh t ds t dh lcas
m pd42s65165, 4265165 22 upper byte late write cycle v ih v il ? ras v ih v il ? ucas lcas v ih v il ? address v ih v il ? we v ih v il ? t rc t ras t rp t asr t crp t cah t asc t rah t rad t csh t rcd t rsh t cas row col. t cpn data in t rcs t oed t wp t dh v ih v il ? u i/o oe t cwl t rwl t ds t oeh t mrh t crp v ih v il ? hi - z remark l i/o: dont care
m pd42s65165, 4265165 23 lower byte late write cycle v ih v il ? ras v ih v il ? ucas lcas v ih v il ? address v ih v il ? we v ih v il ? t rc t ras t rp t asr t crp t cah t asc t rah t rad t csh t rcd t rsh t cas row col. t cpn data in t rcs t oed t wp t dh v ih v il ? l i/o oe t cwl t rwl t ds t oeh t mrh t crp v ih v il ? hi - z remark u i/o: dont care
m pd42s65165, 4265165 24 read modify write cycle ras v ih? v il? we v ih? v il? t ras t rp t rwc ucas lcas v ih? v il? t csh t rcd t crp t rsh t cas t cpn address v ih? v il? t asr t rah t asc t cah t rad row col. t rcs oe v ih? v il? v ih? v il? t rwd t cac data in t awd t cwd t ds t dh t wp t rwl t cwl t aa t rac t oed t oea t oeh u i/o l i/o v oh? v ol? data out hi-z hi-z t oez t clz t olz u i/o l i/o
m pd42s65165, 4265165 25 upper byte read modify write cycle v ih v il ? ras v ih v il ? ucas lcas v ih v il ? address v ih v il ? we v ih v il ? u i/o v ih v il ? oe u i/o v ih v il ? v oh v ol ? row col. t rwc t ras t rp t csh t crp t rcd t rsh t cas t cpn t asr t rah t rad t asc t cah t rwd t awd t cwd t rcs t cwl t rwl t wp t oeh t oea data in hi - z t rac t aa t cac t oed t ds t dh t oez data out hi - z t olz t clz t crp t mrh remark in this cycle, the input data to lower i/o is ineffective. the data out of that remains hi-z.
m pd42s65165, 4265165 26 lower byte read modify write cycle v ih v il ? ras v ih v il ? ucas lcas v ih v il ? address v ih v il ? we v ih v il ? l i/o v ih v il ? oe l i/o v ih v il ? v oh v ol ? row col. t rwc t ras t rp t csh t crp t rcd t rsh t cas t cpn t asr t rah t rad t asc t cah t rwd t awd t cwd t rcs t cwl t rwl t wp t oeh t oea data in hi - z t rac t aa t cac t oed t ds t dh t oez data out hi - z t olz t clz t crp t mrh remark in this cycle, the input data to upper i/o is ineffective. the data out of that remains hi-z.
m pd42s65165, 4265165 27 hyper page mode (edo) read cycle ras ucas lcas address we oe u i/o l i/o t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rch t rrh t wpz t wez t oez t acp t aa t cac t acp t aa t cac t dhc t dhc t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z v i h ? v il ? v i h ? v il ? v i h ? v il ? v i h ? v il ? v i h ? v il ? v o h ? v ol ? t ofr t ofc t cho t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 28 hyper page mode (edo) byte read cycle t rcs t asr t rah row data out hi - z t cah t rac t aa t cac t clz t rasp t crp t csh t rsh t hpc ras v ih ? v il ? v ih ? v il ? we v ih ? v il ? oe v ih ? v il ? v oh ? v ol ? address v ih ? v il ? t acp ucas l i/o data out t rp t rcd t hcas data out t oea t olz t asc col. col. col. t aa t cac t acp t aa t cac t clz t dhc hi - z t oez t dhc t asc t cah t hcas t cp t cp t mrh t hcas t rad t crp t asc t cah t ral t ofr t ofc t cpn t rhcp t cho t wez t rch t wpz v oh ? v ol ? u i/o v ih ? v il ? lcas t rrh t och remarks 1. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle. 2. this cycle can be used to control either ucas or lcas only. or, it can be used to control ucas or lcas simultaneously, or at random.
m pd42s65165, 4265165 29 hyper page mode (edo) read cycle (we control) ras ucas lcas address we oe v i h ? v il ? v i h ? v il ? v i h ? v il ? v i h ? v il ? v i h ? v il ? v o h ? v ol ? t rasp t rp t crp t rcd t hcas t csh t rhcp t rsh t hcas t cpn t hcas t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rrh t wpz t ofr t ofc t oez t aa t aa t clz t cac t cac t clz t wez t wez t oea t olz t rac t aa t cac t clz row col. col. col. data out data out data out hi - z u i/o l i/o t rch t wpz t rcs t rch t wpz t rcs t rch hi - z hi - z t wez t cho t och remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 30 hyper page mode (edo) read cycle (oe control) t rasp t rhcp t rp t csh t hpc t rsh t ral t rad t asr t rah t asc t cah t asc t cah t asc t cah t rcs t rch t rrh t oea t oez t aa hi - z hi - z row col.a col.b col.c t oea t acp t oes t olz t crp t rcd t hcas t cp t hcas t cp t hcas t cpn ras ucas lcas address oe u i/o l i/o data out a data out b data out b data out c t ofc t oez t ofr t oea t acp t och t olz t aa t cac t oez t oez t oep t oep t oep t och t och t cho t cho t cho we t rac t aa t cac t clz t cac t clz v i h ? v il ? v i h ? v il ? v i h ? v il ? v i h ? v il ? v i h ? v il ? v o h ? v ol ? t olz remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 31 hyper page mode (edo) early write cycle ras t rasp v ih? v il? ucas lcas v ih? v il? address v ih? v il? we v ih? v il? u i/o l i/o v ih? v il? t rp t rhcp t rsh t hpc t cpn t csh t hcas t cp t hcas t hcas t cp t ral t cah t cah t asc t cah col. col. row t asr t rah t wcs t wcs t rcd t rad t asc col. t wch t wch t wch data in data in data in t dh t ds t dh t ds t dh t ds t wcs t asc t crp remarks 1. oe: dont care 2. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 32 hyper page mode (edo) byte early write cycle ras v ih? v il? t rasp ucas v ih? v il? l i/o v ih? v il? t rp t rhcp t rsh t hpc t csh t rcd t crp t hcas t cpn t hcas u i/o v ih? v il? address row col. col. col. v ih? v il? t asr t rad t asc t rah t cah t cah t asc t wcs t cah t ral t asc we v ih? v il? t wcs t wch t wcs t wch t wch lcas v ih? v il? t hcas t cp t crp t cp t mrh data in data in t ds t dh t dh t ds data in t ds t dh remarks 1. oe: dont care 2. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle. 3. this cycle can be used to control either ucas or lcas only. or, it can be used to control ucas or lcas simultaneously, or at random.
m pd42s65165, 4265165 33 hyper page mode (edo) late write cycle ucas lcas v ih? v il? t cpn t cp t cp t csh t hcas t rcd ras v ih? v il? t rasp t rp t crp t hpc t rsh t rhcp t hcas t hcas row col. t asr t rah t rad t asc t cah t asc col. t cah t asc col. t cah t ral address v ih? v il? we v ih? v il? t rcs t cwl t wp t rcs t cwl t wp t rcs t cwl t wp t rwl v ih? v il? t oeh t oeh t oeh u i/o l i/o v ih? v il? t oed t ds t dh hi-z data in t oed t ds t dh data in hi-z t oed t ds t dh data in hi-z oe remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 34 hyper page mode (edo) byte late write cycle ras v ih? v il? t rasp ucas v ih? v il? u i/o hi - z v ih? v il? t rp t rhcp t rsh t hpc t csh t rcd t crp t hcas t cpn t hcas lcas v ih? v il? t crp t mrh t cp t hcas t cp address v ih? v il? oe v ih? v il? l i/o v ih? v il? data in t oed hi - z hi - z t dh hi - z data in t oed t oed hi - z hi - z data in t oed t ds t oed t ds t dh t oed t ds t dh t oeh t oeh t oeh t wp t rcs t cwl t cwl t rcs t wp row col. col. col. t rwl t cwl t wp t rcs t ral t cah t asc t cah t asc t cah t asc t rah t asr t rad we v ih? v il? remarks 1. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle. 2. this cycle can be used to control either ucas or lcas only. or, it can be used to control ucas or lcas simultaneously, or at random.
m pd42s65165, 4265165 35 hyper page mode (edo) read modify write cycle t rcs ucas lcas v ih? v il? t cpn t cp t hcas t hcas t cp t hprwc t hcas t rcd ras v ih? v il? t rasp t rp t crp address v ih? v il? t asr t rah t rad t asc t cah t asc t cah t cah t asc row col. col. col. t ral we v ih? v il? t rwd t olz v ih? v il? t dh t ds t awd t cwd t wp t rcs t cwl t acp t cpwd t awd t cwd t wp t cwl t acp t cpwd t awd t cwd t rcs t cwl t rwl t wp oe v ih? v il? u i/o l i/o v oh? v ol? out t oez t clz t oed t oea t cac t aa t rac in t oea t oeh t cac t aa t olz t dh t ds out t oez t clz t oed in t olz t dh t ds out t oez t clz t oed in t oeh t aa t cac t oea t oeh hi-z hi-z hi-z hi-z u i/o l i/o remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 36 hyper page mode (edo) byte read modify write cycle ras v ih? v il? t rasp ucas v ih? v il? l i/o v oh? v ol? t rp t hprwc t rcd t crp t hcas t cpn t hcas lcas v ih? v il? t crp t mrh t cp t hcas t cp address v ih? v il? oe v ih? v il? u i/o v ih? v il? in t dh t olz t clz t cac t oez hi - z hi - z out t ds t olz t oeh t oeh t cwd t wp t rwd t cpwd t rac t cac t rcs t acp row col. col. col. t awd t cwd t cah t cah t asc t rah t asr t rad we v ih? v il? v ih? v il? in out hi - z hi - z in t dh t dh t ds t ds out t oez t oed t oed t clz t oea t cac hi - z t olz t oez t oed t clz t oea t oea t aa t aa t aa t awd t rcs t wp t rcs t oeh t cwd t cwl t cpwd t acp t awd t cwl t rwl t wp t asc t cah t asc t ral t cwl u i/o v oh? v ol? l i/o remarks 1. in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle. 2. this cycle can be used to control either ucas or lcas only. or, it can be used to control ucas or lcas simultaneously, or at random.
m pd42s65165, 4265165 37 hyper page mode (edo) read and write cycle v i h ? v il ? ras v i h ? v il ? ucas lcas v i h ? v il ? address v i h ? v il ? we v i h ? v il ? oe v o h ? v ol ? t rasp t rp t crp t rcd t hcas t csh t cp t rhcp t rsh t hcas t cpn t hcas t hpc t cp t asr t rah t asc t rad t cah t asc t cah t asc t cah t ral t rcs t rch t acp t aa t cac t wez t dhc t oea t rac t aa t cac t clz row col. col. col. data out data out hi - z t oez t wcs t wch hi - z t dh t ds data in u i/o l i/o v i h ? v il ? t cho u i/o l i/o t och t olz remark in the hyper page mode (edo), read, write and read modify write cycles are available for each of the consecutive cas cycles within the same ras cycle.
m pd42s65165, 4265165 38 cas before ras self refresh cycle (only for the m pd42s65165) remark address, oe: dont care l i/o, u i/o: hi-z cautions on use of cas before ras self refresh cas before ras self refresh can be used independently when used in combination with distributed cas before ras long refresh; however, when used in combination with burst cas before ras long refresh or with long ras only refresh (both distributed and burst), the following cautions must be observed. (1) normal combined use of cas before ras self refresh and burst cas before ras long refresh when cas before ras self refresh and burst cas before ras long refresh are used in combination, please perform cas before ras refresh 4,096 times within a 64 ms interval just before and after setting cas before ras self refresh. (2) normal combined use of cas before ras self refresh and long ras only refresh when cas before ras self refresh and ras only refresh are used in combination, please perform ras only refresh 4,096 times within a 64 ms interval just before and after setting cas before ras self refresh. (3) if t rass (min.) is not satisfied at the beginning of cas before ras self refresh cycles (t ras < 100 m s), cas before ras refresh cycles will be executed one time. if 10 m s < t ras < 100 m s, ras precharge time for cas before ras self refresh (t rps ) is applied. and refresh cycles (4,096/128 ms) should be met. for details, please refer to how to use dram users manual. ras ucas lcas we v ih _ v il _ v ih _ v il _ v ih _ v il _ t csr t wsr t whr t rass t rps t crp t rpc t chs t cpn
m pd42s65165, 4265165 39 cas before ras refresh cycle ras t rc v ih? v il? ucas lcas v ih? v il? v ih? v il? t whr t csr t chr t rpc t csr t chr t rpc t cpn t crp t ras t rp t rp t ras t wsr we t rc t wsr t whr remark address, oe: dont care l i/o, u i/o: hi-z ras only refresh cycle ras t rc v ih? v il? v ih? v il? t asr t crp t rpc t cpn t crp t ras t rp t rp t ras t asr t rc row address v ih? v il? t rah t rah row ucas lcas remark we, oe: dont care l i/o, u i/o: hi-z
m pd42s65165, 4265165 40 hidden refresh cycle (read) t rc t rc t ras t rp t rad t ral t asr t rah row col. data out hi - z hi - z t asc t rcs t whr t oes t oea t rac t aa t cac t olz t clz t ofc t oez t cah t rp t ras t crp t rcd t rsh t cpn t chr ras v ih ? v il ? v ih ? v il ? we v ih ? v il ? oe v ih ? v il ? v oh ? v ol ? address v ih ? v il ? t wez t cho t ofr t wpz t rch ucas lcas u i/o l i/o
m pd42s65165, 4265165 41 hidden refresh cycle (write) t ras t rp t ras t rp t rc t rc t crp t rcd t asr t rah t rsh t chr t cpn v ih v il ? ras v ih v il ? ucas lcas v ih v il ? address v ih v il ? we v ih v il ? u i/o l i/o t rad t asc t cah t wcs t dh row col. t ds data in t wch t wsr t whr remark oe: dont care
m pd42s65165, 4265165 42 package drawing 50pin plastic tsop( ii ) (400 mil) item millimeters inches a b c e f g i 21.17 max. 0.8 (t.p.) 1.2 max. 0.97 1.0 max. m n 0.10 10.16?.1 0.13 0.1?.05 0.834 max. 0.040 max. 0.004?.002 0.048 max. 0.038 0.400?.004 0.005 0.004 0.031 (t.p.) h 11.76?.2 0.463?.008 note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.32 0.013?.003 j 0.8?.2 0.031 +0.009 ?.008 k 0.145 0.006?.001 l 0.5?.1 0.020 +0.004 ?.005 s50g5-80-7jf3 p3 +7 ? +0.025 ?.015 +0.08 ?.07 3 +7 ? detail of lead end d m m f 50 26 125 c n g b a l k i h j e p
m pd42s65165, 4265165 43 recommended soldering conditions please consult with our sales offices for soldering conditions of the m pd42s65165, 4265165. type of surface mount device m pd42s65165g5-7jf, 4265165g5-7jf: 50-pin plastic tsop (ii) (400 mil)
m pd42s65165, 4265165 44 [memo]
m pd42s65165, 4265165 45 [memo]
m pd42s65165, 4265165 46 [memo]
m pd42s65165, 4265165 47 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd42s65165, 4265165 2 [memo] no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5

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