View 83C795_6073861.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ethernet system controller 83C795 ? data book
table of contents 1.0. general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.0. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3.0. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1. description of data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2. conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.0. pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1. special input-to-output pin mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.0. ethernet system controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1. host interface internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1. cr - control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.2. eer - eerom register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.3. iopl - i/o pipe data location low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.4. ioph - i/o pipe data location high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.5. hwr - hardware support register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.6. bpr - bios page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.7. icr - interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.8. rev/iopa - revision/i/o pipe address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.9. lan0 - lan5 - lan address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.10. bdid - board id register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.11. cksm - checksum register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.11. gcr2 - general control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.13. iar - i/o address register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.14. rar - ram address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.15. bio - rom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.16. gcr - general control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.17. erfal - early receive fail address low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.18. erfah - early receive fail address high register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2. lan controller register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1. alicnt - alignment error counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.2. bound - receive boundary page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.3. cmd - command register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.4. colcnt - collision count register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.5. crccnt - crc error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.6. curr - current frame buffer pointer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.7. currh - current frame buffer descriptor pointer register high . . . . . . . . . . . . . . . . . 25 5.2.8. currl - current frame buffer descriptor pointer register low . . . . . . . . . . . . . . . . . . 25
5.2.9. dcon - data configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.10. enh - enhancement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.11. erwcnt - early receive warning threshold register . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2.12. group0-group7 - multicast filter table registers . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.13. intmask - interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.14. intstat - interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.15. manch - manchester management register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.16. mpcnt - missed pa cket error counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.17. next - dma controller next buffer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.18. raddh - receive burst starting address high register . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.19. raddl - re ceive burst starting address low register . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.20. rbegin - receive buffer starting address register . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.21. rcnth - receive byte count high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.22. rcntl - receive byte count low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.23. rcon - receive configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.24. rdownh - buffer room remaining high register . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.25. rdownl - buffer room remaining low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.26. rend - receive buffer end register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.27. rstart - receive start page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.28. rstat - receive packet status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.2.29. rstop - receive stop page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.30. rtabh - receive buffer table pointer high register . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.31. rtabl - receive buffer table pointer low register. . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.32. sta0-sta5 - station address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.2.33. taddh - transmit burst starting address high register . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.34. taddl - tr ansmit burst starting address low register . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2.35. tbegin - transmit buffer starting address register . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.36. tcnth - transmit frame length high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.37. tcntl - transmit frame length low register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.38. tcon - transmit configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2.39. tdownh - transfer count high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2.40. tdownl - transfer count low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2.41. tend - transfer buffer end register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2.42. tlevel - transmit fifo track register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.43. tstarth - transmit start page high register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.44. tstartl - transmit start page low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.45. tstat - transmit status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2.46. ttabh - transmit buffer pointer high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2.47. ttabl - transmit buffer pointer low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2.48. ubrcv - ultra board receive register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6.0. host interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1. memory cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.1.1. zero wait state response to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.2. staggered address transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.1.3. operation on micro-channel adapters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2. i/o-mapped pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3. address decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.3.1. memory address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.2. i/o address decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.2.1. pc-98 bus support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4. bus control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.1. iordy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.2. zero wait state response to host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.5. memory bus structure and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5.1. memory bus width control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.5.2. 16-bit response to host access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.6. interrupt request control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.7. eerom controller and its utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.7.1. initialization of 83C795 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.7.2. retrieval and storage of host configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.2.1. eerom interface overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.2.2. eerom recall operation details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.7.2.3. storage operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.8. plug and play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.8.1. auto-configuration ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.8.2. plug and play states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.8.2.1. isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8.2.2. configuration and activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8.3. configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.8.4. resource string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.8.5. configuring as a boot card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.8.6. configuring with an i/o-mapped pipe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.8.7. buffer memory limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.9. external power supply control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.0. lan controller over view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1. dma controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1.1. assembly and disa ssembly latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.1.2. memory interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
7.1.3. lan controller internal bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.4. dma microcontroller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.5. how to access registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.1.6. memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.2. fifos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3. receiver network interface (phy-to-mac). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.3.1. aui differential receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2. twisted-pair differential receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.2.1. extended length for twisted-pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.3. manchester decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.4. carrier sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.5. collision detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.3.6. loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 7.4. mac receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.1. basic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.2. interface to the mac receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.3. loopback paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.4. receive deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.4.5. crc checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.4.6. address recognition logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 7.4.7. received byte counter and early receive warning interrupt. . . . . . . . . . . . . . . . . . . . . 71 7.4.7.1. early receive failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4.8. receive protocol fsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4.9. reception process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.4.9.1. start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.9.2. end of frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.10. receiver blinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.5. transmitter network interface (mac-to-phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.1. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.2. manchester encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.3. aui differential driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.4. collision tran slator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.5. twisted-pair differential driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.6. link integrity test function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.7. jabber protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.8. sqe test (heartbeat test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.5.9. status indications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6. transmitter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.1. basic function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.6.2. preamble generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.3. transmit serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.4. crc generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.5. transmit protocol fsm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.5.1. interframe gap and deference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.5.2. collision handling logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 7.6.6. timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.1. slot timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.2. backoff timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.3. collision counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.6.4. heartbeat detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7. transmitter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7.1. transmission initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7.2. transmission process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.6.7.3. transmit underrun. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.7.4. early transmit underrun protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.7.5. collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7.6.7.6. extensions beyond 802.3 10base5 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.6.7.7 extended length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.0. buffer structuring and data movement processes . . . . . . . . . . . . . . . . . . . . . . . 80 8.1. transmit packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.1. single packet transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.2. multiple packet transmissions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.1.2.1. ownership of buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.1.2.2. modifying the transmit queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.2. receive packet buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.1. ring of buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.2.1.1. automatic ring wrapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2.1.2. ring-empty bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.2.2. linked-list receiver buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.0. electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.2. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3. dc operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3.1. input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3.2. output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.0. ac operating characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.0. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
list of figures figure 1-1. 83C795 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3-1. 83c790 data path flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4-1. 83c790 pin out diagram (160 pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 6-1. memory cache arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6-2. overlapping address structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 6-3. external cascaded address decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 6-4. address generation path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 6-5. interrupt control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 6-6. eerom register logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 6-7. plug and play state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 6-8. plug and play configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 7-1. basic dma cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 7-2. aui/twisted-pair i nterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 7-3. simplified transmit circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 8-1. multiple frame transmit buffer format. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 8-2. receiver buffer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 8-3. ring buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 8-4. receiver buffer ring 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 8-5. receiver buffer ring 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 8-6. linked-list buffer format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 10-1. system clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 10-2. register access timing - read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 10-3. register access timing - write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 10-4. 16-bit register access (i/o pipe only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 10-5. host memory access (16-bit, zws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 10-6. host memory access (16-bit, no zws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 10-7. host memory access (8-bit, zws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 10-8. host memory access (8-bit, no zws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 10-9. rom access (8-bit only, read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 10-10. dma or memory cache writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 10-11. dma or memory cache reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 10-12. eeprom interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 10-13. transmit timing - start of transmission . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 10-14. transmit timing - end of transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 10-15. transmit timing - end of transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 10-16. receive timing - start of packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
figure 10-17. receive timing - end of packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 10-18. collision timing - tp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 10-19. collision timing - aui . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 10-20. loopback timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 10-21. sqe test timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 10-22. link test pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 10-23. rom dump (test mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 11-1. 160-pin pqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
list of tables table 4-1. 83C795 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 4-2. i/o pin mapping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4-3. i/o pin output values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5-1. host interface registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5-2. lan controller registers - normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5-3. lan controller registers - linked-list mode . . . . . . . . . . . . . . . . . . . . . . . . 13 table 5-4. register term definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5-5. buffer window size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5-6. rom window size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5-7. interrupt request field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5-8. page select field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5-9. slot time selection field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5-10. group register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5-11. station address register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 5-12. loopback test selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 5-13. host interface register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 5-14. lan controller register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 6-1. host interface address decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 6-2. jumper example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 6-3. eerom recall operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6-4. config register/init pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 6-5. eerom location allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6-6. auto-configuration ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 6-7. plug and play bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 6-8. plug and play resource string structure . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 7-1. dma burst length field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 8-1. tstat field values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 8-2. format of transmit descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 8-3. meaning of descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 9-1. input pin values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 9-2. output pin values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 10-1. list of timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 10-2. timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 10-3. test pin i/o matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 11-1. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
1.0 general description t he s mc 83C795 e ther net s ys tem contr ol ler implements the ieee 802.3 protocol for networks s uch as e ther net, cheaper net, and 10b as et . i t i s a hi ghl y i ntegr ated devi ce that s hr i nk s the es s ence of a lan adapter card onto a single piece of silicon. it i ncl udes the 8 0 2 . 3 medi a acces s contr ol (mac) functions , the p hys ical l ayer i nterface (p l i ) for 1 0 b as e - t medi a, and a hos t i nter face des i gned for s imple connecti on to the i ndus try s tandard ar chitectur e (i s a) p c/at bus . t o cr eate a l an adapter onl y the 8 3 c7 9 5 , a s i ngl e buff er r am, an e e r om chi p, and an opti onal r om f or b i os or i p l code s tor age ar e r equ i r ed. t r ans f or mer s and s uppor ti ng anal og components complete an adapter design. all necessary control l ogi c i s pr ovi ded by the 8 3 c7 9 5 . t h e r es u l t i n g l an adapter appear s to th e h os t as a bl ock of i /o r egi s ter s wi th a bl ock of s har ed memor y, unl es s the i /o pi pe i s us ed. t he bas e addr es s for i /o r egi s ter s i s pr ogr ammabl e as i s the bas e addr es s and s i z e of the buff er memor y. this device is similar to the smc 83c790 lan controller with three major differences: a small memory cache has been added for host accesses to shared memory. an i/o pipe mode has been added to access the buffer memory. auto-configurability logic has been added in order to comply with the new isa plug and play specification. as wi th the 83c79 0 chi p, ther e ar e two bas i c modes of oper ati on: nor mal and al t e go. i n the nor mal mode, the lan controller operates much like the 83c690 l an contr ol ler wi th received frames bei ng buffered in a r ing of contiguous , fixed-s iz e buffers . when the al t e go featur e i s enabl ed, the devi ce s wi tches to a ver y di ffer ent mode of oper ati on. t he di ffer ences ar e s ummar i z ed her e and ex pl ai ned i n detail thr oughout the s pecifi cati on: 1. linked-list style of buffering instead of ring buffers. 2. different register map for lan controller, ex- posing new registers for the linked-list buff- ering. f igure 1-1 depicts the 83C795s functionality. 2.0 features t he bas i c featur es of the 8 3 c7 9 5 chi p ar e summarized here: memory caching with time-shared access to buffer ram. compliant with the isa plug and play specification software compatible with 83c790 drivers direct interface with isa bus without ttl buffers i/o-mapped pipe access to buffer ram extended length option for the twisted-pair port underrun detection in early receive mode staggered address transfers supported ring-empty bit supplied to host automatic ring-wrapping pc-98 bus support through addition of a jumper buffered 20 mhz clock output available through addition of a jumper support for diskless workstations via initial program load rom programmable base address and window size for buffer memory and ipl rom support for paging of buffer memory and ipl rom programmable i/o base address programmable bus width of either 8 or 16 bits zero wait state operation automatic loading of host interface configuration and lan address from external serial eeprom separate address and data busses to memory with no external address latches 7 programmable interrupt levels clock oscillator full 802.3 mac layer protocol implementation with extended features support for transmission and reception of frames up to 32k bytes long transmit frame start at any location - no word alignment required two modes of frame buffering: 83c690 mode and descriptor table mode loopback modes - internal and external full-duplex dma capability in loopback mode built-in aui serial interface including drivers and receivers
built-in 10base-t serial interface for ethernet on twisted-pair including drivers and receivers manchester encoder/decoder with clock recovery circuitry multicast addressing using 64-bit hashing algorithm i/o pin mapping enables rapid board test development 160-pin pqfp package for surface mounting. figure 1-1. 83C795 block diagram
3.0 functional description t h e pr i n ci pl e s ecti on s of t he dev i ce ar e th e: host interface which mediates host access to internal registers and buffer memory. lan controller which performs 802.3 mac layer protocol and does supporting dma transfers to and from local buffer memory. serial line interface which supplies drivers and receivers for aui and tp interfaces and port control logic for the 10base-t interface. in addition, it provides manchester encoding and decoding. 3.1 description of data path f igure 3-1 illus trates the data path for a 8 3 c7 9 5 - bas ed boar d. al l i nter nal byte s wappi ng i s handl ed by the memor y cache. t he data bus dr i ver s ar e des i gned to dr i ve the i s a bus dir ectl y. 3.2 conventions a number of conventi ons ar e us ed i n thi s databook . 1. a bit may be described as "low" or "logical 0" when its value is set to 0. a bit is described as "high" or "logical 1" when its value is set to 1. 2. the location of a bit is frequently described in this manner: . for example, since the bit menb is located in the cr register, it might be described in this book as cr.menb. or, alternatively, since menb is the sixth bit in the cr regis- ter, it might also be described in this manner: cr.6
figure 3-1. 83c790 data path flow
1.0 general description t he s mc 83C795 e ther net s ys tem contr ol ler implements the ieee 802.3 protocol for networks s uch as e ther net, cheaper net, and 10b as et . i t i s a hi ghl y i ntegr ated devi ce that s hr i nk s the es s ence of a lan adapter card onto a single piece of silicon. it i ncl udes the 8 0 2 . 3 medi a acces s contr ol (mac) functions , the p hys ical l ayer i nterface (p l i ) for 1 0 b as e - t medi a, and a hos t i nter face des i gned for s imple connecti on to the i ndus try s tandard ar chitectur e (i s a) p c/at bus . t o cr eate a l an adapter onl y the 8 3 c7 9 5 , a s i ngl e buff er r am, an e e r om chi p, and an opti onal r om f or b i os or i p l code s tor age ar e r equ i r ed. t r ans f or mer s and s uppor ti ng anal og components complete an adapter design. all necessary control l ogi c i s pr ovi ded by the 8 3 c7 9 5 . t h e r es u l t i n g l an adapter appear s to th e h os t as a bl ock of i /o r egi s ter s wi th a bl ock of s har ed memor y, unl es s the i /o pi pe i s us ed. t he bas e addr es s for i /o r egi s ter s i s pr ogr ammabl e as i s the bas e addr es s and s i z e of the buff er memor y. this device is similar to the smc 83c790 lan controller with three major differences: a small memory cache has been added for host accesses to shared memory. an i/o pipe mode has been added to access the buffer memory. auto-configurability logic has been added in order to comply with the new isa plug and play specification. as wi th the 83c79 0 chi p, ther e ar e two bas i c modes of oper ati on: nor mal and al t e go. i n the nor mal mode, the lan controller operates much like the 83c690 l an contr ol ler wi th received frames bei ng buffered in a r ing of contiguous , fixed-s iz e buffers . when the al t e go featur e i s enabl ed, the devi ce s wi tches to a ver y di ffer ent mode of oper ati on. t he di ffer ences ar e s ummar i z ed her e and ex pl ai ned i n detail thr oughout the s pecifi cati on: 1. linked-list style of buffering instead of ring buffers. 2. different register map for lan controller, ex- posing new registers for the linked-list buff- ering. f igure 1-1 depicts the 83C795s functionality. 2.0 features t he bas i c featur es of the 8 3 c7 9 5 chi p ar e summarized here: memory caching with time-shared access to buffer ram. compliant with the isa plug and play specification software compatible with 83c790 drivers direct interface with isa bus without ttl buffers i/o-mapped pipe access to buffer ram extended length option for the twisted-pair port underrun detection in early receive mode staggered address transfers supported ring-empty bit supplied to host automatic ring-wrapping pc-98 bus support through addition of a jumper buffered 20 mhz clock output available through addition of a jumper support for diskless workstations via initial program load rom programmable base address and window size for buffer memory and ipl rom support for paging of buffer memory and ipl rom programmable i/o base address programmable bus width of either 8 or 16 bits zero wait state operation automatic loading of host interface configuration and lan address from external serial eeprom separate address and data busses to memory with no external address latches 7 programmable interrupt levels clock oscillator full 802.3 mac layer protocol implementation with extended features support for transmission and reception of frames up to 32k bytes long transmit frame start at any location - no word alignment required two modes of frame buffering: 83c690 mode and descriptor table mode loopback modes - internal and external full-duplex dma capability in loopback mode built-in aui serial interface including drivers and receivers
built-in 10base-t serial interface for ethernet on twisted-pair including drivers and receivers manchester encoder/decoder with clock recovery circuitry multicast addressing using 64-bit hashing algorithm i/o pin mapping enables rapid board test development 160-pin pqfp package for surface mounting. figure 1-1. 83C795 block diagram
3.0 functional description t h e pr i n ci pl e s ecti on s of t he dev i ce ar e th e: host interface which mediates host access to internal registers and buffer memory. lan controller which performs 802.3 mac layer protocol and does supporting dma transfers to and from local buffer memory. serial line interface which supplies drivers and receivers for aui and tp interfaces and port control logic for the 10base-t interface. in addition, it provides manchester encoding and decoding. 3.1 description of data path f igure 3-1 illus trates the data path for a 8 3 c7 9 5 - bas ed boar d. al l i nter nal byte s wappi ng i s handl ed by the memor y cache. t he data bus dr i ver s ar e des i gned to dr i ve the i s a bus dir ectl y. 3.2 conventions a number of conventi ons ar e us ed i n thi s databook . 1. a bit may be described as "low" or "logical 0" when its value is set to 0. a bit is described as "high" or "logical 1" when its value is set to 1. 2. the location of a bit is frequently described in this manner: . for example, since the bit menb is located in the cr register, it might be described in this book as cr.menb. or, alternatively, since menb is the sixth bit in the cr regis- ter, it might also be described in this manner: cr.6
figure 3-1. 83c790 data path flow
4.0 pin list this section provides the pin list and pin/signal descriptions for the 83C795. section 4.1 describes the input-to-output pin mapping feature. figure 4-1. 83c790 pin out diagram (160 pins)
mnemonic pin number i/o description ae n 93 i p c addr e s s e nab l e . acti ve l ow. when addr es s e nabl e is active the 83C795 res ponds to any hos t s trobe ( ior, iow, me mr , me mw, smemr, smemw). bale 29 i pc addr e s s l at ch e nabl e . us ed to latch valid addres s es from the la bus. passes la signals through internal latches while hi gh and l atches them on f al l i ng edge. bsr 115 i bias r e s is t or . a res is tor from bs r to vdd s ets the internal bias levels. nominal value is 10k w . cap 113 i p l l f i l t e r cap. a capaci tor (nomi nal val ue . 0 1 m f ) fr om cap to gr ound i s us ed as par t of the fi l ter for the i nter nal phas e l ock l oop. cd+ cd- 126 125 i au i col l i s i on. cd+ / cd- ar e us ed by the ex ter nal tr ans cei ver to signal a collision by sending a 10mhz signal. eecs 132 o e e r om chip s elect. an external 9356 serial e e r om is used to s tor e up to 204 8 bi ts of confi gur ati on data. t hes e s i gnal s (al ong wi th lled and r l e d ) i n ter f ace wi t h th at chi p. eedo 137 i/o eerom data output. gp ou t 11 0 o general purpose output. in some systems, this bit is wired to a s hutdown contr ol i nput of the dc/dc i s ol ated power s uppl y used in 10base2 applications. in other systems, this supplies a control signal for switching power supplies. (the dc signals polarity on the 83C795 is the oppos ite of the 83c790.) hos t clk 71 i/o p er s onal computer b u s cl ock . io16cs 28 o 16 b i t i /o s e l e ct e d. active low. i ndicates to the p c/at bus that the i/o res pons e will be 16 bits wide. only us ed for the i/o pipe. ior 72 i/o p c i /o r e ad. active low. r eads an i /o r egi s ter onto the p c data bu s . iordy 90 o i/o i or dy. r es pons e to hos t acces s which can be us ed directly as i /o channel r eady when r es pondi ng to a per s onal computer bus . it is pulled low (not ready) to lengthen i/o or memory cycles . when the 8 3 c7 9 5 i s r eady to r es pond, the s i gnal i s dr i ven hi gh unti l the hos t acces s is compl eted, then becomes tris tated. t his s i gnal i s dr i ven by a tr i - s tate buffer capabl e of s i nk i ng 2 4 ma. iow 73 i/o pc i/o writ e. active low. writes an i/o register from the pc data bu s . ir q1 108 i/o pc int e r r upt r e que s t l ine s . active high. t ris tated when not acti ve. i r q2-9 on the p c/at bus . i r q1 is the s ame as the xt xd pin in some test modes. irq2 95 i/o irq3 on pc/at bus. same as xloop in some test modes. ir q3 106 i/o irq5 on pc/at bus. same as xcrs in some test modes. ir q4 107 i/o irq7 on pc/at bus. same as xrxc in some test modes. irq5 25 i/o ir q10 on pc/at bus . s ame as xr xd in s ome tes t modes . irq6 24 i/o ir q11 on pc/at bus . s ame as xcol in s ome tes t modes . irq7 23 i/o ir q15 on pc/at bus . s ame as xt xc in s ome tes t modes . table 4-1. 83C795 pin assignments
mnemonic pin number i/o description la17-la23 13-19 i/o pc la address bus. advanced timing version of system address lines a23-a17 from pc/at bus. these are not assumed to be s table during the entir e hos t cycle and ar e latched inter nall y by the b al e s i gnal ( fal l i ng edge) . t hes e s i gnal s ar e acti ve hi gh. lled 131 i/o t wpr l ink s t at us . if valid data or link tes t puls es are received on tpr+ / tpr-, l l e d is low (link s tatus ok). when no data or l i nk t es t pul s es ar e r ecei ved, lled is high. the lled pin can s ink 4ma to drive an external l e d. t his pin als o functions as the eerom clock pin (formerly eesk) and functions as the shift control pin (formerly s hift in) in scan mode. m16cs 26 o me mor y 16 s e l e ct e d. active low. i ndi cates to the p c/at bus that ram access response is 16 bits wide. ma15-ma10 139-144 o me mor y addr e s s l i ne s . t hes e pi ns br i ng out the dma addr es s to memor y or feed- thr ough the hos t addr es s as modi fi ed for pagi ng. when dumpi ng r om contents , thes e pi ns pr es ent rom data bits: ma1 5 r om3 0 then r om3 1 ma1 4 r om2 8 then r om2 9 . . . ma0 0 r om0 0 then r om0 1 ma09/jmp 9 ma08/jmp 8 ma07/jmp 7 ma06/jmp 6 ma05/jmp 5 ma04/jmp 4 ma03/jmp 3 ma02/jmp 2 ma01/jmp 1 ma00/jmp 0 145 146 148 149 150 151 152 153 154 155 i/o s ame as other ma l i nes ex cept that dur i ng r e s e t , the dr i ver s ar e di s abl ed and the i ni t j umper s ar e r ead thr ough thes e pi ns and latched at the trailing edge of r e s e t. t hey are active high and are pulled up weakly by internal resistors (35k w ?150k w ). to s et a zero value on thes e pins , us e an external pull-down r es i s tor of 3. 6k w . md7 md6-md0 158 3-9 i/o me mor y dat a l i ne s . t hes e pi ns connect to the data pi ns of the buffer r am and the i p l or boot r om. me mr 12 i/o p c me mor y r e ad for addr es s es ex ceedi ng 1 m. acti ve l ow. me mw 10 i/o p c me mor y wr i t e for addr es s es ex ceedi ng 1 m. acti ve l ow. os r 11 2 i vco b i as r e s i s t or . a r es i s tor fr om os r to vcc bi as es the internal vco current. nominal value is 24.9k w .. r amoe 156 o r am ou t p u t e nab l e . active low. r amwr 157 o r am wr i t e e nab l e . active low. reset 95 i/o system reset. active high. table 4-1. 83C795 pin assignments (cont.)
mnemonic pin number i/o description r le d 130 i/o r e cv l e d dr ive r . when on, r l e d drives low to turn on an external le d. if no data is received, r l e d is off. if data is received, r l e d goes acti ve for appr ox i mately 50ms l onger than the received packet length. t his pin als o s erves as the e e r om data in pin (e e di) and is us ed as the s can data input (formerly scanin) in scan mode. r omcs 138 o bios r om out put e nabl e . active low. chip s elect for r om bios . us ed for xt xe in s ome tes t modes . rx+ rx- 124 123 i au i r e ce i ve . t he manches ter encoded data fr om the ex ter nal transceiver is received on rx+ / rx-. s a19 - 14 s a13 - 11 s a10 - 09 s a08 - 06 s a05 - 00 88 - 83 78 - 76 44 - 43 38 - 37 35 - 30 i/o pc address bus. normal timing version of system address l i nes . t hes e s i gnal s ar e acti ve hi gh. sbhe 20 i p c b u s h i gh e n ab l e . acti ve l ow. i ndi cates a tr ans fer of data on the upper byte of the data bus , s d8 through s d15. s d15 - 14 s d13 - 12 sd11 - 10 s d09 - 08 sd07 s d06 - 04 s d03 - 02 s d01 - 00 45 - 46 48 - 49 51 - 52 54 - 55 69 65 - 63 61 - 60 58 - 57 i/o system data bus. data input and output to host and shared memor y. t hes e s i gnal s ar e acti ve hi gh. smemr 74 i/o low memory read strobe. reads buffer memory onto the pc data bus . it is active only when the memory addres s is within the fi r s t 1 mb of memor y s pace. acti ve l ow. smemw 75 i/o low me mor y wr it e s t r obe . writes buffer memory from the pc data bus. s me mw i s acti ve onl y when the memor y addr es s i s within the fi rs t 1mb of memory s pace. acti ve l ow. testa testb 117 118 i i/o-mapping control pins. all signal pins on the 83C795 (except for the analog pins) have been divided into two groups, groupa and groupb. the functionality of these pins is controlled by the two test pins, as follows: testa testb groupa groupb 1 1 normal normal 1 0 1 0 0 1 0 1 0 0 tristate tristate table 4-1. 83C795 pin assignments (cont.)
mnemonic pin number i/o description t le d 129 o t r ans mit l e d dr ive r . when on, t l e d dr ives low to tur n on an ex ter nal l e d. w hen ther e i s no tr ans mi s s i on (t x e i nacti ve), t led is off. when data is transmitted, tled goes active for approximately 50ms longer than the tr ans mitted packet length. t l e d does not go acti v e f or l i n k t es t pu l s es . t hi s pi n al s o s er v es as the s can data output (for mer l y s canou t ) i n s can mode, or as a 2 0 mh z buffer ed cl ock output i f j u mp e r 8 i s i ns tal l ed. tpr+ tpr- 128 127 i twpr receive. in 10baset operation, manchester encoded- data are received via tpr+ / tpr-. they are connected to the twi s ted pai r medi um thr ough a tr ans f or mer and fi l ter. tpx1+ tpx1- 103 102 o twpr transmit. tpx1+ and tpx1- are used for 10baset only. t hey ar e the hi gh cur r ent pos i ti ve and negati ve output pi ns . tpx2+ tpx2- 104 101 o twpr transmit. tpx2+ and tpx2- are used for 10baset only. t hey ar e the l ow cur r ent pos i ti ve and negati ve output pi ns . tx+ tx- 99 98 o aui t r ans mit. t x+ and t x- trans mit differential, manches ter encoded data to the tr ans cei ver. t hes e ar e cur r ent- dr i vi ng outputs that fur ni s h e cl l evel s i gnal s when connected to r equi r ed exter nal pullup resistors of 150 w . vdd (14 pins ) 22, 41, 42, 47, 53, 59, 67, 68, 81, 82, 105, 111, 116, 119, 120, 134, 135, 159, 160 +5 volt sources. some are for logic, some power the pin dr i ver s , and other s pr ovi de power to the anal og por ti ons of the ci r cu i t. vs s (24 pins ) 1, 2, 11, 21, 27, 39, 40, 50, 56, 62, 66, 70, 79, 80, 89, 92, 94, 100, 114, 121, 122, 133, 136, 147 gr ou nd. s ome ar e for l ogi c, s ome power the pi n dr i ver s , and other s pr ovi de power to the anal og por ti ons of the ci r cui t. x1 x2 96 97 i o cr y s t al os ci l l at or . t he cr ys tal i s attached acr os s thes e two pins . must be 20.000 mhz 50 ppm. t his clock operates the chi p?s l ogi c and i s di vi ded by 2 i nter nal l y to become the tr ans mi t cl ock . zws 91 o pc z e r o wait s t at e . active low. z ero wait s tate s ignal tells the microproces s or that it can complete the pres ent bus cycl e wi thout i ns er ti ng any addi ti onal wai t cycl es . zws is driven by a tri-state driver capable of sinking 24 ma. table 4-1. 83C795 pin assignments (cont.)
4.1 special input-to-output pin mapping the 83C795 provides a special pin mapping feature which can be used for testing. the pins are divided into two groups, groupa and groupb, for the new i/o pin ma pping scheme. groupa pins groupb pins pin name pin name 3md06 4 md05 5md04 6 md03 7md02 8 md01 9md00 10 me mw 12 me mr 1 3 l a1 7 14 la18 15 la19 16 la20 17 la21 18 la22 19 la23 20 sbhe 23 irq7 24 ir q6 25 ir q15 26 m16cs 28 io16cs 29 bale 30 s a00 31 s a01 32 s a02 33 s a03 34 s a04 35 s a05 36 s a07 37 s a06 38 s a08 43 s a09 44 s a10 45 s d15 46 s d14 48 s d13 49 s d12 51 s d11 52 s d10 54 s d09 55 s d08 57 s d00 58 s d01 60 s d02 61 s d03 63 s d04 64 s d05 65 s d06 69 s d07 71 bs ck 72 ior 73 iow 74 smemr 75 smemw 76 sa11 77 s a12 78 s a13 83 s a14 84 s a15 85 s a16 86 s a17 87 s a18 88 s a19 table 4-2. i/o pin mapping scheme
the i/o pin mapping test for this chip requires only two static vectors. the inputs you must set along with the desired output values are listed in table 4-3. vector pin driven high pins driven low pins outputting 1s pins outputting 0s 1 testa, rxp, tprp, cdp testb, rxm, tprm, cdm gr ou pa pi ns gr ou p b pi ns 2 testb, rxm, tprm, cdm testa, rxp, tprp, cdp gr ou p b pi ns gr ou p a pi ns table 4-3. i/o pin output values note this arrangement does not test the 83C795s analog outputs. groupa pins groupb pins pin name pin nam,e 90 ior dy 91 zws 93 ae n 95 ir q2 106 ir q3 107 ir q4 108 ir q1 109 r e s e t 110 gpout 129 r xm 130 r le d 131 lled 132 e e cs 137 e e do 138 r omcs 139 ma15 140 ma14 141 ma13 142 ma12 143 ma11 144 ma10 145 ma09 146 ma08 148 ma07 149 ma06 150 ma05 151 ma04 152 ma03 153 ma02 154 ma01 155 ma00 156 ramoe 157 r amwr 158 md07 table 4-2. i/o pin mapping scheme (cont.)
5.0 ethernet system controller registers t he r egi s ter s tr uctur e of the 83C795 i s di vi ded i nto two regis ter gr oups : the h os t i nterface regis ters and the l an contr ol l er r egi s ter s . t he fol l owi ng s ections des cri be the contents of each of thes e r egi s ter s , detai l the way they ar e acces s ed, and how they ar e us ed. t abl es 5 -1 thr ough 5 -3 pr ovi de a br i ef over vi ew of thes e r egi s ter s . r efer to the r egi s ter s ummar y tabl es at the end of this section for a quick reference guide to all relevant register bit values. offset swh = 0 swh = 1 00 cr cr 01 eer eer 02 iopl iopl 03 ioph ioph 04 hwr hwr 05 bpr bpr 06 icr icr 07 rev/iopa rev/iopa 08 lan0 gcr2 09 lan1 0a lan2 iar 0b lan3 rar 0c lan4 bio 0d lan5 gcr 0e bdid erfal 0f cksm erfah table 5-1. host interface registers summary
offset page 0 read page 0 write page 1 read page 1 write page 2 read page 2 write page 3 read page 3 write 10 cmd cmd cmd cmd cmd cmd cmd cmd 11 incrl rstart sta0 sta0 rstart incrl test test 12 incrh rstop sta1 sta1 rstop incrh rtest rtest 13 bound bound sta2 sta2 tcntl void ttest ttest 14 tstat tstarth sta3 sta3 tstarth void test2 test2 15 colcnt tcntl sta4 sta4 next next tstartl tstartl 16 {0} tcnth sta5 sta5 tcnth void {0} void 17 intstat intstat curr curr enh enh 18 erwcnt erwcnt group0 group0 raddl raddl 19 renh renh group1 group1 raddh raddh 1a rcntl void group2 group2 taddl taddl 1b rcnth void group3 group3 taddh taddh 1c rstat rcon group4 group4 rcon void 1d alicnt tcon group5 group5 tcon void void 1e crccnt dcon group6 group6 dcon void void 1f mpcnt intmask group7 group7 intmask void manch manch table 5-2. lan controller registers - normal mode offset page 0 read page 0 write page 1 read page 1 write page 2 read page 2 write page 3 read page 3 write 10 cmd cmd cmd cmd cmd cmd cmd cmd 11 rbegin sta0 sta0 rbegin 12 rend sta1 sta1 rend 13 currl currl sta2 sta2 tbegin void 14 tstat tend sta3 sta3 tend void 15 colcnt tbegin sta4 sta4 void tstartl tstartl 16 erwcnt erwcnt sta5 sta5 void {0} void 17 intstat intstat currh currh enh enh 18 rtabl rtabl group0 group0 rdownl rdownl 19 rtabh rtabh group1 group1 rdownh rdownh 1a ttabl ttabl group2 group2 tdownl tdownl 1b ttabh ttabh group3 group3 tdownh tdownh 1c rstat rcon group4 group4 rcon void 1d alicnt tcon group5 group5 tcon void void 1e crccnt group6 group6 dcon void void 1f mpcnt intmask group7 group7 intmask void manch manch table 5-3. lan controller registers - linked-list mode
5.1 host interface internal registers the following section describes the contents of the h os t i nter face i nter nal r egi s ter s . t hi s r egi s ter s et cons i s ts of 24 r egi s ter s ar r anged i n thr ee gr oups of ei ght. t hes e thr ee gr oups ar e the l an addr es s registers, the hardware configuration registers (which write to and read from the e e r om), and the h ar dwar e contr ol r egi s ter s . t he s wi tch r egi s ter bit (h wr .s wh ) determi nes whether the l an addr es s r egi s ter s (s wh = 0) or the h ar dwar e confi gur ati on r egi s ter s (s wh = 1 ) ar e vi s i bl e at any one ti me. (s ee h w r - h ar dwar e s uppor t r egi s ter on page 1 6 for mor e i nfor mati on on thi s bit.) t he hardware control registers (including the cr, eer, hwr, bpr, icr, and rev registers) are al ways vi s i bl e. bits within registers may also have different functi ons dependi ng on whether they ar e r ead fr om or wr i tten to. t hroughout this s ection, certain terms are us ed to des cr i be each r egi s ter and ar e defi ned bel ow: term definition reset value during reset time init if the init3, 2, 1, 0 jumpers = 1001, this value is loaded into the register immediately after reset time. some of these values are forced by hardware and others are recalled from eerom. recall time is on the order of 2 msec. while the initial recall is ongoing, register may have either the reset or init values recall this value is loaded when a recall is performed other than after a reset. register values possible register values are: 1 = logical 1 0 = logical 0 pin = value unknown or wired to external pin. ee = value loaded from eerom. = not used. table 5-4. register term definitions 5.1.1 cr - control register read/write port = 00 t his register has control over buffer memory enabling and soft reset of the lan controller. bit cr reset 7 rnic 1 6 menb 0 5 0 4 cr4 0 3 cr3 0 2 rp15 0 1 rp14 0 0 rp13 0 bit 7: rnic , reset network interface controller s et r ni c to 1 then back to 0 to for ce a hardware reset to the lan controller. bit 6: menb , memory enable s et me nb to 1 to enabl e hos t acces s to s har ed memor y. bit 4-3: cr4-cr3 , reserved for increase in rp field bit 2-0: rp15-rp13 , ram offset a buffer addr es s i s cr eated by addi ng the contents of thi s fi el d to the di ffer ence between the buffer bas e addr es s and the addr es s s uppl i ed by the sa19-sa00 lines. this sum is treated as a movable page offs et whi ch i s then i ns er ted i nto the buffer wi ndow. t hi s offs et val ue s houl d only be us ed when the memor y pr ovi ded i s l ar ger than the wi ndow selected. 5.1.2 eer - eerom register read/write port = 01 t hi s r egi s ter contr ol s the s tor es to and r ecal l s fr om e e r om. i n addi tion, four input pins are vis ible through this register. s ome bits have different functions when r ead than when wr itten.
bit eer read reset 7sto 0 6rc 0 5 ea4 0 4 unlock 0 3 jmp3 pin 2 jmp2 pin 1 jmp1 pin 0 jmp0 pin bit eer write reset 7sto 0 6rc 0 5 ea4 0 4 unlock 0 3 ea3 0 2 ea2 1 1 ea1 1 0 ea0 0 bit 7: sto , store into non-volatile eerom s et this bit to 1 to s tore the 8 l an addr es s regis ters into the e e r om. t he bit automatically r es ets when the store is complete. t his function will not be performed unless the storage circuit has been armed by a series of accesses to the eer register. (s ee s ection 6.5.2.3 for details.) bit 6: rc , recall eerom s et this bit to 1 to r ecall the 8 l an addres s regis ters fr om e e r om. t he bi t wi l l be automati cal l y r es et when the r ecal l i s compl ete. bit 4: unlock , unlock store t his bi t is us ed to unl ock the e e p r om for s tor age operations. (s ee s ection 6.5.2.3 for details.) bits 3-0: jmp3-jmp0 , initialization jumpers t hes e bits are wi red to the jmp i nput pins of the chi p. t he j mp fi el d val ue i s us ed by the r ecal l l ogi c to determi ne which bank of e e r om to load the hos t i nter face confi gur ati on r egi s ter s fr om. bits 5, 3-0: ea4-ea0 , eerom address field t hi s fi el d deter mi nes whi ch bank of e e r om the lan address registers are stored into or recalled from. t his field does not change when a recall operation takes place. e a4 = 1 indicates an access to the plug and play resource string. 5.1.3 iopl - i/o pipe data location low read/write port = 02 t hi s r egi s ter and i op h deter mi ne the l ocati ons data is read from or written to. bit iopl reset 7 iop7 0 6 iop6 0 5 iop5 0 4 iop4 0 3 iop3 0 2 iop2 0 1 iop1 0 0 iop0 0 bits 7-0: iop7-0 , i/o pipe data location low when i op e n (i cr .4) i s s et, thes e ar e the l ocati ons that data is read from or written to in the i/o pipe oper ati on. al l 8 - bi t oper ati ons mus t tak e pl ace through iopl only. 5.1.4 ioph - i/o pipe data location high read/write port = 03 t his regis ter and i op l deter mine the l ocations data is r ead from or wri tten to. bit ioph reset 7 iop15 0 6 iop14 0 5 iop13 0 4 iop12 0 3 iop11 0 2 iop10 0 1 iop9 0 0 iop8 0 bits 15-8: iop15-8 , i/o pipe data location high when i op e n (i cr .4) i s s et, thes e ar e the l ocati ons that data is read from or written to in the i/o pipe oper ati on. al l 8 - bi t oper ati ons mus t tak e pl ace thr ough the i op l regis ter.
5.1.5 hwr - hardware support register read/write port = 04 t his register is used to control general purpose outputs and to s wi tch between conf i gur ati on and l an addr es s r egi s ter s . bit hwr read reset 7swh 0 6 0 5 ethr 1 4 host16 0 3 0 2 istat 0 1 pnpjmp jmp6 0gpoe 0 bit hwr write reset 7swh 0 6 0 5 1 4 0 3 nuke 0 2 0 1 0 0gpoe 0 bit 7: swh , switch register set this bit selects between the lan address registers and the b oar d configur ation regis ters i n the regis ter map wher e: swh = 0 - lan address registers are visible swh = 1 - configuration registers are visible bit 5: ether , mac protocol type when e t h e r = 1 , the 80 2 .3 pr otocol i s pr ovi ded by this device. t he 83C795 s upports only 802.3. bit 4: host16 t his bit reports whether the 83C795 believes it is connected to an 8-bit or 16-bit hos t. t he chip deter - mi nes this by looking at the me mr pi n for acti vi ty. wher e: host16 = 0 - 8-bit host host16 = 1 - 16-bit host bit 3: nuke , restart t hi s bi t i s or ed together wi th the r e s e t pi n s ignal to for m the internal r e s e t for the chip. s etti ng this bi t has the s ame effect on the 83C795 as cycl i ng power on the hos t machi ne. t he chi p wi l l reset to its initial condition and reload from the e e r om. t his bit i s cleared when the r es et be- comes effecti ve. t he nu k e r es et ex ecutes for 256 chi p- cl ock cycl es to al l ow the ma bus to f l oat and the i ni ti al i z ati on j umper s to achi eve thei r tr ue val - ues . note do not try to access this chip during reset. bit 2: istat , interrupt status is t at returns to 1 when network i nterface control- ler has an inter rupt active. bit 1: pnpjmp, plug and play jumper installed a read-only bit that returns a 1 if jumper 6 is in- stalled. if pnpjmp = 1 and the pnpen bit (er- f al .0) i s s et, then p lug and p lay har dwar e is enabl ed. bit 0: gpoe , gpx pin output enable t he output i s enabl ed when gp oe = 1 .
5.1.6 bpr - bios page register read/write port = 05 t hi s r egi s ter contr ol s mappi ng of r om wi ndow to r om addr es s and other mi s cel l aneous contr ol s . bit bpr reset 7 m16en 0 6 bp15 0 5 bp14 0 4 bp13 0 3 0 2 0 1 soft1 0 0 soft0 0 bit 7: m16en , memory 16-bit enable s et m16e n to 1 to enable 16-bit memory acces s by the hos t. t his s hould be onl y s et when all interr upts have been di s abl ed. s ee page 1 7 for detai l s . bits 6-4: bp15-13 , rom offset r om addr es s i s cr eated by addi ng the contents of thi s fi el d to the di ffer ence between r om bas e ad- dr es s and the addr es s s uppl i ed on the s a1 9 - s a0 0 l i nes . t hi s s um s er ves as a movabl e page offs et into the r om window. i t is intended that the offs et be us ed only when the r om pr ovi ded i s l ar ger than the wi ndow s el ected. bits 1-0: soft1-soft0 t hes e bits are written and read by s oftware. t hey may be us ed as claim bits for allocation of drivers to multiple lan connections within a common back- pl ane. 5.1.7 icr - interrupt control register read/write port = 06 this register enables and masks interrupts. it is not us ed to s elect i r q lines . t hat function is per formed thr ough the gcr r egis ter. bit icr reset 7 mctest 0 6stag 0 5 i opav 0 4 iopen 0 3 sint 0 2 mask2 0 1 mask1 0 0 eil 0 bit 7: mctest , memory cache test bit t he memor y cache counter s ar e accel er ated when mct e s t =1. u s e this bit only for tes t purpos es . bit 6: stag , staggered address enable when s t ag = 1 , the l owes t bi t i n the buffer counter i s for ced to 1 on memor y cache mi s s es . bit 5: iopav , i/o pipe address visible when i opav = 1 , i t al l ows the i /o pi pes tempor ar y addr es s r egi s ter to be r ead out of the r e v r egi s ter. bit 4: iopen , i/o pipe enable w h en i op e n = 1 , th e i /o pi pe i s en abl ed. r egu l ar memory accesses should be disabled when this bit is set. bit 3: sint, software interrupt s et s int = 1 to create an interrupt under s oftware control. s et to z er o to remove i nter rupt. f or more details, refer to page 52. bit 2: mask2 , mask interrupt sources s et mas k 2 to 1 to mas k out interr upt from the ni c. bit 1: mask1 , not used bit 0: eil , enable interrupts s et to 1 to enable inter rupts from thi s device. t his enable controls s i nt and interr upts fr om the l an controller. for more details, refer to page 52.
5.1.8 rev/iopa - revision/i/o pipe address register read/write port = 07 t hi s r egi s ter s er ves two functi ons : 1. it provides the host with revision information about the chip (chip3-0 and rev3-0). 2. it provides a port for loading the i/o pipe address into the buffer counter. for more on this, see section 6.2. t he revision information is read-only and will be r etur ned on r eads to this locati on when the i opav bit (icr.5) is zero. t his information is detailed as follows : bit rev read reset 7 chip3 0 6 chip2 1 5 chip1 0 4 chip0 0 3 rev3 0 2 rev2 0 1 rev1 0 0 rev0 0 bits 7-4: chip3-chip0 , chip type depending on the condition of jumper 9, this field yields either 0100 or 0010. a value of 0100 indi- cates to the hos t that thi s is an 83C795 device; a val ue of 0 0 1 0 i ndi cates an 8 3 c7 9 0 devi ce. bits 3-0: rev3-rev0 , revision number t hes e bi ts i ni ti al i z e to the r evi s i on number of thi s chi p. when the i /o pi pe i s enabl ed C that i s , when i op e n i s s et (i cr .4) C the i /o pi pe addr es s i s l oaded i nto the buffer counter through this r egis ter. s i nce the buff er counter i s 1 6 - bi ts wi de, two cons ecuti ve wr ites ar e r equir ed to accompl is h this us ing this method. the first write, which contains the lower byte of the address, is stored in a temporary register. the second write, which contains the upper byte of the address, is then transferred, along with the contents of the temporary register, into the buffer counter. any hos t acces s to the chip between the fir s t and s econd writes will automatically res et the proces s . when i op av i s s et, the contents of the tempor ar y regis ter can be read from this location. bit iopa reset 7iopa7 0 6iopa6 0 5iopa5 1 4iopa4 0 3iopa3 0 2iopa2 0 1iopa1 1 0iopa0 0 bits 7-0: iopa7-iopa0 , i/o pipe address t hi s r egi s ter pr ovi des the l ocati on of the i /o p i pe addr es s . 5.1.9 lan0 - lan5 - lan address registers read/write ports = 08 - 0d s wh = 0 these six lan address registers (along with the bdid and chksum registers) recall or store gener al - pur pos e data fr om the e e r om and, dur i ng normal use, recall the permanently-assigned lan addr es s for the adapter. reg ln reset init recall lan0 ln07-ln00 0 ee ee lan1 ln15-ln08 0 ee ee lan2 ln23-ln16 0 ee ee lan3 ln31-ln24 0 ee ee lan4 ln39-ln32 0 ee ee lan5 lnmsb, ln46-ln40 0eeee bits 0-7: ln07-ln00 i n nor mal us e, thes e ar e the l eas t s i gni fi cant bi ts of the globally-assigned lan address block. bits 8-15: ln08-ln15 in normal use, ln8-ln15 are part of the globally as s i gned l an addr es s bl ock . bits 16-23: ln16-ln23 i n nor mal us e, l n16- l n23 ar e par t of the gl obal l y as s i gned l an addr es s bl ock .
bits 24-31: ln24-ln31 i n nor mal us e, l n24 - l n3 1 i s par t of the uni que l an addr es s for each adapter ( l n 4 7 - l n 2 4 ) and may be as s i gned at the ti me of manufactur e for the end pr oduct. bits 32-39: ln32-ln39 i n nor mal us e, l n32 - l n3 9 i s par t of the uni que l an addr es s for each adapter ( l n 4 7 - l n 2 4 ) and may be as s i gned at the ti me of manufactur e for the end pr oduct. bits 40-46: ln40-ln46 ln40-ln46 forms part of the unique lan addres s for each adapter ( l n 4 7 - l n 2 4 ) and may be as s i gned at the ti me of manufactur e for the end pr oduct. bit 47: lnmsb lnmsb is the most significant digit of the unique lan addres s block which compris es ln24 through ln47. 5.1.10 bdid - board id register read port = oe swh=0 t his register is similar to the lan registers except that i t contai ns an 8 - bi t code i denti fyi ng the boar d type for software purposes. t he administration of thi s i d byte i s beyond the s cope of thi s s peci fi cati on. t hi s r egi s ter i s s tor ed and r ecal l ed al ong wi th the lan registers. bit bdid reset init recall 7 bdid7 0 ee ee 6 bdid6 0 ee ee 5 bdid5 0 ee ee 4 bdid4 0 ee ee 3 bdid3 0 ee ee 2 bdid2 0 ee ee 1 bdid1 0 ee ee 0 bdid0 0 ee ee 5.1.11 cksm - checksum register read/write port = of s wh=0 before storing a lan address, cksm should be pr ogr ammed wi th an 8- bi t checks um whi ch caus es the 2s complement sum of all eight second-group r egi s ter contents to be f f h . t he s um mus t i ncl ude thi s r egi s ter. t hi s r egi s ter i s s tor ed and r ecal l ed al ong wi th the l an r egi s ter s . i t i s r ecommended that on r ecal l of the l an addr es s , the r egi s ter s i ntegr i ty s houl d be confi r med by computi ng ( i n s oftwar e) the checks um of the s econd gr oup of r egi s ter s . bit cksm reset init recall 7 chk7 1 ee ee 6 chk6 1 ee ee 5 chk5 1 ee ee 4 chk4 1 ee ee 3 chk3 1 ee ee 2 chk2 1 ee ee 1 chk1 1 ee ee 0 chk0 1 ee ee bits 7-0: chk7-chk0 , checksum register t he 83 c7 9 5 s tor es the checks um amount i n thi s register for reference and comparison with the lan registers amounts. 5.1.12 gcr2 - general control register 2 read/write ports = 08 s wh=1 t his register is used to hold general control information. bit gcr2 reset init 7 0 0 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 pnpiop 0 0 bit 0: pnpiop, pnp and i/o mapped pipe t his bit is us ed to communicate to the p lug and p l ay l ogi c that the adapter us es the i /o-mapped mode. when pnpiop = 1, the plug and play ram control r egi s ter s ar e di s abl ed and the r om contr ol r egi s - ters are moved from 48hC4ch to 40hC44h. 5.1.13 iar - i/o address register read/write port = 0a s wh=1 this register programs the base i/o address for the chi p.
bit iar reset init 7 ia15 0 0 6 ia14 0 0 5 ia13 0 0 4ia8 0 0 3ia7 1 1 2ia6 0 0 1ia5 0 0 0 pnpboot 0 0 bits 7-5: ia15-ia13 , i/o addr ess lines t hes e bi ts ar e compar ed agai ns t the a15-a13 l i nes fr om the hos t when i or or i ow ar e acti ve and ae n is not. to access the chip, the lines must match. bits 4-1: ia8-ia5 , i/o address lines t hes e bi ts ar e compar ed agai ns t the a8 - 5 l i nes fr om the hos t when i or or i ow ar e acti ve and ae n is not. to access the chip, the lines must match. bit 0: pnpboot, plug and play boot bit pnpboot = 1 to indicate to the plug and play hardware that the adapter i s a boot car d. t his allows the 83C795 addr es s decoders to be acti ve wi thout wai ti ng for the p l ug and p l ay har dwar e activate command. 5.1.14 rar - ram address register read/write port = ob s wh=1 t hi s r egi s ter contr ol s the bas e addr es s and wi ndow s iz e for the buffer r am. bit rar reset init 7 hram 0 0 6 ra17 0 0 5 ramsz1 0 0 4 ramsz0 0 0 3 ra16 0 0 2 ra15 1 1 1 ra14 0 0 0 ra13 0 0 bit 7: hram , high ram address t hi s bi t pr ovi des a means of l ocati ng the buffer memor y above the 1mb dos l i mi t. when h r am = 0 , the buff er addr es s decoder matches l a2 3 - l a2 0 agai ns t z ero. when h r am = 1, the l a23-l a20 l i nes ar e matched agai ns t the val ue f . t hi s fi el d i s not s upported by the p lug and p lay har dwar e. bits 5-4: ramsz1-ramsz0 , buffer window size field t hi s encoded f i el d deter mi nes the appar ent s i z e of the buffer r am. i t i s decoded i n the f ol l owi ng man- ner: sz1 sz0 window size 0 0 8k bytes 0 1 16k bytes 1 0 32k bytes 1 1 64k bytes table 5-5. buffer window size field bits 6, 3-0: ra17, ra16-ra13 , ram base address field t hes e bi ts for m par t of the bas e addr es s for the buffer r am decoder al ong with the fix ed value of 11 for ra19-ra18. when s a19-s a13 has a value between this bas e addres s and the bas e pl us the wi ndow s i z e, the r eques t for memor y i s r ecogni z ed. once the s a1 9 -s a1 3 val ue i s no l onger i n thi s r ange, the hos t ends the acces s . note the 64k window size is not supported by plug and play. 5.1.15 bio - rom control register read/write port = 0c s wh = 1 this register programs the base address and window s iz e for the external r om. bit bio reset init recall 7 fine16 0 0 ee 6 ba17 0 0 ee 5 biosz1 1 1 ee 4 biosz0 1 1 ee 3 ba16 0 0 ee 2 ba15 0 0 ee 1 ba14 0 0 ee 0 ba13 0 0 ee
bit 7: fine16 , fine decode when fine16 = 1, mem16css response is gen- er ated onl y when the actual r am wi ndow i s bei ng addr es s ed. i t i ncl udes s a16 - s a13 i n the addr es s decodi ng pr oces s . s ee page 5 1 for mor e detai l s . bits 5-4: biosz1-biosz0 , rom window size field t hes e two bits determi ne the r om window s i z e and ar e decoded i n thi s manner : sz1 sz0 rom window size 00 8k 0 1 16k 1 0 32k 1 1 disabled table 5-6. rom window size field bits 6, 3-0: ba17, ba16-ba13 , base address field t hes e bi ts for m par t of the bas e addr es s for the r om decoder al ong wi th the fi x ed val ue of 11 for ba19-ba18. when s a19-s a13 has a value be- tween thi s bas e addr es s and the bas e pl us the wi ndow s i z e and s me mr ar e acti ve, a r eques t for the r om i s r ecogni z ed. a chi p s el ect wi l l be gener - ated to the r om if not dis abled. memory acces s at the s ame addr es s i s bl ock ed i f r om i s enabl ed. 5.1.16 gcr - general control register read/write port = od s wh = 1 t his register controls interrupt level selection, zero wait state response, and several other functions. bit gcr reset init recall 7 xlength 0 0 ee 6 ir2 0 0 ee 5 zwsen 0 0 ee 4ripl 0 0ee 3 ir1 0 0 ee 2 ir0 0 0 ee 1gpout0 0ee 0lit 0 0ee bit 7: xlength , extended length bit enable when x l e ngt h = 1, the extended l ength opti on i s enabl ed as s peci fi ed by the 802 .3 s peci fi cati on (r efer to page 69). bit 5: zwsen , zero wait state enable t his bit i s s et to 1 to enabl e the chip to generate a z ws r es pons e when the r am i s acces s ed and avai l abl e to the hos t. bit 4: ripl , software flag bits 6, 3-2: ir2-ir0 , interrupt request field t hes e bits form an encoded field to s elect through which i r q pin the i nter rupt output i s channeled. because of plug and play logic, it is necessary to connect the interr upt pins to s pecifi c lines on the i s a bus , as s hown bel ow. t he i nter r upt r eques t pi ns and their cor r es pondi ng i s a l i nes ar e decoded i n this fas hion: irq2 irq1 irq0 irq pin selected isa bus line 0 0 0 none none 0 0 1 irq1 irq2/9 0 1 0 irq2 irq3 0 1 1 irq3 irq5 1 0 0 irq4 irq7 1 0 1 irq5 irq10 1 1 0 irq6 irq11 1 1 1 irq7 irq15 table 5-7. interrupt request field bit 1: gpout , general purpose output t his bit controls the gpout pin of the chip. when gp ou t = 1, i t caus es the gp ou t pi n to dr i ve l ow. in some systems, this bit is wired to a shutdown contr ol i nput f or dc/dc i s ol ated power s uppl y us ed in 10base2 applications. for more information on this featur e, refer to s ection 6.7. bit 0: lit , link integrity test t his bit controls the link integrity test. in s tar- lan-10 networks, the link integrity tes t s hould be di s abl ed. lit = 0 - link test is disabled lit = 1 - link test is enabled.
dis abling the l ink i ntegrity t es t (l i t ) for ces the 83C795 to s elect the twis ted-pair interface. when lit is enabled, the twisted-pair interface will be automatically s elected when li nk activity is found and the au i i nter face wi l l be s el ected when the twis ted-pair link enters the 10b as e -t link fail s tate. 5.1.17 erfal - early receive fail address low register read/write port = oe s wh = 1 t hi s r egi s ter contai ns the l ower ei ght bi ts for the addr es s at whi ch the ear ly-r ecei ve l ogi c detected an under r un. t hi s r egi s ter al s o contai ns a contr ol bit for the plug and play logic. bit erfal reset recall 7 erfa7 6 erfa6 5 erfa5 4 erfa4 3 erfa3 2 erfa2 1 0 0 0 pnpen 1 ee bits 7-2: erfa7-2 , early receive failure address t his r egis ter contai ns the lower ei ght bits of the addr es s wher e the ear l y r ecei ve l ogi c detected an underrun. t he comparis on has a granularity of 4 bytes s o the leas t s ignificant two bits are z er o. t his value is read-only. bit 0: pnpen , plug and play enable when pnpen = 1 along with the installation of jumper6, plug and play logic is enabled. t his bit i s r eadabl e but can only be s et by the i ni ti al e e r om load. 5.1.18 erfah - early receive fail address high register read/write port = of s wh = 1 t hi s r egi s ter contai ns the hi gher ei ght bi ts for the addr es s at whi ch the ear l y r ecei ve l ogi c detected an underrun. bit erfah reset recall 7 erfa15 6 erfa14 5 erfa13 4 erfa12 3 erfa11 2 erfa10 1 erfa09 0 erfa08 bits 7-0: erfa15-8 , early receive failure address t hi s r egi s ter contai ns the hi gher ei ght bi ts of the addr es s wher e the ear l y r ecei ve l ogi c detected an underrun.
5.2 lan controller register descriptions t o s i mpl i fy the pr ogr ammi ng model f or the l an controller and r etain compatibili ty wi th the s mc 83c690 lan controller, the internal registers are di vi ded i nto two addr es s maps . t he defaul t addr es s map is us ed for r ing-s tyle buffering (like the 83c690). t hos e registers needed for linked-list buffer i ng ar e gr ouped together i n the al ter nate addr es s map and ar e enabl ed thr ough the e nhancement (e nh ) r egi s ter des cr i bed s tar ti ng on page 26. e ach map pr ov i des acces s t o al l r egi s t er s necessary for operating that particular buffering mode. many r egi s ter s ar e vi s i bl e i n both maps , al though not al ways at the s ame addr es s i n each. t o facilitate manufacturing tes t of the device, many i nter nal r egi s ter s can be acces s ed i n one or both of thes e maps . wi thin each map, the r egis ter s are or gani z ed i nto 4 pages of 1 6 r egi s ter s each. onl y one page is visible at a time. page selection is made thr ough the command (cmd) regis ter des cr ibed starting on page 24. t he addr es s es l i s ted i n thi s s peci fi cati on ar e i n an abbr evi ated for m. t he fir s t hex di gi t i s r eal ly a two-bi t page val ue which is wri tten into the l an command (cmd) register to access the 16 registers visible for that page. the digits after the colon are the offs et within the 83C795s l an contr ol l er i /o s egment i n thi s manner : page : offset t o deter mi ne the cor r ect addr es s , you mus t fi r s t know the 83C795s base address then select the cor r ect page and fi nal l y s el ect the cor r ect off s et. s o, for example, "3:1c" indicates that the address for this particular register is found on page 3 at the offs et value 1c. i n the fol lowing des cri ptions , the mos t s i gnificant bit pos i ti on i s number ed 7 . t he l i ne l abel l ed r e s e t s hows the i ni ti al val ues l oaded i nto the r egi s ter by as s er ti on of the r e s e t pi n. t he s ymbol 0 denotes void bits which always return zero when read. 5.2.1 alicnt - alignment error counter register normal map read port = 0:1d link-list map read port = 0:1d t hi s r egi s ter i s the al i gnment er r or counter. i t i s i ncr emented by the r ecei ve uni t when a packet i s r ecei ved wi th a fr ame al i gnment er r or. onl y packets whos e addr es s es ar e r ecogni z ed wi l l be i ncl uded in this tally. t he counter will increment to 255 and s top i f addi ti onal al i gnment er r or s ar e detected. t he counter i s cl ear ed when r ead. bit alicnt reset 7 ct7 0 6 ct6 0 5 ct5 0 4 ct4 0 3 ct3 0 2 ct2 0 1 ct1 0 0 ct0 0 5.2.2 bound - receive boundary page register n or mal map r ead/w r i te p or t = 0 : 1 3 the receive boundary page register points to the ol des t us ed r ecei ve buffer i n the r i ng. i t i s us ed to pr event over fl ow i n the buffer r i ng. t he dma compar es the contents of thi s r egi s ter to the nex t buffer addr es s when l i nk i ng buffer s together for s tor age of a r ecei ved fr ame. i f the contents match the nex t buffer addr es s , the dma oper ati on i s aborted. only a08-a15 are s pecified since all buffer s ar e al i gned on 256 - byte boundar i es . f or more information, refer to page 85. bit bound reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x
5.2.3 cmd - command register n or mal map r ead/w r i te p or t = x : 1 0 l i nk ed- l i s t map r ead/wr i te p or t = x : 1 0 bit cmd reset 7 ps1 0 6 ps0 0 5 rfu 0 4 enetch 0 3 disetch 0 2 txp 0 1sta 0 0 stp 1 t he command r egi s ter i s us ed to i ni ti al i z e the 83C795 chip, s tart transmis sions , and s witch pages . bits 7-6: ps1-ps0 , page select t hi s 2 - bi t f i el d des i gnates whi ch of 4 pages i s s howi ng. t hey decode as f ol l ows : ps1 ps0 page select 00page 1 10page 2 01page 3 11page 4 table 5-8. page select field bit 5: rfu, reserved for future use t his bit is not us ed by 83C795 and always returns zero when read. bit 4: enetch , enable early transmit checking b y s etting this bit to 1, i t enables compar is on of transmit dma address against the host memory wr i te addr es s . once s et, thi s bi t can be cl ear ed and the 83C795 conti nues to check tr ans mis s ion ad- dresses until disetch is set. see page 78 for more details. bit 3: disetch , disable early transmit checking b y s etti ng this bit to 1, it dis ables the early trans mit addr es s checking. once s et, the bi t can be cl ear ed and transmit address checking is suppressed until enetch is set. see page 78 for more details. bit 2: txp , transmit packet s et thi s bi t after l oadi ng the t r ans mi t b uffer and control regis ters to initi ate trans mis s ion of a packet. t he 83C795 clears this bit upon completi on or abor ti on of the tr ans mi s s i on. bit 1: sta , start bit s et the s t a bit to activate the 83C795 after power up or when the 83C795 has been res et by a soft- ware command. no frames can be s ent or received until this bit has been set. the users software should set up the other registers prior to bringing the devi ce on li ne, but s etting this bi t is the actual command whi ch br i ngs the t r ans mi t and r ecei ve por ti ons of the devi ce onl i ne. once s et, thi s bi t may be cl ear ed and the 8 3 c7 9 5 wi l l conti nue to r emai n online. bit 0: stp , stop bit s et the s t p bi t to take the chip offline and dis en- gage fr om the l an. f r ames par ti al l y tr ans mi tted or received are completed before reset occurs. int - stat.rst is set high when the transmit and re- ceive s ection have completed all outs tanding oper ati ons (s ee page 28). no fr ames wi l l be r e- ceived or trans mitted until the s tar t bit has been s et. 5.2.4 colcnt - collision count register n or mal map r ead p or t = 0 : 1 5 l i nk ed- l i s t map r ead p or t = 0 : 1 5 t hi s r egi s ter contai ns the number of col l i s i ons detected while attempti ng to tr ans mi t the curr ent (or mos t r ecent) packet. i t is cleared to z ero at the s tar t of transmission. if no collisions are detected, the counter will read zero. f or each collis ion encountered, the count is incr emented. i f more than 1 5 col l i s i ons occur , the abor t bi t of t s t at i s s et and the count is res et to z ero (s ee page 38). bit colcnt reset 7 t10 0 6t9 0 5t8 0 4t7 0 3 ct3 0 2 ct2 0 1 ct1 0 0 ct0 0 bits 7-4: t10-t7 , backoff counter t hes e 4 cons ecuti ve bi ts al ways r etur n z er o.
bits 3-0: ct3-ct0 , collision counter t hes e bits indicate the value of the collis ion counter . t hey ar e al ways r eadabl e. 5.2.5 crccnt - crc error counter n or mal map r ead p or t = 0 : 1 e l i nk ed- l i s t map r ead p or t = 0 : 1 e t hi s r egi s ter i s i ncr emented by the r ecei ve uni t when a pack et i s r ecei ved wi th a cr c er r or. onl y packets whos e addres s is recognized will be included in this tall y. when a r unt fr ame is received wi th a cr c er r or, cr ccnt i s incr emented i f r con. r u nt s i s enabl ed (s ee page 32 ). t he counter will increment to 255 and s tick if additional cr c er r or s ar e detected. t he counter i s cl ear ed when r ead. bit crccnt reset 7 ct7 0 6 ct6 0 5 ct5 0 4 ct4 0 3 ct3 0 2 ct2 0 1 ct1 0 0 ct0 0 5.2.6 curr - current frame buffer pointer register n or mal map r ead/w r i te p or t = 1 : 1 7 t his regis ter points to the firs t buffer us ed for s tor age of the pr es ent fr ame. i t i s us ed by dma as a back up addr es s for r ecover i ng buffer s i n cas e of a flawed packet and facilitates s torage of buffer h eader i n f or mat i on. t h e cu r r r egi s t er s h oul d be i ni ti al i z ed to the s ame val ue as r s t ar t (s ee page 33) and not al ter ed ther eafter by the us er unl es s the controller is reset. only a08-a15 are specified s i nce al l buffer s ar e al i gned on 2 5 6 - byte boundar i es . bit curr reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.7 currh - current frame buffer descriptor pointer register high l i nk ed- l i s t map r ead/wr i te p or t = 1 : 1 7 t hi s r egi s ter i s one of a pai r of r egi s ter s (cu r r h and cu r r l ) that poi nt to the fir s t buffer des cr iptor us ed for s tor age of the pr es ent fr ame. t hey ar e us ed by dma as a back up addr es s f or r ecover i ng buffer s i n the cas e of a fl awed pack et and to facilitate storage of buffer header information. neither the currh nor currl registers should be al ter ed by the us er. t hey ar e acces s i bl e for tes t pur pos es onl y. bit currh reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.8 currl - current frame buffer descriptor pointer register low l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 3 t hi s r egi s ter i s one of a pai r of r egi s ter s (cu r r h and cu r r l ) that poi nt to the fir s t buffer des cr iptor us ed for s tor age of the pr es ent fr ame. t hey ar e us ed by dma as a back up addr es s f or r ecover i ng buffer s i n the cas e of a fl awed pack et and to facilitate storage of buffer header information. neither the currh nor currl registers should be al ter ed by the us er. t hey ar e acces s i bl e for tes t pur pos es onl y.
bit currl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x 5.2.9 dcon - data configuration register l inked-l i s t map r ead p or t = 2:1e l inked-l is t map write port = 0:1e t his r egis ter always returns 41h. i n the 83c790 this regis ter controlled dma burs t lengths ; however, the 83C795 is hardwired for 8-byte bursts. refer to page 65 for more information. 5.2.10 enh - enhancement register n or mal map r ead/w r i te p or t = 2 : 1 7 l i nk ed- l i s t map r ead/wr i te p or t = 2 : 1 7 t hi s r egi s ter enabl es enhancement featur es . bit enh reset 7 0 6 1 5 altego 0 4 slot1 0 3 slot0 0 2 eotint 0 1 0 0 sback 0 bits 7-6: unused bit 5: altego , buffering format selection altego = 0 - des i gnates r i ng buff er i ng and s i ngl e f r ame tr ans - mission format. t his is essentially 8390/83c690 compatibility mode. altego = 1 - des i gnates l i nked-l i s t r ecei ve buffer i ng and mul ti - pl e fr ame tr ans mi s s i on f or mat. t he r egi s ter ad- dr es s map i s s el ected wi th thi s bi t, ex pos i ng the r egi s ter s as s oci ated wi th the s el ected buffer i ng mode. bits 4-3: slot1-0 , slot time selection t his two-bit field s elects the s lot ti me according to table 5-10. slot1 slot0 slot time 0 x 512 bit times (ethernet) 1 0 256 bit times 1 1 1024 bit times table 5-9. slot time selection field bit 2: eotint , interrupt on end-of-transmit eotint = 1 - i nter rupt on e nd-of-t r ans mi t chain ins tead of each tr ans mi tted fr ame. t his bit is ignored if not operati ng in multiple frame transmission mode. eotint = 0 - i nter rupt on each tr ans mi tted fr ame. bit 0: sback , enable stop backup modifications sback = 1 - e nabl e the s top b ackoff modi fications to the back- off timer. sback = 0 - normal backoff. 5.2.11 erwcnt - early receive warning threshold register n or mal map r ead/w r i te p or t = 0 : 1 8 l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 8 t h i s r egi s t er con tai n s t he r ecei v ed b y te cou n t threshold at which the e arly receive warning interrupt is generated. t he e rw interrupt is gener ated when r b c 3 e rw. bits 3-0 of rbc are ignored. f or more information on this register, refer to page 71.
bit erwcnt reset 7 erw11 0 6 erw10 0 5 erw9 0 4 erw8 0 3 erw7 0 2 erw6 0 1 erw5 0 0 erw4 0 5.2.12 group0-group7 - multicast filter table registers group register normal map port address linked-list map port address read write read write group0 1:18 1:18 1:18 1:18 group1 1:19 1:19 1:19 1:19 group2 1:1a 1:1a 1:1a 1:1a group3 1:1b 1:1b 1:1b 1:1b group4 1:1c 1:1c 1:1c 1:1c group5 1:1d 1:1d 1:1d 1:1d group6 1:1e 1:1e 1:1e 1:1e group7 1:1f 1:1f 1:1f 1:1f t hes e 8 r egi s ter s hol d the nodes mul ti cas t fi l ter table. s ee table 5-10 for the registers bit as s i gnments . 5.2.13 intmask - interrupt mask register n or mal map r ead p or t = 2 : 1 f n or mal map wr i te port = 0:1f linked-list map read port = 2:1f linked-list write port = 0:1f t he i nter rupt mas k r egis ter is us ed to mas k out certain interrupt sources selectively. mask bits set to 1 all ow the cor res ponding interr upts to caus e an i r q. mas k bits s et to 0 block their res pecti ve inter rupt s our ces . bit intmask reset 7 0 6 erwe 0 5 cnte 0 4ovwe 0 3 txee 0 2 rxee 0 1 ptxe 0 0 prxe 0 bit 6: erwe , early receive warning enable when e r we = 1, this bit enables e arly r eceive war ni ng as def i ned by the e r w bi t i n the i nter r upt s tatus r egi s ter. (s ee the nex t r egi s ter, i nt s t at .) bit 5: cnte , counter overflow enable when cnt e = 1, this bi t enabl es counter over flow as defined by the cnt bit in the interrupt s tatus r egi s ter. (s ee the nex t r egi s ter, i nt s t at .) bit 4: ovwe , overwrite warning enable when ovwe = 1, this bit enables overwrite warn- ing as defined by the ovw bi t in the i nterr upt s tatus r egi s ter. (s ee the nex t r egi s ter, i nt s t at .) group registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 group0 ga07 ga06 ga05 ga04 ga03 ga02 ga01 ga00 group1 ga15 ga14 ga13 ga12 ga11 ga10 ga09 ga08 group2 ga23 ga22 ga21 ga20 ga19 ga18 ga17 ga16 group3 ga31 ga30 ga29 ga28 ga27 ga26 ga25 ga24 group4 ga39 ga38 ga37 ga36 ga35 ga34 ga33 ga32 group5 ga47 ga46 ga45 ga44 ga43 ga42 ga41 ga40 group6 ga55 ga54 ga53 ga52 ga51 ga50 ga49 ga48 group7 ga63 ga62 ga61 ga60 ga59 ga58 ga57 ga56 table 5-10. group register bits
bit 3: txee , transmit error enable when txee = 1, this bit enables transmit error as defi ned by the t x e bi t i n the i nter r upt s tatus r eg- i s ter. (s ee the nex t r egi s ter, i nt s t at .) bit 2: rxee , receive error enable when rxee = 1, this bit enables receive error as defined by the r x e bit in the i nterrupt s tatus r eg- i s ter. (s ee the nex t r egi s ter, i nt s t at .) bit 1: ptxe , packet transmitted enable when t xe e = 1, this bit enables packet t rans mit- ted as defined by the p t x bi t i n the i nter rupt s tatus r egi s ter. (s ee the nex t r egi s ter, i nt s t at .) bit 0: prxe , packet received enable when p r x e = 1, thi s bi t enabl es p ack et r ecei ved as defined by the p r x e bi t in the i nterr upt s tatus r egi s ter. (s ee the nex t r egi s ter, i nt s t at .) 5.2.14 intstat - interrupt status register n or mal map r ead/w r i te p or t = 0 : 1 7 l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 7 t he i nter r upt s tatus r egi s ter enabl es the hos t to determi ne the caus e of an i nter rupt and to eval uate pending or mas ked interrupts . masked-out inter rupts ar e vi s i bl e in this regis ter although they will not generate an ir q to the hos t. p ending interrupts can be cleared by writing 1 to the as s oci ated bi t of thi s r egi s ter. t he i r q s i gnal i s acti ve as l ong as any unmas k ed i nter r upt bi t remains set. for more details, see page 80. bit intstat reset 7 rst 1 6 erw 0 5 cnt 0 4ovw 0 3 txe 0 2 rxe 0 1 ptx 0 0 prx 0 bit 7: rst , reset status t his bit is set by 83C795 when its t ransmit and receive sections are stopped in response to the as s er ti on of the r e s e t pi n or the s etti ng of the cmd. s t p bi t. t he r s t bi t does not gener ate an inter rupt. bit 6: erw , early receive warning when this bi t is s et it indicates that the number of bytes r ecei ved i n the cur r ent fr ame has ex ceeded the pr ogr ammabl e l i mi t of the e r wcnt r egi s ter . bit 5: cnt , counter overflow when this bi t i s s et it i ndicates that the ms b of one or mor e networ k er r or counter s has been s et. bit 4: ovw , overwrite warning t hi s bi t i s s et when the r ecei ve dma mus t abor t fr ame r ecepti on due to a l ack of r ecei ve buffer s . bit 3: txe , transmit error t his bit is set when excessive collisions, out-of-win- dow collisions, fifo underrun, or early transmit addr es s vi ol ati ons pr event tr ans mi s s i on of a pack et. bit 2: rxe , receive error t his bit is s et when a packet is r eceived with one or mor e of the fol l owi ng er r or s : crc error (happens when sep is enabled) frame alignment error (happens when sep is enabled) fifo overrun missed packet (monitor mode) t hi s i nter r upt wi l l not be pos ted i f a dma abor t occurs , a condition indicated by the as s ertion of an ovw interrupt. if rxe is previously set, it will not be changed due to ovw. bit 1: ptx , packet transmitted this bit is set when a packet is transmitted success- ful l y. when the bi t e nh . e ot i nt i s s et i n mul ti pl e p acket t r ans mi t mode (s ee page 5 -26), s etti ng of this interr upt is deferr ed until the entir e trans mit chai n has been pr oces s ed. p t x i s then s et i f any packet in the chain was tr ans mitted s ucces s ful ly, or if a zero length transmit chain was processed. bit 0: prx , packet received when p r x = 1 , i t i ndi cates that a pack et was received with no errors.
5.2.15 manch - manchester management register n or mal map r ead/w r i te p or t = 3 : 1 f l i nk ed- l i s t map r ead/wr i te p or t = 3 : 1 f t h i s r egi s ter al l ows the r eadi ng back of the 1 0 b as et s tatus l e d dr i ver s to s uppor t networ k and s tati on management functi ons . i t al s o enabl es and contr ols the 83C795s internal manches ter encoder /decoder. bit manch reset 7 mandis 0 6 sel 1 50 0 4 enapol 1 3 pled 0 2 lled 0 1 rled 0 0 tled 0 bit 7: mandis , manchester disable mandi s = 1 - dis ables the internal manches ter e ncoder /decoder . when di s abl ed, the l an con- tr oller us es the decoder s eri al i nter face cons is ti ng of these lines: xt xd, xt xe, xt xc, xrxd, xrxc, x cr s , x col , x l oop. mandi s = 0 - e nabl es the manches ter e ncoder /d ecoder . bit 6: sel , select aui mode for idle state s e l = 0 - t x+ is pos itive in relation to t x-. s e l = 1 - t x+ = t x-. bit 4: enapol , automatic polarity correct e nap ol = 1 - e nabl e auto p olari ty corr ect e nap ol = 0 - dis able auto p olar ity corr ect bit 3: pled , tprx polarity led readback when pl e d = 1, this l e d is on. note there is no pled pin onto which this signal might be driven. bit 2: lled , link status led readback when lled = 1, this led is on (output sinking cur r ent) . bit 1: rled , receive led readback when rled = 1, this led is on (output sinking cur r ent) . bit 0: tled , transmit led readback when tled = 1, this led is on (output sinking cur r ent) . 5.2.16 mpcnt - missed packet error counter register normal map read port = 0:1f linked-list map read port = 0:1f t hi s r egi s ter i s i ncr emented by the r ecei ve uni t whenever i t cannot r ecei ve a pack et due to a l ack of r ecei ve buffer s , r ecei ve f i f o over fl ow, or becaus e the r ecei ver i s i n moni tor mode. onl y packets whos e addres s is recognized will be included in this tally. t he counter will increment to 2 5 5 and s ti ck i f addi ti onal pack ets ar e mi s s ed. t he counter i s cl ear ed when r ead. bit mpcnt reset 7 ct7 0 6 ct6 0 5 ct5 0 4 ct4 0 3 ct3 0 2 ct2 0 1 ct1 0 0 ct0 0
5.2.17 next - dma controller next buffer register n or mal map r ead/w r i te p or t = 2 : 1 5 t hi s i s a wor k i ng r egi s ter of the d ma contr ol l er. i t holds a pointer to the next buffer to be opened. bit next reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.18 raddh - receive burst starting address high register n or mal map r ead/w r i te p or t = 2 : 1 9 t hi s i s the hi gher 8 bi ts of a r egi s ter pair us ed inter nall y by the dma contr oller as a s cratch pad for the bur s t addr es s of the r ecei ve pr oces s . wr i ti ng to the r addh and r addl regis ters while communi cati on i s tak i ng pl ace may caus e er r or s i n the dma pr oces s . bit raddh reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.19 raddl - receive burst starting address low register n or mal map r ead/w r i te p or t = 2 : 1 8 this is the lower 8 bits of a register pair used inter nall y by the dma contr oller as a s cratch pad for the bur s t addr es s of the r ecei ve pr oces s . wr i ti ng to the r addh and r addl regis ters while communi cati on i s tak i ng pl ace may caus e er r or s i n the dma pr oces s . bit raddl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x 5.2.20 rbegin - receive buffer starting address register l inked-l is t map r ead p ort = 2:11 l inked-l is t map write p ort = 0:11 t his r egi s ter holds the upper 8 bi ts of the s tarti ng addr es s of the r ecei ve buffer des cr i ptor tabl e. t he l ower 8 bi ts ar e as s umed to be z er o. bit rbegin reset 7 rb15 x 6 rb14 x 5 rb13 x 4 rb12 x 3 rb11 x 2 rb10 x 1 rb09 x 0 rb08 x
5.2.21 rcnth - receive byte count high register n or mal map r ead p or t = 0 : 1 b t his regis ter contains the upper 8 bi ts of the recei ve u n i ts cou n t of by t es r ecei v ed i n th e mos t r ecen t fr ame. i t i s cl ear ed by the r ecei ve uni t at the s tar t of reception. bit rcnth reset 7 ct15 0 6 ct14 0 5 ct13 0 4 ct12 0 3 ct11 0 2 ct10 0 1 ct09 0 0 ct08 0 5.2.22 rcntl - receive byte count low register n or mal map r ead p or t = 0 : 1 a t his regis ter contai ns the lower 8 bi ts of the recei ve u n i ts cou n t of by t es r ecei v ed i n th e mos t r ecen t fr ame. i t i s cl ear ed by the r ecei ve uni t at the s tar t of reception. bit rcntl reset 7 ct07 0 6 ct06 0 5 ct05 0 4 ct04 0 3 ct03 0 2 ct02 0 1 ct01 0 0 ct00 0 5.2.23 rcon - receive configuration register normal map r ead p ort = 2:1c normal map write port = 0:1c l i nk ed- l i s t map r ead p or t = 2 : 1 c l i nk ed- l i s t map write port = 0:1c t he r ecei ve confi gur ati on r egi s ter defi nes opti onal behavi or of the r ecei ve uni t. i t contr ol s addr es s r ecogn i ti on and the acceptan ce of abnor mal pack ets . t hes e bi ts can be s et independently, although the monitor mode takes pr ecedence over the other bi ts . bit rcon reset 70 0 6 rca 0 5mon 0 4 prom 0 3 group 0 2 broad 0 1 runts 0 0 sep 0 bit 7: unused t his bit is unus ed in 83C795. when read, it always returns zero. bit 6: rca , receive abort frame on collision s etti ng this bit allows the receiver unit to abor t r ecepti on of any fr ame i n whi ch the col pi n i s acti ve after the s tar t of f r ame del i mi ter. r ecepti on of any fr ame whos e pr efi x contai ns cons ecuti ve 0 bits is also aborted. neither cause results in rxe bei ng s et. i t i s not over r i dden by the s e p bi t. t hi s bit was unus ed in the 83c690. bit 5: mon , check addresses/crc without buffering mon = 1 - t his bi t enables the r eceive unit to check addr es s es and cr c on i ncomi ng pack ets wi thout buffer i ng them to memor y. t he mi s s ed p ack et counter (mp cnt ) wi l l be i ncr emented for each recognized packet. mon = 0 - t his is normal operation. bit 4: prom , promiscuous reception when p r om = 1, this bi t enables promi s cuous r ecepti on of al l fr ames havi ng i ndi vi dual addr es s es .
bit 3: group , receive multicast frames when gr ou p = 1 , thi s bi t enabl es r ecepti on of al l frames that: have multicast addresses pass the multicast address hashing filter bit 2: broad , receive broadcast frames when b r oad = 1 , thi s bi t enabl es r ecepti on of al l fr ames havi ng a b r oadcas t ( al l 1 s ) des ti nati on addr es s . bit 1: runts , receive runts frames when r u nt s = 1, this bi t all ows r eception of fr ames havi ng l es s than 6 4 bytes , pr ovi ded that they other wi s e meet the r equir ements of the 802 .3 pr otocol . bit 0: sep , save errored packets when s e p = 1, i t di r ects the r ecei ve uni t to s ave pack ets havi ng cr c or fr ame al i gnment er r or s i n the buffer s . 5.2.24 rdownh - buffer room remaining high register l i nk ed- l i s t map r ead/wr i te p or t = 2 : 1 9 t his register contains the upper 8 bits of a register pai r us ed by the dma contr ol l er as a s cr atch pad for the buffer room remaining count during the r ecepti on pr oces s . note writing to these registers while commu- nication is taking place may cause er- rors in the dma process. bit rdownh reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.25 rdownl - buffer room remaining low register l i nk ed- l i s t map r ead/wr i te p or t = 2 : 1 8 t hi s r egi s ter contai ns the l ower 8 bi ts of a r egi s ter pai r us ed by the dma contr ol l er as a s cr atch pad for the buffer room remaining count during the r ecepti on pr oces s . note writing to these registers while commu- nication is taking place may cause er- rors in the dma process. bit rdownl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x 5.2.26 rend - receive buffer end register l inked-l is t map r ead p ort = 2:12 l inked-l is t map write port = 0:12 t hi s r egi s ter hol ds the upper 8 bi ts of the fi r s t addr es s beyond the end of the r ecei ve buffer des cr i ptor tabl e. t he l ower 8 bi ts ar e as s umed to be z er o. t he tabl e l i es between the number s (r b e gin * 256) and (r e nd * 256 - 1). r efer to page 88 for more details . bit rend reset 7 re15 x 6 re14 x 5 re13 x 4 re12 x 3 re11 x 2 re10 x 1 re9 x 0 re8 x
5.2.27 rstart - receive start page register normal map read port = 2:11 normal map write port = 0:11 r ecei ve s tar t p age regis ter points to the s tar t of the r ecei ve buffer r i ng. only a08 - a15 ar e s peci fi ed s i nce al l buffer s ar e al i gned on 2 5 6 - byte boundaries. refer to page 88 for more information. bit rstart reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.28 rstat - receive packet status register normal map read port = 0:1c linked-list map read port = 0:1c t hi s r egi s ter r epor ts the s tatus of the mos t-r ecently received packet. it categorizes any errors that were detected and r epor ts on the type of addr es s r ecogni z ed. al l bi ts ar e cl ear ed at the s tar t of r ecepti on ex cept for di s . bit rstat reset 7 drf 0 6dis 0 5 group 0 4mpa 0 3 over 0 2fae 0 1 crc 0 0 prx 0 bit 7: dfr , deferring igsm t hi s bi t i s s et when the i nter fr ame gap s tate ma- chine (igsm) is deferring. if the transceiver has asserted the cd line as a result of jabber, this bit will stay set indicating the jabber condition. bit 6: dis , receiver disabled t his bit is set when the receiver is in monitor mode. i t i s cl ear ed when the r ecei ver l eaves moni tor mode. bit 5: group , group address recognized t his bi t is s et when the r ecogniz ed addr es s was ei ther a gr oup addr es s (mul ti cas t) or br oadcas t. i t i s cl ear ed to i ndi cate an i ndi vi dual (phys i cal ) ad- dress match. bit 4: mpa , missed packet t his bit i s s et when a packet intended for this s tati on cannot be accepted by the devi ce due to a l ack of receive buffers or becaus e the device is in monitor mode. t he mi s s ed p ack et counter (mp cnt ) i s al s o i ncr emented when thi s occur s . bit 3: over , fifo overrun t his bit i s s et when the r eceiver attempts to wr ite i nto a f i f o that i s al r eady ful l . t hi s occur s when the dma fails to keep up wi th the received data. bit 2: fae , frame alignment error when f ae = 1, it indi cates that the incoming packet di d not end on a byte boundar y and the cr c di d not match at the l as t byte boundary. t he ali gnment e r r or counter i s i ncr emented when thi s condi ti on occur s . bit 1: crc , crc error when this bit is s et, it indi cates that the frames computed cr c fai l ed to cor r es pond wi th the cr c appended to the end of the fr ame. t hi s er r or al s o caus es the cr c counter to be i ncr emented. bit 0: prx , packet received intact when s et to 1, this bi t indi cates that a packet was r eceived wi thout er ror. t his means that cr c = f ae = ove r = mpa = 0.
5.2.29 rstop - receive stop page register n or mal map r ead p or t = 2 : 1 2 normal map write p ort = 0:12 t he r ecei ve s top p age r egi s ter poi nts to the fi r s t addr es s beyond the l as t r ecei ve buffer i n the r i ng before wrapping around to the r s t ar t buffer. only a0 8 -a1 5 ar e s peci fi ed s i nce al l buffer s ar e al i gned on 256-byte boundaries . bit rstop reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.30 rtabh - receive buffer table pointer high register l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 9 t hi s r egi s ter contai ns the upper 8 bi ts for the r egis ter pair us ed as a pointer to the r eceive buffer descriptors table. these registers should be initializ ed to the s ame val ue as the r b e gi n regis ter when the des cr i ptor tabl e i s cr eated and ther eaf ter left unaltered unless the receiver buffer pool is rebuilt. f or more information, refer to page 89. bit rtabh reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.31 rtabl - receive buffer table pointer low register l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 8 t his regis ter contains the lower 8 bits for the r egis ter pair us ed as a pointer to the r eceive buffer descriptors table. these registers should be initializ ed to the s ame val ue as the r b e gi n regis ter when the des cr i ptor tabl e i s cr eated and ther eaf ter left unaltered unless the receiver buffer pool is rebuilt. f or more information, refer to page 89. bit rtabl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x 5.2.32 sta0-sta5 - station address registers sta register normal map port address linked-list map port address read write read write sta0 1:11 1:11 1:11 1:11 sta1 1:12 1:12 1:12 1:12 sta2 1:13 1:13 1:13 1:13 sta3 1:14 1:14 1:14 1:14 sta4 1:15 1:15 1:15 1:15 sta5 1:16 1:16 1:16 1:16 t hes e 6 r egi s ter s hol d the nodes i ndi vi dual s tati on address. table 5-11 shows the bits defined for these registers.
5.2.33 taddh - transmit burst starting address high register n or mal map r ead/w r i te p or t = 2 : 1 b t hi s i s the hi gher 8 bi ts of a r egi s ter pair us ed inter nall y by the dma contr oller as a s cratch pad for the bur s t addr es s of the tr ans mi t pr oces s . wr i ti ng to the taddh and taddl registers while communi cati on i s tak i ng pl ace may caus e er r or s i n the dma pr oces s . bit taddh reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.34 taddl - tr ansmit burst starting address low register n or mal map r ead/w r i te p or t = 2 : 1 a t hi s r egi s ter contai ns the l ower 8 bi ts for a r egi s ter pair us ed internally by the dma controller as a s cratch pad for the bur s t addres s of the trans mit process . writing to the taddh and taddl r egis ter s while communication is taking place may caus e er r or s i n the dma pr oces s . bit taddl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x sta registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sta0 da07 da06 da05 da04 da03 da02 da01 da00 sta1 da15 da14 da13 da12 da11 da10 da09 da08 sta2 da23 da22 da21 da20 da19 da18 da17 da16 sta3 da31 da30 da29 da28 da27 da26 da25 da24 sta4 da39 da38 da37 da36 da35 da34 da33 da32 sta5 da47 da46 da45 da44 da43 da42 da41 da40 reset xxxxxxxx table 5-11. station address register bits
5.2.35 tbegin - transmit buffer starting address register l i nk ed- l i s t map r ead p or t = 2 : 1 3 l i nk ed- l i s t map wr i te p or t = 0 : 1 5 t his r egi s ter holds the upper 8 bi ts of the s tarti ng addr es s of the tr ans mi t buffer des cr i ptor tabl e. t he l ower 8 bi ts ar e as s umed to be z er o. r efer to page 80 for more information. bit tbegin reset 7 tb15 x 6 tb14 x 5 tb13 x 4 tb12 x 3 tb11 x 2 tb10 x 1 tb09 x 0 tb08 x 5.2.36 tcnth - transmit frame length high register normal map read port = 2:16 normal map write port = 0:16 t his regis ter contains the upper 8 bits of a two-r egis ter s et that holds the byte count for the frame to be trans mitted. t his byte count mus t i ncl ude the da, s a, and data fiel ds . i f cr c gener ati on i s i nhi bi ted, thi s count mus t al s o i ncl ude the cr c fi el d i n the buffer . bit tcnth reset 7 l15 x 6 l14 x 5 l13 x 4 l12 x 3l11 x 2 l10 x 1 l09 x 0 l08 x 5.2.37 tcntl - transmit frame length low register normal map read port = 2:13 normal map write port = 0:15 t hi s r egi s ter contai ns the l ower 8 bi ts of a two-r egis ter s et that holds the byte count for the frame to be trans mitted. t his byte count mus t i ncl ude the da, s a, and data fiel ds . i f cr c gener ati on i s i nhi bi ted, thi s count mus t al s o i ncl ude the cr c fi el d i n the buffer . bit tcntl reset 7 l07 x 6 l06 x 5 l05 x 4 l04 x 3 l03 x 2 l02 x 1 l01 x 0 l00 x 5.2.38 tcon - transmit configuration register normal map r ead p ort = 2:1d normal map write port = 0:1d l i nk ed- l i s t map r ead p or t = 2 : 1 d l i nk ed- l i s t map write port = 0:1d t his regis ter controls loopback options and tr ans mi tter mode operations . bit tcon reset 70 0 60 0 50 0 40 0 30 0 2 lb1 0 1 lb0 0 0 crcn 0 bits 2-1: lb1, lb0 , loopback test selection t hes e two bi ts ar e decoded as s hown i n t abl e 5 - 1 2 .
lb1 lb0 operation 0 0 normal (no loopback) 0 1 internal loopback (before man codec) 1 0 internal loopback, loop pin is high (after man codec) 1 1 external loopback with loop pin low table 5-12. loopback test selection bit 0: crcn , crc generation inhibition s etti ng thi s bi t inhibits gener ation of cr c duri ng transmission of frame. the user is responsible for cal cul ati ng the fr ames cr c and pl aci ng i t i n the buffer in such a way that when the last 4 bytes of the buffer ar e s hi fted out, they for m the cor r ect cr c for the fr ame. note that the s eri al iz er s hifts bytes out l s b fir s t wher eas the cr c mus t be s hi fted ms b fi rs t. t he operati on of the receiver is not affected by this bit. 5.2.39 tdownh - transfer count high register l i nk ed- l i s t map r ead/wr i te p or t = 2 : 1 b t hi s r egi s ter contai ns the upper 8 bi ts for the r egi s ter pai r us ed by the dma contr ol l er as a s cratch pad for the bytes r emai ni ng to trans fer count dur i ng the tr ans mi s s i on pr oces s . t hey can be acces s ed for manuf actur i ng tes t pur pos es . note writing to these registers while commu- nication is taking place may cause er- rors in the dma process. bit tdownh reset 7a15 x 6a14 x 5a13 x 4a12 x 3a11 x 2a10 x 1a09 x 0a08 x 5.2.40 tdownl - transfer count low register l i nk ed- l i s t map r ead/wr i te p or t = 2 : 1 a t his regis ter contains the lower 8 bits for the r egi s ter pai r us ed by the dma contr ol l er as a s cratch pad for the bytes r emai ni ng to trans fer count dur i ng the tr ans mi s s i on pr oces s . t hey can be acces s ed for manuf actur i ng tes t pur pos es . note writing to these registers while commu- nication is taking place may cause er- rors in the dma process. bit tdownl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x 5.2.41 tend - transfer buffer end register l i nk ed- l i s t map r ead p or t = 2 : 1 4 l i nk ed- l i s t map wr i te p or t = 0 : 1 4 t hi s r egi s ter hol ds the upper 8 bi ts of the fi r s t addr es s beyond the end of the tr ans mi t buffer des cr i ptor tabl e. t he l ower 8 bi ts ar e as s umed to be zero. t he table lies between (t be gin * 256) and (t e nd * 256 - 1). r efer to page 80 for more information. bit tend reset 7 te15 x 6 te14 x 5 te13 x 4 te12 x 3 te11 x 2 te10 x 1 te9 x 0 te8 x
5.2.42 tlevel - transmit fifo track register n or mal map r ead p or t = 3 : 1 e l i nk ed- l i s t map r ead p or t = 3 : 1 e t his counter tr acks the number of empty bytes in the tr ans mit f i f o. an empty f i f o has 10h i n this counter. a full fifo has 00h. bit tlevel reset 7 0 6 0 5 0 4 ct04 0 3 ct03 0 2 ct02 0 1 ct01 0 0 ct00 0 5.2.43 tstarth - transmit start page high register n or mal map r ead p or t = 2 : 1 4 normal map write p ort = 0:14 t hi s r egi s ter i s the hi gher 8 bi ts of a r egi s ter pai r that poi nts to the as s embl ed pack et to be tr ans mi tted. t o retain compati bi lity with 83c690 dr i ver s , the us er s houl d s tar t al l fr ames on 256 - byte boundar i es and not wr i te to t s t ar t l . bit tstarth reset 7a15 0 6a14 0 5a13 0 4a12 0 3a11 0 2a10 0 1a09 0 0a08 0 5.2.44 tstartl - transmit start page low register n or mal map r ead/w r i te p or t = 3 : 1 5 l i nk ed- l i s t map r ead/wr i te p or t = 3 : 1 5 t hi s r egi s ter i s the l ower 8 bi ts of a r egi s ter pai r that points to the as s embled packet to be trans mitted. to retain compatibility with 83c690 drivers, the us er s houl d s tar t al l fr ames on 2 5 6 - byte boundar i es and only wri te to the t s t ar t h r egi s ter. bit tstartl reset 7 a07 0 6 a06 0 5 a05 0 4 a04 0 3 a03 0 2 a02 0 1 a01 0 0 a00 0 5.2.45 tstat - transmit status register n or mal map r ead p or t = 0 : 1 4 l i nk ed- l i s t map r ead p or t = 0 : 1 4 t he t r ans mi t s tatus r egi s ter r epor ts events that occur on the medi a at the end of pack et tr ans mi s s i on. al l bi ts ar e cl ear ed pr i or to tr ans mi s s i on of a packet and ar e s et as needed. when al t e go = 1 , the r egi s ter i s cl ear ed only at the begi nni ng of a tr ans mi t chai n and i s s et af ter each packet has compl eted. bit tstat reset 7owc 0 6 cdh 0 5 under 0 4 crl 0 3 abort 0 2twc 0 1 ndt 0 0 ptx 0 bit 7: owc , out of window collision t hi s bi t i s s et i f a col l i s i on i s detected mor e than one s lot time after the s tar t of tr ans mi s s ion. t rans mis - s i on i s abor ted under thes e condi ti ons .
bit 6: cdh , collision detect heartbeat t hi s bi t i s s et to a 1 dur i ng tr ans mi s s i on of each packet. it is set to 0 if a collision is detected within 3.6 m s ec of the end of each pack et tr ans mi s s i on. i f no col l i s i on i s detected wi thi n thi s wi ndow, i t r e- mai ns 1 . bit 5: underfifo , fifo or buffer underrun when thi s bi t i s s et, i t means ei ther : a fifo underrun condition has occurred. this condition results when the transmit unit at- tempts to read from an empty fifo prior to receiving the transmit done flag from dma. this means that the fifo failed to supply enough data for the serializer to maintain frame genera- tion. a buffer underrun has occurred. this condition happens when the transmit dma accesses an address that is greater than or equal to the most recent host-written location in memory, pro- vided that the early transmit check feature is enabled. bit 4: crl , carrier sense lost t his bit i s s et if the carr ier is l os t dur ing packet transmission. carrier sense is monitored from its r i s i ng edge at the s tar t of the outgoi ng fr ames echo. transmission is not aborted upon loss of carrier. it is reported for statistical purposes. bit 3: abort , abort transmission t his bit is s et if the tr ans mis s ion is aborted due to excessive collisions. bit 2: twc , transmitted with collisions t hi s bi t i s s et i f the fr ame col l i ded at l eas t once wi th another frame on the network. i t is not s et for either out-of-window collis ions or excess ive collis ion abor ts . bit 1: ndt , non-deferred transmission this bit is set if the frame was transmitted success- fully without deferring. a deferred trans mis s ion can only occur the fi rs t time an attempt i s made to s end a packet. collisions are not deferred transmissions. bit 0: ptx , packet transmitted t his bit is s et to indicate tr ans mis s ion of a packet without exces s ive collis ions or a f if o underrun. 5.2.46 ttabh - transmit buffer pointer high register l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 b t his regis ter contains the higher 8 bits of the r egi s ter pair us ed as a poi nter to the tr ans mi t buffer descriptors table. these registers should be i ni ti al i z ed to the s ame val ue as t b e gi n when the des cr iptor tabl e is cr eated, and not altered ther eafter by the us er unl es s the tr ans mi t buffer pool is rebuilt. f or more information, refer to page 80. bit ttabh reset 7 a15 x 6 a14 x 5 a13 x 4 a12 x 3a11 x 2 a10 x 1 a09 x 0 a08 x 5.2.47 ttabl - transmit buffer pointer low register l i nk ed- l i s t map r ead/wr i te p or t = 0 : 1 a t hi s r egi s ter contai ns the l ower 8 bi ts of the r egi s ter pai r us ed as a poi nter to the tr ans mi t buffer descriptor table. these registers should be i ni ti al i z ed to the s ame val ue as t b e gi n when the des cr iptor tabl e is cr eated, and not altered ther eafter by the us er unl es s the tr ans mi t buffer pool i s r ebui l t. bit ttabl reset 7 a07 x 6 a06 x 5 a05 x 4 a04 x 3 a03 x 2 a02 x 1 a01 x 0 a00 x
5.2.48 renh - receive enhancement register n or mal map r ead/w r i te p or t = 0 : 1 9 t he r ecei ve e nhancement r egi s ter contai ns several bits required for the new receive features of the 83C795 chip. bit renh reset 7 0 6 0 5 0 4 0 3 0 2 rempty 0 1 erfbit 0 0 wrapen 0 bit 2: rempty , ring bit empty when r e mp t y = 1, this r ead-only bi t i ndicates that the r ecei ve buffer r i ng has no compl etely r ecei ved frames . bit 1: erfbit , early receive fail bit when e r f b i t = 1 i t i ndi cates that an under r un has occur r ed dur i ng the r ecepti on of a fr ame. t he hos t cl ear s thi s bi t after r eadi ng the addr es s wher e the fai l ur e occur r ed fr om the e r f a r egi s ter s . bit 0: wrapen , automatic ring-wrap enable when wr ap e n = 1 it enables the auto-wrapping feature. for more information on automatic ring- wrap, refer to page 87.
address function name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 control cr rnic menb cr4 cr3 rp15 rp14 rp13 01 eerom rd er store rc ea4 unlock jmp3 jmp2 jmp1 jmp0 01 eerom wr er store rc ea4 unlock ea3 ea2 ea1 ea0 02 io pipe low iopl iop7 iop6 iop5 iop4 iop3 iop2 iop1 iop0 03 io pipe high ioph iop15 iop14 iop13 iop12 iop11 iop10 iop9 iop8 04 hw supp rd hwr swh ether host16 istat pnpjmp gpoe hw supp wr hwr swh nuke gpoe 05 bios page bpr m16en bp15 bp14 bp13 soft1 soft0 06 int control icr mctest stag iopav iopen sint mask2 m ask1 eil 07 revision rev chip3 chip2 chip1 chip0 rev3 rev2 rev1 rev0 io pipe addr iopa iopa7 iopa6 iopa5 iopa4 iopa3 iopa2 iopa1 iopa0 08 swh=0 lan addr0 lan0 ln07 ln06 ln05 ln04 ln03 ln02 ln01 ln00 09 swh=0 lan addr1 lan1 ln15 ln14 ln13 ln12 ln11 ln10 ln09 ln08 0a swh=0 lan addr2 lan2 ln23 ln22 ln21 ln20 ln19 ln18 ln17 ln16 0b swh=0 lan addr3 lan3 ln31 ln30 ln29 ln28 ln27 ln26 ln25 ln24 0c swh=0 lan addr4 lan4 ln39 ln38 ln37 ln36 ln35 ln34 ln33 ln32 0d swh=0 lan addr5 lan5 lnmsb ln46 ln45 ln44 ln43 ln42 ln41 ln40 0e swh=0 board id bdid bdid7 bdid6 bdid5 bdid4 bdid3 bdid2 bdid1 bdid0 0f swh=0 checksum cksm chk7 chk6 chk5 chk4 chk3 chk2 chk1 chk0 08 swh=1 general cntl2 gcr2 pnpiop 0a swh=1 i/o address iar ia15 ia14 ia13 ia8 ia7 ia6 ia5 pnpboot 0b swh=1 ram base rar hram ra17 ramsz1 ramsz0 ra16 ra15 ra14 ra13 0c swh=1 bios base bio fine ba17 biosz1 biosz0 ba16 ba15 ba14 ba13 0d swh=1 gen control gcr xlength ir2 ows ripl ir1 ir0 gpout lit 0e swh=1 erf addr low erfal erfa7 erfa6 erfa5 erfa4 erfa3 erfa2 pnpen 0f swh=1 erf addr high erfah erfa15 erfa14 erfa13 erfa12 erfa11 erfa10 erfa9 erfa8 table 5-13. host interface register summary
register ring linked bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 alicnt 0:1d 0:1d ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 bound 0:13 0:13 a15 a14 a13 a12 a11 a10 a09 a08 cmd x:10 x:10 x:10 x:10 ps1 ps0 0 enetch disetch txp sta stp colcnt 0:15 0:15 t10 t9 t8 t7 ct3 ct2 ct1 ct0 crccnt 0:1e 0:1e ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 curr 1:17 1:17 curr15 curr14 curr13 curr12 curr11 curr10 curr09 curr08 currh 1:17 1:17 curr15 curr14 curr13 curr12 curr11 curr10 curr09 curr08 currl 0:13 0:13 curr07 curr06 curr05 curr04 curr03 curr02 curr01 curr00 dcon 2:1e 0:1e 2:1e 0:1e 01000001 enh 2:17 2:17 2:17 2:17 0 1 altego slot1 slot0 eotint s back erwcnt 0:18 0:18 0:18 0:18 erw11 erw10 erw9 erw8 erw7 erw6 erw5 erw4 group0 1:18 1:18 1:18 1:18 ga07 ga06 ga05 ga04 ga03 ga02 ga01 ga00 group1 1:19 1:19 1:19 1:19 ga15 ga14 ga13 ga12 ga11 ga10 ga09 ga08 group2 1:1a 1:1a 1:1a 1:1a ga23 ga22 ga21 ga20 ga19 ga18 ga17 ga16 group3 1:1b 1:1b 1:1b 1:1b ga31 ga30 ga29 ga28 ga27 ga26 ga25 ga24 group4 1:1c 1:1c 1:1c 1:1c ga39 ga38 ga37 ga36 ga35 ga34 ga33 ga32 group5 1:1d 1:1d 1:1d 1:1d ga47 ga46 ga45 ga44 ga43 ga42 ga41 ga40 group6 1:1e 1:1e 1:1e 1:1e ga55 ga54 ga53 ga52 ga51 ga50 ga49 ga48 group7 1:1f 1:1f 1:1f 1:1f ga63 ga62 ga61 ga60 ga59 ga58 ga57 ga56 intmask 2:1f 0:1f 2:1f 0:1f 0 erwe cnte ovwe txee rxee ptxe prxe intstat 0:17 0:17 0:17 0:17 rst erw cnt ovw txe rxe ptx prx manch 3:1f 3:1f 3:1f 3:1f mandis sel 0 enapol tpol lnk rled xled mpcnt 0:1f 0:1f ct7 ct6 ct5 ct4 ct3 ct2 ct1 ct0 next 2:15 2:15 a15 a14 a13 a12 a11 a10 a09 a08 raddh 2:19 2:19 a15 a14 a13 a12 a11 a10 a09 a08 raddl 2:18 2:18 a07 a06 a05 a04 a03 a02 a01 a00 rbegin 2:11 0:11 a15 a14 a13 a12 a11 a10 a09 a08 rcnth 0:1b ct15 ct14 ct13 ct12 ct11 ct10 ct09 ct08 rcntl 0:1a ct07 ct06 ct05 ct04 ct03 ct02 ct01 ct00 rcon 2:1c 0:1c 2:1c 0:1c 0 rca mon prom group broad runts sep rdownh 2:19 2:19 a15 a14 a13 a12 a11 a10 a09 a08 rdownl 2:18 2:18 a07 a06 a05 a04 a03 a02 a01 a00 rend 2:12 0:12 a15 a14 a13 a12 a11 a10 a09 a08 renh 0:19 0:19 re mpty erfbit wrapen rstart 2:11 0:11 a15 a14 a13 a12 a11 a10 a09 a08 rstat 0:1c 0:1c dfr dis group mpa over fae crc prx rstop 2:12 0:12 a15 a14 a13 a12 a11 a10 a09 a08 rtabh 0:19 0:19 a15 a14 a13 a12 a11 a10 a09 a08 table 5-14. lan controller register summary
register ring linked bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rtabl 0:18 0:18 a07 a06 a05 a04 a03 a02 a01 a00 sta0 1:11 1:11 1:11 1:11 da07 da06 da05 da04 da03 da02 da01 da00 sta1 1:12 1:12 1:12 1:12 da15 da14 da13 da12 da11 da10 da09 da08 sta2 1:13 1:13 1:13 1:13 da23 da22 da21 da20 da19 da18 da17 da16 sta3 1:14 1:14 1:14 1:14 da31 da30 da29 da28 da27 da26 da25 da24 sta4 1:15 1:15 1:15 1:15 da39 da38 da37 da36 da35 da34 da33 da32 sta5 1:16 1:16 1:16 1:16 da47 da46 da45 da44 da43 da42 da41 da40 taddh 2:1b 2:1b a15 a14 a13 a12 a11 a10 a09 a08 taddl 2:1a 2:1a a07 a06 a05 a04 a03 a02 a01 a00 tbegin 2:13 0:15 a15 a14 a13 a12 a11 a10 a09 a08 tcnth 2:16 0:16 l15 l14 l13 l12 l11 l10 l09 l08 tcntl 2:15 2:15 l07 l06 l05 l04 l03 l02 l01 l00 tcon 2:1d 0:1d 2:1d 0:1d lb1lb0 crcn tdownh 2:1b 2:1b a15 a14 a13 a12 a11 a10 a9 a8 tdownl 2:1a 2:1a a07 a06 a05 a04 a03 a02 a01 a00 tend 2:14 0:14 te15 te14 te13 te12 te11 te10 te09 te08 tlevel 3:1e 3:1e ct04ct03 ct02 ct01 ct00 tstarth 2:14 0:14 a15 a14 a13 a12 a11 a10 a09 a08 tstartl 3:15 3:15 3:15 3:15 a07 a06 a05 a04 a03 a02 a01 a00 tstat 0:14 0:14 owc cdh under crl abort twc ndt ptx ttabh 0:1b 0:1b a15 a14 a13 a12 a11 a10 a09 a08 ttabl 0:1a 0:1a a07 a06 a05 a04 a03 a02 a01 a00 table 5-14. lan controller register summary (cont.)
6.0 host interface section t he h os t i nter f ace i s a conf i gur abl e i nter f ace between an industry s tandard architecture bus (like ibm pc/xt /at ) and the lan controller with its buff er memor y. t he i nter face i s a s l ave per i pher al wi th s har ed r am and s uppor t for an i ni ti al p r ogr am load rom. the basic functions of the host interface section are the: address decode memory address generation retrieval and storage of configuration parame- ters and lan address interrupt mapping and control control over certain hw functions for support circuitry 6.1 memory cache t he memory cache in the 83C795 cons is ts of a 4-byte-deep f i f o whi ch s er ves as an intermediate buff er between the i s a bus and the l ocal buffer r am. f or r ead oper ati ons , the cache acts as a small prefetch buffer which fills itself with data from locations i n the buffer r am that depend on the address of the last data location read by the host. f or wr i te oper ati ons , the cache acts as s ever al tempor ar y r egi s ter s that can be as ynchr onous l y written by the hos t, then s ynchronous ly flus hed to buffer r am as time permits . t his method provides s ever al advantages over pr evi ous methods : host accesses to shared memory can be treated more like register accesses, thus simpli- fying zero-wait state timing. a single 8-bit wide buffer ram is u sed but the chip can accommodate 8- or 16-bit accesses by the host. asynchronous arbitration between the host and the dma controller for access to the buffer ram is not necessary. i n addi tion to the data f i f o, the cache r equir es two address counters for its operation. the first, called the h os t counter, is compared with the incomi ng hos t addr es s . t he s econd, cal l ed the b uffer counter, is us ed to gener ate the addr es s to the l ocal buffer r am. t he s ame data f i f o i s us ed for both r eads and wr i tes r es ul ti ng i n two di ffer ent modes of oper ati on: r ead mode and wr i te mode. read mode i f the hos t addr es s does not equal the val ue i n the h os t counter , then both counter s ar e l oaded wi th the i ncomi ng addr es s . t hen the cache i s fi l l ed wi th data fr om the buffer r am a byte at a ti me by i ncr ementi ng the b uffer counter. t he hos t acces s i s s tal l ed dur i ng thi s ti me by dr i vi ng the i or dy s i gn al l ow. on ce th e cach e has a v al i d wor d of data from the buffer r am, the ior dy line is driven high. t hi s s i gnal s the hos t that the data i s val i d, and the hos t, in turn, ends the acces s . once the hos t has fi ni s hed, the h os t counter i s i ncr emented (the increment step will be either 1 or 2 depending on whether the host access was for a byte or for a wor d) , and the f i f o poi nter s ar e updated. t he cache continues to fill with data as long as there is room in the f if o. if the hos t addres s matches the val ue i n the h os t counter (and ther e i s val i d data i n the cache), the r ead can be s er vi ced i mmedi ately. wr i t e mode t he write mode is handled like the read mode except that the data moves in the oppos ite dir ecti on thr ough the f i f o. al s o, i f an addr es s mi s s occur s i n wr i te mode, the cache mus t fir s t fl us h al l val i d data in the f i f o out to the buffer r am before loading new values into the addr es s counter s . t he i or dy s i gnal i s us ed when the cache needs to s tall a hos t acces s . t his s ignal is outputted by a high current, tri-s tatable driver which is normally tur ned off between acces s es to the board. i t dr ives low to indi cate that the boar d i s not i or dy and drives high when making the transition from not ready to ready. when the acces s compl etes , the i or dy l i ne i s tr i-s tated by the ending of the hos ts s tr obes . f igure 6 -1 depi cts the memor y cache ar r angement.
6.1.1 zero wait state response to host t he z ero wait s tate signal tells the microprocessor that i t can compl ete the pr es ent bus cycl e wi thout inserting any additional wait cycles. for 16-bit memor y acces s , thi s means z er o wai t s tates ar e i ns er ted by the hos t bus l ogi c and the acces s cycl e completes in 2 bus clocks. when asserted for an 8 bi t memor y acces s , an i s a bus automati cal ly inserts the minimum of 2 wait states. the response algorithm for the z ws line depends upon the memory width, the hos t acces s type and whether the boar d has been enabl ed to act as a 1 6 - bi t devi ce. t he appr opr i ate zws response logic is selected on the basis of the bpr.m16en control bi t and whether the boar d i s i n an 8 - or 1 6 - bi t s l ot. t he memor y cache can accommodate z er o wai t s tate timing if the following conditions are met: 1. the type of host access matches the current mode of the cache, 2. the host address matches the value in the host counter, and 3. the cache either contains at least one valid data word for reads or has room for at least one more word for writes. f or wr i tes , z er o wai t s tates ar e al s o al ways pos s i bl e if the cache is in read mode, or if it is currently empty. t here is a zero wait enable bit in one of the host i nter face r egi s ter s (cr .z ws e n) whi ch can be us ed to prevent the 83C795 fr om as s erti ng the z ero wait s tate s i gnal . 6.1.2 staggered address transfers staggered address transfers occur when the host attempts 16-bit data transfers from system memory to the l ocal buff er r am and fi nds that the addr es s of the s ys tem data di ffer s fr om the l ocal addr es s i n the l eas t s i gnificant bit (one is even, one is odd). i n consequence, the isa bus forbids 16-bit accesses to odd locations and br eaks the trans fer into two 8 - bi t cycl es whi ch r un cons i der abl y s l ower . to overcome this on the 795: figure 6-1. memory cache arrangement
1. make sure the system address is even. if the address comes out odd, transfer one byte. 2. set the stag bit (icr.6). this forces a 1 into bit 0 of the buffer counter when the address is loaded note this only happens on a cache miss. this makes it possible for the host to perform an even- to- even tr ans f er , but the i nter nal addr es s to the l ocal r am i s tr ans for med to an odd addr es s . 6.1.3 operation on micro-channel adapters do not us e this chip for micro-channel applications . a futur e var iant may be created with the neces s ary interface logic. 6.2 i/o-mapped pipe t he i /o- mapped pi pe pr ovi des another method for acces s i ng the l ocal buffer r am. when enabl ed, al l memor y acces s es tak e pl ace thr ough two i /o r egi s ter s i n the hos t i nter face i /o s pace (i op l and i op h). t he data in thes e two i /o locations cor r es ponds to the the locati on in the buffer memor y i ndi cated by the b uffer counter. when r un i n thi s mode, the memor y- s pace addr es s decoder s are disabled, so the adapter will not use any host memor y s pace for the buffer r am. t he mechani s m us ed by the i /o- pi pe i s s i mi l ar to that us ed by the memor y cache ex cept for addr es s handli ng. i n this method, the addres s is loaded into the b uffer counter by per for mi ng two cons ecuti ve wr i tes to the i op a r egi s ter. t he fir s t wr i te s tor es the l ower hal f of the addr es s i nto a tempor ar y r egi s ter . t he s econd wr ite s tor es data di rectly into the upper half of the buffer counter and moves the temporary r egis ter into the lower half. any acces s to the chip between the two wr i tes wi l l caus e the s tate machi ne to not l oad the addr es s . t he h os t counter i s not used during this process. t o us e the i/o-pipe, the iop e n bit (i cr .4) mus t be s et to 1, and the me nb bi t (cr .6) mus t be s et to 0. all 8-bit transfers must take place through iopl only. als o, it is imperative that when s witching from r ead mode to wr i te mode, the addr es s mus t be r el oaded even if the counter hol ds the cor rect value. 6.3 address decoders t hr ee addr es s decoder s ar e us ed to detect hos t accesses to the buffer memory, i/o registers, and i p l r om. t hes e decoder s obs er ve the s a19 - s a05 lines to decode access within a range of addresses ( a wi ndow). t he buff er and i p l r om decoder s al l ow pl acement of their r es pecti ve wi ndows on any 8k boundary between c0000h and e ffffh r egar dl es s of wi ndow s i z e. t hi s al l ows wi ndows to s tar t on even or odd 8k boundar i es . t he r am and i p l r om ar e s cr ol l abl e (and ther efor e can be paged) thr ough thei r pr ogr ammabl e wi ndow s i z e as s hown i n t abl e 6 - 1 bel ow. decoder min base max base increment window sizes buffer c0000h ee000h 2000h 8k 16k 32k 64k* disabled ipl rom c0000h ee000h 2000h 8k 16k 32k disabled i/o base 0200h e3e0h 20h, 2000h 32 bytes table 6-1. host interface address decoders * plug and play cannot utilize this window s ize.
b ecaus e of the 1 6 - bi t memor y mechani s m empl oyed i n i s a bus es , do not al l ow the memor y wi ndow to over lap the df f f f h to e 0000h boundary when using 16-bit memory. if the boundary crosses, host memory accesses to portions above e0000h are made into 8-bit cycles. note use caution when overlapping the rom and ram windows if the ram is 16-bit wide and both windows are en- abled. with 16-bit access enabled, the m16cs is asserted for all accesses within the same 128k address block as the ram base window address. should the access actually be intended to the rom, the host falsely expects the rom to return 16-bit data. this can crash the operating system. to avoid such problems on 16-bit boards, copy rom code to system ram and disable the rom window. alternatively, map the rom into other 128k address block. p r ogr am contr ol enabl es buffer memor y decodi ng thr ough a r egi s ter i n the hos t i nter face s ecti on. when connected to a 1 6 - bi t bus , thi s compar i s on i s qual i fi ed by me mr , me mw, and the i nver s e of ae n. when connected to an 8-bit bus , the qualification is by smemr, smemw, and the i nver s e of ae n. t he buffer memor y wi ndow s i z e i s program-s electable as 8k, 16k, 32k, 64k bytes or di s abl ed. t he bu f f er bas e addr es s can be s et to any 8k boundary from c0000h through e e 000h. b y s etti ng a bi t i n the r am addr es s r egi s ter (r ar .hr am), the decoded buffer range can be changed to the range f c0000h - f e e 000h. (t his range is not possible when using plug and play.) when connected to a p c/x t bus havi ng no l a lines, it is required that the bpr.m16e n be kept a zero (inactive). t he i p l r om decodi ng i s enabl ed by pr ogr am control thr ough the b i o r egi s ter in the hos t inter face s ecti on. decoder qual i fi cati on i s by smemr and an inverted aen. rom window size is program s electable from 8k, 16k, 32k bytes or dis abled. t he r om wi ndow pl acement i n hos t memor y s pace figure 6-2. overlapping address structure
i s pr ogr ammabl e on any 8k boundar y fr om c0 0 00 h t o e e 0 0 0 h . w h er e r om an d r am decodi ng over l aps , r om takes pr ecedence. f i gur e 6-2 shows how the overlapping address structure wor k s . y ou can r el ocate r am and r om bas e addr es s es in tandem above 1m (100000h) with the application of an ex ter nal cas caded addr es s decoder. t hi s i s i l l us tr ated i n f i gur e 6 - 3 . note relocation of the memory windows in this way is not supported when plug and play is enabled. 6.3.1 memory address generation roms and buffer memories larger than their programmed windows can be s crolled (paged) by us i ng pr ogr ammabl e addr es s modi fi er s (adder s ) that l i e between the hos t addr es s and the r om or buffer memor y. t hes e addr es s modi fi er s can add i ndependentl y to ei ther addr es s any of the fol l owi ng val ues and ex pos e di ffer ent par ts of the tar geted memor y wi thi n the wi ndow: 0000h 2000h 4000h 6000h 8000h a000h c000h e000h t he l ower addr es s l i nes (s a12- 0 ) fr om the hos t ar e multiplexed wi th the dma addr es s lines to generate par t of the memor y addr es s . t wo potenti al memor y addresses are generated by subtracting the respective ram and rom base address bits (17-13) from s a17-s a13, then adding the rp15-rp13 field of the cr register for the ram figure 6-3. external cascaded address decoder
addr es s or the b p 15- b p 13 fi el d of the b p r r egi s ter for the r om addr es s . dependi ng on whether the buffer memor y or the r om wi ndow i s bei ng acces s ed, one of thos e two pos s i bl e s ums becomes ma15-ma1 3 to the memor y cache counter s . r efer to f igure 6-4 for an ill us tr ation of the addr es s gener ati on path. figure 6-4. address generation path
6.3.2 i/o address decode t he i /o addr es s decoder compar es the s ys tem address lines sa15-sa13 and sa8-sa5 against a programmable value. s a9 is compared to 1. t he l ower gr oup of l i nes gi ves a wi ndow s i z e of 3 2 bytes l ocated on 3 2 - byte boundar i es over the r ange of 2 0 0 h to 3 e 0 h . t he compar i s on wi th upper addr es s bi ts al l ows the wi ndow to be l ocated outs i de the bas e i /o ar ea i n the event ther e ar e mul ti pl e l an cards on the same backplane. t his comparison is qual i fi ed by the ior, iow, and the inverse of the aen lines. i/o base location possibilities are: 0200, 0220, 0240, ..., 03e0 2200, 2220, 2240, ..., 23e0 4200, 4220, 4240, ..., 43e0 ... e200, e220, e240, ..., e3e0 note only the first base location option is supported by plug and play. t he i /o addr es s i s fur ther decoded to r es ol ve between the l an controller and regis ters as s oci ated wi th the hos t i nter face bas ed on the a4 addr es s l i ne. 6.3.2.1 pc-98 bus support t h i s f eat ur e al l ows t he i /o addr es s decodi ng to be changed to s uppor t the n e c p c- 9 8 bus . t hi s i s done by i ns tal l i ng j u mp e r 7 , whi ch connects an ex ter nal r es i s tor between ma7 and gr ound. when enabled, the sa9-sa1 lines replace the sa8-sa0 lines, the sa12-sa10 lines must be all 1s, and the s a0 line must be zero for an i/o access to occur. this remapping only affects i/o accesses and l eaves memor y decodi ng unchanged. 6.4 bus control signals t wo s i gnal s contr ol much of the bus acti vi ty. t hey ar e i /o channel r eady (i or dy ) and z er o wai t state ( z ws ). e ach i s ex pl ai ned bel ow. 6.4.1 iordy t he i or dy output is a high cur rent, tri-s tate dr iver which is nor mally turned off between acces s es to the boar d. i t will actively dr ive l ow to indicate that the boar d i s not i or dy and dr i ves hi gh when making the tr ans iti on from not r eady to r eady. acces s to the inter nal regis ter s of the l an cont r ol l er i s ar bi tr at ed by th e l an con tr ol l er . t h i s ar bi tr ati on i s tr ans par ent to the hos t. when host access is completed, iordy is tri-stated by the endi ng of the hos ts s tr obes . 6.4.2 zero wait state response to host the zero wait state ( z ws ) s ignal tells the mi cr opr oces s or t hat i t can compl et e th e pr es en t bus cycl e wi thout i ns er ti ng any addi ti onal wai t cycles. the response algorithm for the zws line depends on the memory width, the hos t acces s type, and whether the boar d has been enabl ed to act as a 1 6 - bi t devi ce. t he appr opr i ate type of zws response logic is selected on the basis of memory wi dth and the m1 6 e n contr ol bi t s tate. t here is a zero wait enable bit in one of the host i nter face r egi s ter s (cr .z ws e n) whi ch can be us ed to prevent the 83C795 fr om as s erti ng the z ero wait s tate s i gnal .
6.5 memory bus structure and configuration 6.5.1 memory bus width control b ecaus e of the 83C795s memor y cache, the wi dth of the memory path is fixed at 8 bit. by means of the memor y cache, the i /o pi pe can s er vi ce ei ther an 8-bit or 16-bit host access. the host and host interface logic are programmed for a s pecific memor y width by s etti ng bi t 7 in the b i os p age r egi s ter, m16e n. (s ee page 1 7 for mor e on thi s bi t. ) t he 83C795 calculates the width of the hos t bus by obs er vi ng the me mr l i ne for tr ans i ti ons . an i nter nal fl ag (e e r om. h os t 1 6 ) i s s et to i ndi cate a 1 6- bi t hos t bus after 2 r i s i ng edges ar e s een on thi s pi n. when connected to an 8-bi t hos t, this pin i s left unconnected or is tied to vdd and s hould not have any tr ans i ti ons . 6.5.2 16-bit response to host access the bpr.m16en bit in the bios page register tell s the hos t i nter face l ogic whether to make the l an adapter r es pond as a 1 6 - bi t or an 8 - bi t peripheral to the hos t. t he 83C795 res ponds to ei ther hos t bus wi dth. when the hos t acces s es memor y, an addr es s comparator within the 83C795 looks at the la23-l a17 lines to determine if the 83C795s memor y ter r i tor y i s bei ng acces s ed. i f i t i s and i f mp r . m1 6e n i s s et, the m16cs li ne i s acti vated to tell the hos t to run a 16-bit trans fer cycl e. when this deci s i on i s bas ed onl y on the l a addr es s l i nes , i t i s pos s ible that the m16cs will be s ent out when the host is accessing a device other than 83C795 within the same address range. to allow finer resolution for the m1 6 cs decode, ther e i s an opti onal means of i ncl udi ng the decodi ng of s a16-s a13 lines in the generati on of the m16cs r es pons e. t hi s can be enabl ed by the f i n e 1 6 bi t of the memor y p age r egi s ter. b ecaus e the s a l i nes ar e not guar anteed s tabl e as ear ly as l a l i nes , thi s for m of decodi ng can l ead to er r oneous r es ul ts . b e careful when you us e this method. t o avoid bus width conflicts between buffer memory and the r om as wel l as con f l i ct s wi th ot her car ds i n t he system, the 16-bit response should be turned on by s oftwar e onl y when that s oftwar e can guar antee that no acces s to the r om is taking place and that the only acces s es within the 128k memor y range ar e to 1 6 - bi t devi ces . t hi s may mean ens ur i ng that no acces s to any other card can take place. in existing drivers, this is done by performing all 16-bit tr ans fer s within interr upt s er vice routines that keep all other interr upts di s abled dur ing the tr ans fer. t ake s peci al car e when wr i ti ng i p l r om code. i f the code actually gets executed out of r om, the r om can potentially be configured within the s ame 1 2 8 k bl ock . t he bes t advi ce i s to copy code f r om r om to s ys tem memor y outs i de the bl ock or to wr i te code that does not enabl e 1 6 -bi t tr ans fer s . t he host is provided with the zws signal in accor dance wi th whether the memor y cache can accommodate the tr ans fer. t he ti mi ng of thi s s i gnal is dependent upon the width of the trans fer bei ng per for med wi th the hos t. t o meet the memor y bandwi dth r equi r ed by the i s a bus , i t i s neces s ar y to i mpl ement the buff er memor y
with fas t (35 ns ec) r ams . f or more details , s ee the ac timing specs in section 10. 6.6 interrupt request control logic t her e ar e two s our ces of i nter rupt reques ts to the hos t: the l an contr ol l er and a pr ogr ammabl e bi t (s i nt ) i n the i cr r egi s ter . t he l an contr ol l er s ecti on pr ovi des for the mas k i ng, pol l i ng, and clearing of its individual interrupt conditions. t he s um of the mas k ed l an i nter r upt condi ti ons i s or ed with the programmable i nter rupt from the hos t i nter face s ecti on ( s i n t ) and gated by the e i l bi t fr om the i cr r egi s ter pr i or to tur ni ng on one of the s even program-s el ectable tr i-s tate dr iver s . t he driver selection is made via bits in the gcr register. i nter r upt di s abl i ng s houl d be accompl i s hed vi a the i cr .e i l bit, not by changing the inter rupt level to 0, becaus e dur ing the trans i tion from an acti ve level to tri-s tate, fals e inter rupts may be generated. t he i nter r upt r eques t contr ol l ogi c i s depi cted i n figure 6-5. figure 6-5. interrupt control logic
6.7 eerom controller and its utilization t he 83C795 is des igned to operate in conjunction wi th a s er i al e e r om memor y that s tor es the conf i gur ati on of the hos t i nter f ace and the per manentl y - as s i gned l an s tati on addr es s . i t can r educe the number of j umper s needed on a boar d and al l ows f or r econf i gur ati on wi thout r emovi ng the boar d fr om the s ys tem. t he e e r om i s us ed to i ni ti al i z e s ome of the hos t i nter face confi gur ati on r egis ter s at res et ti me. 6.7.1 initialization of 83C795 activation of the r es et pin for ces the i nter nal s tate of the 83C795 to a known value. t here is a group of opti on bi ts that can be conf i gur ed by attachi ng r es i s ti ve pul l -downs to four of the memor y addr es s output lines (ma09-ma00). t hes e pins are s ometimes referr ed to as the i ni t pi ns . t hey s ti ll per for m thei r functi on as memor y addr es s l i nes but al s o act as i nput pi ns dur i ng the r e s e t pr oces s . e ach pin has a high impedance internal pull-up r es i s tor that caus es the pi n to r ead as 1 unl es s a lower-impedance external pull-down resistor brings the natur al s tate of the li ne to a logic 0 level. i t is ex pected th at an appl i cat i on of t hi s ch i p wou l d u s e a set of jumpers to selectively connect these pins to the exter nal pull -downs , as s hown in t able 6-2 bel ow. jumpers pins effect these jumpers are installed to mark 0 bits jmp0-3 ma0-3 eerom config. field, bits 0-3. these jumpers are installed to activate features jmp4 ma4 switching ps hiduty option. jmp5 ma5 switching ps output from gpout. jmp6 ma6 plug and play logic enable. jmp7 ma7 nec pc-98 bus support. jmp8 ma8 drive 20 mhz clock out tled pin. jmp9 ma9 use 83c790 chip id field instead of the 83C795 id field. table 6-2. jumper example at the end of r es et, thes e i ni t pi ns ar e s ampl ed and latched. one of thes e combinations determines whether the e e r om i s r ead i nto the hos t i nter face regis ters. ordinarily, the 83C795 loads its conf i gur ati on r egi s ter s fr om e e r om, but s el ecti on of one special combination of jumpers (when all i ni t s ar e pul l ed down) pr ovi des a means of by pas s i ng the e e r om l oad to al l ow r api d s imulati on and tes ting of the device. u til iz e the bypas s mode to pr oduce a l es s ex pens i ve adapter des ign which does not retain configuration or addr es s per manently. t her e i s al s o a means of accel er ati ng the e e r om cl ock and as s oci ated e e r om i nter face pi ns (eedo, eecs, lled, rled) for test purposes. lled is connected to the eerom clock pin (eesk) and i s nor mal l y the pr i mar y cl ock (2 0 mh z ) di vi ded down by 128 during e e r om acces s es. t he ior and i ow pi ns ar e l atched on the r i s i ng edge of r e s e t . i f both are active (low) at the s ame time, the cl ock accelerates to 10 mh z . t o res tore the normal 156 khz clock rate, the chip is reset without activating i or or i ow. r l e d is connected to the eeroms data-in pin, eedi. u n l es s by pas s ed, th e e e r om data i s r ead automatically into the hos t inter face r egis ter s jus t after the 83C795 is res et. t his takes approximately 2 milliseconds. during this time, memory, rom, and r egi s ter acces s i s di s abl ed. i /o acces s es to any host interface register return garbage except for bit 6 , whi ch wi l l r etur n 1 unti l the r egi s ter s ar e l oaded at whi ch time bi t 6 returns 0. t o determine when the initial load of registers is completed, poll the eer register. if the recall bit (bit 6) equals 0, the initial load is complete. the registers start out with their reset values and ar e changed one r egi s ter at a ti me as the e e r om i s r ead out. t he buff er memor y i s al ways di s abl ed upon r es et and mus t be enabl ed by s of twar e. t he first time an eerom is powered up, it has random data. t he 83C795 can be acces s ed at known initial addresses if a special setting of the i ni t pi ns i s chos en when r e s e t pi n i s acti ve. t hi s i s ex pl ai ned i n mor e detai l i n the fol l owi ng s ecti on.
6.7.2 retrieval and storage of host configuration registers 6.7.2.1 eerom interface overview an external 9356 s erial e e r om is us ed to s tore up to 256 bytes of data. i t takes about 2 ms to read all 1 6 r egi s ter s after the end of the r es et pul s e. i t tak es about 200 ms to s tore the e e r om. t he lan contr ol l er s houl d not be onl i ne (tr ans mi tti ng or abl e to r ecei ve) whi l e e e r om r ecal l or s tor e oper ati ons ar e ongoi ng, nor s houl d any of the r egi s ter s i n the lan controller or host interface section be accessed during that time. unpredictable results may occur because the internal data busses will be s upporting the data movement to or from the e e r om dur ing that time interval . an exception to this rule is made in the cas e of the e e r r egi s ter, whi ch may be pol l ed to deter mi ne when the r ecal l or s tor e oper ati on compl etes . when the e e r r egi s ter i s r ead, the e e r . s t o and e e r .r c bi ts are vis ible to the hos t. other bits from that r egi s ter ar e meani ngful only when ther e i s no ongoing eerom operation. all 256 bytes of e e r om can be written to and read fr om. t hey ar e r ead i nto the l an addr es s r egi s ter s 8 by tes at a ti me. once ther e, they can be changed and s tor ed. t he e e r om contr ol l er can be oper ated under pr ogr am contr ol to do par ti al r etr i eval s fr om and s ave configuration data into the e e r om. e e r oms have a l i mi ted number of s tor age cycl es . t he s tor e oper ati on s houl d onl y tak e pl ace at i ni ti al board configuration or at initial ins tallation in a cus tomer s computer . 6.7.2.2 eerom recall operation details all recalls from e e rom into host interface registers ar e made i n gr oups of ei ther 8 or 1 6 r egi s ter s . t he choi ces ar e pr ogr ammed into the e e r r egi s ter in the hos t interface s ection according to t abl e 6-3. reset recall action 0 0 no recall 0 1 recall from bank ea into lan addr registers 1 x recall from bank 6 into lan addr registers and from bank init into configuration registers. table 6-3. eerom recall operations t he recall of hos t interface configuration regis ters (addresses 08-0fh, swh=1) are done from the bank s elected by 4 i ni t jumpers . t abl e 6-4 defines which bank of configuration regis ters corres ponds to each ar rangement of the i ni t pins . init: ma3-0 bank notes 0000 none all pins jumpered to ground. this is the bypass condition. 0001 14 0010 13 0011 12 0100 11 0101 10 0110 9 0111 8 1000 7 1001 6 initial recall defaults: i/o = 280h rom= disabled at c0000h ram = 8k at c8000h int = 0 (no interrupt mapped) lit = disabled, gpout = 0 configuration registers (iar, rar, bio, gcr, gcr2) are not recalled after this reset. 1010 5 1011 4 1100 3 1101 2 1110 1 1111 0 no jumpers are atta ched to pins. table 6-4. config register/init pins
t he r ecal l of l an addr es s r egi s ter s ar e fr om the bank s el ected by the 4 - bi t e a fi el d and ar e wr i tten to registers at i/o locations 08h-0fh, s wh=0. upon r e s e t , the e a field points to b ank 6. unles s the e e r om l oad i s bypas s ed by j umper s (i ni t = 0000), the 8 3 c795 r ecal l s ei ther 8 or 1 6 r egi s ter s . when confi g #6 i s j umper ed, onl y 8 r egi s ter s ar e r ecal l ed and the har dwar e defaul ts ar e us ed for the configuration regis ters. all other initial conf i gur ati ons r es ul t i n 1 6 r egi s ter l oads . t hes e ar e done automatically. s ince ea always initializes to b ank 6, the initial load from the e e r om always pul l s i n the l an addr es s fr om s ame l ocati on. refer to f igure 6-6 for a depiction of the e e rom r egi s ter l ogi c. 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 a a lar0 lar0 gcr2 always to bank ea always from bank ea (ea powers up at '6') upon reset, recall configuration registers from the bank according to init jumpers. (no recall from bank 6.) banks of 8 registers in eerom lar1 lar1 gcr2 erfal erfal lar2 lar2 reset disable adapter load default values into registers bypass eerom load? are init jumpers in position '6'? recall? yes yes no no yes no enable adapter retrieve 8 registers from bank designated by ea field into lan address registers retrieve configuration registers pidl, pidh, iar, rar, bio, gcr from bank indexed by init jumpers retrieve lan address registers from bank indexed by ea field iar iar lar3 lar3 rar rar lar4 lar4 bio bio lar5 lar5 gcr gcr bdid bdid chk chk b b c c d d e e f f figure 6-6. eerom register logic
6.7.2.3 storage operations t he s tor e oper ati on onl y copi es the 8 l an addr es s r egi s ter s to the e e r om. t hi s does not depend upon i n i t j umper s etti ngs . t he s tor e oper ati on al ways moves the l an addr es s r egi s ter s i nto the bank s el ected by the 4 - bi t e a fi el d. table 6-5 defines how each bank of 8 e e rom l ocati ons has been al l ocated: bank allocation 00 user programmable (soft) configuration 01 configuration 1 02 configuration 2 03 configuration 3 04 configuration 4 05 configuration 5 06 permanent lan address 07 configuration 7 08 configuration 8 09 configuration 9 0a reserved for driver configuration storage 0b configuration 11 0c configuration 12 0d configuration 13 0e configuration 14 0f reserved for driver configuration storage 10-1f pnp data table 6-5. eerom location allocation unlocking the eerom for write operations t hi s convol uted method i s us ed to pr otect the e e r om fr om getti ng acci dental l y er as ed by s omeone el s es s oftwar e. t he e e rom register (e e r) looks like this: bit eer write reset 7sto 0 6rc 0 5 ea4 0 4 unlock 0 3 ea3 0 2 ea2 1 1 ea1 1 0 ea0 0 t he s cheme r equir es a s equence of thr ee wr i tes i nto the e e r om r egi s ter to s tar t a s tor e oper ati on. t he fi rs t two writes are requi red to s et the u nl ock bi t and the thir d wr i te executes the s tor e. t he 1s t wr i te mus t be: store=0, reca ll=0, ea4=x, unlock=0, ea[3C0] = ch. t he 2nd write mus t be: store=0, reca ll=0, ea4=x, unlock=1, ea[3C0] = ah. the 3rd write is: store=1, recall=0, unlock=0, ea[4C0] = eerom bank. the value for the ea4-ea0 field is the eerom bank you intend to s tore in it. t he wr i ti ng of any other val ue to the e e r other than the r equir ed ones i n the s equence wi l l s et the l ock i ng mechani s m back to i ts i ni ti al condi ti on and all three writes will once again be required in s equence to unl ock the wr i te pr otecti on. i nter veni ng i /o oper ati ons to other r egi s ter s and r eads of the e e r om r egi s ter do not affect the unl ock s equence.
s tor age of u s er - defi ned i ni ti al confi gur ati ons to define any of the 15 recallable configurations, fol l ow thes e s teps . 1. build an image of the desired configuration registers in the lan register bank (swh=0, addr=8:f). 2. write the unlock/store sequence with the fi- nal ea field of the eerom register selecting the desired configuration bank. do not use bank 6 because that is reserved for the per- manent device lan address. do not use bank 10 either because that is reserved for driver-related information storage and can- not be recalled as a board configuration. 3. wait about 200 msec or poll the store bit to determine whether that operation has completed. s tor age of u s er - defi ned l an addr es s t o s tor e a us er - defi ned l an addr es s , fol l ow thes e steps. 1. program the desired lan address, board id register, and checksum register with desired values. 2. write the unlock store sequence with the final ea field of eerom register selecting the bank 6. 3. wait about 200 msec or poll the store bit to determine that operation has completed. s tor age of u s er - defi ned data i n s ome appl i cati ons , ther e may be other data you need to s ave i n the e e r om, l ike boar d type and r evi s i on number s , mul ti cas t fi l ter acceptance mas k , s oftwar e dr i ver par ameter s , and the hos t machi ne type. s ince s ome e e r om locations may not be needed for configuration or l an addres s s torage, they can be us ed for this purpos e. 1. overwrite lan address, board id, and checksum registers with the data you need to save. 2. store the data as if it were a board configu- ration. the driver setup program uses this method to store driver related parameters into eerom bank 10. t o r ecall this us er defined data, pr ogr am the e a fi el d for the bank and do a r ecal l oper ati on. 6.8 plug and play t he 83C795 s uppor ts the p lug and p lay i s a s pecification. t his specification provides full and interactive configuration of all pnp-compliant boards installed on the isa bus. the essential steps in this process are the abilities to: power up and reset plug and play devices send out an initiation key to bring all pnp de- vices into a known state isolate each isa adapter in turn read the adapters resource requirements arbitrate the available resources to all of the pnp cards identify each board and configure its resources activate the cards on the isa bus locate a suitable driver for the adapter, if nec- essary t o be effecti ve i n thi s new envir onment, the 83C795 cont ai ns th e l ogi c n eces s ar y to pr epar e any boar d on which it is placed for plug and play standards. t hi s l ogi c wi l l be acti ve onl y when both the p np e n bi t (e r f al . 0 as r ead fr om e e r om) i s s et and a 3.6k w resistor is connected to the ma[6] pin (jmp6) between ma6 and gn d. t his s ection contains a brief overview of how p lug and p l ay wor k s , al ong wi th i nfor mati on s peci fi c to the 83C795s implementation of p np. f or more detai l on the p l ug and p l ay pr oces s and pr otocol , pleas e refer to the lates t ver s ion of the plug and play is a s pecification . 6.8.1 auto-configuration ports t he p l ug and p l ay pr otocol r equi r es that al l l ogi c not r el ated to p np on a p np boar d not r es pond to any isa bus access until the pnp logic activates the car d, ex cept for devi ces r equi r ed for boot ( s ee s ection 6.8.5). u ntil this happens , the only acces s to the car d is through the p np auto-confi gur ations por ts . t hes e por ts cons i s t of thr ee 8 - bi t i /o registers, as shown in table 6-6.
port name location type address fi xe d a t 0279h (lpt2 status port) write-only write_data fixed at 0a79h (lpt2 status port + 0800h) write-only read_data r e l o ca t ab l e i n range 0200h C 03ffh read-only table 6-6. auto-configuration ports al l wr i tes to the addr e s s por t ar e s tor ed i n an addr es s r egi s ter. t he val ue i n thi s r egi s ter i s us ed as an index into the internal 256-byte range that holds the pnp configuration registers. any accesses to the write_data or read_data port will be to the p np configuration regis ter that is cur r entl y i ndex ed by the addr es s r egi s ter . s ee s ection 6.8.3 for details on the configuration registers. 6.8.2 plug and play states t he main plug and play state machine contains four s tates and i s i l l us tr ated i n f i gur e 6 - 7 . all cards will enter the waitforkey s tate in r es pons e to ei ther a power -up r es et or the r es et and wai t for k ey commands . no commands ar e active in this state until the initiation key is detected on the i s a bus . t he wai tf or k ey s tate i s the defaul t state for plug and play cards during normal system oper ati on. t he i ni ti ati on k ey pl aces the p l ug and p l ay s tate machi ne i nto the s l eep s tate. t he i ni ti ati on k ey cons i s ts of a pr edefi ned s er i es of wr i tes to the addr e s s por t. t he wr i te s equence i s decoded by on- car d l ogi c. i f the pr oper s equence of i /o wr i tes i s detected, the p l ug and p l ay auto-confi gur ati on por ts ar e enabl ed. t he s equence of wr i tes that ar e expected i s : 0x6a,0xb5,0xda,0xed,0xf6,0xfb,0x7d,0xbe, 0xdf,0x6f,0x37,0x1b,0x0d,0x86,0xc3,0x61, 0xb0,0x58,0x2c,0x16,0x8b,0x45,0xa2,0xd1, 0xe8,0x74,0x3a,0x9d,0xce,0xe7,0x73,0x39 figure 6-7. plug and play state machine
any writes to the addr e s s por t that do not match the i nitiati on k ey s equence wil l caus e the logic to res et back to the s tart of the k ey. while the p np s tate machi ne i s i n the wai tf or k ey s tate, al l acces s to the r e ad_ dat a or wr i t e _ dat a ports is di s abl ed. once the s tate machi ne i s i n the s l eep s tate, the boar d r es ponds to a wak e [cs n ] command. e ach p np boar d has a r egi s ter to s tor e a car d s el ect number, and this r egis ter contai ns a z ero at power-up. t he card responds to a wake [cs n] command onl y i f the cs n i n the command matches the val ue i n the car d s el ect number r egi s ter. i f the cards cs n does not match the cs n in the wak e [cs n], i t goes i nto the s l eep s tate. t he car d stays in the sleep state until awakened by the corr ect wak e [cs n]. i f the cs n is z er o, then the card enter s the i s ol ation s tate, other wis e it moves into the configurati on s tate. 6.8.2.1 isolation a simple algorithm is used to isolate each plug and p l ay car d. t he i s ol ati on pr otocol r equi r es that each car d contai n a uni que number , r efer r ed to as the serial identifier . t his is a 72-bit number composed of two 3 2 -bi t fi el ds and an 8 -bi t checks um. t he fi r s t field is a vendor identifier. t he s econd can be any val ue - f or ex ampl e, a s er i al number or par t of a l an address. the number is accessed serially, bit by bit, by the i s ol ati on l ogi c and i s us ed to di ffer enti ate the adapter s . t he pnp software begins the isolation by sending out a wake[0] command. t his will cause all pnp cards that have not been is ol ated to trans ition to the i s olation s tate. i f this i s the fir s t pas s thr ough the protocol, then the software will pick an initial location for the r e ad_ dat a por t at this ti me. t he software then issues two reads to the is olat ion r egi s ter for each bi t i n the s er i al i denti fi er. i f the current bit is a 1, then the pnp board is expected to retur n 0x 55 on the fir s t r ead, and 0x aa on the s econd. i f the cur r ent bi t i s a 0, then the p np l ogi c will drive nothing on the bus , but will instead obs er ve the bus to s ee i f another car d i s dr i vi ng the 0x 55, 0xaa pattern. i f it does s ee that patter n for the two r eads , then that card mus t put its elf back i nto the s l eep s tate. t hi s ens ur es that onl y one p np car d wi l l be i n the i s ol ati on s tate at the end of the pr otocol . t he p np s oftwar e wi l l r ecogni z e the 0 x 5 5, 0x aa pattern as a 1 for that bi t pos i tion, and any other pattern as a 0. once all 72 bits have been read, the p np s oftwar e wi l l then ver i fy that the checks um matches the data. i f i t does , then the s oftware wi ll as s i gn a uni que, non- z er o cs n to the one car d that made i t to the end of the pr otocol . t hi s wi l l caus e that one card to tr ans is ti on to the configurati on s tate. i f the check s um does not match, then the s oftware wil l move the locati on of the r e ad_ dat a por t, and s tar t the pr otocol over . 6.8.2.2 configuration and activation t he i s ol ati on pr otocol ens ur es that onl y one car d can be i n the configuration s tate at a time. t his makes it pos s ible to r ead out the res our ce s tri ng byte-s er i al l y when i n thi s s tate. t hi s i s done thr ough the r es our ce_ data r egi s ter (l ocati on 0 x 0 4 ) , af ter polling the status bit (location 0x05, bit 0) to make s ure the data i n the regis ter is valid. t he p np s oftware will us e this method to read the entire resource string from the pnp card. this string lists the res our ce r equir ements of the card, along with what the car d i s capabl e of us i ng ( s ee s ecti on 6 . 8 . 5 for more on the resource string). the software r epeats thi s pr oces s wi th al l of the p np car ds i n the s ys tem, and thus obtai ns an i mage of al l of the r es our ce r equi r ements i n the s ys tem. t he s oftwar e then ar bi tr ates the avai l abl e r es our ces to meet the needs of each car d. i f a conf i gur ati on can be found, then the as s i gned confi gur ati on for each car d wi l l be wr itten to the cards . t he s oftware then activates the card by s etting the activate bit (location 0x30, bit 0). on the 83C795, this caus es the s oftware to tr ans fer the appr opr i ate s etti ngs i n the p np configuration registers to the 83C795s conf i gur ati on r egi s ter s by way of a s hi ft chai n. once this trans fer is complete, the res t of the logi c i n the 83C795 becomes active. 6.8.3 configuration registers f i gu r e 6 - 8 contai ns a map s howi ng al l of the confi gur ati on r egi s ter s i mpl emented by the 83C795. t his fi gur e al s o il lus trates the r elations hip between the auto- confi gur ati on por ts , the p np s econ dar y addr es s s pace, an d t he r es ou r ce s t r i n g. mos t of the conf i gur ati on r egi s ter s can onl y be acces s ed when the p np s tate machi ne i s i n cer tai n s tates . any unus ed r egi s ter s or bi ts i n the p np register space must return zeros when read. the
r egi s ter map s hown i n t abl e 6 - 7 changes when the adapter is run in i/o-mapped mode (see section 6.8.6). also, when the rom s pace is disabled (when bio.4 and bio.5 are both set), the rom conf i gur ati on r egi s ter s become r ead- onl y and al ways r ead z er os . t here are 22-bits of information in the pnp conf i gur ati on r egi s ter s that ar e us ed for confi gur i ng the 83c79 5 . t hes e bi ts ar e s hi fted fr om the p np s ecti on to the 83C795 s ecti on whenever the chi p i s activated. t he s ame bits are s hifted from the 83C795 section back to the pnp section at the end of the initial eerom load (to get the default values into the p np regis ters ). s ome of thes e bits may have to be r emapped bef or e they ar e s hi fted s o as to match the formats of the two different regis ter address function name read_data port address resource string number secondary address 00 01 0 - 7 02 8 03 9 - n 04 n + 1 05 06 07 n + 2 30 31 40 41 42 43 44 48 49 4a 4b 4c 60 61 70 71 serial isolation configuration control wake (csn) resource data status card select number (csn) logical device number activate i/o range check ram base address [23-16] ram base address [15-08] rom base address [23-16] ram range length [15-08] rom base address [15-08] ram control ram range length [23-16] rom control rom range length [23-16] rom range length [15-08] i/o base address [15-08] i/o base address [07-00] irq number irq type serial id checksum resource data end tag checksum item address write_data read_data 0x0279 0x0a79 0x0200 - 0x03ff isa address space eerom contents pnp secondary address space figure 6-8. plug and play configuration registers
field pnp bit 795 bit mapping function name no. location location pnp bits 795 bits ram base 1 0x40.1 rar.6 direct mapping 2 0x40.0 rar.3 3 0x41.7 rar.2 4 0x41.6 rar.1 5 0x41.5 rar.0 ram size 6 0x44.6 rar.5 6 7 rar.5 rar.4 7 0x44.5 rar.4 0 0 1 0 0111 1001 1100 rom base 8 0x48.1 bio.6 direct mapping 9 0x48.0 bio.3 10 0x49.7 bio.2 11 0x49.6 bio.1 12 0x49.5 bio.0 rom size 13 0x4c.6 bio.5 13 14 bio.5 bio.4 14 0x4c.5 bio.4 0 0 1 0 0111 1001 1100 i/o base 15 0x60.0 iar.4 direct mapping 16 0x61.7 iar.3 17 0x61.6 iar.2 18 0x61.5 iar.1 irq level used 19 0x70.3 gcr.6 19 20 21 22 gcr.6 gcr.3 gcr.2 20 0x70.2 gcr.3 0 0 0 0 0 0 0 21 0x70.1 gcr.2 0 0 1 0 0 0 1 22 0x70.0 0 0 1 1 0 1 0 010101 1 011110 0 100100 1 101010 1 101111 0 111111 1 table 6-7. plug and play bit remapping
s ets . t hes e bi ts ar e l i s ted i n t abl e 6 -7 , al ong wi th any neces s ar y mappi ng i nfor mati on. 6.8.4 resource string the plug and play resource string is stored in e e r om and can be acces s ed ei ther bi twi s e thr ough the s er i al i s ol ati on r egi s ter or byte- s er i al l y thr ough the r es our ce data r egis ter. t his s tri ng should completely describe the resource needs and options for a 83C795 bas ed card. a s ample ver s i on of this s tructure is l is ted in t able 6-8. once the 83C795 has been acti vated by the pnp logic, the resource string is accessed in the byte value swapped value name description 00 4d b2 vendor_id.0 serial identifier 01 a3 c5 vendor_id.1 02 84 21 vendor_id.2 03 16 68 vendor_id.3 04 c0 03 lan_addr.0 05 01 80 lan_addr.1 06 23 c4 lan_addr.2 07 45 a2 lan_addr.3 08 4c 32 checksum 09 0a 50 pnp_version_type plug and play version descriptor 0a 10 08 pnp_version 0b 10 08 vendor_version 0c 82 41 ansi_identifier_type ansi descriptor for card 0d 0d 30 descriptor_length [7-0] 0e 00 00 descriptor_length [15-8] 0f 53 ca ansi character C s 10 4d b2 ansi character C m 11 43 c2 ansi character C c 12 ff ff ansi character C 13 38 1c ansi character C 8 14 34 2c ansi character C 4 15 31 8c ansi character C 1 16 36 6c ansi character C 6 17 ff ff ansi character C 18 43 c2 ansi character C c 19 61 86 ansi character C a 1a 72 4e ansi character C r 1b 64 26 ansi character C d table 6-8. plug and play resource string structure
byte value swapped value name description 1c 15 a8 logical_device_type logical device descriptor 1d 4d b2 logical_device_id.0 1e a3 c5 logical_device_id.1 1f 84 21 logical_device_id.2 20 16 68 logical_device_id.3 21 02 40 logical_device_flags (non-boot, does i/o range che cking) 22 23 c4 interrupt_descriptor_type interrupt format descriptor 23 a8 15 irq_mask [7-0] C interrupts supported: 3, 5, 7 24 8e 71 irq_mask [15-8] C interrupts supported: 9, 10, 11, 15 25 16 68 irq_information 26 47 e2 i/o_port_descriptor_type i/o port descriptor 27 00 00 i/o_port_info 28 00 00 i/o_min_base_addr [7-0] 29 02 40 i/o_min_base_addr [15-8] C minimum base address = 0x0200 2a e0 07 i/o_max_base_addr [7-0] 2b 03 c0 i/o_max_base_addr [15-8] C maximum base address = 0x03e0 2c 20 04 i/o_base_alignment C alignment = 32-byte blocks 2d 20 04 i/o_range_length C length = 32 bytes 2e 81 18 memory_range_descriptor_type memory range descriptor #1 2f 09 90 descriptor_length [7-0] (two would be required for cards using 30 00 00 descriptor_length [15-8] both rom and shared ram) 31 11 88 memory_range_information C 8-/16-bit, writable 32 00 00 mem1_min_base_addr [15-8] 33 0c 30 mem1_min_base_addr [23-16] C minimum base address = 0x0c0000 34 e0 07 mem1_max_base_addr [15-8] 35 0f f0 mem1_max_base_addr [23-16] C maximum base address = 0x0fe000 36 00 00 mem1_base_alignment [7-0] 37 40 02 mem1_base_alignment [15-8] C alignment = 16-kbyte blocks 38 40 02 mem1_range_length [7-0] 39 00 00 mem1_range_length [15-8] C length = 16 kbytes 3a 79 9e end_tag_type end tag 3b 0e 70 checksum C covers all data bytes table 6-8. plug and play resource string structure (cont.)
s ame manner ( for both r eads and wr i tes ) as the r es t of the eerom contents, except that ea[4] (eer.5) must be set. 6.8.5 configuring as a boot card many l an adapter s ar e confi gur ed as boot car ds . s i nce thes e car ds mus t be vi s i bl e to the b i os at boot time, they may have to be activated befor e the p np s oftware has had a chance to run. t he pnpboot bit (iar .0) was implemented to do this . when this bi t i s read out of e e r om as s et, the chip becomes acti ve on the i s a bus . t his bi t als o for ces bi t 0 of the i ar r egi s ter to 1 whi ch i denti fi es the car d as a boot car d to the p np s oftwar e. 6.8.6 configuring with an i/o-mapped pipe when the 83C795 is configured with an i /o- mapped pi pe i ns tead of s har ed memor y, the boar d wi l l not us e any memor y addr es s s pace for the buffer r am. t her efor e, the p np r am contr ol registers (usually locations 40hC44h) are not necessary. if this card requires a rom, then the des cr i ptor for the r om memor y wi ndow wi l l be the first one in the resource string. t his requires that the pnp rom control registers be re-mapped from 48h-4ch to 40h-44h. t his is accomplis hed by s etting the p np iop bit (gcr 2.0). t his bit mus t be read out of eerom because it must have the corr ect value before the chip i s activated by the p np logic. s etting this bit als o caus es locations 4 8 h- 4 ch to r ead as z er oes . 6.8.7 buffer memory limitations n or mal l y, buffer memor y can be l ocated above the 1mb dos limit by setting the buffer address line (l a23-l a20) decoder to match at f rather than z ero (done by s etting the hr am bit, r ar .7). t his is not supported by the pnp hardware as i mpl emented i n the 8 3 c7 95 . 6.9 external power supply control t he gp ou t pi n can be us ed to contr ol an ex ter nal power supply supporting a 10base2 mau circuit. t his pin can be us ed to s ource either a s imple dc cont r ol s i gn al or a pu l s e tr ai n. t h e d c s i gn al i s u s ed to enabl e or di s abl e a contr ol l abl e power s uppl y. note the dc signals polarity on the 83C795 is the opposite of the 83c790s. t he puls e tr ain is des i gned to be the s wi tchi ng contr ol s i gnal for a s peci fi c des i gn of s wi tchi ng power s uppl y. t he pul s e tr ai n i ncl udes a s tar t- up s equence as wel l as a choi ce of two nor mal oper ati ng pul s e tr ai ns . b efor e the gp ou t pi n can emi t a pul s e tr ai n, i ns tal l the i ni t 5 jumper to pull down the ma5 pin. t he i ni t 4 j umper deter mi nes whi ch of the two pul s e tr ains is emi tted. t he puls e tr ain is tur ned on or off us i ng the gcr .gp ou t bi t (s ee page 21 for detai l s ). t he pul s e tr ai n i s a 31 2 k h z s i gnal wi th 1 /8 duty cycle for the firs t 1024 clocks after gpout is enabl ed. t hi s i s fol l owed by 1 /4 duty cycl e f or 1 k cl ock s , 3 /8 duty cy cl e for 1 k cl ock s , and 1 /2 ( 5 0 % ) duty cycl e ther eafter . i ns tallati on of the i ni t 4 jumper caus es the final duty cycle to be 17/32 (53% ) ins tead of 1/2.
7.0 lan controller overview t he l an contr ol l er cons i s ts of 3 bas i c bl ock s : dma controller, transmitter, and receiver. e ach of thes e bl ocks cons is ts of s ub-s ections . t he dma contr ol l er i ncl udes a memor y i nter face uni t, contr ol r egi s ter s , and a mi cr o- coded s equencer that handles data buffering for the trans mitter and r ecei ver s ecti ons . t he tr ans mitter bl ock has a mac (media acces s control) section that performs the ieee 802.3 tr ans mi s s i on pr ot ocol and a p hy s i cal l ay er i nter face (p l i ) s ecti on that does manches ter encodi ng and dr i ves the cabl es . t he r ecei ver bl ock has a mac s ecti on that per for ms the 8 0 2 . 3 r ecepti on pr otocol and a p l i s ecti on that conver ts l i ne l evel di ffer enti al s i gnal s to i nter nal l ogi c s i gnal s whi l e doi ng cl ock r ecover y, and manches ter decodi ng. 7.1 dma controller t he dma controller handles data movement between the f i f os and buffer memor y for tr ans mi s s i on and r ecepti on of fr ames . al l dma data traffic is 8-bit wide. one dma controller is shared between the tr ans mit and receive functions . t he contr ol l er gr oups memor y tr ans fer s i nto bur s ts of 8 bytes f or both tr ans mi t and r ecei ve functi ons . t he d ma contr ol l er al ways acces s es memor y by doi ng two single-byte transfers in a row. the burst size and i ts tr i gger l evel s ar e s hown i n t abl e 7 - 1 . burst trigger level rx tx 8 bytes r 3 8t 8 table 7-1. dma burst length field t hough inter nall y 8 bi ts wide, the dma contr ol ler generates 16-bit addresses. it accesses memory in 2 cycl es of the chi ps mas ter cl ock (per byte). w hen conducti ng a l oop- back tes t, thi s contr ol l er can handle full-duplex buffering of full length frames at s er ial data r ates up to 10 mbps . i t does not handle the gener al cas e of independent (concurr ent) tr ans mi t and r ecepti on pr oces s es . 7.1.1 assembly and disassembly latches t hes e l atches ar e us ed to match up the i nter nal 8-bit data path wi th the exter nal data bus . as s embly l atches bui l d a 16- bi t wor d out of two 8 -bi t wor ds or s uppl i es the cons ecuti ve bytes when i nter faci ng to an 8-bit bus. disassembly latches perform the i nver s e functi on. t hes e ar e us ed dur i ng dma oper ati ons and ar e by pas s ed when the chi ps r egi s ter s ar e wr i tten or r ead. 7.1.2 memory interface unit t he memor y i nter face uni t (mi u ) tr ans fer s data from buffer memory to the internal dis as s embly latches and fr om the internal as s embly latches to buffer memor y. i t i s a par t of the dma contr ol l er . t hi s bl ock gener ates the memor y s tr obes (ramoe, ramwr) when the dma is accessing the buffer r am. miu operation is initiated by the dma controller after i t s ets up the addr es s for the tr ans fer and puts outgoi ng data (r ecei ver functi ons ) i nto the as s embl y latches . t he mi u then per for ms the memory transfer in the next time slot assigned to the dma. the basic dma cycles are in figure 7-1. real detai l s can be f ound i n the ac ti mi ng s ecti on.
0 0 1 5 0 0 1 5 1 5 1 5 1 5 1 5 1 5 1 5 11 5 cache cache cache cache address address data data ramwr ramoe dmasel dmasel state state clk clk even even low low even+1 even+1 high high even+2 even+2 low low cache cache cache cache even+3 even+3 high high cache cache cache cache dma writes dma reads 1 5 1 5 1 1 8 2 6 2 5 1 5 5 1 55 1 3 7 3 6 1 5 4 8 4 7 1 5 1 5 figure 7-1. basic dma cycles
7.1.3 lan controller internal bus arbitration t his portion of the 83C795 is us ed to res olve conf l i cts that can occur on data bus es us ed by both the dma contr oller and hos t acces s es to the i nter nal r egi s ter s of the l an contr ol l er s ecti on. t he l an bus ar bi tr ati on s ecti on obs er ves a l an s elect (cs ) s ignal derived from the memory bus ar bi ter and pr ovi des a r eady hands hak e s i gnal i n return. it also controls internal data flow within the lan controller and holds off the dma microcontroller during i/o accesses. 7.1.4 dma microcontroller t he cor e of the d ma contr ol l er i s a r om- bas ed mi cr ocontr ol l er whi ch i ncl udes an addr es s counter for the memor y pos i ti on, compar ator s for i nter nal address comparisons, some decrementers for loop control, registers for storage of operating variables, and i /o control s i gnal s that attach to many cir cuits within the lan controller section of the chip. i n addi ti on to the mi cr ocode as s oci ated wi th nor mal tr ans mi t, r ecei ve and l oopback pr oces s es , ther e i s addi ti onal code to facil itate tes ting of the l an controller. 7.1.5 how to access registers a r eques t for l an r egi s ter acces s i s made when the hos t pr es ents an i /o addr es s that decodes to a regis ter within the upper 16 bytes of the 83C795s i /o bl ock and a val i d ior or iow is presented. t he chip will respond with an i/o channel not r eady s i gnal ( i or dy ) whi l e i nter nal ar bi tr ati on proceeds . it remains not ior dy until the des ired tr ans fer i s r eady to be compl eted. access to the registers of the lan controller section is allowed after any ongoing dma burst is completed. at that ti me, the dma may wis h to become acti ve agai n i n r es pons e to new needs , but the ar bi tr ati on l ogi c wi l l al l ow hos t acces s to the chi p unti l the i /o s tr obe becomes fal s e. t he ar bi ter generates the i or dy s ignal as an indication to the hos t that the i nter nal bus has been made avai l abl e and that the reques ted i /o acces s has been made. b etween acces s es to the chi p, i or dy i s undr i ven. t o r ead f r om a r egi s ter , an i /o addr es s i s pl aced on the s axx pins and ior is asserted by the host (must be as s er ted after a val i d addr es s ) and r ecogni z ed by the bus ar bi tr ati on l ogi c whi ch enabl es data fl ow fr om the addr es s ed r egi s ter to the d00- d07 pi ns . r egi s ter r eads ar e al way s done thr ough the d00-d07 pins , except for 16-bit i/o pipe acces ses . t he d08-d15 pins will be tri-s tated during read operations. iordy will indicate when the host may s ampl e data and ter mi nate the r ead oper ati on. t o wr i te to a r egi s ter , an i /o addr es s i s pl aced on the s axx pins and i ow i s as s er ted by the hos t and r ecogni z ed by the bus ar bi ter . addr es s mus t become s tabl e befor e i ow i s as s er ted. when the bus i s fr ee for the tr ans fer, i or dy i s as s er ted. data is latched into an intermediate trans fer latch with the trail ing edge of iow and then trans ferred to the des ti nati on r egi s ter two cl ock s l ater. t hi s del ayed wr i te oper ati on r equir es an i nter nal recovery period between host accesses to r egi s ter s . t hi s per i od i s documented i n the detai l ed ti mi ng di agr ams . 7.1.6 memory interface t he internal dma controller moves packets between buffer memor y and the f i f os .
7.2 fifos t her e ar e two f i f o s tr uctur es us ed to ex pedi te the tr ans fer pr oces s between the dma pr oces s or and the t r ans mi t/r ecei ve uni ts . e ach f i f o i s 16- bytes deep. as s oci ated wi th each f i f o ar e up/down counter s that keep track of how full each f i f o is . t he nor mal l oadi ng s our ce f or each f i f o r ecei ves an over fl ow i ndi cati on when i t occur s and the nor mal unl oadi ng des ti nati on has an empty s i gnal to pr event drawing of nonexis tent data. 7.3 receiver network interface (phy-to-mac) t his s ection of the 83C795 has squelched, differential receivers for the au i and t wp inter faces . t he i nputs from thes e inter faces are multiplexed together with a feedback path to a common phas e- l ock ed- l oop ci r cui t for cl ock r ecover y and data decodi ng. f i gur e 7 - 2 s hows the au i and t wi s ted- p ai r i nter f ace r el ati ons hi p. figure 7-2. aui/twisted-pair i nterface
7.3.1 aui differential receiver with the s tandard 78 w tr ans cei ver au i cabl e, the di ffer enti al i nput mus t be ex ter nal ly ter mi nated. t hi s r equi r ement may be s ati s f i ed by connecti ng two 3 9 w resistors in series with one optional common mode bypas s capaci tor. t o pr event noi s e at the au i r x +/- i nput fr om fal s ely tr igger ing the decoder, a s quelch ci rcuit r ej ects signals with pulse widths less than 25 nsec (negative going), or with levels les s than 175 mv. when the i nput ex ceeds the s quel ch l evel s , the analog phase-locked loop locks into the incoming s i gnal and manches ter decodi ng tak es pl ace. t he i nter nal car r i er s ens e s i gnal i s acti vated and the r ecei ve data ( r x d) and the r ecei ve cl ock ( r x c) become avai l abl e wi thi n s even bi t ti mes . at the end of a f r ame when nor mal mi d- bi t tr ans i ti on on the differential input ceas es , carrier s ens e is deacti vated. t he r eceive cl ock remains active for an addi ti onal 5 bi t ti mes . 7.3.2 twisted-pair differential receiver t he r ecei ved s i gnal fr om the uns hi el ded cabl e may be noisy, so minimum voltage and timing limits must be met befor e the r ecei ver l ogi c i s enabl ed. a s mar t s quel ch di gi tal noi s e f i l ter i s us ed i n addi ti on to the anal og s quel ch ci r cui t i n the r ecei ver . if the input polarity is reversed it will be automatically detected and corrected. when polarity is normal, the ple d (manch.3) bit will be set. t he phas e- l ock ed l oop and manches ter decoder ar e the s ame cir cui ts us ed by the au i r ecei ver. 7.3.2.1 extended length for twisted-pair s etti ng the x l e ngt h bi t (gcr .7) increas es the s quelch levels used by the t p receiver. t his enables the adapter to be connected to a cabl e that is longer than s pecified by the 802.3 s tandard. 7.3.3 manchester decoder decodi ng i s accompl i s hed by an anal og phas e-l ocked loop that s eparates the manches ter-encoded data s tream into clock s i gnal s and n r z data. t hi s l oop can tol er ate up to 2 0 ns ec of j i tter on each s i gnal edge, ex ceedi ng the 802. 3 r equi r ements . 7.3.4 carrier sense t he aui interface determines carrier presence by r equir i ng the di ffer enti al r ecei ved s i gnal to ex ceed the negative s quelch l evel for a minimal period, nominally 25 ns ec. t he twis ted-pair interface r equi r es that the pos i ti ve and negati ve s quel ch l evel s be ex ceeded s ever al ti mes for a per i od of at leas t 20 nsec. when operating in loopback mode, internal transmit enable s ignal is returned to the mac as the carr ier indication. 7.3.5 collision detect collis ion detection for the au i interface is indicated when the di ffer enti al s i gnal on the cd i nput pai r ex ceeds the negati ve s quel ch thr es hol d. col l i s i on detection for the twis ted-pair i nter face is indicated when ther e i s car r i er s ens ed whi l e the tr ans mi tter is active. 7.3.6 loopback mode when the l an controller is pr ogr ammed to operate in loopback mode 2, it provides a s ignal to the line receiver s ection which caus es the manches ter decoder to derive its input from the encoded tr ans mi t data i ns tead of the di ffer ential r eceivers of au i and t p i nter faces . t he au i and t p i nter faces are ignored while the loopback indication is active.
7.4 mac receiver 7.4.1 basic functions t he 83C795s receiver section process es a s erial s tr eam of n r z data. t he s tar t of the fr ame i s i denti fi ed, des ti nati on addr es s i s check ed agai ns t the station address, recognized frames are tr ans fer r ed to memor y and check ed f or val i d formation. e rror conditions are reported. 7.4.2 interface to the mac receiver t he s eri al interface to the mac r eceiver s ection is handled by four signals: carrier s ense (xcrs ), collis ion detect (xcol ), r eceive data (xr xd), and r ecei ve cl ock (x r x c). t he gr oup may come fr om one of thr ee s our ces : internally from the manchester decoder direct from the pins internally from the transmit section. all s ources are treated equally. s election of s ource i s done by pr ogr ammi ng confi gur ati on r egi s ter s . r efer to the t con and mandis r egis ters for further information. note these signals are multiplexed with the irq pins and are used for testing pur- poses only. 7.4.3 loopback paths the 83C795 has 3 loopback modes. mode 1 pr ovi des the path between r ecei ver and tr ans mi tter ins ide the l an controll er. i n this mode, nr z data from the tr ans mi tter connects to the r ecei ver s r x d i n put, by pas s i ng manches ter encoder /decoder. x r x c i s gener ated i nter nal l y for thi s mode by di vi di ng 2 0 mhz cl ock by two. t he mi ni mum fr ame l ength for mode 1 l oopback i s 2 5 bytes . mode 2 connects tr ans mi t and r ecei ve data thr ough the manches ter encoder /decoder. t he s er i al data i s wr apped ar ound j us t i ns i de the devi ce pi ns wi th neither aui nor t p interfaces actually driving the outs i de wor l d. t he mi ni mum f r ame l ength for mode 2 loopback is 25 bytes . mode 3 has transmitter and receiver pins active wi th l oopback pi ns i nacti ve. t he dma contr ol l er wi l l run its special loopback code to allow reception of the outgoing transmission if it is echoed back. in this mode, the dma can handl e del ay of the echo pr ovi ded that the fr ames l ength ex ceeds echo delay by at leas t 200 bit times (25 bytes ). when run in this mode, the board being tes ted should be connected to an 802.3-compliant cable. t hat cable may or may not have other 802.3 nodes attached. note caution is advised when running this test on a live network or when other nodes on the test cable could send a frame to the node under test. reception of a frame destined to the loopback node could confuse the results of the loopback test as the node will be able to receive the incoming frame. 7.4.4 receive deserialization r ecei ve des er i al i z er i s acti vated by car r i er s ens e. b yte ali gnment is determi ned by a s ynch ci rcuit which detects the s tart-of-f rame delimiter (s f d) when it s ees the serial s equence 10101011 after the s tar t of carr ier s ens e. t his patter n marks the fi r s t octet boundar y and deter mi nes byte al i gnment for the entir e fr ame. incoming rxd bits are clocked into an 8 bit wide serial-to-parallel shift register. t he bits are received in order from least significant to most significant within each byte. when an octet is complete, par al l el data i s l oaded i nto the r ecei ver f i f o. when car r i er i s l os t, the fr ame i s cons i der ed to have terminated; and all remaining serial data are dr opped. s er i al data i s pas s ed to the cr c check er whi ch i s i ni ti al i z ed upon r ecogni ti on of the s f d . t h i s pr oces s or di n ar i l y di s car ds al l bi ts that pr ecede the s f d patter n wi thout pr ej udi ci ng r ecepti on of the fr ame. s ome ex cepti ons can be made to this proces s to i mpr ove the r obus tnes s of the r ecei ver. t hey ar e di s cus s ed bel ow. t her e i s a s el ectabl e mode (us i ng the r con . r ca bit) during the receiver operation which adds robus tnes s by monitoring the x col s ignal continuous ly throughout reception, s tarting after the s tar t-of-f rame deli miter. i f colli s i on is detected, r ecepti on of the fr ame i s abor ted.
operating in alt e go mode engages a second i mpr ovement to the r ecepti on pr oces s . t he r ecei ver check s for cor r upti on of the pr eambl e and ter mi nates r ecepti on of any fr ame whi ch has cons ecutive 0 bits . al l valid preambles have an alter nati ng 10 patter n followed by the s tar t-of-f r ame del imi ter (11). t he above is check ed i mmedi atel y on the as s er ti on of the internal carrier sense without any grace periods. nei ther of thes e caus es for abor t for ces l ogi c to s et rxe. 7.4.5 crc checker t he r ecei ver computes the cr c of an i ncomi ng frame serially. crc computation includes addres s , data, and cr c fr ame fi el ds . i t ex cl udes pr eambl e and s f d. computati on s tops after r ecepti on of l as t whole octet following loss of carrier. t he final value of the cr c mus t be " c704dd7 b " for the pack et to be val i dated. t he cr c pol ynomi al us ed i s au t odi n i i : x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1. i f the r ecei ved fr ames cr c does not check out, a cr c er r or i s i ndi cated i n the s tatus r egi s ter and the crc e rror counter is incremented. frame reception will terminate unles s the r ecei ve- wi th- e r r or s mode i s enabl ed. i n addi ti on, if the number of bits r eceived i n the las t octet (when the carr ier is ter minated) is greater than one and les s than 8 (a full octet), and the cr c check for all complete octets fails , the frame is als o labeled as an al i gnment er r or and an er r or fl ag i s s et i n the status register; if this occurs, the alignment error counter wi l l be i ncr emented. 7.4.6 address recognition logic des tination addresses that are individual are compar ed to a 6 - byte s tati on addr es s s tor ed i n regis ters . if all bits match or if the p r omis cuous mode i s enabl ed, the fr ame i s r ecei ved. a s naps hot i s tak en of the par ti al l y- computed cr c as the end of the des ti nati on fi el d pas s es thr ough the cr c check er . i f the addr es s has the gr oup or mul ti cas t bi t s et, 6 bi ts of thi s check s um ar e us ed as a has hed index to a 64-bit multicas t f il ter table. i f r ecepti on of mul ti cas t fr ames has been enabl ed and if the 6-bit parti al cr c points to a bi t in the table that has been tur ned on, the mul ti cas t fr ame wi l l be r ecogni z ed. b r oadcas t fr ames ar e r ecei ved when the b roadcas t e nable bit (r con.b r oad) is active or when the has hed bi t i n the mul ti cas t f i l ter tabl e has been s et. t o caus e pr omi s cuous r ecepti on of mul ti cas t and br oadcas t fr ames , the entir e gr oup addr es s tabl e s houl d be tur ned on and r ecepti on of mul ti cas t fr ames enabl ed. i f the addr es s i s r ej ected, the fr ame i s al s o r ej ected and none of the fr ame is tr ans ported to the buffer memor y. i f the addr es s i s r ecogni z ed, buffer i ng of the fr ame begi ns . 7.4.7 received byte counter and early receive warning interrupt t hi s cir cui t counts the number of bytes i n each completed frame and filters out runt frames (les s than 64 bytes ) unl es s the r unt fi lter is defeated by s etting the accept r unt bit in the r eceive confi gur ati on r egi s ter (r con.r u nt s ). t he e ar ly r ecei ve war ni ng (e r w) i nter r upt i s gener ated when the r ecei ved byte count equal s or ex ceeds a val ue s peci fi ed i n the e ar ly r ecei ve war ni ng count r egi s ter (e r wcnt ). t he val ue of e r wcn t i s l eft- s hi fted f our bi ts (mul ti pl i ed by 1 6 ) before it i s compared to the r eceive byte count. t he value i s 8 bits wide, all owi ng the e r w thres hol d to be s et between 0 and 4k with a res olution of 16 bytes . t he e r w inter rupt is onl y gener ated if an acti ve reception is in progress. once an early receive inter rupt has been s et, it may be cleared and wi ll not be s et agai n unti l another pack et ex ceeds the e r w thr es hol d or the e r wcnt r egi s ter i s wr i tten to. wri ting a val ue to e r wcnt that is les s than the cur r ent r ecei ve byte count (whi l e r ecepti on i s i n progres s ) wi ll automatically s et the e r w i nter rupt. t he e r w interr upt i s mapped to bi t 6 in the i nter rupt s tatus r egi s ter (i ns t at ). t he e r w i nter r upt i s enabled or disabled like all other interrupts by the cor r es pondi ng bi t i n the i nter r upt mas k r egi s ter (int mas k).
7.4.7.1 early receive failure detection dur i ng the r ecepti on of a f r ame wi th ear l y r ecei ve enabled, it is pos s ible for the hos t to read fr ame data from the buffer r am before the dma writes it if the early receive threshold is set too low. t he failure detection logic enables the hos t to detect i f thi s has happened; i f s o, i t goes back and r ecopi es the corr ect data. t he logic required for this is similar to the logic used for early transmit underrun detection. t he local memor y addr es s i s l atched ever y ti me the dma wr ites to the buffer r am. when the memory cache or i /o pipe r eads data from the r am, the l ocal memor y addres s is compar ed to the las t latched addr es s . (t he l eas t s i gni fi cant 2 bi ts ar e not compar ed s o the detecti on mechani s m has a gr anul ar i ty of 4 bytes ). t hi s compar i s on i s tur ned off when the dma fi ni s hes pl aci ng the fr ame i n s har ed memor y. i f the two addr es s es ar e equal , e r f b i t (u b r cv.1) i s s et and the latched addr es s i s s tor ed i n the e r f a r egi s ter s (e r f al and e r f ah ). when the hos t r eads that e r f b i t i s s et, i t s houl d begi n r ecopyi ng data fr om a poi nt at or before erfa and reset erfbit. note the value in erfa contains the local memory address where the failure oc- curred, not the host address. t he e r f a r egis ter s r emai n s et unti l the hos t clears the erfbit. for more on erfbit, see page 40. for more on the erfa registers, see page 22. 7.4.8 receive protocol fsm t he r ecei ve p r otocol f s m contr ol s r ecepti on of fr ames , check s for er r or s , and pos ts s tatus to a register after completion of each reception. it oper ates counter s for the number of bytes i n the fr ame and for thr ee types of er r or condi ti ons . t he r ecei ver pr otocol f s m can be confi gur ed vi a a r egi s ter , al l owi ng s ome fl ex i bi l i ty as to whi ch fr ames ar e to be r ecei ved. t he r ecei ved byte counter i s 1 6 - bi ts wi de. t he thr ee er r or counter s ar e each 8 -bi ts wi de. t hes e wi l l count fr om z er o up to 255, wher e they s ti ck to avoi d wrap-around. t he error counters are self-clearing when r ead and they can gener ate a s har ed i nter r upt condition when any of them have counted up to 192. t he r ecei ve p r otocol f s m i nter faces wi th the dma s ection to coordinate buffering of received frames . it informs the dma of abort conditions, should they occur as well as valid completions of received fr ames . after the fr ame has been buffer ed to memor y by the dma, the dma s ecti on copi es the r ecei ver s tatus r egi s ter (r s t at ) and the number of bytes r ecei ved fr om the r ecei ver i nto the header of the buffer. t he receiver fifo is monitored for overflow conditions and if one occur s , fr ame recepti on i s ter minated and an er ror flag is pos ted to the s tatus register. t he receiver section is enabled by setting the s tart and cl ear i ng the s top bi ts i n the command r egi s ter - cmd.s ta and cmd.s t p. until enabled, the r ecei ver s ecti on i gnor es i ncomi ng fr ames . once the s tart bit has been s et, it remains true internally until the s top bit is set or the chip is reset. clearing the s tar t bi t i n command r egi s ter does not caus e the r ecei ver s ecti on to s top oper ati ng. if the s top bit is set while receiver is operational, it wil l complete the handli ng of any ongoing fr ame and then go to a s oft r es et conditi on, ignoring new i ncomi ng fr ames . t he r ecei ver wi l l cl ear the r s t at r egi s ter when the cur r ent fr ame i s fi ni s hed and pos ted. when both trans mitter and receiver s ecti ons ar e s topped, the r s t bi t i n the i nter r upt status register will be set. it should be noted that the dma controller may remain active while s top is set. t he pr otocol machi ne can be confi gur ed to oper ate in a "monitor mode" which checks validity of incoming frames and maintains error s tatistics for them but does not s tor e them in memor y. e ach time an acceptabl e fr ame i s compl eted whi l e i n thi s mode, the mi s s ed p ack et counter (mp cn t ) i s i ncr emented. t hi s counter i s not i ncr emented by fifo overflows. 7.4.9 reception process ieee 802.3 packets consist of thes e fields and are ther efor e pr oces s ed i n thi s or der : preamble field sfd field da field sa field
data field crc field e ach of thes e fi el ds i s ex pl ai ned i n the fol l owi ng sections. 7.4.9.1 start of frame t he pr eambl e fi el d i s us ed to tr ai n the manches ter decoder and to detect carrier. if carrier is detected, pr eambl e pas s es thr ough the r ecei ve des er i al i z er which discards it while searching for the s tar t- of-f r ame del i mi ter (s f d) s ymbol . on detecting a good s f d, a val id_f r ame s ignal is as s er ted and the r ecei ve f i f o i s cl ear ed to accept the r ecei ved fr ame. t he r ecei ve f i f o i s l oaded by the des er ializ er with octets (bytes ) s tar ting with the fi rs t bit after s f d. whi l e the des ti nati on addr es s ( da f i el d) i s bei ng ch eck ed f or r ecogni ti on, the r ecei ve d ma i s di s abl ed. i f the addr es s i s r ecogni z ed, the dma i s enabl ed and tr ans fer to memor y begi ns when the f i f o fi lls to the programmed bur s t level . i f the fr ames addr es s i s not r ecogni z ed, the r ecei ve uni t clears out the f if o, s tops filling it, and waits for the start of the next frame. t he s our ce addr es s and data fi el ds ar e pas s ed to buffer memor y. i n s ome pr otocol s , the fi r s t 2 bytes of the data field denote a fr ame length. t hes e bytes are not interpreted by the s mc795. t hey are tr eated as or di nar y data. 7.4.9.2 end of frame if there is a loss of carrier sense, 3 dribble clocks (recei ve cl ocks that occur after the los s of carr ier s ens e) ar e needed to ens ur e the s ynchr oni z ati ons of al l li ne s ignals to the r eceiver cir cui ts . when us i ng the inter nal manches ter decoder (either 10b as e -t or au i interfaces ), this decoder automatically supplies sufficient dribble clocks to the receiver to compl ete pr oces s i ng of the fr ame. when the manchester decoder is bypassed, it is necessary to s uppl y dr i bbl e cl ock s at the x r x c pi n af ter x cr s ter minates . t he cr c fr om the r ecei ved fr ame i s s ent to memor y with the fr ame vi a dma and is included in the byte count pos ted in the buffer header. i f the r ecei ve uni t detects er r or s i n the fr ame (s uch as an i ncor r ect cr c, an al i gnment pr obl em, a fores hortened fr ame), it can abort reception dependi ng on the confi gur ati on of the s ave e r r or ed p ack ets and accept r unt f r ames bi ts of the receive configuration register - rcon.sep and r con.r u nt s r es pecti vel y. cer tai n other types of errors (including fifo overflow and receiver buffer over wr i te) al way s abor t r ecepti on. i f r ecepti on i s abor ted, the d ma contr ol l er s tops s ending bytes to the buffer, the r eceive s tatus r egi s ter (r s r ) and the i nter r upt s tatus r egi s ter ( i s r ) ar e updated, and the r ecei ve uni t wai ts for the next frame to begin. no buffer header wi l l be pos ted for the fr ames that have not been accepted; the pr evi ous contents of the header l ocati on wi l l r emai n unchanged. t he r ecei ved pack et l ength s houl d be l es s than 32,764 bytes , including da, s a, data, and crc. t he r ecei ver does not r ej ect l onger fr ames but i t may be har d to fi t the contents into available buffer s pace. t he buffer r i ng mus t al ways have enough s pace to contai n the entir e fr ame wi th a 4 - byte header. p ack ets l ar ger than the avai l abl e buffer space will not be received, regardless of the s e p bi t i n the r con r egi s ter. s uch fr ames wi l l be pos ted as r i ng over wr i tes and caus es the ovw inter rupt to be s et. receiver interrupts (rxe for frames with errors and p r x for frames wi thout err or s ) indi cate the dma has compl etel y pos ted the fr ame to memor y. i f the dma aborts , thes e interr upts are not s et for the cur r ent fr ame. i f s et pr evi ous l y, they r emai n unchanged. packets shorter than 64 bytes will be r ecei ved onl y when the accept r unts bi t (r con.r unt s ) is enabled. 7.4.10 receiver blinding t he r ecei ver car r i er s ens e functi on i s bl i nded for a period of 4.0 m s ec s tar ting at the end of (x cr s + x col ) when the devi ce has tr ans mi tted a f r ame. t his allows the heartbeat to be detected without r es etti ng the deference timer and ens ur es that an improperly-spaced frame will not interfere with pr oper pos ti ng of s tatus for a new r ecepti on.
7.5 transmitter network interface (mac-to-phy) 7.5.1 oscillator a 20 mhz parallel resonant crystal can be connected between pi ns x 1 and x 2 ; or an ex ter nal cl ock can be connected at x 1 . t he os ci l l ator s 2 0 mhz output is divided in hal f inter nall y to provide the cl ock s i gnal s for the encodi ng and decodi ng ci r cu i t s . oper at i on at s er i al data r ates ot her t han 1 0 mh z r equi r es an ex ter nal l y-s uppl i ed cl ock s i nce the oscillator is only tuned for 20 mhz. the ieee 802.3 s tandar d r equi r es 0 . 0 1 % abs ol ute accur acy on the trans mitted s ignal fr equency; however, s tray capaci tance can s hi ft the cr y s tal s f r equency out of r ange caus i ng i t to ex ceed the 0. 01 tol er ance. 7.5.2 manchester encoder data encodi ng and trans mis s ion begin when the i nter nal tr ans mi t enabl e s i gnal fr om the l an controller goes high and continues as long as it remains high. transmission ends when the t r ans mi t e nabl e s i gnal goes l ow. t he l as t tr ans i ti on occur s at the center of the bi t cel l i f the l as t bi t i s 1 or at the boundar y of the bi t cel l i f the l as t bi t i s 0 . 7.5.3 aui differential driver t he au i di ffer enti al l i ne dr i ver has the abi l i ty to dr i ve up to 50 meter s of twi s ted-pai r au i /e thernet tr ans cei ver cabl e. t hes e dr i ver s pr ovi de emitter-coupled logic (e cl) level signals. t he outputs cons is t of curr ent drivers that mus t be loaded with external 150 w pull-up resistors . t he i nter face can be pr ogr ammed to oper ate i n ei ther half-step or full-step mode in the idle state. t his is done vi a the s e l bi t i n the manch r egi s ter. i n full -s tep mode, t x + is pos i tive in relation to t x - when idle. in half-step mode, t x+ and t x- are equal, res ulting in nearly zero differential output voltage. b y s etting a bi t in the manch r egi s ter, manches ter encoder /decoder l ogi c can be bypas s ed completely. e xter nal cir cui try s hould dri ve x t x c, xrxc, xcrs , xrxd, and xcol pins. 7.5.4 collision translator when the 83C795 i s us ed as an au i devi ce, a separate ethernet transceiver (mau) detects collisions on the coaxial cable and generates a 10 mhz s i gnal whi ch i s moni tor ed by the 8 3 c7 95 through the collis ion detect pins (cd+, cd-). t he pres ence of this s ignal activates the internal collision detect signal (cd) connected to the lan contr ol l er . t he col l i s i on detect s i gnal i s deacti vated wi thi n 160 ns ec after the abs ence of the 10 mhz signal. wi th the s tandar d 78 w trans ceiver au i cabl e, the cd+ /cd- di ffer enti al i nput pai r mus t be ex ter nal l y ter minated. t his r equir ement may be s atis fied by connecting two 39 w resistors in series with one opti onal common mode by pas s capaci tor . when 83C795 is us ed in twis ted-pair configuration, the col lis ion is generated i f the manches ter decoder detects car rier while the tr ans mi t enable i s acti ve. 7.5.5 twisted-pair differential driver t he t p driver can tr ans mi t thr ough up to 100 meter s of uns hielded twis ted pair cable. t he dr iver i ncl udes a ci r cui t f or tr ans mi t equal i z ati on whi ch attenuates the tr ans mit waveforms low-fr equency components . t hi s r educes the r ecei ved s i gnal s z er o- cr os s i ng j i tter and mak es the r ecei ver des i gn simpler. i n the tr ans mitter, phas e compens ation is us ed to r educe j i tter . t hi s i s accompl i s hed by us i ng ex ter nal r es is tor s to deter mine the dr ive s trength during the s econd half of a double-width puls e as compared to the dr i ve s tr ength of the fir s t hal f. t her e ar e two pairs of twisted-pair transmit drivers: tpx1 and t px2. t px2 is a much weaker driver than t px1. duri ng the fir s t half-bit-ti me of each pul s e, both pai r s of dr i ver s dr i ve out the encoded tr ans mi t data. if the pulse is a full-bit-time in length, t px2 switches polarity during the s econd half of the puls e and acts to r educe the amplitude of the tr ans mi tted s ignal. a s i mpl i fi ed ex ampl e of ex ter nal tr ans mi t ci r cui tr y i s s hown in figure 7-3.
7.5.6 link integrity test function e ach t p dr i ver tr ans mi ts a s hor t pos i ti ve pul s e periodically when it is not s ending data. t hese pul s es ar e r ecei ved at the other end of the twi s ted pair cable, s ignaling that the link is operating cor r ectl y. t he ti me between l i nk tes t pul s es i s compar ed to the ex pected r ange at the r ecei ver to help ignore nois e puls es . i f the link tes t fails (no pul s es or data r ecei ved wi thi n a fi x ed ti me per i od) then the l l e d pi n i s s et hi gh and au i i nter face i s s el ected. i f the l i nk i s r es tor ed, the chi p automatically s elects t p inter face. t he l ink i ntegrity t es t is als o us ed to cor rect the r ecei ver connecti ons pol ar i ty. t he l i nk i ntegr i ty test signal and start-of-idle both have positive pol ar i ty. t he pol ar i ty cor r ecti on s tate machi ne l ooks at both of thes e to deter mine whether to fli p r eceiver polarity. polarity correction can be disabled by a bit in the manch r egis ter (manch.e napol ). t he l i nk i ntegr i ty t es t can be di s abl ed by a bi t i n the gener al contr ol r egi s ter (gcr .l i t ). di s abl i ng l ink tes t forces the 83C795 to s elect the twi s ted-pair inter face. 7.5.7 jabber protection if the internal transmit enable signal is active for mor e than 46 ms ec, the twis ted-pair tr ans mitter wi ll be di s abl ed and a col l i s i on i ndi cati on i s s ent to the mac tr ans mitter ci rcuit. when the internal trans mit enable s ignal has been inactive for more than 368 msec, the internal collision indicator will become i nacti ve and the twi s ted-pai r trans mitter wi ll be r e- enabl ed. j abber pr otecti on for the au i por t i s pr ovi ded by an ex ter nal mau . 7.5.8 sqe test (heartbeat test) i n twis ted-pair oper ation, a bri ef internal colli s i on indication will be s ent to the mac tr ans mi tter after each pack et i s tr ans mi tted. w hen an au i por t i s i n us e, an ex ter nal mau wi l l pr ovi de thi s s i gnal . 7.5.9 status indications to assist in installation and management of the network, indi cator l e ds can be dri ven dir ectl y by four outputs fr om the 8 3 c79 5 . t hes e s how the res ult of l ink t es t, polarity check, trans mit and r eceive acti vi ty. t he l e d outputs can be read back thr ough the manch regis ter to s upport network management functions . 83C795 20 mhz low pass elliptic filter 100 ohms phone jack tpx2+ tpx1+ r32 240 r31 60 r34 60 r33 240 tpx1- tpx2- r31 || r32 = 50 ohm = r33 || r34 ratio of r31 to r32 determines how much smaller the second half of the pulse is than the first half 1 1 001 01 polarity tpx1 tpx2 + + + + + - - - - - - - + + + - - + - + + + - - + + figure 7-3. simplified transmit circuitry
7.6 transmitter section 7.6.1 basic function t he tr ans mitter s ection gener ates s er ial s tream of nr z data. i t pr oduces pr eambl e and the s f d fi el d at the beginning of a frame, then data is s hi fted from the f i f o s er i al l y fol l owed by the cr c fi el d. t he transmitter checks for collisions and retransmits the fr ames i f neces s ar y, i t counts i nter fr ame gap and implements random backoff algorithm. it maintains the tr ans mit s tatis tics and generates s tatus information on each attempted trans mis s ion. s el ecti on of opti onal oper ati ng modes of the t ransmitter section is done primarily by pr ogr ammi ng the t r ans mi t confi gur ati on r egi s ter. 7.6.2 preamble generator at the beginning of each frame, the tr ans mitter gener at es 5 6 bi ts of pr eambl e ( an al ter nati n g 1 0 1 0 pattern). i mmediately after this , it gener ates a s tar t f rame delimiter s equence which is 10101011. 7.6.3 transmit serializer t he t r ans mi t s er i al i z er conver ts 8 bi ts of par al l el data from the f i f o into s eri al trans mit nr z data. data i s s hi fted out leas t-s ignificant-bit (l s b ) fir s t. s er i al data i s cl ock ed onto an i nter nal s i gnal ( t x d) by the r i s i ng edge of the tr ans mi t cl ock . t hi s s i gnal pas s es to the manches ter e ncoder whi ch encodes i t and dr i ves the s el ected s er i al i nter face. when the encoder i s bei ng bypas s ed, the s er i al data dr i ves the xt xd pin directly. 7.6.4 crc generator t he tr ans mitter calculates the cr c s eri al ly and appends i t to each fr ame. cr c i s cl ock ed out mos t-s i gnificant-bit (ms b ) fir s t. t he tr ans mitter can be configured to exclude attachment of the computed cr c by s etti ng the cr cn opti on bi t i n the t ransmit configuration register (t con. cr cn). t hi s i s us eful for s ome br i dgi ng applications in which the original checksum must r emai n attached to the packet unti l the fi nal des ti nati on. 7.6.5 transmit protocol fsm t r ans mi t p r otocol f s m contr ol s tr ans mi s s i on of fr ames , defer s to acti ve car r i er s and col l i s i ons , monitors collis ion conditions , and initiates both backoff and re-trans mis s ion when needed. 7.6.5.1 interframe gap and deference deference is initiated when both xcrs and xcol have ter mi nated at the end of a fr ame. t he tr ans mi tter deference logic i ni tiates a 2-par t ti mer at the end of network activity. while this ti mer is running, no frame trans mis s ion will be initiated. t he fir s t part of the timer (interf rame s pacingp ar t1) i s us ed to obs er ve the networ k for tr ans mi s s i on activity by other stations. if this station is trans mitting, carrier is s ens ed, or collis ion is detected during this par t of the timer, the timer wi l l be r es et to z er o and held there unti l the termi nati on of li ne activity. when the fi rs t par t of the ti mer el aps es , l i ne acti vi ty i s no l onger obs er ved and the ti mer r uns to compl eti on. i f any f r ame i s queued up for tr ans mi s s i on at the moment of timer expiration, transmission will be initiated regardless of line activity. t he combination of interf rame s pacingpart1 and i nter f r ame s paci ngp ar t2 mak es up the inter-frame gap (ifg) as defined by the 802.3 s pecification. t he interf rame s pacingpart1 is 6.0 m s ec and interf rame s pacingpart2 is 3.6 m sec. 7.6.5.2 collision handling logic when collis ion is detected by the trans mitter s ection dur ing the firs t s lot time of an active tr ans mi s s ion, the trans mis s i on does not termi nate i mmedi atel y. i ns tead, the pr eambl e i s al l owed to fi ni s h and the j am s equence i s tr ans mi tted. t he j am s equence cons i s ts of 32 bi ts of logic 1s . i f collis i on is detected after the s lot time is pas s ed, the 83C795 wi l l abor t the tr ans mi s s i on wi th j am and wi thout retry and out of window collision bit is set in the transmission status register.
7.6.6 timers 7.6.6.1 slot timer duri ng tr ans mi t, the s lot timer s tar ts counting once the r ecei ver r ecogni z es that a car r i er i s pr es ent at the s tar t of a r etur ni ng pr eambl e. when back i ng off, the s lot timer s tar ts with the end of t x e for the collided frame and does not get reset by any other incoming frames . s lot time i s pr ogr ammable through the e nhancement regis ter. t he choices are 256-, 512-, and 1024-bit times . t he default value is 512-bit times . 7.6.6.2 backoff timer after a tr ans mi s s i on i s ter mi nated becaus e of a collision, a retransmission is attempted. t iming of i t i s deter mi ned by the tr uncated bi nar y ex ponenti al back off al gor i thm. t hi s al gor i thm i s : draw random integer r: 0 <= r < 2**k wher e k equal s the number of r etr i es al r eady on thi s transmission. k starts at 0. wait r number of slot ti mes and then s tart nor mal tr ans mi t deferr al . t he backoff ti mer i s a 12-bit counter that is i ni ti al i z ed to a r andom number when an attempted transmission results in a collision. the counter decrements once per slot time until it reaches zero. t he t r ans mi t p r otocol s tate machi ne uti l i z es thi s ti mer to i ns er t a var i abl e amount of del ay ahead of its attempt to r etrans mit the frame. t her e i s a s el ectabl e enhancement to backoff ti mer oper ati on whi ch caus es i t to s us pend counti ng whi l e ther e i s networ k acti vi ty and r es ume dur i ng idle times. in this mode of operation, the backoff ti mer conti nues to oper ate whi l e a car r i er s ens e remains from the initial collision but does not operate during any other carrier indication. t his is referred to as the s top backoff algorithm. it may put s tati ons that us e i t at a di s advantage when oper ating on the s ame networ k with s tations not utiliz ing it and caution in its us e is advis ed. t his al gor i thm can be enabl ed by s etti ng the s b ack bi t in the enh register. 7.6.6.3 collision counter all r etrans mis s i on attempts are counted by the collision counter. after the maximum number of attempts is reached (16), the trans mis s ion of the fr ame is abor ted, an inter rupt is generated and event i s r epor ted as an er r or i n the tr ans mi t s tatus register. 7.6.6.4 heartbeat detection after each tr ans mi s s i on, the tr ans mi t l ogi c opens a window 3.6 m sec long during which it looks for a pulse on the xcol signal. t his pulse is normally generated by the mau and is received through the au i i nter face. i f the pul s e i s r ecei ved, the cdh status bit of the tstat register is cleared. if no pulse is received during the window, the cdh bit is set. 7.6.7 transmitter operation 7.6.7.1 transmission initialization p ackets to be trans mitted are built in buffer memory by the hos t. t hes e pack ets mus t i ncl ude the da, s a, and data fi el ds . cr c i s not r ead fr om buffer memor y unl es s cr c gener ati on i s di s abl ed. t he tr ans mitter reques ts the frame from the dma when the t x p bi t of the cmd r egi s ter i s s et by the host. the tstart and tcnt registers must be pr oper l y pr ogr ammed pr i or to s etti ng t x p. once s et by the hos t, t x p can be cleared only by the dma after the trans mitter has s ignalled completion of an attempted tr ans mis s ion. 7.6.7.2 transmission process t he dma s tar ts to fi ll the trans mit f i f o wi th burs ts of data then notifies the trans mitter that it is ready for trans mis s i on. t he tr ans mi tter defers unti l the medi a i s cl ear and an i nter fr ame gap has pas s ed then generates preamble and s f d fields . i t then pulls bytes out of the trans mit f i f o, s er ializ es them, and s hifts bits to the output pins whil e computi ng the cr c on the pack et. t he dma al s o moni tor s the amount of r oom r emai ni ng i n the f i f o and i ni ti ates a bur s t of memor y tr ans fer s when ther e i s enough r oom for the entir e bur s t to fit.
once the dma has filled the t ransmit f if o with the l as t byte of the packet, i t s ets a fl ag. when the f i f o becomes empty, i t s i gni fi es the end of the fr ame. cr c computati on s tops and the cr c i s appended serially to the frame, most significant bit first. 7.6.7.3 transmit underrun i f the f i f o becomes empty befor e the i nter nal fl ag is set, it is considered a transmit underflow and is pos ted as a tr ans mi t er r or i n the t r ans mi t s tatus (t s tat ) register. in this case, transmission of the pack et i s abor ted and an i nter r upt can be gener ated. 7.6.7.4 early transmit underrun protection t his feature is us ed to facilitate initiation of transmission prior to completion of assembly of the outgoi ng fr ame i n the tr ans mi t buffer. e arl y tr ans mit under run protection i s contr ol led by two bi ts i n the command r egi s ter - cmd.di s e t ch and cmd.e ne t ch . s etting di s e t ch to 1 di s abl es ear l y tr ans mi t under r un check i ng and s etting e ne t ch to 1 enables checki ng. wr iti ng both bits to z ero l eaves tr ans mit checking in its previous state. s etting both bits to 1 is illegal. t his oper ati on wor k s the s ame as the command r egi s ter s tar t and s top bi ts for br i ngi ng the chi p on and offline. whi l e ear l y tr ans mi t under r un checki ng i s enabl ed, the memory addr es s is latched each time the hos t does a wr i te to the buffer memor y (the actual memor y addr es s i s us ed, not the hos t addr es s ). when the dma r eads packet data fr om the buffer memor y, the memor y addr es s i s compar ed to the mos t r ecen tl y - l atch ed memor y wr i te addr es s (wr i tten fr om the hos t wi th e t ch on onl y). t he dma di s ti ngui s hes between acces s es to des cr i ptor tabl e entr i es and actual pack et data. i f ear l y tr ans mi t check i ng i s on, and the dmas memor y r ead addr es s i s gr eater than the abs ol ute val ue of the l atched memor y wr i te addr es s , a "buffer underrun" condition is s et. t his condition abor ts the trans mitter which in tur n aborts the dma. t he condi ti on i s cl ear ed when the dma detects the abor t and clears the tr ans mit f i f o. t he trans mit abor t i s r epor ted as though i t wer e a f i f o under r un and both the t s t at .u nde r and i nt s t at .r x e flag bits are s et. 7.6.7.5 collisions when a collision is reported on the cd pin, the transmitter sends a 32-bit sequence composed of al l 1 bi ts as a j am s i gnal , then ter mi nates i ts tr ans mi s s i on . i f col l i s i on occur s dur i n g the pr eambl e of a fr ame, the r emai nder of the pr eambl e is sent before sending the jam signal. i f the col l i s i on occur r ed after the end of one s l ot ti me, trans mis s i on is abor ted without retr y after s ending a jam pattern. t his is considered an out-of-window collision and posts a status bit in the t s t at r egi s ter ( t s t at . owc) and i s a contr i butor to the t x e fl ag i n the i nt s t at r egi s ter. f or col l i s i ons that occur wi thi n the fi r s t s l ot ti me of a f r ame, a cou nt er of r etr i es i s i n cr ement ed and checked agains t the retr y li mit (16). i f the number of retries is less than the limit, a back-off delay (in uni ts of s l ot-ti me) i s chos en at r andom. t he tr ans mi tter then reques ts the frames r etr ans mi s s i on fr om memor y and del ay i s i ni ti ated. t he dma contr ol l er cl ear s out the tr ans mi t f i f o, loads its pointer to the s tar t of frame in memor y, and waits for the abor t s ignal to s ubs i de. t he f i f o is loaded in the same manner as it was initially. if the max i mum number of col l i s i ons (16) i s ex ceeded, tr ans mi s s ion is aborted without fur ther r etries and no back -off del ay i s ex ecuted.
7.6.7.6 extensions beyond 802.3 10base5 protocol t he 80 2 .3 1 0 b as e5 pr otocol uti l i z es fr ame l engths between 64 and 1518 bytes inclus ively. t he tr ans mi tter s ection is capable of s ending fr ames greater than 17 and les s than 32,768 bytes in length. transmission of longer or shorter frames than permi tted within the 10b as e5 definiti on may be useful in other variations of 802.3 protocols. when cons i der i ng the tr ans mi s s i on of gi ant fr ames on a non-802.3 network, be aware that very long fr ames can activate j abber detector s in exis ti ng 10b as ex mau s and r epeater s . t he us e of s uch frames in non-s tandard networks requires cons iderabl e planni ng and s ome caution. to s upport non-802.3 protocols, the 83C795s s lot ti me i s pr ogr am- s el ectabl e. choos e fr om 256 - bi t, 512-bit, or 1024-bit times. t he s top b ack off al gor i thm i s s el ectabl e for back off modi fi cati on fol l owi ng col l i s i ons . when operating in alt e go mode, detection of any pair of cons ecuti ve 0 bi ts wi thi n the pr eambl e caus es the r ecepti on of that fr ame to be abandoned. no error is reported. t he r con.r ca bit enables the receiver to abandon r ecepti on of any fr ame whi ch caus es a collision. no error is reported. 7.6.7.7 extended length when the xl e ngt h bit (gcr .7) is s et, the twi s ted- pai r por t can be connected to cabl es l onger than the 100-meter limit specified by the 802.3 specification
8.0 buffer structuring and data movement processes 8.1 transmit packets 8.1.1 single packet transmission a pack et for tr ans mi s s i on i s pl aced by the hos t i nto buffer memor y. t hi s pack et mus t i ncl ude the da, s a, and data f i el ds . t he pr eambl e, s f d, and cr c (normally) are not included in the buffer. if crc generation is suppressed, the crc field for the pack et i s al s o s uppl i ed by the hos t. t he pack et i s placed in a contiguous block of memory in the buff er , s tar ti ng on a 2 5 6 - byte boundar y. val i d 8 0 2 . 3 pack ets have at l eas t 4 8 bytes of data. if les s data is to be trans mitted on an 802.3 network, it is the responsibility of the host to build a packet with pad data included. t he 83C795 w ill transmit fr ames of any pr ogr ammed l ength ( gr eater than 1 7 bytes ), even thos e whi ch ar e too s hor t to be val i d fr ames i n an 8 0 2 . 3 networ k . dma wi l l tr ans fer the number of bytes pr ogr ammed i nto the t cnt h and tcntl register pair starting from address (t s t ar t * 100h). 8.1.2 multiple packet transmissions to support multiple transmissions per command, a tr ans mi t queue can be enabl ed by s etti ng the al t e go bi t i n the e nhancement r egi s ter (e nh . 5). i n thi s mode, a tabl e of fr ame des cr i ptor s def i nes the s tar ti ng l ocati on and l ength of al l enqueued transmissions. this descriptor table is processed in a circular manner by the lan controller. t he table is treated as a r ing of entr ies whos e s tar ti ng and endi ng poi nts ar e defi ned by a pai r of regis ters (t b e gin and t e nd) in the l an contr ol l er. t hes e r egi s ter s ar e i ni ti al i z ed wi th the upper 8-bits of addr es s for the fi rs t l ocation of the table and the fir s t location after the end of the table. t e nd is not within the table. when table proces s ing r eaches the locati on defined by t e nd, it is s witched back to tbegin. the table must be aligned with 2 5 6 byte boundar y i n the buffer memor y. e ach entr y is 8 bytes long. t he format of this buffering is defi ned i n f i gur e 8 - 1 . to send multiple transmissions, the driver builds the fr ames i n buffer memor y i n the s ame conti guous for m pr es ently ex pected. t he dr i ver then adds an entry for each fr ame into a table of trans mit des cr iptors . t hi s entry contains the s tarti ng locati on and l ength, and tr ans mi t conf i gur ati on for each fr ame i n the tr ans mi t queue. p l aces ar e pr ovi ded i n the tabl e for r etur n of the t r ans mit s tatus (t s t at ) r egi s ter and col l i s i on count as s oci ated wi th each tr ans mi s s i on. a s i mpl e s emaphor e pr otocol wi l l be used to control ownership of transmit buffers. t he lan controller keeps a pointer in the t tabh and t t ab l r egis ter s to the tr ans mi t des cr iptor tabl e. t hi s poi nter i s i ni ti al i z ed by the dr i ver when the table is fi rs t buil t and s hould not need re-initializ ation thereafter. when trans mit command has been s et and devi ce i s onl i ne, tr ans mi t begi ns fr om the entry poi nted to by the t t ab h and t t ab l registers. t he lan controller first checks the t stat field. if it encounters a field equal to ff, it wil l attempt to trans mit the frame pointed to by the entry. t he s tatus fi el d wi ll be changed to z er o after the r emai nder of the entr y has been r ead. when i t encounters a t s t at field not equal to f f, no frame wil l be s ent, the tr ans mit complete inter rupt will be s ent and the f i el d wi l l not be al ter ed. if the frame is marked for transmission, the dma controller loads its t s tart h, t s tart l, t cnt h, tcntl, and tcon registers from the descriptor. t s t at gets mar ked as havi ng been opened by the lan controller and transmission proceeds as with s i ngle tr ans mi s s ions except that when the transmission has completed, the transmit status and col l i s i on count ar e moved by d ma i nto the tabl e. t he tabl e poi nter i s updated and tr ans mi s s i on of nex t entr y begi ns . if a transmit abort occurs (too many collisions) the tr ans mi tter wi l l s top pr oces s i ng the chai n and pos t the current trans mit and interrupt s tatus . i f the cmd.s t p bi t is s et, the tr ans mi s s ion of any ongoi ng fr ame pr oceeds unti l compl eti on or abor t but no successive frames in the chain are processed. the ttab indices will point to the first unpr oces s ed fr ame i n the tabl e s o that none ar e lost. an al ter nati ve mode of contr ol l i ng the tr ans mi t inter rupt can be enabl ed by the e ot i nt bit i n the e nhancement (e nh ) r egi s ter. when enabl ed, the trans mit inter rupt will be generated only upon
figure 8-1. multiple frame transmit buffer format
completion of the tr ans mi t chain. nor mal mas ki ng appl i es on top of thi s del ay mechani s m. without enabling this new mode of controlling tr ans mi t interr upts , an inter rupt will be generated on a fr ame by frame bas is but the interr upt s tatus may not be cur r ent by the ti me i t can be r ead by the dr i ver software. 8.1.2.1 ownership of buffers t he t s t at fi el d of the tabl e entr y i s us ed to contr ol owner s hi p of the fr ame buffer s . h ands hak e over control of trans mit frame buffers is governed by the following conventions : tstat field value meaning tstat field = 00 83C795 has begun transmission. tstat field > 00 and < ffh frame completed. tstat field = ff assembled frame, not yet transmitted. table 8-1. tstat field values t he dr i ver s oftwar e fi l l s the t s t at tabl e entr y wi th f f h when i t r el eas es the fr ame to the l an contr ol l er for transmission. when transmit command has been s et and devi ce i s onl i ne, the dma l ook s at tstat field. if it encounters a field = ff, it will attempt to trans mit the fr ame poi nted to by the entr y. t he s tatus fi el d wi l l be changed to z er o after des cr i ptor entr y i s r ead and tr ans mi tter commi ts to s endi ng. i f dma encounter s a t s t at fi el d gr eater than or l es s than f f h, no fr ame wi l l be tr ans mi tted, the trans mit complete i nter rupt will be s ent. t he field is not altered. when a transmission completes, the contents of t s t at r egis ter wi ll be moved into that location. 8.1.2.2 modifying the transmit queue t o add a fr ame to the tr ans mi t queue, bui l d the fr ame i n buffer memory then find the table entry fol l owi ng the l as t enqueued fr ame. e nter the des cr i ptor for the new fr ame wi th a t s t at that i s neither 00 nor f f in value. when des criptor is compl ete, wr i te t s t at wi th f f . t he des cr i ptor entr y fol l owi ng the l as t enqueued fr ame entr y mus t have i ts t s t at val ue mar k ed wi th a non- f f val ue. t hat defi nes the end of the enqueued fr ames for the dma. s et the t x p bit of the command r egi s ter to ens ure that the new tr ans mis s ion goes out. t he t x p bit can be wr i tten r egar dl es s of compl eti on s tatus and wi l l ens ur e that the lates t fr ame does get trans mitted. i f the l an contr ol l er r eaches the end of the tr ans mi t queue befor e the new fr ame has been added, a tr ans mi t complete interr upt is generated for the old por ti on of the queue and another tr ans mi t compl ete i nter r upt wi l l be gener ated when the added por ti on compl etes . t he dri ver s hould not attempt to alter any buffer ed fr ame whos e t s t at i s ei ther 00 or f f whi l e cmd.t x p is turned on. wai t unti l al l trans mis s ions are complete or s et the cmd.s t p bit and wait for the s t op s tatus to be confir med in the i nter rupt s tatus r egi s ter. e xami ne t s t at tabl e entr i es to deter mi ne whi ch fr ames have been tr ans mi tted. t hos e whos e entr i es ar e f f have not been opened by tr ans mitter. r efer to t ables 8-2 and 8-3 for a s ummary of the tr ans mi t des cr i ptor tabl e f or mat. 8-bit memory 16-bit memory d15-d08 d07-d00 colcnt tstat colcnt tstat tstarth tstartl tstartl tcnth tcntl tstarth not used tcon tcntl tcnth tcon not used table 8-2. format of transmit descriptor table
reg description colcnt wri tt en w it h t he number o f collisions experiences by the lan controller while attempting to transmit this frame. tstat this entry in the table is used to control ownership of the frame buffer: tstat = 00 means the 83C795 has begun transmission tstat>00 but 83C795 is initi al iz ed. r s t ar t points to the fi rs t buffer in the ri ng and r s t op points to the buffer after the las t one in the ri ng. e ach pack et r ecei ved wi l l be s tor ed i nto one or mor e of thes e buffer s , wi th a 4 - byte header i ns er ted at the s tar t of the f i r s t buffer. f i gur e 8 - 2 detai l s the f or mat of a r ecei ved pack et i n memor y.
figure 8-2. receiver buffer format
f rames that extend to the buffer des ignated by r s t op ar e conti nued i n the buffer des i gnated by rstart and successive locations. rstop may be either gr eater than r s t ar t +1 or les s than rstart. making rstop equal to rstart or rstart + 1 leads to unpredictable results. the r el ati ons hi p of thes e r egi s ter s to r i ng pl acement i n memory is illus trated in f igure 8-3. u p to 254 buffers can be all ocated to the r ing. t he receiver dma will us e as many as required to s tore a pack et. t hi s al l ows the chi p to be conf i gur ed to r ecei ve fr ames near l y as l ong as 6 4 k bytes . t hi s can be us eful i n cus tomi z ed cs ma networ k s ; however, allocating s o many buffers to the r ecepti on pr oces s l eaves ver y l i ttl e capabi l i ty for buff er i ng tr ans mi t f r ames al though i t i s wi thi n the capabili ty of the 83C795. t he r ecei ve dma uti l i z es two addi ti onal r egi s ter s to manage the buffer r i ng. t hes e ar e the cur r ent p age register (curr) and the boundary page register (b ou nd). t he cu r r r egis ter points to the fi rs t buffer that is not part of a completely received pack et. when r dma i s s tor i ng a fr ame, thi s r egi s ter points to the s tart of the fr ame bei ng s tor ed. when r dma is not s toring a frame, it points to the firs t buffer that wi l l be us ed for the nex t fr ame to be received. t he b ou nd r egi s ter pr otects r ecei ved fr ames fr om being over wri tten by later fr ames . i t points to the fir s t buffer in the ri ng that is not to be overwr itten. figure 8-3. ring buffer structure
when the receive dma proces s attempts to open the buffer that b ou nd points to for s tor age of a packet, it aborts the reception and s ets the i nt s t at .ovw flag (in the interrupt s tatus r egi s ter ) and the r s t at . mpa bi t (i n the r ecei ver s tatus r egi s ter ). t he pr otected buffer i s not wr i tten to. normal ly, b ou nd is s et up to point to the ol des t r ecei ved pack et i n the r i ng. t hi s poi nter can be managed by the hos t. t o di s car d an unwanted fr ame, the hos t may s i mpl y r ewr i te b ou nd to poi nt to the next packet. a good practice is to write zeros into the fir s t byte of the dis car ded packet to pr event futur e interpretati on as a r eceived packet. when b ou nd and cu r r have the s ame val ue, the r i ng may be ei ther ful l or empty. t he 83C795 can distinguish between full and empty rings. cu r r is updated by the dma contr oller at the end of a fr ame r ecepti on. t he r i ng i s cons i der ed ful l i f thes e two r egi s ter s ar e equal and the dma contr ol l er updated cu r r mor e r ecentl y than the hos t updated b ou n d. conver s el y, when data i s being removed from the ring, the host updates b ou nd after r emoval . when i t has been advanced pas t the end of the l as t r ecei ved fr ame, i t s houl d have the s ame val ue as cu r r . t he chi p tr eats the r i ng as empty when thes e two r egi s ter val ues ar e equal and b ou nd has been updated after cu r r . when initializing the buffer ring, bound and curr may be gi ven the s ame or di ffer ent val ues . t hes e r egis ter s may be i ni tializ ed to point to any buffer withi n the r ing. t hey may point to r s t ar t but may not point to r s t op. i f cu r r poi nts outs i de the ring, the rdma will store frames outside the ring in an unpredictable manner. if bound points outside the r i ng, the r ecei ved fr ames wi l l not be pr otected fr om overwrites by later frames. f igure 8-4 illus trates the buffer ring in two common states. the top ring, initrbuf, illustrates the relations hip between thes e pointers in a typical ring initialization. t he bottom ring, r buf, s hows a ring that has r ecei ved a few fr ames - the nor mal condition for the r ing. figure 8-4. receiver buffer ring 1
f igure 8-5 s hows the s ame ring after proper r emoval of the ol des t r ecei ved pack et. t he top r i ng, fullring, shows a ring that is completely full. the bottom r i ng, ove r f l ow, s hows a r i ng on the ver ge of over fl ow. 8.2.1.1 automatic ring wrapping automatic ri ng wrapping enables the hos t to r ead a contiguous block of data from the buffer r am without havi ng to check whether the block is s o long that the acces s wr aps ar ound the end of the buffer r i ng. t hi s i s accompl i s hed by checki ng whether the next val ue to be l oaded i nto the memor y caches buffer counter i s equal to the r egis ter r s t op. i f this is tr ue, then the value of the r s t ar t regis ter is loaded into the counter ins tead. t he memory caches host counter is left unchanged so the host can conti nue acces s i ng memor y pas t the end of the r i ng, but i ns tead r ecei ves the cor r ect data fr om the s tar t of the r i ng. t he compar i s on i s onl y made when the counter i s incrementing s o it is not pos s i bl e to s tart the block of data pas t the r ings end. als o, since the host is sending addresses that are greater than the end of the r ing, it i s r equir ed that the 83C795s memor y s pace extend beyond the end of the r i ng. t hi s can be accompl i s hed by ar r angi ng the memor y s pace s uch that the tr ans mit buffers come after the r ecei ve buffer r i ng. t hi s featur e i s enabl ed by s etti ng the wr ap e n bit (u b r cv.0). f or more on this , refer to page 40. 8.2.1.2 ring-empty bit t hi s i s a r ead- onl y bi t l ocated at u b r cv. 2 whi ch indicates to the hos t that ther e ar e no completely r ecei ved fr ames i n the buffer r i ng yet. t he hos t check s thi s bi t after i t f i ni s hes r ecei vi ng a fr ame and qui ckl y deter mi nes whether ther e ar e mor e fr ames to copy. t his bit i s s et when b ou nd equals cu r r . b ou nd i s updated after cu r r . s ince this bi t is onl y cleared for completely received fr ames , another method mus t be us ed to determi ne i f ther e i s a par ti al fr ame i n the buffer that ex ceeds figure 8-5. receiver buffer ring 2
the early receive threshold (early receive mode onl y). t hi s i s done by checki ng the i nter r upt s tatus r egi s ter after checki ng the r i ng-empty bi t. 8.2.2 linked-list receiver buffering l i nk ed- l i s t r ecei ver b uffer i ng i s enabl ed by a bi t i n the e nhancement r egi s ter, e nh .al t e go, and i s an alternative to receive ring form of buffering. in this mode, the r eceiver dir ects its input to a gr oup of i ndi vi dual l y- s i z ed buffer s that ar e not neces s ar i l y contiguous . all buffers need not be the s ame s iz e. mul ti pl e buffer s can be chai ned together as needed to receive an incoming frame. t hes e buffer s are linked together vi a a tabl e of buffer descriptors which define the starting location, size, and usage of all receiver buffers. t his table contr ol s both the r ecei ved fr ames and the avai l abl e buff er pool . t he des cri ptor table is treated as a r ing of entri es whos e s tar ti ng and endi ng poi nts ar e defi ned by a pair of regis ters (r b e gin and r e nd) in the l an contr ol l er. t hes e r egi s ter s ar e i ni ti al i z ed wi th the upper 8-bits of addr es s for the fi rs t l ocation of the table and the fir s t location after the end of the table. r e nd is not within the table. when table pr oces s i ng r eaches the l ocati on defi ned by r e nd, it is switched back to rbegin. t he table must be aligned with 256-byte boundary in the buffer memory. e ach entry is 8-bytes long. t he format of thi s buffer i ng ar r angement i s depi cted i n f i gur e 8 -6 . figure 8-6. linked-list buffer format
t he l an contr ol l er k eeps a poi nter (r egi s ter s rtabh and rtabl) to the receive descriptor tabl e. t hi s poi nter i s i ni ti al i z ed by the dr i ver when the table is fi rs t buil t and s hould not need re-initialization thereafter. when the l an contr ollers dma becomes acti ve to r ecei ve a fr ame, i t wi l l us e r t ab as a poi nter to the firs t free receive buffer. r s t at field of des criptor is checked to s ee if the buffer is free (r s t at =00). if fr ee, the s iz e and s tarti ng location of the buffer are l oaded f r om the des cr i ptor and r ounded down to even val ues . s tor age of the fr ame i nto the buffer begi ns . t he val ue of r t ab i s s aved at the s tar t of r ecepti on for each fr ame i n cas e the fr ame gets abor ted and r t ab has al ready been updated to the next table entry. while a frame is being buffered, the l an controller wil l follow the entri es in the des cr iptor table to obtain addi tional buffer s as needed to recei ve the entir e frame. u pon completion, the des criptor for the firs t buffer of that fr ame i s wr i tten wi th the r ecei ver s tatus regis ter and the total byte count for that frame. t he by te count i ncl udes s tor age of the r ecei ved f cs . s houl d a par ti al l y r ecei ved fr ame be r ej ected by the lan controller, it will reclaim the buffers by resetting the r t ab poi nter to i ts val ue pr evi ous to s tar t of reception of this frame. t o add fr ee buffer s to the end of the des cr i ptor tabl e, fi ll i n the fir s t new tabl e entr y wi th r s t at =non-z ero, bui l d al l other tabl e entr i es wi th r s t at = 0 , then change the fir s t r s t at to 00 to indicate availabili ty.
9.0 electrical specifications 9.1 absolute maximum ratings supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v ttl input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C 5.5v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 C 5.5v differential output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C 16v differential output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40ma storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c (-85f) to 150c (302f) absolute maximum ratings indicate limits beyond which permanent damage may occur. continuous oper ati ng at thes e l i mi ts i s not r ecommended; oper ati on s houl d be l i mi ted to condi ti ons s peci fi ed under " dc oper ati ng char acter i s ti cs ." 9.2 recommended operating conditions supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c (32f) to 70c (158f) 9.3 dc operating characteristics t a = 0 c (32 f ) to 70 c (158 f ) v dd = +5v 5% note all currents into device pins are positive. all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. 9.3.1 input pins symbol parameter min max unit conditions i dd supply current 110 ma v ih input high voltage (ma09-ma00) 2.0 v internal pull-down resistor val ue between 35k w and 150k w . input high voltage (ma07-ma00, me mr , me mw, sbhe) 1.65 1.94 v v when v cc =4.5v when v cc =5.5v for s chmitt-triggered inputs, t t l-compatible levels input high voltage (x 1) 3.5 v cmos level input input high voltage (all other inputs) 2.0 v ttl levels, high impedance
symbol parameter min max unit conditions v il input low voltage (ma09-ma00) 0.8v internal pull-down resistor val ue between 35k w and 150k w . input low voltage (ma07-ma00, me mr , me mw, sbhe) 1.04 1.20 v when v dd =4.5v when v dd =5.5v internal pull-down resistor val ue between 35k w and 150k w . input low voltage (x 1) 1.5v cmos level input input low voltage (all other inputs) 1.04 1.20 v v when v dd =4.5v when v dd =5.5v v hys i nput vol tage h ys ter es i s (s chmitt inputs ) 0.40 0.39 0.51 0.59 v v when v dd =4.5v when v dd =5.5v v t+ input voltage t t l + (s chmitt inputs ) 1.45 1.65 1.65 1.94 v v when v dd =4.5v when v dd =5.5v v t- input voltage t t l- (s chmitt inputs ) 1.04 1.20 1.18 1.35 v v when v dd =4.5v when v dd =5.5v v ds di ffer enti al s quel ch t hr es hol d (r x , cd ) -175 -300 mv di ffer enti al s quel ch t hr es hol d (t p r ) 300 500 mv i il input low current (r x , cd , t pr ) -500 ua input low current (ma09-ma00, md07-md00, me mr , me mw, sbhe) -25 -200 ua input low current (x 1) -50ua input low current (all other inputs) -10ua i ih input high current (r x , cd , t pr ) 500 ua input high current (x 1) 50ua input high current (all other inputs) 10ua i in input current (cap ) -1.0 -1.0 ma when v in = 2.5v table 9-1. input pin values
9.3.2 output pins symbol parameter min max unit conditions v ol output l ow vol tage (x 2) 0.7 v iol = 8ma output l ow vol tage (t p x 1 ) 0.6 v i ol = 30ma output l ow vol tage (t p x 2 )0.75vi ol = 14ma output l ow vol tage ( zws) 0.4 v i ol = 24ma output l ow vol tage (gp ou t , ior dy, io16cs , m16cs , sd00-sd16) 0.4 v i ol = 24ma output l ow vol tage (al l other outputs ) 0 .4 v i ol = 4ma v oh output h i gh vol tage (x 2) 3.5 v ioh = -100ma output h i gh vol tage (t p x 1 )v dd -0.6 v i oh = 30ma output h i gh vol tage (t p x 2 )v dd -0.75 v i oh = 14ma output h i gh vol tage ( zws) 2.4 v i oh = 24ma output h i gh vol tage (gp ou t , ior dy, io16cs , m16cs , sd00-sd16) 2.4 v i oh = 24ma output h i gh vol tage (al l other outputs ) 2. 4 v i oh = 4ma v od di ffer enti al output vol tage (t x ) -500 500 -1200 1200 mv mv 78 w ter mi nati on and 150 w fr om each output to v dd. v out output vol tage (b s r ) 2.25 2.75 v 10.0 k w ex ter nal resistor to v dd . output vol tage (os r ) 2.25 2.75 v 24.9 k w ex ter nal resistor to v dd . table 9-2. output pin values
10.0 ac operating characteristics and timing t his s ections provides timing diagrams and parameters for 83C795 s ignals . table 10-1 indicates the timing diagrams i ncluded in thi s s ecti on. t able 10-2 i ndicates the timing par ameter s applying to each timi ng di agr am. e x cept wher e other wi s e noted, ti mi ng uni ts ar e i n nanos econds . figure title 10 - 1 s ys tem cl ock t i mi ng 1 0 - 2 r egi s ter acces s t i mi ng C r ead 1 0 - 3 r egi s ter acces s t i mi ng C w r i te 10-4 16-bit r egis ter acces s (i/o pipe only) 10-5 host memory access (16-bit, zws) 10-6 host memory access (8-bit, no zws) 10-7 host memory access (8-bit, zws) 10-8 host memory access (8-bit, no zws) 10-9 rom access (8-bit only, read only) 10 - 10 dma or memor y cache wr i tes 10 - 11 dma or memor y cache r eads 10-12 e e pr om interface 10-13 t r ans mi t t iming C s tar t of t r ans mis s ion 10-14 transmit timing C end of transmission (last bit = 1) 10-15 transmit timing C end of transmission (last bit = 0) 10 - 16 r ecei ve t i mi ng C s tar t of p ack et 1 0 - 1 7 r ecei ve t i mi ng C e nd of p ack et 10-18 collision t iming C aui 10-19 collision t iming C t p 1 0 - 2 0 l oopback t i mi ng 10-21 s qe test t iming 10-22 link tes t puls e 10-23 r om dump (tes t mode) table 10-1. list of timing diagrams
parameter description min typ max units t 1 r egi s ter r ead: data val i d del ay 3 C 5 cycl es t2 register read: data hold time C C 15 nsec t 6 addr es s s etup for r egi s ter i /o C C 18 t 7 address hold for register i/o C C 0 t 8 iordy inactive delay from i/o strobe C C 20 t 9 iordy active delay from x1 C C 28 t 10 i or dy tr is tate delay from i /o s tr obe C C 14 t 11 r egis ter wr ite: data s et up ti me 15 C C t 12 r egis ter wr ite: data hold ti me 20 C C t13 iow active time 300 C C t14 ior active time 300 C C t15 mcs 1 6 acti ve fr om l a addr es s ( fine16=0) C C 15 t20 m1 6 cs i nacti ve fr om l a addr es s C C 1 3 t21 io16cs active from sa address C C 17 t22 io16cs inactive from sa address C C 15 t 23 i or dy acti ve del ay fr om h os t cl k C C 2 5 t27 z ws tris tate delay fr om s me mx s tr obe C C 11 t28 z ws acti ve fr om me mx s tr obe (1 6 bi t) C 9 1 3 t29 z ws tris tate from me mx s trobe C C 11 t30 s me mr acti ve to i nacti ve 4 2 5 C C t31 smemr active to r omcs active C C 155 t 32 r omcs active to s d valid C C 270 t 33 r om read: data hold time 15 C C t 35 s a addr es s s etup for me mx s tr obe 18 C C t 36 s a adress hold for me mx strobe C C 0 t 41 ior dy inactive delay from me m s trobe C C 23 t 42 ior dy active delay from x1 C C 27 t 43 i or dy tr is tate delay from me m s tr obe C C 17 t46 z ws active delay from hos t cl k C C 17 t 48 e e cs s et up ti me 100 C C t49 eecs hold time 100 C C t50 r l e d s et up time 100 C C t51 rled hold time 100 C C t52 eedo delay C C 200 table 10-2. timing parameters
parameter description min typ max units t 5 3 ma addr es s acti ve del ay fr om x 1 C C 2 6 ns ec t 5 4 ma addr es s i nacti ve del ay fr om x 1 C C 1 0 t57 ramwr active delay from x1 C C 11 t58 ramwr inactive delay from x1 C C 9 t59 ma address set up to ramwr, ramoe 10 C C t 6 0 ma addr es s hol d fr om ramwr 15 C C t 6 1 data val i d del ay ti me f r om x 1 C C 2 4 t 6 2 data hol d ti me fr om ramwr 15 C C t64 ramoe active delay from x1 C C 12 t65 ramoe inactive delay from x1 C C 9 t 6 6 data s etup ti me to x 1 1 2 C C t 6 7 data hol d ti me to x 1 0 C C t68 xtxe setup time to xtxc 25 C C t69 xtxe hold time from xtxc 0 C C t70 xtxd hold time from xtxc 0 C C t 71 t x outputs delay to i dl e C C 310 t 72 t x outputs stay high before idle 240 C C t73 xtxd setup time to xtxc 20 C C t 74 t x outputs delay from xt xc - aui C C 100 t x outputs del ay fr om x t x c - t p C C 1 0 0 t 75 xcol active delay - aui C C 60 t76 xcol active delay - tp C C 900 t 77 xcol inactive delay - aui C C 350 t78 xcol inactive delay - tp C C 160 t 79 xcr s active delay - aui C C 300 xcrs active delay - t p C C 60 t 80 xcr s inactive delay - aui C C 250 xcr s inactive delay - t p C C 160 t 81 differential input reject pulse width - aui 8 C 35 differential input reject pulse width - t p 8 20 30 t 82 acqui s i tion time from p l l - au i C C 700 acquisition time from pll - t p C C 950 t 83 xrxd stable from xrxc 40 ? ? t 84 s qe tes t start delay - t p ? 900 ? t 85 s qe tes t duration - t p ? 1000 ? t 8 6 l oopback s etup ti me ? ? ? t 8 7 l oopback hol d ti me ? ? ? table 10-2. timing parameters (cont.)
parameter description min typ max units t 88 x 1 cl ock per i od 45 5 0 C ns ec t 8 9 x 1 cl ock wi dth hi gh 2 2 . 5 2 5 C t90 x1 clock rise time C C 3 t 91 x1 clock fall time C C 3 t 9 2 x 1 cl ock wi dth l ow 2 2 . 5 2 5 C t 9 3 l i nk tes t pul s e wi dth C 1 0 0 C t94 i/o write recovery time 2 C C cycles table 10-2. timing parameters (cont.) notes 1. all numbers are in nanoseconds except where otherwise designated. 2. all outputs are measured under 50pf load. 3. the external manchester encoder/decoder port is multiplexed out on other pins in certain test modes only. use the table below to determine which manchester signals correspond to which pin names. manchester signals 83C795 i/o pins xtxd irq1 xloop irq2 xcrs irq3 xrxc irq4 xrxd irq5 xcol irq6 xtxc irq7 xtxe romcs table 10-3. test pin i/o matching refer to chapter 4 for more details.
x1 t90 t91 t88 t92 t89 10% 90% figure 10-1. system clock timing x1 bale address valid t6 t7 t10 t9 t1 t2 t8 t14 sd7 - sd0 data valid iordy ior sa15 - sa00 figure 10-2. register access timing - read
x1 bale address valid t6 t7 t10 t9 t11 t12 t8 t13 sd0 - sd7 data iordy iow sa15 - sa00 figure 10-3. register access timing - write t43 t42 t41 iordy x1 sbhe address valid t21 t6 t7 t22 ior, iow io16cs sa15 - sa00 figure 10-4. 16-bit register access (i/o pipe only)
t43 t28 iordy hostclk sbhe bale address valid valid t20 t15 t29 t35 t36 memr, memw m16cs zws sa15 - sa00 la23 - la17 figure 10-5. host memory access (16-bit, zws)
t43 t42 t41 iordy x1 sbhe bale address valid valid t20 t15 t35 t36 memr, memw m16cs sa15 - sa00 la23 - la17 figure 10-6. host memory access (16-bit, no zws)
t46 t27 zws t43 t23 t41 iordy hostclk sbhe bale address valid valid t35 t36 smemr, smemw sa15 - sa00 la23 - la17 figure 10-7. host memory access (8-bit, zws)
x1 t43 t42 t41 iordy sbhe bale address valid valid t35 t36 smemr, smemw sa15 - sa00 la23 - la17 figure 10-8. host memory access (8-bit, no zws)
t32 t31 t33 sd7 - sd0 data valid romcs hostclk address valid t35 t30 t36 smemr sa15 - sa00 figure 10-9. rom access (8-bit only, read only)
figure 10-10. dma or memory cache writes
figure 10-11. dma or memory cache reads
figure 10-12. eeprom interface
figure 10-13. transmit timing - start of transmission
(last bit = 1) figure 10-14. transmit timing - end of transmission
(last bit = 0) figure 10-15. transmit timing - end of transmission
figure 10-16. receive timing - start of packet
figure 10-17. receive timing - end of packet
figure 10-18. collision timing - aui figure 10-19. collision - tp
figure 10-20. loopback timing figure 10-21. sqe test timing
figure 10-22. link test pulse
figure 10-23. rom dump (test mode)
11.0 package dimensions f igure 11-1 illustrates the 160-pin pqf p package. figure 11-1. 160-pin pqfp package
letter min nom max min nom max a4.07l1.60 a1 0.05 0.5 p 0.65bsc a2 3.10 3.67 q 0 7 d 30.95 31.20 31.45 w 0.20 0.40 d1 27.90 28.00 28.10 r 1 0.20 e 3 30.95 31.20 31.45 r 2 0.30 e 1 27.90 28.00 28.10 t d 30.45 h 0.10 2.20 t e 30.45 l 0.65 0.80 0.95 table 11-1. package dimensions notes: 1. coplanarity is 0.100 mm. maximum. 2. tolerance on the position of the leads is 0.120 mm maximum. 3. package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm. 4. dimensions t d and t e are important for testing by robotic handler. 5. dimensions for foot length l when measured at the centerline of the leads are given at the table. dimension for foot length l when measured at the gauge plane 0.25 mm above the seating plane, is 0.78-1.03 mm. 6. controlling dimension is millimeter. 7. details of pin 1 identifier are optional but must be located within the zone indicated.
! 10base-t status led driver reading back 29 16-bit host bus indicator 51 16-bit response to host access 51 83c585 compatibility with 83c790 19 83c690 similarities to 83c790 1 83c790 operating conditions 90 a abort transmission field 39 ac operating characteristics 93 accessing lan register 67 address decoders 46 address generation path 49 address modifiers 48 address recognition logic 71 aen 6 alignment error counter register 23 altego 80 see buffering format selection arbitration internal bus 50 aui collisions 6 aui differential driver transmitter 74 aui differential receiver receiver 69 auto-configuration ports 57 automatic polarity correct field 29, 75 automatic ring wrapping 87 avoiding sa and la line conflicts 51 b backoff counter field 24 backoff timer 77 bale 6 bios page register 17 block diagram 1 board id register 19 boundary page register 85 broadcast frames 71 receiving 32 bsr 6 buffer memory decoding 47 buffer room remaining count registers 32 buffer structure and data movement processes 80 - 89 buffer underrun field 39 buffer window size field 20 buffering format selection field 26, 79 burst starting address 35 c cap 6 carrier sense 69 carrier sense lost field 39 carrier sense monitoring 39 cd 69 cd+/cd- 6 chaining multiple buffers 88 check addresses/ crc without buffering field 31 chip type indication field 18 collision count register 24 collision counter 77 collision counter field 25 collision detect heartbeat field 39 collision detection 78 receiver 69 collision handling logic 76 collision tran slator 74 command register 23 - 24, 78 configuration register 55 configuring plug and play as a boot card 64 configuring plug and play with an i/o-mapped pipe 64 control register 14 controller registers 12 conventions 3 counter overflow enable field 27 counter overflow field 28 counting packet collisions 24 crc checking 71 crc error counter 25 crc error field 33 crc generation inhibition field 37 crc generator 76 wake 59 current frame buffer descriptor pointer registers 25 current frame buffer pointer register 25 d data configuration register 26 data path description 3 index
dc operating characteristics 90, 92 deserialization of the receiver 70 designating linked-list buffering 26 designating ring buffering 26, 79 designating the next dma buffer 30 determining the cause of an interrupt 28 dma controller 65 assembly and disassembly latches 65 loopback testing 65 memory interface 68 memory interface unit (miu) 65 microcontroller 67 dma controller next buffer register 30 dma memory interface 67 dma microcontroller 67 e early receive warning 71 early receive warning count register 71 early receive warning enable field 27 early receive warning field 28 early transmit checking 78 early transmit checking (enetch & disetch) fields 24 early transmit underrun protection 78 eecs 6 eedo 6 eerom interface overview 54 recall operations 54 register logic 55 storage of user-defined initial configurations 57 storage of user-defined lan address 57 storage operations 56 unlocking write operations 56 eerom address field 15 eerom controller and its utilization 53 eerom register 14, 54 electrical specifications 90 - 92 emitter-coupled logic 74 enable interrupts field 17 end-of-transmit interrupt 26 enhancement register 23, 26, 77 erfbit 72 erw interrupt 71 extensions beyond 802.3 79 external power supply control 64 f features 1 fifo structure 68 fifo overrun field 33 fifo underrun field 39 frame alignment error field 33 functional description 3 g general control register 21 - 22 general description 1 general purpose output (gpout) field 21, 64 giant frames accommodating on a non-802.3 network 79 gpout 64 gpx pin value selection 16 group address recognized field 33 h hardware support register 16 heartbeat detection 77 heartbeat test 75 high ram address field 20 host bit width selection 16 host interface address decoders 46 basic functions 44 eerom controller and its utilization 53 i/o address decode 50 i/o-mapped pipe 46 internal bus arbitration 50 interrupt request control logic 52 introduction 44 memory address generation 48 memory bus structure 51 memory cache 44 plug and play 57 zero wait state response to the host 50 host interface internal registers introduction 14 host registers bios page register 17 board id register 19 control register 14 eerom register 14 general control register 21 - 22 hardware support register 16 i/o address register 19 lan address registers 18 pos id registers 19 ram address register 20 rom control register 20
hostclk 6 hram 64 i i/o address decode 50 i/o address register 19 i/o-mapped pipe 46 igsm deferral field 33 init pins see ma03-ma00 initialization 53 initialize eerom jumpers 15 initrbuf 86 inter-frame gap definition 76 interframe gap and deference 76 internal bus arbitration 50 lan controller 67 interrupt disabling 52 interrupt mask register 27 interrupt on end-of-transmit field 26, 82 interrupt request control 52 interrupt request field 21 interrupt status field 16 interrupt status register 28 intmask 71 ior 6 iordy 6, 44, 50, 67 iow 6, 67 ipl rom code 51 irq lines 6 j jabber protection 75 jumper6 22 l la address bus 7 lan address registers 18 lan controller dma 65 dma memory interface 67 dma microcontroller 67 fifos 68 how to access registers 67 internal bus arbitration 67 overview 65 - 79 receiver network interface 68 lan controller registers alignment error counter register 23 buffer room remaining count registers 32 collision count register 24 command register 24 crc error counter 25 current frame buffer descriptor pointer registers 25 current frame buffer pointer register 25 data configuration register 26 dma controller next buffer register 30 enhancement register 26 interrupt mask register 27 interrupt status register 28 introduction 23 lan command register 23 manchester management register 29 missed packet error counter register 29 multicast filter table registers 27 offset addressing 23 page select 24 receive boundary page register 23 receive buffer end register 32 receive buffer starting address register 30 receive buffer table pointer registers 34 receive burst starting address registers 30 receive byte count registers 31 receive configuration register 31 receive packet status register 33 receive start page register 33 receive stop page register 34 received byte count register 26 station address registers 34 transfer buffer end register 37 - 38 transfer count registers 37 transmit buffer pointer registers 39 transmit buffer starting address register 36 transmit burst starting address registers 35 transmit configuration register 36 transmit frame length registers 36 transmit start page registers 38 transmit status register 38 led test and enable fields 29 leds 76 link integrity test field 21, 75 link integrity test function 21, 75 link status led readback field 29 linked-list buffering introduction 23 selecting 26 linked-list buffering format 88 linked-list receiver buffering 88 lit 22, 75 lled 7, 75 loopback mode 69 lpoe 7
m m16cs 7, 51 m16en 17 m16en bit 45 ma lines 7 mac protocol type select field 16 mac receiver address recognition logic 71 basic functions 70 crc checking 71 interface to manchester decoder 70 loopback paths 70 receive deser ialization 70 receive protocol fsm 72 received byte counter and early receive warning 71 receiver blinding 73 reception process 72 mac-to-phy interface 74 manchester decoder 69 manchester enable/disable field 29 manchester encoder 74 manchester encoder/decoder enabling and controlling 29 manchester management register 29, 74 mask interrupt sources field 17 memory 16-bit enable field 17 memory address generation 48 memory bit width select 7 memory bus structure 51 memory bus width control 51 memory cache 44 advantages 44 read mode 44 staggered address transfers 45 using micro-channel adapters 46 zero wait state response to host 45 memory enable field 14 memr 7 memw 7 missed packet counter register 72 missed packet error counter register 29 missed packet field 33 modifying the transmit queue 82 monitor mode 33 multicast field table registers 27 multicast frames receiving 32 multiple packet transmissions 80 multiple packet transmit mode 28 n non-802.3 protocols 79 non-8390 features enabling 26 non-deferred field 39 - 40 normal map buffering see ring-style buffering o operating conditions 90 operation on micro-channel adapters 46 oscillator 74 osr 7 out-of-window collision field 38, 78 overwrite warning enable field 27 overwrite warning field 28 ownership of buffers 82 p package description 116 package dimensions 116 - 117 packet received enable field 28 packet received field 28 packet received intact field 33 packet transmitted enable field 28 packet transmitted field 28, 39 - 40 page select field 24 pc-98 bus support 50 phy-to-mac interface 68 pin list 5 - 11 pled 69 pli 1 plug and play 57 auto-configuration ports 57 boot bit 20 buffer memory limitations 64 configuration and activation 59 configuration registers 59 configuring as a boot card 64 configuring with an i/o-mapped pipe 64 enable bit 22 isolation 59 plug and play jumper installed bit 16 pnp and i/o mapped pipe bit 19 resource string 62 states 58 pnjmp 16 pnpboot 20, 64 pnpen 22 pnpiop 19, 64 pos id registers 19
preamble generator 76 promiscuous mode 71 promiscuous reception field 31 pulse train sourcing 64 r ram address register 20 ram base address field 20 ram offset field 14 ramcs1 8 ramoe 7 ramwr 7 recall eerom field 15 receieve boundary page register 23 receive abort frame field 31 receive broadcast frames field 32 receive buffer end register 32, 88 receive buffer starting address register 30 receive buffer table pointer registers 34, 89 receive burst starting address registers 30 receive byte count registers 31 receive configuration register 31, 71, 73 receive error enable field 28 receive error field 28 receive led readback 29 receive multicast frames 32 receive packet buffering 83 receive packet status register 33 receive runt frames field 32 receive start page register 33, 88 receive stop page register 34 received byte count register 26 received byte counter 71 receiver blinding 73 receiver disable field 33 receiver fields 72 crc field 73 da field 73 end-of-frame 73 sa and data fields 73 sfd field 73 receiver network interface 68 receiver protocol fsm 72 recommended operating conditions 90 register overview 12 relocating ram and rom base addresses in tandem 48 reset 7, 53 reset network interface controller field 14 reset status field 28 resource string 62 restart field 16 retrieval and storage of host configuration registers 54 revision number indication field 18 ring arrangements 86 ring of buffers 83 ring-buffering selecting 26, 79 ring-style buffering introduction 23 rled 8 rom base address field 21 rom control register 20 rom offset field 17 rom size selection 48 rom window size field 20 runt frames receiving 32 runts frames receiving 71 rx+/rx- 8 s sa address lines 8 save error packets field 32 sbhe 8, 51 sd data lines 8 sending multiple transmissions 80 single packet transmission 80 slot timer 77 smart squelch digital noise filter 69 smemr 8 smemw 8 software interrupt field 17 sqe test 75 squelch circuitry 69 staggered address transfers 45 start bit field 24, 72 start page 38 start page register 33 start-of-frame delimiter (sfd) 70, 73 station address registers 34 status indicators 75 stop backup modifications 26 stop bit field 24, 72 stop page register 34 store to non-volatile field 15 supporting non-802.3 protocols 79 switch register bit 14 switch register set 16
t timers backoff timer 77 collision counter 77 heartbeat detection 77 slot timer 77 truncated binary exponential backoff algorithm 77 timing diagrams 93 - 115 parameters 94 tled 9 tpr+/tpr- 9 tprx polarity led readback field 29 tpx+/tpx- 9 tpx1/tpx2 74 tpx2+/tpx2- 9 transfer buffer end register 37 - 38, 80 transfer count registers 37 transmission initialization 77 transmission process 77 transmit buffer pointer registers 39, 80 transmit buffer starting address register 36, 80 transmit burst starting address registers 35 transmit configuration register 36, 76 transmit error enable field 28 transmit error field 28, 78 transmit frame length registers 36, 80 transmit led readback 29 transmit packet initiation field 24 transmit packets buffer ownership 82 multiple packet transmissions 80 single packet transmission 80 transmit queue modification 82 transmit protocol fsm 76 transmit queue modifying 82 transmit serializer 76 transmit start page registers 38 transmit status register 38, 78, 80, 82 transmit underrun 78 transmitted with collisions field 39 - 40 transmitter basic function 76 collisions 78 crc generator 76 early transmit underrun protection 78 extensions beyond 802.3 79 fifo 77 initialization 77 operation 77 preamble generator 76 timers 77 transmission process 77 transmit protocol fsm 76 transmit serializer 76 transmit underrun 78 transmitter network interface 74 transmitter operation 77 twisted-pair differential driver transmitter 74 twisted-pair differential receiver 69 tx+/tx- 9, 74 txd 76 u unlock eerom storage field 15 using an external eerom 54 v vdd pins 9 vss pins 9 w wait state selection 26 waitforkey 58 wrapen 87 x x1/x2 9, 74 xtxd 76 z zero wait state enable field 21 zero wait state in 16-bit transfers 52 zero wait state response to the host 50 zws 9, 50 - 51 response to host 45

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