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cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 1 general description features patent number #5,565, 761, #5,747,977, #5,742,151, #5,804,950, #5,798,635 pin to pin compatible w i th f a n6903/4 enable low e st bom for pow er supply w i th pf c internally sy nchronized pf c and pw m in one ic patented slew rate enhanced voltage error amplifier w i th advanced input current shaping technique universal line input voltage ccm boost or dcm boost w i th leading edge modulation pf c using input current shaping t e chnique f eedforw a rd iac pin to do the automatic slope compensation pfcovp, pfc vccovp, precision -1v pfc ilimit , t r i-f ault detect comparator to meet ul1950 no bleed resistor required low supply currents; start- up: 100ua ty pical, operating current: 2ma ty pical. sy nchronized leading pfc and trailing edge modulation pw m to reduce ripple current in the storage capacitor betw een the pf c and pw m sections and to reduce sw itching noise in the sy stem vinok comparator to guarantee to enable pw m w hen pf c reach steady state high efficiency trailing-edge current mode pw m uvlo, ref o k, and brow nout protection digital pw m softstart: cm6903a (10ms) precision pw m 1.5v current limit for current mode operation t he cm6903a is a space-saving pf c-pw m controller for pow er factor corrected, sw it ched mode pow er supplies that offers very low start-up and operating currents. f o r the pow er supply less than 500watt, its input current shaping pf c performance could be very close to cm6800 or ml4800 architecture. pow e r f a ctor correction (pf c ) offers the use of smaller, low e r cost bulk capacitors, reduces pow er line loading and stress on the sw itching f e t s , and results in a pow er supply fully compliant to iec1000-3-2 specifications. t he cm6903a includes circuits fo r the implementation of a leading edge, input current s haping technique ?boost? ty pe pfc and a trailing edge, pw m. t he cm6903a?s pf c and pw m operate at the same frequency , 67khz. t h is higher frequency allow s the user to design w i th smaller pw m components w h ile maintaining the optimum operating frequency for the pf c. an pf c ovp comparator shuts dow n the pf c section in the event of a sudden decrease in load. t he pf c section also includes peak current limiting for enhanced sy stem reliability . 24 hours technical support---websim champion provides customers an online circuit simulation tool called w ebsim. you could simply logon our w ebsite at www. c h a m p i o n - m i c r o . c o m f o r d e t a i l s . applications pin configuration desktop pc pow e r supply ac adaptor internet server pow e r supply ipc pow e r supply ups battery charger dc motor pow e r supply monitor pow e r supply t e lecom sy stem pow e r supply distributed pow e r sip-09 (z 09) f r ont view d c il im it vcc pw m o ut pf co ut gn d is e n s e ve ao vf b ia c 1 23 45 67 89
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 2 pin description op eratin g vo ltag e pin no . sy mb o l descrip tio n m i n . t y p . ma x . unit 1 d c i lim i t pw m current limit compar ator input 0 1.5 v 2 v cc positive supply 1 0 1 3 1 8 v 3 pw m out pw m driver output 0 vcc v 4 pf c out pf c driver output 0 vcc v 5 g n d g r o u n d 6 i sen se current sense input to the pf c curr ent limit comparator -5 0.7 v 7 v e a o pf c transconductance voltage error amplifier output 0 6 v 8 v fb pf c transconductance voltage erro r amplifier input 0 2.5 3 v 9 iac f eedforw a rd input to do slope compensation and to start up the sy stem 0 1 v block diagram 6 isense 8 vfb 4 pfcout 7 veao 9 iac 2 vcc 3 pwmout 1 dcilimit 5 gnd 2.5v 17.9v 16.4v 0.5v 2.75v 2.5v pwm clk vref ok vref ok vcc 2.45v -1v vfb 0.75v 1.5v vcc + - pwmcmp - . - + uvlo . . s r q q r r s r q q r 100k ohm vcc ovp + - . - - + . pfc ilimit + - . pfc ovp + - . - + - . pfccmp + - . vin ok + - . + 10ms .. . .. 400k ohm pfcclkb pwmclk . . + + out u1 sum . . . . 5.1k ohm ramp faultb pfcclkb pwmclk fpfc= 67khz fpwm= 67khz cm6903a tri-fault detect gmv isenseamp osc r1c r1b r1a vrefok uvlo ss 1v
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/01/20 champion microelectronic corporation page 3 ordering information part number temperature range package cm6903aiz -40 to 125 9-pin sip (z09) CM6903AGIZ* -40 to 125 9-pin sip (z09) *note: g : suffix for pb free product absolute maximum ratings absolute maximum ratings are those values beyond which the device c ould be permanently damaged. parameter min. max. units v cc max 20 v iac (after start up) gnd-0.3 1.0 v i sense voltage -5 0.7 v pfc out gnd ? 0.3 vcc + 0.3 v pwm out gnd ? 0.3 vcc + 0.3 v veao 0 6.3 v voltage on any other pin gnd ? 0.3 vcc + 0.3 v i cc current (average) 40 ma peak pfc out current, source or sink 0.5 a peak pwm out current, source or sink 0.5 a pfc out, pwm out energy per cycle 1.5 j junction temperature 150 storage temperature range -65 150 operating temper ature range -40 125 lead temperature (soldering, 10 sec) 260 thermal resistance ( ja ) 80 /w electrical characteristics unless otherwise stated, these sp ecifications apply vcc=+15v, t a =operating temperature range (note 1) cm6903a symbol parameter test conditions min. typ. max. unit voltage error amplifier (g mv ) input voltage range 0 5 v transconductance v noninv = v inv , veao = 3.75v 30 65 90 mho feedback reference voltage 2.45 2.5 2.55 v input bias current note 2 -0.5 -1.0 a output high voltage 5.8 6.0 v output low voltage 0.1 0.4 v sink current v fb = 3v, veao = 6v -20 -35 a source current v fb = 1.5v, veao = 1.5v 30 40 a open loop gain 50 60 db power supply rejection ratio 11v < v cc < 16.5v 50 60 db iac input impedance isense = 0v 4080 5100 6120 ohm vcc ovp comparator threshold voltage 17.4 17.9 18.4 v hysteresis 1.2 1.5 1.65 v
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/01/20 champion microelectronic corporation page 4 electrical characteristics (conti.) unless otherwise stat ed, these specifications apply vcc=+15v, r t = 52.3k ? , c t = 470pf, t a =operating temperature range (note 1) cm6903a symbol parameter test conditions min. typ. max. unit pfc ovp comparator threshold voltage 2.60 2.77 2.85 v hysteresis 200 290 mv pfc i limit comparator threshold voltage -0.9 -1 -1.15 v delay to output 150 300 ns v in ok comparator threshold voltage 2.35 2.45 2.55 v hysteresis 1.65 1.75 1.85 v pwm digital soft start digital soft start timer (note 2) right after start up (cm6903a) 10 ms dc i limit comparator threshold voltage 1.4 1.5 1.6 v delay to output (note 2) 150 300 ns tri-fault detect comparator fault detect high 2.65 2.75 2.85 v time to fault detect high v fb =v fault detect low to v fb = open, 470pf from v fb to gnd 2 4 ms fault detect low 0.4 0.5 0.6 v oscillator initial accuracy t a = 25 62 67 74 khz voltage stability 10v < v cc < 15v 1 % temperature stability 2 % total variation line, temp 60 67 74.5 khz pfc dead time (note 2) 0.3 0.45 0.65 s pfc minimum duty cycle i ac =100ua,v fb =2.55v, i sense = 0v 0 % maximum duty cycle i ac =0ua,v fb =2.0v, i sense = 0v 90 95 % output low impedance 15 22.5 ohm i out = -100ma 0.8 1.5 v output low voltage i out = -10ma, v cc = 8v 0.4 0.8 v output high impendence 30 45 ohm output high voltage i out = 100ma, v cc = 15v 13.5 14.2 v rise/fall time (note 2) c l = 1000pf 50 ns
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 5 electrical characteristics (co n t i.) un less o t h e rw ise stat ed , th ese sp ecificatio n s ap p l y vcc= + 15v, r t = 52.3k ? , c t = 470p f , t a =ope ra ting te mpe r a t ure ra nge (note 1 ) cm6903a sy m b o l p a ra me te r te s t conditions m i n . t y p . ma x . unit pwm duty cy cle range cm6903a 0-49.5 0-50 % output low impedance 15 22.5 ohm i out = -100ma 0.8 1.5 v output low voltage i out = -10ma, v cc = 8v 0.7 1.5 v output high impendence 30 45 ohm output high voltage i out = 100ma, v cc = 15v 13.5 14.2 v rise/f a ll t i me (note 2) c l = 1000pf 50 ns supply s t a r t - u p c u r r e n t v cc = 11v, c l = 0 100 150 ua o p e r a t i n g c u r r e n t v cc = 15v, c l = 0 2.5 4.0 ma undervoltage lockout t h re s h o l d 1 2 . 7 4 1 3 . 0 1 3 . 2 6 v undervoltage lockout hy st e r e s i s 2 . 8 5 3 . 0 3 . 1 5 v note 1: limits are guaranteed by 100% testing, sampli ng, or correlation w i th w o rst-case test conditions. note 2: guaranteed by desi gn, not 100% production test. typical performance characteristic 57 64 71 78 85 92 99 106 113 120 127 2 2 .1 2 . 2 2 .3 2 . 4 2 .5 2 . 6 2 .7 2 . 8 2 .9 3 vfb ( v ) transconductance (umho) voltage error amplifier (g mv ) transconductance
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 6 functional description t he cm6903a consists of an icst (input current shaping t e chnique), ccm (continuous conduction mode) or dcm (discontinuous conduction mode) boost pf c (pow er f a ctor correction) front end and a sy nchronized pw m (pulse w i dth modulator) back end. t he cm6903a is pin to pin compatible w i th f a n6903/4 (9 pin sip package), w h ich is the second generation of t he ml4803 w i th 8 pin package. it is distinguished from earlier combo controllers by its low count, innovative input current shaping technique, and very low start-up and operating curr ents. t he pw m section is dedicated to peak current mode operation. it uses conventional trailing-edge modulat ion, w h ile the pfc uses leading-edge modulation. t h is patented leading edge/t r ailing edge (let e) modulation technique helps to minimize ripple current in the pf c dc buss capacitor. t he main improvements from ml4803 are: 1.) remove the one pin error amplifier and add back the slew rate enhancement gmv, w h ich is using voltage input instead of current input. t h is transconductance amplif ier w ill increase the transient response 5 to 10 times from the conventional op 2.) vfb pfc ovp comparator 3.) t r i-fault detect for ul1950 compliance and enhanced safety 4.) a feedforw a rd signal from iac pin is added to do the automatic slope co mpensation. t h is increases the signal to noise ratio during the light load; therefore, t hd is improved at light load and high input line voltage. 5.) cm6903a does not require the bleed resistor and it uses the less than 500k ohm resistor betw een iac pin and rectified li ne voltage to feed the initial current before the chip w a kes up. 6.) vinok comparator is added to guaranteed pw m cannot turn on until vf b reaches 2.5v in w h ich pf c boost output is about steady state, ty pical 380v. 7.) a 10ms digital pw m soft start circuit is added 8.) 9 pin sip package 9.) no internal z ener but w i th vccovp comparator t he cm6903a operates both pf c and pw m sections at 67khz. t h is allow s the use of smaller pw m magnetic and output filter components, w h ile minimizing sw itching losses in the pf c stage. several protection features have been built into the cm6903a. t hese include soft-start, redundant pf c overvoltage protection, t r i- f ault detect, vinok, peak current limiting, duty cy cle limiting, under-voltage lockout, reference ok comparator and vccovp. detailed pin descrip tio n s dcilimit (pin 1 ) t h is pin is tied to the primary side pw m current sense resistor or transformer. it provi des the internal pulse-by - pulse current limit for the pw m stage (w hich occurs at 1.5v) and the peak current mode feedback path for the current mode control of the pw m stage. besi des current information, the optocouple also goes into dcilimit pin. t herefore, it is the sum amplifier input. vcc (pin 2) vcc is the pow er input connection to the ic. t he vcc start-up current is 100ua. t he no-load icc current is 2ma. vcc quiescent current w ill include both the ic biasing currents and the pf c and pw m out put currents. given the operating frequency and the mo sf et gate charge (qg), average pf c and pw m output curr ents can be calculated as iout = qg x f . t he average magnetizing current required for any gate drive transformers must also be included. t he vcc pin is also assumed to be proportional to the pf c output voltage. internally it is ti ed to the vcc ovp comparator (17.9v) providing redundant high-speed over-voltage protection (ovp) of the pf c stage. vcc also ties internally to the uvlo circuitry and vr ef ok comparator, enabling the ic at 13v and disabling it at 10v. vcc must be by passed w i th a high quality ceramic by pass capacitor placed as close as possible to the ic. good by pa ssing is critical to the proper operation of the cm6903a. vcc is ty pically produced by an additional w i nding off the boost inductor or pf c choke, providing a voltage that is proportional to the pf c output voltage. since the vcc ovp max voltage is 17.9v, an in ternal shunt limits vcc overvoltage to an acceptable value. an external clamp, such as show n in f i gure 1, is desirable but not necessary . vc c gn d 1n 52 50b f i gur e 1 . o p t i onal v c c c l am p t h is limits the maximum vcc t hat can be applied to the ic w h ile allow i ng a vcc w h ich is high enough to trip the vcc ovp. an rc filter at vcc is required betw een boost trap w i nding and vcc.
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 7 pfc out (pin 4) and pwm out (pin3) pf c out and pw m out are the high-current pow er driver capable of directly driving the gate of a pow er mosf et w i th peak currents up to -1a and + 0 .5a. both outputs are actively held low w hen vcc is below the uvlo threshold level w h ich is 13v or vref ok comparator is low . gnd (pin 5) gnd is the return point for all circuits associated w i th this part. note: a high-quality , low impedance ground is critical to the proper operation of the ic. high frequency grounding techniques should be used. isense (pin 6) t h is pin ties to a resistor w h ich senses the pf c input current. t h is signal should be negative w i th respect to the ic ground. it internally feeds t he pulse-by - pulse current limit comparator and the current sense feedback signal. t he ilimit trip level is ?1v. t he isense feedback is internally multiplied by a gain of f our and compared against the internal programmed ramp to set the pf c duty cy cle. t he intersection of the boost inductor current dow nslope w i th the internal programming ramp determines the boost off-time. it requires a rc filter betw een isense and pf c boost sensing resistor. vea o (pin 7) t h is is the pf c slew rate enhanced transconductance amplifier output w h ich needs to connected w i th a compensation netw o rk. vfb (pin 8) besides this is the pf c slew rate enhanced transconductance input, it also tie to a couple of protection comparators, pf covp, and t r i-f ault detect ia c (pin 9) t y pically , it has a feedforw a rd resistor, rac, 800k ohm resistor connected betw een this pin and rectified line input voltage. t h is pin serves 2 purposes: 1.) during the startup conditi on, it supplies the startup current; therefore, the sy stem does not requires additional bleed resistor to start up the chip. 2.) t he current of rac w ill program the automatic slope compensation for the sy stem. t h is feedforw a rd signal can increase the signal to noise ratio for the light load condition or the high input line voltage condition. po w e r f acto r co rrectio n pow e r factor correction makes a nonlinear load look like a resistive load to the ac line. f o r a resistor, the current draw n from the line is in phase w i th and proportional to the line voltage, so the pow er factor is unity (one). a common class of nonlinear load is the i nput of most pow er supplies, w h ich use a bridge rectifier and capacitive input filter fed from the line. t he peak-charging effect, w h ich occurs on the input filter capacitor in these supplies, causes brief high-amplitude pulses of current to flow from the pow er line, rather than a sinusoidal curr ent in phase w i th the line voltage. such supplies present a pow er factor to the line of less than one (i.e. they cause si gnificant current harmonics of the pow er line frequency to appear at their input). if the input current draw n by such a supply (or any other nonlinear load) can be made to follow the i nput voltage in instantaneous amplitude, it w ill appear resistiv e to the ac line and a unity pow er factor w ill be achieved. t o hold the input current draw of a device draw ing pow er from the ac line in phase w i th and proportional to the input voltage, a w a y must be found to prevent that device from loading the line except in pr oportion to the instantaneous line voltage. t he pf c section of the cm6903a uses a boost-mode dc-dc converter to accomplish this. t he input to the converter is the full w a ve rectified ac line voltage. no bulk filtering is applied follow i ng the bridge rectifier, so the input voltage to the boost converter ranges (at tw ice line frequency ) from zero volts to t he peak value of the ac input and back to zero. by forcing the boost converter to meet tw o simultaneous conditions, it is possible to ensure that the current draw s from the pow er line matches the instantaneous line voltage. one of these conditions is t hat the output voltage of the boost converter must be set hi gher than the peak value of the line voltage. a commonly used value is 385vf b , to allow for a high line of 270vac rm s . t he other condition is that the current that the converter is a llow ed to draw from the line at any given instant must be pr oportional to the line voltage. pfc control: le a d ing edge modula t ion w i th input curre nt sha p ing te c hnique (i.c.s.t.) t he only differences betw een t he conventional pf c control topology and i.c.s.t . is: the current loop of t he conventional control method is a close loop method and it requires a detail understanding about the sy stem loop gain to design. w i th i.c.s.t ., since the current loop is an open loop, it is very st raightforw ard to implement it. t he end result of the any pf c sy stem, the pow er supply is like a pure resistor at low frequenc y . t herefore, current is in phase w i th voltage. in the conventional control, it forces the input current to follow the input voltage. in cm6903a, the chip thinks if a boost converter needs to behave like a low frequency resistor, w hat the duty cy cle should be. t he follow i ng equations is cm6903a try to achieve: in in e i v r = ( 1 ) in l i i = ( 2 )
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 8 equation 2 means: average boost inductor current equals to input current. d out l in i v i v ( 3 ) t herefore, input instantaneous pow er is about to equal to the output instantaneous pow er. f o r steady state and for the each phase angle, boost converter dc equation at c ontinuous conduction mode is: ) 1 ( 1 d v v in out ? = ( 4 ) rearrange above equations, (1), (2),(3), and (4) in term of vout and d, boost converter duty cy cle and w e can get average boost diode current equation (5): e out d r v d i ? = 2 ) 1 ( ( 5 ) also, the average diode current can be expressed as: dt t i t i off t d sw d ? = ) ( 1 0 ( 6 ) if the value of the boost inductor is large enough, w e can assume . it means during each cy cle or w e can say during the sampling, the diode current is a constant. d d i t i ~ ) ( t herefore, equation (6) becomes: ) 1 ( ' d i d i t t i i d d sw off d d ? = = = (7) combine equation (7) and equation (5), and w e get: sw off e out d e out d e out d t t r v i r v d i r v d d i = = = ' 2 ' ' ) ( ( 8 ) f r om this simple equation (8), w e implement the pf c control section of the cm6903a. le a d ing/tra iling modula t ion conventional pulse w i dth m odulation (pw m) techniques employ trailing edge modulation in w h ich the sw itch w ill turn on right after the trailing edge of the sy stem clock. t he error amplifier output is then compar ed w i th the modulating ramp. w hen the modulating ramp reac hes the level of the error amplifier output voltage, the sw itch w ill be turned off. w hen the sw itch is on, the inductor current w ill ramp up. t he effective duty cy cle of t he trailing edge modulation is determined during the on time of the sw itch. f i gure 2 show s a ty pical trailing edge control scheme. in case of leading edge modulati on, the sw itch is turned of f right at the leading edge of t he sy stem clock. w hen the modulating ramp reaches the le vel of the error amplifier output voltage, the sw itch w ill be turned on. t he effective duty - cy cle of the leading edge modulation is determined during of f time of the sw itch. f i gure 3 show s a leading edge control scheme.
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 9 one of the advantages of this control technique is that it required only one sy stem clock. sw itch 1(sw 1) turns of f and sw itch 2 (sw 2 ) turns on at the same instant to minimize the momentary ?no- load? period, thus low e ring ripple voltage generated by the sw itching action. w i th such sy nchronized sw itching, the ri pple voltage of the first stage is reduced. calculation and ev aluation have show n that the 120hz component of the pf c?s output ripple voltage can be reduced by as much as 30% using this method, substantially reducing dissipat ion in the high-voltage pf c capacitor. ty pical applications pfc section: pfc volta g e loop error a m p, vea o t he ml4803 utilizes an one pin voltage error amplifier in the pfc section (veao). in the cm6903a, it is using the slew rate enhanced transconduct ance amplifier, w h ich is the same as error amplifier in the cm6800. t he unique transconductance profile c an speed up the conventional transient response by 10 times. t he internal reference of the veao is 2.5v. t he input of the veao is vfb pin. pfc volta g e loop compe n s a t ion t he voltage-loop bandw idth must be set to less than 120hz to limit the amount of line cu rrent harmonic distortion. a ty pical crossover frequency is 30hz. t he voltage loop gain (s) cv v dc eao 2 outdc in fb eao out fb eao out z * gm * c * s * v * v v 5 . 2 * p v v * v v * v v ? ? ? ? ? ? ? = z cv : compensation net w o rk for the voltage loop gm v : t r ansconductance of veao p in : average pf c input pow e r v out d c : pf c boost output voltage; ty pical designed value is 380v. c dc : pf c boost output capacitor ? v eao : t h is is the necessary change of the veao to deliver the designed average input pow er. t he average value is 6v-3v= 3v since w hen the input line voltage increases, the delta veao w ill be reduced to deliver the same to the output. t o over compensate, w e choose the delta veao is 3v. in tern al vo ltag e ramp t he internal ramp current source is programmed by w a y of veao pin voltage. when veao in creases the ramp current source is also increase. t h is current source is used to develop the internal ramp by charging the internal 30pf + 12/ -10% capacitor. t he frequency of the internal programming ramp is set internally to 67khz. design pfc isense filtering isense filter, the rc filter betw een rs and isense: t here are 2 purposes to add a filter at isense pin: 1.) protection: during star t up or inrush current conditions, it w ill have a large voltage cross rs, w h ich is the sensing resistor of the pf c boost converter. it requires the isense f ilter to attenuate the energy . 2.) reduce l, the boost i nductor: t he isense f ilter also can reduce the boost inductor value since the isense f ilter behaves lik e an integrator before going isense w h ich is the i nput of the current error amplifier, ieao.
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 10 t he i sen se filter is a rc filter. t he resistor value of the i sen se f ilter is betw een 100 ohm and 50 ohm. by selecting r filt er equal to 50 ohm w ill keep the offset of the ieao less than 5mv. usually , w e design the pole of i sen se f ilter at fpfc/6, one sixth of the pf c sw itching frequency . t herefore, the boost inductor can be reduced 6 times w i thout disturbing the stability . t heref ore, the capacitor of the i sen se filter, c filt er , w ill be around 283nf. iac, r ac , automatic slope compensation, dcm at high line and light load, and startup current t here are 4 purposes for iac pin: 1.) f o r the leading edge m odulation, w hen the duty cy cle is less than 50%, it requires the similar slope compensation, as the dut y cy cle of the trailing edge modulation is greater than 50%. in the cm6903a, it is a relatively easy thing to design. use an more than 800k ohm resistor, r ac to connect iac pin and the re ctified line voltage. it w ill do the automatic sl ope compensation. if the input boost inductor is too small, the r ac may need to be reduced more. 2.) during the startup period, rac also provides the initial startup current, 100ua;therefore, the bleed resistor is not needed. 3.) since iac pin w i th r ac behaves as a feedforw a rd signal, it also enhances the signal to noise ratio and the t hd of the input current. 4.) it also w ill try to keep the maximum input pow er to be constant. how e ver, the maximum input pow er w ill still go up w hen the i nput line voltage goes up. start up o f th e sy stem, uvl o, an d vref ok during the start-up period, r ac resistor w ill provide the start up current~ 100ua from the rectif ied line voltage to iac pin. inside of cm6903a during the start-up period, iac is connected to vcc until the vcc reaches uvlo voltage w h ich is 13v and internal refer ence voltage is stable, it w ill disconnect itself from vcc. pf c sectio n w akes u p after start u p p e rio d after start up period, pfc section w ill softly start since veao is zero before the star t-up period. since veao is a slew rate enhanced transconductance amplifier (see figure 3), veao has a high impedanc e output like a current source and it w ill slow ly char ge the compensation net w o rk w h ich needs to be designed by using the voltage loop gain equation. before pf c boost output reaches its design voltage, it is around 380v and vfb reaches 2.5v, pwm section is off. pw m sectio n w akes u p after pf c reach es stead y state pw m section is off all the time before pf c vf b reaches 2.45v. t hen internal 10ms digital pw m soft start circuit slow ly ramps up the soft-start voltage. pfc ovp comparator pf c ovp comparator sense vf b pin w h ich is the same the voltage loop input. t he good thing is the compensation netw o rk is connected to veao. t he pfc ovp function is a relative fast ovp. it is not lik e the conventional error amplifier w h ich is an operational amplif ier and it requires a local feedback and it make the ovp action becomes very slow . t he threshold of the pf c ovp is 2.5v+ 10% = 2 .75v w i th 250mv hy steresis. tri-fa ult de te c t compa r a t or t o improve pow er supply reliability , reduce sy stem component count, and simplify compliance to ul1950 safety standards, the cm6903a includes t r i-f ault detect. t h is feature monitors vf b (pin 8) for certain pf c fault conditions. in case of a feedback path fa ilure, the output of the pf c could go out of safe operating limits. w i th such a failure, vf b w ill go outside of its normal operating area. should vfb go too low , too high, or open, t r i- f ault detect senses the error and terminates the pf c output drive. t r i-f ault detect is an entirely internal circuit. it requires no external components to serve its protective function. vcc ovp a nd ge ne ra te vcc f o r the cm6903a sy stem, if v cc is generated from a source that is proportional to the pf c output voltage and once that source reaches 17.9v, pfcout , pfc driver w ill be off. t he vcc ovp resets once the vcc discharges below 16.4v, pf c output driver is enabled. it serves as redundant pf c ovp function. t y pically , there is a bootstrap w i nding off the boost inductor. t he vcc ovp comparator senses w hen this voltage exceeds 17.9v, and terminates t he pf c output drive. once the vcc rail has decreased to below 16.4v the pf c output drive be enabled. given that 16v on vcc corresponds to 380v on the pf c output, 17.9v on vcc corresponds to an ovp level of 460v. it is a necessary to put rc filter betw een bootstrap w i nding and vcc. f o r vcc= 13v, it is sufficient to drive either a pow er mosf et or a igbt .
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/01/20 champion microelectronic corporation page 11 uvlo the uvlo threshold is 13v providing 3v hysteresis. pfcout and pwmout both pfcout and pwmout are cmos drivers. they both have adaptive anti-shoot through to reduce the switching loss. its pull-up is a 30ohm pmos driver and its pull-down is a 15ohm nmos driver. it can source 0.5a and sink 1a if the vcc is above 13v. pwm section after 10ms digital soft start, cm6903a?s pwm is operating as a typical current mode. it requires a secondary feedback, typically, it is c onfigured with cm431, and photo couple. since pwm section is different from cm6800 family, it needs the emitter of the phot o couple to connected with dcilimit instead of the co llector. the pwm current information also goes into dcilimit. usually, the pwm current information requires a rc filter before goes into the dcilimit. therefore, dcilimit actua lly is a summing node from voltage information which is from photo couple and cm431 and current information which is from one end of pwm sensing resistor and the signal goes through a single pole, rc filter then enter the dcilimit pin. this rc filter at dcilmit also serves several functions: 1.) it protects ic. 2.) it provides level shift for voltage information. 3.) it filters the switching noise from current information. the pole location of the rc f ilter should be greater than one sixth of the pwm switching frequency which is 67khz for cm6903a and which is 134khz for cm6903a. since the typical photo couple should be biased around 1ma, the resistor of the rc filter should be around 1.5v/1ma~1.5k ohm and we suggest r is 1k ohm. therefore, for cm6903a, c should be around 14nf. the maximum input voltage of the dcilimit pin is 1.5v. component reduction components associated with the vrms and ieao pins of a typical pfc controller such as the cm6800 have been eliminated. the pfc power limit and bandwidth does vary with line voltage. double the power can be delivered from a 220v ac line versus a 110v ac line. since this is a combination pfc/pwm, the power to the load is limited by the pwm stage.
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 12 application circuit (cm6903a) 6 isense 8 vfb 4 pfcout 7 veao 9 iac 2 vcc 3 pwmout 1 dcilimit 5 gnd 2.5v 17.9v pwm clk 2.5v 1.5v 16.4v vcc_circle vcc -1v vref ok vfb 1.5v 0.5v vcc vout 2.5v vref ok 2.75v + - r13 pwmcmp - . - + r14 uvlo . . r17 sr1 r16 c21 r2 d8 r15 d10 c1 u2 q3 r10 f1 l1 d2 d1 z1 s r q q r 100k ohm vcc ovp + - . - + - . pfc ilimit + - . pfc ovp + - . - + - . pfccmp + - . rac vin ok + - . + .. d10 s r q q r r5 400k ohm r4 c5 c4 d8 10ms .. . c13 r19 d6 d9 d11 r11 c7 c16 c15 c14 c11 c8 d3 r21 r3 c9 c8 r7 t2 r20 c9 t1 c10 d7 r8 r12 pfcclkb pwmclk . . r9 q1 cfilter q2 q4 r22 d14 d5 s r q q r r r23 rfilter d16 d15 t1 d13 + + out u1 sum . . . . d12 c17 l2 5.1k ohm c19 c18 r1a uvlo 1v tri-fault detect ramp fpwm= r1c ac in pwmclk osc fpfc= faultb gmv r1b ss 67khz 67khz cm6903a vrefok isenseamp pfcclkb
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/0 1 /20 cham pion mi cro e le ctro nic corpo r ation page 13 package dimension 9-pin sip (z09)
cm6903a low pin count pfc/pwm c ontroller c ombo 2005/01/20 champion microelectronic corporation page 14 important notice champion microelectronic corporation (cmc) re serves the right to make changes to its products or to discontinue any integrated circuit product or service without notice, and advises its customers to obtain the late st version of relevant information to ve rify, before placing orders, that the information being relied on is current. a few applications using integrated circuit products may involv e potential risks of death, personal injury, or severe property or environmental damage. cmc integrated circ uit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. use of cmc products in such applications is understood to be fully at the risk of the cust omer. in order to minimize risks associated with the customer?s applications, th e customer should provide adequate design and operating safeguards. hsinchu headquarter sales & marketing 5f, no. 11, park avenue ii, science-based industrial park, hsinchu city, taiwan 11f, no. 306-3, sec. 1, ta tung rd., hsichih, taipei hsien 221 taiwan, r.o.c. t e l : +886-3-567 9979 t e l : +886-2-8692 1591 f a x : +886-3-567 9909 f a x : +886-2-8692 1596 http://www.champion-micro.com

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