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91400 rm (im) sk no.6700-1/21 ver.1.05 71896 preliminary overview - cpu : operable at a minimum bus cycle time of 0.5 s (microsecond) - on-chip rom maximum capacity : 48k bytes - on-chip ram capacity : 1152 bytes (LC866548a/40a/32a) : 896 bytes (lc866528a/24a) - vfd automatic display controller/driver - 16-bit timer/counter (or two 8-bit timers) - 16-bit timer/ pwm (or two 8-bit timers) - 8-channels 8 bit ad converter - two 8-bit synchronous serial-interface circuits (1-channel 16 bit, 1-channel 8 bit) - 14-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. features (1) read only memory (rom) : LC866548a 49152 8 bits : lc866540a 40960 8 bits : lc866532a 32768 8 bits : lc866528a 28672 8 bits : lc866524a 24576 8 bits 8-bit single chip microcontroller LC866548/40/32/28/24a ordering number : enn*6700 cmos ic
LC866548/40/32/28/24a no.6700-2/21 (2) random access memory (ram) : LC866548a/40a/32a 1152 8 bits lc866528a/24a 896 8 bits (3) bus cycle time / instruction cycle time the bus cycle time indicates the speed to read rom. bus cycle time cycle time clock divider system clock oscillation oscillation frequency voltage 0.5 s 1 s 1/1 ceramic resonator oscillation 6mhz 4.5 - 6.0v 2 s 4 s 1/2 ceramic resonator oscillation 3mhz 4.5 - 6.0v 7.5 s 15 s 1/2 rc resonator oscillation 800mhz 4.5 - 6.0v 183 s 366 s 1/2 crystal oscillation 32.768khz 4.5 - 6.0v note : external resisters (rf, rd) are required when x?tal oscillation is used. (4) ports - input/output ports : 3 ports (16 terminals : port 1, 7, 8) input/output port programmable in a bit - 15v withstand input/output ports : 2 ports (16 terminals) input/output port programmable nibble unit : 1 port (8 terminals : port 0) (when the n-channel open drain output is selected, the data in a bit can be inputted.) input/output port programmable in a bit : 1 port (8 terminals : port 3) - input port : 2 ports (6 terminals : port 7, 8) - vfd output port : 52 terminals large current output for digit : 16 terminals pull-down resistor option available - other function input/output port : 2 ports (12 terminals : port f, g) input port : 3 ports (24 terminals : port c, d, e) (5) vfd automatic display controller - segment/digit output pattern programmable any segment/digit combination available vfd parallel-drive available - 16-step dimmer function available (6) ad converter - 8-channels 8-bit ad converter (7) serial interface - 1-channel 16-bit serial interface circuits - 1-channel 8-bit serial interface circuits - lsb first/msb first function available - internal 8-bit baud-rate generator in common with two serial interface circuits - sio automatic transmission available (2-32 byte data can be transmitted with program automatically and continuously.)
LC866548/40/32/28/24a no.6700-3/21 (8) timers - timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-bit programmable prescaler mode 0 : two 8-bit timers with programmable prescaler mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter mode 2 : 16-bit timer with a programmable prescaler mode 3 : 16-bit counter the resolution of timer is t cyc . (t cyc : cycle time) - timer 1 : 16-bit timer/pwm with mode 0 : two 8-bit timers mode 1 : 8-bit timer + 8-bit pwm mode 2 : 16-bit timer mode 3 : variable-bit pwm (9-16 bits) in mode 0 and mode 1, the resolution of timer and pwm is t cyc . in mode 2 and mode 3, the resolution of timer and pwm selectable : t cyc or 1/2t cy c by program - base timer every 500ms overflow system for a clock application (using 32.768khz crystal oscillation for base timer clock) every 976 s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768khz crystal oscillation for base timer clock) the base timer clock selectable ; 32.768khz crystal oscillation, system clock, and programmable prescaler output of timer 0 (9) buzzer output - the buzzer sound frequency selectable ; 4khz, 2khz (using 32.768khz crystal oscillation for base timer clock) (10) remote control receiver circuit (connected to the p73/int3/t0in terminal) - noise rejection function (the time constant of noise rejection filter : 1tcyc/16tcyc/64tcyc) (tcyc : instruction cycle time) - polarity switching (11) watchdog timer - the watchdog timer is taken on rc outside - watchdog timer operation selectable : interrupt system, system reset (12) interrupt system - 14-source 10-vectored interrupts : 1. external interrupt int0 (include watchdog timer) 2. external interrupt int1 3. external interrupt int2, timer/counter t0l (lower 8 bits) 4. external interrupt int3, base timer 5. timer/counter t0h (upper 8 bits) 6. timer t1h / t1l 7. serial interface sio0 8. serial interface sio1 9. ad converter 10. vfd automatic display controller, port 0 - built-in interrupt priority control register microcontroller allows 3 levels of interrupt ; low level, high level, and highest level of multiplex interrupt. it can specify a low level or a high level interrupt priority from int2/t0l through port 0 (i. e. the above interrupt number from three through ten). it can also specify a low level or the highest level interrupt priority to int0 and int1. (13) subroutine stack levels - 128 levels (max.) : stack area included in ram area
LC866548/40/32/28/24a no.6700-4/21 (14) multiplication and division - 16 bit 8 bit (7 instruction cycle times) - 16 bit 8 bit (7 instruction cycle times) (15) three oscillation circuits - on-chip rc oscillation circuit used for the system clock - on-chip cf oscillation circuit used for the system clock - on-chip crystal oscillation circuit used for the system clock and for time-base clock note : external resisters (rf, rd) are required (16) standby function - halt mode function the halt mode is used to reduce the power dissipation. in this operation mode, the program execution is stopped. this operation mode can be released by the interrupt request signals or the initial system reset request signal. - hold mode function the hold mode is used to stop all the oscillations ; rc (internal), cf and crystal oscillations. this mode can be released by the following operations. reset terminal ( res ) set to low level. input a assigned level to p70/int0/t0in or p71/int1/t0in terminal. input a port0 interrupt condition. (17) factory shipment qfp100e delivery form (18) development tools - evaluation chip : lc866094 - eprom version : lc86e6548 - one time version : lc86p6548 - emulator : eva86000 + ecb866500 (evaluation chip board) + pod866500 (pod) notes for use follow the under table. frequency range of the system clock voltage range clock divider note 15khz to 3mhz 1/1 can not use 1/2 divider 30khz to 6mhz 1/1, 1/2 internal rc oscillation 4.5v to 6.0v 1/1, 1/2
LC866548/40/32/28/24a no.6700-5/21 pin assignment qip100e package dimension (unit : mm) 3151 sanyo : qip-100e 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 s48/pg0 s49/pg1 s50/pg2 s51/pg3 p00 p01 p02 p03 vss2 vdd2 p04 p05 p06 p07 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 s19/pc3 s18/pc2 s17/pc1 s16/pc0 vdd3 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 vdd4 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 vp p16/buz z p17/pwm0 p30 p31 p32 p33 p34 p35 p36 p37 p70/int0 res xt1/p74 xt2/p75 vss1 cf1 cf2 vdd1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 p71/int1 p72/int2/t0i n p72/int3/t0i n s0/t0
LC866548/40/32/28/24a no.6700-6/21 system block diagram interrupt control standby control ir rom pla cf rc x?tal clock generator pc base timer sio0 sio1 timer 0 timer 1 adc int0 to 3 noise filtter ram 128 bytes port 1 port 3 port 7 high voltage output vfd controller bus interface acc b register c register psw rar ram stack pointer watch dog timer port 0 si0 automatic transmission alu port 8
LC866548/40/32/28/24a no.6700-7/21 LC866548a/40a/32a/28a/24a pin description pin name i/o function description option vss1, 2 power pin (-) *1 vdd1,2,3,4 power pin (+) *1 vp power pin (+) for the vfd output pull-down resist port 0 p00 - p07 i/o 8-bit input/output port input/output in nibble units input for port 0 interrupt input for hold release 15v withstand at n-channel open drain output pull-up resistor : provided/not provided (each nibble) output form : cmos/n-channel open drain (each bit) port 1 8-bit input/output port input/output can be specified in bit unit. other pin functions p10 p11 p12 p13 p14 p15 p16 p17 sio0 data output sio0 data input/bus input/output sio0 clock input/output sio1 data output sio1 data input/bus input/output sio1 clock input/output buzzer output timer1 output (pwm0 output) output form : cmos/n-channel open drain (each bit) p10 - p17 i/o port 3 p30 - p37 i/o 8-bit input/output port input/output in bit unit 15v withstand at n-channel open drain output output form : cmos/n-channel open drain (each bit) port 7 4-bit input/output port input/output in bit unit 2-bit input port other pin function p70 p71 p72 p73 p74 p75 int0 input/hold release /nch-tr. output for watchdog timer int1 input/hold release input int2 input/timer 0 event input int3 input with noise filter/timer 0 event input input pin xt1 for 32.768khz crystal resonator oscillation output pin xt2 for 32.768khz crystal resonator oscillation interrupt received form, vector address rising falling rising/ falling h level l level vector p70 - p73 p74 - p75 i/o i int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable 03h 0bh 13h 1bh port 8 p80 - p83 p84 - p87 i i/o 4-bit input/output port input/output in bit unit 4-bit input port other function ad input port (8 port pins) s0/t0 to s6/t6 o output for vfd display controller segment/timing in common pull-down resistor : provided/not provided (each bit) (continue)
LC866548/40/32/28/24a no.6700-8/21 pin name i/o function description option s7/t7 to s15/t15 o output for vfd display controller segment/timing with internal pull-down resistor in common internal pull-down resistor output output for vfd display controller segment other function s16 : high voltage input port pc0 s17 : high voltage input port pc1 s18 : high voltage input port pc2 s19 : high voltage input port pc3 s20 : high voltage input port pc4 s21 : high voltage input port pc5 s22 : high voltage input port pc6 s23 : high voltage input port pc7 s24 : high voltage input port pd0 s25 : high voltage input port pd1 s26 : high voltage input port pd2 s27 : high voltage input port pd3 s28 : high voltage input port pd4 s29 : high voltage input port pd5 s30 : high voltage input port pd6 s31 : high voltage input port pd7 s16 to s31 i/o pull-down resistor : provided/not provided (each bit) output for vfd display controller segment other function s32 : high voltage input port pe0 s33 : high voltage input port pe1 s34 : high voltage input port pe2 s35 : high voltage input port pe3 s36 : high voltage input port pe4 s37 : high voltage input port pe5 s38 : high voltage input port pe6 s39 : high voltage input port pe7 s40 : high voltage i/o port pf0 s41 : high voltage i/o port pf1 s42 : high voltage i/o port pf2 s43 : high voltage i/o port pf3 s44 : high voltage i/o port pf4 s45 : high voltage i/o port pf5 s46 : high voltage i/o port pf6 s47 : high voltage i/o port pf7 s32 to s47 i/o pull-down resistor : provided/not provided (each bit) output for vfd display controller segment other function s48 : high voltage i/o port pg0 s49 : high voltage i/o port pg1 s50 : high voltage i/o port pg2 s51 : high voltage i/o port pg3 s48 to s51 i/o res i reset pin xt1/ p74 i input pin for 32.768khz crystal oscillation other function p74 for input port in case of non use, connect to vdd1. (continue)
LC866548/40/32/28/24a no.6700-9/21 pin name i/o function description option xt2/p75 o output pin for 32.768khz crystal oscillation other function p75 for input port in case of non use, at using as oscillator, should be left opened. at using as a port, connect to vdd1. cf1 i input pin for ceramic resonator oscillation cf2 o output pin for ceramic resonator oscillation * all of port options (except pull-up resistor of port 0) can be specified in bit unit. * a state of pins at reset pin name input/output mode a state of pull-up resistor specified at pull-up option port 0 input fixed pull-up resistor off ports 1, 3 input programmable pull-up resistor off s0/t0 to s15/t15 p channel transistor off s16 to s51 p channel transistor off *1 connect like the following figure to reduce noise into a vdd1 terminal. shorted the vss1 terminal to the vss2 terminal and to make the back-up time long. power supply lsi vdd1 back-up capacitor vdd2 vdd3 vss2 vss1 vdd4 vfd powers
LC866548/40/32/28/24a no.6700-10/21 1. absolute maximum ratings at vss1=vss2=0v and ta=25 c ratings parameter symbol pins conditions vdd[v] min. typ. max. unit supply voltage vdd max vdd1, vdd2 vdd3, vdd4 vdd1=vdd2 =vdd3=vdd4 -0.3 +7.0 vi(1) ports 74 ,75 ports 80,81,82, 83 port 8 res -0.3 vdd+0.3 input voltage vi(2) vp vdd-45 vdd+0.3 output voltage vo s0/t0-s15/t15 vdd-45 vdd+0.3 vio(1) port 1 ports 70,71,72, 73 ports 84,85,86, 87 ports 0, 3 at cmos output option -0.3 vdd+0.3 vio(2) ports 0, 3 at n-ch open drain output option -0.3 15 input/output voltage vio(3) s16 - s51 vdd-45 vdd+0.3 v ioph(1) ports 0, 1, 3 cmos output for each pin. -10 ioph(2) s0/t0-s15/t15 for each pin. -30 peak output current ioph(3) s16 - s51 for each pin. -15 ioah(1) port 0 -30 ioah(2) ports 1, 3 -30 ioah(3) s0/t0-s15/t15 -55 ioah(4) s16 - s27 -60 ioah(5) s28 - s39 -60 high level output current total output current ioah(6) s40 - s51 the total of all pins. -60 iopl(1) ports 0, 1, 3 20 peak output current iopl(2) ports 70,71,72, 73 ports 84,85,86, 87 for each pin. 15 ioal(1) port 0 60 ioal(2) ports 1, 3, 70 50 low level output current total output current ioal(3) ports 71,72, 73 ports 84,85,86, 87 the total of all pins. 20 ma power dissipation (max.) pdmax qfp100e ta=-30 to+70 c 500 mw operating temperature range topr -30 70 storage temperature range tstg -55 125 c
LC866548/40/32/28/24a no.6700-11/21 2. recommended operating range at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit operating supply voltage range vdd(1) vdd1=vdd2 =vdd3=vdd4 0.98 s tcyc tcyc 400 s 4.5 6.0 hold voltage vhd vdd1=vdd2 rams and the registers hold voltage at hold mode. 2.0 6.0 pull-down voltage vp vp 4.5 - 6.0 -35 vdd vih(1) port 0 at cmos output option output disable 4.5 - 6.0 0.33vdd +1.0 vdd vih(2) port 0 at n-ch open drain output output disable 4.5 - 6.0 0.75vdd 13.5 vih(3) port 1 ports 72, 73 port 3 at cmos output option output disable 4.5 - 6.0 0.75vdd vdd vih(4) port 3 at n-ch open drain output output disable tr. off 4.5 - 6.0 0.75vdd 13.5 vih(5) port 70 port input /interrupt port 71 res output disable 4.5 - 6.0 0.75vdd vdd vih(6) port 70 watchdog timer output disable 4.5 - 6.0 0.9vdd vdd vih(7) port 8 ports 74 , 75 output disable 4.5 - 6.0 0.75vdd vdd input high voltage vih(8) s16 - s51 output p-channel tr. off 4.5 - 6.0 0.33vdd +1.0 vdd vil(1) port 0 at cmos output option output disable 4.5 - 6.0 vss 0.2vdd vil(2) port 0 at n-ch open drain output output disable 4.5 - 6.0 vss 0.25vdd vil(3) ports 1, 3 ports 72, 73 output disable 4.5 - 6.0 vss 0.25vdd vil(4) port 70 port input /interrupt port 71 res output disable 4.5 - 6.0 vss 0.25vdd vil(5) port 70 watchdog timer output disable 4.5 - 6.0 vss 0.8vdd -1.0 vil(6) port 8 ports 74 , 75 output disable 4.5 - 6.0 vss 0.25vdd input low voltage vil(7) s16 - s51 output p-channel tr. off 4.5 - 6.0 vp 0.2vdd v operation cycle time tcyc 4.5 - 6.0 0.98 400 s (continue)
LC866548/40/32/28/24a no.6700-12/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit fmcf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 1 4.5 - 6.0 6 fmcf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 1 4.5 - 6.0 3 fmrc rc oscillation 4.5 - 6.0 0.3 0.8 3.0 mhz oscillation frequency range (note 1) fsx?tal xt1, xt2 32.768khz (crystal oscillation) refer to figure 2 4.5 - 6.0 32.768 khz tmscf(1) cf1, cf2 6mhz (ceramic resonator oscillation) refer to figure 3 4.5 - 6.0 0.1 3.0 tmscf(2) cf1, cf2 3mhz (ceramic resonator oscillation) refer to figure 3 4.5 - 6.0 0.1 3.0 ms oscillation stable time period (note 1) tssx?tal xt1, xt2 32.768khz (crystal oscillation) refer to figure 3 4.5 - 6.0 0.7 1.0 s (note 1) the oscillation constant is shown on table 1.
LC866548/40/32/28/24a no.6700-13/21 3. electrical characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iih(1) ports 0, 3 of open drain output output disable vin=13.5v (including off-leak current of the output tr.) 4.5 - 6.0 5 iih(2) port 0 without pull-up mos tr. ports 1, 3 output disable pull-up mos tr. off vin=vdd (including off-leak current of the output tr.) 4.5 - 6.0 1 iih(3) ports70,71,72,73 port 8 output disable vin=vdd (including off-leak current of the output tr.) 4.5 - 6.0 1 iih(4) res vin=vdd 4.5 - 6.0 1 iih(5) ports 74 , 75 vin=vdd 4.5 - 6.0 1 input high current iih(6) s16 to s51 without pull-down resistor (ports c, d, e, f,g) output p-channel tr. off vin=vdd 4.5 - 6.0 1 a iil(1) ports 1, 3 port 0 without pull-up mos tr. output disable pull-up mos tr. off vin=vss (including off-leak current of the output tr.) 4.5 - 6.0 -1 iil(2) ports70,71,72,73 port 8 output disable vin=vss (including off-leak current of the output tr.) 4.5 - 6.0 -1 iil(3) res vin=vss 4.5 - 6.0 -1 input low current iil(4) ports 74 , 75 vin=vss 4.5 - 6.0 -1 a voh(1) ioh=-1.0ma 4.5 - 6.0 vdd-1 voh(2) ports 0, 1, 3 of cmos output ioh=-0.1ma 4.5 - 6.0 vdd-0.5 voh(3) ioh=-20ma 4.5 - 6.0 vdd-1.8 voh(4) s0/t0 to s15/t15 ioh=-1ma the current of any unmeasurement pin is not over 1ma. 4.5 - 6.0 vdd-1 voh(5) ioh=-5ma 4.5 - 6.0 vdd-1.8 output high voltage voh(6) s16 to s51 the current of any unmeasurement pin is not over 1ma. 4.5 - 6.0 vdd-1 v (continue)
LC866548/40/32/28/24a no.6700-14/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit vol(1) iol=10ma 4.5 - 6.0 1.5 vol(2) ports 0, 1, 3 iol=1.6ma 4.5 - 6.0 0.4 vol(3) port 70 iol=1ma 4.5 - 6.0 0.4 output low voltage vol(4) ports 71, 72, 73 ports84,85,86,87 iol=1.6ma 4.5 - 6.0 0.4 v pull-up mos tr. resistor rpu ports 0, 1, 3 voh=0.9vdd 4.5 - 6.0 15 40 70 k ? ioff(1) output p-ch tr. off vout=vss 4.5 - 6.0 -1 output off- leak current ioff(2) s0/t0 to s6/t6, s16 to s51 with- out pull-down resistor output p-ch tr. off vout=vdd-40v 4.5 - 6.0 -30 a resistance of the low level hold tr. rinpd s16 to s51 output p-ch tr. off using as input ports 4.5 - 6.0 200 high voltage pull-down resistor rpd s0/t0 to s15/t15, s16 to s51 with pull-down resistor output p-ch tr. off vout=3v vp=-30v 5.0 60 100 200 vp pull-down resistor rvppd vp vss=gnd vp=-30v 5.0 60 100 200 k ? hysteresis voltage vhis port 1 ports 70, 71, 72, 73, 75 res output disable 4.5 - 6.0 0.1 vdd v pin capacitance cp all pins f=1mhz unmeasurement terminals for the input are set to vss level. ta=25 c 4.5 - 6.0 10 pf
LC866548/40/32/28/24a no.6700-15/21 4. serial input/output characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit cycle tckcy(1) 2 low level pulse width tckl(1) 1 input clock high level pulse width tckh(1) sck0 sck1 refer to figure 5. 4.5 - 6.0 1 cycle tckcy(2) 2 low level pulse width tckl(2) 1/2tckcy serial clock output clock high level pulse width tckh(2) sck0 sck1 use pull-up resistor (1k ? ) when open drain output. refer to figure 5. 4.5 - 6.0 1/2tckcy tcyc data set up time tick 0.1 serial input data hold time tcki si0 si1 sb0 sb1 data set-up to sck0, 1. data hold from sck0, 1. refer to figure 5. 4.5 - 6.0 0.1 output delay time (serial clock is external clock) tcko(1) 7/12tcyc +0.2 serial output output delay time (serial clock is internal clock) tcko(2) so0 so1 sb0 sb1 use pull-up resistor (1k ? ) when open drain output. data hold from sck0, 1 refer to figure 5. 4.5 - 6.0 1/3tcyc +0.2 s 5. pulse input conditions at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit tpih(1) tpil(1) int0, int1 int2/t0in interrupt acceptable timer0-countable 4.5 - 6.0 1 tpih(2) tpil(2) int3/t0in (the noise rejection clock is select to 1/1.) interrupt acceptable timer0-countable 4.5 - 6.0 2 tpih(3) tpil(3) int3/t0in (the noise rejection clock is select to 1/16.) interrupt acceptable timer0-countable 4.5 - 6.0 32 tpih(4) tpil(4) int3/t0in (the noise rejection clock is select to 1/64.) interrupt acceptable timer0-countable 4.5 - 6.0 128 tcyc high/low level pulse width tpil(5) res reset acceptable 4.5 - 6.0 200 s
LC866548/40/32/28/24a no.6700-16/21 6. ad converter characteristics at ta=-30 c to + 70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit resolution n 4.5 - 6.0 8 bit absolute precision (note2) et 4.5 - 6.0 1.5 lsb ad conversion time =16 tcyc (adcr2=0) *note3 4.5 - 6.0 15.68 (tcyc =0.98 s) 65.28 (tcyc =4.08 s) conversion time tcad ad conversion time =32 tcyc (adcr2=1) *note3 4.5 - 6.0 31.36 (tcyc =0.98 s) 130.56 (tcyc =4.08 s) s analog input voltage range vain 4.5 - 6.0 vss vdd v iainh vain=vdd 4.5 - 6.0 1 analog port input current iainl an0 - an7 vain=vss 4.5 - 6.0 -1 a (note 2) absolute precision excepts quantizing error (1/2 lsb). (note 3) the conversion time means the time from executing the ad conversion instruction to setting the complete digital conversion value to the register. 7. current dissipation characteristics at ta=-30 c to +70 c, vss1=vss2=0v ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddop(1) fmcf=6mhz ceramic resonator oscillation internal rc oscillation stops. fsxtal=32.768khz crystal oscillation system clock : cf oscillation 1/1 divided 4.5 - 6.0 10 25 iddop(2) fmcf=3mhz ceramic resonator oscillation internal rc oscillation stops. fsxtal=32.768khz crystal oscillation system clock : cf oscillation 1/2 divided 4.5 - 6.0 3 9 iddop(3) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscillation 1/2 divided 4.5 - 6.0 0.7 3.4 ma current dissipation during basic operation (note 4) iddop(4) fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscillation internal rc oscillation stops. 1/2 divided 4.5 - 6.0 35 130 a
LC866548/40/32/28/24a no.6700-17/21 ratings parameter symbol pins conditions vdd[v] min. typ. max. unit iddhalt(1) halt mode fmcf=6mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation internal rc oscillation stops. system clock : cf oscillation 1/1 divided 4.5 - 6.0 5 14 iddhalt(2) halt mode fmcf=3mhz ceramic resonator oscillation fsxtal=32.768khz crystal oscillation internal rc oscillation stops. system clock : cf oscillation 1/2 divided 4.5 - 6.0 2.2 7 ma iddhalt(3) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : rc oscilaltion 1/2 divided 4.5 - 6.0 400 1600 current dissipation halt mode (note 4) iddhalt(4) halt mode fmcf=0hz (when oscillation stops) fsxtal=32.768khz crystal oscillation system clock : crystal oscilaltion internal rc oscillation stops. 1/2 divided 4.5 - 6.0 25 100 a current dissipation hold mode (note 4) iddhold(1) hold mode 4.5 - 6.0 0.05 30 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored. table 1. ceramic resonator oscillation guaranteed constant (main clock) oscillation type maker oscillator c1 c2 csa6.00mg 33pf 33pf murata cst6.00mgw on chip kbr-6.0msb 33pf 33pf pbrc6.00a (chip type) 33pf 33pf kbr-6.0mkc 6mhz ceramic resonator oscillation kyocera pbrc6.00b (chip type) on chip csa3.00mg 33pf 33pf murata cst3.00mgw on chip 3mhz ceramic resonator oscillation kyocera kbr-3.0ms 33pf 33pf * both c1 and c2 must be a k rank (10%) and sl characteristics.
LC866548/40/32/28/24a no.6700-18/21 table 2. crystal oscillation guaranteed constant (sub clock) oscillation type maker oscillator c1 c2 rf rd epson c-002rx 18pf 18pf 10m ? 680k ? cfs-308 32.768khz crystal oscillation citizen cfs-206 18pf 18pf 10m ? 330k ? * both c3 and c4 must use j rank (5%) and ch characteristics. (it is about the application which is not in need of high precision. use k rank (10%) and sl characteristics.) (notes) since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the osci llation pins as possible with the shortest possible pattern length. if you use other oscillators herein, we provide no guarantee for the characteristics. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit c1 c2 cf cf2 cf1 c3 rd c4 x?tal xt2 xt1 rf
LC866548/40/32/28/24a no.6700-19/21 < reset time and oscillation stabilizing time. > < hold release signal and oscillation stabilizing time. > figure 3 oscillation stable time figure 4 reset circuit (note) fix the value of c res , r res that is sure to reset until 200 s, after powe r supply has been over inferior limit o f supply voltage. vdd vdd limit 0v reset time tmscf tssxtal power suppl y res internal rc resonator oscillation cf1, cf2 operation mode xt1, xt2 unfixed reset instruction execution mode instruction execution mode ocr6=1 tmscf tssxtal internal rc resonator oscillation cf1, cf2 operation mode xt1, xt2 hold instruction execution mode valid hold release signal res vdd r res c res
LC866548/40/32/28/24a no.6700-20/21 figure 5 serial input / output test condition figure 6 pulse input timing condition 0.5vdd tckcy tckl tckh tick tcki tcko sck0 sck1 si0 si1 so0, so1 sb0 , sb1 vdd 1k ? 50pf tpil tpih
LC866548/40/32/28/24a no.6700-21/21 ps

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