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general description the MAX5865 ultra-low-power, highly integrated analog front end is ideal for portable communication equipment such as handsets, pdas, wlan, and 3g wireless termi- nals. the MAX5865 integrates dual 8-bit receive adcs and dual 10-bit transmit dacs while providing the high- est dynamic performance at ultra-low power. the adcs analog i-q input amplifiers are fully differential and accept 1v p-p full-scale signals. typical i-q channel phase matching is 0.2 and amplitude matching is 0.05db. the adcs feature 48.4db sinad and 70dbc spurious-free dynamic range (sfdr) at f in = 5.5mhz and f clk = 40mhz. the dacs?analog i-q outputs are fully differential with 400mv full-scale output, and 1.4v com- mon-mode level. typical i-q channel phase matching is 0.15 and gain matching is 0.05db. the dacs also feature dual 10-bit resolution with 72dbc sfdr, and 57db snr at f out = 2.2mhz and f clk = 40mhz. the adcs and dacs operate simultaneously or indepen- dently for frequency-division duplex (fdd) and time-divi- sion duplex (tdd) modes. a 3-wire serial interface controls power-down and transceiver modes of opera- tion. the typical operating power is 75.6mw at f clk = 40msps with the adcs and dacs operating simultane- ously in transceiver mode. the MAX5865 features an internal 1.024v voltage reference that is stable over the entire operating power-supply range and temperature range. the MAX5865 operates on a +2.7v to +3.3v ana- log power supply and a +1.8v to +3.3v digital i/o power supply for logic compatibility. the quiescent current is 8.5ma in idle mode and 1? in shutdown mode. the MAX5865 is specified for the extended (-40? to +85?) temperature range and is available in a 48-pin thin qfn package. applications narrowband/wideband cdma handsets and pdas fixed/mobile broadband wireless modems 3g wireless terminals features integrated dual 8-bit adcs and dual 10-bit dacs ultra-low power 75.6mw at f clk = 40mhz (transceiver mode) 64mw at f clk = 22mhz (transceiver mode) low-current idle and shutdown modes excellent dynamic performance 48.4db sinad at f in = 5.5mhz (adc) 70db sfdr at f out = 2.2mhz (dac) excellent gain/phase match 0.2 phase, 0.05db gain at f in = 5.5mhz (adc) internal/external reference option +1.8v to +3.3v digital output level (ttl/cmos compatible) multiplexed parallel digital input/output for adcs/dacs miniature 48-pin thin qfn package (7mm ? 7mm) evaluation kit available (order MAX5865evkit) MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ________________________________________________________________ maxim integrated products 1 adc adc ia+ ia- qa+ qa- id+ id- qd+ qd- refp com refn din sclk cs refin dac dac adc output mux dac input mux clk da0?a7 dd0?d9 max 5865 ref and bias serial interface and system control functional diagram 19-2916; rev 1; 10/03 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package MAX5865etm -40 c to +85 c 48 thin qfn-ep* (7mm x 7mm) MAX5865e/d -40 c to +85 c dice** * ep = exposed paddle. ** contact factory for dice specifications. pin configuration appears at end of data sheet.
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd, ov dd to ognd................................-0.3v to +3.3v gnd to ognd.......................................................-0.3v to +0.3v ia+, ia-, qa+, qa-, id+, id-, qd+, qd-, refp, refn, refin, com to gnd ..............................-0.3v to (v dd + 0.3v) dd0 dd9, sclk, din, cs , clk, da0 da7 to ognd .............................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70 c) 48-pin thin qfn (derate 26.3mw/ c above +70 c)..............................................................................2.1w thermal resistance ja .................................................+38 c/w operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-60 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage v dd 2.7 3.0 3.3 v output supply voltage ov dd 1.8 v dd v ad c op er ati ng m od e, f in = 5.5m h z, f c lk = 40m h z, d ac op er ati ng m od e, f ou t = 2.2m h z 25.2 32 adc operating mode (rx), f in = 5.5mhz, f clk = 40m h z, dac digital inputs at zero or ov d d 21 dac operating mode (tx), f out = 2.2mhz, f clk = 40m h z, adc off 12.8 standby mode, dac digital inputs and clk at zero or ov dd 2.0 idle mode, dac digital inputs at zero or ov dd , f clk = 40m h z 11 ma v dd supply current shutdown mode, digital inputs and clk at zero or ov dd , cs = ov dd 1a adc operating mode, f in = 5.5mhz, f clk = 40msps, dac operating mode, f out = 2.2mhz 3.8 ma idle mode, dac digital inputs at zero or ov dd, f clk = 40m h z 37.4 ov dd supply current shutdown mode, dac digital inputs and clk at zero or ov dd , cs = ov dd 1 a
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units adc dc accuracy resolution 8 bits integral nonlinearity inl 0.15 lsb differential nonlinearity dnl no missing codes over temperature 0.15 lsb offset error residual dc offset error 0.22 5 %fs gain error includes reference error 0.48 5 %fs dc gain matching 0.03 0.25 db offset matching 3 lsb gain temperature coefficient 42 ppm/ c offset error (v dd 5%) 0.2 power-supply rejection psrr gain error (v dd 5%) 0.07 lsb adc analog input input differential range v id differential or single-ended inputs 0.512 v input common-mode voltage range v dd / 2 v r in switched capacitor load 120 k ? input impedance c in 5pf adc conversion rate maximum clock frequency f clk (note 2) 40 mhz channel i 5 data latency channel q 5.5 clock cycles adc dynamic characteristics (note 3) f in = 5.5mhz 47 48.5 signal-to-noise ratio snr f in = 20mhz 48.2 db f in = 5.5mhz 46.5 48.4 signal-to-noise and distortion ratio sinad f in = 20mhz 48.2 db f in = 5.5mhz 58 70 spurious-free dynamic range sfdr f in = 20mhz 70 dbc f in = 5.5mhz -75.4 third-harmonic distortion hd3 f in = 20mhz -75 dbc intermodulation distortion imd f 1 = 2mhz, -7dbfs; f 2 = 2.01mhz, -7dbfs -66 dbc third-order intermodulation distortion im3 f 1 = 2mhz, -7dbfs; f 2 = 2.01mhz, -7dbfs -70 dbc f in = 5.5mhz -71 -57 total harmonic distortion thd f in = 20mhz -70 dbc
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) large-signal bandwidth fbw a in = -0.5dbfs 440 mhz aperture delay 3.3 ns aperture jitter 2.7 ps rms overdrive recovery time 1.5 full-scale input 2 ns adc interchannel characteristics crosstalk rejection f inx = 5.5mhz at -0.5dbfs, f iny = 0.3mhz at -0.5dbfs (note 5) -75 db amplitude matching f in = 5.5mhz at -0.5dbfs (note 6) 0.05 db phase matching f in = 5.5mhz at -0.5dbfs (note 6) 0.2 d eg r ees dac dc accuracy resolution n 10 bits integral nonlinearity inl 1 lsb differential nonlinearity dnl guaranteed monotonic 0.5 lsb zero-scale error residual dc offset 3 lsb full-scale error include reference error -35 +35 lsb dac dynamic performance dac conversion rate (note 2) 40 msps noise over nyquist n d f out = 2.2mhz, f clk = 40mhz -130.6 dbc/hz output-of-band noise power density n o f out = 1.2mhz, f clk = 22mhz, offset = 10mhz -130.9 dbc/hz glitch impulse 10 pvs f clk = 40mhz f out = 2.2mhz 59 72.3 spurious-free dynamic range sfdr f clk = 22mhz f out = 200khz 73.5 dbc total harmonic distortion (to nyquist) thd f clk = 40mhz, f out = 2.2mhz -70 -58.5 db signal-to-noise ratio (to nyquist) snr f clk = 40mhz, f out = 2.2mhz 57 db dac interchannel characteristics dac-to-dac output isolation f outx, y = 2.2mhz, f outx, y = 2.0mhz 80 db gain mismatch between dac outputs f out = 2.2mhz, f clk = 40mhz 0.05 db phase mismatch between dac outputs f out = 2.2mhz, f clk = 40mhz 0.15 d eg r ees
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units dac analog output full-scale output voltage v fs 400 mv output common-mode range 1.29 1. 5 v adc-dac interchannel characteristics adc-dac isolation adc f ini = f inq = 5.5mhz, dac f outi = f outq = 2.2mhz, f clk = 40mhz 75 db adc-dac timing characteristics clk rise to i-adc channel-i output data valid t doi figure 3 (note 4) 7.4 9 ns clk fall to q-adc channel-q output data valid t doq figure 3 (note 4) 6.9 9 ns i-dac data to clk fall setup time t dsi figure 4 (note 4) 10 ns q-dac data to clk rise setup time t dsq figure 4 (note 4) 10 ns clk fall to i-dac data hold time t dhi figure 4 (note 4) 0 ns c lk ri se to q- d ac d ata h ol d ti m e t dhq figure 4 (note 4) 0 ns clock duty cycle 50 % clk duty-cycle variation 15 % digital output rise/fall time 20% to 80% 2.6 ns serial interface timing characteristics falling edge of cs to rising edge of first sclk time t css figure 5 (note 4) 10 ns din to sclk setup time t ds figure 5 (note 4) 10 ns din to sclk hold time t dh figure 5 (note 4) 0 ns sclk pulse width high t ch figure 5 (note 4) 25 ns sclk pulse width low t cl figure 5 (note 4) 25 ns sclk period t cp figure 5 (note 4) 50 ns sclk to cs setup time t cs figure 5 (note 4) 0 ns cs high pulse width t csw figure 5 (note 4) 80 ns mode recovery timing characteristics from shutdown to rx mode, figure 6, adc settles to within 1db 20 shutdown wake-up time t wake , sd from shutdown to tx mode, figure 6, dac settles to within 10 lsb error 40 s
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units from idle to rx mode with clk present during idle, figure 6, adc settles to within 1db sinad 10 idle wake-up time (with clk) t wake , st0 from idle to tx mode with clk present during idle, figure 6, dac settles to 10 lsb error 10 s from standby to rx mode, figure 6, adc settles to within 1db sinad 10 standby wake-up time t wake , st1 from standby to tx mode, figure 6, dac settles to 10 lsb error 40 s enable time from xcvr or tx to rx t enable , rx adc settles to within 1db sinad 10 s enable time from xcvr or rx to tx t enable , tx dac settles to 10 lsb error 10 s internal reference (refin = v dd . v refp , v refn and v com are generated internally.) positive reference v refp - v com 0.256 v negative reference v refn - v com -0.256 v common-mode output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v differential reference output v ref v refp - v refn +0.49 +0.512 +0.534 v differential reference temperature coefficient reftc 30 ppm/ c maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma buffered external reference (refin = 1.024v. v refp , v refn , and v com are generated internally.) reference input v refin 1.024 v differential reference output v diff v refp - v refn 0.512 v common-mode output voltage v com v dd / 2 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma refin input resistance >500 k ? refin input current -0.7 a digital inputs (clk, sclk, din, cs , dd0?d9) input high threshold v inh dd0 dd9, clk, sclk, din, cs 0.7 x ov dd v
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, unless otherwise noted. typical values are at t a = +25 c, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units input low threshold v inl dd0 dd9, clk, sclk, din, cs 0.3 x ov dd v input leakage di in dd0 dd9, clk, sclk, din, cs = ognd or ov dd 5a input capacitance dc in 5pf digital outputs (da0 da7) output voltage low v ol i sink = 200a 0.2 x ov dd v output voltage high v oh i source = 200a 0.8 x ov dd v tri-state leakage current i leak 5a tri-state output capacitance c out 5pf note 1: specifications from t a = +25 c to +85 c are guaranteed by product tests. specifications from t a = +25 c to -40 c are guaranteed by design and characterization. note 2: the minimum clock frequency for the MAX5865 is 22mhz. note 3: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5dbfs referenced to the amplitude of the digital outputs. sinad and thd are calculated using hd2 through hd6. note 4: guaranteed by design and characterization. note 5: crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec- ond channel. ffts are performed on each channel. the parameter is specified as the power ratio of the first and second channel fft test tone bins. note 6: amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and phase of the fundamental bin on the calculated fft. typical operating characteristics (v dd = dv dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, t a = +25 c, unless otherwise noted.) -110 -70 -90 -30 -50 -10 -80 -100 -40 -60 hd3 hd2 q a ia -20 0 048121620 adc channel-ia fft plot MAX5865 toc01 frequency (mhz) amplitude (dbfs) f clk = 40mhz f ia = 12.499mhz f qa = 19.99mhz a ia = a qa = 0.5dbfs 8192-point data record -110 -70 -90 -30 -50 -10 -80 -100 -40 -60 i a -20 0 048121620 adc channel-qa fft plot MAX5865 toc02 frequency (mhz) amplitude (dbfs) f clk = 40mhz f ia = 12.499mhz f qa = 19.99mhz a ia = a qa = 0.5dbfs 8192-point data record hd2 hd3 qa -110 -70 -90 -30 -50 -10 -80 -100 -40 -60 f 2 -20 0 048121620 adc channel-ia two-tone fft plot MAX5865 toc03 frequency (mhz) amplitude (dbfs) f 1 f clk = 40mhz f 1 = 1.8mhz f 2 = 2.2mhz a ia = a qa = -7dbfs per tone 8192-point data record
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 8 _______________________________________________________________________________________ -80 -75 -70 -65 -60 -55 -50 -45 -40 0 25 50 75 100 125 adc total harmonic distortion vs. analog input frequency MAX5865 toc07 analog input frequency (mhz) thd (db) 50 55 60 65 70 75 80 0 25 50 75 100 125 adc spurious-free dynamic range vs. analog input frequency MAX5865 toc08 analog input frequency (mhz) sfdr (dbc) 40 45 50 55 65 50 75 70 80 0 25 50 75 100 125 adc spurious-free dynamic range vs. analog input frequency MAX5865 toc09 analog input frequency (mhz) sfdr (dbc) single-ended 0 10 20 ia qa 30 50 40 60 -24 -20 -16 -12 -8 -4 0 adc signal-to-noise ratio vs. analog input power MAX5865 toc10 analog input power (dbfs) snr (db) f in = 10.0732mhz 0 10 20 30 50 40 60 -24 -20 -16 -12 -8 -4 0 adc signal-to-noise and distortion ratio vs. analog input power MAX5865 toc11 analog input power (dbfs) sinad (db) f in = 10.0732mhz -80 -75 -70 -65 -35 -40 -45 -55 -60 -50 -30 -24 -20 -16 -12 -8 -4 0 adc total harmonic distortion vs. analog input power MAX5865 toc12 analog input power (dbfs) thd (db) f in = 10.0732mhz typical operating characteristics (continued) (v dd = dv dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, t a = +25 c, unless otherwise noted.) -110 -70 -90 -30 -50 -10 -80 -100 -40 -60 -20 0 048121620 adc channel-qa two-tone fft plot MAX5865 toc04 frequency (mhz) amplitude (dbfs) f clk = 40mhz f 1 = 1.8mhz f 2 = 2.2mhz a ia = -7dbfs per tone 8192-point data record f 2 f 1 46.0 46.5 47.0 47.5 48.0 48.5 ia qa 49.0 49.5 50.0 0 25 50 75 100 125 adc signal-to-noise ratio vs. analog input frequency MAX5865 toc05 analog input frequency (mhz) snr (db) 46.0 46.5 47.0 47.5 48.0 48.5 ia qa 49.0 49.5 50.0 0 25 50 75 100 125 adc signal-to-noise and distortion ratio vs. analog input frequency MAX5865 toc06 analog input frequency (mhz) sinad (db)
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end _______________________________________________________________________________________ 9 -80 -75 -70 -55 -60 -65 -50 22 24 28 32 26 30 34 36 38 40 adc total harmonic distortion vs. sampling rate MAX5865 toc16 sampling rate (mhz) thd (db) f in = 10.0732mhz 50 55 60 75 70 65 80 22 24 28 32 26 30 34 36 38 40 adc spurious-free dynamic range vs. sampling rate MAX5865 toc17 sampling rate (mhz) sfdr (dbc) f in = 10.0732mhz adc signal-to-noise ratio vs. clock duty cycle MAX5865 toc18 clock duty cycle (%) snr (db) 65 55 60 45 50 40 35 46 47 48 49 50 45 30 70 ia f in = 10.0732mhz qa adc signal-to-noise and distortion ratio vs. clock duty cycle MAX5865 toc19 clock duty cycle (%) sinad (db) 65 55 60 50 45 40 35 46 47 48 49 50 45 30 70 f in = 10.0732mhz qa ia -80 -78 -74 -62 -66 -70 -76 -64 -68 -72 -60 30 40 50 60 70 adc total harmonic distortion vs. clock duty cycle MAX5865 toc20 clock duty cycle (%) thd (db) f in = 10.0732mhz 50 55 65 75 60 70 80 30 40 50 60 70 adc spurious-free dynamic range vs. clock duty cycle MAX5865 toc21 clock duty cycle (%) sfdr (dbc) f in = 10.0732mhz typical operating characteristics (continued) (v dd = dv dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, t a = +25 c, unless otherwise noted.) 30 35 40 45 75 70 65 55 50 60 80 -24 -20 -16 -12 -8 -4 0 adc spurious-free dynamic range vs. analog input power MAX5865 toc13 analog input power (dbfs) sfdr (dbc) f in = 10.0732mhz 44 45 46 49 48 47 50 22 24 28 32 26 30 34 36 38 40 adc signal-to-noise ratio vs. sampling rate MAX5865 toc14 sampling rate (mhz) snr (db) f in = 10.0732mhz qa ia 45 46 47 49 48 50 22 24 28 32 26 30 34 36 38 40 adc signal-to-noise and distortion ratio vs. sampling rate MAX5865 toc15 sampling rate (mhz) sinad (db) f in = 10.0732mhz qa ia
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 10 ______________________________________________________________________________________ dac spurious-free dynamic range vs. sampling rate MAX5865 toc25 sampling rate (mhz) sfdr (dbc) 38 36 32 34 26 28 30 24 62 64 66 68 70 72 74 76 78 80 60 22 40 f out = f clk /10 dac spurious-free dynamic range vs. output frequency MAX5865 toc26 frequency (mhz) sfdr (dbc) 15 10 5 55 60 65 70 75 80 50 020 dac spurious-free dynamic range vs. output power MAX5865 toc27 output power (dbfs) sfdr (dbc) -5 -10 -15 -20 -25 40 50 60 70 80 90 30 -30 0 f out = 2mhz dac channel-id spectral plot MAX5865 toc28 frequency (mhz) amplitude (db) 15 10 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 f id = 5.498mhz f id dac channel-qd spectral plot MAX5865 toc29 frequency (mhz) amplitude (db) 15 10 5 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 f qd = 5.498mhz f qd dac channel-id two-tone spectral plot MAX5865 toc30 frequency (mhz) amplitude (db) 18.0 14.5 11.0 7.5 4.0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.5 f 1 f 2 f 1 = 4mhz, f 2 = 4.5mhz, -7dbfs typical operating characteristics (continued) (v dd = dv dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, t a = +25 c, unless otherwise noted.) -1.0 -0.8 0 0.8 -0.4 0.4 -0.2 0.6 -0.6 0.2 1.0 -40 -15 35 10 60 85 adc offset error vs. temperature MAX5865 toc22 temperature ( c) offset error (%fs) 0 0.2 1.0 1.8 0.6 1.4 0.8 1.6 0.4 1.2 2.0 -40 -15 35 10 60 85 adc gain error vs. temperature MAX5865 toc23 temperature ( c) gain error (%fs) 0 10 20 i dd i ovdd 5 15 25 22 26 34 30 38 supply current vs. sampling rate MAX5865 toc24 sampling rate (mhz) supply current (ma) rx mode only
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________ 11 adc integral nonlinearity MAX5865 toc34 digital output code inl (lsb) 224 192 128 160 64 96 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 adc differential nonlinearity MAX5865 toc35 digital output code dnl (lsb) 224 192 128 160 64 96 32 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 dac integral nonlinearity MAX5865 toc36 digital input code inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 dac differential nonlinearity MAX5865 toc37 digital input code dnl (lsb) 896 768 512 640 256 384 128 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 1024 reference output voltage vs. temperature MAX5865 toc38 temperature ( c) v refp - v refn (v) 60 35 10 -15 0.505 0.510 0.515 0.520 0.500 -40 85 v refp - v refn typical operating characteristics (continued) (v dd = dv dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 40mhz 50% duty cycle, adc input amplitude = -0.5dbfs, dac output amplitude = 0dbfs, differential adc input, differential dac output, c refp = c refn = c com = 0.33f, xcvr mode, t a = +25 c, unless otherwise noted.) dac channel-qd two-tone spectral plot MAX5865 toc31 frequency (mhz) amplitude (db) 18.0 14.5 11.0 7.5 4.0 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0.5 f 1 f 2 f 1 = 4mhz, f 2 = 4.5mhz, -7dbfs supply current vs. sampling rate MAX5865 toc33 sampling rate (mhz) supply current (ma) 38 36 34 32 30 28 26 24 5 10 15 20 25 30 0 22 40 i dd i ovdd xcvr mode
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 12 ______________________________________________________________________________________ pin name function 1 refp upper reference voltage. bypass with a 0.33f capacitor to gnd as close to refp as possible. 2, 8, 43 v dd analog supply voltage. bypass v dd to gnd with a combination of a 2.2f capacitor in parallel with a 0.1f capacitor. 3 ia+ channel ia positive analog input. for single-ended operation, connect signal source to ia+. 4 ia- channel ia negative analog input. for single-ended operation, connect ia- to com. 5, 7, 12, 37, 42 gnd analog ground. connect all pins to gnd ground plane. 6 clk conversion clock input. clock signal for both adcs and dacs. 9 qa- channel qa negative analog input. for single-ended operation, connect qa- to com. 10 qa+ channel qa positive analog input. for single-ended operation, connect signal source to qa+. 11, 33, 39 v dd analog supply voltage. connect to v dd power plane as close to the device as possible. 13 16, 19 22 da0 da7 adc tri-state digital output bits. da7 is the most significant bit (msb), and da0 is the least significant bit (lsb). 17 ognd output driver ground 18 ov dd output driver power supply. supply range from +1.8v to v dd to accommodate most logic levels. bypass ov dd to ognd with a combination of a 2.2f capacitor in parallel with a 0.1f capacitor. 23 32 dd0 dd9 dac digital input bits. dd9 is the msb, and dd0 is the lsb. 34 din 3-wire serial interface data input. data is latched on the rising edge of the sclk. 35 sclk 3-wire serial interface clock input 36 cs 3-wire serial interface chip select input. apply logic low enables the serial interface. 38 n.c. no connection 40, 41 qd+, qd- dac channel-qd differential voltage output 44, 45 id-, id+ dac channel-id differential voltage output 46 refin reference input. connect to v dd for internal reference. 47 com common-mode voltage i/o. bypass com to gnd with a 0.33f capacitor. 48 refn negative reference i/o. conversion range is (v refp - v refn ). bypass refn to gnd with a 0.33f capacitor. ep exposed paddle. exposed paddle is internally connected to gnd. connect ep to the gnd plane. pin description
detailed description the MAX5865 integrates dual 8-bit receive adcs and dual 10-bit transmit dacs while providing ultra-low power and highest dynamic performance at a conver- sion rate of 40msps. the adcs analog input amplifiers are fully differential and accept 1v p-p full-scale signals. the dacs analog outputs are fully differential with 400mv full-scale output range at 1.4v common mode. the MAX5865 includes a 3-wire serial interface to con- trol operating modes and power management. the ser- ial interface is spi and microwire compatible. the MAX5865 serial interface selects shutdown, idle, standby, transmit, receive, and transceiver modes. the MAX5865 can operate in fdd or tdd applications by configuring the device for transmit, receive, or trans- ceiver modes through a 3-wire serial interface. in tdd mode, the digital bus for receive adc and transmit dac can be shared to reduce the digital i/o to a single 10-bit parallel multiplexed bus. in fdd mode, the MAX5865 digital i/o can be configured for an 18-bit, parallel multiplexed bus to match the dual 8-bit adc and dual 10-bit dac. the MAX5865 features an internal precision 1.024v bandgap reference that is stable over the entire power- supply and temperature ranges. MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________ 13 spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. figure 1. MAX5865 adc internal t/h circuits s3b s3a com s5b s5a qa+ qa- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a ia+ ia- s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b MAX5865
MAX5865 dual 8-bit adc the adc uses a seven-stage, fully differential, pipelined architecture that allows for high-speed con- version while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel ia and 5.5 clock cycles for channel qa. the adc s full-scale analog input range is v ref with a common-mode input range of v dd /2 0.2v. v ref is the difference between v refp and v refn . see the reference configurations section for details. input track-and-hold (t/h) circuits figure 1 displays a simplified functional diagram of the adc s input t/h circuitry. in track mode, switches s1, s2a, s2b, s4a, s4b, s5a, and s5b are closed. the fully differential circuits sample the input signals onto the two capacitors (c2a and c2b) through switches s4a and s4b. s2a and s2b set the common mode for the amplifier input, and open simultaneously with s1, sam- pling the input waveform. switches s4a, s4b, s5a, and s5b are then opened before switches s3a and s3b connect capacitors c1a and c1b to the output of the amplifier and switch s4c is closed. the resulting differ- ential voltages are held on capacitors c2a and c2b. the amplifiers charge capacitors c1a and c1b to the same values originally held on c2a and c2b. these val- ues are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. the wide input bandwidth t/h amplifiers allow the adc to track and sample/hold analog inputs of high frequen- cies (> nyquist). both adc inputs (ia+, qa+, ia-, and qa-) can be driven either differentially or single ended. match the impedance of ia+ and ia-, as well as qa+ and qa-, and set the common-mode voltage to mid- supply (v dd /2) for optimum performance. adc digital output data (da0?a7) da0 da7 are the adcs digital logic outputs. the logic level is set by ov dd from 1.8v to v dd . the digital out- put coding is offset binary ( table 1, figure 2 ). the capacitive load on digital outputs da0 da7 should be kept as low as possible (<15pf) to avoid large digital currents feeding back into the analog portion of the MAX5865 and degrading its dynamic performance. buffers on the digital outputs isolate them from heavy capacitive loads. adding 100 ? resistors in series with the digital outputs close to the MAX5865 helps improve adc performance. refer to the MAX5865 ev kit schematic for an example of the digital outputs driving a digital buffer through 100 ? series resistors. ultra-low-power, high-dynamic- performance, 40msps analog front end 14 ______________________________________________________________________________________ table 1. output codes vs. input voltage differential input voltage differential input (lsb) offset binary (da7 da0) output decimal code 127 (+full scale - 1lsb) 1111 1111 255 126 (+full scale - 2lsb) 1111 1110 254 +1 1000 0001 129 0 (bipolar zero) 1000 0000 128 -1 0111 1111 127 -127 (-full scale + 1lsb) 0000 0001 1 -128 (-full scale) 0000 0000 0 v ref 127 128 v ref 126 128 v ref 1 128 v ref 0 128 v ref 1 128 ? v ref 127 128 ? v ref 128 128 ?
adc system timing requirements figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. channel ia (chi) and channel qa (chq) are simultaneously sam- pled on the rising edge of the clock signal (clk) and the resulting data is multiplexed at the da0 da7 out- puts. chi data is updated on the rising edge and chq data is updated on the falling edge of the clk. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for chi and 5.5 clock cycles for chq. dual 10-bit dac the 10-bit dacs are capable of operating with clock speeds up to 40mhz. the dac s digital inputs, dd0 dd9, are multiplexed on a single 10-bit bus. the voltage reference determines the data converters full- scale output voltages. see the reference configurations section for setting reference voltage. the dacs utilize a current-array technique with a 1ma (with 1.024v refer- ence) full-scale output current driving a 400 ? internal resistor resulting in a 400mv full-scale differential out- put voltage. the MAX5865 is designed for differential output only and is not intended for single-ended appli- cation. the analog outputs are biased at 1.4v common mode and designed to drive a differential input stage with input impedance 70k ? . this simplifies the analog interface between rf quadrature upconverters and the MAX5865. rf upconverters require a 1.3v to 1.5v com- mon-mode bias. the internal dc common-mode bias eliminates discrete level setting resistors and code-gen- erated level-shifting while preserving the full dynamic range of each transmit dac. table 2 shows the output voltage vs. input code. MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________ 15 figure 2. adc transfer function input voltage (lsb) -1 -126 -125 256 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+1 -127 +126 +128 +127 -128 +125 (com) (com) offset binary output code (lsb) 0000 0000 0000 0001 0000 0010 0000 0011 1111 1111 1111 1110 1111 1101 0111 1111 1000 0000 1000 0001 figure 3. adc system timing diagram t doq t doi 5 clock-cycle latency (chi), 5.5 clock-cycle latency (chq) da0 da7 d0q d1i d1q d2i d2q d3i d3q d4i d4q d5i d5q d6i d6q chi chq clk
MAX5865 dac timing figure 4 shows the relationship between the clock, input data, and analog outputs. data for the i channel (id) is latched on the falling edge of the clock signal, and q- channel (qd) data is latched on the rising edge of the clock signal. both i and q outputs are simultaneously updated on the next rising edge of the clock signal. 3-wire serial interface and operation modes the 3-wire serial interface controls the MAX5865 opera- tion modes. upon power-up, the MAX5865 must be pro- grammed to operate in the desired mode. use the 3-wire serial interface to program the device for the shutdown, idle, standby, rx, tx, or xcvr mode. an 8-bit data register sets the operation modes as shown in table 3 . the serial interface remains active in all six modes. ultra-low-power, high-dynamic- performance, 40msps analog front end 16 ______________________________________________________________________________________ table 2. dac output voltage vs. input codes (internal reference mode v refdac = 1.024v, external reference mode v refdac = v refin ) differential output voltage offset binary (dd0 dd9) input decimal code 11 1111 1111 1023 11 1111 1110 1022 10 0000 0001 513 10 0000 0000 512 01 1111 1111 511 00 0000 0001 1 00 0000 0000 0 v refdac 2.56 1023 1023 v refdac 2.56 1021 1023 v refdac 2.56 3 1023 v refdac 2.56 1 1023 v refdac 2.56 1 1023 ? v refdac 2.56 1021 1023 ? v refdac 2.56 1023 1023 ? figure 4. dac system timing diagram t dsq t dsi q: n-2 i: n-1 dd0 dd9 clk id qd q: n-1 i: n q: n i: n+1 n-2 n-1 n n-2 n-1 n t dhq t dhi
shutdown mode offers the most dramatic power sav- ings by shutting down all the analog sections of the MAX5865 and placing the adcs digital outputs in tri- state mode. when the adcs outputs transition from tri- state to on, the last converted word is placed on the digital outputs. the dacs digital bus inputs must be zero or ov dd because the bus is not internally pulled up. the dacs previously stored data is lost when com- ing out of shutdown mode. the wake-up time from shut- down mode is dominated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external refer- ence mode, the wake-up time is typically 40s to enter xcvr mode, 20s to enter rx mode, and 40s to enter tx mode. in idle mode, the reference and clock distribution cir- cuits are powered, but all other functions are off. the adcs outputs are forced to tri-state. the dacs digital bus inputs must be zero or ov dd , because the bus is not internally pulled up. the wake-up time from the idle mode is 10s required for the adcs and dacs to be fully operational. when the adcs outputs transition from tri-state to on, the last converted word is placed on the digital outputs. in the idle mode, the supply cur- rent is lowered if the clock input is set to zero or ov dd ; however, the wake-up time extends to 40s. in standby mode, only the adcs reference is powered; the rest of the device s functions are off. the pipeline adcs are off and da0 to da7 are in tri-state mode. the dacs digital bus inputs must be zero or ov dd because the bus is not internally pulled up. the wake- up time from standby mode to the xcvr mode is domi- nated by the 40s required to activate the pipeline adcs and dacs. when the adc outputs transition from tri-state to active, the last converted word is placed on the digital outputs. the serial digital interface is a standard 3-wire connec- tion compatible with spi/qspi /microwire/dsp interfaces. set cs low to enable the serial data loading at din. following cs high-to-low transition, data is shift- ed synchronously, msb first, on the rising edge of the serial clock (sclk). after 8 bits are loaded into the seri- al input register, data is transferred to the latch. cs must transition high for a minimum of 80ns before the next write sequence. the sclk can idle either high or low between transitions. figure 5 shows the detailed timing diagram of the 3-wire serial interface. MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________ 17 qspi is a trademark of motorola, inc. table 3. MAX5865 operation modes function description d7 ( msb ) d6 d5 d4 d3 d2 d1 d0 shutdown d evi ce shutd ow n. re f i s off, ad c s ar e off, and the ad c b us i s tr i - stated ; d ac s ar e off and the d ac i np ut b us m ust b e set to zer o or ov d d . xxxxx000 idle ref and clk are on, adcs are off, and the adc bus is tri-stated; dacs are off and the dac input bus must be set to zero or ov dd . xxxxx001 rx ref is on, adcs are on; dacs are off, and the dac input bus must be set to zero or ov dd . xxxxx010 tx ref is on, adcs are off, and the adc bus is tri-stated; dacs are on. xxxxx011 xcvr ref is on, adcs and dacs are on. x x x x x 1 0 0 standby ref is on, adcs are off, and the adc bus is tri-stated; dacs are off and the dac input bus must be set to zero or ov dd . xxxxx101 x = don? care.
MAX5865 mode recovery timing figure 6 shows the mode recovery timing diagram. t wake is the wake-up time when exiting shutdown, idle, or standby mode and entering into rx, tx, or xcvr mode. t enable is the recovery time when switching between any rx, tx, or xcvr mode. t wake or t enable is the time for the adc to settle within 1db of specified sinad performance and dac settling to 10 lsb error. t wake or t enable times are measured after the 8-bit serial command is latched into the MAX5865 by cs transition high. t enable for xcvr mode is dominated by the dac wake-up time. the recovery time is 10s to switch between xcvr, tx, or rx modes. the recovery time is 40s to switch from shutdown or standby mode to xcvr mode. system clock input (clk) clk input is shared by both the adcs and dacs. it accepts a cmos-compatible signal level set by ov dd from 1.8v to v dd . since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<2ns). specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. any significant clock jitter limits the snr performance of the on-chip adcs as follows: where f in represents the analog input frequency and t aj is the time of the clock jitter. snr tt in aj = ? ? ? ? ? ? 20 1 2 log ultra-low-power, high-dynamic- performance, 40msps analog front end 18 ______________________________________________________________________________________ figure 5. 3-wire serial interface timing diagram msb cs sclk din lsb t csw t cs t cp t css t cl t ch t ds t dh figure 6. MAX5865 mode recovery timing diagram cs sclk din id/qd dao da7 8-bit data adc digital output. sinad settles within 1db dac analog output. output settles to 10 lsb error t wake, sd, st_ (rx) or t enable, rx t wake, sd, st_ (tx) or t enable t x
clock jitter is especially critical for undersampling applications. consider the clock input as an analog input and route away from any analog input or other digital signal lines. the MAX5865 clock input operates with an ov dd /2 voltage threshold and accepts a 50% 15% duty cycle. reference configurations the MAX5865 features an internal precision 1.024v bandgap reference that is stable over the entire power supply and temperature range. the refin input pro- vides two modes of reference operation. the voltage at refin (v refin ) sets reference operation mode ( table 4 ). in internal reference mode, connect refin to v dd . v ref is an internally generated 0.512v. com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2 + v ref /2, and v refn = v dd /2 - v ref /2. bypass refp, refn, and com each with a 0.33f capacitor. bypass refin to gnd with a 0.1f capacitor. in buffered external reference mode, apply 1.024v 10% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd /2, v refp = v dd /2 + v refin /4, and v refn = v dd /2 - v refin /4. bypass refp, refn, and com each with a 0.33f capacitor. bypass refin to gnd with a 0.1f capaci- tor. in this mode, the dac s full-scale output voltage and common-mode voltage are proportional to the external reference. for example, if the v refin is increased by 10% (max), the dacs full-scale output voltage is also increased by 10% or to 440mv, and the common-mode voltage increases by 10%. applications information using balun transformer ac-coupling an rf transformer ( figure 7 ) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum adc performance. connecting the center tap of the transformer to com provides a v dd /2 dc level shift to the input. a 1:1 trans- former can be used, or a step-up transformer can be selected to reduce the drive requirements. in general, the MAX5865 provides better sfdr and thd with fully differential input signals than single-ended signals, especially for high-input frequencies. in differential mode, even-order harmonics are lower as both inputs (ia+, ia-, qa+, qa-) are balanced, and each of the adc inputs only requires half the signal swing com- pared to single-ended mode. figure 8 shows an rf transformer converting the MAX5865 dacs differential analog outputs to single ended. MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________ 19 table 4. reference modes v refin reference mode >0. 8 x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33f capacitor. 1.024v 10% buffered external reference mode. an external 1.024v 10% reference voltage is applied to refin. v ref is internally generated to be v refin /2. bypass refp, refn, and com each with a 0.33f capacitor. bypass refin to gnd with a 0.1f capacitor. figure 7. balun-transformer coupled single-ended to differential input drive for adcs com ia+ ia- 25 ? 0.1 f 0.33 f 25 ? 0.1 f v in MAX5865 22pf 22pf qa+ qa- 25 ? 0.1 f 0.33 f 25 ? 0.1 f v in 22pf 22pf
MAX5865 using op-amp coupling drive the MAX5865 adcs with op amps when a balun transformer is not available. figures 9 and 10 show the adcs being driven by op amps for ac-coupled single- ended, and dc-coupled differential applications. amplifiers such as the max4354/max4454 provide high speed, high bandwidth, low noise, and low distor- tion to maintain the input signal integrity. figure 10 can also be used to interface with the dac differential ana- log outputs to provide gain or buffering. the dac dif- ferential analog outputs cannot be used in single- ended mode because of the internally generated 1.4vdc common-mode level. also, the dac analog outputs are designed to drive a differential input stage with input impedance 70k ? . if single-ended outputs are desired, use an amplifier to provide differential to single-ended conversion and select an amplifier with proper input common-mode voltage range. fdd and tdd modes the MAX5865 can be used in diverse applications operating fdd or tdd modes. the MAX5865 operates in xcvr mode for fdd applications such as wcdma- 3gpp (fdd) and 4g technologies. also, the MAX5865 can switch between tx and rx modes for tdd applica- tions like td-scdma, wcdma-3gpp (tdd), ieee802.11a/b/g, and ieee802.16. in fdd mode, the adc and dac operate simultaneously. the adc bus and dac bus are dedicated and must be connected in 18-bit parallel (8-bit adc and 10-bit dac) to the digital baseband processor. select xcvr mode through the 3-wire serial interface and use the conversion clock to latch data. in fdd mode, the MAX5865 uses 75.6mw power at f clk = 40mhz. this is the total power of the adc and dac operating simultaneously. in tdd mode, the adc and dac operate independent- ly. the adc and dac bus are shared and can be con- nected together, forming a single 10-bit parallel bus to the digital baseband processor. using the 3-wire serial interface, select between rx mode to enable the adc and tx mode to enable the dac. when operating in rx mode, the dac does not transmit because the core is disabled and in tx mode, the adc bus is tri-state. this eliminates any unwanted spurious emissions and pre- vents bus contention. in tdd mode, the MAX5865 uses 63mw power in rx mode at f clk = 40mhz, and the dac uses 38.4mw in tx mode. figure 11 illustrates the MAX5865 working with the max2820 in tdd mode to provide a complete 802.11b radio front-end solution. because the MAX5865 dac has full differential analog outputs with a common-mode level of 1.4v, and the adc has wide-input common-mode ultra-low-power, high-dynamic- performance, 40msps analog front end 20 ______________________________________________________________________________________ figure 9. single-ended drive for adcs MAX5865 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf inb+ inb- com ina+ ina- 0.1 f r iso 50 ? r iso 50 ? refp refn v in 0.1 f 1k ? 1k ? 100 ? 100 ? c in 22pf c in 22pf 0.1 f r iso 50 ? r iso 50 ? refp refn v in figure 8. balun-transformer coupled differential to single- ended output drive for dacs MAX5865 id+ id- v out qd+ qd- v out
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________________________ 21 figure 10. adc dc-coupled differential drive MAX5865 ina+ com ina- r iso 22 ? r iso 22 ? r11 600 ? r9 600 ? r3 600 ? r2 600 ? r1 600 ? r10 600 ? r8 600 ? r5 600 ? r4 600 ? r7 600 ? r6 600 ? c in 5pf c in 5pf figure 11. typical application circuit for tdd adc adc dac dac adc output mux dac input mux clk 10 bit digital baseband processor serial bus max 5865 max2391 quadrature demodulator max2395 quadrature transmitter t/r
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 22 ___________________________________________________________________________________________________ 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (1/2 lsb ) at step 001 (1/4 lsb ) 111 digital input code analog output value figure 12a. integral nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-1/4 lsb) differential linearity error (+1/4 lsb) 1 lsb 1 lsb digital input code analog output value figure 12b. differential nonlinearity range, it can interface directly with rf transceivers while eliminating discrete components and amplifiers used for level-shifting circuits. also, the dac s full dynamic range is preserved because the internally generated common- mode level eliminates code-generated level shifting or attenuation due to resistor level shifting. the MAX5865 adc has 1v p-p full-scale range and accepts input com- mon-mode levels of v dd /2 ( 200mv). these features simplify the analog interface between rf quadrature demodulator and adc while eliminating discrete gain amplifiers and level-shifting components. grounding, bypassing, and board layout the MAX5865 requires high-speed board layout design techniques. refer to the MAX5865 ev kit data sheet for a board layout reference. locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface- mount devices for minimum inductance. bypass v dd to gnd with a 0.1f ceramic capacitor in parallel with a 2.2f capacitor. bypass ov dd to ognd with a 0.1f ceramic capacitor in parallel with a 2.2f capacitor. bypass refp, refn, and com each to gnd with a 0.33f ceramic capacitor. bypass refin to gnd with a 0.1f capacitor. multilayer boards with separated ground and power planes yield the highest level of signal integrity. use a split ground plane arranged to match the physical loca- tion of the analog ground (gnd) and the digital output driver ground (ognd) on the device package. connect the MAX5865 exposed backside paddle to the gnd plane. join the two ground planes at a single point such that the noisy digital ground currents do not inter- fere with the analog ground plane. the ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. make this connection with a low-value, surface-mount resistor (1 ? to 5 ? ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system s ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensi- tive analog traces. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. dynamic parameter definitions adc and dac static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the device are measured using the end-point method. (dac figure 12a). differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes (adc) and a monotonic transfer function (adc and dac) (dac figure 12b). adc offset error ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point.
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end dac offset error offset error ( figure 12a ) is the difference between the ideal and actual offset point. the offset point is the out- put value when the digital input is midscale. this error affects all codes by the same amount and usually can be compensated by trimming. adc gain error ideally, the adc full-scale transition occurs at 1.5 lsb below full scale. the gain error is the amount of devia- tion between the measured transition point and the ideal transition point with the offset error removed. adc dynamic parameter definitions aperture jitter figure 13 depicts the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken ( figure 13 ). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error) and results directly from the adc s resolution (n bits): snr(max) = 6.02db x n + 1.76db (in db) in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc s error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: enob = (sinad - 1. 76) / 6.02 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 v 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious component, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation products relative to the total input power when two tones, f 1 and f 2 , are present at the inputs. the intermodulation prod- ucts are (f 1 f 2 ), (2 ? f 1 ), (2 ? f 2 ), (2 ? f 1 f 2 ), (2 ? f 2 f 1 ). the individual input tone levels are at -7dbfs. 3rd-order intermodulation (im3) im3 is the power of the worst third-order intermodula- tion product relative to the input power of either input tone when two tones, f 1 and f 2 , are present at the inputs. the 3rd-order intermodulation products are (2 x f 1 f 2 ), (2 ? f 2 f 1 ). the individual input tone levels are at -7dbfs. thd (v +v +v +v +v ) v 2 2 3 2 4 2 5 2 6 2 1 = ? ? ? ? ? ? ? ? 20log hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 13. t/h aperture timing ______________________________________________________________________________________ 23
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end 24 ______________________________________________________________________________________ power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supply is changed 5%. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal s slew rate does not limit the adc s performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. note that the t/h performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as the full- power bandwidth frequency. dac dynamic parameter definitions total harmonic distortion thd is the ratio of the rms sum of the output harmonics up to the nyquist frequency divided by the fundamental: where v 1 is the fundamental amplitude and v 2 through v n are the amplitudes of the 2nd through nth harmonic up to the nyquist frequency. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component up to the nyquist frequency excluding dc. thd (v + v + ...+ v ) v 2 2 3 2 n 2 1 = ? ? ? ? ? ? ? ? 20log chip information transistor count: 16,765 process: cmos cs sclk v dd dd9 dd6 dd5 dd4 dd2 dd3 dd8 dd7 din ia+ ia- gnd clk gnd v dd qa- gnd qa+ v dd v dd refp 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 ognd ov dd da4 da6 dd1 dd0 da7 da3 da2 da1 da0 com refin id+ id- v dd gnd qd- qd+ v dd gnd n.c. refpn qfn MAX5865 da5 top view 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 pin configuration
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end ______________________________________________________________________________________ 25 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48l qfn thin, 7x7x0.8 mm 1 b rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX5865 ultra-low-power, high-dynamic- performance, 40msps analog front end maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2003 maxim integrated products printed usa is a registered trademark of maxim integrated products. proprietary information document control no. approval title: b rev. 2 2 exposed pad variations 21-0144 package outline 32, 44, 48l qfn thin, 7x7x0.8 mm common dimensions ** note: t4877-1 is a custom 48l pkg. with 4 leads depopulated. total number of leads are 44. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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