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preliminary product information t h is d o cume n t con t ains inf o rm a tion f o r a n e w p r oduct. ci r rus l ogic r e serv e s the r ight t o m o dify this p rod u ct witho u t no t i c e . 1 copyright ? cirrus logic, inc. 1997 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cdb5334/35/60 evaluation board for cs5334/CS5335/cs5360 features l demon s tr a tes rec o m m ende d lay o ut and grounding arrange m ents l cs8402a generates aes/ebu, s/pdif, & eiaj-340 compat i bl e digital audio l buffer e d seria l outpu t interface l dig i ta l and an a l og patch ar e as l on-boar d or e x te r na l ly sup p l ie d sy s tem ti m ing descripti o n th e cdb53 3 4/35 / 60 ev a lua t i on boa r d is a n e x ce l l e nt mean s f o r qu i ck l y eva l ua t i n g t he c s 5 334 , CS5335 , or cs53 6 0 s te r eo a/d c o nve r te r s . e v alu a t i on re q ui r es a d i g i t a l s i gna l pro c esso r , a l ow di s to r t i on an a log s i gn a l s o urc e a n d a powe r supp l y . an a lo g i npu t s ar e p r ov i ded v i a xlr c onnec t o r s f o r bo t h chann e ls . a l so i nc l ude d i s a cs8402 a dig i t a l aud i o i nte r f ace t ran s - m i t t e r whi c h gene r a t es aes / eb u , s / pdif , an d eiaj - 340 c o m p a t i b l e a ud i o d a ta . th e dig i t a l au d io da t a i s a v ai l ab l e v i a rc a ph o no, and op t i c al con n ec t o rs. th e eva l ua t i on boa r d ma y a l so b e con f i g ure d t o acc e pt e x te r na l t im i n g s i gna l s f o r op e ra t io n i n a us e r app l i c at i on d u r i ng sys t em de v e l opment. ordering info cdb533 4 /35 / 60 i oct 97 ds194db3
cdb5334/35/60 2 ds194db3 cdb5334/35 / 60 system o verview t h e cd b 53 3 4 / 35 / 6 0 e va l u a t i on b o a r ds a re a n e x - c e l l e n t m e a ns o f q ui c k l y ev a l ua t i n g the c s53 3 4, cs 5 335, or c s53 6 0. the cs 8 40 2 a di g ital a u dio i n t e rf a ce t ra n s m i t t e r p rov i d e s a n e a sy i n t e r fa c e to d i gi t al a u d i o sig n al p r o c essors, i n c l u di n g t he m a - j o ri t y of di g i t al a u d io t est e qu i p m e nt. t h e e v a l u a - t i on b o a r d h as b e e n d es i g n e d t o ac c e p t a n a n a l o g i n pu t , a n d pr o vi d e op t i c a l a n d co a x i al di g i t al o u t - p u ts . t h e e v a l u a t i o n b o a r d a l so a l l o ws t h e u se r t o a c c e ss c l o ck s a n d d ata th r ough a 1 0 -pin h e a d e r f o r syst e m d e v e l o p m e n t. in a dd i t i on, t he e v a lu a t ion bo a rd s u pp o rts t he i n put l e v e l m o ni t or i ng fun c t ion pr o vi d ed by the cs 5 33 4 , cs 5 33 5 , a n d c s53 6 0. t h e p e ak s i g n al l e v e l b i ts a r e d i sp l ay e d on b a r - gr a ph leds or 7 s e gm e n t d ispl a ys for b o th l e ft and ri g ht c h a nn e ls. t h e cd b 53 3 4 / 35 / 60 sc h e m a t i c h a s b e e n p a r t i - tion e d i n to 7 sch e mati c s s h own in figur e s 2 t h rou g h 8. e a c h p a r t i t io n ed sch e m a t ic i s r ep r es e n t - ed i n t he s y st e m di a gr a m shown in f i g u re 1 . n o t i ce t h at t he syst e m di a gr a m a l so i n c l ud e s the c o nn e c - t i ons b e tw ee n the p a rt i t i o n ed s c he m a t i c s. power supp l y circuitry an d grounding pow e r is s u ppli e d to the e v a l u ati o n b o a rd by six binding p o sts as sho w n in figu r e 2. + 5 va p rovid e s 5 vo l t p ow e r t o t h e c on v e r t e r a n d t he res e t c i r c u i t - ry. the 1 2 v binding p o sts p ro v ide p o wer to the a n a l og i np u t b u ff e r. c 1- c 3 a n d c5 - c7 p rov i de g e ne r al pow e r sup p ly f i l t e ri n g for t he an a l og su p - pli e s. z1-z3 a re tr a n si e n t supp r ession dio d es which a l so pro v i d e pro t e c t i o n f rom i n c or r e c t l y c o nn e c t ed power sup p ly leads . +5vd s u pplie s 5 v o lt p ower to t h e d i g i t a l se c t i on of t h e b o ar d . c 4 1 a nd c 1 0 pr o - v i de g e n er a l p ow e r su p ply fi l t e r i ng. z 4 is a t r a n - sient su p pressor. l o c a l i z e d d e c o up l i n g f o r t he cs 5 33 4 , cs5 3 35, o r cs 5 36 0 is p r ovid e d by c1 6 , c1 7 , c 32, a nd c 3 3 , a s shown in fig u re 4. r1 0 , c 1 6 , a nd c 3 2 form a l o w p a ss filter which isolates va+ fr o m n o ise on v d +. t h e e v a l u a t i o n b o ard uses s e p a r a te a n a l og a nd d i g - i t al gr o und pl a n e s wh i ch are j oi n ed to g e t h e r u n de r - n e ath r e sistors r 6 , r 4 1 , a nd r 52 - r5 5 . this a r ra n g e m e nt i so l a t es t h e a n a l og c ir c u i try f r om t he d i gi t a l l o gi c . reset circuit a nd offset calib r ation t w o metho d s o f pl a c ing the cs 5 33 4 , c s53 3 5, o r cs 5 360 i n to po w er - down mode a re pr o vid e d on t h e e v a l u a t i on bo a rd. t h e cal sw i t c h, s h own in fi g ure 8 , p u ll s the dif0 and dif1 li n es high on the cs 5 33 4 , cs 5 33 5 , or cs 5 36 0 , t h us pl ac ing the ad c i n to p o we r -down mo d e. r el e asin g the cal switch causes the dif0 a n d dif1 s ettings to be re- st o r e d , up o n which a n initializ a tion se q u e n c e b e - gins, a s d e s c rib e d in the c s53 3 4/cs5 3 3 5 and cs 5 360 data sheets. t h e r e set c i r c uit pro v i d ed o n the e v a l u a t i on b o ard is shown i n f ig u re 2. u pon p o wer u p , t h is c i rc u it se n ds a r e set t o t he r st p i n of t he c s5 3 34, cs 5 33 5 , or cs 5 36 0 . power- d own, foll o wed by offs e t c a libr a tion, c an a lso be p e rform e d by pr e ss- i n g a nd t h e n r e l e a si n g the rst sw i t c h. i t sho u l d be no t ed t h at o n l y t h e r st m e th o d of p ow e ri n g down t h e cs5 3 34, c s53 3 5, o r cs 5 360 w i ll i n c l ude t he d e cisi o n o f master or slave op e r a tion. input buff e r and protection c ircuits t h e d if f er e n t i a l i np u t c i r cu i t s h own i n f i gu r e 3 i s well - suit e d f o r the c s5 3 34, c s5 3 35, a n d c s 5360 in p rof e ssi o nal a p pl i c a t io n s. t he c i r c u it w i ll a c c e pt a d if f er e n t i a l o r si n gl e - e nd e d s i gn a l o f e i t h e r po l a r - i t y and p r ov i de a d i ff e r e n t i a l sig n al w i th t h e pr o p e r dc o ffset to the cs 5 33 4 , c s5 3 35, o r cs5 3 60. the c i r c uit a lso i n c orp o r a t e s 6 db o f a t t en u a t i o n to sc a le d o wn p r of e ssio n al i n put l e v e ls t o t he i n put volt a ge r a n g e of the c s53 3 4, cs 5 33 5 , or c s5 3 60. a no m i nal in p ut l e v el o f 4 vol t s r m s t o the e v a l u a - t i o n bo a r d wi l l a c hi e ve a fu l l sc a le d i g i t a l o u t put from t h e cs 5 33 4 , cs 5 33 5 , or cs 5 36 0 . t h e c o m - mon mode r e j e c t ion of the syst e m i s l im i t e d by the p a ss i ve c o m po n e n t m a t c h i n g of t he i n put b u ff e r
cdb5334/35/60 ds19 4 d b3 3 c i r c ui t . t he a n a l og i np u t c on n e c t o r is a s t a n da r d f e - male xlr with pin 2 p o siti v e, pin 3 r e turn, a n d pin 1 shi e l d. r1, r 5 , a n d c8 f orm an rc netwo r k which pr o - v i des a nt i - a l i as f i l t e r ing a nd t he o p t i m um sou r ce imp e d a n c e for the c s53 3 4, cs 5 33 5 , or cs 5 360 r i g h t c h a n n e l i n p u t s. r 2 , r 3 , a n d c 4 2 d u p l i ca t e t h is fu n c t ion f o r t h e l e ft c h a nn e l . sp a ce h a s b e e n l e ft on t he e v a l u a t i o n bo a rd f o r i n - put pr o t e c t i o n d i od e s d1 - d4 on the r i ght c h a n n e l, a n d d8 - d11 o n t he l e ft c h an n e l , shown in fi g ure 3. t h ese d i od e s a r e o pt i o n al as t he cs 5 33 4 , c s53 3 5, a n d c s53 6 0 a re a ble t o wi t hst a nd i n put c ur r en t s o f 100 m a m a x i mum, a s s t a t ed in the cs 5 334/cs 5 335 a nd c s5 3 60 d ata sh e ets. t h e o u t- put c u r re n t from t h e op - a m p us e d in t he a n a log f i l - t e r on t he e v a l u a t i o n bo a rd i s n ot a b l e to d e l i v er a c u rr e n t th a t e x c e e d s 10 0 m a. inp u t p ro t e c t i on d i - odes ar e r e comm e nded if ther e is a po s sibi l i t y t h a t ov e r-r a n g e s i gn a ls c ou l d be a p p l i e d at t h e adc i n - p u ts w h ic h e x c e e d t h is l e v el . see t h e a p p l i c at i o n no t e, "a / d c on v e r t e r i np u t pro t e c t ion t e c h ni q u e s" in t h e 1 994 cr y st a l s e m i c o n du c t o r a u dio d a - t a bo o k. cs5334, cs 5 335, and cs53 6 0 a/d converters t h e c s 533 4 , c s53 3 5, a nd c s53 6 0 a/d c on v e r t e rs are sh o wn in figu r e 4. a d es c ription of th e se d evi c - e s are i n c l u ded i n t he c s 533 4 / c s53 3 5 a nd cs 5 360 d a ta s h e e ts. cs8402a di g ital audio inter f ace fi g ure 5 s h ow s t h e cir c uitry f o r t h e cs 8 40 2 a d i g - i t al a ud i o i n t e r fa c e tr a ns m i t t er. t he c s84 0 2a c an implemen t aes/ebu , s/pd i f , an d eiaj-340 in- t e rf a ce st a nd a r d s. t he di g i t al in t er f a c e f o r m at (dif) for t h e tr a ns m i t t er i s s e t a u t o m a t i c a l ly to m a t ch t he f o r m at c h o se n f o r t he c s53 3 4, c s53 3 5, or c s5 3 60 ( the dif is s e l e c t e d b y th e dif 1 and dif0 switc h e s o n sw 1 , as d efine d in table 3). sw2 p rovides 8 dip s w itches to s elect va r i o us mod e s a n d b its f o r the cs8 4 02a; s w itch d e fini- t i ons a nd t h e d e f a ult s e t t i ngs for s w 2 a re l i st e d in t a b l es 4 and 5 . di g i t al o u t p uts a r e pro v i d ed on an r c a c o nn e c t or v ia is o l a t i on t r a nsfo r m e r a nd o n an op t i c a l t ra n s m i t t e r. for m o r e d e t a i l e d i nf o r m a t ion o n the c s84 0 2a a n d t h e di g ital a udio st a nd a rds, see the cs8 4 01a/cs 8 40 2 a d ata sheet. serial out p ut interface a s e ri a l outp u t inter f a c e is p rovid e d on h dr2, a s shown in figure 6. w h en the s m ode1 and smode2 jumpers, defined in table 2, are set to t h e master posi t ion , mc l k, sclk , lrck, sdata , and frame signals a r e outputs. when the s mode1 and smode 2 jumper s are in the slave po s ition , mclk , s d ata, and frame a r e o u t pu t s, wh i le s c lk a n d l r c k b e c o m e i n - puts . hence , in slav e mode , the sclk and l r ck si g n a ls m u st be e xt e r n a l ly d e r i ved f r om mclk to run the a dc. all sig n al s a re buf f er e d in or d er to i so l a t e t h e c o nv e r t er fr o m e x t er n al c i r c u i t - ry. sign a l b u ffe r ing is pr o vided by a 7 4 hct243 tr a n s c eiv e r (u1 0 ) and a 74h c t541 b u ff e r (u1 1 ). altera p l d and peak s ignal level l e ds t h e al t era e pm 7 128 pro g r a m m a b l e l o g ic d e v i ce (pld), s h own in fi g ure 8, is de s ig n ed to sup p ort t h ree m a j o r fe a t u r e s on t he e v a l u a t i on b o a rd. f i rst, it a ut o m a t i c a l ly c onf i g u res t he c s84 0 2a t ra n s m i t - t e r to a c ce pt t he d i g i t a l in t e r fa c e f o r m at c h o sen f o r t h e cs5 3 34, c s5 3 35, o r c s53 6 0. s e co n d , the pld pr o vi d es a 12 8 x fs m a st e r clo c k f o r t h e c s84 0 2a. t h ir d , i t d e c od e s a n d up d a t es t he pe a k si g n a l l e v el (ps l ) b i t s wh i c h g ive i nf o r m a t i o n ab o ut t h e a m p l i - t u d e of t he i n p u t si g n a l. cs8402a f o rmat configurati o n t h e cs 5 33 4 , cs 5 33 5 , a nd cs 5 360 su p port th r ee di g ital inte r fa c e form a ts for both mast e r a n d sl a v e c o nfigu r atio n s. form a t 0 h a s v alid d a ta o n the ris- i n g e dge of s c l k. t h e c s84 0 2a t ra n s m i t t e r h a s no c o r r es p on d ing mode which matc h es f o rmat 0,
cdb5334/35/60 4 ds194db3 but i n ve r t i ng t he s c l k so t h at da t a i s v a l i d on t he fa l l ing e d ge of s c lk wi l l m a ke t h e f o r m at 0 i n t e r - fa c e l in e s m a t c h t he f o r m at 1 i n t e rf a ce l in e s o n t he cs 8 402 a . the pld co n f i g ur e s the c s8 4 02a to form a t 1 a n d p e rforms s c lk inv e rsi o n a u tom a ti- cally when t h e dif 1 , dif0 switche s o n sw1 are set to 0 0. di g i t al i n t e rf a ce f o r m at 1 o n t h e cs5 3 34, c s53 3 5, a n d cs5 3 60 h a s v a l i d d a ta o n t h e f a l l i n g e d ge o f sc l k. t h is i n t e rf a ce fo r m a t m a t c h e s for m a t 1 on t h e cs8 4 02a, so n o m o d if i c a t i o n i s p e rf o r m ed on t h e d i g i t a l i n t er f a c e l i n es. t h e p l d c on f ig u res t he cs 8 402a to fo r mat 1 and p asses the i n terface lin e s from the cs5 3 34, c s 533 5 , o r cs 5 360 t h rou g h t o t h e c s84 0 2a u nc h a n g e d wh e n t he dif1, dif0 switche s are set to 0 1. di g i t al in t e rfa c e for m a t 2 is t he i2s c o m p a t i b le mod e . it m a t c h e s fo r m a t 4 on th e tr a n smitter. the pld c onfig u res the c s8 4 02a to form a t 4 and p a ss e s t h e i nt e rf ac e l i n e s from t he c s53 3 4, cs 5 335, or cs 5 360 thro u gh to the c s8 4 02a u n - changed when the dif1 , dif0 switches are set to 10. cs8402a mc l k generation w h en the cd b 533 4 / 3 5/ 6 0 is set u p for slave m od e , t he c rys t al o s c i l l a t or (u5) c an b e 25 6 x, 38 4 x, or 5 12x fs. t h e cs8 4 02 a re q u i r es a m a st e r clo c k f r e q u e n c y o f 1 28x fs to op e r a t e . th e pld c a n be c o nf i gur e d t o d i vi d e m c l k _5 3 35 ( t he o s- c i l l a t or o ut p u t ) b y 2, 3 , o r 4 t o g e n e r a te mc l k _ 840 2 , t h us a c c o m m o da t i ng the va r i o us poss i b l e f re q u e n c i e s o f the o sc i l l a t or. t he sw i t c h e s on s w 1 l a bel e d mclk _ s1 a n d m c lk _ s0 s e l e ct t h e d e gr e e of c l o ck d i v i si o n as d e fi n ed i n t a b l e 3. decoding psl bits / driving leds t h e pld d e c o des a n d d i sp l a y s t h e pe a k s i g n al l e v e l bi t s f o r b o th hi g h r es o lu t i o n a nd b a rg r aph mod e s (f o r d e tail e d inf o rmati o n o n the psl bits, see the cs 5 33 4 / c s53 3 5 and cs5 3 60 d a tash e e ts). when the tmode 1 a n d tmo d e2 j u mpers , de- fi n ed i n t a b l e 2, are set t o ba r gra p h, t h e p l d d e c o des t h e psl bits a n d drives b a rgr a ph led s f o r t h e l eft a n d r i ght ch a n n e l s. w h e n t he tm o de1 and t m ode2 jumpers a r e se t to hi re s ( high reso- l u t i o n m o d e ), t h e pl d dr i v e s t h e 7 s e g m e nt d i s- p l ays f o r l e ft a n d ri g ht c h a nn e l s. t h e p ld al s o pr o vides a peak up d ate ( pu) si g nal, which adjusts the rate at which the psl bits are up- d a t e d. fo u r settin g s pr o vi d e u pd a te r a tes r a n g ing from 4 2 ms to 2.7 s ( f or a 4 8 khz sam p le rate ) . the switc h es on sw1 labeled p u _s1 and pu _ s0 select t h e pu fr e qu e n c y as sho w n in ta b le 3 . groundi n g and power supply decoupl i ng t h e c s53 3 4, c s5 3 35, a n d cs 5 360 r e q u ire c a r e ful a t t e n t i o n to p ow e r sup p ly a nd g r ou n di n g a r ra n g e - ments to o p timize p e r formance. figure 4 shows the r e comm e nd e d pow e r a rr a n g em e n ts. the c s5 3 34, cs 5 33 5 , o r cs 5 360 is p o sitio n ed o v er the a n a log gr o und p l a n e , n e a r the digital/an a lo g gr o und p l a n e spl i t , t o m i n i mi z e the dis t anc e t h a t the c l o c ks tr a v- e l . t he se r i e s r e sis t ors a re p res e nt on t h e c l o c k and d a ta l i n e s t o r e d u ce the e ffe c t s o f t r ans i e n t c urr e n t s when driving a capacitive load i n master mode, a n d t o re d u c e c l o c k o ve r sho o t w hen a pp l y i n g e x - t e rn a l c l o cks t o the adc in s l ave m od e . t h is l a y out t e c h n i que is us e d t o m i n i m i z e d i g i t al nois e a n d to insure p r op e r p o wer sup p ly matc h - i n g/s e q u en c i ng. t he d e c ou p l i n g c a p a c i t o rs a r e l o - c a t ed as c lose t o the ad c as pos s ibl e . ext e nsive use o f gr o und pl a ne f i ll on b o th t he a n a l og a nd d i g - i t al s e c t i o ns o f t h e e v a l u a t i o n b o ard y i e l d l a rge r e - du c tio n s in r a di a t e d n o ise e ff e cts.
cdb5334/35/60 ds19 4 d b3 5 t ab l e 1. sys t em conn e c t io n s t ab l e 2. j umpe r se l ec t ab l e op t io n s c o nnec t or input/output signal prese n t +5 v a i np u t +5 v o l t s f o r an a lo g se c t i on +5vd i np u t +5 v o l t s f o r d i g i t a l s ec t ion 1 2v i np u t 12 v o l t s f o r an a lo g i nput a gnd i np u t an a log g r ound conne c t i on f r o m p o w e r sou r ce dgnd i np u t d i g i t a l g roun d c o nnec t i o n f ro m powe r so u rce a i n l i np u t l e f t chann e l d i ff ere n t i a l /s i ng l e ended ana l og i n put ainr i np u t r ig h t chann e l d i ff er e nt i a l /s i ng l e ended ana l og i nput lrck , sclk i npu t/ outp u t i / o fo r s er i a l a n d l e f t / r i gh t c lo c ks mclk o utp u t mas t e r c l oc k ou t put sd a t a o utp u t s e r i al da t a o u tput f r ame o utp u t f ram i n g si g na l ou t pu t f o r ps l bi t s coax i a l o u tput o utp u t cs842 0 a d i g i t a l o u tpu t vi a t ran s fo r mer o pt i ca l outp u t o utp u t cs842 0 a d i g i t a l o u tpu t vi a op t i ca l t ra n smi t ter jumper purpose p osit i on f u nct i on selected smode1, s m ode2 se l ec t s ma s te r / s la v e o p era t i on f o r cs533 4 , CS5335 , an d cs536 0 an d i /o s t at u s o f h d r2 . smode1 a n d smode2 s h oul d a l ways be se t t o the same pos i t ion. *master sl a ve t i min g ge n era t i on o n boa r d. ex t e r nal c l oc k g e nera t i on, de r i ved f r om mclk. tm o de1 , tmod e 2 se l ec t s t h e f u nct i on a l i t y o f t h e psl b i t s . tmode1 a n d tmode2 s hou l d a lwa y s b e s e t t o t h e s a m e po s i t i on. hi res *bargraph psl b i t s di s p l a y t he i nput l evel psl b i t s di s p l a y t he ba r graph hpsel ena b le s o r di s ab l es the i npu t h i gh p a s s f i l t e r o n t he cs5 3 34 , CS5335 , a nd cs53 6 0 defe a t *enable de f ea t s h i gh p as s f i l t er enab l e s h i gh p as s f i l t er
cdb5334/35/60 6 ds194db3 t ab l e 3 . sw i tc h def i n i t i ons * de f au l t s e t t i n g from fa c t ory t a bl e 4. cs 8 402a sw i t c h de f in i t i on s - c o nsume r m o de swi t ch # 0 = c l osed , 1 = open comment 8, 7 m c l k_s1, mclk_s 0 d i v i des m clk _ 5335 to gene r a t e mclk_84 0 2 f or t h e cs8 4 02 a t rn s m i t ter *0 0 0 1 1 0 1 1 gene r a t es a 12 8 x f s c l oc k whe n u s in g a 256 x f s osc i l la t or rese r ved gene r a t es a 12 8 x f s c l oc k whe n u s in g a 384 x f s osc i l la t or gene r a t es a 12 8 x f s c l oc k whe n u s in g a 512 x f s osc i l la t or 6, 5 *0 0 rese r ved 4, 3 d i f1, dif0 se l ec t s t he d i gi t a l i nt e r f ace fo r mat f o r th e cs5334 / 35 / 60 , an d cs840 2 a *0 0 0 1 1 0 1 1 con f i gure s t he cs5334 / 35/ 6 0 f or fo r m a t 0, and t h e cs84 0 2 a f or fo r m a t 1 con f i gure s t he cs5334 / 35/ 6 0 f or fo r m a t 1, and t h e cs84 0 2 a f or fo r m a t 1 con f i gure s t he cs53 3 4/35 / 6 0 fo r fo r ma t 2 ( i 2 s) , an d th e cs8402 a fo r fo r ma t 4 (i 2 s) p l ace s t he cs5 3 34/ 3 5/6 0 i n p owe r dow n m o de 2, 1 pu_s1, pu_s0 ad j us t s t he f r eque n cy of th e pea k upda t e s i gna l f or psl bi t s *0 0 0 1 1 0 1 1 upda t es t h e psl b i t s a t a f r eque n cy of lrck/2 11 upda t es t h e psl b i t s a t a f r eque n cy of lrck/2 13 upda t es t h e psl b i t s a t a f r eque n cy of lrck/2 15 upda t es t h e psl b i t s a t a f r eque n cy of lrck/2 17 swi t ch # 0 = c l osed , 1 = open comment 6 p r o = 0 con s u m e r m o d e ( c 0 = 0) 8, 5 fc1, fc0 c24 , c2 5 , c26, c27 - sampl e f r equen c y 0 0 *0 1 1 0 1 1 00 0 0 - 4 4 . 1 khz 01 0 0 - 4 8 khz 1 1 00 - 3 2 khz 00 0 0 - 4 4 . 1 khz , c d m o de 7 c 3 c3 , c4 , c 5 - emphas i s ( 1 o f 8 b i t s) *1 0 00 0 - none 10 0 - 50 / 1 5 s 4 c 2 c2 - copy / copy r i g ht *1 0 0 - copy i n hi b i t ed /cop y r i gh t as s ered 1 - copy perm i t t ed / copy r i g ht not ass e r t ed 3 c 1 5 c15 - gene r ate s s t a t us *1 0 0 - de f in i t ion i s based on ca t egor y c ode 1 - see cs8402a da t a shee t , app. a 1, 2 c8 , c9 c8 - c14 - categ o ry code (2 o f 7 b i t s) 1 1 1 0 0 1 *0 0 00 0 0000 - g e ner a l 01 0 0000 - pcm enco d er / deco d er 10 0 0000 - co m p a ct di s k - c d 1 1 00000 - di g i t a l aud i o t ape - d a t
cdb5334/35/60 ds19 4 d b3 7 t a bl e 5. cs 8 402a sw i t c h de f i n i t io n s - p r o f e s s i ona l m o de swi t ch # 0 = c l osed , 1 = open comment 6 p r o = 1 po f ess i ona l m o d e ( c0 = 1) 8 cre lo c al samp l e ad d res s cou n te r a n d re l i ab i l i t y f l ags 0 1 d i sab l ed i n t e r n a lly g e n e r a t e d 7, 4 c6 , c7 c6 , c7 - samp l e f r eque n cy 0 0 0 1 1 0 1 1 00 - no t i nd i ca t e d - d e fau l t t o 4 8 khz 01 - 48 khz 10 - 44 . 1 khz 1 1 - 3 2 khz 5 c 1 c1 - aud i o 1 0 0 - norma l audio 1 - non - audio 3 c 9 c8 , c9 , c 1 0 , c 1 1 - channe l mod e ( 1 o f 4 b i t s ) 1 0 00 0 0 - no t i nd i ca t e d - def a ul t t o 2- c hannel 01 0 0 - s t ereo p hon i c 1 , 2 em1 , em0 c2 , c3 , c 4 - emphas i s ( 2 o f 3 b i t s) 1 1 1 0 0 1 0 0 00 0 - no t i nd i ca t e d - defa u l t t o none 10 0 - n o emphas i s 1 1 0 - 5 0 /1 5 s 1 1 1 - cc i ttj . 17
cdb5334/35/60 8 ds194db3 f i gu r e 1 . sys t em b l ock d i ag r am and s ig n al f low fi g ur e 2. pow e r su p pl y and re s e t ci r cu i t r y
cdb5334/35/60 ds19 4 d b3 9 note: bat8 5 d i odes a r e no t in s ta l l e d o n t he eva l uta t i on b o ard ( s ee tex t ) fi g u r e 3. ana l o g inpu t bu f fer
cdb5334/35/60 10 ds194db3 fig u re 4 . cs53 3 4, cs5 3 35, a nd cs53 6 0 conn e c t io n s
cdb5 334 /35/60 ds19 4 d b 3 11 f i gu r e 5 . cs840 2 a dig i t a l aud i o t r an s mi t t e r a n d conn e ct i ons
cdb5334/35/60 12 ds194db3 fi g ur e 6. i /o i n te r f a ce f o r c l o c ks a n d da t a fi g ure 7. de c oup l in g cap s fo r pld
cdb5334/35/60 ds19 4 d b3 13 fi gur e 8. al t e r a pld and di s p l ay l e ds
cdb5334/35/60 14 ds194db3 fi g ure 9 . cdb53 3 4/ 3 5 / 6 0 compon e nt s i d e ( t op)
cdb5334/35/60 ds19 4 d b3 15 fi g ur e 10. cdb5 3 34 / 35 / 60 comp o nen t s i de ( bo t tom)
cdb5334/35/60 16 ds194db3 f i gur e 11 . cd b 5 334 / 35 / 6 0 so l der s i d e ( bot t om)
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