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high-frequency programmable pecl clock generation module cy2xp304 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07589 rev. *d revised october 27, 2005 features ? 40 ps typical peak-peak period jitter at 125 mhz ? 30 ps typical output-output skew at 400 mhz ? four low-skew lvpecl outputs ? phase-locked loop (pll) multiplier select ? serially-configurable multiply ratios ? eight-bit feedback counter and six-bit reference counter for high accuracy ? hstl inputs?hstl-to-l vpecl level translation ? 125- to 500-mhz output range for high-speed applications ? high-speed pll bypass mode to 1.5 ghz ? 36-vfbga, 6 8 1 mm ? 3.3v operation block diagram pin configuration ina inab clk0 clk0b clk1 clk1b clk2 clk2b clk3 clk3b clk_sel xtal oscillator pll xm xin xout ser clk ser data 0 1 pll_mult 6 5 top view 4 3 2 1 abc d e f gh cy2x p 304 36 v fbg a p in co nfig uratio n to p v iew clk0 v dda gnd xout xin v ddb clk0b gnd ser_d ata ser_cl k gnd v ddb clk1 gnd gnd gnd clk1b pll_mu lt clk2 clk_se l clk2b gnd gnd in a clk3 gnd v ddb v ddb gnd in a b clk3b vdda v dda nc vdda v dda
cy2xp304 document #: 38-07589 rev. *d page 2 of 11 cy2xp304 two-wire serial interface introduction the cy2xp304 has a two-wire serial interface designed for data transfer operations, and is used for programming the p and q values for frequency generation. s clk is the serial clock line controlled by the master device. s data is a serial bidirec- tional data line. the cy2xp304 is a slave device and can either read or write information on the dataline upon request from the master device. figure 1 shows the basic bus connections between master and slave device. the buses are shared by a number of devices and are pulled high by a pull-up resistor. serial interface specifications figure 2 shows the basic transmission specification. to begin and end a transmission, the master device generates a start signal (s) and a stop signal (p). start (s) is defined as switching the s data from high to low while the s clk is at high. similarly, stop (p) is defined as switching the s data from low to high while holding the s clk high. between these two signals, data on s data is synchronous with the clock on the s clk . data is allowed to change only at low period of clock, and must be stable at the high period of clock. to acknowledge, drive the s data low before the s clk rising edge and hold it low until the s clk falling edge. serial interface format each slave carries an address. the data transfer is initiated by a start signal (s). each transfer segment is one byte in length. the slave address and the read/write bit are first sent from the master device after the start signal. the addressed slave device must acknowledge (ack) the master device. depending on the read/write bit, the master device will either write data into (logic 0) or read data (logic 1) from the slave device. each time a byte of data is successfully transferred, the receiving device must acknowledge. at the end of the transfer, the master device will generate a stop signal (p). serial interface transfer format figure 2 shows the serial interface transfer format used with the cy2xp304. two dummy bytes must be transferred before the first data byte. the cy2xp304 has only three bytes of latches to store information, and the third byte of data is reserved. extra data will be ignored. pin definitions pin # pin name pin description a1,b1,g3,g4 vddb 3.3v power supply for crystal driver a2 xin reference crystal input a3 xout reference crystal feedback a4,b2,c1,c3,c4,f3,f4,g2,g5,b5 gnd ground a5,h1,h2,h4,h5 vdda 3.3v power supply a6 clk0 lvpecl clock output b6 clk0b lvpecl clock output (complement) c6 clk1 lvpecl clock output d6 clk1b lvpecl clock output (complement) e6 clk2 lvpecl clock output f6 clk2b lvpecl clock output (complement) g6 clk3 lvpecl clock output h6 clk3b lvpecl clock output (complement) b3 ser_clk serial interface clock b4 ser_data serial interface data d1 pll_mult pll multiplier select input , internal pull-up resistor, see frequency table e1 clk_sel clock select input, internal pull down . high select ina/inab, internal pll is bypassed. low select internal pll f1,g1 ina,inab differential clock input pair , used in pll-bypassed mode h3 nc no connect frequency table pll_mult m (pll multiplier) example inpu t crystal frequency c lk[0:3],clkb[0:3] 0 x16 25 mhz 400 mhz 31.25 mhz 500 mhz 1 x8 15.625 mhz 125 mhz
cy2xp304 document #: 38-07589 rev. *d page 3 of 11 to program the cy2xp304 using the two-wire serial interface, set the selpq bit high. the default setting of this bit is low. the p and q values are determined by the following formulas: p final = (p 7..0 + 3) * 2 q final = q 5..0 + 2 if the qcntbyp bit is set high, then q final defaults to a value of 1. the default setting of this bit is low. if the selpq bit is set low, the pll multipliers will be set using the values in the select function table. cyberclocks? has been developed to generate p and q values for stable pll operation. this software is downloadable from www.cypress.com. figure 1. device connections figure 2. serial interface specifications figure 3. cy2xp304 transfer format serial interface address for the cy2xp304 a6 a5 a4 a3 a2 a1 a0 r/w 11001010 serial interface programming for the cy2xp304 b7 b6 b5 b4 b3 b2 b1 b0 data0 qcntbyp selpq q<5> q<4> q<3> q<2> q<1> q<0> data1p<7>p<6>p<5>p<4>p<3>p<2>p<1>p<0> data2 reserved reserved reserved reserved reserved reserved reserved reserved s clk s data s clk _c s clk _in s data _c s data _in master device r p s clk _in s data _c s data _in slave device v dd r p start (s) stop (p) s clk s data valid data acknowledge ack 1 bit 8 bits data 1 p slave address ack s dummy byte 0 r/w dummy byte 1 ack 1 bit 1 bit ack 1 bit 7 bits 8 bits 1 bit data 0 ack 1 bit 8 bits 1 bit 8 bits
cy2xp304 document #: 38-07589 rev. *d page 4 of 11 pll frequency = reference x p/q = output functional specifications crystal input the cy2xp304 receives its reference from an external crystal. pin xin is the reference crystal input, and pin xout is the reference crystal feedback. the parameters for the crystal are given on page 5 of this data sheet. the oscillator circuit requires external capacitors. please refer to the application note entitled crystal oscillator topics for details. select input there are two select input pins, the pll_mult and clk_sel. pll_mult pin selects the frequency multiplier in the pll, and is a standard lvcmos input. the s pin has an internal pull-up resistor. the multiplier selection is given on page 2 of this data sheet (see frequency table). state transition characteristics specifies the maximum settling time of the clk and clkb outputs from device power-up. for v dd and v ddx any sequences are allowed to power-up and power-down the cy2xp304. reference pll q p vco output figure 4. pll block diagram state transition characteristics from to transition latency description v dd /v ddx on clk/clk b normal 3 ms time from v dd /v ddx is applied and settled to clk/clkb outputs settled.
cy2xp304 document #: 38-07589 rev. *d page 5 of 11 crystal requirements requirements to use parallel mode fundamental xtal. external capacitors are required in the crystal oscillator circuit. please refer to the application note entitled crystal oscillator topics for details. note: 1. where v cc is 3.3v5%. absolute maximum conditions parameter description condition min. max. unit v cc supply voltage non-functional ?0.3 4.6 v v cc operating voltage f unctional 3.135 3.465 v vtt output termination voltage relative to v cc [1] v cc ? 2 v v in input voltage relative to v cc [1] ?0.3 v cc + 0.3 v v out output voltage relative to v cc [1] ?0.3 v cc + 0.3 v lu i latch up immunity functional 100 ma t s temperature, storage non-functional ?65 +150 c t a temperature, operating ambient functional ?40 +85 c t j temperature, junction non-functional ? 150 c ? jc dissipation, junction to case functional 11.38 c/w ? ja dissipation, junction to ambient functional 85.83 c/w esd h esd protection (human body model) 2000 v m sl moisture sensitivity level 3 n.a. g ates total functional gate count assembled die 50 ea. crystal requirements parameter description min. max. unit x f frequency 10 31.25 mhz dc electrical specifications parameter description min. max. unit v dd supply voltage 3.135 3.465 v v il input signal low voltage at pin pll_mult ? 0.35 v v ih input signal high voltage at pin pll_mult 0.65 ? v r pup internal pull-up resistance 10 100 k ? t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 500 ms operating conditions parameter description min. max. unit t a commercial temperature 0 70 c industrial temperature ?40 85 c
cy2xp304 document #: 38-07589 rev. *d page 6 of 11 dc specifications (v cc = 3.3 v 5%, commercial and industrial temp.) parameter description condition min. max. unit clock input pair ina, inab (hstl differential signals) v dif hstl differential input voltage [2] 0.4 1.9 v v x hstl differential crosspoint voltage [3] 0.68 0.9 v i in input current v in = v x 0.2v |150| a pecl outputs clk[0:3], clk[0:3]b (pecl differential signals) v ol output low voltage v cc = 3.3v 5% i ol = ?5 ma [4] v cc ? 1.995 v cc ? 1.5 v v oh output high voltage i oh = ?30 ma [4] v cc ? 1.25 v cc ? 0.7 v supply current and v bb i ee maximum quiescent supply current without output termination current 150 ma c in input pin capacitance ina, inab 3 pf l in pin inductance 1nh ac electrical specifications einput parameter description min. max. unit f in input frequency with driven reference, crystal inputs 1 133 mhz f xtal,in input frequency with crystal input 10 31.25 mhz f ina_in input frequency with ina/inab inputs 0 1500 mhz c in,cmos input capacitance at pll_mult pin [5] ?10pf ac specifications epecl clock outputs clk[0:3], clk[0:3]b parameter description conditions min. typ. max. unit f o output frequency clk_sel = 0 125 ? 500 mhz clk_sel = 1 0 ? 1500 mhz vo (p-p) differential output voltage (peak-to-peak) f o < 1ghz 0.375 ? ? v v cmro output common voltage range v cc ? 1.425 v tsk (o) output-to-output skew 400-mhz 50% duty cycle standard load differential operation ?3050ps tsk (pp) part-to-part output skew 400-mhz 50% duty cycle standard load differential operation ??150ps t r ,t f output rise / fall time 400-mhz 50% duty cycle differential 20% to 80% ??0.3ns dc long-term average output duty cycle 45?55% t dc,err cycle-cycle duty cycle error at x8 with 15.625-mhz input ??70ps phase noise phase noise at 10 khz (x8 mode) @ 125 mhz ?107 ? ?92 dbc bw loop pll loop bandwidth 50 khz (?3db) notes: 2. v dif (dc) is the amplitude of the differential hstl input voltage swing required for device functionality. 3. v x (dc) is the crosspoint of the differential hstl input signal. fu nctional operations is obtained when the crosspoint is within the v x (dc) range and the input swing lies within the v dif (dc) specification. 4. equivalent to a termination of 50 ? to v tt . 5. capacitance measured at freq. = 1 mhz, dc bias = 0.9v, and vac < 100 mv.
cy2xp304 document #: 38-07589 rev. *d page 7 of 11 t jcrms cycle-to-cycle rms jitter at 125-mhz frequency ? 12.1 15 ps at 400-mhz frequency ? 8.2 10 ps at 500-mhz frequency ? 9.7 12 ps t jcpk cycle-to-cycle jitter (pk-pk) at 125-mhz frequency ? 72 95 ps at 200-mhz frequency, xf = 25 mhz ? 50 65 ps at 400-mhz frequency ? 40 55 ps at 500-mhz frequency ? 50 65 ps t jprms period jitter rms at 125-mhz frequency ? 5.7 6.8 ps at 400-mhz frequency ? 4.5 5.6 ps at 500-mhz frequency ? 5.6 6.8 ps t jppk period jitter (pk-pk) at 125-mhz frequency ? 4.0 55 ps at 200-mhz frequency, xf = 25 mhz ? 38 50 ps at 400-mhz frequency ? 34 45 ps at 500-mhz frequency ? 39 50 ps t jlt long term rms jitter (p < 20) at 125-mhz frequency ? ? 25 ps at 400-mhz frequency ? ? 20 ps at 500-mhz frequency ? ? 25 ps t jlt long term rms jitter (20 < p < 40) at 125-mhz frequency ? ? 55 ps at 400-mhz frequency ? ? 65 ps at 500-mhz frequency ? ? 55 ps t jlt long-term rms jitter (40 < p < 60) at 125-mhz frequency ? ? 70 ps at 400-mhz frequency ? ? 90 ps at 500-mhz frequency ? ? 65 ps ac electrical specifications epecl clock outputs: pll bypass mode parameter description conditions min max unit vo (p-p) differential output voltage ( peak-to-peak) differential prbs fo < 1.0 ghz 0.375 ? v j p period jitter 660 mhz 50% duty cycle standard load ? 1.3 ps r.m.s. t pd propagation delay (ina/inab to output) pecl, 660mhz 280 650 ps hstl, <1 ghz 280 750 ps ac specifications epecl clock outputs clk[0:3], clk[0:3]b (continued) parameter description conditions min. typ. max. unit tr, tf, 20-80% vo figure 5. ecl/lvpecl output
cy2xp304 document #: 38-07589 rev. *d page 8 of 11 jitter this section defines the specific ations that relate to timing uncertainty (or jitter) of the input and output waveforms. figure 6 shows the definition of period jitter with respect to the falling edge of the clk signal. period jitter is the difference between the minimum and ma ximum cycle times over many cycles (typically 12800 cycles at 400 mhz). equal require- ments apply for rising edges of the clk signal. t jp is defined as the output period jitter. figure 7 shows the definition of cy cle-to-cycle jitter with respect to the falling edge of the clk signal. cycle-to-cycle jitter is the difference betwe en cycle times of adjacent cycles over many cycles (typically 12800 cycles at 400 mhz). equal requirements apply for rising edges of the clk signal. t jc is defined as the clock output cycle-to-cycle jitter. figure 8 shows the definition of cycle-to-cycle duty cycle error. cycle-to-cycle duty cycle error is defined as the difference between high-times of adjac ent cycles over many cycles (typically 12800 cycles at 400 mhz). equal requirements apply to the low-times. t dc , err is defined as the clock output cycle-to-cycle duty cycle error. figure 9 shows the definition of long-term jitter error. long-term jitter is defined as the accumulated timing error over many cycles (typically 12800 cycles at 400 mhz). it applies to both rising and falling edges. t jlt is defined as the long-term jitter. t cycle t jp = t cycle,max ? t cycle, min. over many cycles clk clkb figure 6. period jitter t cycle,i t jc = t cylce,i ? t cycle,i+1 over many consecutive cycles clk clkb t cycle, i+1 figure 7. cycle -to-cycle jitter tpw+,i t dc,err = t pw+,i ? t pw+,i+1 over many consecutive cycles clk clkb tpw+,i+1 tcycle,i+1 tcycle, i+1 cycle i cycle i+1 figure 8. cycle-to-cyc le duty cycle error t jlt = t max ? t min over many cycles clk clkb t min t max figure 9. long-term jitter
cy2xp304 document #: 38-07589 rev. *d page 9 of 11 test configurations standard test load using a di fferential pulse generator and differential measurement instrument. applications information termination examples osc pll pulse generator z = 50 ohm zo = 50 ohm vtt vtt 5" vtt 5" zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm clk_sel xtal dut figure 10. cy2xp304 ac test reference clock xtal 1.3 v zo = 50 ohm 1.3 v r t = 50 ohm r t = 50 ohm vcc = 3.3v vee = 0v figure 11. standard lvpec l?pecl output termination 3.3 v zo = 50 ohm 3.3 v 120 ohm 120 ohm vcc =3.3 v vee = 0v lvds 51 ohm (2 places) 33 ohm (2 places) lvpecl to lvds clock xtal figure 12. low-voltage positive emitter-coupled logic (lvpecl) to a low-voltage differential signaling (lvds) interface
cy2xp304 document #: 38-07589 rev. *d page 10 of 11 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package drawing and dimensions cyberclocks is a trademark of cypress semiconductor. all produc t and company names mentioned in this document may be the trademarks of their respective holders. ordering information ordering code package type operating range operating voltage cy2xp304bvc 36-lead vfbga commercial, to 400 mhz 3.3v cy2xp304bvct 36-lead vfbga ? tape and reel commercial, to 400 mhz 3.3v cy2xp304bvi 36-lead vfbga industrial, to 400 mhz 3.3v CY2XP304BVIT 36-lead vfbga ? tape and reel industrial, to 400 mhz 3.3v lead-free cy2xp304bvxc 36-lead vfbga co mmercial, to 400 mhz 3.3v cy2xp304bvxct 36-lead vfbga ? tape an d reel commercial, to 400 mhz 3.3v cy2xp304bvxi 36-lead vfbga in dustrial, to 400 mhz 3.3v cy2xp304bvxit 36-lead vfbg a ? tape and reel industr ial, to 400 mhz 3.3v a 1 a1 corner 0.75 0.75 ?0.300.05(36x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.10 c a1 corner top view bottom view 2 3 4 3.75 5.25 b c d e f g h 65 46 5 23 1 d h f g e c b a 6.000.10 8.000.10 a 8.000.10 6.000.10 b 1.875 2.625 0.26 max. 36-lead vfbga (6 x 8 x 1 mm) bv36a 51-85149-*c
cy2xp304 document #: 38-07589 rev. *d page 11 of 11 document history page document title: cy2xp304 high-frequency programmable pecl clock generation module document number: 38-07589 rev. ecn no. issue date orig. of change description of change ** 129898 12/02/03 rgl new data sheet *a 235868 see ecn rgl updated jitter spec based on the characterization report *b 247601 see ecn rgl/ggk changed v oh and v ol to match the char data *c 300320 see ecn rgl minor change: re-phrased the first bullet in the features *d 413407 see ecn rgl added lead-free devices added typical values

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