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hi-6010 arinc 429 transmitter/receiver for 8 bit bus the hi-6010 is a cmos integrated circuit designed to interface the avionics data bus standard arinc 429 to an 8 bit port. it contains one receiver and one transmitter. they operate independently except for the self test option and the parity option. the receiver demands that the incoming data meet the standard protocol and the trans- mitter outputs a standard protocol stream. the hi-6010 provides flexible options for interfacing to the user system. the controlling processor can operate both the receiver and transmitter either by using hard wired flags and gates at the pins or by using software reads and writes of the status register and control register or a combination thereof. the chip is programmable to operate with single 8 bit bytes requiring "on the fly transmitter loading and receiver downloading" or to operate in 32 bit "extended buffer" mode. in addition there is an option to use automatic label recognition after loading 8 possible labels for comparison. parity and self test are also software programmable. master reset is activated only by taking the mr pin high. two clock inputs allow independent selection of the data rates of the transmitter and receiver. each must be 4x the desired arinc 429 frequency. error flags are generated for transmitter underwrites and for receiver data framing miscues, parity errors, and buffer overwrites. the hi-6010 i s a 5 volt chip that will require data transla- tion from and to the arinc bus. the hi-8482 and hi-8588 line receivers are available for the receiver side and the hi-318x and hi-858x line drivers are available for the transmitter side. vdd=5.0volts5% vss = 0.0 volts operating supply voltage general description arinc 429 protocol controller with interface to an 8 bit bus automatic label recognition option 8 bit or 32 bit buffering option self test and parity options cmos / ttl logic pins plastic and ceramic package options - surface mount or dip military processing available avionics data communication serial to parallel conversion parallel to serial conversion applications features pin configuration (top view) 28 27 c/ 26 25 24 d7 23 d6 22 d5 21 d4 20 d3 19 d2 18 d1 17 d0 16 rxd1 15 v re cs we d dd v1 wef 2 3 txc 4 hfs 5 mr 6 txe 7 rxrdy 8 txrdy 9 txd0 10 txd1 11 rxc 12 fcr 13 rxd0 14 ss cts pin numbers apply for plastic and ceramic dip and for plastic plcc. consult factory for pin out of 48 lead ceramic leadless chip carrier. holt integrated circuits (ds6010 rev.d) 01/06 www.holtic.com january 2006
pin symbol function description 1 v power 0.0 volts 2 wef output error indication if high. status register must be read to determine specific error. 3 input enables data transmission when low. 4 txc input source clock for data transmission. 4 times bit rate. 5 hfs input hardware feature select. 6 mr input master reset, active high. 7 txe output low when transmission in progress. 8 rxrdy output high when data of received word is available. 9 txrdy output high when data of a transmitted word may be input. 10 txd0 output "zeroes" data output of transmitter. 11 txd1 output "ones" data output of transmitter. 12 rxc input source clock for data reception. 4 times bit rate. 13 fcr output first character received flag. 14 rxd0 input "zeroes" data input to receiver. 15 v power 5 volts 5% 16 rxd1 input "ones" data input to receiver. 17 d0 i / o data bus 18 d1 i / o data bus 19 d2 i / o data bus 20 d3 i / o data bus 21 d4 i / o data bus 22 d5 i / o data bus 23 d6 i / o data bus 24 d7 i / o data bus 25 input 8 bit data bus input control active low. 26 input chip select, active low. 27 c/ input high for control or status register operations, low for data 28 input 8 bit data bus output control, active low. ss dd cts we cs d re pin descriptions hi-6010 using the receiver the receiver logic is independent of the transmitter except in the following ways: 1. self test 2. parity option in self test, the transmitter outputs route to the receiver inputs internally ignoring the external inputs. also in self test, the external receiver clock is replaced with the transmitter clock. the parity option affects both the receiver and transmitter. either both are operational or neither. wef is an error indicator. it goes high for a transmitter "underwrite" (failure to keep up with byte loading) and pin 2 hardware control of the receiver pin 2 - wef goes high for any one of three receiver errors. the status register will show which of the three errors occurred: sr3 received a parity error sr4 data overwritten sr5 receiving sequence error the possible receiver sequence errors are: 1. rxd0 and rxd1 simultaneously a one. 2. less than 32 bits before 3 nulls. 3. more than 32 bits. there are no errors flagged for labels received that don't match stored labels when in the label recognition mode. errors are cleared by mr or by reading the status register. this pin, along with the control register, sets up the functioning (e.g. modes) of the chip. if hfs is low, the status register bit error pin 5 - hfs and the control register holt integrated circuits 2
communicating with the control and status registers label recognition option loading labels reading labels pin 27, c/ , must be high to read the status register or write the control register. reading the status register resets errors. there is no provision to read the control register. pin 5 must be high if label recognition is selected in either the 8 or 32 bit modes and all eight label buffers must be written using redundant labels, if necessary. the chip compares the incoming label to the stored labels. if a match is found, the data is processed. if a match is not found, no indicators of receiving arinc data are presented. after the write that changes cr7 from 0 to 1, the next 8 writes of data (c/ is a zero for data) will load the label registers. labels must be loaded whenever pin 5 goes from low to high. after the write that changes cr1 from 0 to 1, the next 8 data reads are labels. d d pin 6 - mr in 8 - rxrdy pin 12 - rxc pin 13 - fcr when mr is a 1, the control word is set to 0x10 0101 (cr7 - cr0). for the receiver this sets up 8 bit mode with the receiver and parity enabled. mr also initializes the registers and logic. the first arinc reception will only occur a word gap. in 8 bit mode, this pin goes high whenever 8 bits are received without error. in 32 bit mode, this pin goes high after all 32 bits are received with no error. this flag may be inhibited for one arinc word if cr3 is programmed to 1. this flag is also inhibited in label recognition if the incoming arinc label does not match one of the stored 8 labels. this pin must have a clock applied that is 4x the desired receive frequency. in 8 bit mode, this pin flags the first character (byte) received. in 32 bit mode, this pin goes high for a valid 32 bit word. the pin is not affected by cr3 programming. after p using the receiver (cont.) receiver is not programmable to the 32 bit "extended buffer" mode nor to the label recognition mode. affecting the receiver: pin 14 - rxd0 and pin 16 - rxd1 these pins must be 5 volt logic levels. there must be a translator between the arinc bus and these inputs. typically a receiver chip, such as the hi-8482 or hi-8588 is inserted between the arinc bus and the logic chips. rxd0 is looking for a high level for zero inputs and rxd1 is looking for a high level for one inputs. when both inputs are low this is referred to as the null state. by writing to the control register and reading the status register the controlling processor can operate the receiver without hardware interrupts. the control register in combination with the wiring of pin 5 was explained above. the status register bits pertaining to the receiver are explained below: software control of the receiver * cr3 will be automatically reset to 0 after being programmed to a 1 at the completion of an arinc word reception. this allows a software label recognition different from the automatic option available. control program pin 5 bit name value value operation cr1 x 0 no action 0 1 no action 1 1 next 8 data read cycles will read stored labels. one time only sequence on each transiton of cr1 to a 1. cr2 0 x receiver is disabled 1 x receiver is enabled cr3* 0 x rxrdy goes high normally 1 x blocks rxrdy for one arinc word cr4 0 x self test disabled 1 x self test enabled cr5 0 0 no parity errors enabled and 32nd bit is data 1 0 parity error flag enabled 0 1 32 bit "extended mode" enabled and parity enabled. 1 1 8 bit "one byte at a time" mode and parity enabled. cr7 x 0 label recognition not programmable 0 1 label recognition disabled 1 1 label recognition enabled sr1 0 no receiver data 1 receiver data ready sr3 0 no parity error 1 parity error - parity was even sr4 0 receiver data not overwritten 1 receiver data was overwritten sr5 0 receiver data received without framing error 1 framing error - did not receive exactly 32 good bits sr6 0 did not receive first byte 1 received first byte - same flag as pin 13 status bit value meaning hi-6010 holt integrated circuits 3
using the transmitter the transmitter logic is independent of the receiver except in the following ways: 1. self test 2. parity option in self test the transmitter outputs route to the receiver inputs internally and the txd0 and txd1 outputs are inhibited. when parity is enabled, both the receiver and transmitter are affected. odd parity is automatically generated in the 32nd bit if this option is selected. this output goes high for 1 transmitter error and 3 receiver errors. to determine which error is being flagged, read the status register. reading the status register also clears the error flag. the transmitter will not function until the error is cleared. it can also be cleared by mr going high. the only possible transmitter error is generated when running in 8 bit mode. for the transmitter this means loading the last 3 bytes while the transmission is in progress. failure to load a byte before the previous byte's 8th bit is transmitted will generate the error, indicated by status bit sr7 set to a 1. this pin is a hardware gate for transmissions. if the transmitter buffer is loaded and control register bit cr0 is a one, the only inhibit of the transmitter would be for to be a one. when taken low, transmission of an arinc word is enabled. it may be pulsed to release each transmitted word. the data rate of transmission is controlled by this pin. this clock must be 4x the desired date rate. this pin along with the control register sets the functioning of the chip. for the transmitter: hardware control of the transmitter pin 2 - wef pin 3 - pin 4 - txc pin 5 - hfs and the control register cts cts pin 7 - txe pin 9 - txrdy pin 10 - txd0 and pin 11 - txd1 whenever a transmission begins, this pin goes low and returns high after the transmission is complete. whenever txrdy is a one, data may be written into the transmitter buffer. in 8 bit "one byte at a time" mode, this pin may be monitored to indicate when to write the next 8 bits. txd0 will go high during a transmission if the data is zero. txd1 goes high if data is a one. when both pins are low this is referred to as the null state. typically an arinc transmitter chip, such as the hi-3182, hi-3183, hi-8585 or hi-8586 is connected to these pins to translate the 5 volt levels to the proper arinc bus levels. data is not output when the hi-6010 is in self-test mode. by writing into the control register and reading the status register, the controlling processor can operate the transmitter independent of the flags at the pins. transmission can be initiated by changing cr0 from a 0 to a 1 after the transmitter buffer has been loaded. then the status register may be monitored as follows: software control of the transmitter cabling noise the hi-6010 has ttl compatible inputs and therefore they are susceptible to noise near ground. if the data bus is passed by ribbon cable or the equivalent to the device under test, it is possible to get significant glitches on the master reset line. the problem will appear to be a pattern sensitive failure. one cure is simply to adequately bypass master reset. another is to buffer the hi-6010 inputs near the chip. after master reset the hi-6010 receiver must see a word gap before the first arinc data bit. error flags must be cleared by either a status register read or by a master reset. the operation of either the transmitter or the receiver is inhibited upon error. receiver seems dead applications tips control program pin 5 bit name value value operation cr0 0 x transmitter is disabled 1 x transmitter is enabled cr4 0 x not in self test 1 x self test enabled cr5 0 0 8 bit mode + data in 32nd bit 1 0 8 bit mode + parity enabled 0 1 32 bit mode with parity enabled 1 1 8 bit mode with parity enabled sr0 0 do not load the transmitter buffer 1 ready to load the transmitter buffer sr2 0 transmission in progress 1 transmitter is idle sr7 0 no transmission error 1 8 bit mode only error for underwriting data status bit value meaning pin 6 - mr the chip is initialized whenever this pin goes high. the control register is set to 0x10 0101 (cr7 - cr0). for the transmitter this sets up 8 bit mode with the transmitter enabled. hi-6010 holt integrated circuits 4
28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 0* 0 0 0 0 1 0 0 0 1 x 1 x load control word d0 = 1 1 0 0 p t 0 0 0 0 x 0 x load data to transmit - byte 1 p 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x 0 x status bits 0 ,2&7( p 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 x 1 x status bit 0 goes high 1 0 0 p t 0 0 0 0 x 0 x load the next byte to transmit p 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x 0 x monitor status bit 0 p 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 x 1 x detect a transition 1 0 0 p t 0 0 0 0 x 0 x load 3rd byte p 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 x 0 x monitor status bit 0 p 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 x 1 x detect a transition 1 0 0 p t 0 0 0 0 x 0 x load 4th byte d8 td7 td6 td5 td4 td3 td2 td1 txrdy, txe & error) d16 td15 td14 td13 td12 td11 td10 td9 d24 td23 td22 td21 td20 td19 td18 td17 d32 td31 td30 td29 td28 td27 td26 td25 8 bit "one byte at a time" transmit monitoring status register bit 0 pins * with pin 5 low, control register bit 5 selects if the 32nd bit is either odd parity or data. p = pulse x = don't care * with pin 5 low, control register bit 5 selects if the 32nd bit is either odd parity or data. p= pulse x = don't care pins 8 bit "one byte at a time" transmit using txrdy, pin 9, to trigger next byte load 28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 0* 0 0 0 0 1 0 0 x 1 x 1 x load control word 1 0 0 p t 0 0 0 0 x 0 x txrdy & txe go low after load data 1 0 0 1 x x x x x x x x 0 0 0 0 x 1 x monitor pin 9 to go high 1 0 0 p t 0 0 0 0 x 0 x after pin 9 high then load next byte 1 0 0 1 x x x x x x x x 0 0 0 0 x 1 x monitor pin 9 to go high 1 0 0 p t 0 0 0 0 x 0 x load 1 0 0 1 x x x x x x x x 0 0 0 0 x 1 x monitor pin 9 to go high 1 0 0 p t 0 0 0 0 x 0 x load 1 0 1 1 x x x x x x x x 0 0 0 1 x 1 x transmission complete d8 td7 td6 td5 td4 td3 td2 td1 d16 td15 td14 td13 td12 td11 td10 td9 d24 td23 td22 td21 td20 td19 td18 td17 d32 td31 td30 td29 td28 td27 td26 td25 * with pin 5 low, control register bit 5 selects if the 32nd bit is either odd parity or data. p = pulse x = don't care * with pin 5 low, control register bit 5 selects if the 32nd bit is either odd parity or data. p= pulse x = don't care hi-6010 re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr holt integrated circuits 5
receiving 8 bit mode software interrupt receiving 32 bit words hardware interrupt pins 28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 0 0 0 1 0 0 0 1 x x 0 x 0 write cr: 1 1 0 1 x x x x x x x x 0 1 x x 1 x 1 await pin 8 or pin 13 to go high p 0 0 1 0 1 x x 1 x 1 read 1st byte p 0 0 1 0 1 x x 1 x 0 read 2nd byte p 0 0 1 0 1 x x 1 x 0 read 3rd byte p 0 0 1 0 1 x x 1 x 0 read 4th byte 1001xxxxxxxx01xx0x0 32 bit recieve & no label recogn. rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd16 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd24 rd23 rd22 rd21 rd20 rd19 rd18 rd17 par rd31 rd30 rd29 rd28 rd27 rd26 rd25 pins 28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 1 0 0 1 0 0 0 1 x x 0 x 0 write cr: p 1 0 1 0 0 0 0 0 x 0 0 0 1 x x 0 x 0 monitor the status register p 1 0 1 0 1 0 0 0 x 1 0 0 1 x x 1 x 1 sr1&sr6 go high - first character p 0 0 1 0 1 x x 0 x 0 read 1st byte p 1 0 1 0 0 0 0 0 x 0 0 0 1 x x 0 x 0 look for sr 1 to go high again p10100000x1001xx1x0 p 0 0 1 0 1 x x 0 x 0 read 2nd byte p 1 0 1 0 0 0 0 0 x 0 0 0 1 x x 0 x 0 look for sr 1 to go high again p10100000x1001xx1x0 p 0 0 1 0 1 x x 0 x 0 read 3rd byte p 1 0 1 0 0 0 0 0 x 0 0 0 1 x x 0 x 0 look for sr 1 to go high again p10100000x1001xx1x0 p 0 0 1 0 1 x x 0 x 0 read 4th byte 8 bit receive & not label recong. rd8 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd16 rd15 rd14 rd13 rd12 rd11 rd10 rd9 rd24 rd23 rd22 rd21 rd20 rd19 rd18 rd17 par rd31 rd30 rd29 rd28 rd27 rd26 rd25 p = pulse x = don't care p= pulse x = don't care p = pulse x = don't care p= pulse x = don't care hi-6010 re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr holt integrated circuits 6
transmit in 32 bit mode (extended buffer) using to initiate cts pins 28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 0 0 0 0 0 1 0 1 1 1 x 1 x load control word d 5=0&d0=1 1 0 0 p 0 1 1 1 x 1 x load data to transmit - byte 1 1 0 0 p 0 1 1 1 x 1 x load data to transmit - byte 2 1 0 0 p 0 1 1 1 x 1 x load data to transmit - byte 3 1 0 0 p x t 0 1 1 1 x 0 x load data to transmit - byte 4 1 1 1 1 x x x x x x x x 0 1 0 1 x 0 x take low to start transmitting 32nd bit will be parity td8 td7 td6 td5 td4 td3 td2 td1 td16 td15 td14 td13 td12 td11 td10 td9 td24 td23 td22 td21 td20 td19 td18 td17 d31 td30 td29 td28 td27 td26 td25 cts transmit in 32 bit mode (extended buffer) using software write to control register pins 28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 0 0 0 0 0 0 0 1 0 1 x 1 x load control word d 5=0&d0=0 1 0 0 p 0 1 0 1 x 0 x load data to transmit - byte 1 1 0 0 p 0 1 0 1 x 0 x load data to transmit - byte 2 1 0 0 p 0 1 0 1 x 0 x load data to transmit - byte 3 1 0 0 p x t 0 1 0 1 x 0 x load data to transmit - byte 4 1 1 0 p 0 0 0 0 0 0 0 1 0 1 0 0 x 0 x write control word d0 = 1 32nd bit will be parity td8 td7 td6 td5 td4 td3 td2 td1 td16 td15 td14 td13 td12 td11 td10 td9 td24 td23 td22 td21 td20 td19 td18 td17 d31 td30 td29 td28 td27 td26 td25 p = pulse x = don't care p= pulse x = don't care p = pulse x = don't care p= pulse x = don't care hi-6010 re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr holt integrated circuits 7
28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 0 0 0 0 0 1 0 0 0 1 x x x x x control bit 7 must be 0 first 1 1 0 p 1 0 0 0 0 1 0 0 0 1 x x x x x write 1 into control bit 7 1 0 0 p 1l7 1l6 1l5 1l4 1l3 1l2 1l1 1l0 0 1 x x x x x load the 1st label 1 0 0 p 2l7 2l6 2l5 2l4 2l3 2l2 2l1 2l0 0 1 x x x x x load the 2nd label 1 0 0 p 3l7 3l6 3l5 3l4 3l3 3l2 3l1 3l0 0 1 x x x x x load the 3rd label 1 0 0 p 4l7 4l6 4l5 4l4 4l3 4l2 4l1 4l0 0 1 x x x x x load the 4th label 1 0 0 p 5l7 5l6 5l5 5l4 5l3 5l2 5l1 5l0 0 1 x x x x x load the 5th label 1 0 0 p 6l7 6l6 6l5 6l4 6l3 6l2 6l1 6l0 0 1 x x x x x load the 6th label 1 0 0 p 7l7 7l6 7l5 7l4 7l3 7l2 7l1 7l0 0 1 x x x x x load the 7th label 1 0 0 p 8l7 8l6 8l5 8l4 8l3 8l2 8l1 8l0 0 1 x x x x x load the 8th label loading labels pins 28 27 26 25 24 23 22 21 20 19 18 17 6 5 3 7 8 9 13 comments 1 1 0 p 1 0 0 0 0 1 0 0 0 1 x x x x x make sure bit 1 of control word is 0 1 1 0 p 1 0 0 0 0 1 1 0 0 1 x x x x x write 1 into control bit 1 p 0 0 1 1l7 1l6 1l5 1l4 1l3 1l2 1l1 1l0 0 1 x x x x x read the 1st label p 0 0 1 2l7 2l6 2l5 2l4 2l3 2l2 2l1 2l0 0 1 x x x x x read the 2nd label p 0 0 1 3l7 3l6 3l5 3l4 3l3 3l2 3l1 3l0 0 1 x x x x x read the 3rd label p 0 0 1 4l7 4l6 4l5 4l4 4l3 4l2 4l1 4l0 0 1 x x x x x read the 4th label p 0 0 1 5l7 5l6 5l5 5l4 5l3 5l2 5l1 5l0 0 1 x x x x x read the 5th label p 0 0 1 6l7 6l6 6l5 6l4 6l3 6l2 6l1 6l0 0 1 x x x x x read the 6th label p 0 0 1 7l7 7l6 7l5 7l4 7l3 7l2 7l1 7l0 0 1 x x x x x read the 7th label p 0 0 1 8l7 8l6 8l5 8l4 8l3 8l2 8l1 8l0 0 1 x x x x x read the 8th label reading labels pins p = pulse x = don't care p= pulse x = don't care p = pulse x = don't care p= pulse x = don't care hi-6010 re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr re c/d cs we d7 d6 d5 d4 d3 d2 d1 d0 hfs cts txe rxrdy txrdy fcr mr holt integrated circuits 8
timing diagrams c/d data bus cs data bus timing - read t cds valid t cdh t cshr valid t dr t rd t cssr rd c/d data bus cs data bus timing - write t cds valid t cdh t cshw valid t dwh t dws t cssw we t wp transmtter operation receiver operation txe cts txd0/ txd1 txrdy t ctl t cpw t endat t dtx t txry first bit last bit t dr last bit rxd0/ rxd1 rxrdy/ fcr figure 3. figure 4. figure 1. figure 2. hi-6010 holt integrated circuits 9
parameter symbol min typ max units t t t t t t t t t t t t t t t t t t t setup c/ to 50 ns hold c/ to 0ns delay to data 200 ns delay data bus hi-z from 150 ns setup to 0ns hold to 0ns set c/ to 0ns hold c/ to 0ns setup data bus to 200 ns hold data bus to 100 ns setup to 0ns hold to 0ns pulse width 200 ns delay txe from 1.5 2.0 clks delay txrdn from 1 clk delay txrdy from last txdn 16 clks delay txe from last txdn 4 data bits pulse width 1 clk delay last rxdn to rxrdy clks mr pulse width 1 clk data bus timing - read (see figure 1.) data bus timing - write (see figure 2.) transmitter timing (see figure 3.) receiver timing (see figure 4.) drd drd rd rd cs rd rd cs dwe dwe we we cs we cs we we cts cts cts cds cdh rd dr cssr cshr cds cdh dws dwh cssw cshw wp ctl endat txrdy tdtx cpw dr 3 t mr absolute maximum ratings supply voltage: v -0.5v to +7.0v input voltage range v -0.5v to v +0.5v input current i +10ma output current +25ma dd in dd in out i power dissipation p 500mw operating temperature range: t (industrial) -40c to +85c t (hi temp & military) -55c to +125c storage temperature range: t -65c to +150c lead temperature t 300c for 60 seconds d a a stg lead note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics v = 5.0v, v = 0v, t = operating temperature range (unless otherwise specified). dd ss a parameter symbol condition min typ max units operating voltage v 4.75 5 5.25 v min. input voltage (hi) v 2.1 1.4 v max. input voltage (lo) v 1.4 0.7 v min. input current (hi) i v = 4.9v 1.5 a max. input current (lo) i v = 0.1v -1.5 a min. output voltage (hi) v i = -1.5ma 2.7 v max. output voltage (lo) v i = 1.8ma 0.7 v operating current drain i f = 400khz 0.8 2.8 ma input capacitance c not tested 20 pf dd ih il ih ih il il oh out ol out dd in (voltages referenced to v = 0v) ss ac electrical characteristics v = 5.0v, v = 0v, t =operating temperature range (unless otherwise specified). dd ss a hi-6010 holt integrated circuits 10
ordering information package description package description temperature range temperature range 28 pin ceramic side brazed dip 28 pin plastic j-lead plcc flow flow burn in burn in -40c to +85c -40c to +85c no no i i -55c to +125c -55c to +125c -55c to +125c no no yes t t m hi - 6010c x-xx hi - 6010j x x part number part number part number t f t m-01 blank blank blank part number part number c j lead finish lead finish tin / lead (sn / pb) solder tin / lead (sn / pb) solder 100% matte tin (pb-free, rohs compliant) gold gold hi-6010 holt integrated circuits 11
28-pin ceramic side-brazed dip package type: .050 typ. (1.270 typ.) .018 .002 (.457 .051) 1.400 .014 (35.560 .356) .600 .010 (15.240 .254) .085 .009 (2.159 .229) .200 max. (5.080 max.) .125 min. (3.175 min.) .100 .005 (2.540 .127 .595 .010 (15.113 .254) .610 .010 (15.494 .254) 010 .002 .001 (.254 .051 .025) 28c 28-pin plastic plcc package type: .045 x 45 .453 .003 (11.506 .076) sq. .490 .005 (12.446 .127) sq. .045 x 45 see detail a .173 .008 (4.394 .203) pin no. 1 ident pin no. 1 .015 .002 (.381 .051) detail a .020 min (.508 min ) .025 .045 .410 .020 (10.414 .508) .031 .005 (.787 .127) .017 .004 (.432 .102) .050 .005 (1.27 .127) 28j r hi-6010 package dimensions inches (millimeters) holt integrated circuits 12

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