ICS670-03 mds 670-03 g 1 revision 010306 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com l ow p hase n oise , z ero d elay b uffer and m ultiplier description the ICS670-03 is a high speed, low phase noise, zero delay buffer (zdb) which in tegrates ics? proprietary analog/digital phase locked loop (pll) techniques. it is identical to the ics670-01, but with an increased maximum output frequency of 210 mhz. part of ics? clockblocks tm family, the part?s zero delay feature means that the rising edge of the input clock aligns with the rising edges of the out puts giving the appearance of no delay through the device . there are two identical outputs on the chip. the fbclk should be used to connect to the fbin. each output has its own output enable pin. the ICS670-03 is ideal for synchronizing outputs in a large variety of systems, fr om personal computers to data communications to video. by allowing off-chip feedback paths, the ICS670-03 can eliminate the delay through other devices. the 15 different on-chip multipliers work in a variet y of applications. for other multipliers, including functi onal multipliers, see the ics527. features ? packaged in 16-pin soic ? available in pb (lead) free package ? clock inputs from 5 to 210 mhz (see page 2) ? patented pll with low phase noise ? output clocks up to 210 mhz at 3.3v ? 15 selectable on- chip multipliers ? power down mode available ? low phase noise: -124 dbc/hz at 10 khz ? output enable function tri-states outputs ? low jitter 15 ps one sigma ? advanced, low power, sub-micron cmos process ? industrial temperature rated ? operating voltage of 3.3 v or 5 v block diagram divide by n voltage controlled oscillator fbclk oe1 phase detector, charge pump, and loop filter fbin s3:s0 iclk clk2 4 oe2 vdd 3 gnd 3 external feedback from fbclk is recommended.
l ow p hase n oise , z ero d elay b uffer and m ultiplier mds 670-03 g 2 revision 010306 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ICS670-03 pin assignment multiplier select table pin descriptions 12 1 11 2 10 3 9 vdd 4 vdd 5 vdd 6 gnd 7 clk2 8 oe2 gnd s0 s1 fbclk s3 oe1 iclk 16 15 14 13 fbin gnd s2 s3 s2 s1 s0 clk2 (and fbclk) input range (mhz) 0 0 0 0 low (power down entire chip) - 0 0 0 1 input x1.333 18 - 157.5 0 0 1 0 input x6 5 - 35 0 0 1 1 input x1.5 16.67 - 140 0 1 0 0 input x3.333 7.5 - 63 0 1 0 1 input x2.50 10 - 84 0 1 1 0 input x4 6 - 52.5 0 1 1 1 input x1 25 - 210 1 0 0 0 input x2.333 11 - 90 1 0 0 1 input x2.666 10 - 78.75 1 0 1 0 input x12 5 - 17.5 1 0 1 1 input x3 8 - 70 1 1 0 0 input x10 5 - 21 1 1 0 1 input x5 6 - 42 1 1 1 0 input x8 5 - 26.25 1 1 1 1 input x2 12 - 105 pin number pin name pin type pin description 1 - 3 vdd input power supply. connect both pins to the same voltage (either 3.3 v or 5 v). 4 clk2 output clock output from vco. output fr equency equals the input frequency times multiplier. 5 oe2 input output clock enable 2. tri- states the clock 2 output when low. 6 fbclk output clock output from vco. output fr equency equals the input frequency times multiplier. 7 oe1 input output clock enable 1. tri-st ates the feedback clock output when low. 8 fbin input feedback clock input. 9 iclk input clock input. connect to a 5 - 210 mhz clock. 10 s3 input multiplier select pin 3. determines outputs per table above. internal pull-up. 11 s2 input multiplier select pin 2. determines outputs per table above. internal pull-up. 12 s1 input multiplier select pin 1. determines outputs per table above. internal pull-up. 13 s0 input multiplier select pin 0. determines outputs per table above. internal pull-up. 14 - 16 gnd power connect to ground.
l ow p hase n oise , z ero d elay b uffer and m ultiplier mds 670-03 g 3 revision 010306 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ICS670-03 external components the ICS670-03 requires a minimum number of external components for proper operation. decoupling capacitors of 0.01mf should be conn ected between vdd (pins 1, 2, and 3) and gnd (pins 14, 15, and 16), as close to the device as possible. a series termination resistor of 33 ? may be used to each clock output pin to reduce reflections. absolute maximum ratings stresses above the ratings listed below can cause per manent damage to the ICS670-03. these ratings, which are standard values for ics commercially rated part s, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electr ical parameters are guaranteed on ly over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3v 10%, ambient temperature -40 to +85 c, unless stated otherwise item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured in respect to gnd) +3.0 +5.5 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.0 5.5 v input high voltage v ih 2v input low voltage v il 0.8 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v output high voltage, cmos level v oh i oh = -4 ma vdd-0.4 v operating supply current idd no load 35 ma
l ow p hase n oise , z ero d elay b uffer and m ultiplier mds 670-03 g 4 revision 010306 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ICS670-03 ac electrical characteristics vdd = 3.3v 10%, ambient temperature -40 to +85 c, unless stated otherwise note 1: rising edge of iclk compared with rising ed ge of clk2, with fbclk connected to fbin, and 15 pf load on clk2. see graph on page 5 for skew vs. frequency and loading. thermal characteristics short circuit current i os each output 50 ma internal pull-up resistor r pu oe, select pins 200 k ? input capacitance c in oe, select pins 5 pf parameter symbol conditions min. typ. max. units parameter symbol conditions min. typ. max. units input clock frequency f in see table on page 2 5 210 mhz output clock frequency 210 mhz output rise time t or 0.8 to 2.0 v, no load 1.5 ns output fall time t of 2.0 to 0.8 v, no load 1.5 ns output clock duty cycle t dc measured at vdd/2 40 50 60 % input to output skew note 1 100 ps maximum absolute jitter short term 45 ps maximum jitter one sigma 15 ps phase noise, relative to carrier, 125 mhz (x5) 100 hz offset -110 dbc/hz 1 khz offset -122 dbc/hz 10 khz -124 dbc/hz 200 khz -117 dbc/hz parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 120 c/w ja 1 m/s air flow 115 c/w ja 3 m/s air flow 105 c/w thermal resistance junction to case jc 58 c/w
l ow p hase n oise , z ero d elay b uffer and m ultiplier mds 670-03 g 5 revision 010306 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ICS670-03 figure 1. skew fr om iclk to clk2 , with change in load capacitance (vdd = 3.3v) adjusting input/output skew the data in figure 1 can be used to adjust indivi dual circuit characteristic s and achieve the minimum possible skew between iclk and clk2. with a 125 mhz output, for example, having a total load capacitance of 15 pf will result in nearly zero skew between iclk and cl k2. note that the load capacitance includes board trace capacitance, inpu t capacitance of the load being driven by the ICS670-03, and any additional capacitors connected to clk2. figure 2. phase noise at 125 mhz out, 25 mhz clock input (vdd = 3.3v) -400 -300 -200 -100 0 100 200 300 25 50 75 100 125 150 clk2 frequency (mhz) skew (ps) skew (ps) 20 pf skew (ps) 10 pf ics670 phase noise -140 -120 -100 -80 -60 -40 -20 0 10.e+0 100.e+0 1.e+3 10.e+3 100.e+3 1.e+6 10.e+6 offset frequency l(f) dbc
l ow p hase n oise , z ero d elay b uffer and m ultiplier mds 670-03 g 6 revision 010306 integrated circuit systems l 525 race street, san jose, ca 95126 l tel (408) 297-1201 l www.icst.com ICS670-03 package outline and package dimensions (16-pin soic, 150 mil. narrow body) package dimensions are kept curr ent with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringem ent of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses ar e implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics670m-03i ics670m-03i tubes 16-pin soic -40 to +85 c ics670m-03it ics670m-03i tape and reel 16-pin soic -40 to +85 c ics670m-03ilf 670m-03ilf tubes 16-pin soic -40 to +85 c ics670m-03ilft 670m-03ilf tape and reel 16-pin soic -40 to +85 c index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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