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1 precision digital power monitor isl28022 the isl28022 is a bi-directional high-side and low-side digital current sense and voltage monito r with serial interface. the device monitors current and voltage and provides the results digitally along with calculated power. the isl28022 provides tight accuracy of less than 0.3% for both voltage and current monitoring over the entire input range. the digital power monitor has configurable faul t thresholds and measurable adc gain ranges. the isl28022 handles common-m ode input voltage ranging from 0v to 60v. the wide range permits the device to handle telecom, automotive and industri al applications with minimal external circuitry. both high and low-side ground sensing applications are easily handled with the flexible architecture. the isl28022 consumes an aver age current of just 700a and is available in the space saving 10 ld msop package. the isl28022 is also offered in a 16 ld qfn package. the part operates over the extended temperature range from -40c to +125c. features ? bus voltage sense range . . . . . . . . . . . . . . . . . . . . . . 0v to 60v ?16-bit ? adc monitors current and voltage ? voltage measuring error . . . . . . . . . . . . . . . . . . . . . . . . . <0.3% ? current measuring error . . . . . . . . . . . . . . . . . . . . . . . . . <0.3% ? handles negative system voltage ?over/undervoltage and current fault monitoring ?i 2 c/smbus interface ?wide v cc range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3v to 5.5v ? esd (hbm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8kv ? supports high speed i 2 c . . . . . . . . . . . . . . . . . . . . . . . 3.4mhz applications ?routers and servers ? dc/dc, ac/dc converters ? battery management/charging ? automotive power ?power distribution ? medical and test equipment i 2 c smbus a1 smbclk/scl smbdat/sda vinp vinm gnd rsh adc 16-bit sw mux to c voltage regulator vout en eclk/int v in = 0v to 60v reg map vcc load vbus a0 v cc figure 1. typical application april 26, 2013 fn8386.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28022 2 fn8386.1 april 26, 2013 table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 smbus support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 broadcast addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 measurement stability vs acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 fast transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 typical applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 point of load power monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power monitor boost regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 floating supply dpm (> 60v or < 0v operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
isl28022 3 fn8386.1 april 26, 2013 block diagram digital control logic i 2 c sm bus a0 16 a1 smbclk smbdat osc vinm vinp vcc gnd adc 16- bit reg map ref clock div sw mux cm = 0 to 60v eclk/int vbus pin configurations isl28022 (10 ld msop) top view isl28022 (16 ld qfn) top view a1 a0 ext_clk/int sda/smbdat scl/smbclk 1 2 3 4 5 10 9 8 7 6 vcc gnd vbus vinm vinp 1 3 4 15 a1 a0 ext_clk/int sda/smbdat nc nc nc vinp 16 14 13 2 12 10 9 11 6 578 vinm vbus gnd vcc scl/smbclk nc nc nc gnd
isl28022 4 fn8386.1 april 26, 2013 pin descriptions msop pin number qfn pin number pin name description 11 a1i 2 c address, bit 1 22 a0i 2 c address, bit 0 3 3 ext_clk/int external adc clock input or cpu interrupt output signal. when the pin is configured as an interrupt, the output is an open drain. 44smbdat/sdai 2 c serial data input/output 55smbclk/scli 2 c clock input 6 9 vcc positive power pin. the positive power supply to the part. 7 10 gnd negative power pin. can be connect ed to ground or a negative voltage. 8 11 vbus vbus power voltage sense. 9 12 vinm current sense minus input. 10 13 vinp current sense plus input. 6 nc no connect. no internal connection. 7 nc no connect. no internal connection. 8 nc no connect. no internal connection. 14 nc no connect. no internal connection. 15 nc no connect. no internal connection. 16 nc no connect. no internal connection. epad gnd negative power pin. can be connect ed to ground or a negative voltage ordering information part number (note 4) part marking package (pb-free) pkg. dwg. # coming soon isl28022fuz (note 1) 8022f 10 ld msop m10.118 coming soon isl28022frz (note 1) 022f 16 ld qfn l16.3x3b isl28022frzr5453 022f 16 ld qfn l16.3x3b isl28022frz-tr5453 (note 2) 022f 16 ld qfn l16.3x3b isl28022frz-t7ar5453 (note 2) 022f 16 ld qfn l16.3x3b ISL28022FUZR5453 8022f 10 ld msop m10.118 isl28022fuz-tr5453 (note 2) 8022f 10 ld msop m10.118 isl28022fuz-t7ar5453 (note 2) 8022f 10 ld msop m10.118 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 4. for moisture sensitivity level (msl), please see device information page for isl28022 . for more information on msl please see tech brief tb363 .
isl28022 5 fn8386.1 april 26, 2013 absolute maximum rating s thermal information vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0v vbus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..63v common mode input voltage (v inp, v inm ) . . . . . . . . . . . . . . . . . . . . . . . 63v differential input voltage (v inp , v inm ) . . . . . . . . . . . . . . . . . . . . . . . . . .63v input voltage (digital pins) . . . . . . . . . . . . . . . . . . . . . . . . .gnd-0.3v to 5.5v output voltage (digital pins) . . . . . . . . . . . . . . . . . . . . gnd-0.3 to vcc+0.3v open drain output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma open drain voltage (interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300v charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0kv latch up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60v @ + 125c thermal resistance (typical) ja (c/w) jc (c/w) 16 ld qfn (notes 5, 6) . . . . . . . . . . . . . . . . 52 6.5 10 ld msop (notes 7, 8) . . . . . . . . . . . . . . . 150 55 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (t jmax ) . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 8. for jc, the ?case temp? location is taken at the package top center. electrical specifications t a = +25c, v cc = 3.3, v inp = v bus = 12v, v sense = v inp -v inm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. parameter description conditions min (note 9) typ max (note 9) unit inputs v sensediff useful full scale current sense differential voltage range (v inp -v inm ) pga gain = /1 0 40 mv pga gain = /2 0 80 mv pga gain = /4 0 160 mv pga gain = /8 0 300 mv v shunt _step lsb step size, shunt voltage 10 v v cmsense current sense common mode (vinp, vinm) 0v bus v v os v sense offset voltage pga gain = /1, /2, /4, /8; adc setting = 1111 10 75 v v ostc v sense offset voltage temperature coefficient 0.15 v/c cmrr v sense v os vs common mode v bus = 0 to 60v; brng = 2, 3 110 130 db psrr v sense v os vs power supply v cc = 3v to 5v 105 db a cs current sense gain error 40 m% a cstc current sense gain error temperature coefficient 1 m%/c i vinact input leakage, vin pins active mode (for both v inp and v inm pins) 20 a i vinact input leakage, vin pins power down mode (for both v inp and v inm pins) 0.1 0.5 a
isl28022 6 fn8386.1 april 26, 2013 v bus useful bus voltage range brng = 0 0 16 v brng = 1 0 32 v brng = 2, 3 0 60 v v bus _step lsb step size, bus voltage brng = 0 4 mv v bus _ vco v bus voltage coefficient 50 ppm/v r vbact input impedance, vbus pin active mode 600 k dc accuracy adc resolution (native) pga gain = /1, v sense = 300mv 16 bits current measurement error t a = +25c 0.2 0.3 % current measurement error over temperature t a = -40c to +85c 0.5% % t a = -40c to +125c 1% % bus voltage measurement error t a = +25c 0.2 0.3 % bus voltage measurement error over temperature t a = -40c to +85c 0.5% % t a = -40c to +125c 1% % adc timing specs t s adc conversion time adc setting = 0000 72 79.2 s adc setting = 0001 132 145.2 s adc setting = 0010 258 283.8 s adc setting = 0011 508 558.8 s adc setting = 1001 1.01 1.11 ms adc setting = 1010 2.01 2.21 ms adc setting = 1011 4.01 4.41 ms adc setting = 1100 8.01 8.81 ms adc setting = 1101 16.01 17.61 ms adc setting = 1110 32.01 35.21 ms adc setting = 1111 64.01 70.41 ms i 2 c interface specifications v il sda and scl input buffer low voltage -0.3 0.3 x vcc v v ih sda and scl input buffer high voltage 0.7 x v cc v cc + 0.3 v hysteresis sda and scl input buffer hysteresis 0.05 x v cc v v ol sda output buffer low voltage, sinking 3ma v cc = 5v, i ol = 3ma 0 0.02 0.4 v c pin sda and scl pin capacitance t a = +25c, f = 1mhz, v cc = 5v, v in = 0v, v out = 0v 10 pf f scl scl frequency 400 khz electrical specifications t a = +25c, v cc = 3.3, v inp = v bus = 12v, v sense = v inp -v inm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. (continued) parameter description conditions min (note 9) typ max (note 9) unit
isl28022 7 fn8386.1 april 26, 2013 t in pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed. 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of v cc , until sda exits the 30% to 70% of v cc window. 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of v cc during a stop condition, to sda crossing 70% of v cc during the following start condition. 1300 ns t low clock low time measured at the 30% of v cc crossing. 1300 ns t high clock high time measured at the 70% of v cc crossing. 600 ns t su:sta start condition setup time scl risi ng edge to sda falling edge. both crossing 70% of v cc . 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of v cc to scl falling edge crossing 70% of v cc . 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of v cc window, to scl rising edge crossing 30% of v cc. 100 ns t hd:dat input data hold time from scl falling edge crossing 30% of v cc to sda entering the 30% to 70% of v cc window. 20 900 ns t su:sto stop condition setup time from scl rising edge crossing 70% of v cc , to sda rising edge crossing 30% of v cc . 600 ns t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of v cc . 600 ns t dh output data hold time from scl falling edge crossing 30% of v cc , until sda enters the 30% to 70% of v cc window. 0ns t r sda and scl rise time from 30% to 70% of v cc 20 + 0.1 x cb 300 ns t f sda and scl fall time from 70% to 30% of v cc 20 + 0.1 x cb 300 ns cb capacitive loading of sda or scl total on-chip and off-chip 75 pf r pu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f . for cb = 400pf, max is about 2k ~2.5k . for cb = 40pf, max is about 15k ~20k 1k electrical specifications t a = +25c, v cc = 3.3, v inp = v bus = 12v, v sense = v inp -v inm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. (continued) parameter description conditions min (note 9) typ max (note 9) unit
isl28022 8 fn8386.1 april 26, 2013 power supply operating supply voltage range 3 5.5 v i ccext power supply current on v cc pin, active mode external power supply mode, v cc = 5v 0.7 1.0 ma i ccpd power supply current on v cc pin, power-down mode external power supply mode, v cc = 5v 515a note: 9. parameters with min and/or ma x limits are 100% tested at +25c, unless otherw ise specified. temperature limits established by characterization and are not production tested. electrical specifications t a = +25c, v cc = 3.3, v inp = v bus = 12v, v sense = v inp -v inm = 32mv, unless otherwise specified. all voltages with respect to gnd pin. (continued) parameter description conditions min (note 9) typ max (note 9) unit typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, s(b)adc =15; unless otherwise specified. figure 2. v shunt v os figure 3. v shunt v os vs temperature figure 4. v shunt measurement error figure 5. v shunt measurement error vs v shunt input 0 5 10 15 20 25 -75 -60 -45 -30 -15 0 15 30 45 60 75 hits v shunt v os (v) -0.0750 -0.0625 -0.0500 -0.0375 -0.0250 -0.0125 0 0.0125 0.0250 0.0375 0.0500 0.0625 0.0750 -50 -25 0 25 50 75 100 125 temperature (c) v os (mv) v cc = 3.3v v cc = 3v v cc = 5v sadc = 15 0 5 10 15 20 25 30 35 40 -0.30 -0.25 -0.20 -0.15 -0.10 -0.0 5 0 0.05 0.10 0.15 0.20 0.25 0.30 hits v shunt measurement error (%) -0.3 -0.2 -0.1 0 0.1 0.2 0.3 -0.30 -0.25 -0.20 -0.15 -0.10 -0. 05 0 0.05 0.10 0.15 0.20 0.25 0.30 v shunt (v) v shunt measurement error (%) v cc = 5.5v v cc = 3.3v v cc = 3v t = +25c v shunt (cmv) = 12v sadc = 15
isl28022 9 fn8386.1 april 26, 2013 figure 6. v shunt gain vs temperature figure 7. v bus measurement error distribution figure 8. v bus measurement error vs v bus (t a = +25c) figure 9. v bus measurement error vs temperature figure 10. cmrr vs temperature figure 11. supply current vs mode vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, s(b)adc =15; unless otherwise specified. (continued) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature (c) gain error (%) v cc = 5.5v v cc = 3.3v v cc = 3v v shunt (diff) = 32mv v shunt (cmv) = 12v sadc = 15 0 10 20 30 40 50 60 70 -0.30 -0.25 -0.20 -0.15 -0.10 -0 .05 0 0.05 0.10 0.15 0.20 0.25 0.30 hits v bus measurement error (%) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 8 16 24 32 40 48 56 64 v bus (v) v bus measurement error (%) v cc = 5.5v v cc = 3.3v v cc = 3v -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -50 -25 0 25 50 75 100 125 temperature (c) v bus measurement error (%) v cc = 5.5v v cc = 3.3v v cc = 3v 120 125 130 135 140 145 150 155 -50 -25 0 25 50 75 100 125 temperature (c) v cc = 3v v cc = 3.3v v cc = 5v v shunt (dcmv) = 0v to 60v sadc = 15 cmrr (db) 300 350 400 450 500 550 600 650 700 750 800 -50 -25 0 25 50 75 100 125 temperature (c) supply current (a) mode = 7 mode = 4
isl28022 10 fn8386.1 april 26, 2013 figure 12. supply current vs mode vs vcc figure 13. supply current vs mode 0 vs temperature figure 14. supply current vs mode 0 vs v cc figure 15. shunt i vin vs temperature (mode 5) figure 16. shunt i vin vs common mode voltage (mode 5) figure 17. shunt i vin vs temperature (mode 0, 4) typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, s(b)adc =15; unless otherwise specified. (continued) 300 350 400 450 500 550 600 650 700 750 800 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) supply current (a) mode = 7 mode = 4 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 temperature (c) supply current (a) 0 2 4 6 8 10 12 14 16 18 20 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) supply current (a) 5 7 9 11 13 15 17 19 -50 -25 0 25 50 75 100 125 temperature (c) i vin (a) 5 6 7 8 9 10 11 12 13 14 15 0 8 16 24 32 40 48 56 64 vcm (v) i vin (a) 0 0.005 0.010 0.015 0.020 -50 -25 0 25 50 75 100 125 temperature (c) i vin (a) mode = 4 mode = 0
isl28022 11 fn8386.1 april 26, 2013 figure 18. shunt i vin vs common mode voltage (mode 0, 4) figure 19. shunt i os vs temperature (mode 5) figure 20. shunt i os vs common mode voltage (mode 5) figure 21. shunt i os vs temperature (mode 0, 4) figure 22. shunt i os vs common mode voltage (mode 0, 4) figure 23. v shunt bandwidth vs sadc mode typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, s(b)adc =15; unless otherwise specified. (continued) 0 0.005 0.010 0.015 0.020 0 8 16 24 32 40 48 56 64 vcm (v) mode = 0 mode = 4 i vin (a) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature (c) i os (a) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 8 16 24 32 40 48 56 64 vcm (v) i os (a) -0.0020 -0.0015 -0.0010 -0.0005 0 0.0005 0.0010 0.0015 0.0020 -50 -25 0 25 50 75 100 125 temperature (c) i os (a) mode = 4 mode = 0 -0.0020 -0.0015 -0.0010 -0.0005 0 0.0005 0.0010 0.0015 0.0020 0 8 16 24 32 40 48 56 64 vcm (v) i os (a) mode = 4 mode = 0 -50 -40 -30 -20 -10 0 10 10 100 1k 10k frequency (hz) gain (db) sadc = 1 sadc = 0 sadc = 2 sadc = 3 v in = 200mv p-p sine wave
isl28022 12 fn8386.1 april 26, 2013 functional description overview the isl28022 is a digital power monitor (dpm) device that is capable of measuring bi-directional currents while monitoring the bus voltage. the dpm requires an external sh unt resistor to enable current measurements. the shunt resistor translates the bus current to a voltage. the dpm measures the voltage across the shunt resistors and reports the measured value out digitally via an i 2 c interface. a register within the dpm is reserved to store the value of the shunt resistor. the stored current sense resistor value allows the dpm to output the curr ent value to an external digital device. the isl28022 measures bus voltage and current sequentially. the device has a power measurement functionality that multiplies current and voltage measured values. the power calculation is stored in a unique register. the power measurement allows the user to monitor power to or from the load in addition to current and voltage. the isl28022 can monitor supplies from 0 to 60v while operating on a chip supply ranging from 3v to 5.5v. the isl28022 adc sample rate can be configured to an internal oscillator (500khz) or a user can provide a synchronized clock. detailed description the isl28022 consists of a tw o channel analog front end multiplexer, a 16-bit sigma delta adc and digital signal processing/serial communication circuitry. the main block within the device is a 3rd order sigma delta adc. the input signal bandwidth is 1khz, wide enough for power monitoring applications. the main block includes an internal 1.2v band gap voltage reference that is used to drive the adc. the analog front end multiplexer selects the input to the adc. the selection to the input of th e adc is either a single ended v bus measurement or a fully diff erential measurement across a shunt resistor. the digital block contains controllable registers, i 2 c serial communication circuitry and a st ate machine. the state machine controls the behavior of the adc acquisition, whether the acquisition is triggered or continuous. a more detailed description of the state machine states can be found in ?mode: operating mode? on page 14. pin descriptions a1 a1 is the address select pin. a1 is one of two i 2 c/smbus slave address select pins that are mult i-logic programmable for a total of 16 different address combinations. there are four selectable levels for a1, vcc, gnd, scl/smbclk, and sda/smbdat. see table 21 for more details in setting the slave address of the device. a0 a0 is the address select pin. a0 is one of two i 2 c/smbus slave address select pins that are mult i-logic programmable for a total of 16 different address combinations. there are four selectable levels for a0, vcc, gnd, scl/smbclk, and sda/smbdat. see table 21 for more details in setting the slave address of the device. ext_clk/int ext_clk/int is the external/interrupt clock pin. ext_clk/int is a bi-directional pin. the pin provides a connection to the system clock. the system clock is connected to the adc. the acquisitions rate of the adc can be varied through the ext_clk/int pin. the pin functionality is set through a control register bit. when the ext_clk/int pin is configured as an output, the pin functionality becomes an interrup t flag to connecting devices. ext_clk/int pin as an output requires a pull up resistor to a power supply, up to 20v, for proper operation.the internal threshold detectors (ov sh /uv sh /ov b /uv b ) signal level relative to the measured value determines the state of the int pin. figure 24. v shunt bandwidth vs external clock frequency typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, s(b)adc =15; unless otherwise specified. (continued) -50 -40 -30 -20 -10 0 10 10 100 1k 10k frequency (hz) sadc = 3 f_extclk = off sadc = 3 f_extclk = 768khz sadc = 3 f_extclk = 384khz v in = 200mv p-p sine wave gain (db)
isl28022 13 fn8386.1 april 26, 2013 sda/smbdat sda/smbdat is the serial data input/output pin. sda/smbdat is a bi-directional pin used to transfer data to and from the device. the pin is an open drain output and may be wired with other open drain/collector outputs. the open drain output requires a pull-up resistor for proper functionality. the pull-up resistor should be connected to vcc of the device. scl/smbclk scl/smbclk is the serial cloc k input pin. the scl/smbclk input is responsible for clocking in all data to and from the device. vcc vcc is the positive supply voltage pin. vcc is an analog power pin. vcc supplies power to the device. gnd gnd is the ground pin. all volt ages internal to the chip are referenced to ground. gnd should be tied to 0v for single supply applications. for dual supply applications, the pin should be connected to the most negative voltage in the application. vbus vbus is the power bus voltage input pin. the pin should be connected to the desired power supply bus to be monitored. vinp vinp is the shunt voltage monitor positive input pin. the pin connects to the most positive voltage of the current shunt resistor. vinm vinm is the shunt voltage monitor negative input pin. the pin connects to the most negative voltage of the current shunt resistor. register descriptions table 1 is the register map for the device. the table describes the function of each register and it s respective valu e. the addresses are sequential and the register si ze is 16 bits (2 bytes) per address. configuration register the configuration register (table 2) controls the functionality of the chip. adc measurable range, converter acquisition times, converter resolution and state machine modes are configurable bits within this register. rst: reset bit configuring the reset bit (bit15) to a 1 generates a system reset that initializes all registers to th eir default values and performs a system calibration. brng: bus voltage range bits 13 and 14 of the configuration register sets the bus measurable voltage range. table 3 shows the brng bit configurations versus the allowable full scale measurement range. the shaded row is the power-up default. table 1. isl28022 register descriptions register address (hex) register name function power-on reset value (hex) access 00 configuration power on reset, bus and shunt ranges, adc acquisition times, mode configuration 799f r/w 01 shunt voltage shunt voltage measurement value 0000 r 02 bus voltage bus voltage measurement value 0000 r 03 power power measurement value 0000 r 04 current current measurement value 0000 r 05 calibration register register used to enable current and power measurements. 0000 r/w 06 shunt voltage threshold min/max shunt thresholds 7f81 r/w 07 bus voltage threshold min/max vbus thresholds ff00 r/w 08 dcs interrupt status threshold interrupts 0000 r/w 09 aux control register register to control the interrupts and external clock functionality 0000 r/w table 2. configuration register bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name rst brng1 brng0 pg1 pg0 badc3 badc2 badc1 badc0 sadc3 sadc2 sadc1 sadc0 mode2 mode1 mode0
isl28022 14 fn8386.1 april 26, 2013 pg: pga (shunt voltage only) bits 11 and 12 of the configurat ion register determines the shunt voltage measurement range. table 4 shows the pga bit configurations versus the allo wable full scale measurement range. the shaded row is the power up default. badc: bus adc resolution/averaging bits [10:7] of the configuration register sets the adc resolution/ averaging when the adc is configured in the v bus mode. the adc can be configured versus bit accuracy. the bit accuracy selections range from 12 to 15-bits. the adc is configurable versus the number of averages. the selection ranges from 2 to 128 samples. table 5 shows the breakdown of each badc setting. the shaded row is the default setting upon power up. sadc: shunt adc resolution/averaging bits [10:7] of the configuration register sets the adc resolution/ averaging when the adc is configured in the v shunt mode. the adc can be configured versus bit accuracy. the bit accuracy selections range from 12 to 15-bits. the adc is configurable versus number of averages. the selection ranges from 2 to 128 samples. table 5 shows the brea k down of each sadc setting. the shaded row is the default setting upon power-up. mode: operating mode bits [2:0] of the configuration register controls the state machine within the chip. the state machin e globally controls the overall functionality of the chip. table 6 shows the various states the chip can be configured to, as well as the mode bit definitions to achieve a desired state. the shaded row is the default setting upon power-up. table 3. brng bit settings brng1 brng0 usable full scale range (v) 00 16 01 32 10 60 1 1 60 table 4. pga bit settings pg1 pg0 gain range (mv) 0 0 1 40 0 1 2 80 1 0 4 160 1 1 8 300 table 5. adc settings, applies to both sadc and badc control adc3 adc2 adc1 adc0 mode/samples conversion time 0 x 0 0 12-bit 72s 0 x 0 1 13-bit 132s 0 x 1 0 14-bit 258s 0 x 1 1 15-bit 508s 1 0 0 0 15-bit 508s 100121.01ms 101042.01ms 101184.01ms 1100168.01ms 11013216.01ms 11106432.01ms 111112864.01ms
isl28022 15 fn8386.1 april 26, 2013 shunt voltage register 01h (read-only) the shunt voltage register reports the measured value across the shunt pins (vinp and vinm) into the register. the shunt register lsb is independent of pga range settings. the pga setting for the shunt register ma sks the unused most significant bit with a sign bit. for lower range of pga settings, multiple sign bits are returned by the dpm. only one sign bit should be used to calculate the measured value. tables 7 through 10 show the weights of each bit for various pga ranges. the tables should be used to calculate the measured value across the shunt pins from the binary to decimal domains. to calculate the measured decimal value across the shunt, first read the shunt voltage register. a ssume the pga setting is set to the 80mv range. for this example, the reading output by the chip is 1111 1010 0000 0101. the 80mv range has three sign bits. only one sign bit needs to be used to calculate the measured decimal value. bits 14 and 15 are omitted from the calculation. this leaves a binary reading of 11 1010 0000 0101. next, multiply each bit by its respective weight. bit0 value would be multiplied by bit0 weight (1), bit1 value * bit1 weight (2), etc.... add all the multiplied values to equate to a single number. for the binary reading 11 1010 0000 0101 this equates to -1531. the lsb for a shunt register is 10v. multiplying the decimal value by the lsb weight yields the measured voltage across the shunt. a 1111 1010 0000 0101 reading equals -15.31mv measured across the shunt pins. table 6. operating mode settings mode2 mode1 mode0 mode 0 0 0 power-down 0 0 1 shunt voltage, triggered 010bus voltage, triggered 011shunt and bus, triggered 1 0 0 adc off (disabled) 1 0 1 shunt voltage, continuous 1 1 0 bus voltage, continuous 1 1 1 shunt and bus, continuous table 7. shunt voltage register, pg gain = /8 (r ange = 11), full scale = 300mv, 15 bits wide bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8421 table 8. shunt voltage register, pg gain = /4 (r ange = 10), full scale = 160mv, 14 bits wide bit d15 d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign sign bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -1638481924096204810245122561286432168421 table 9. shunt voltage register, pg gain = /2 (r ange = 01), full scale = 80mv, 13 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign sign sign bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 10. shunt voltage register, pg gain = /1 (r ange = 00), full scale = 40mv, 12 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign sign sign sign bit11 bit10 bit9 bi t8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 weight -4096 2048 1024 512 256 128 64 32 16 8 4 2 1
isl28022 16 fn8386.1 april 26, 2013 . bus voltage register 02h (read-only) the bus voltage register is where the dpm reports the measured value of the v bus . there are three scale ranges possible depending on the brng setting co ntrolled from the configuration register(00h). tables 11 through 13 are the weight bits for each brng setting. the binary value recorded in the bus voltage register is translated to a decimal value in the same way as the shunt voltage register is converted to a decimal value. equation 1 is the mathematical equation for converting the binary v bus value to a decimal value. n is the bit number. the lsb value for the v bus measurement equals 4mv across all bus range (brng) settings. cnvr: conversion ready (bit 1) the conversion ready bit indicates when the adc has finished a conversion and transferred the reading(s) to the appropriate register(s). the cnvr is only operable when the dpm is set to one of three trigger modes. the cnvr is at a high state when the conversion is in progress. the cnvr transitions and remains at a low state when the conversion is complete. the cnvr bit is initialized or re-initialized in the following ways; 1. writing to the configuration register. 2. reading from power register ovf: math overflow flag (bit 0) the math overflow flag (ovf) is a bit that is set to indicate the current or power data being read from the dpm is over ranged and meaningless. calibration register 05h (read/write) to accurately read the current and power measurements from the chip, the calibration regi ster needs to be programmed. the calibration register value is calculated as follows: 1. calculate the full scale current range that is desired. this is calculated using equation 2. r shunt is the value of the shunt resistor. vshunt is the full scale setting that is desired. in most cases, it is the pga full scal e range (300mv, 160mv, 80mv and 40mv) that the dpm is programmed to. 2. from the current full scale range, the current lsb is calculated using equation 3. cu rrent full scale is the outcome from equation 2. adc res is the resolution of shunt voltage reading. the value is determined by the sadc setting in configuration register. sadc setting equal to 3 and greater will have a 15-bit resolution. the adc res value equals 2 15 or 32768. table 11. bus voltage register, brng = 10 or 11, full scale = 60v, 14 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cnvr ovf weight 8192 4096 2048 1024 512 256 128 64 32 16 8421 table 12. bus voltage register, brng = 01, full scale = 32v, 13 bits wide bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cnvr ovf weight 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 13. bus voltage register, brng = 00, full scale = 16v, 12 bits wide bit d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 cnvr ovf weight 2048 1024 512 256 128 64 32 16 8 4 2 1 table 14. calibration register, 05h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name fs15 fs14 fs13 fs12 fs11 fs10 fs9 fs8 fs7 fs6 fs5 fs4 fs3 fs2 fs1 fs0 v bus 0 15 n bit n bit_weight n ? () = ? ? ? ? ? ? ? ? vbus lsb ? (eq. 1) (eq. 2) current fs vshunt fs r shunt (eq. 3) current lsb current fs adc res
isl28022 17 fn8386.1 april 26, 2013 3. from equation 3, the calibration resister value is calculated using equation 4. the resolution of the math that is processed internally in the dpm is 4096 or 12 bits of resolution. the vshunt lsb is set to 10v. equation 4 yields a 16-bit binary number that can be written to the calibration register. the calibration register format is represented in table 14. current register 04h (read-only) once the calibration register ( 05h) is programmed, the output current is calculated using equation 5. bit is the returned value of each bit from the current register either 1 or a 0. the weight of each bit is represented in table 15. n is the bit number. the current lsb is the value calculated from equation 3. power register 03h (read-only) the power register only has meaning if the calibration register (05h) is programmed. the units for the power register are in watts. the power is calculated using equation 6. bit is the returned value of each bit from the power register either 1 or a 0. the weight of each bit is represented in table 16. n is the bit number. the power lsb is calculated from equation 7. if v bus range, brng, is set to 60v, the power equation in equation 6 is multiplied by 2. threshold registers the shunt voltage or v bus threshold registers are used to set the min/max threshold limits that will be tested versus v shunt or v bus readings. measurement readin gs exceeding the respective vshunt or v bus limits, either above or below, will set a register flag and perhaps an external interrupt depending on the configuration of the interrupt enable bit (intren) in register 09h. the testing of the adc reading versus the respective threshold limits occurs once per adc conversion. shunt voltage threshold register 06h (read/write) the v shunt minimum and maximum threshold limits are set using one register. the shunt value readings are either positive or negative. d15 and d7 bits of table 17 are given to represent the sign of the limit. smx bits repr esent the upper limit threshold. smn represents the lower threshold limit. equation 8 is the calculation used to convert the v shunt threshold binary value to decimal. bit is the value of each bit set in the shunt threshold register. the value is either 1 or a 0. the weight of each bit is represented in table 17. n is the bit number. the shunt voltage threshold lsb is 2.56mv. (eq. 4) calreg val integer math res vshunt lsb ? current lsb r shunt ? () ? ? ? ? ? ? calreg val integer 0.04096 current lsb r shunt ? () ? ? ? ? ? ? current 0 15 n bit n bit_weight n ? () = ? ? ? ? ? ? ? ? current lsb ? (eq. 5) (eq. 6) power 0 15 n bit n bit_weight n ? () = ? ? ? ? ? ? ? ? power lsb ? 5000 ? ? (eq. 7) table 15. current register, 04h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 namebit 15bit14bit13bit12bit11bit10bit9bit8bit7bit6bit5bit4bit3bit2bit1bit0 weight -32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 16. power register, 03h bit d15 d14 d13 d12 d11 d10 d9d8d7d6d5d4d3d2d1d0 name pd15 pd14 pd13 pd12 pd11 pd10 pd 9pd8pd7pd6pd5pd4pd3pd2pd1pd0 weight 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 table 17. shunt voltage threshold register, 06h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name sign smx6 smx5 smx4 smx3 smx2 smx1 sm x0 sign smn6 smn5 smn4 smn3 smn2 smn1 smn0 weight -128 64 32 16 8 4 2 1 -128 64 32 16 8 4 2 1 vs thresh 0 7 n bit n bit_weight n ? () = ? ? ? ? ? ? ? ? vsthresh lsb ? (eq. 8)
isl28022 18 fn8386.1 april 26, 2013 bus voltage threshold register 07h (read/write) the v bus minimum and maximum threshold limits are set using one register. the v bus value readings range from 0 to 60v. table 18 shows the register configuration and bit weights for the v bus threshold register. bmx bits represent the upper limit threshold. bmn represents the lo wer threshold limit. equation 9 is the calculation used to convert the v bus threshold binary value to decimal. bit is the value of each bit set in the v bus threshold register. the value is either 1 or a 0. the weight of each bit is represented in table 18. n is the bit number. the v bus voltage threshold lsb is 256mv. interrupt status register 08h (read/write) the interrupt status register consis ts of a series of bit flags that indicate if an adc reading has ex ceeded the readings respective limit. a 1 or high reading from a warning bit indicates the reading has exceeded the limit. to clear a warning, write a 1 or high to the set warning bit. table 19 shows the definition of the interrupt status register. bmnw is bus voltage minimum warning. a 1 reading for this bit indicates the bus reading is below the bus voltage minimum threshold limit. bmxw is bus voltage maximum warning. a 1 reading for this bit indicates the bus reading is above the bus voltage maximum threshold limit. smnw is shunt voltage minimum warning. a 1 reading for this bit indicates the shunt reading is below the shunt voltage minimum threshold limit. smxw is shunt voltage maximum warning. a 1 reading for this bit indicates the shunt reading is above the shunt voltage maximum threshold limit. aux control register 09h (read/write) the aux control register controls the functionality of the extclk/int pin of the isl28022. table 20 shows the definition of the register. forceintr is the force interrupt bit. programming a 1 to the bit will force a 0 or a low at the extclk/int pin. intren is the interrupt enable bit. programming a 1 to the bit will allow for a threshold measur ement violation to set the state of the extclk/int pin. with the intren set, any flag set from the interrupt status register will chan ge the state of the extclk/int pin from 1 to a 0. exclken is the external clock enable bit. setting the bit enables the external clock. this also ch anges the extclk/int pin from an output to an input. the internal oscillator will shut down when the bit is enabled. extclkdiv are the external clock divider bits. the bits control an internal clock divider that are useful for fast system clocks. the internal clock frequency from pin to chip is represented in equation 10. f extclk is the frequency of the signal driven to the extclk/int pin. extclkdiv is the decimal value of the clock divide bits. table 18. bus voltage threshold register, 07h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name bmx7 bmx6 bmx5 bmx4 bmx3 bmx2 bmx1 bmx0 bmn7 bmn6 bmn5 bmn4 bmn3 bmn2 bmn1 bmn0 weight 128 64 32 16 8 4 2 1 128 64 32 16 8 4 2 1 (eq. 9) vb thresh 0 7 n bit n bit_weight n ? () = ? ? ? ? ? ? ? ? vbthresh lsb ? table 19. interrupt status register, 08h bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name na na na na na na na na na na na na smxw smnw bmxw bmnw weight0000000000000000 table 20. aux control register, 09h bitd15d14d13d12d11d10d9 d8 d7 d6 d5d4d3d2d1d0 name na na na na na na na forceintr intren extclken extclkdiv[5:0] weight0000000 0 0 0 000000 freq internal f extclk extclkdiv 1 + ()2 ?
isl28022 19 fn8386.1 april 26, 2013 i 2 c serial interface the isl28022 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl28022 operates as a slave device in all applications. the isl28022 uses two bytes to tr ansfer all reads and writes. all communication over the i 2 c interface is conducted by sending the msbyte of each byte of data first, followed by the lsbyte. protocol conventions for normal operation, data states on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 25). on power-up of the isl28022, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the isl28022 continuously monitors the sda and scl lines for the start condition and does not resp ond to any command until this condition is met (see figure 25). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 25). a stop condition at the end of a read operation or at the end of a write operation to memory only places the device in its standby mode. figure 25. valid data changes, start and stop conditions figure 26. acknowledge response from receiver figure 27. byte write sequence (s lave address indicated by nnnn) sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high high impedance s t a r t identification byte data byte a c k signals from the master signals from the isl28022 a c k 10 0 0n write signal at sda 0000 nnn address byte s t o p data byte a c k a c k
isl28022 20 fn8386.1 april 26, 2013 smbus support the isl28022 supports smbus protocol, which is a subset of the global i 2 c protocol. smbclk and smbdat have the same pin functionality as the scl and sda pins, respectively. the smbus operates at 100khz. device addressing following a start condition, the master must output a slave address byte. the 7 msb?s are the device identifiers. the a0 and a1 pins control the bus address. these bits are shown in table 21, there are 16 possible combinations depend ing on the a0/a1 connections. table 21. i 2 c slave addresses a1 a0 slave address gnd gnd 1000 000 gnd vcc 1000 001 gnd sda 1000 010 gnd scl 1000 011 vcc gnd 1000 100 vcc vcc 1000 101 vcc sda 1000 110 vcc scl 1000 111 sda gnd 1001 000 sda vcc 1001 001 sda sda 1001 010 sda scl 1001 011 scl gnd 1001 100 scl vcc 1001 101 scl sda 1001 110 scl scl 1001 111 broadcast address 0111 111
isl28022 21 fn8386.1 april 26, 2013 the last bit of the slave address byte defines a read or write operation to be performed. when this r/w bit is a ?1?, a read operation is selected. a ?0? sele cts a write operation (refer to figure 27). after loading the entire slave address byte from the sda bus, the isl28022 compares the loaded value to the internal slave address. upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the one word address byte, as shown in figure 28. in a random read operation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the registers, the slave byte must be ?100nnnnx? in both places. write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, two data bytes, and a stop condition. the first data byte contains the lsb of the data, the second contains the msb. after each of the four bytes, the isl28022 responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a thr ee byte instruction, followed by two data bytes (see figure 28). th e master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start, and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl28022 resp onds with an ack. then the isl28022 transmits two data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of the first byte. the master termin ates the read operation (issuing no ack then a stop condition) follo wing the last bit of the second data byte (see figure 28). the data bytes are from the memory location indicated by an internal pointer. this pointer?s in itial value is determined by the address byte in the read operatio n instruction, and increments by one during transmission of each pair of data bytes. the highest valid memory location is 09h, re ads of addresses higher than that will not return useful data. broadcast addressing the dpm has a feature that allows the user to configure the settings of all dpm chips at once. for example, a system has 16 dpm chips connected to an i 2 c bus. a user can set the range or initiate a data acquisition in one i 2 c data transaction by using a slave address of 0111 111. the broadcast feature saves time in configuring the dpm as well as measuring signal parameters in time synchronization. the broadc ast should not be used for dpm read backs. this will cause all devices connected to the i 2 c bus to talk to the master simultaneously. i 2 c clock speed the isl28022 supports high-speed digital transactions up to 3.4mbs. to access the high speed i 2 c feature, a master byte code of 0000 1nnn is attached to the beginning of a standard frequency read/ write i 2 c protocol. the n in the master byte code can either equal a 0 or a 1. the master byte code should be clocked into the chip at freque ncies equal or less than 400khz. the master code command configures the internal filters of the isl28022 to permit data bit fr equencies greater than 400khz. once the master code has been clocked into the device, the protocol for a standard read/ write transaction is followed. the frequency at which the standard protocol is clocked in at can be as great as 3.4mhz. a stop bit at the end of a standard protocol will terminate the high speed transaction mode. appending another standard protoc ol serial transaction to the data string without a stop bit, will resume the high speed digital transaction mode. figure 30 illustrates the da ta sequence for the high speed mode. figure 28. read sequence (slave address shown as nnnn) signals from the master signals from the slave signal at sda s t a r t identification byte with r/w = 0 address byte a c k a c k 0 s t o p 1 identification byte with r/w = 1 a c k s t a r t second read data byte first read data byte a c k 10 0 nnnn 10 0 nn nn figure 29. slave address, word address, and data bytes d15 d14 d13 d10 d12 d11 d9 d8 a0 a7 a2 a4 a3 a1 data byte 1 a6 a5 1 00 n n n r/w n word address d7 d6 d5 d2 d4 d3 d1 d0 slave address byte data byte 2
isl28022 22 fn8386.1 april 26, 2013 signal integrity the purity of the signal being measured by the isl28022 is not always ideal. environmental noise or noise generated from a regulator can degrade the measurement accuracy. the isl28022 maintains a high cmrr ratio from dc to approximately 10khz, as shown in figure 31. the cmrr vs frequency graph best represents the response of the isl28022 when an aberrant sign al is applied to the circuit. the normal state of the measured si gnal is dc and is the state at which the isl28022 internal calibration is performed. the graph was generated by shor ting the isl28022 input without any filtering and applying a 0 to 10v triangle wave to the shunt inputs, vinp and vinm. the voltage shunt measurement was recorded for each frequency applied to shunt input. the cmrr of can be improved by designing an filter stage for the of the isl28022. the purpose of the filter stage is to attenuate the amplitude of the unwanted signal to the noise level of the isl28022. figure 32 is a simple filter example to attenuate unwanted signals. the filter circuit in figure 32 attenuates unwanted signals. csh and rsh is single pole rc filter that differentially attenuates unwanted signals to the isl28022. most power monitoring applications require a shunt resistor to be low in value to measure large currents. for small shunt resistors, a large value capacitor is required to attenuate low frequency signals. most large value capacitors are not offered in space saving packages. the corner frequency of the differential filter, csh and rsh, should be designed for higher value frequency filtering. r1 and c1 for both inputs are the single ended filter to the isl28022. the value of the series resistor to the isl28022 can be a larger value than the shunt resistor, rsh. a larger series resistor to the input allows for a lower cutoff frequency filter design to the isl28022. the isl28022 can source up to 20a of transient current in the measur ement mode. the transient or switching offset current can be a large as 10a. the switching offset current combined with the series resistance, r1, creates an error offset voltage. a balance of the value of r1 and the shunt measurement error should be achieved for this filter design. the common mode voltage of the shunt input stage ranges from 0v to 60v. the capacitor voltage rating for c1 and csh should comply with the nominal voltage being applied to the input. measurement stability vs acquisition time the badc and sadc bits within the configuration register configures the conversion time and accuracy for the bus and shunt inputs respectively. the faster the conversion time the less accuracy and more noise introd uced into the measurement. figure 33 is a graph that illustrates the shunt measurement variability versus a set sadc mode. the standard deviation of 2048 shunt vos measurements is used to quantify the measurement variability of each mode. figure 30. byte transaction sequence fo r initiating data rates above 400kbs figure 31. cmrr vs frequency 80 85 90 95 100 105 110 115 120 125 130 10 100 1k 10k 100k 1m frequency (hz) cmrr (db) figure 32. simplified filter design to improve noise performance to the isl28022 load rsh from source isl28022 r1 r1 csh c1 c1
isl28022 23 fn8386.1 april 26, 2013 fast transients an small isolation resistor plac ed between isl28022 inputs and the source is recommended. in ho t swap or other fast transient events, the amplitude of a signal can exceed the recommended operating voltage of the part due to the line inductance. the isolation resistor creates a low pass filter between the device and the source. the value of the isolation resistor should not be too large. a large value isolation resistor can effect the measurement accuracy. the offset current for shunt input can be as large as 10a. the value of the isolation resistor combined with the offset current creates an error offset voltage at the shunt input. the input of the bus channel is connected to the top of a precision resistor divider. th e accuracy of the resistor divider determines the gain error of the bus channel. the input resistance of the bus channel is 600k . placing an isolation resistor of the 10 will change the gain error of the bus channel by 0.0016%. external clock an externally controlled clock allows measurements to be synchronized to an event that is time dependent. the event could be application generated, such as timing a current measurement to a charging capacitor in a switch regulator application or the event could be environmental. a voltage or current measurement may be suspectable to crosstal k from a controlled source. instead of filtering the en vironmental noise from the measurement, another approach would be to synchronize the measurement to the source. the variability and accuracy of the measurement will improve. the isl28022 has the functionality to allow for synchronization to an external clock. the speed of the external clock combined with the choice of the internal chip frequency division value determines the acquisition times of the adc. the internal system clock frequency is 500khz. the internal system clock is also the adc sampling clock. the acquisition times scale linearly from 500khz. for example, an external clock frequency of 1.0mhz with a frequency divide setting of 2 results in acquisition times that equals the internal oscillator frequency when enabled. the internal clock frequency of the isl28022 should not exceed 500khz. the adc modulator is optimized for frequencies of 500khz and below. operating inte rnal clock frequencies above 500khz result in measurement accuracy errors due to the modulator not having en ough time to settle. suppose an external clock frequenc y of 1.0mhz is applied with a divide by 8 internal frequency setting, the system clock speed is 125khz or 4x slower than internal system clock. the acquisition times for this example will increa se by 4. for a s(b)adc setting of 3, the isl28022 will have an acquisition time of 2.032ms instead of 508s. the eclk/int pin connects to a buffer that drives a d-flip flop. figure 35 illustrates a simple schematic of the eclk/int pin internal connection. the series of divide by 2 configured d-flip flops are control by the clkdiv bits from the aux control register. the buffer is a schmitt triggered buffer. the bandwidth of the buffer is 4mhz. figure 36 shows the bandwidth of the eclk/int pin. figure 33. measurement stability vs sadc mode figure 34. simplified sc hematic of the isl28022 synchronized to a pwm source 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sadc mode v shunt v os sigma (mv) i 2 c smbus a1 scl sda vinp vinm gnd rsh adc 16-bit sw mux eclk reg map vcc vbus a0 isl28022 dpm load to mcu function generator 3.3v + - vth figure 35. simplified internal block connection of the eclk/int pin figure 36. external clock bandwidth vs measurement accurancy d q d q d q eclk/int -1 0 1 2 3 4 5 1 10 external clock frequency (mhz) v shunt measurement error normalized (%) clkdiv = 5 ( 12) sadc = 3
isl28022 24 fn8386.1 april 26, 2013 the v shunt measurement error degrades at eclk frequencies above 4mhz. it is recommended that the eclk does not exceed 4mhz. at eclk frequencies below 2.5mhz or internal clock frequencies of 208khz, the clock frequency to modulator is too slow allowing the charged capacitors to discharge due to parasitic leakages. the capaci tor discharge results in a measurement error. over-ranging it is not recommended to operate the isl28022 outside the set voltage range. in the event of measuring a shunt voltage beyond the maximum set range (300mv) and lower than the clamp voltage of the protection diode (1v), the measured output reading may be within the accepted range but will be incorrect. typical applications point of load power monitor complex systems are subdivided in to smaller simplified specific tasks. the circuit illustrated in figure 37 is a solution that can be used to monitor a load?s performance. the vreg is a voltage regulator that regulates to a point of load (pol) voltage. 5v, 3.3v, 2.5v and 1.8v are examples of pol voltages. the main bus voltage applied to the voltage regulator regulates the voltage to the load at the vinm, vbus and sense node for the configuration shown above. the pl acement of the shunt resistor in the circuit allows current to be monitored while regulating the voltage to the load. the maximu m shunt voltage the isl28022 is able to measure is 300mv. the shunt resistor value is determined by the equation 11. current fs is the maximum current to be measured through the load. this is chosen by the user. the isl28022 has over/undervoltage (ov/uv) sensing circuitry for the bus and shunt inputs. the levels of the error detection circuitry are controlled digitally via a i 2 c/smbus communication protocol. the status of each inputs? error detection can be read digitally via a register. the isl2 8022 allows for the summation of error detection bits to be routed to an interrupt pin. for the point of load monitoring circuit shown in figure 37, the interrupt pin is connected to the enable pin of the regulator. in a fault condition, the isl28022 will trig ger an interrupt causing the voltage regulator to shutdown. in the case of when a fault always exist, the isl28022 interrupt pin outp ut state can be digitally programmed. the isl28022 calculates the power and current through hardware and stores the results in an internal register. the v bus connected directly to the load enables a measurement system that monitors power to the load. power monitor boost regulation the power monitor boost regular application is an example of the isl28022 used as a digital he lper, figure 38. with minimal circuitry, the isl28022 enables smart designs that digitally monitor the electrical parameters to a load. alternative designs require a current amplifier paired with an adc. the adc chosen is often not compliant to comm on communication standards, such as i 2 c. the isl28022 solves this problem and allows for 16 devices on a single i 2 c bus. the isl97516 chip is a high efficiency step-up voltage regulator. the max current the regulator can deliver is 2.0a. for this particular application, the isl97516 is configured to step up the voltage at the vdd pin to 12v. the voltage at vdd can range from 2.3v to 5v for normal 12v regulated operation. a usb power pin could be used to drive the isl97516. figure 37. point of load monitoring design idea i 2 c smbus a1 scl sda vinp vinm gnd rsh adc 16-bit sw mux vout en eclk/int vrail = 0 to 60v reg map vcc vbus a0 isl28022 dpm sense vout voltage regulator load to c (eq. 11) r shunt rsh 0.30 current fs figure 38. power monitor boost regulator design idea rsh vout =12v vrail = 2.3v to 5v load ref gen osc cntrl en pwm cntrl fet drive isl97516 comp vdd fb gnd lx ss en fsel from eclk/int i 2 c smbus a1 scl sda vinp vinm gnd adc 16-bit eclk/int reg map vcc vbus a0 isl28022 dpm vout to c sw mux to en
isl28022 25 fn8386.1 april 26, 2013 the regulation node of the circui t, shown in figure 38 is at v out . the isl97516 has feedback circuitry that removes the current sense resistor, rsh, from impacting the regulation voltage. the current sense resistor is calculated using equation 11. equation 11 shows the formula used to calculate r shunt . the isl28022 interrupt pin is conne cted to the enable pin of the regulator. the isl28022 has ov/uv alerts for both the bus and shunt channels. a fault conditio n from either channel powers down the voltage regulator. floating supply dpm (> 60v or < 0v operation) the isl28022 is operational when the potential of the measured circuitry is greater than the potential at the ground pin. in most application the ground pin potent ial equals 0v. a zero potential ground reference limits the operating range of the isl28022 to 0v to 60v. this application illustrates the connectivity of the dpm to measure and operate at potentials greater than 60v or less than 0v. assume an application that meas ures a -48v supply. the ground reference voltage of the system, v_low, equals -48v. v_high equals 0v for the example. the power supply voltage to the system is -48v. the load supply voltage is set by the voltage regulator, vload reg. the regulator can be either a shunt or a linear regulator. the voltage levels for i 2 c communication lines are determined by v_low and the isl28022 shunt regulator. a low voltage equals the v_low potential. a high level equals the summation of v_low and the shunt regulator voltage. for a -48v system with a 3.3v shunt regulator, a low voltage equals -48v and a high voltage level equals -44.7v. the voltage from the i 2 c communication pins can not be directly connected to a ground referenced micro-controller. the optocouplers are used to translate the voltage level from the -48v referenced system to the ground referenced micro-controller system. the isl28022 measures voltage between two nodes. for the shunt input, the isl28022 measures the voltage between vinp and vinm nodes. for the bus input, the isl28022 measures the difference between v bus and gnd nodes. the v bus voltage for a floating system is calculate using equation 12. v low is the ground reference voltage of the system. in this instance, the value is -48v. vbus lsb is the step size of the v bus measurement. this equals 4mv. vbus reg is the integer value of the v bus measurement reported by the isl28022. figure 39. floating supply design idea i 2 c smbus a1 scl sda vinp vinm gnd rsh adc 16-bit sw mux vout eclk/int reg map vcc vbus a0 isl28022 dpm vout 3v ? 5.5v shunt reg optocouplers v_low v load reg mcu v_high load optocoupler gpio (eq. 12) v bus v low vbus lsb vbus reg ? ( ) +
isl28022 26 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8386.1 april 26, 2013 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change april 26, 2013 fn8386.1 added r-spec parts to ordering information and updated verbiage in about intersil. april 16, 2013 fn8386.0 initial release
isl28022 27 fn8386.1 april 26, 2013 package outline drawing m10.118 10 lead mini small ou tline plastic package rev 1, 4/12 detail "x" side view 2 typical recommended land pattern top view pin# 1 id 0.18 - 0.27 detail "x" 0.10 0.05 (4.40) (3.00) (5.80) h c 1.10 max 0.09 - 0.20 33 gauge plane 0.25 0.95 ref 0.55 0.15 b 0.08 c a-b d 3.00.05 12 10 0.85010 seating plane a 0.50 bsc 3.00.05 4.90.15 (0.29) (1.40) (0.50) d 5 5 side view 1 dimensioning and tolerancing conform to jedec mo-187-ba plastic interlead protrusions of 0.15mm max per side are not dimensions in ( ) are for reference only. dimensions are measured at datum plane "h". plastic or metal protrusions of 0.15mm max per side are not dimensions are in millimeters. 3. 4. 5. 6. notes: 1. 2. and amsey14.5m-1994. included. included. 0.10 c m
isl28022 28 fn8386.1 april 26, 2013 package outline drawing l16.3x3b 16 lead quad flat no-lead plastic package rev 1, 4/07 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view bottom view side view 9 ( 2. 80 typ ) ( 1. 70 ) (4x) 0.15 ( 12x 0 . 5 ) ( 16x 0 . 60) ( 16x 0 . 23 ) 0 . 90 0.1 index area pin 1 6 a 3.00 b 3.00 12 4 4 5 8 16x 0.40 0.10 5 0 . 2 ref c 0 . 00 min. 0 . 05 max. b c ma 0.10 c - 0.05 base plane 0.10 c see detail "x" c 0.08 seating plane + 0.07 16x 0.23 16 13 12x 1.5 4x 0.50 1 6 pin #1 index area 1 .70 + 0.10 - 0.15

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